drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 364                                                 int refclk)
 365 {
 366         struct drm_device *dev = crtc->dev;
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         const intel_limit_t *limit;
 369
 370         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 371                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 372                     LVDS_CLKB_POWER_UP) {
 373                         /* LVDS dual channel */
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_dual_lvds;
 378                 } else {
 379                         if (refclk == 100000)
 380                                 limit = &intel_limits_ironlake_single_lvds_100m;
 381                         else
 382                                 limit = &intel_limits_ironlake_single_lvds;
 383                 }
 384         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 385                         HAS_eDP)
 386                 limit = &intel_limits_ironlake_display_port;
 387         else
 388                 limit = &intel_limits_ironlake_dac;
 389
 390         return limit;
 391 }
 392
 393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 394 {
 395         struct drm_device *dev = crtc->dev;
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         const intel_limit_t *limit;
 398
 399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 400                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 401                     LVDS_CLKB_POWER_UP)
 402                         /* LVDS with dual channel */
 403                         limit = &intel_limits_g4x_dual_channel_lvds;
 404                 else
 405                         /* LVDS with dual channel */
 406                         limit = &intel_limits_g4x_single_channel_lvds;
 407         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 408                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 409                 limit = &intel_limits_g4x_hdmi;
 410         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 411                 limit = &intel_limits_g4x_sdvo;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 413                 limit = &intel_limits_g4x_display_port;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (!IS_GEN2(dev)) {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i9xx_lvds;
 437                 else
 438                         limit = &intel_limits_i9xx_sdvo;
 439         } else {
 440                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 441                         limit = &intel_limits_i8xx_lvds;
 442                 else
 443                         limit = &intel_limits_i8xx_dvo;
 444         }
 445         return limit;
 446 }
 447
 448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 449 static void pineview_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = clock->m2 + 2;
 452         clock->p = clock->p1 * clock->p2;
 453         clock->vco = refclk * clock->m / clock->n;
 454         clock->dot = clock->vco / clock->p;
 455 }
 456
 457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 458 {
 459         if (IS_PINEVIEW(dev)) {
 460                 pineview_clock(refclk, clock);
 461                 return;
 462         }
 463         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 464         clock->p = clock->p1 * clock->p2;
 465         clock->vco = refclk * clock->m / (clock->n + 2);
 466         clock->dot = clock->vco / clock->p;
 467 }
 468
 469 /**
 470  * Returns whether any output on the specified pipe is of the specified type
 471  */
 472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 473 {
 474         struct drm_device *dev = crtc->dev;
 475         struct drm_mode_config *mode_config = &dev->mode_config;
 476         struct intel_encoder *encoder;
 477
 478         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 479                 if (encoder->base.crtc == crtc && encoder->type == type)
 480                         return true;
 481
 482         return false;
 483 }
 484
 485 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 486 /**
 487  * Returns whether the given set of divisors are valid for a given refclk with
 488  * the given connectors.
 489  */
 490
 491 static bool intel_PLL_is_valid(struct drm_device *dev,
 492                                const intel_limit_t *limit,
 493                                const intel_clock_t *clock)
 494 {
 495         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 496                 INTELPllInvalid("p1 out of range\n");
 497         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 498                 INTELPllInvalid("p out of range\n");
 499         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 500                 INTELPllInvalid("m2 out of range\n");
 501         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 502                 INTELPllInvalid("m1 out of range\n");
 503         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 504                 INTELPllInvalid("m1 <= m2\n");
 505         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 506                 INTELPllInvalid("m out of range\n");
 507         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 508                 INTELPllInvalid("n out of range\n");
 509         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 510                 INTELPllInvalid("vco out of range\n");
 511         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 512          * connector, etc., rather than just a single range.
 513          */
 514         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 515                 INTELPllInvalid("dot out of range\n");
 516
 517         return true;
 518 }
 519
 520 static bool
 521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 522                     int target, int refclk, intel_clock_t *match_clock,
 523                     intel_clock_t *best_clock)
 524
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         intel_clock_t clock;
 529         int err = target;
 530
 531         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 532             (I915_READ(LVDS)) != 0) {
 533                 /*
 534                  * For LVDS, if the panel is on, just rely on its current
 535                  * settings for dual-channel.  We haven't figured out how to
 536                  * reliably set up different single/dual channel state, if we
 537                  * even can.
 538                  */
 539                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 540                     LVDS_CLKB_POWER_UP)
 541                         clock.p2 = limit->p2.p2_fast;
 542                 else
 543                         clock.p2 = limit->p2.p2_slow;
 544         } else {
 545                 if (target < limit->p2.dot_limit)
 546                         clock.p2 = limit->p2.p2_slow;
 547                 else
 548                         clock.p2 = limit->p2.p2_fast;
 549         }
 550
 551         memset(best_clock, 0, sizeof(*best_clock));
 552
 553         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 554              clock.m1++) {
 555                 for (clock.m2 = limit->m2.min;
 556                      clock.m2 <= limit->m2.max; clock.m2++) {
 557                         /* m1 is always 0 in Pineview */
 558                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 559                                 break;
 560                         for (clock.n = limit->n.min;
 561                              clock.n <= limit->n.max; clock.n++) {
 562                                 for (clock.p1 = limit->p1.min;
 563                                         clock.p1 <= limit->p1.max; clock.p1++) {
 564                                         int this_err;
 565
 566                                         intel_clock(dev, refclk, &clock);
 567                                         if (!intel_PLL_is_valid(dev, limit,
 568                                                                 &clock))
 569                                                 continue;
 570                                         if (match_clock &&
 571                                             clock.p != match_clock->p)
 572                                                 continue;
 573
 574                                         this_err = abs(clock.dot - target);
 575                                         if (this_err < err) {
 576                                                 *best_clock = clock;
 577                                                 err = this_err;
 578                                         }
 579                                 }
 580                         }
 581                 }
 582         }
 583
 584         return (err != target);
 585 }
 586
 587 static bool
 588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 589                         int target, int refclk, intel_clock_t *match_clock,
 590                         intel_clock_t *best_clock)
 591 {
 592         struct drm_device *dev = crtc->dev;
 593         struct drm_i915_private *dev_priv = dev->dev_private;
 594         intel_clock_t clock;
 595         int max_n;
 596         bool found;
 597         /* approximately equals target * 0.00585 */
 598         int err_most = (target >> 8) + (target >> 9);
 599         found = false;
 600
 601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 602                 int lvds_reg;
 603
 604                 if (HAS_PCH_SPLIT(dev))
 605                         lvds_reg = PCH_LVDS;
 606                 else
 607                         lvds_reg = LVDS;
 608                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 609                     LVDS_CLKB_POWER_UP)
 610                         clock.p2 = limit->p2.p2_fast;
 611                 else
 612                         clock.p2 = limit->p2.p2_slow;
 613         } else {
 614                 if (target < limit->p2.dot_limit)
 615                         clock.p2 = limit->p2.p2_slow;
 616                 else
 617                         clock.p2 = limit->p2.p2_fast;
 618         }
 619
 620         memset(best_clock, 0, sizeof(*best_clock));
 621         max_n = limit->n.max;
 622         /* based on hardware requirement, prefer smaller n to precision */
 623         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 624                 /* based on hardware requirement, prefere larger m1,m2 */
 625                 for (clock.m1 = limit->m1.max;
 626                      clock.m1 >= limit->m1.min; clock.m1--) {
 627                         for (clock.m2 = limit->m2.max;
 628                              clock.m2 >= limit->m2.min; clock.m2--) {
 629                                 for (clock.p1 = limit->p1.max;
 630                                      clock.p1 >= limit->p1.min; clock.p1--) {
 631                                         int this_err;
 632
 633                                         intel_clock(dev, refclk, &clock);
 634                                         if (!intel_PLL_is_valid(dev, limit,
 635                                                                 &clock))
 636                                                 continue;
 637                                         if (match_clock &&
 638                                             clock.p != match_clock->p)
 639                                                 continue;
 640
 641                                         this_err = abs(clock.dot - target);
 642                                         if (this_err < err_most) {
 643                                                 *best_clock = clock;
 644                                                 err_most = this_err;
 645                                                 max_n = clock.n;
 646                                                 found = true;
 647                                         }
 648                                 }
 649                         }
 650                 }
 651         }
 652         return found;
 653 }
 654
 655 static bool
 656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 657                            int target, int refclk, intel_clock_t *match_clock,
 658                            intel_clock_t *best_clock)
 659 {
 660         struct drm_device *dev = crtc->dev;
 661         intel_clock_t clock;
 662
 663         if (target < 200000) {
 664                 clock.n = 1;
 665                 clock.p1 = 2;
 666                 clock.p2 = 10;
 667                 clock.m1 = 12;
 668                 clock.m2 = 9;
 669         } else {
 670                 clock.n = 2;
 671                 clock.p1 = 1;
 672                 clock.p2 = 10;
 673                 clock.m1 = 14;
 674                 clock.m2 = 8;
 675         }
 676         intel_clock(dev, refclk, &clock);
 677         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 678         return true;
 679 }
 680
 681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 682 static bool
 683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                       int target, int refclk, intel_clock_t *match_clock,
 685                       intel_clock_t *best_clock)
 686 {
 687         intel_clock_t clock;
 688         if (target < 200000) {
 689                 clock.p1 = 2;
 690                 clock.p2 = 10;
 691                 clock.n = 2;
 692                 clock.m1 = 23;
 693                 clock.m2 = 8;
 694         } else {
 695                 clock.p1 = 1;
 696                 clock.p2 = 10;
 697                 clock.n = 1;
 698                 clock.m1 = 14;
 699                 clock.m2 = 2;
 700         }
 701         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 702         clock.p = (clock.p1 * clock.p2);
 703         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 704         clock.vco = 0;
 705         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 706         return true;
 707 }
 708
 709 /**
 710  * intel_wait_for_vblank - wait for vblank on a given pipe
 711  * @dev: drm device
 712  * @pipe: pipe to wait for
 713  *
 714  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 715  * mode setting code.
 716  */
 717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 718 {
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         int pipestat_reg = PIPESTAT(pipe);
 721
 722         /* Clear existing vblank status. Note this will clear any other
 723          * sticky status fields as well.
 724          *
 725          * This races with i915_driver_irq_handler() with the result
 726          * that either function could miss a vblank event.  Here it is not
 727          * fatal, as we will either wait upon the next vblank interrupt or
 728          * timeout.  Generally speaking intel_wait_for_vblank() is only
 729          * called during modeset at which time the GPU should be idle and
 730          * should *not* be performing page flips and thus not waiting on
 731          * vblanks...
 732          * Currently, the result of us stealing a vblank from the irq
 733          * handler is that a single frame will be skipped during swapbuffers.
 734          */
 735         I915_WRITE(pipestat_reg,
 736                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 737
 738         /* Wait for vblank interrupt bit to set */
 739         if (wait_for(I915_READ(pipestat_reg) &
 740                      PIPE_VBLANK_INTERRUPT_STATUS,
 741                      50))
 742                 DRM_DEBUG_KMS("vblank wait timed out\n");
 743 }
 744
 745 /*
 746  * intel_wait_for_pipe_off - wait for pipe to turn off
 747  * @dev: drm device
 748  * @pipe: pipe to wait for
 749  *
 750  * After disabling a pipe, we can't wait for vblank in the usual way,
 751  * spinning on the vblank interrupt status bit, since we won't actually
 752  * see an interrupt when the pipe is disabled.
 753  *
 754  * On Gen4 and above:
 755  *   wait for the pipe register state bit to turn off
 756  *
 757  * Otherwise:
 758  *   wait for the display line value to settle (it usually
 759  *   ends up stopping at the start of the next frame).
 760  *
 761  */
 762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765
 766         if (INTEL_INFO(dev)->gen >= 4) {
 767                 int reg = PIPECONF(pipe);
 768
 769                 /* Wait for the Pipe State to go off */
 770                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 771                              100))
 772                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 773         } else {
 774                 u32 last_line;
 775                 int reg = PIPEDSL(pipe);
 776                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 777
 778                 /* Wait for the display line to settle */
 779                 do {
 780                         last_line = I915_READ(reg) & DSL_LINEMASK;
 781                         mdelay(5);
 782                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 783                          time_after(timeout, jiffies));
 784                 if (time_after(jiffies, timeout))
 785                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 786         }
 787 }
 788
 789 static const char *state_string(bool enabled)
 790 {
 791         return enabled ? "on" : "off";
 792 }
 793
 794 /* Only for pre-ILK configs */
 795 static void assert_pll(struct drm_i915_private *dev_priv,
 796                        enum pipe pipe, bool state)
 797 {
 798         int reg;
 799         u32 val;
 800         bool cur_state;
 801
 802         reg = DPLL(pipe);
 803         val = I915_READ(reg);
 804         cur_state = !!(val & DPLL_VCO_ENABLE);
 805         WARN(cur_state != state,
 806              "PLL state assertion failure (expected %s, current %s)\n",
 807              state_string(state), state_string(cur_state));
 808 }
 809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 811
 812 /* For ILK+ */
 813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 814                            enum pipe pipe, bool state)
 815 {
 816         int reg;
 817         u32 val;
 818         bool cur_state;
 819
 820         if (HAS_PCH_CPT(dev_priv->dev)) {
 821                 u32 pch_dpll;
 822
 823                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 824
 825                 /* Make sure the selected PLL is enabled to the transcoder */
 826                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 827                      "transcoder %d PLL not enabled\n", pipe);
 828
 829                 /* Convert the transcoder pipe number to a pll pipe number */
 830                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 831         }
 832
 833         reg = PCH_DPLL(pipe);
 834         val = I915_READ(reg);
 835         cur_state = !!(val & DPLL_VCO_ENABLE);
 836         WARN(cur_state != state,
 837              "PCH PLL state assertion failure (expected %s, current %s)\n",
 838              state_string(state), state_string(cur_state));
 839 }
 840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 842
 843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 844                           enum pipe pipe, bool state)
 845 {
 846         int reg;
 847         u32 val;
 848         bool cur_state;
 849
 850         reg = FDI_TX_CTL(pipe);
 851         val = I915_READ(reg);
 852         cur_state = !!(val & FDI_TX_ENABLE);
 853         WARN(cur_state != state,
 854              "FDI TX state assertion failure (expected %s, current %s)\n",
 855              state_string(state), state_string(cur_state));
 856 }
 857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 859
 860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 861                           enum pipe pipe, bool state)
 862 {
 863         int reg;
 864         u32 val;
 865         bool cur_state;
 866
 867         reg = FDI_RX_CTL(pipe);
 868         val = I915_READ(reg);
 869         cur_state = !!(val & FDI_RX_ENABLE);
 870         WARN(cur_state != state,
 871              "FDI RX state assertion failure (expected %s, current %s)\n",
 872              state_string(state), state_string(cur_state));
 873 }
 874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 876
 877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 878                                       enum pipe pipe)
 879 {
 880         int reg;
 881         u32 val;
 882
 883         /* ILK FDI PLL is always enabled */
 884         if (dev_priv->info->gen == 5)
 885                 return;
 886
 887         reg = FDI_TX_CTL(pipe);
 888         val = I915_READ(reg);
 889         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 890 }
 891
 892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 893                                       enum pipe pipe)
 894 {
 895         int reg;
 896         u32 val;
 897
 898         reg = FDI_RX_CTL(pipe);
 899         val = I915_READ(reg);
 900         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 901 }
 902
 903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 904                                   enum pipe pipe)
 905 {
 906         int pp_reg, lvds_reg;
 907         u32 val;
 908         enum pipe panel_pipe = PIPE_A;
 909         bool locked = true;
 910
 911         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 912                 pp_reg = PCH_PP_CONTROL;
 913                 lvds_reg = PCH_LVDS;
 914         } else {
 915                 pp_reg = PP_CONTROL;
 916                 lvds_reg = LVDS;
 917         }
 918
 919         val = I915_READ(pp_reg);
 920         if (!(val & PANEL_POWER_ON) ||
 921             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 922                 locked = false;
 923
 924         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 925                 panel_pipe = PIPE_B;
 926
 927         WARN(panel_pipe == pipe && locked,
 928              "panel assertion failure, pipe %c regs locked\n",
 929              pipe_name(pipe));
 930 }
 931
 932 void assert_pipe(struct drm_i915_private *dev_priv,
 933                  enum pipe pipe, bool state)
 934 {
 935         int reg;
 936         u32 val;
 937         bool cur_state;
 938
 939         /* if we need the pipe A quirk it must be always on */
 940         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 941                 state = true;
 942
 943         reg = PIPECONF(pipe);
 944         val = I915_READ(reg);
 945         cur_state = !!(val & PIPECONF_ENABLE);
 946         WARN(cur_state != state,
 947              "pipe %c assertion failure (expected %s, current %s)\n",
 948              pipe_name(pipe), state_string(state), state_string(cur_state));
 949 }
 950
 951 static void assert_plane(struct drm_i915_private *dev_priv,
 952                          enum plane plane, bool state)
 953 {
 954         int reg;
 955         u32 val;
 956         bool cur_state;
 957
 958         reg = DSPCNTR(plane);
 959         val = I915_READ(reg);
 960         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 961         WARN(cur_state != state,
 962              "plane %c assertion failure (expected %s, current %s)\n",
 963              plane_name(plane), state_string(state), state_string(cur_state));
 964 }
 965
 966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 968
 969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 970                                    enum pipe pipe)
 971 {
 972         int reg, i;
 973         u32 val;
 974         int cur_pipe;
 975
 976         /* Planes are fixed to pipes on ILK+ */
 977         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 978                 reg = DSPCNTR(pipe);
 979                 val = I915_READ(reg);
 980                 WARN((val & DISPLAY_PLANE_ENABLE),
 981                      "plane %c assertion failure, should be disabled but not\n",
 982                      plane_name(pipe));
 983                 return;
 984         }
 985
 986         /* Need to check both planes against the pipe */
 987         for (i = 0; i < 2; i++) {
 988                 reg = DSPCNTR(i);
 989                 val = I915_READ(reg);
 990                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 991                         DISPPLANE_SEL_PIPE_SHIFT;
 992                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 993                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 994                      plane_name(i), pipe_name(pipe));
 995         }
 996 }
 997
 998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 999 {
1000         u32 val;
1001         bool enabled;
1002
1003         val = I915_READ(PCH_DREF_CONTROL);
1004         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005                             DREF_SUPERSPREAD_SOURCE_MASK));
1006         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010                                        enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014         bool enabled;
1015
1016         reg = TRANSCONF(pipe);
1017         val = I915_READ(reg);
1018         enabled = !!(val & TRANS_ENABLE);
1019         WARN(enabled,
1020              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021              pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025                             enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027         if ((val & DP_PORT_EN) == 0)
1028                 return false;
1029
1030         if (HAS_PCH_CPT(dev_priv->dev)) {
1031                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034                         return false;
1035         } else {
1036                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043                               enum pipe pipe, u32 val)
1044 {
1045         if ((val & PORT_ENABLE) == 0)
1046                 return false;
1047
1048         if (HAS_PCH_CPT(dev_priv->dev)) {
1049                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050                         return false;
1051         } else {
1052                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053                         return false;
1054         }
1055         return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059                               enum pipe pipe, u32 val)
1060 {
1061         if ((val & LVDS_PORT_EN) == 0)
1062                 return false;
1063
1064         if (HAS_PCH_CPT(dev_priv->dev)) {
1065                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066                         return false;
1067         } else {
1068                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075                               enum pipe pipe, u32 val)
1076 {
1077         if ((val & ADPA_DAC_ENABLE) == 0)
1078                 return false;
1079         if (HAS_PCH_CPT(dev_priv->dev)) {
1080                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081                         return false;
1082         } else {
1083                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084                         return false;
1085         }
1086         return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090                                    enum pipe pipe, int reg, u32 port_sel)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099                                      enum pipe pipe, int reg)
1100 {
1101         u32 val = I915_READ(reg);
1102         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104              reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108                                       enum pipe pipe)
1109 {
1110         int reg;
1111         u32 val;
1112
1113         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117         reg = PCH_ADPA;
1118         val = I915_READ(reg);
1119         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120              "PCH VGA enabled on transcoder %c, should be disabled\n",
1121              pipe_name(pipe));
1122
1123         reg = PCH_LVDS;
1124         val = I915_READ(reg);
1125         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127              pipe_name(pipe));
1128
1129         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135  * intel_enable_pll - enable a PLL
1136  * @dev_priv: i915 private structure
1137  * @pipe: pipe PLL to enable
1138  *
1139  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1140  * make sure the PLL reg is writable first though, since the panel write
1141  * protect mechanism may be enabled.
1142  *
1143  * Note!  This is for pre-ILK only.
1144  */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147         int reg;
1148         u32 val;
1149
1150         /* No really, not for ILK+ */
1151         BUG_ON(dev_priv->info->gen >= 5);
1152
1153         /* PLL is protected by panel, make sure we can write it */
1154         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155                 assert_panel_unlocked(dev_priv, pipe);
1156
1157         reg = DPLL(pipe);
1158         val = I915_READ(reg);
1159         val |= DPLL_VCO_ENABLE;
1160
1161         /* We do this three times for luck */
1162         I915_WRITE(reg, val);
1163         POSTING_READ(reg);
1164         udelay(150); /* wait for warmup */
1165         I915_WRITE(reg, val);
1166         POSTING_READ(reg);
1167         udelay(150); /* wait for warmup */
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170         udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174  * intel_disable_pll - disable a PLL
1175  * @dev_priv: i915 private structure
1176  * @pipe: pipe PLL to disable
1177  *
1178  * Disable the PLL for @pipe, making sure the pipe is off first.
1179  *
1180  * Note!  This is for pre-ILK only.
1181  */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         /* Don't disable pipe A or pipe A PLLs if needed */
1188         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189                 return;
1190
1191         /* Make sure the pipe isn't still relying on us */
1192         assert_pipe_disabled(dev_priv, pipe);
1193
1194         reg = DPLL(pipe);
1195         val = I915_READ(reg);
1196         val &= ~DPLL_VCO_ENABLE;
1197         I915_WRITE(reg, val);
1198         POSTING_READ(reg);
1199 }
1200
1201 /**
1202  * intel_enable_pch_pll - enable PCH PLL
1203  * @dev_priv: i915 private structure
1204  * @pipe: pipe PLL to enable
1205  *
1206  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207  * drives the transcoder clock.
1208  */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210                                  enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         if (pipe > 1)
1216                 return;
1217
1218         /* PCH only available on ILK+ */
1219         BUG_ON(dev_priv->info->gen < 5);
1220
1221         /* PCH refclock must be enabled first */
1222         assert_pch_refclk_enabled(dev_priv);
1223
1224         reg = PCH_DPLL(pipe);
1225         val = I915_READ(reg);
1226         val |= DPLL_VCO_ENABLE;
1227         I915_WRITE(reg, val);
1228         POSTING_READ(reg);
1229         udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233                                   enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237                 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239         if (pipe > 1)
1240                 return;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure transcoder isn't still depending on us */
1246         assert_transcoder_disabled(dev_priv, pipe);
1247
1248         if (pipe == 0)
1249                 pll_sel |= TRANSC_DPLLA_SEL;
1250         else if (pipe == 1)
1251                 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255                 return;
1256
1257         reg = PCH_DPLL(pipe);
1258         val = I915_READ(reg);
1259         val &= ~DPLL_VCO_ENABLE;
1260         I915_WRITE(reg, val);
1261         POSTING_READ(reg);
1262         udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         int reg;
1269         u32 val, pipeconf_val;
1270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1271
1272         /* PCH only available on ILK+ */
1273         BUG_ON(dev_priv->info->gen < 5);
1274
1275         /* Make sure PCH DPLL is enabled */
1276         assert_pch_pll_enabled(dev_priv, pipe);
1277
1278         /* FDI must be feeding us bits for PCH ports */
1279         assert_fdi_tx_enabled(dev_priv, pipe);
1280         assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282         reg = TRANSCONF(pipe);
1283         val = I915_READ(reg);
1284         pipeconf_val = I915_READ(PIPECONF(pipe));
1285
1286         if (HAS_PCH_IBX(dev_priv->dev)) {
1287                 /*
1288                  * make the BPC in transcoder be consistent with
1289                  * that in pipeconf reg.
1290                  */
1291                 val &= ~PIPE_BPC_MASK;
1292                 val |= pipeconf_val & PIPE_BPC_MASK;
1293         }
1294
1295         val &= ~TRANS_INTERLACE_MASK;
1296         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1297                 if (HAS_PCH_IBX(dev_priv->dev) &&
1298                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299                         val |= TRANS_LEGACY_INTERLACED_ILK;
1300                 else
1301                         val |= TRANS_INTERLACED;
1302         else
1303                 val |= TRANS_PROGRESSIVE;
1304
1305         I915_WRITE(reg, val | TRANS_ENABLE);
1306         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308 }
1309
1310 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311                                      enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         /* FDI relies on the transcoder */
1317         assert_fdi_tx_disabled(dev_priv, pipe);
1318         assert_fdi_rx_disabled(dev_priv, pipe);
1319
1320         /* Ports must be off as well */
1321         assert_pch_ports_disabled(dev_priv, pipe);
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         val &= ~TRANS_ENABLE;
1326         I915_WRITE(reg, val);
1327         /* wait for PCH transcoder off, transcoder state */
1328         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1329                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1330 }
1331
1332 /**
1333  * intel_enable_pipe - enable a pipe, asserting requirements
1334  * @dev_priv: i915 private structure
1335  * @pipe: pipe to enable
1336  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1337  *
1338  * Enable @pipe, making sure that various hardware specific requirements
1339  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340  *
1341  * @pipe should be %PIPE_A or %PIPE_B.
1342  *
1343  * Will wait until the pipe is actually running (i.e. first vblank) before
1344  * returning.
1345  */
1346 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347                               bool pch_port)
1348 {
1349         int reg;
1350         u32 val;
1351
1352         /*
1353          * A pipe without a PLL won't actually be able to drive bits from
1354          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1355          * need the check.
1356          */
1357         if (!HAS_PCH_SPLIT(dev_priv->dev))
1358                 assert_pll_enabled(dev_priv, pipe);
1359         else {
1360                 if (pch_port) {
1361                         /* if driving the PCH, we need FDI enabled */
1362                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364                 }
1365                 /* FIXME: assert CPU port conditions for SNB+ */
1366         }
1367
1368         reg = PIPECONF(pipe);
1369         val = I915_READ(reg);
1370         if (val & PIPECONF_ENABLE)
1371                 return;
1372
1373         I915_WRITE(reg, val | PIPECONF_ENABLE);
1374         intel_wait_for_vblank(dev_priv->dev, pipe);
1375 }
1376
1377 /**
1378  * intel_disable_pipe - disable a pipe, asserting requirements
1379  * @dev_priv: i915 private structure
1380  * @pipe: pipe to disable
1381  *
1382  * Disable @pipe, making sure that various hardware specific requirements
1383  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384  *
1385  * @pipe should be %PIPE_A or %PIPE_B.
1386  *
1387  * Will wait until the pipe has shut down before returning.
1388  */
1389 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390                                enum pipe pipe)
1391 {
1392         int reg;
1393         u32 val;
1394
1395         /*
1396          * Make sure planes won't keep trying to pump pixels to us,
1397          * or we might hang the display.
1398          */
1399         assert_planes_disabled(dev_priv, pipe);
1400
1401         /* Don't disable pipe A or pipe A PLLs if needed */
1402         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403                 return;
1404
1405         reg = PIPECONF(pipe);
1406         val = I915_READ(reg);
1407         if ((val & PIPECONF_ENABLE) == 0)
1408                 return;
1409
1410         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1411         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412 }
1413
1414 /*
1415  * Plane regs are double buffered, going from enabled->disabled needs a
1416  * trigger in order to latch.  The display address reg provides this.
1417  */
1418 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419                                       enum plane plane)
1420 {
1421         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423 }
1424
1425 /**
1426  * intel_enable_plane - enable a display plane on a given pipe
1427  * @dev_priv: i915 private structure
1428  * @plane: plane to enable
1429  * @pipe: pipe being fed
1430  *
1431  * Enable @plane on @pipe, making sure that @pipe is running first.
1432  */
1433 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434                                enum plane plane, enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440         assert_pipe_enabled(dev_priv, pipe);
1441
1442         reg = DSPCNTR(plane);
1443         val = I915_READ(reg);
1444         if (val & DISPLAY_PLANE_ENABLE)
1445                 return;
1446
1447         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1448         intel_flush_display_plane(dev_priv, plane);
1449         intel_wait_for_vblank(dev_priv->dev, pipe);
1450 }
1451
1452 /**
1453  * intel_disable_plane - disable a display plane
1454  * @dev_priv: i915 private structure
1455  * @plane: plane to disable
1456  * @pipe: pipe consuming the data
1457  *
1458  * Disable @plane; should be an independent operation.
1459  */
1460 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461                                 enum plane plane, enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         reg = DSPCNTR(plane);
1467         val = I915_READ(reg);
1468         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469                 return;
1470
1471         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1472         intel_flush_display_plane(dev_priv, plane);
1473         intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1477                            enum pipe pipe, int reg, u32 port_sel)
1478 {
1479         u32 val = I915_READ(reg);
1480         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1481                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1482                 I915_WRITE(reg, val & ~DP_PORT_EN);
1483         }
1484 }
1485
1486 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487                              enum pipe pipe, int reg)
1488 {
1489         u32 val = I915_READ(reg);
1490         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1491                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492                               reg, pipe);
1493                 I915_WRITE(reg, val & ~PORT_ENABLE);
1494         }
1495 }
1496
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499                                     enum pipe pipe)
1500 {
1501         u32 reg, val;
1502
1503         val = I915_READ(PCH_PP_CONTROL);
1504         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
1506         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1509
1510         reg = PCH_ADPA;
1511         val = I915_READ(reg);
1512         if (adpa_pipe_enabled(dev_priv, val, pipe))
1513                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515         reg = PCH_LVDS;
1516         val = I915_READ(reg);
1517         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1519                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520                 POSTING_READ(reg);
1521                 udelay(100);
1522         }
1523
1524         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526         disable_pch_hdmi(dev_priv, pipe, HDMID);
1527 }
1528
1529 static void i8xx_disable_fbc(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32 fbc_ctl;
1533
1534         /* Disable compression */
1535         fbc_ctl = I915_READ(FBC_CONTROL);
1536         if ((fbc_ctl & FBC_CTL_EN) == 0)
1537                 return;
1538
1539         fbc_ctl &= ~FBC_CTL_EN;
1540         I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542         /* Wait for compressing bit to clear */
1543         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544                 DRM_DEBUG_KMS("FBC idle timed out\n");
1545                 return;
1546         }
1547
1548         DRM_DEBUG_KMS("disabled FBC\n");
1549 }
1550
1551 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int cfb_pitch;
1560         int plane, i;
1561         u32 fbc_ctl, fbc_ctl2;
1562
1563         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564         if (fb->pitches[0] < cfb_pitch)
1565                 cfb_pitch = fb->pitches[0];
1566
1567         /* FBC_CTL wants 64B units */
1568         cfb_pitch = (cfb_pitch / 64) - 1;
1569         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571         /* Clear old tags */
1572         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573                 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575         /* Set it up... */
1576         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577         fbc_ctl2 |= plane;
1578         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581         /* enable it... */
1582         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583         if (IS_I945GM(dev))
1584                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587         fbc_ctl |= obj->fence_reg;
1588         I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591                       cfb_pitch, crtc->y, intel_crtc->plane);
1592 }
1593
1594 static bool i8xx_fbc_enabled(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599 }
1600
1601 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603         struct drm_device *dev = crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct drm_framebuffer *fb = crtc->fb;
1606         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607         struct drm_i915_gem_object *obj = intel_fb->obj;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610         unsigned long stall_watermark = 200;
1611         u32 dpfc_ctl;
1612
1613         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622         /* enable it... */
1623         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626 }
1627
1628 static void g4x_disable_fbc(struct drm_device *dev)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         u32 dpfc_ctl;
1632
1633         /* Disable compression */
1634         dpfc_ctl = I915_READ(DPFC_CONTROL);
1635         if (dpfc_ctl & DPFC_CTL_EN) {
1636                 dpfc_ctl &= ~DPFC_CTL_EN;
1637                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639                 DRM_DEBUG_KMS("disabled FBC\n");
1640         }
1641 }
1642
1643 static bool g4x_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648 }
1649
1650 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 blt_ecoskpd;
1654
1655         /* Make sure blitter notifies FBC of writes */
1656         gen6_gt_force_wake_get(dev_priv);
1657         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659                 GEN6_BLITTER_LOCK_SHIFT;
1660         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664                          GEN6_BLITTER_LOCK_SHIFT);
1665         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667         gen6_gt_force_wake_put(dev_priv);
1668 }
1669
1670 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct drm_framebuffer *fb = crtc->fb;
1675         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676         struct drm_i915_gem_object *obj = intel_fb->obj;
1677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679         unsigned long stall_watermark = 200;
1680         u32 dpfc_ctl;
1681
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         dpfc_ctl &= DPFC_RESERVED;
1684         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685         /* Set persistent mode for front-buffer rendering, ala X. */
1686         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695         /* enable it... */
1696         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698         if (IS_GEN6(dev)) {
1699                 I915_WRITE(SNB_DPFC_CTL_SA,
1700                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702                 sandybridge_blit_fbc_update(dev);
1703         }
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void ironlake_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool ironlake_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 bool intel_fbc_enabled(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734         if (!dev_priv->display.fbc_enabled)
1735                 return false;
1736
1737         return dev_priv->display.fbc_enabled(dev);
1738 }
1739
1740 static void intel_fbc_work_fn(struct work_struct *__work)
1741 {
1742         struct intel_fbc_work *work =
1743                 container_of(to_delayed_work(__work),
1744                              struct intel_fbc_work, work);
1745         struct drm_device *dev = work->crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         mutex_lock(&dev->struct_mutex);
1749         if (work == dev_priv->fbc_work) {
1750                 /* Double check that we haven't switched fb without cancelling
1751                  * the prior work.
1752                  */
1753                 if (work->crtc->fb == work->fb) {
1754                         dev_priv->display.enable_fbc(work->crtc,
1755                                                      work->interval);
1756
1757                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1759                         dev_priv->cfb_y = work->crtc->y;
1760                 }
1761
1762                 dev_priv->fbc_work = NULL;
1763         }
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         kfree(work);
1767 }
1768
1769 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770 {
1771         if (dev_priv->fbc_work == NULL)
1772                 return;
1773
1774         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776         /* Synchronisation is provided by struct_mutex and checking of
1777          * dev_priv->fbc_work, so we can perform the cancellation
1778          * entirely asynchronously.
1779          */
1780         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781                 /* tasklet was killed before being run, clean up */
1782                 kfree(dev_priv->fbc_work);
1783
1784         /* Mark the work as no longer wanted so that if it does
1785          * wake-up (because the work was already running and waiting
1786          * for our mutex), it will discover that is no longer
1787          * necessary to run.
1788          */
1789         dev_priv->fbc_work = NULL;
1790 }
1791
1792 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793 {
1794         struct intel_fbc_work *work;
1795         struct drm_device *dev = crtc->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         if (!dev_priv->display.enable_fbc)
1799                 return;
1800
1801         intel_cancel_fbc_work(dev_priv);
1802
1803         work = kzalloc(sizeof *work, GFP_KERNEL);
1804         if (work == NULL) {
1805                 dev_priv->display.enable_fbc(crtc, interval);
1806                 return;
1807         }
1808
1809         work->crtc = crtc;
1810         work->fb = crtc->fb;
1811         work->interval = interval;
1812         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814         dev_priv->fbc_work = work;
1815
1816         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818         /* Delay the actual enabling to let pageflipping cease and the
1819          * display to settle before starting the compression. Note that
1820          * this delay also serves a second purpose: it allows for a
1821          * vblank to pass after disabling the FBC before we attempt
1822          * to modify the control registers.
1823          *
1824          * A more complicated solution would involve tracking vblanks
1825          * following the termination of the page-flipping sequence
1826          * and indeed performing the enable as a co-routine and not
1827          * waiting synchronously upon the vblank.
1828          */
1829         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830 }
1831
1832 void intel_disable_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         intel_cancel_fbc_work(dev_priv);
1837
1838         if (!dev_priv->display.disable_fbc)
1839                 return;
1840
1841         dev_priv->display.disable_fbc(dev);
1842         dev_priv->cfb_plane = -1;
1843 }
1844
1845 /**
1846  * intel_update_fbc - enable/disable FBC as needed
1847  * @dev: the drm_device
1848  *
1849  * Set up the framebuffer compression hardware at mode set time.  We
1850  * enable it if possible:
1851  *   - plane A only (on pre-965)
1852  *   - no pixel mulitply/line duplication
1853  *   - no alpha buffer discard
1854  *   - no dual wide
1855  *   - framebuffer <= 2048 in width, 1536 in height
1856  *
1857  * We can't assume that any compression will take place (worst case),
1858  * so the compressed buffer has to be the same size as the uncompressed
1859  * one.  It also must reside (along with the line length buffer) in
1860  * stolen memory.
1861  *
1862  * We need to enable/disable FBC on a global basis.
1863  */
1864 static void intel_update_fbc(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct drm_crtc *crtc = NULL, *tmp_crtc;
1868         struct intel_crtc *intel_crtc;
1869         struct drm_framebuffer *fb;
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int enable_fbc;
1873
1874         DRM_DEBUG_KMS("\n");
1875
1876         if (!i915_powersave)
1877                 return;
1878
1879         if (!I915_HAS_FBC(dev))
1880                 return;
1881
1882         /*
1883          * If FBC is already on, we just have to verify that we can
1884          * keep it that way...
1885          * Need to disable if:
1886          *   - more than one pipe is active
1887          *   - changing FBC params (stride, fence, mode)
1888          *   - new fb is too large to fit in compressed buffer
1889          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1890          */
1891         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893                         if (crtc) {
1894                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896                                 goto out_disable;
1897                         }
1898                         crtc = tmp_crtc;
1899                 }
1900         }
1901
1902         if (!crtc || crtc->fb == NULL) {
1903                 DRM_DEBUG_KMS("no output, disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905                 goto out_disable;
1906         }
1907
1908         intel_crtc = to_intel_crtc(crtc);
1909         fb = crtc->fb;
1910         intel_fb = to_intel_framebuffer(fb);
1911         obj = intel_fb->obj;
1912
1913         enable_fbc = i915_enable_fbc;
1914         if (enable_fbc < 0) {
1915                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916                 enable_fbc = 1;
1917                 if (INTEL_INFO(dev)->gen <= 6)
1918                         enable_fbc = 0;
1919         }
1920         if (!enable_fbc) {
1921                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923                 goto out_disable;
1924         }
1925         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927                               "compression\n");
1928                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929                 goto out_disable;
1930         }
1931         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933                 DRM_DEBUG_KMS("mode incompatible with compression, "
1934                               "disabling\n");
1935                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936                 goto out_disable;
1937         }
1938         if ((crtc->mode.hdisplay > 2048) ||
1939             (crtc->mode.vdisplay > 1536)) {
1940                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942                 goto out_disable;
1943         }
1944         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947                 goto out_disable;
1948         }
1949
1950         /* The use of a CPU fence is mandatory in order to detect writes
1951          * by the CPU to the scanout and trigger updates to the FBC.
1952          */
1953         if (obj->tiling_mode != I915_TILING_X ||
1954             obj->fence_reg == I915_FENCE_REG_NONE) {
1955                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957                 goto out_disable;
1958         }
1959
1960         /* If the kernel debugger is active, always disable compression */
1961         if (in_dbg_master())
1962                 goto out_disable;
1963
1964         /* If the scanout has not changed, don't modify the FBC settings.
1965          * Note that we make the fundamental assumption that the fb->obj
1966          * cannot be unpinned (and have its GTT offset and fence revoked)
1967          * without first being decoupled from the scanout and FBC disabled.
1968          */
1969         if (dev_priv->cfb_plane == intel_crtc->plane &&
1970             dev_priv->cfb_fb == fb->base.id &&
1971             dev_priv->cfb_y == crtc->y)
1972                 return;
1973
1974         if (intel_fbc_enabled(dev)) {
1975                 /* We update FBC along two paths, after changing fb/crtc
1976                  * configuration (modeswitching) and after page-flipping
1977                  * finishes. For the latter, we know that not only did
1978                  * we disable the FBC at the start of the page-flip
1979                  * sequence, but also more than one vblank has passed.
1980                  *
1981                  * For the former case of modeswitching, it is possible
1982                  * to switch between two FBC valid configurations
1983                  * instantaneously so we do need to disable the FBC
1984                  * before we can modify its control registers. We also
1985                  * have to wait for the next vblank for that to take
1986                  * effect. However, since we delay enabling FBC we can
1987                  * assume that a vblank has passed since disabling and
1988                  * that we can safely alter the registers in the deferred
1989                  * callback.
1990                  *
1991                  * In the scenario that we go from a valid to invalid
1992                  * and then back to valid FBC configuration we have
1993                  * no strict enforcement that a vblank occurred since
1994                  * disabling the FBC. However, along all current pipe
1995                  * disabling paths we do need to wait for a vblank at
1996                  * some point. And we wait before enabling FBC anyway.
1997                  */
1998                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999                 intel_disable_fbc(dev);
2000         }
2001
2002         intel_enable_fbc(crtc, 500);
2003         return;
2004
2005 out_disable:
2006         /* Multiple disables should be harmless */
2007         if (intel_fbc_enabled(dev)) {
2008                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009                 intel_disable_fbc(dev);
2010         }
2011 }
2012
2013 int
2014 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015                            struct drm_i915_gem_object *obj,
2016                            struct intel_ring_buffer *pipelined)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 alignment;
2020         int ret;
2021
2022         switch (obj->tiling_mode) {
2023         case I915_TILING_NONE:
2024                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                         alignment = 128 * 1024;
2026                 else if (INTEL_INFO(dev)->gen >= 4)
2027                         alignment = 4 * 1024;
2028                 else
2029                         alignment = 64 * 1024;
2030                 break;
2031         case I915_TILING_X:
2032                 /* pin() will align the object as required by fence */
2033                 alignment = 0;
2034                 break;
2035         case I915_TILING_Y:
2036                 /* FIXME: Is this true? */
2037                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038                 return -EINVAL;
2039         default:
2040                 BUG();
2041         }
2042
2043         dev_priv->mm.interruptible = false;
2044         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2045         if (ret)
2046                 goto err_interruptible;
2047
2048         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049          * fence, whereas 965+ only requires a fence if using
2050          * framebuffer compression.  For simplicity, we always install
2051          * a fence as the cost is not that onerous.
2052          */
2053         if (obj->tiling_mode != I915_TILING_NONE) {
2054                 ret = i915_gem_object_get_fence(obj, pipelined);
2055                 if (ret)
2056                         goto err_unpin;
2057
2058                 i915_gem_object_pin_fence(obj);
2059         }
2060
2061         dev_priv->mm.interruptible = true;
2062         return 0;
2063
2064 err_unpin:
2065         i915_gem_object_unpin(obj);
2066 err_interruptible:
2067         dev_priv->mm.interruptible = true;
2068         return ret;
2069 }
2070
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072 {
2073         i915_gem_object_unpin_fence(obj);
2074         i915_gem_object_unpin(obj);
2075 }
2076
2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078                              int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long Start, Offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093                 break;
2094         default:
2095                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096                 return -EINVAL;
2097         }
2098
2099         intel_fb = to_intel_framebuffer(fb);
2100         obj = intel_fb->obj;
2101
2102         reg = DSPCNTR(plane);
2103         dspcntr = I915_READ(reg);
2104         /* Mask out pixel format bits in case we change it */
2105         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106         switch (fb->bits_per_pixel) {
2107         case 8:
2108                 dspcntr |= DISPPLANE_8BPP;
2109                 break;
2110         case 16:
2111                 if (fb->depth == 15)
2112                         dspcntr |= DISPPLANE_15_16BPP;
2113                 else
2114                         dspcntr |= DISPPLANE_16BPP;
2115                 break;
2116         case 24:
2117         case 32:
2118                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 break;
2120         default:
2121                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122                 return -EINVAL;
2123         }
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 if (obj->tiling_mode != I915_TILING_NONE)
2126                         dspcntr |= DISPPLANE_TILED;
2127                 else
2128                         dspcntr &= ~DISPPLANE_TILED;
2129         }
2130
2131         I915_WRITE(reg, dspcntr);
2132
2133         Start = obj->gtt_offset;
2134         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       Start, Offset, x, y, fb->pitches[0]);
2138         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 I915_WRITE(DSPSURF(plane), Start);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPADDR(plane), Offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), Start + Offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long Start, Offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->bits_per_pixel) {
2181         case 8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case 16:
2185                 if (fb->depth != 16)
2186                         return -EINVAL;
2187
2188                 dspcntr |= DISPPLANE_16BPP;
2189                 break;
2190         case 24:
2191         case 32:
2192                 if (fb->depth == 24)
2193                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194                 else if (fb->depth == 30)
2195                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196                 else
2197                         return -EINVAL;
2198                 break;
2199         default:
2200                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201                 return -EINVAL;
2202         }
2203
2204         if (obj->tiling_mode != I915_TILING_NONE)
2205                 dspcntr |= DISPPLANE_TILED;
2206         else
2207                 dspcntr &= ~DISPPLANE_TILED;
2208
2209         /* must disable */
2210         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212         I915_WRITE(reg, dspcntr);
2213
2214         Start = obj->gtt_offset;
2215         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2216
2217         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218                       Start, Offset, x, y, fb->pitches[0]);
2219         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220         I915_WRITE(DSPSURF(plane), Start);
2221         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222         I915_WRITE(DSPADDR(plane), Offset);
2223         POSTING_READ(reg);
2224
2225         return 0;
2226 }
2227
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2229 static int
2230 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231                            int x, int y, enum mode_set_atomic state)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         int ret;
2236
2237         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238         if (ret)
2239                 return ret;
2240
2241         intel_update_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return 0;
2245 }
2246
2247 static int
2248 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2249                     struct drm_framebuffer *old_fb)
2250 {
2251         struct drm_device *dev = crtc->dev;
2252         struct drm_i915_master_private *master_priv;
2253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2254         int ret;
2255
2256         /* no fb bound */
2257         if (!crtc->fb) {
2258                 DRM_ERROR("No FB bound\n");
2259                 return 0;
2260         }
2261
2262         switch (intel_crtc->plane) {
2263         case 0:
2264         case 1:
2265                 break;
2266         case 2:
2267                 if (IS_IVYBRIDGE(dev))
2268                         break;
2269                 /* fall through otherwise */
2270         default:
2271                 DRM_ERROR("no plane for crtc\n");
2272                 return -EINVAL;
2273         }
2274
2275         mutex_lock(&dev->struct_mutex);
2276         ret = intel_pin_and_fence_fb_obj(dev,
2277                                          to_intel_framebuffer(crtc->fb)->obj,
2278                                          NULL);
2279         if (ret != 0) {
2280                 mutex_unlock(&dev->struct_mutex);
2281                 DRM_ERROR("pin & fence failed\n");
2282                 return ret;
2283         }
2284
2285         if (old_fb) {
2286                 struct drm_i915_private *dev_priv = dev->dev_private;
2287                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2288
2289                 wait_event(dev_priv->pending_flip_queue,
2290                            atomic_read(&dev_priv->mm.wedged) ||
2291                            atomic_read(&obj->pending_flip) == 0);
2292
2293                 /* Big Hammer, we also need to ensure that any pending
2294                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2295                  * current scanout is retired before unpinning the old
2296                  * framebuffer.
2297                  *
2298                  * This should only fail upon a hung GPU, in which case we
2299                  * can safely continue.
2300                  */
2301                 ret = i915_gem_object_finish_gpu(obj);
2302                 (void) ret;
2303         }
2304
2305         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2306                                          LEAVE_ATOMIC_MODE_SET);
2307         if (ret) {
2308                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2309                 mutex_unlock(&dev->struct_mutex);
2310                 DRM_ERROR("failed to update base address\n");
2311                 return ret;
2312         }
2313
2314         if (old_fb) {
2315                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2316                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2317         }
2318
2319         mutex_unlock(&dev->struct_mutex);
2320
2321         if (!dev->primary->master)
2322                 return 0;
2323
2324         master_priv = dev->primary->master->driver_priv;
2325         if (!master_priv->sarea_priv)
2326                 return 0;
2327
2328         if (intel_crtc->pipe) {
2329                 master_priv->sarea_priv->pipeB_x = x;
2330                 master_priv->sarea_priv->pipeB_y = y;
2331         } else {
2332                 master_priv->sarea_priv->pipeA_x = x;
2333                 master_priv->sarea_priv->pipeA_y = y;
2334         }
2335
2336         return 0;
2337 }
2338
2339 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2340 {
2341         struct drm_device *dev = crtc->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         u32 dpa_ctl;
2344
2345         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2346         dpa_ctl = I915_READ(DP_A);
2347         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2348
2349         if (clock < 200000) {
2350                 u32 temp;
2351                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2352                 /* workaround for 160Mhz:
2353                    1) program 0x4600c bits 15:0 = 0x8124
2354                    2) program 0x46010 bit 0 = 1
2355                    3) program 0x46034 bit 24 = 1
2356                    4) program 0x64000 bit 14 = 1
2357                    */
2358                 temp = I915_READ(0x4600c);
2359                 temp &= 0xffff0000;
2360                 I915_WRITE(0x4600c, temp | 0x8124);
2361
2362                 temp = I915_READ(0x46010);
2363                 I915_WRITE(0x46010, temp | 1);
2364
2365                 temp = I915_READ(0x46034);
2366                 I915_WRITE(0x46034, temp | (1 << 24));
2367         } else {
2368                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2369         }
2370         I915_WRITE(DP_A, dpa_ctl);
2371
2372         POSTING_READ(DP_A);
2373         udelay(500);
2374 }
2375
2376 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2377 {
2378         struct drm_device *dev = crtc->dev;
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2381         int pipe = intel_crtc->pipe;
2382         u32 reg, temp;
2383
2384         /* enable normal train */
2385         reg = FDI_TX_CTL(pipe);
2386         temp = I915_READ(reg);
2387         if (IS_IVYBRIDGE(dev)) {
2388                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2389                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2390         } else {
2391                 temp &= ~FDI_LINK_TRAIN_NONE;
2392                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2393         }
2394         I915_WRITE(reg, temp);
2395
2396         reg = FDI_RX_CTL(pipe);
2397         temp = I915_READ(reg);
2398         if (HAS_PCH_CPT(dev)) {
2399                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2400                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2401         } else {
2402                 temp &= ~FDI_LINK_TRAIN_NONE;
2403                 temp |= FDI_LINK_TRAIN_NONE;
2404         }
2405         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2406
2407         /* wait one idle pattern time */
2408         POSTING_READ(reg);
2409         udelay(1000);
2410
2411         /* IVB wants error correction enabled */
2412         if (IS_IVYBRIDGE(dev))
2413                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2414                            FDI_FE_ERRC_ENABLE);
2415 }
2416
2417 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2418 {
2419         struct drm_i915_private *dev_priv = dev->dev_private;
2420         u32 flags = I915_READ(SOUTH_CHICKEN1);
2421
2422         flags |= FDI_PHASE_SYNC_OVR(pipe);
2423         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2424         flags |= FDI_PHASE_SYNC_EN(pipe);
2425         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2426         POSTING_READ(SOUTH_CHICKEN1);
2427 }
2428
2429 /* The FDI link training functions for ILK/Ibexpeak. */
2430 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2431 {
2432         struct drm_device *dev = crtc->dev;
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2435         int pipe = intel_crtc->pipe;
2436         int plane = intel_crtc->plane;
2437         u32 reg, temp, tries;
2438
2439         /* FDI needs bits from pipe & plane first */
2440         assert_pipe_enabled(dev_priv, pipe);
2441         assert_plane_enabled(dev_priv, plane);
2442
2443         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2444            for train result */
2445         reg = FDI_RX_IMR(pipe);
2446         temp = I915_READ(reg);
2447         temp &= ~FDI_RX_SYMBOL_LOCK;
2448         temp &= ~FDI_RX_BIT_LOCK;
2449         I915_WRITE(reg, temp);
2450         I915_READ(reg);
2451         udelay(150);
2452
2453         /* enable CPU FDI TX and PCH FDI RX */
2454         reg = FDI_TX_CTL(pipe);
2455         temp = I915_READ(reg);
2456         temp &= ~(7 << 19);
2457         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2458         temp &= ~FDI_LINK_TRAIN_NONE;
2459         temp |= FDI_LINK_TRAIN_PATTERN_1;
2460         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2461
2462         reg = FDI_RX_CTL(pipe);
2463         temp = I915_READ(reg);
2464         temp &= ~FDI_LINK_TRAIN_NONE;
2465         temp |= FDI_LINK_TRAIN_PATTERN_1;
2466         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467
2468         POSTING_READ(reg);
2469         udelay(150);
2470
2471         /* Ironlake workaround, enable clock pointer after FDI enable*/
2472         if (HAS_PCH_IBX(dev)) {
2473                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2475                            FDI_RX_PHASE_SYNC_POINTER_EN);
2476         }
2477
2478         reg = FDI_RX_IIR(pipe);
2479         for (tries = 0; tries < 5; tries++) {
2480                 temp = I915_READ(reg);
2481                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482
2483                 if ((temp & FDI_RX_BIT_LOCK)) {
2484                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2485                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                         break;
2487                 }
2488         }
2489         if (tries == 5)
2490                 DRM_ERROR("FDI train 1 fail!\n");
2491
2492         /* Train 2 */
2493         reg = FDI_TX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         temp &= ~FDI_LINK_TRAIN_NONE;
2496         temp |= FDI_LINK_TRAIN_PATTERN_2;
2497         I915_WRITE(reg, temp);
2498
2499         reg = FDI_RX_CTL(pipe);
2500         temp = I915_READ(reg);
2501         temp &= ~FDI_LINK_TRAIN_NONE;
2502         temp |= FDI_LINK_TRAIN_PATTERN_2;
2503         I915_WRITE(reg, temp);
2504
2505         POSTING_READ(reg);
2506         udelay(150);
2507
2508         reg = FDI_RX_IIR(pipe);
2509         for (tries = 0; tries < 5; tries++) {
2510                 temp = I915_READ(reg);
2511                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513                 if (temp & FDI_RX_SYMBOL_LOCK) {
2514                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2515                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2516                         break;
2517                 }
2518         }
2519         if (tries == 5)
2520                 DRM_ERROR("FDI train 2 fail!\n");
2521
2522         DRM_DEBUG_KMS("FDI train done\n");
2523
2524 }
2525
2526 static const int snb_b_fdi_train_param[] = {
2527         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2528         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2529         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2530         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2531 };
2532
2533 /* The FDI link training functions for SNB/Cougarpoint. */
2534 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2535 {
2536         struct drm_device *dev = crtc->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539         int pipe = intel_crtc->pipe;
2540         u32 reg, temp, i;
2541
2542         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543            for train result */
2544         reg = FDI_RX_IMR(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_RX_SYMBOL_LOCK;
2547         temp &= ~FDI_RX_BIT_LOCK;
2548         I915_WRITE(reg, temp);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         /* enable CPU FDI TX and PCH FDI RX */
2554         reg = FDI_TX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~(7 << 19);
2557         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_1;
2560         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561         /* SNB-B */
2562         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2563         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2564
2565         reg = FDI_RX_CTL(pipe);
2566         temp = I915_READ(reg);
2567         if (HAS_PCH_CPT(dev)) {
2568                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2569                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2570         } else {
2571                 temp &= ~FDI_LINK_TRAIN_NONE;
2572                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2573         }
2574         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2575
2576         POSTING_READ(reg);
2577         udelay(150);
2578
2579         if (HAS_PCH_CPT(dev))
2580                 cpt_phase_pointer_enable(dev, pipe);
2581
2582         for (i = 0; i < 4; i++) {
2583                 reg = FDI_TX_CTL(pipe);
2584                 temp = I915_READ(reg);
2585                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586                 temp |= snb_b_fdi_train_param[i];
2587                 I915_WRITE(reg, temp);
2588
2589                 POSTING_READ(reg);
2590                 udelay(500);
2591
2592                 reg = FDI_RX_IIR(pipe);
2593                 temp = I915_READ(reg);
2594                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596                 if (temp & FDI_RX_BIT_LOCK) {
2597                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2598                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2599                         break;
2600                 }
2601         }
2602         if (i == 4)
2603                 DRM_ERROR("FDI train 1 fail!\n");
2604
2605         /* Train 2 */
2606         reg = FDI_TX_CTL(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_LINK_TRAIN_NONE;
2609         temp |= FDI_LINK_TRAIN_PATTERN_2;
2610         if (IS_GEN6(dev)) {
2611                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612                 /* SNB-B */
2613                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614         }
2615         I915_WRITE(reg, temp);
2616
2617         reg = FDI_RX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         if (HAS_PCH_CPT(dev)) {
2620                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622         } else {
2623                 temp &= ~FDI_LINK_TRAIN_NONE;
2624                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2625         }
2626         I915_WRITE(reg, temp);
2627
2628         POSTING_READ(reg);
2629         udelay(150);
2630
2631         for (i = 0; i < 4; i++) {
2632                 reg = FDI_TX_CTL(pipe);
2633                 temp = I915_READ(reg);
2634                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635                 temp |= snb_b_fdi_train_param[i];
2636                 I915_WRITE(reg, temp);
2637
2638                 POSTING_READ(reg);
2639                 udelay(500);
2640
2641                 reg = FDI_RX_IIR(pipe);
2642                 temp = I915_READ(reg);
2643                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644
2645                 if (temp & FDI_RX_SYMBOL_LOCK) {
2646                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2647                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2648                         break;
2649                 }
2650         }
2651         if (i == 4)
2652                 DRM_ERROR("FDI train 2 fail!\n");
2653
2654         DRM_DEBUG_KMS("FDI train done.\n");
2655 }
2656
2657 /* Manual link training for Ivy Bridge A0 parts */
2658 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2659 {
2660         struct drm_device *dev = crtc->dev;
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663         int pipe = intel_crtc->pipe;
2664         u32 reg, temp, i;
2665
2666         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2667            for train result */
2668         reg = FDI_RX_IMR(pipe);
2669         temp = I915_READ(reg);
2670         temp &= ~FDI_RX_SYMBOL_LOCK;
2671         temp &= ~FDI_RX_BIT_LOCK;
2672         I915_WRITE(reg, temp);
2673
2674         POSTING_READ(reg);
2675         udelay(150);
2676
2677         /* enable CPU FDI TX and PCH FDI RX */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~(7 << 19);
2681         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2682         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2683         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2684         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686         temp |= FDI_COMPOSITE_SYNC;
2687         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2688
2689         reg = FDI_RX_CTL(pipe);
2690         temp = I915_READ(reg);
2691         temp &= ~FDI_LINK_TRAIN_AUTO;
2692         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2693         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2694         temp |= FDI_COMPOSITE_SYNC;
2695         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2696
2697         POSTING_READ(reg);
2698         udelay(150);
2699
2700         if (HAS_PCH_CPT(dev))
2701                 cpt_phase_pointer_enable(dev, pipe);
2702
2703         for (i = 0; i < 4; i++) {
2704                 reg = FDI_TX_CTL(pipe);
2705                 temp = I915_READ(reg);
2706                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2707                 temp |= snb_b_fdi_train_param[i];
2708                 I915_WRITE(reg, temp);
2709
2710                 POSTING_READ(reg);
2711                 udelay(500);
2712
2713                 reg = FDI_RX_IIR(pipe);
2714                 temp = I915_READ(reg);
2715                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2716
2717                 if (temp & FDI_RX_BIT_LOCK ||
2718                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2719                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2720                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2721                         break;
2722                 }
2723         }
2724         if (i == 4)
2725                 DRM_ERROR("FDI train 1 fail!\n");
2726
2727         /* Train 2 */
2728         reg = FDI_TX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2731         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2732         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2734         I915_WRITE(reg, temp);
2735
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2739         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2740         I915_WRITE(reg, temp);
2741
2742         POSTING_READ(reg);
2743         udelay(150);
2744
2745         for (i = 0; i < 4; i++) {
2746                 reg = FDI_TX_CTL(pipe);
2747                 temp = I915_READ(reg);
2748                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2749                 temp |= snb_b_fdi_train_param[i];
2750                 I915_WRITE(reg, temp);
2751
2752                 POSTING_READ(reg);
2753                 udelay(500);
2754
2755                 reg = FDI_RX_IIR(pipe);
2756                 temp = I915_READ(reg);
2757                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758
2759                 if (temp & FDI_RX_SYMBOL_LOCK) {
2760                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2761                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2762                         break;
2763                 }
2764         }
2765         if (i == 4)
2766                 DRM_ERROR("FDI train 2 fail!\n");
2767
2768         DRM_DEBUG_KMS("FDI train done.\n");
2769 }
2770
2771 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2772 {
2773         struct drm_device *dev = crtc->dev;
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776         int pipe = intel_crtc->pipe;
2777         u32 reg, temp;
2778
2779         /* Write the TU size bits so error detection works */
2780         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2781                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2782
2783         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2784         reg = FDI_RX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         temp &= ~((0x7 << 19) | (0x7 << 16));
2787         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2788         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2789         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2790
2791         POSTING_READ(reg);
2792         udelay(200);
2793
2794         /* Switch from Rawclk to PCDclk */
2795         temp = I915_READ(reg);
2796         I915_WRITE(reg, temp | FDI_PCDCLK);
2797
2798         POSTING_READ(reg);
2799         udelay(200);
2800
2801         /* Enable CPU FDI TX PLL, always on for Ironlake */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2805                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2806
2807                 POSTING_READ(reg);
2808                 udelay(100);
2809         }
2810 }
2811
2812 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         u32 flags = I915_READ(SOUTH_CHICKEN1);
2816
2817         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2818         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2819         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2820         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2821         POSTING_READ(SOUTH_CHICKEN1);
2822 }
2823 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2824 {
2825         struct drm_device *dev = crtc->dev;
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828         int pipe = intel_crtc->pipe;
2829         u32 reg, temp;
2830
2831         /* disable CPU FDI tx and PCH FDI rx */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2835         POSTING_READ(reg);
2836
2837         reg = FDI_RX_CTL(pipe);
2838         temp = I915_READ(reg);
2839         temp &= ~(0x7 << 16);
2840         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2841         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2842
2843         POSTING_READ(reg);
2844         udelay(100);
2845
2846         /* Ironlake workaround, disable clock pointer after downing FDI */
2847         if (HAS_PCH_IBX(dev)) {
2848                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2849                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2850                            I915_READ(FDI_RX_CHICKEN(pipe) &
2851                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2852         } else if (HAS_PCH_CPT(dev)) {
2853                 cpt_phase_pointer_disable(dev, pipe);
2854         }
2855
2856         /* still set train pattern 1 */
2857         reg = FDI_TX_CTL(pipe);
2858         temp = I915_READ(reg);
2859         temp &= ~FDI_LINK_TRAIN_NONE;
2860         temp |= FDI_LINK_TRAIN_PATTERN_1;
2861         I915_WRITE(reg, temp);
2862
2863         reg = FDI_RX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         if (HAS_PCH_CPT(dev)) {
2866                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2867                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2868         } else {
2869                 temp &= ~FDI_LINK_TRAIN_NONE;
2870                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2871         }
2872         /* BPC in FDI rx is consistent with that in PIPECONF */
2873         temp &= ~(0x07 << 16);
2874         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2875         I915_WRITE(reg, temp);
2876
2877         POSTING_READ(reg);
2878         udelay(100);
2879 }
2880
2881 /*
2882  * When we disable a pipe, we need to clear any pending scanline wait events
2883  * to avoid hanging the ring, which we assume we are waiting on.
2884  */
2885 static void intel_clear_scanline_wait(struct drm_device *dev)
2886 {
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_ring_buffer *ring;
2889         u32 tmp;
2890
2891         if (IS_GEN2(dev))
2892                 /* Can't break the hang on i8xx */
2893                 return;
2894
2895         ring = LP_RING(dev_priv);
2896         tmp = I915_READ_CTL(ring);
2897         if (tmp & RING_WAIT)
2898                 I915_WRITE_CTL(ring, tmp);
2899 }
2900
2901 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2902 {
2903         struct drm_i915_gem_object *obj;
2904         struct drm_i915_private *dev_priv;
2905
2906         if (crtc->fb == NULL)
2907                 return;
2908
2909         obj = to_intel_framebuffer(crtc->fb)->obj;
2910         dev_priv = crtc->dev->dev_private;
2911         wait_event(dev_priv->pending_flip_queue,
2912                    atomic_read(&obj->pending_flip) == 0);
2913 }
2914
2915 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct drm_mode_config *mode_config = &dev->mode_config;
2919         struct intel_encoder *encoder;
2920
2921         /*
2922          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2923          * must be driven by its own crtc; no sharing is possible.
2924          */
2925         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2926                 if (encoder->base.crtc != crtc)
2927                         continue;
2928
2929                 switch (encoder->type) {
2930                 case INTEL_OUTPUT_EDP:
2931                         if (!intel_encoder_is_pch_edp(&encoder->base))
2932                                 return false;
2933                         continue;
2934                 }
2935         }
2936
2937         return true;
2938 }
2939
2940 /*
2941  * Enable PCH resources required for PCH ports:
2942  *   - PCH PLLs
2943  *   - FDI training & RX/TX
2944  *   - update transcoder timings
2945  *   - DP transcoding bits
2946  *   - transcoder
2947  */
2948 static void ironlake_pch_enable(struct drm_crtc *crtc)
2949 {
2950         struct drm_device *dev = crtc->dev;
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2953         int pipe = intel_crtc->pipe;
2954         u32 reg, temp, transc_sel;
2955
2956         /* For PCH output, training FDI link */
2957         dev_priv->display.fdi_link_train(crtc);
2958
2959         intel_enable_pch_pll(dev_priv, pipe);
2960
2961         if (HAS_PCH_CPT(dev)) {
2962                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2963                         TRANSC_DPLLB_SEL;
2964
2965                 /* Be sure PCH DPLL SEL is set */
2966                 temp = I915_READ(PCH_DPLL_SEL);
2967                 if (pipe == 0) {
2968                         temp &= ~(TRANSA_DPLLB_SEL);
2969                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2970                 } else if (pipe == 1) {
2971                         temp &= ~(TRANSB_DPLLB_SEL);
2972                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2973                 } else if (pipe == 2) {
2974                         temp &= ~(TRANSC_DPLLB_SEL);
2975                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2976                 }
2977                 I915_WRITE(PCH_DPLL_SEL, temp);
2978         }
2979
2980         /* set transcoder timing, panel must allow it */
2981         assert_panel_unlocked(dev_priv, pipe);
2982         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2983         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2984         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2985
2986         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2987         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2988         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2989         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2990
2991         intel_fdi_normal_train(crtc);
2992
2993         /* For PCH DP, enable TRANS_DP_CTL */
2994         if (HAS_PCH_CPT(dev) &&
2995             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2996              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2997                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2998                 reg = TRANS_DP_CTL(pipe);
2999                 temp = I915_READ(reg);
3000                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3001                           TRANS_DP_SYNC_MASK |
3002                           TRANS_DP_BPC_MASK);
3003                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3004                          TRANS_DP_ENH_FRAMING);
3005                 temp |= bpc << 9; /* same format but at 11:9 */
3006
3007                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3008                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3009                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3010                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3011
3012                 switch (intel_trans_dp_port_sel(crtc)) {
3013                 case PCH_DP_B:
3014                         temp |= TRANS_DP_PORT_SEL_B;
3015                         break;
3016                 case PCH_DP_C:
3017                         temp |= TRANS_DP_PORT_SEL_C;
3018                         break;
3019                 case PCH_DP_D:
3020                         temp |= TRANS_DP_PORT_SEL_D;
3021                         break;
3022                 default:
3023                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3024                         temp |= TRANS_DP_PORT_SEL_B;
3025                         break;
3026                 }
3027
3028                 I915_WRITE(reg, temp);
3029         }
3030
3031         intel_enable_transcoder(dev_priv, pipe);
3032 }
3033
3034 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3035 {
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3038         u32 temp;
3039
3040         temp = I915_READ(dslreg);
3041         udelay(500);
3042         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3043                 /* Without this, mode sets may fail silently on FDI */
3044                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3045                 udelay(250);
3046                 I915_WRITE(tc2reg, 0);
3047                 if (wait_for(I915_READ(dslreg) != temp, 5))
3048                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3049         }
3050 }
3051
3052 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3053 {
3054         struct drm_device *dev = crtc->dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057         int pipe = intel_crtc->pipe;
3058         int plane = intel_crtc->plane;
3059         u32 temp;
3060         bool is_pch_port;
3061
3062         if (intel_crtc->active)
3063                 return;
3064
3065         intel_crtc->active = true;
3066         intel_update_watermarks(dev);
3067
3068         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3069                 temp = I915_READ(PCH_LVDS);
3070                 if ((temp & LVDS_PORT_EN) == 0)
3071                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3072         }
3073
3074         is_pch_port = intel_crtc_driving_pch(crtc);
3075
3076         if (is_pch_port)
3077                 ironlake_fdi_pll_enable(crtc);
3078         else
3079                 ironlake_fdi_disable(crtc);
3080
3081         /* Enable panel fitting for LVDS */
3082         if (dev_priv->pch_pf_size &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3084                 /* Force use of hard-coded filter coefficients
3085                  * as some pre-programmed values are broken,
3086                  * e.g. x201.
3087                  */
3088                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3089                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3090                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3091         }
3092
3093         /*
3094          * On ILK+ LUT must be loaded before the pipe is running but with
3095          * clocks enabled
3096          */
3097         intel_crtc_load_lut(crtc);
3098
3099         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3100         intel_enable_plane(dev_priv, plane, pipe);
3101
3102         if (is_pch_port)
3103                 ironlake_pch_enable(crtc);
3104
3105         mutex_lock(&dev->struct_mutex);
3106         intel_update_fbc(dev);
3107         mutex_unlock(&dev->struct_mutex);
3108
3109         intel_crtc_update_cursor(crtc, true);
3110 }
3111
3112 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117         int pipe = intel_crtc->pipe;
3118         int plane = intel_crtc->plane;
3119         u32 reg, temp;
3120
3121         if (!intel_crtc->active)
3122                 return;
3123
3124         intel_crtc_wait_for_pending_flips(crtc);
3125         drm_vblank_off(dev, pipe);
3126         intel_crtc_update_cursor(crtc, false);
3127
3128         intel_disable_plane(dev_priv, plane, pipe);
3129
3130         if (dev_priv->cfb_plane == plane)
3131                 intel_disable_fbc(dev);
3132
3133         intel_disable_pipe(dev_priv, pipe);
3134
3135         /* Disable PF */
3136         I915_WRITE(PF_CTL(pipe), 0);
3137         I915_WRITE(PF_WIN_SZ(pipe), 0);
3138
3139         ironlake_fdi_disable(crtc);
3140
3141         /* This is a horrible layering violation; we should be doing this in
3142          * the connector/encoder ->prepare instead, but we don't always have
3143          * enough information there about the config to know whether it will
3144          * actually be necessary or just cause undesired flicker.
3145          */
3146         intel_disable_pch_ports(dev_priv, pipe);
3147
3148         intel_disable_transcoder(dev_priv, pipe);
3149
3150         if (HAS_PCH_CPT(dev)) {
3151                 /* disable TRANS_DP_CTL */
3152                 reg = TRANS_DP_CTL(pipe);
3153                 temp = I915_READ(reg);
3154                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3155                 temp |= TRANS_DP_PORT_SEL_NONE;
3156                 I915_WRITE(reg, temp);
3157
3158                 /* disable DPLL_SEL */
3159                 temp = I915_READ(PCH_DPLL_SEL);
3160                 switch (pipe) {
3161                 case 0:
3162                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3163                         break;
3164                 case 1:
3165                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3166                         break;
3167                 case 2:
3168                         /* C shares PLL A or B */
3169                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3170                         break;
3171                 default:
3172                         BUG(); /* wtf */
3173                 }
3174                 I915_WRITE(PCH_DPLL_SEL, temp);
3175         }
3176
3177         /* disable PCH DPLL */
3178         if (!intel_crtc->no_pll)
3179                 intel_disable_pch_pll(dev_priv, pipe);
3180
3181         /* Switch from PCDclk to Rawclk */
3182         reg = FDI_RX_CTL(pipe);
3183         temp = I915_READ(reg);
3184         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3185
3186         /* Disable CPU FDI TX PLL */
3187         reg = FDI_TX_CTL(pipe);
3188         temp = I915_READ(reg);
3189         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3190
3191         POSTING_READ(reg);
3192         udelay(100);
3193
3194         reg = FDI_RX_CTL(pipe);
3195         temp = I915_READ(reg);
3196         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3197
3198         /* Wait for the clocks to turn off. */
3199         POSTING_READ(reg);
3200         udelay(100);
3201
3202         intel_crtc->active = false;
3203         intel_update_watermarks(dev);
3204
3205         mutex_lock(&dev->struct_mutex);
3206         intel_update_fbc(dev);
3207         intel_clear_scanline_wait(dev);
3208         mutex_unlock(&dev->struct_mutex);
3209 }
3210
3211 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3212 {
3213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214         int pipe = intel_crtc->pipe;
3215         int plane = intel_crtc->plane;
3216
3217         /* XXX: When our outputs are all unaware of DPMS modes other than off
3218          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3219          */
3220         switch (mode) {
3221         case DRM_MODE_DPMS_ON:
3222         case DRM_MODE_DPMS_STANDBY:
3223         case DRM_MODE_DPMS_SUSPEND:
3224                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3225                 ironlake_crtc_enable(crtc);
3226                 break;
3227
3228         case DRM_MODE_DPMS_OFF:
3229                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3230                 ironlake_crtc_disable(crtc);
3231                 break;
3232         }
3233 }
3234
3235 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3236 {
3237         if (!enable && intel_crtc->overlay) {
3238                 struct drm_device *dev = intel_crtc->base.dev;
3239                 struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241                 mutex_lock(&dev->struct_mutex);
3242                 dev_priv->mm.interruptible = false;
3243                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3244                 dev_priv->mm.interruptible = true;
3245                 mutex_unlock(&dev->struct_mutex);
3246         }
3247
3248         /* Let userspace switch the overlay on again. In most cases userspace
3249          * has to recompute where to put it anyway.
3250          */
3251 }
3252
3253 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3254 {
3255         struct drm_device *dev = crtc->dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258         int pipe = intel_crtc->pipe;
3259         int plane = intel_crtc->plane;
3260
3261         if (intel_crtc->active)
3262                 return;
3263
3264         intel_crtc->active = true;
3265         intel_update_watermarks(dev);
3266
3267         intel_enable_pll(dev_priv, pipe);
3268         intel_enable_pipe(dev_priv, pipe, false);
3269         intel_enable_plane(dev_priv, plane, pipe);
3270
3271         intel_crtc_load_lut(crtc);
3272         intel_update_fbc(dev);
3273
3274         /* Give the overlay scaler a chance to enable if it's on this pipe */
3275         intel_crtc_dpms_overlay(intel_crtc, true);
3276         intel_crtc_update_cursor(crtc, true);
3277 }
3278
3279 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3280 {
3281         struct drm_device *dev = crtc->dev;
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         int pipe = intel_crtc->pipe;
3285         int plane = intel_crtc->plane;
3286
3287         if (!intel_crtc->active)
3288                 return;
3289
3290         /* Give the overlay scaler a chance to disable if it's on this pipe */
3291         intel_crtc_wait_for_pending_flips(crtc);
3292         drm_vblank_off(dev, pipe);
3293         intel_crtc_dpms_overlay(intel_crtc, false);
3294         intel_crtc_update_cursor(crtc, false);
3295
3296         if (dev_priv->cfb_plane == plane)
3297                 intel_disable_fbc(dev);
3298
3299         intel_disable_plane(dev_priv, plane, pipe);
3300         intel_disable_pipe(dev_priv, pipe);
3301         intel_disable_pll(dev_priv, pipe);
3302
3303         intel_crtc->active = false;
3304         intel_update_fbc(dev);
3305         intel_update_watermarks(dev);
3306         intel_clear_scanline_wait(dev);
3307 }
3308
3309 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3310 {
3311         /* XXX: When our outputs are all unaware of DPMS modes other than off
3312          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3313          */
3314         switch (mode) {
3315         case DRM_MODE_DPMS_ON:
3316         case DRM_MODE_DPMS_STANDBY:
3317         case DRM_MODE_DPMS_SUSPEND:
3318                 i9xx_crtc_enable(crtc);
3319                 break;
3320         case DRM_MODE_DPMS_OFF:
3321                 i9xx_crtc_disable(crtc);
3322                 break;
3323         }
3324 }
3325
3326 /**
3327  * Sets the power management mode of the pipe and plane.
3328  */
3329 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3330 {
3331         struct drm_device *dev = crtc->dev;
3332         struct drm_i915_private *dev_priv = dev->dev_private;
3333         struct drm_i915_master_private *master_priv;
3334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335         int pipe = intel_crtc->pipe;
3336         bool enabled;
3337
3338         if (intel_crtc->dpms_mode == mode)
3339                 return;
3340
3341         intel_crtc->dpms_mode = mode;
3342
3343         dev_priv->display.dpms(crtc, mode);
3344
3345         if (!dev->primary->master)
3346                 return;
3347
3348         master_priv = dev->primary->master->driver_priv;
3349         if (!master_priv->sarea_priv)
3350                 return;
3351
3352         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3353
3354         switch (pipe) {
3355         case 0:
3356                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3357                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3358                 break;
3359         case 1:
3360                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3361                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3362                 break;
3363         default:
3364                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3365                 break;
3366         }
3367 }
3368
3369 static void intel_crtc_disable(struct drm_crtc *crtc)
3370 {
3371         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3372         struct drm_device *dev = crtc->dev;
3373
3374         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3375         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3376         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3377
3378         if (crtc->fb) {
3379                 mutex_lock(&dev->struct_mutex);
3380                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3381                 mutex_unlock(&dev->struct_mutex);
3382         }
3383 }
3384
3385 /* Prepare for a mode set.
3386  *
3387  * Note we could be a lot smarter here.  We need to figure out which outputs
3388  * will be enabled, which disabled (in short, how the config will changes)
3389  * and perform the minimum necessary steps to accomplish that, e.g. updating
3390  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3391  * panel fitting is in the proper state, etc.
3392  */
3393 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3394 {
3395         i9xx_crtc_disable(crtc);
3396 }
3397
3398 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3399 {
3400         i9xx_crtc_enable(crtc);
3401 }
3402
3403 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3404 {
3405         ironlake_crtc_disable(crtc);
3406 }
3407
3408 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3409 {
3410         ironlake_crtc_enable(crtc);
3411 }
3412
3413 void intel_encoder_prepare(struct drm_encoder *encoder)
3414 {
3415         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3416         /* lvds has its own version of prepare see intel_lvds_prepare */
3417         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3418 }
3419
3420 void intel_encoder_commit(struct drm_encoder *encoder)
3421 {
3422         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3423         struct drm_device *dev = encoder->dev;
3424         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3425         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3426
3427         /* lvds has its own version of commit see intel_lvds_commit */
3428         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3429
3430         if (HAS_PCH_CPT(dev))
3431                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3432 }
3433
3434 void intel_encoder_destroy(struct drm_encoder *encoder)
3435 {
3436         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3437
3438         drm_encoder_cleanup(encoder);
3439         kfree(intel_encoder);
3440 }
3441
3442 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3443                                   struct drm_display_mode *mode,
3444                                   struct drm_display_mode *adjusted_mode)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447
3448         if (HAS_PCH_SPLIT(dev)) {
3449                 /* FDI link clock is fixed at 2.7G */
3450                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3451                         return false;
3452         }
3453
3454         /* All interlaced capable intel hw wants timings in frames. */
3455         drm_mode_set_crtcinfo(adjusted_mode, 0);
3456
3457         return true;
3458 }
3459
3460 static int i945_get_display_clock_speed(struct drm_device *dev)
3461 {
3462         return 400000;
3463 }
3464
3465 static int i915_get_display_clock_speed(struct drm_device *dev)
3466 {
3467         return 333000;
3468 }
3469
3470 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3471 {
3472         return 200000;
3473 }
3474
3475 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3476 {
3477         u16 gcfgc = 0;
3478
3479         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3480
3481         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3482                 return 133000;
3483         else {
3484                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3485                 case GC_DISPLAY_CLOCK_333_MHZ:
3486                         return 333000;
3487                 default:
3488                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3489                         return 190000;
3490                 }
3491         }
3492 }
3493
3494 static int i865_get_display_clock_speed(struct drm_device *dev)
3495 {
3496         return 266000;
3497 }
3498
3499 static int i855_get_display_clock_speed(struct drm_device *dev)
3500 {
3501         u16 hpllcc = 0;
3502         /* Assume that the hardware is in the high speed state.  This
3503          * should be the default.
3504          */
3505         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3506         case GC_CLOCK_133_200:
3507         case GC_CLOCK_100_200:
3508                 return 200000;
3509         case GC_CLOCK_166_250:
3510                 return 250000;
3511         case GC_CLOCK_100_133:
3512                 return 133000;
3513         }
3514
3515         /* Shouldn't happen */
3516         return 0;
3517 }
3518
3519 static int i830_get_display_clock_speed(struct drm_device *dev)
3520 {
3521         return 133000;
3522 }
3523
3524 struct fdi_m_n {
3525         u32        tu;
3526         u32        gmch_m;
3527         u32        gmch_n;
3528         u32        link_m;
3529         u32        link_n;
3530 };
3531
3532 static void
3533 fdi_reduce_ratio(u32 *num, u32 *den)
3534 {
3535         while (*num > 0xffffff || *den > 0xffffff) {
3536                 *num >>= 1;
3537                 *den >>= 1;
3538         }
3539 }
3540
3541 static void
3542 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3543                      int link_clock, struct fdi_m_n *m_n)
3544 {
3545         m_n->tu = 64; /* default size */
3546
3547         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3548         m_n->gmch_m = bits_per_pixel * pixel_clock;
3549         m_n->gmch_n = link_clock * nlanes * 8;
3550         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3551
3552         m_n->link_m = pixel_clock;
3553         m_n->link_n = link_clock;
3554         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3555 }
3556
3557
3558 struct intel_watermark_params {
3559         unsigned long fifo_size;
3560         unsigned long max_wm;
3561         unsigned long default_wm;
3562         unsigned long guard_size;
3563         unsigned long cacheline_size;
3564 };
3565
3566 /* Pineview has different values for various configs */
3567 static const struct intel_watermark_params pineview_display_wm = {
3568         PINEVIEW_DISPLAY_FIFO,
3569         PINEVIEW_MAX_WM,
3570         PINEVIEW_DFT_WM,
3571         PINEVIEW_GUARD_WM,
3572         PINEVIEW_FIFO_LINE_SIZE
3573 };
3574 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3575         PINEVIEW_DISPLAY_FIFO,
3576         PINEVIEW_MAX_WM,
3577         PINEVIEW_DFT_HPLLOFF_WM,
3578         PINEVIEW_GUARD_WM,
3579         PINEVIEW_FIFO_LINE_SIZE
3580 };
3581 static const struct intel_watermark_params pineview_cursor_wm = {
3582         PINEVIEW_CURSOR_FIFO,
3583         PINEVIEW_CURSOR_MAX_WM,
3584         PINEVIEW_CURSOR_DFT_WM,
3585         PINEVIEW_CURSOR_GUARD_WM,
3586         PINEVIEW_FIFO_LINE_SIZE,
3587 };
3588 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3589         PINEVIEW_CURSOR_FIFO,
3590         PINEVIEW_CURSOR_MAX_WM,
3591         PINEVIEW_CURSOR_DFT_WM,
3592         PINEVIEW_CURSOR_GUARD_WM,
3593         PINEVIEW_FIFO_LINE_SIZE
3594 };
3595 static const struct intel_watermark_params g4x_wm_info = {
3596         G4X_FIFO_SIZE,
3597         G4X_MAX_WM,
3598         G4X_MAX_WM,
3599         2,
3600         G4X_FIFO_LINE_SIZE,
3601 };
3602 static const struct intel_watermark_params g4x_cursor_wm_info = {
3603         I965_CURSOR_FIFO,
3604         I965_CURSOR_MAX_WM,
3605         I965_CURSOR_DFT_WM,
3606         2,
3607         G4X_FIFO_LINE_SIZE,
3608 };
3609 static const struct intel_watermark_params i965_cursor_wm_info = {
3610         I965_CURSOR_FIFO,
3611         I965_CURSOR_MAX_WM,
3612         I965_CURSOR_DFT_WM,
3613         2,
3614         I915_FIFO_LINE_SIZE,
3615 };
3616 static const struct intel_watermark_params i945_wm_info = {
3617         I945_FIFO_SIZE,
3618         I915_MAX_WM,
3619         1,
3620         2,
3621         I915_FIFO_LINE_SIZE
3622 };
3623 static const struct intel_watermark_params i915_wm_info = {
3624         I915_FIFO_SIZE,
3625         I915_MAX_WM,
3626         1,
3627         2,
3628         I915_FIFO_LINE_SIZE
3629 };
3630 static const struct intel_watermark_params i855_wm_info = {
3631         I855GM_FIFO_SIZE,
3632         I915_MAX_WM,
3633         1,
3634         2,
3635         I830_FIFO_LINE_SIZE
3636 };
3637 static const struct intel_watermark_params i830_wm_info = {
3638         I830_FIFO_SIZE,
3639         I915_MAX_WM,
3640         1,
3641         2,
3642         I830_FIFO_LINE_SIZE
3643 };
3644
3645 static const struct intel_watermark_params ironlake_display_wm_info = {
3646         ILK_DISPLAY_FIFO,
3647         ILK_DISPLAY_MAXWM,
3648         ILK_DISPLAY_DFTWM,
3649         2,
3650         ILK_FIFO_LINE_SIZE
3651 };
3652 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3653         ILK_CURSOR_FIFO,
3654         ILK_CURSOR_MAXWM,
3655         ILK_CURSOR_DFTWM,
3656         2,
3657         ILK_FIFO_LINE_SIZE
3658 };
3659 static const struct intel_watermark_params ironlake_display_srwm_info = {
3660         ILK_DISPLAY_SR_FIFO,
3661         ILK_DISPLAY_MAX_SRWM,
3662         ILK_DISPLAY_DFT_SRWM,
3663         2,
3664         ILK_FIFO_LINE_SIZE
3665 };
3666 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3667         ILK_CURSOR_SR_FIFO,
3668         ILK_CURSOR_MAX_SRWM,
3669         ILK_CURSOR_DFT_SRWM,
3670         2,
3671         ILK_FIFO_LINE_SIZE
3672 };
3673
3674 static const struct intel_watermark_params sandybridge_display_wm_info = {
3675         SNB_DISPLAY_FIFO,
3676         SNB_DISPLAY_MAXWM,
3677         SNB_DISPLAY_DFTWM,
3678         2,
3679         SNB_FIFO_LINE_SIZE
3680 };
3681 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3682         SNB_CURSOR_FIFO,
3683         SNB_CURSOR_MAXWM,
3684         SNB_CURSOR_DFTWM,
3685         2,
3686         SNB_FIFO_LINE_SIZE
3687 };
3688 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3689         SNB_DISPLAY_SR_FIFO,
3690         SNB_DISPLAY_MAX_SRWM,
3691         SNB_DISPLAY_DFT_SRWM,
3692         2,
3693         SNB_FIFO_LINE_SIZE
3694 };
3695 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3696         SNB_CURSOR_SR_FIFO,
3697         SNB_CURSOR_MAX_SRWM,
3698         SNB_CURSOR_DFT_SRWM,
3699         2,
3700         SNB_FIFO_LINE_SIZE
3701 };
3702
3703
3704 /**
3705  * intel_calculate_wm - calculate watermark level
3706  * @clock_in_khz: pixel clock
3707  * @wm: chip FIFO params
3708  * @pixel_size: display pixel size
3709  * @latency_ns: memory latency for the platform
3710  *
3711  * Calculate the watermark level (the level at which the display plane will
3712  * start fetching from memory again).  Each chip has a different display
3713  * FIFO size and allocation, so the caller needs to figure that out and pass
3714  * in the correct intel_watermark_params structure.
3715  *
3716  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3717  * on the pixel size.  When it reaches the watermark level, it'll start
3718  * fetching FIFO line sized based chunks from memory until the FIFO fills
3719  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3720  * will occur, and a display engine hang could result.
3721  */
3722 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3723                                         const struct intel_watermark_params *wm,
3724                                         int fifo_size,
3725                                         int pixel_size,
3726                                         unsigned long latency_ns)
3727 {
3728         long entries_required, wm_size;
3729
3730         /*
3731          * Note: we need to make sure we don't overflow for various clock &
3732          * latency values.
3733          * clocks go from a few thousand to several hundred thousand.
3734          * latency is usually a few thousand
3735          */
3736         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3737                 1000;
3738         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3739
3740         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3741
3742         wm_size = fifo_size - (entries_required + wm->guard_size);
3743
3744         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3745
3746         /* Don't promote wm_size to unsigned... */
3747         if (wm_size > (long)wm->max_wm)
3748                 wm_size = wm->max_wm;
3749         if (wm_size <= 0)
3750                 wm_size = wm->default_wm;
3751         return wm_size;
3752 }
3753
3754 struct cxsr_latency {
3755         int is_desktop;
3756         int is_ddr3;
3757         unsigned long fsb_freq;
3758         unsigned long mem_freq;
3759         unsigned long display_sr;
3760         unsigned long display_hpll_disable;
3761         unsigned long cursor_sr;
3762         unsigned long cursor_hpll_disable;
3763 };
3764
3765 static const struct cxsr_latency cxsr_latency_table[] = {
3766         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3767         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3768         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3769         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3770         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3771
3772         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3773         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3774         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3775         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3776         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3777
3778         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3779         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3780         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3781         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3782         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3783
3784         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3785         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3786         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3787         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3788         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3789
3790         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3791         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3792         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3793         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3794         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3795
3796         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3797         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3798         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3799         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3800         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3801 };
3802
3803 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3804                                                          int is_ddr3,
3805                                                          int fsb,
3806                                                          int mem)
3807 {
3808         const struct cxsr_latency *latency;
3809         int i;
3810
3811         if (fsb == 0 || mem == 0)
3812                 return NULL;
3813
3814         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3815                 latency = &cxsr_latency_table[i];
3816                 if (is_desktop == latency->is_desktop &&
3817                     is_ddr3 == latency->is_ddr3 &&
3818                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3819                         return latency;
3820         }
3821
3822         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3823
3824         return NULL;
3825 }
3826
3827 static void pineview_disable_cxsr(struct drm_device *dev)
3828 {
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831         /* deactivate cxsr */
3832         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3833 }
3834
3835 /*
3836  * Latency for FIFO fetches is dependent on several factors:
3837  *   - memory configuration (speed, channels)
3838  *   - chipset
3839  *   - current MCH state
3840  * It can be fairly high in some situations, so here we assume a fairly
3841  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3842  * set this value too high, the FIFO will fetch frequently to stay full)
3843  * and power consumption (set it too low to save power and we might see
3844  * FIFO underruns and display "flicker").
3845  *
3846  * A value of 5us seems to be a good balance; safe for very low end
3847  * platforms but not overly aggressive on lower latency configs.
3848  */
3849 static const int latency_ns = 5000;
3850
3851 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3852 {
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         uint32_t dsparb = I915_READ(DSPARB);
3855         int size;
3856
3857         size = dsparb & 0x7f;
3858         if (plane)
3859                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3860
3861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3862                       plane ? "B" : "A", size);
3863
3864         return size;
3865 }
3866
3867 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3868 {
3869         struct drm_i915_private *dev_priv = dev->dev_private;
3870         uint32_t dsparb = I915_READ(DSPARB);
3871         int size;
3872
3873         size = dsparb & 0x1ff;
3874         if (plane)
3875                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3876         size >>= 1; /* Convert to cachelines */
3877
3878         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3879                       plane ? "B" : "A", size);
3880
3881         return size;
3882 }
3883
3884 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3885 {
3886         struct drm_i915_private *dev_priv = dev->dev_private;
3887         uint32_t dsparb = I915_READ(DSPARB);
3888         int size;
3889
3890         size = dsparb & 0x7f;
3891         size >>= 2; /* Convert to cachelines */
3892
3893         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3894                       plane ? "B" : "A",
3895                       size);
3896
3897         return size;
3898 }
3899
3900 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3901 {
3902         struct drm_i915_private *dev_priv = dev->dev_private;
3903         uint32_t dsparb = I915_READ(DSPARB);
3904         int size;
3905
3906         size = dsparb & 0x7f;
3907         size >>= 1; /* Convert to cachelines */
3908
3909         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3910                       plane ? "B" : "A", size);
3911
3912         return size;
3913 }
3914
3915 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3916 {
3917         struct drm_crtc *crtc, *enabled = NULL;
3918
3919         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3920                 if (crtc->enabled && crtc->fb) {
3921                         if (enabled)
3922                                 return NULL;
3923                         enabled = crtc;
3924                 }
3925         }
3926
3927         return enabled;
3928 }
3929
3930 static void pineview_update_wm(struct drm_device *dev)
3931 {
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         struct drm_crtc *crtc;
3934         const struct cxsr_latency *latency;
3935         u32 reg;
3936         unsigned long wm;
3937
3938         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3939                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3940         if (!latency) {
3941                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3942                 pineview_disable_cxsr(dev);
3943                 return;
3944         }
3945
3946         crtc = single_enabled_crtc(dev);
3947         if (crtc) {
3948                 int clock = crtc->mode.clock;
3949                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3950
3951                 /* Display SR */
3952                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3953                                         pineview_display_wm.fifo_size,
3954                                         pixel_size, latency->display_sr);
3955                 reg = I915_READ(DSPFW1);
3956                 reg &= ~DSPFW_SR_MASK;
3957                 reg |= wm << DSPFW_SR_SHIFT;
3958                 I915_WRITE(DSPFW1, reg);
3959                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3960
3961                 /* cursor SR */
3962                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3963                                         pineview_display_wm.fifo_size,
3964                                         pixel_size, latency->cursor_sr);
3965                 reg = I915_READ(DSPFW3);
3966                 reg &= ~DSPFW_CURSOR_SR_MASK;
3967                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3968                 I915_WRITE(DSPFW3, reg);
3969
3970                 /* Display HPLL off SR */
3971                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3972                                         pineview_display_hplloff_wm.fifo_size,
3973                                         pixel_size, latency->display_hpll_disable);
3974                 reg = I915_READ(DSPFW3);
3975                 reg &= ~DSPFW_HPLL_SR_MASK;
3976                 reg |= wm & DSPFW_HPLL_SR_MASK;
3977                 I915_WRITE(DSPFW3, reg);
3978
3979                 /* cursor HPLL off SR */
3980                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3981                                         pineview_display_hplloff_wm.fifo_size,
3982                                         pixel_size, latency->cursor_hpll_disable);
3983                 reg = I915_READ(DSPFW3);
3984                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3985                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3986                 I915_WRITE(DSPFW3, reg);
3987                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3988
3989                 /* activate cxsr */
3990                 I915_WRITE(DSPFW3,
3991                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3992                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3993         } else {
3994                 pineview_disable_cxsr(dev);
3995                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3996         }
3997 }
3998
3999 static bool g4x_compute_wm0(struct drm_device *dev,
4000                             int plane,
4001                             const struct intel_watermark_params *display,
4002                             int display_latency_ns,
4003                             const struct intel_watermark_params *cursor,
4004                             int cursor_latency_ns,
4005                             int *plane_wm,
4006                             int *cursor_wm)
4007 {
4008         struct drm_crtc *crtc;
4009         int htotal, hdisplay, clock, pixel_size;
4010         int line_time_us, line_count;
4011         int entries, tlb_miss;
4012
4013         crtc = intel_get_crtc_for_plane(dev, plane);
4014         if (crtc->fb == NULL || !crtc->enabled) {
4015                 *cursor_wm = cursor->guard_size;
4016                 *plane_wm = display->guard_size;
4017                 return false;
4018         }
4019
4020         htotal = crtc->mode.htotal;
4021         hdisplay = crtc->mode.hdisplay;
4022         clock = crtc->mode.clock;
4023         pixel_size = crtc->fb->bits_per_pixel / 8;
4024
4025         /* Use the small buffer method to calculate plane watermark */
4026         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4027         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4028         if (tlb_miss > 0)
4029                 entries += tlb_miss;
4030         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4031         *plane_wm = entries + display->guard_size;
4032         if (*plane_wm > (int)display->max_wm)
4033                 *plane_wm = display->max_wm;
4034
4035         /* Use the large buffer method to calculate cursor watermark */
4036         line_time_us = ((htotal * 1000) / clock);
4037         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4038         entries = line_count * 64 * pixel_size;
4039         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4040         if (tlb_miss > 0)
4041                 entries += tlb_miss;
4042         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4043         *cursor_wm = entries + cursor->guard_size;
4044         if (*cursor_wm > (int)cursor->max_wm)
4045                 *cursor_wm = (int)cursor->max_wm;
4046
4047         return true;
4048 }
4049
4050 /*
4051  * Check the wm result.
4052  *
4053  * If any calculated watermark values is larger than the maximum value that
4054  * can be programmed into the associated watermark register, that watermark
4055  * must be disabled.
4056  */
4057 static bool g4x_check_srwm(struct drm_device *dev,
4058                            int display_wm, int cursor_wm,
4059                            const struct intel_watermark_params *display,
4060                            const struct intel_watermark_params *cursor)
4061 {
4062         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4063                       display_wm, cursor_wm);
4064
4065         if (display_wm > display->max_wm) {
4066                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4067                               display_wm, display->max_wm);
4068                 return false;
4069         }
4070
4071         if (cursor_wm > cursor->max_wm) {
4072                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4073                               cursor_wm, cursor->max_wm);
4074                 return false;
4075         }
4076
4077         if (!(display_wm || cursor_wm)) {
4078                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4079                 return false;
4080         }
4081
4082         return true;
4083 }
4084
4085 static bool g4x_compute_srwm(struct drm_device *dev,
4086                              int plane,
4087                              int latency_ns,
4088                              const struct intel_watermark_params *display,
4089                              const struct intel_watermark_params *cursor,
4090                              int *display_wm, int *cursor_wm)
4091 {
4092         struct drm_crtc *crtc;
4093         int hdisplay, htotal, pixel_size, clock;
4094         unsigned long line_time_us;
4095         int line_count, line_size;
4096         int small, large;
4097         int entries;
4098
4099         if (!latency_ns) {
4100                 *display_wm = *cursor_wm = 0;
4101                 return false;
4102         }
4103
4104         crtc = intel_get_crtc_for_plane(dev, plane);
4105         hdisplay = crtc->mode.hdisplay;
4106         htotal = crtc->mode.htotal;
4107         clock = crtc->mode.clock;
4108         pixel_size = crtc->fb->bits_per_pixel / 8;
4109
4110         line_time_us = (htotal * 1000) / clock;
4111         line_count = (latency_ns / line_time_us + 1000) / 1000;
4112         line_size = hdisplay * pixel_size;
4113
4114         /* Use the minimum of the small and large buffer method for primary */
4115         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4116         large = line_count * line_size;
4117
4118         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4119         *display_wm = entries + display->guard_size;
4120
4121         /* calculate the self-refresh watermark for display cursor */
4122         entries = line_count * pixel_size * 64;
4123         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4124         *cursor_wm = entries + cursor->guard_size;
4125
4126         return g4x_check_srwm(dev,
4127                               *display_wm, *cursor_wm,
4128                               display, cursor);
4129 }
4130
4131 #define single_plane_enabled(mask) is_power_of_2(mask)
4132
4133 static void g4x_update_wm(struct drm_device *dev)
4134 {
4135         static const int sr_latency_ns = 12000;
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4138         int plane_sr, cursor_sr;
4139         unsigned int enabled = 0;
4140
4141         if (g4x_compute_wm0(dev, 0,
4142                             &g4x_wm_info, latency_ns,
4143                             &g4x_cursor_wm_info, latency_ns,
4144                             &planea_wm, &cursora_wm))
4145                 enabled |= 1;
4146
4147         if (g4x_compute_wm0(dev, 1,
4148                             &g4x_wm_info, latency_ns,
4149                             &g4x_cursor_wm_info, latency_ns,
4150                             &planeb_wm, &cursorb_wm))
4151                 enabled |= 2;
4152
4153         plane_sr = cursor_sr = 0;
4154         if (single_plane_enabled(enabled) &&
4155             g4x_compute_srwm(dev, ffs(enabled) - 1,
4156                              sr_latency_ns,
4157                              &g4x_wm_info,
4158                              &g4x_cursor_wm_info,
4159                              &plane_sr, &cursor_sr))
4160                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4161         else
4162                 I915_WRITE(FW_BLC_SELF,
4163                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4164
4165         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4166                       planea_wm, cursora_wm,
4167                       planeb_wm, cursorb_wm,
4168                       plane_sr, cursor_sr);
4169
4170         I915_WRITE(DSPFW1,
4171                    (plane_sr << DSPFW_SR_SHIFT) |
4172                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4173                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4174                    planea_wm);
4175         I915_WRITE(DSPFW2,
4176                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4177                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4178         /* HPLL off in SR has some issues on G4x... disable it */
4179         I915_WRITE(DSPFW3,
4180                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4181                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4182 }
4183
4184 static void i965_update_wm(struct drm_device *dev)
4185 {
4186         struct drm_i915_private *dev_priv = dev->dev_private;
4187         struct drm_crtc *crtc;
4188         int srwm = 1;
4189         int cursor_sr = 16;
4190
4191         /* Calc sr entries for one plane configs */
4192         crtc = single_enabled_crtc(dev);
4193         if (crtc) {
4194                 /* self-refresh has much higher latency */
4195                 static const int sr_latency_ns = 12000;
4196                 int clock = crtc->mode.clock;
4197                 int htotal = crtc->mode.htotal;
4198                 int hdisplay = crtc->mode.hdisplay;
4199                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4200                 unsigned long line_time_us;
4201                 int entries;
4202
4203                 line_time_us = ((htotal * 1000) / clock);
4204
4205                 /* Use ns/us then divide to preserve precision */
4206                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4207                         pixel_size * hdisplay;
4208                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4209                 srwm = I965_FIFO_SIZE - entries;
4210                 if (srwm < 0)
4211                         srwm = 1;
4212                 srwm &= 0x1ff;
4213                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4214                               entries, srwm);
4215
4216                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4217                         pixel_size * 64;
4218                 entries = DIV_ROUND_UP(entries,
4219                                           i965_cursor_wm_info.cacheline_size);
4220                 cursor_sr = i965_cursor_wm_info.fifo_size -
4221                         (entries + i965_cursor_wm_info.guard_size);
4222
4223                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4224                         cursor_sr = i965_cursor_wm_info.max_wm;
4225
4226                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4227                               "cursor %d\n", srwm, cursor_sr);
4228
4229                 if (IS_CRESTLINE(dev))
4230                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4231         } else {
4232                 /* Turn off self refresh if both pipes are enabled */
4233                 if (IS_CRESTLINE(dev))
4234                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4235                                    & ~FW_BLC_SELF_EN);
4236         }
4237
4238         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4239                       srwm);
4240
4241         /* 965 has limitations... */
4242         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4243                    (8 << 16) | (8 << 8) | (8 << 0));
4244         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4245         /* update cursor SR watermark */
4246         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4247 }
4248
4249 static void i9xx_update_wm(struct drm_device *dev)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         const struct intel_watermark_params *wm_info;
4253         uint32_t fwater_lo;
4254         uint32_t fwater_hi;
4255         int cwm, srwm = 1;
4256         int fifo_size;
4257         int planea_wm, planeb_wm;
4258         struct drm_crtc *crtc, *enabled = NULL;
4259
4260         if (IS_I945GM(dev))
4261                 wm_info = &i945_wm_info;
4262         else if (!IS_GEN2(dev))
4263                 wm_info = &i915_wm_info;
4264         else
4265                 wm_info = &i855_wm_info;
4266
4267         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4268         crtc = intel_get_crtc_for_plane(dev, 0);
4269         if (crtc->enabled && crtc->fb) {
4270                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4271                                                wm_info, fifo_size,
4272                                                crtc->fb->bits_per_pixel / 8,
4273                                                latency_ns);
4274                 enabled = crtc;
4275         } else
4276                 planea_wm = fifo_size - wm_info->guard_size;
4277
4278         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4279         crtc = intel_get_crtc_for_plane(dev, 1);
4280         if (crtc->enabled && crtc->fb) {
4281                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4282                                                wm_info, fifo_size,
4283                                                crtc->fb->bits_per_pixel / 8,
4284                                                latency_ns);
4285                 if (enabled == NULL)
4286                         enabled = crtc;
4287                 else
4288                         enabled = NULL;
4289         } else
4290                 planeb_wm = fifo_size - wm_info->guard_size;
4291
4292         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4293
4294         /*
4295          * Overlay gets an aggressive default since video jitter is bad.
4296          */
4297         cwm = 2;
4298
4299         /* Play safe and disable self-refresh before adjusting watermarks. */
4300         if (IS_I945G(dev) || IS_I945GM(dev))
4301                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4302         else if (IS_I915GM(dev))
4303                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4304
4305         /* Calc sr entries for one plane configs */
4306         if (HAS_FW_BLC(dev) && enabled) {
4307                 /* self-refresh has much higher latency */
4308                 static const int sr_latency_ns = 6000;
4309                 int clock = enabled->mode.clock;
4310                 int htotal = enabled->mode.htotal;
4311                 int hdisplay = enabled->mode.hdisplay;
4312                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4313                 unsigned long line_time_us;
4314                 int entries;
4315
4316                 line_time_us = (htotal * 1000) / clock;
4317
4318                 /* Use ns/us then divide to preserve precision */
4319                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4320                         pixel_size * hdisplay;
4321                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4322                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4323                 srwm = wm_info->fifo_size - entries;
4324                 if (srwm < 0)
4325                         srwm = 1;
4326
4327                 if (IS_I945G(dev) || IS_I945GM(dev))
4328                         I915_WRITE(FW_BLC_SELF,
4329                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4330                 else if (IS_I915GM(dev))
4331                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4332         }
4333
4334         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4335                       planea_wm, planeb_wm, cwm, srwm);
4336
4337         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4338         fwater_hi = (cwm & 0x1f);
4339
4340         /* Set request length to 8 cachelines per fetch */
4341         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4342         fwater_hi = fwater_hi | (1 << 8);
4343
4344         I915_WRITE(FW_BLC, fwater_lo);
4345         I915_WRITE(FW_BLC2, fwater_hi);
4346
4347         if (HAS_FW_BLC(dev)) {
4348                 if (enabled) {
4349                         if (IS_I945G(dev) || IS_I945GM(dev))
4350                                 I915_WRITE(FW_BLC_SELF,
4351                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4352                         else if (IS_I915GM(dev))
4353                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4354                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4355                 } else
4356                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4357         }
4358 }
4359
4360 static void i830_update_wm(struct drm_device *dev)
4361 {
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         struct drm_crtc *crtc;
4364         uint32_t fwater_lo;
4365         int planea_wm;
4366
4367         crtc = single_enabled_crtc(dev);
4368         if (crtc == NULL)
4369                 return;
4370
4371         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4372                                        dev_priv->display.get_fifo_size(dev, 0),
4373                                        crtc->fb->bits_per_pixel / 8,
4374                                        latency_ns);
4375         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4376         fwater_lo |= (3<<8) | planea_wm;
4377
4378         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4379
4380         I915_WRITE(FW_BLC, fwater_lo);
4381 }
4382
4383 #define ILK_LP0_PLANE_LATENCY           700
4384 #define ILK_LP0_CURSOR_LATENCY          1300
4385
4386 /*
4387  * Check the wm result.
4388  *
4389  * If any calculated watermark values is larger than the maximum value that
4390  * can be programmed into the associated watermark register, that watermark
4391  * must be disabled.
4392  */
4393 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4394                                 int fbc_wm, int display_wm, int cursor_wm,
4395                                 const struct intel_watermark_params *display,
4396                                 const struct intel_watermark_params *cursor)
4397 {
4398         struct drm_i915_private *dev_priv = dev->dev_private;
4399
4400         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4401                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4402
4403         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4404                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4405                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4406
4407                 /* fbc has it's own way to disable FBC WM */
4408                 I915_WRITE(DISP_ARB_CTL,
4409                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4410                 return false;
4411         }
4412
4413         if (display_wm > display->max_wm) {
4414                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4415                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4416                 return false;
4417         }
4418
4419         if (cursor_wm > cursor->max_wm) {
4420                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4421                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4422                 return false;
4423         }
4424
4425         if (!(fbc_wm || display_wm || cursor_wm)) {
4426                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4427                 return false;
4428         }
4429
4430         return true;
4431 }
4432
4433 /*
4434  * Compute watermark values of WM[1-3],
4435  */
4436 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4437                                   int latency_ns,
4438                                   const struct intel_watermark_params *display,
4439                                   const struct intel_watermark_params *cursor,
4440                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4441 {
4442         struct drm_crtc *crtc;
4443         unsigned long line_time_us;
4444         int hdisplay, htotal, pixel_size, clock;
4445         int line_count, line_size;
4446         int small, large;
4447         int entries;
4448
4449         if (!latency_ns) {
4450                 *fbc_wm = *display_wm = *cursor_wm = 0;
4451                 return false;
4452         }
4453
4454         crtc = intel_get_crtc_for_plane(dev, plane);
4455         hdisplay = crtc->mode.hdisplay;
4456         htotal = crtc->mode.htotal;
4457         clock = crtc->mode.clock;
4458         pixel_size = crtc->fb->bits_per_pixel / 8;
4459
4460         line_time_us = (htotal * 1000) / clock;
4461         line_count = (latency_ns / line_time_us + 1000) / 1000;
4462         line_size = hdisplay * pixel_size;
4463
4464         /* Use the minimum of the small and large buffer method for primary */
4465         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4466         large = line_count * line_size;
4467
4468         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4469         *display_wm = entries + display->guard_size;
4470
4471         /*
4472          * Spec says:
4473          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4474          */
4475         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4476
4477         /* calculate the self-refresh watermark for display cursor */
4478         entries = line_count * pixel_size * 64;
4479         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4480         *cursor_wm = entries + cursor->guard_size;
4481
4482         return ironlake_check_srwm(dev, level,
4483                                    *fbc_wm, *display_wm, *cursor_wm,
4484                                    display, cursor);
4485 }
4486
4487 static void ironlake_update_wm(struct drm_device *dev)
4488 {
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int fbc_wm, plane_wm, cursor_wm;
4491         unsigned int enabled;
4492
4493         enabled = 0;
4494         if (g4x_compute_wm0(dev, 0,
4495                             &ironlake_display_wm_info,
4496                             ILK_LP0_PLANE_LATENCY,
4497                             &ironlake_cursor_wm_info,
4498                             ILK_LP0_CURSOR_LATENCY,
4499                             &plane_wm, &cursor_wm)) {
4500                 I915_WRITE(WM0_PIPEA_ILK,
4501                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4502                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4503                               " plane %d, " "cursor: %d\n",
4504                               plane_wm, cursor_wm);
4505                 enabled |= 1;
4506         }
4507
4508         if (g4x_compute_wm0(dev, 1,
4509                             &ironlake_display_wm_info,
4510                             ILK_LP0_PLANE_LATENCY,
4511                             &ironlake_cursor_wm_info,
4512                             ILK_LP0_CURSOR_LATENCY,
4513                             &plane_wm, &cursor_wm)) {
4514                 I915_WRITE(WM0_PIPEB_ILK,
4515                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4516                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4517                               " plane %d, cursor: %d\n",
4518                               plane_wm, cursor_wm);
4519                 enabled |= 2;
4520         }
4521
4522         /*
4523          * Calculate and update the self-refresh watermark only when one
4524          * display plane is used.
4525          */
4526         I915_WRITE(WM3_LP_ILK, 0);
4527         I915_WRITE(WM2_LP_ILK, 0);
4528         I915_WRITE(WM1_LP_ILK, 0);
4529
4530         if (!single_plane_enabled(enabled))
4531                 return;
4532         enabled = ffs(enabled) - 1;
4533
4534         /* WM1 */
4535         if (!ironlake_compute_srwm(dev, 1, enabled,
4536                                    ILK_READ_WM1_LATENCY() * 500,
4537                                    &ironlake_display_srwm_info,
4538                                    &ironlake_cursor_srwm_info,
4539                                    &fbc_wm, &plane_wm, &cursor_wm))
4540                 return;
4541
4542         I915_WRITE(WM1_LP_ILK,
4543                    WM1_LP_SR_EN |
4544                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4545                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4546                    (plane_wm << WM1_LP_SR_SHIFT) |
4547                    cursor_wm);
4548
4549         /* WM2 */
4550         if (!ironlake_compute_srwm(dev, 2, enabled,
4551                                    ILK_READ_WM2_LATENCY() * 500,
4552                                    &ironlake_display_srwm_info,
4553                                    &ironlake_cursor_srwm_info,
4554                                    &fbc_wm, &plane_wm, &cursor_wm))
4555                 return;
4556
4557         I915_WRITE(WM2_LP_ILK,
4558                    WM2_LP_EN |
4559                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4560                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4561                    (plane_wm << WM1_LP_SR_SHIFT) |
4562                    cursor_wm);
4563
4564         /*
4565          * WM3 is unsupported on ILK, probably because we don't have latency
4566          * data for that power state
4567          */
4568 }
4569
4570 void sandybridge_update_wm(struct drm_device *dev)
4571 {
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4574         u32 val;
4575         int fbc_wm, plane_wm, cursor_wm;
4576         unsigned int enabled;
4577
4578         enabled = 0;
4579         if (g4x_compute_wm0(dev, 0,
4580                             &sandybridge_display_wm_info, latency,
4581                             &sandybridge_cursor_wm_info, latency,
4582                             &plane_wm, &cursor_wm)) {
4583                 val = I915_READ(WM0_PIPEA_ILK);
4584                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4585                 I915_WRITE(WM0_PIPEA_ILK, val |
4586                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4587                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4588                               " plane %d, " "cursor: %d\n",
4589                               plane_wm, cursor_wm);
4590                 enabled |= 1;
4591         }
4592
4593         if (g4x_compute_wm0(dev, 1,
4594                             &sandybridge_display_wm_info, latency,
4595                             &sandybridge_cursor_wm_info, latency,
4596                             &plane_wm, &cursor_wm)) {
4597                 val = I915_READ(WM0_PIPEB_ILK);
4598                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4599                 I915_WRITE(WM0_PIPEB_ILK, val |
4600                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4601                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4602                               " plane %d, cursor: %d\n",
4603                               plane_wm, cursor_wm);
4604                 enabled |= 2;
4605         }
4606
4607         /* IVB has 3 pipes */
4608         if (IS_IVYBRIDGE(dev) &&
4609             g4x_compute_wm0(dev, 2,
4610                             &sandybridge_display_wm_info, latency,
4611                             &sandybridge_cursor_wm_info, latency,
4612                             &plane_wm, &cursor_wm)) {
4613                 val = I915_READ(WM0_PIPEC_IVB);
4614                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615                 I915_WRITE(WM0_PIPEC_IVB, val |
4616                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4617                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4618                               " plane %d, cursor: %d\n",
4619                               plane_wm, cursor_wm);
4620                 enabled |= 3;
4621         }
4622
4623         /*
4624          * Calculate and update the self-refresh watermark only when one
4625          * display plane is used.
4626          *
4627          * SNB support 3 levels of watermark.
4628          *
4629          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4630          * and disabled in the descending order
4631          *
4632          */
4633         I915_WRITE(WM3_LP_ILK, 0);
4634         I915_WRITE(WM2_LP_ILK, 0);
4635         I915_WRITE(WM1_LP_ILK, 0);
4636
4637         if (!single_plane_enabled(enabled) ||
4638             dev_priv->sprite_scaling_enabled)
4639                 return;
4640         enabled = ffs(enabled) - 1;
4641
4642         /* WM1 */
4643         if (!ironlake_compute_srwm(dev, 1, enabled,
4644                                    SNB_READ_WM1_LATENCY() * 500,
4645                                    &sandybridge_display_srwm_info,
4646                                    &sandybridge_cursor_srwm_info,
4647                                    &fbc_wm, &plane_wm, &cursor_wm))
4648                 return;
4649
4650         I915_WRITE(WM1_LP_ILK,
4651                    WM1_LP_SR_EN |
4652                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4654                    (plane_wm << WM1_LP_SR_SHIFT) |
4655                    cursor_wm);
4656
4657         /* WM2 */
4658         if (!ironlake_compute_srwm(dev, 2, enabled,
4659                                    SNB_READ_WM2_LATENCY() * 500,
4660                                    &sandybridge_display_srwm_info,
4661                                    &sandybridge_cursor_srwm_info,
4662                                    &fbc_wm, &plane_wm, &cursor_wm))
4663                 return;
4664
4665         I915_WRITE(WM2_LP_ILK,
4666                    WM2_LP_EN |
4667                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4668                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4669                    (plane_wm << WM1_LP_SR_SHIFT) |
4670                    cursor_wm);
4671
4672         /* WM3 */
4673         if (!ironlake_compute_srwm(dev, 3, enabled,
4674                                    SNB_READ_WM3_LATENCY() * 500,
4675                                    &sandybridge_display_srwm_info,
4676                                    &sandybridge_cursor_srwm_info,
4677                                    &fbc_wm, &plane_wm, &cursor_wm))
4678                 return;
4679
4680         I915_WRITE(WM3_LP_ILK,
4681                    WM3_LP_EN |
4682                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4684                    (plane_wm << WM1_LP_SR_SHIFT) |
4685                    cursor_wm);
4686 }
4687
4688 static bool
4689 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4690                               uint32_t sprite_width, int pixel_size,
4691                               const struct intel_watermark_params *display,
4692                               int display_latency_ns, int *sprite_wm)
4693 {
4694         struct drm_crtc *crtc;
4695         int clock;
4696         int entries, tlb_miss;
4697
4698         crtc = intel_get_crtc_for_plane(dev, plane);
4699         if (crtc->fb == NULL || !crtc->enabled) {
4700                 *sprite_wm = display->guard_size;
4701                 return false;
4702         }
4703
4704         clock = crtc->mode.clock;
4705
4706         /* Use the small buffer method to calculate the sprite watermark */
4707         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4708         tlb_miss = display->fifo_size*display->cacheline_size -
4709                 sprite_width * 8;
4710         if (tlb_miss > 0)
4711                 entries += tlb_miss;
4712         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4713         *sprite_wm = entries + display->guard_size;
4714         if (*sprite_wm > (int)display->max_wm)
4715                 *sprite_wm = display->max_wm;
4716
4717         return true;
4718 }
4719
4720 static bool
4721 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4722                                 uint32_t sprite_width, int pixel_size,
4723                                 const struct intel_watermark_params *display,
4724                                 int latency_ns, int *sprite_wm)
4725 {
4726         struct drm_crtc *crtc;
4727         unsigned long line_time_us;
4728         int clock;
4729         int line_count, line_size;
4730         int small, large;
4731         int entries;
4732
4733         if (!latency_ns) {
4734                 *sprite_wm = 0;
4735                 return false;
4736         }
4737
4738         crtc = intel_get_crtc_for_plane(dev, plane);
4739         clock = crtc->mode.clock;
4740
4741         line_time_us = (sprite_width * 1000) / clock;
4742         line_count = (latency_ns / line_time_us + 1000) / 1000;
4743         line_size = sprite_width * pixel_size;
4744
4745         /* Use the minimum of the small and large buffer method for primary */
4746         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4747         large = line_count * line_size;
4748
4749         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4750         *sprite_wm = entries + display->guard_size;
4751
4752         return *sprite_wm > 0x3ff ? false : true;
4753 }
4754
4755 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4756                                          uint32_t sprite_width, int pixel_size)
4757 {
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4760         u32 val;
4761         int sprite_wm, reg;
4762         int ret;
4763
4764         switch (pipe) {
4765         case 0:
4766                 reg = WM0_PIPEA_ILK;
4767                 break;
4768         case 1:
4769                 reg = WM0_PIPEB_ILK;
4770                 break;
4771         case 2:
4772                 reg = WM0_PIPEC_IVB;
4773                 break;
4774         default:
4775                 return; /* bad pipe */
4776         }
4777
4778         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4779                                             &sandybridge_display_wm_info,
4780                                             latency, &sprite_wm);
4781         if (!ret) {
4782                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4783                               pipe);
4784                 return;
4785         }
4786
4787         val = I915_READ(reg);
4788         val &= ~WM0_PIPE_SPRITE_MASK;
4789         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4790         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4791
4792
4793         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4794                                               pixel_size,
4795                                               &sandybridge_display_srwm_info,
4796                                               SNB_READ_WM1_LATENCY() * 500,
4797                                               &sprite_wm);
4798         if (!ret) {
4799                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4800                               pipe);
4801                 return;
4802         }
4803         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4804
4805         /* Only IVB has two more LP watermarks for sprite */
4806         if (!IS_IVYBRIDGE(dev))
4807                 return;
4808
4809         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4810                                               pixel_size,
4811                                               &sandybridge_display_srwm_info,
4812                                               SNB_READ_WM2_LATENCY() * 500,
4813                                               &sprite_wm);
4814         if (!ret) {
4815                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4816                               pipe);
4817                 return;
4818         }
4819         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4820
4821         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4822                                               pixel_size,
4823                                               &sandybridge_display_srwm_info,
4824                                               SNB_READ_WM3_LATENCY() * 500,
4825                                               &sprite_wm);
4826         if (!ret) {
4827                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4828                               pipe);
4829                 return;
4830         }
4831         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4832 }
4833
4834 /**
4835  * intel_update_watermarks - update FIFO watermark values based on current modes
4836  *
4837  * Calculate watermark values for the various WM regs based on current mode
4838  * and plane configuration.
4839  *
4840  * There are several cases to deal with here:
4841  *   - normal (i.e. non-self-refresh)
4842  *   - self-refresh (SR) mode
4843  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4844  *   - lines are small relative to FIFO size (buffer can hold more than 2
4845  *     lines), so need to account for TLB latency
4846  *
4847  *   The normal calculation is:
4848  *     watermark = dotclock * bytes per pixel * latency
4849  *   where latency is platform & configuration dependent (we assume pessimal
4850  *   values here).
4851  *
4852  *   The SR calculation is:
4853  *     watermark = (trunc(latency/line time)+1) * surface width *
4854  *       bytes per pixel
4855  *   where
4856  *     line time = htotal / dotclock
4857  *     surface width = hdisplay for normal plane and 64 for cursor
4858  *   and latency is assumed to be high, as above.
4859  *
4860  * The final value programmed to the register should always be rounded up,
4861  * and include an extra 2 entries to account for clock crossings.
4862  *
4863  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4864  * to set the non-SR watermarks to 8.
4865  */
4866 static void intel_update_watermarks(struct drm_device *dev)
4867 {
4868         struct drm_i915_private *dev_priv = dev->dev_private;
4869
4870         if (dev_priv->display.update_wm)
4871                 dev_priv->display.update_wm(dev);
4872 }
4873
4874 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4875                                     uint32_t sprite_width, int pixel_size)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878
4879         if (dev_priv->display.update_sprite_wm)
4880                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4881                                                    pixel_size);
4882 }
4883
4884 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4885 {
4886         if (i915_panel_use_ssc >= 0)
4887                 return i915_panel_use_ssc != 0;
4888         return dev_priv->lvds_use_ssc
4889                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4890 }
4891
4892 /**
4893  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4894  * @crtc: CRTC structure
4895  * @mode: requested mode
4896  *
4897  * A pipe may be connected to one or more outputs.  Based on the depth of the
4898  * attached framebuffer, choose a good color depth to use on the pipe.
4899  *
4900  * If possible, match the pipe depth to the fb depth.  In some cases, this
4901  * isn't ideal, because the connected output supports a lesser or restricted
4902  * set of depths.  Resolve that here:
4903  *    LVDS typically supports only 6bpc, so clamp down in that case
4904  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4905  *    Displays may support a restricted set as well, check EDID and clamp as
4906  *      appropriate.
4907  *    DP may want to dither down to 6bpc to fit larger modes
4908  *
4909  * RETURNS:
4910  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4911  * true if they don't match).
4912  */
4913 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4914                                          unsigned int *pipe_bpp,
4915                                          struct drm_display_mode *mode)
4916 {
4917         struct drm_device *dev = crtc->dev;
4918         struct drm_i915_private *dev_priv = dev->dev_private;
4919         struct drm_encoder *encoder;
4920         struct drm_connector *connector;
4921         unsigned int display_bpc = UINT_MAX, bpc;
4922
4923         /* Walk the encoders & connectors on this crtc, get min bpc */
4924         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4925                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4926
4927                 if (encoder->crtc != crtc)
4928                         continue;
4929
4930                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4931                         unsigned int lvds_bpc;
4932
4933                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4934                             LVDS_A3_POWER_UP)
4935                                 lvds_bpc = 8;
4936                         else
4937                                 lvds_bpc = 6;
4938
4939                         if (lvds_bpc < display_bpc) {
4940                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4941                                 display_bpc = lvds_bpc;
4942                         }
4943                         continue;
4944                 }
4945
4946                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4947                         /* Use VBT settings if we have an eDP panel */
4948                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4949
4950                         if (edp_bpc < display_bpc) {
4951                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4952                                 display_bpc = edp_bpc;
4953                         }
4954                         continue;
4955                 }
4956
4957                 /* Not one of the known troublemakers, check the EDID */
4958                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4959                                     head) {
4960                         if (connector->encoder != encoder)
4961                                 continue;
4962
4963                         /* Don't use an invalid EDID bpc value */
4964                         if (connector->display_info.bpc &&
4965                             connector->display_info.bpc < display_bpc) {
4966                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4967                                 display_bpc = connector->display_info.bpc;
4968                         }
4969                 }
4970
4971                 /*
4972                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4973                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4974                  */
4975                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4976                         if (display_bpc > 8 && display_bpc < 12) {
4977                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4978                                 display_bpc = 12;
4979                         } else {
4980                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4981                                 display_bpc = 8;
4982                         }
4983                 }
4984         }
4985
4986         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4987                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4988                 display_bpc = 6;
4989         }
4990
4991         /*
4992          * We could just drive the pipe at the highest bpc all the time and
4993          * enable dithering as needed, but that costs bandwidth.  So choose
4994          * the minimum value that expresses the full color range of the fb but
4995          * also stays within the max display bpc discovered above.
4996          */
4997
4998         switch (crtc->fb->depth) {
4999         case 8:
5000                 bpc = 8; /* since we go through a colormap */
5001                 break;
5002         case 15:
5003         case 16:
5004                 bpc = 6; /* min is 18bpp */
5005                 break;
5006         case 24:
5007                 bpc = 8;
5008                 break;
5009         case 30:
5010                 bpc = 10;
5011                 break;
5012         case 48:
5013                 bpc = 12;
5014                 break;
5015         default:
5016                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5017                 bpc = min((unsigned int)8, display_bpc);
5018                 break;
5019         }
5020
5021         display_bpc = min(display_bpc, bpc);
5022
5023         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5024                       bpc, display_bpc);
5025
5026         *pipe_bpp = display_bpc * 3;
5027
5028         return display_bpc != bpc;
5029 }
5030
5031 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5032 {
5033         struct drm_device *dev = crtc->dev;
5034         struct drm_i915_private *dev_priv = dev->dev_private;
5035         int refclk;
5036
5037         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5038             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5039                 refclk = dev_priv->lvds_ssc_freq * 1000;
5040                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5041                               refclk / 1000);
5042         } else if (!IS_GEN2(dev)) {
5043                 refclk = 96000;
5044         } else {
5045                 refclk = 48000;
5046         }
5047
5048         return refclk;
5049 }
5050
5051 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5052                                       intel_clock_t *clock)
5053 {
5054         /* SDVO TV has fixed PLL values depend on its clock range,
5055            this mirrors vbios setting. */
5056         if (adjusted_mode->clock >= 100000
5057             && adjusted_mode->clock < 140500) {
5058                 clock->p1 = 2;
5059                 clock->p2 = 10;
5060                 clock->n = 3;
5061                 clock->m1 = 16;
5062                 clock->m2 = 8;
5063         } else if (adjusted_mode->clock >= 140500
5064                    && adjusted_mode->clock <= 200000) {
5065                 clock->p1 = 1;
5066                 clock->p2 = 10;
5067                 clock->n = 6;
5068                 clock->m1 = 12;
5069                 clock->m2 = 8;
5070         }
5071 }
5072
5073 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5074                                      intel_clock_t *clock,
5075                                      intel_clock_t *reduced_clock)
5076 {
5077         struct drm_device *dev = crtc->dev;
5078         struct drm_i915_private *dev_priv = dev->dev_private;
5079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080         int pipe = intel_crtc->pipe;
5081         u32 fp, fp2 = 0;
5082
5083         if (IS_PINEVIEW(dev)) {
5084                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5085                 if (reduced_clock)
5086                         fp2 = (1 << reduced_clock->n) << 16 |
5087                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5088         } else {
5089                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5090                 if (reduced_clock)
5091                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5092                                 reduced_clock->m2;
5093         }
5094
5095         I915_WRITE(FP0(pipe), fp);
5096
5097         intel_crtc->lowfreq_avail = false;
5098         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5099             reduced_clock && i915_powersave) {
5100                 I915_WRITE(FP1(pipe), fp2);
5101                 intel_crtc->lowfreq_avail = true;
5102         } else {
5103                 I915_WRITE(FP1(pipe), fp);
5104         }
5105 }
5106
5107 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5108                               struct drm_display_mode *mode,
5109                               struct drm_display_mode *adjusted_mode,
5110                               int x, int y,
5111                               struct drm_framebuffer *old_fb)
5112 {
5113         struct drm_device *dev = crtc->dev;
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5116         int pipe = intel_crtc->pipe;
5117         int plane = intel_crtc->plane;
5118         int refclk, num_connectors = 0;
5119         intel_clock_t clock, reduced_clock;
5120         u32 dpll, dspcntr, pipeconf, vsyncshift;
5121         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5122         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5123         struct drm_mode_config *mode_config = &dev->mode_config;
5124         struct intel_encoder *encoder;
5125         const intel_limit_t *limit;
5126         int ret;
5127         u32 temp;
5128         u32 lvds_sync = 0;
5129
5130         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5131                 if (encoder->base.crtc != crtc)
5132                         continue;
5133
5134                 switch (encoder->type) {
5135                 case INTEL_OUTPUT_LVDS:
5136                         is_lvds = true;
5137                         break;
5138                 case INTEL_OUTPUT_SDVO:
5139                 case INTEL_OUTPUT_HDMI:
5140                         is_sdvo = true;
5141                         if (encoder->needs_tv_clock)
5142                                 is_tv = true;
5143                         break;
5144                 case INTEL_OUTPUT_DVO:
5145                         is_dvo = true;
5146                         break;
5147                 case INTEL_OUTPUT_TVOUT:
5148                         is_tv = true;
5149                         break;
5150                 case INTEL_OUTPUT_ANALOG:
5151                         is_crt = true;
5152                         break;
5153                 case INTEL_OUTPUT_DISPLAYPORT:
5154                         is_dp = true;
5155                         break;
5156                 }
5157
5158                 num_connectors++;
5159         }
5160
5161         refclk = i9xx_get_refclk(crtc, num_connectors);
5162
5163         /*
5164          * Returns a set of divisors for the desired target clock with the given
5165          * refclk, or FALSE.  The returned values represent the clock equation:
5166          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5167          */
5168         limit = intel_limit(crtc, refclk);
5169         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5170                              &clock);
5171         if (!ok) {
5172                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5173                 return -EINVAL;
5174         }
5175
5176         /* Ensure that the cursor is valid for the new mode before changing... */
5177         intel_crtc_update_cursor(crtc, true);
5178
5179         if (is_lvds && dev_priv->lvds_downclock_avail) {
5180                 /*
5181                  * Ensure we match the reduced clock's P to the target clock.
5182                  * If the clocks don't match, we can't switch the display clock
5183                  * by using the FP0/FP1. In such case we will disable the LVDS
5184                  * downclock feature.
5185                 */
5186                 has_reduced_clock = limit->find_pll(limit, crtc,
5187                                                     dev_priv->lvds_downclock,
5188                                                     refclk,
5189                                                     &clock,
5190                                                     &reduced_clock);
5191         }
5192
5193         if (is_sdvo && is_tv)
5194                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5195
5196         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5197                                  &reduced_clock : NULL);
5198
5199         dpll = DPLL_VGA_MODE_DIS;
5200
5201         if (!IS_GEN2(dev)) {
5202                 if (is_lvds)
5203                         dpll |= DPLLB_MODE_LVDS;
5204                 else
5205                         dpll |= DPLLB_MODE_DAC_SERIAL;
5206                 if (is_sdvo) {
5207                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5208                         if (pixel_multiplier > 1) {
5209                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5210                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5211                         }
5212                         dpll |= DPLL_DVO_HIGH_SPEED;
5213                 }
5214                 if (is_dp)
5215                         dpll |= DPLL_DVO_HIGH_SPEED;
5216
5217                 /* compute bitmask from p1 value */
5218                 if (IS_PINEVIEW(dev))
5219                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5220                 else {
5221                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5222                         if (IS_G4X(dev) && has_reduced_clock)
5223                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5224                 }
5225                 switch (clock.p2) {
5226                 case 5:
5227                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5228                         break;
5229                 case 7:
5230                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5231                         break;
5232                 case 10:
5233                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5234                         break;
5235                 case 14:
5236                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5237                         break;
5238                 }
5239                 if (INTEL_INFO(dev)->gen >= 4)
5240                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5241         } else {
5242                 if (is_lvds) {
5243                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5244                 } else {
5245                         if (clock.p1 == 2)
5246                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5247                         else
5248                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5249                         if (clock.p2 == 4)
5250                                 dpll |= PLL_P2_DIVIDE_BY_4;
5251                 }
5252         }
5253
5254         if (is_sdvo && is_tv)
5255                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5256         else if (is_tv)
5257                 /* XXX: just matching BIOS for now */
5258                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5259                 dpll |= 3;
5260         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5261                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5262         else
5263                 dpll |= PLL_REF_INPUT_DREFCLK;
5264
5265         /* setup pipeconf */
5266         pipeconf = I915_READ(PIPECONF(pipe));
5267
5268         /* Set up the display plane register */
5269         dspcntr = DISPPLANE_GAMMA_ENABLE;
5270
5271         if (pipe == 0)
5272                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5273         else
5274                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5275
5276         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5277                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5278                  * core speed.
5279                  *
5280                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5281                  * pipe == 0 check?
5282                  */
5283                 if (mode->clock >
5284                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5285                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5286                 else
5287                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5288         }
5289
5290         /* default to 8bpc */
5291         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5292         if (is_dp) {
5293                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5294                         pipeconf |= PIPECONF_BPP_6 |
5295                                     PIPECONF_DITHER_EN |
5296                                     PIPECONF_DITHER_TYPE_SP;
5297                 }
5298         }
5299
5300         dpll |= DPLL_VCO_ENABLE;
5301
5302         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5303         drm_mode_debug_printmodeline(mode);
5304
5305         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5306
5307         POSTING_READ(DPLL(pipe));
5308         udelay(150);
5309
5310         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5311          * This is an exception to the general rule that mode_set doesn't turn
5312          * things on.
5313          */
5314         if (is_lvds) {
5315                 temp = I915_READ(LVDS);
5316                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5317                 if (pipe == 1) {
5318                         temp |= LVDS_PIPEB_SELECT;
5319                 } else {
5320                         temp &= ~LVDS_PIPEB_SELECT;
5321                 }
5322                 /* set the corresponsding LVDS_BORDER bit */
5323                 temp |= dev_priv->lvds_border_bits;
5324                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5325                  * set the DPLLs for dual-channel mode or not.
5326                  */
5327                 if (clock.p2 == 7)
5328                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5329                 else
5330                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5331
5332                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5333                  * appropriately here, but we need to look more thoroughly into how
5334                  * panels behave in the two modes.
5335                  */
5336                 /* set the dithering flag on LVDS as needed */
5337                 if (INTEL_INFO(dev)->gen >= 4) {
5338                         if (dev_priv->lvds_dither)
5339                                 temp |= LVDS_ENABLE_DITHER;
5340                         else
5341                                 temp &= ~LVDS_ENABLE_DITHER;
5342                 }
5343                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5344                         lvds_sync |= LVDS_HSYNC_POLARITY;
5345                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5346                         lvds_sync |= LVDS_VSYNC_POLARITY;
5347                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5348                     != lvds_sync) {
5349                         char flags[2] = "-+";
5350                         DRM_INFO("Changing LVDS panel from "
5351                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5352                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5353                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5354                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5355                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5356                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5357                         temp |= lvds_sync;
5358                 }
5359                 I915_WRITE(LVDS, temp);
5360         }
5361
5362         if (is_dp) {
5363                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5364         }
5365
5366         I915_WRITE(DPLL(pipe), dpll);
5367
5368         /* Wait for the clocks to stabilize. */
5369         POSTING_READ(DPLL(pipe));
5370         udelay(150);
5371
5372         if (INTEL_INFO(dev)->gen >= 4) {
5373                 temp = 0;
5374                 if (is_sdvo) {
5375                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5376                         if (temp > 1)
5377                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5378                         else
5379                                 temp = 0;
5380                 }
5381                 I915_WRITE(DPLL_MD(pipe), temp);
5382         } else {
5383                 /* The pixel multiplier can only be updated once the
5384                  * DPLL is enabled and the clocks are stable.
5385                  *
5386                  * So write it again.
5387                  */
5388                 I915_WRITE(DPLL(pipe), dpll);
5389         }
5390
5391         if (HAS_PIPE_CXSR(dev)) {
5392                 if (intel_crtc->lowfreq_avail) {
5393                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5394                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5395                 } else {
5396                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5397                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5398                 }
5399         }
5400
5401         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5402         if (!IS_GEN2(dev) &&
5403             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5404                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5405                 /* the chip adds 2 halflines automatically */
5406                 adjusted_mode->crtc_vtotal -= 1;
5407                 adjusted_mode->crtc_vblank_end -= 1;
5408                 vsyncshift = adjusted_mode->crtc_hsync_start
5409                              - adjusted_mode->crtc_htotal/2;
5410         } else {
5411                 pipeconf |= PIPECONF_PROGRESSIVE;
5412                 vsyncshift = 0;
5413         }
5414
5415         if (!IS_GEN3(dev))
5416                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5417
5418         I915_WRITE(HTOTAL(pipe),
5419                    (adjusted_mode->crtc_hdisplay - 1) |
5420                    ((adjusted_mode->crtc_htotal - 1) << 16));
5421         I915_WRITE(HBLANK(pipe),
5422                    (adjusted_mode->crtc_hblank_start - 1) |
5423                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5424         I915_WRITE(HSYNC(pipe),
5425                    (adjusted_mode->crtc_hsync_start - 1) |
5426                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5427
5428         I915_WRITE(VTOTAL(pipe),
5429                    (adjusted_mode->crtc_vdisplay - 1) |
5430                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5431         I915_WRITE(VBLANK(pipe),
5432                    (adjusted_mode->crtc_vblank_start - 1) |
5433                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5434         I915_WRITE(VSYNC(pipe),
5435                    (adjusted_mode->crtc_vsync_start - 1) |
5436                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5437
5438         /* pipesrc and dspsize control the size that is scaled from,
5439          * which should always be the user's requested size.
5440          */
5441         I915_WRITE(DSPSIZE(plane),
5442                    ((mode->vdisplay - 1) << 16) |
5443                    (mode->hdisplay - 1));
5444         I915_WRITE(DSPPOS(plane), 0);
5445         I915_WRITE(PIPESRC(pipe),
5446                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5447
5448         I915_WRITE(PIPECONF(pipe), pipeconf);
5449         POSTING_READ(PIPECONF(pipe));
5450         intel_enable_pipe(dev_priv, pipe, false);
5451
5452         intel_wait_for_vblank(dev, pipe);
5453
5454         I915_WRITE(DSPCNTR(plane), dspcntr);
5455         POSTING_READ(DSPCNTR(plane));
5456         intel_enable_plane(dev_priv, plane, pipe);
5457
5458         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5459
5460         intel_update_watermarks(dev);
5461
5462         return ret;
5463 }
5464
5465 /*
5466  * Initialize reference clocks when the driver loads
5467  */
5468 void ironlake_init_pch_refclk(struct drm_device *dev)
5469 {
5470         struct drm_i915_private *dev_priv = dev->dev_private;
5471         struct drm_mode_config *mode_config = &dev->mode_config;
5472         struct intel_encoder *encoder;
5473         u32 temp;
5474         bool has_lvds = false;
5475         bool has_cpu_edp = false;
5476         bool has_pch_edp = false;
5477         bool has_panel = false;
5478         bool has_ck505 = false;
5479         bool can_ssc = false;
5480
5481         /* We need to take the global config into account */
5482         list_for_each_entry(encoder, &mode_config->encoder_list,
5483                             base.head) {
5484                 switch (encoder->type) {
5485                 case INTEL_OUTPUT_LVDS:
5486                         has_panel = true;
5487                         has_lvds = true;
5488                         break;
5489                 case INTEL_OUTPUT_EDP:
5490                         has_panel = true;
5491                         if (intel_encoder_is_pch_edp(&encoder->base))
5492                                 has_pch_edp = true;
5493                         else
5494                                 has_cpu_edp = true;
5495                         break;
5496                 }
5497         }
5498
5499         if (HAS_PCH_IBX(dev)) {
5500                 has_ck505 = dev_priv->display_clock_mode;
5501                 can_ssc = has_ck505;
5502         } else {
5503                 has_ck505 = false;
5504                 can_ssc = true;
5505         }
5506
5507         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5508                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5509                       has_ck505);
5510
5511         /* Ironlake: try to setup display ref clock before DPLL
5512          * enabling. This is only under driver's control after
5513          * PCH B stepping, previous chipset stepping should be
5514          * ignoring this setting.
5515          */
5516         temp = I915_READ(PCH_DREF_CONTROL);
5517         /* Always enable nonspread source */
5518         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5519
5520         if (has_ck505)
5521                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5522         else
5523                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5524
5525         if (has_panel) {
5526                 temp &= ~DREF_SSC_SOURCE_MASK;
5527                 temp |= DREF_SSC_SOURCE_ENABLE;
5528
5529                 /* SSC must be turned on before enabling the CPU output  */
5530                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5531                         DRM_DEBUG_KMS("Using SSC on panel\n");
5532                         temp |= DREF_SSC1_ENABLE;
5533                 }
5534
5535                 /* Get SSC going before enabling the outputs */
5536                 I915_WRITE(PCH_DREF_CONTROL, temp);
5537                 POSTING_READ(PCH_DREF_CONTROL);
5538                 udelay(200);
5539
5540                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5541
5542                 /* Enable CPU source on CPU attached eDP */
5543                 if (has_cpu_edp) {
5544                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5545                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5546                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5547                         }
5548                         else
5549                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5550                 } else
5551                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5552
5553                 I915_WRITE(PCH_DREF_CONTROL, temp);
5554                 POSTING_READ(PCH_DREF_CONTROL);
5555                 udelay(200);
5556         } else {
5557                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5558
5559                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5560
5561                 /* Turn off CPU output */
5562                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5563
5564                 I915_WRITE(PCH_DREF_CONTROL, temp);
5565                 POSTING_READ(PCH_DREF_CONTROL);
5566                 udelay(200);
5567
5568                 /* Turn off the SSC source */
5569                 temp &= ~DREF_SSC_SOURCE_MASK;
5570                 temp |= DREF_SSC_SOURCE_DISABLE;
5571
5572                 /* Turn off SSC1 */
5573                 temp &= ~ DREF_SSC1_ENABLE;
5574
5575                 I915_WRITE(PCH_DREF_CONTROL, temp);
5576                 POSTING_READ(PCH_DREF_CONTROL);
5577                 udelay(200);
5578         }
5579 }
5580
5581 static int ironlake_get_refclk(struct drm_crtc *crtc)
5582 {
5583         struct drm_device *dev = crtc->dev;
5584         struct drm_i915_private *dev_priv = dev->dev_private;
5585         struct intel_encoder *encoder;
5586         struct drm_mode_config *mode_config = &dev->mode_config;
5587         struct intel_encoder *edp_encoder = NULL;
5588         int num_connectors = 0;
5589         bool is_lvds = false;
5590
5591         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5592                 if (encoder->base.crtc != crtc)
5593                         continue;
5594
5595                 switch (encoder->type) {
5596                 case INTEL_OUTPUT_LVDS:
5597                         is_lvds = true;
5598                         break;
5599                 case INTEL_OUTPUT_EDP:
5600                         edp_encoder = encoder;
5601                         break;
5602                 }
5603                 num_connectors++;
5604         }
5605
5606         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5607                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5608                               dev_priv->lvds_ssc_freq);
5609                 return dev_priv->lvds_ssc_freq * 1000;
5610         }
5611
5612         return 120000;
5613 }
5614
5615 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5616                                   struct drm_display_mode *mode,
5617                                   struct drm_display_mode *adjusted_mode,
5618                                   int x, int y,
5619                                   struct drm_framebuffer *old_fb)
5620 {
5621         struct drm_device *dev = crtc->dev;
5622         struct drm_i915_private *dev_priv = dev->dev_private;
5623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5624         int pipe = intel_crtc->pipe;
5625         int plane = intel_crtc->plane;
5626         int refclk, num_connectors = 0;
5627         intel_clock_t clock, reduced_clock;
5628         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5629         bool ok, has_reduced_clock = false, is_sdvo = false;
5630         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5631         struct intel_encoder *has_edp_encoder = NULL;
5632         struct drm_mode_config *mode_config = &dev->mode_config;
5633         struct intel_encoder *encoder;
5634         const intel_limit_t *limit;
5635         int ret;
5636         struct fdi_m_n m_n = {0};
5637         u32 temp;
5638         u32 lvds_sync = 0;
5639         int target_clock, pixel_multiplier, lane, link_bw, factor;
5640         unsigned int pipe_bpp;
5641         bool dither;
5642
5643         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5644                 if (encoder->base.crtc != crtc)
5645                         continue;
5646
5647                 switch (encoder->type) {
5648                 case INTEL_OUTPUT_LVDS:
5649                         is_lvds = true;
5650                         break;
5651                 case INTEL_OUTPUT_SDVO:
5652                 case INTEL_OUTPUT_HDMI:
5653                         is_sdvo = true;
5654                         if (encoder->needs_tv_clock)
5655                                 is_tv = true;
5656                         break;
5657                 case INTEL_OUTPUT_TVOUT:
5658                         is_tv = true;
5659                         break;
5660                 case INTEL_OUTPUT_ANALOG:
5661                         is_crt = true;
5662                         break;
5663                 case INTEL_OUTPUT_DISPLAYPORT:
5664                         is_dp = true;
5665                         break;
5666                 case INTEL_OUTPUT_EDP:
5667                         has_edp_encoder = encoder;
5668                         break;
5669                 }
5670
5671                 num_connectors++;
5672         }
5673
5674         refclk = ironlake_get_refclk(crtc);
5675
5676         /*
5677          * Returns a set of divisors for the desired target clock with the given
5678          * refclk, or FALSE.  The returned values represent the clock equation:
5679          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5680          */
5681         limit = intel_limit(crtc, refclk);
5682         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5683                              &clock);
5684         if (!ok) {
5685                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5686                 return -EINVAL;
5687         }
5688
5689         /* Ensure that the cursor is valid for the new mode before changing... */
5690         intel_crtc_update_cursor(crtc, true);
5691
5692         if (is_lvds && dev_priv->lvds_downclock_avail) {
5693                 /*
5694                  * Ensure we match the reduced clock's P to the target clock.
5695                  * If the clocks don't match, we can't switch the display clock
5696                  * by using the FP0/FP1. In such case we will disable the LVDS
5697                  * downclock feature.
5698                 */
5699                 has_reduced_clock = limit->find_pll(limit, crtc,
5700                                                     dev_priv->lvds_downclock,
5701                                                     refclk,
5702                                                     &clock,
5703                                                     &reduced_clock);
5704         }
5705         /* SDVO TV has fixed PLL values depend on its clock range,
5706            this mirrors vbios setting. */
5707         if (is_sdvo && is_tv) {
5708                 if (adjusted_mode->clock >= 100000
5709                     && adjusted_mode->clock < 140500) {
5710                         clock.p1 = 2;
5711                         clock.p2 = 10;
5712                         clock.n = 3;
5713                         clock.m1 = 16;
5714                         clock.m2 = 8;
5715                 } else if (adjusted_mode->clock >= 140500
5716                            && adjusted_mode->clock <= 200000) {
5717                         clock.p1 = 1;
5718                         clock.p2 = 10;
5719                         clock.n = 6;
5720                         clock.m1 = 12;
5721                         clock.m2 = 8;
5722                 }
5723         }
5724
5725         /* FDI link */
5726         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5727         lane = 0;
5728         /* CPU eDP doesn't require FDI link, so just set DP M/N
5729            according to current link config */
5730         if (has_edp_encoder &&
5731             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5732                 target_clock = mode->clock;
5733                 intel_edp_link_config(has_edp_encoder,
5734                                       &lane, &link_bw);
5735         } else {
5736                 /* [e]DP over FDI requires target mode clock
5737                    instead of link clock */
5738                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5739                         target_clock = mode->clock;
5740                 else
5741                         target_clock = adjusted_mode->clock;
5742
5743                 /* FDI is a binary signal running at ~2.7GHz, encoding
5744                  * each output octet as 10 bits. The actual frequency
5745                  * is stored as a divider into a 100MHz clock, and the
5746                  * mode pixel clock is stored in units of 1KHz.
5747                  * Hence the bw of each lane in terms of the mode signal
5748                  * is:
5749                  */
5750                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5751         }
5752
5753         /* determine panel color depth */
5754         temp = I915_READ(PIPECONF(pipe));
5755         temp &= ~PIPE_BPC_MASK;
5756         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5757         switch (pipe_bpp) {
5758         case 18:
5759                 temp |= PIPE_6BPC;
5760                 break;
5761         case 24:
5762                 temp |= PIPE_8BPC;
5763                 break;
5764         case 30:
5765                 temp |= PIPE_10BPC;
5766                 break;
5767         case 36:
5768                 temp |= PIPE_12BPC;
5769                 break;
5770         default:
5771                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5772                         pipe_bpp);
5773                 temp |= PIPE_8BPC;
5774                 pipe_bpp = 24;
5775                 break;
5776         }
5777
5778         intel_crtc->bpp = pipe_bpp;
5779         I915_WRITE(PIPECONF(pipe), temp);
5780
5781         if (!lane) {
5782                 /*
5783                  * Account for spread spectrum to avoid
5784                  * oversubscribing the link. Max center spread
5785                  * is 2.5%; use 5% for safety's sake.
5786                  */
5787                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5788                 lane = bps / (link_bw * 8) + 1;
5789         }
5790
5791         intel_crtc->fdi_lanes = lane;
5792
5793         if (pixel_multiplier > 1)
5794                 link_bw *= pixel_multiplier;
5795         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5796                              &m_n);
5797
5798         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5799         if (has_reduced_clock)
5800                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5801                         reduced_clock.m2;
5802
5803         /* Enable autotuning of the PLL clock (if permissible) */
5804         factor = 21;
5805         if (is_lvds) {
5806                 if ((intel_panel_use_ssc(dev_priv) &&
5807                      dev_priv->lvds_ssc_freq == 100) ||
5808                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5809                         factor = 25;
5810         } else if (is_sdvo && is_tv)
5811                 factor = 20;
5812
5813         if (clock.m < factor * clock.n)
5814                 fp |= FP_CB_TUNE;
5815
5816         dpll = 0;
5817
5818         if (is_lvds)
5819                 dpll |= DPLLB_MODE_LVDS;
5820         else
5821                 dpll |= DPLLB_MODE_DAC_SERIAL;
5822         if (is_sdvo) {
5823                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5824                 if (pixel_multiplier > 1) {
5825                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5826                 }
5827                 dpll |= DPLL_DVO_HIGH_SPEED;
5828         }
5829         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5830                 dpll |= DPLL_DVO_HIGH_SPEED;
5831
5832         /* compute bitmask from p1 value */
5833         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5834         /* also FPA1 */
5835         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5836
5837         switch (clock.p2) {
5838         case 5:
5839                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5840                 break;
5841         case 7:
5842                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5843                 break;
5844         case 10:
5845                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5846                 break;
5847         case 14:
5848                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5849                 break;
5850         }
5851
5852         if (is_sdvo && is_tv)
5853                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5854         else if (is_tv)
5855                 /* XXX: just matching BIOS for now */
5856                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5857                 dpll |= 3;
5858         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5859                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5860         else
5861                 dpll |= PLL_REF_INPUT_DREFCLK;
5862
5863         /* setup pipeconf */
5864         pipeconf = I915_READ(PIPECONF(pipe));
5865
5866         /* Set up the display plane register */
5867         dspcntr = DISPPLANE_GAMMA_ENABLE;
5868
5869         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5870         drm_mode_debug_printmodeline(mode);
5871
5872         /* PCH eDP needs FDI, but CPU eDP does not */
5873         if (!intel_crtc->no_pll) {
5874                 if (!has_edp_encoder ||
5875                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5876                         I915_WRITE(PCH_FP0(pipe), fp);
5877                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5878
5879                         POSTING_READ(PCH_DPLL(pipe));
5880                         udelay(150);
5881                 }
5882         } else {
5883                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5884                     fp == I915_READ(PCH_FP0(0))) {
5885                         intel_crtc->use_pll_a = true;
5886                         DRM_DEBUG_KMS("using pipe a dpll\n");
5887                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5888                            fp == I915_READ(PCH_FP0(1))) {
5889                         intel_crtc->use_pll_a = false;
5890                         DRM_DEBUG_KMS("using pipe b dpll\n");
5891                 } else {
5892                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5893                         return -EINVAL;
5894                 }
5895         }
5896
5897         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5898          * This is an exception to the general rule that mode_set doesn't turn
5899          * things on.
5900          */
5901         if (is_lvds) {
5902                 temp = I915_READ(PCH_LVDS);
5903                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5904                 if (HAS_PCH_CPT(dev)) {
5905                         temp &= ~PORT_TRANS_SEL_MASK;
5906                         temp |= PORT_TRANS_SEL_CPT(pipe);
5907                 } else {
5908                         if (pipe == 1)
5909                                 temp |= LVDS_PIPEB_SELECT;
5910                         else
5911                                 temp &= ~LVDS_PIPEB_SELECT;
5912                 }
5913
5914                 /* set the corresponsding LVDS_BORDER bit */
5915                 temp |= dev_priv->lvds_border_bits;
5916                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5917                  * set the DPLLs for dual-channel mode or not.
5918                  */
5919                 if (clock.p2 == 7)
5920                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5921                 else
5922                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5923
5924                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5925                  * appropriately here, but we need to look more thoroughly into how
5926                  * panels behave in the two modes.
5927                  */
5928                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5929                         lvds_sync |= LVDS_HSYNC_POLARITY;
5930                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5931                         lvds_sync |= LVDS_VSYNC_POLARITY;
5932                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5933                     != lvds_sync) {
5934                         char flags[2] = "-+";
5935                         DRM_INFO("Changing LVDS panel from "
5936                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5937                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5938                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5939                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5940                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5941                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5942                         temp |= lvds_sync;
5943                 }
5944                 I915_WRITE(PCH_LVDS, temp);
5945         }
5946
5947         pipeconf &= ~PIPECONF_DITHER_EN;
5948         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5949         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5950                 pipeconf |= PIPECONF_DITHER_EN;
5951                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5952         }
5953         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5954                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5955         } else {
5956                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5957                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5958                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5959                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5960                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5961         }
5962
5963         if (!intel_crtc->no_pll &&
5964             (!has_edp_encoder ||
5965              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5966                 I915_WRITE(PCH_DPLL(pipe), dpll);
5967
5968                 /* Wait for the clocks to stabilize. */
5969                 POSTING_READ(PCH_DPLL(pipe));
5970                 udelay(150);
5971
5972                 /* The pixel multiplier can only be updated once the
5973                  * DPLL is enabled and the clocks are stable.
5974                  *
5975                  * So write it again.
5976                  */
5977                 I915_WRITE(PCH_DPLL(pipe), dpll);
5978         }
5979
5980         intel_crtc->lowfreq_avail = false;
5981         if (!intel_crtc->no_pll) {
5982                 if (is_lvds && has_reduced_clock && i915_powersave) {
5983                         I915_WRITE(PCH_FP1(pipe), fp2);
5984                         intel_crtc->lowfreq_avail = true;
5985                         if (HAS_PIPE_CXSR(dev)) {
5986                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5987                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5988                         }
5989                 } else {
5990                         I915_WRITE(PCH_FP1(pipe), fp);
5991                         if (HAS_PIPE_CXSR(dev)) {
5992                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5993                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5994                         }
5995                 }
5996         }
5997
5998         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5999         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6000                 pipeconf |= PIPECONF_INTERLACED_ILK;
6001                 /* the chip adds 2 halflines automatically */
6002                 adjusted_mode->crtc_vtotal -= 1;
6003                 adjusted_mode->crtc_vblank_end -= 1;
6004                 I915_WRITE(VSYNCSHIFT(pipe),
6005                            adjusted_mode->crtc_hsync_start
6006                            - adjusted_mode->crtc_htotal/2);
6007         } else {
6008                 pipeconf |= PIPECONF_PROGRESSIVE;
6009                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6010         }
6011
6012         I915_WRITE(HTOTAL(pipe),
6013                    (adjusted_mode->crtc_hdisplay - 1) |
6014                    ((adjusted_mode->crtc_htotal - 1) << 16));
6015         I915_WRITE(HBLANK(pipe),
6016                    (adjusted_mode->crtc_hblank_start - 1) |
6017                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6018         I915_WRITE(HSYNC(pipe),
6019                    (adjusted_mode->crtc_hsync_start - 1) |
6020                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6021
6022         I915_WRITE(VTOTAL(pipe),
6023                    (adjusted_mode->crtc_vdisplay - 1) |
6024                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6025         I915_WRITE(VBLANK(pipe),
6026                    (adjusted_mode->crtc_vblank_start - 1) |
6027                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6028         I915_WRITE(VSYNC(pipe),
6029                    (adjusted_mode->crtc_vsync_start - 1) |
6030                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6031
6032         /* pipesrc controls the size that is scaled from, which should
6033          * always be the user's requested size.
6034          */
6035         I915_WRITE(PIPESRC(pipe),
6036                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6037
6038         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6039         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6040         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6041         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6042
6043         if (has_edp_encoder &&
6044             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6045                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6046         }
6047
6048         I915_WRITE(PIPECONF(pipe), pipeconf);
6049         POSTING_READ(PIPECONF(pipe));
6050
6051         intel_wait_for_vblank(dev, pipe);
6052
6053         I915_WRITE(DSPCNTR(plane), dspcntr);
6054         POSTING_READ(DSPCNTR(plane));
6055
6056         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6057
6058         intel_update_watermarks(dev);
6059
6060         return ret;
6061 }
6062
6063 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6064                                struct drm_display_mode *mode,
6065                                struct drm_display_mode *adjusted_mode,
6066                                int x, int y,
6067                                struct drm_framebuffer *old_fb)
6068 {
6069         struct drm_device *dev = crtc->dev;
6070         struct drm_i915_private *dev_priv = dev->dev_private;
6071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072         int pipe = intel_crtc->pipe;
6073         int ret;
6074
6075         drm_vblank_pre_modeset(dev, pipe);
6076
6077         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6078                                               x, y, old_fb);
6079         drm_vblank_post_modeset(dev, pipe);
6080
6081         if (ret)
6082                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6083         else
6084                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6085
6086         return ret;
6087 }
6088
6089 static bool intel_eld_uptodate(struct drm_connector *connector,
6090                                int reg_eldv, uint32_t bits_eldv,
6091                                int reg_elda, uint32_t bits_elda,
6092                                int reg_edid)
6093 {
6094         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095         uint8_t *eld = connector->eld;
6096         uint32_t i;
6097
6098         i = I915_READ(reg_eldv);
6099         i &= bits_eldv;
6100
6101         if (!eld[0])
6102                 return !i;
6103
6104         if (!i)
6105                 return false;
6106
6107         i = I915_READ(reg_elda);
6108         i &= ~bits_elda;
6109         I915_WRITE(reg_elda, i);
6110
6111         for (i = 0; i < eld[2]; i++)
6112                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6113                         return false;
6114
6115         return true;
6116 }
6117
6118 static void g4x_write_eld(struct drm_connector *connector,
6119                           struct drm_crtc *crtc)
6120 {
6121         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6122         uint8_t *eld = connector->eld;
6123         uint32_t eldv;
6124         uint32_t len;
6125         uint32_t i;
6126
6127         i = I915_READ(G4X_AUD_VID_DID);
6128
6129         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6130                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6131         else
6132                 eldv = G4X_ELDV_DEVCTG;
6133
6134         if (intel_eld_uptodate(connector,
6135                                G4X_AUD_CNTL_ST, eldv,
6136                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6137                                G4X_HDMIW_HDMIEDID))
6138                 return;
6139
6140         i = I915_READ(G4X_AUD_CNTL_ST);
6141         i &= ~(eldv | G4X_ELD_ADDR);
6142         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6143         I915_WRITE(G4X_AUD_CNTL_ST, i);
6144
6145         if (!eld[0])
6146                 return;
6147
6148         len = min_t(uint8_t, eld[2], len);
6149         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6150         for (i = 0; i < len; i++)
6151                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6152
6153         i = I915_READ(G4X_AUD_CNTL_ST);
6154         i |= eldv;
6155         I915_WRITE(G4X_AUD_CNTL_ST, i);
6156 }
6157
6158 static void ironlake_write_eld(struct drm_connector *connector,
6159                                      struct drm_crtc *crtc)
6160 {
6161         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162         uint8_t *eld = connector->eld;
6163         uint32_t eldv;
6164         uint32_t i;
6165         int len;
6166         int hdmiw_hdmiedid;
6167         int aud_config;
6168         int aud_cntl_st;
6169         int aud_cntrl_st2;
6170
6171         if (HAS_PCH_IBX(connector->dev)) {
6172                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6173                 aud_config = IBX_AUD_CONFIG_A;
6174                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6175                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6176         } else {
6177                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6178                 aud_config = CPT_AUD_CONFIG_A;
6179                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6180                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6181         }
6182
6183         i = to_intel_crtc(crtc)->pipe;
6184         hdmiw_hdmiedid += i * 0x100;
6185         aud_cntl_st += i * 0x100;
6186         aud_config += i * 0x100;
6187
6188         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6189
6190         i = I915_READ(aud_cntl_st);
6191         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6192         if (!i) {
6193                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6194                 /* operate blindly on all ports */
6195                 eldv = IBX_ELD_VALIDB;
6196                 eldv |= IBX_ELD_VALIDB << 4;
6197                 eldv |= IBX_ELD_VALIDB << 8;
6198         } else {
6199                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6200                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6201         }
6202
6203         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6204                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6205                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6206                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6207         } else
6208                 I915_WRITE(aud_config, 0);
6209
6210         if (intel_eld_uptodate(connector,
6211                                aud_cntrl_st2, eldv,
6212                                aud_cntl_st, IBX_ELD_ADDRESS,
6213                                hdmiw_hdmiedid))
6214                 return;
6215
6216         i = I915_READ(aud_cntrl_st2);
6217         i &= ~eldv;
6218         I915_WRITE(aud_cntrl_st2, i);
6219
6220         if (!eld[0])
6221                 return;
6222
6223         i = I915_READ(aud_cntl_st);
6224         i &= ~IBX_ELD_ADDRESS;
6225         I915_WRITE(aud_cntl_st, i);
6226
6227         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6228         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6229         for (i = 0; i < len; i++)
6230                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6231
6232         i = I915_READ(aud_cntrl_st2);
6233         i |= eldv;
6234         I915_WRITE(aud_cntrl_st2, i);
6235 }
6236
6237 void intel_write_eld(struct drm_encoder *encoder,
6238                      struct drm_display_mode *mode)
6239 {
6240         struct drm_crtc *crtc = encoder->crtc;
6241         struct drm_connector *connector;
6242         struct drm_device *dev = encoder->dev;
6243         struct drm_i915_private *dev_priv = dev->dev_private;
6244
6245         connector = drm_select_eld(encoder, mode);
6246         if (!connector)
6247                 return;
6248
6249         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6250                          connector->base.id,
6251                          drm_get_connector_name(connector),
6252                          connector->encoder->base.id,
6253                          drm_get_encoder_name(connector->encoder));
6254
6255         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6256
6257         if (dev_priv->display.write_eld)
6258                 dev_priv->display.write_eld(connector, crtc);
6259 }
6260
6261 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6262 void intel_crtc_load_lut(struct drm_crtc *crtc)
6263 {
6264         struct drm_device *dev = crtc->dev;
6265         struct drm_i915_private *dev_priv = dev->dev_private;
6266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267         int palreg = PALETTE(intel_crtc->pipe);
6268         int i;
6269
6270         /* The clocks have to be on to load the palette. */
6271         if (!crtc->enabled)
6272                 return;
6273
6274         /* use legacy palette for Ironlake */
6275         if (HAS_PCH_SPLIT(dev))
6276                 palreg = LGC_PALETTE(intel_crtc->pipe);
6277
6278         for (i = 0; i < 256; i++) {
6279                 I915_WRITE(palreg + 4 * i,
6280                            (intel_crtc->lut_r[i] << 16) |
6281                            (intel_crtc->lut_g[i] << 8) |
6282                            intel_crtc->lut_b[i]);
6283         }
6284 }
6285
6286 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6287 {
6288         struct drm_device *dev = crtc->dev;
6289         struct drm_i915_private *dev_priv = dev->dev_private;
6290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6291         bool visible = base != 0;
6292         u32 cntl;
6293
6294         if (intel_crtc->cursor_visible == visible)
6295                 return;
6296
6297         cntl = I915_READ(_CURACNTR);
6298         if (visible) {
6299                 /* On these chipsets we can only modify the base whilst
6300                  * the cursor is disabled.
6301                  */
6302                 I915_WRITE(_CURABASE, base);
6303
6304                 cntl &= ~(CURSOR_FORMAT_MASK);
6305                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6306                 cntl |= CURSOR_ENABLE |
6307                         CURSOR_GAMMA_ENABLE |
6308                         CURSOR_FORMAT_ARGB;
6309         } else
6310                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6311         I915_WRITE(_CURACNTR, cntl);
6312
6313         intel_crtc->cursor_visible = visible;
6314 }
6315
6316 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6317 {
6318         struct drm_device *dev = crtc->dev;
6319         struct drm_i915_private *dev_priv = dev->dev_private;
6320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6321         int pipe = intel_crtc->pipe;
6322         bool visible = base != 0;
6323
6324         if (intel_crtc->cursor_visible != visible) {
6325                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6326                 if (base) {
6327                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6328                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6329                         cntl |= pipe << 28; /* Connect to correct pipe */
6330                 } else {
6331                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6332                         cntl |= CURSOR_MODE_DISABLE;
6333                 }
6334                 I915_WRITE(CURCNTR(pipe), cntl);
6335
6336                 intel_crtc->cursor_visible = visible;
6337         }
6338         /* and commit changes on next vblank */
6339         I915_WRITE(CURBASE(pipe), base);
6340 }
6341
6342 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6343 {
6344         struct drm_device *dev = crtc->dev;
6345         struct drm_i915_private *dev_priv = dev->dev_private;
6346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347         int pipe = intel_crtc->pipe;
6348         bool visible = base != 0;
6349
6350         if (intel_crtc->cursor_visible != visible) {
6351                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6352                 if (base) {
6353                         cntl &= ~CURSOR_MODE;
6354                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6355                 } else {
6356                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6357                         cntl |= CURSOR_MODE_DISABLE;
6358                 }
6359                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6360
6361                 intel_crtc->cursor_visible = visible;
6362         }
6363         /* and commit changes on next vblank */
6364         I915_WRITE(CURBASE_IVB(pipe), base);
6365 }
6366
6367 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6368 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6369                                      bool on)
6370 {
6371         struct drm_device *dev = crtc->dev;
6372         struct drm_i915_private *dev_priv = dev->dev_private;
6373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6374         int pipe = intel_crtc->pipe;
6375         int x = intel_crtc->cursor_x;
6376         int y = intel_crtc->cursor_y;
6377         u32 base, pos;
6378         bool visible;
6379
6380         pos = 0;
6381
6382         if (on && crtc->enabled && crtc->fb) {
6383                 base = intel_crtc->cursor_addr;
6384                 if (x > (int) crtc->fb->width)
6385                         base = 0;
6386
6387                 if (y > (int) crtc->fb->height)
6388                         base = 0;
6389         } else
6390                 base = 0;
6391
6392         if (x < 0) {
6393                 if (x + intel_crtc->cursor_width < 0)
6394                         base = 0;
6395
6396                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6397                 x = -x;
6398         }
6399         pos |= x << CURSOR_X_SHIFT;
6400
6401         if (y < 0) {
6402                 if (y + intel_crtc->cursor_height < 0)
6403                         base = 0;
6404
6405                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6406                 y = -y;
6407         }
6408         pos |= y << CURSOR_Y_SHIFT;
6409
6410         visible = base != 0;
6411         if (!visible && !intel_crtc->cursor_visible)
6412                 return;
6413
6414         if (IS_IVYBRIDGE(dev)) {
6415                 I915_WRITE(CURPOS_IVB(pipe), pos);
6416                 ivb_update_cursor(crtc, base);
6417         } else {
6418                 I915_WRITE(CURPOS(pipe), pos);
6419                 if (IS_845G(dev) || IS_I865G(dev))
6420                         i845_update_cursor(crtc, base);
6421                 else
6422                         i9xx_update_cursor(crtc, base);
6423         }
6424
6425         if (visible)
6426                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6427 }
6428
6429 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6430                                  struct drm_file *file,
6431                                  uint32_t handle,
6432                                  uint32_t width, uint32_t height)
6433 {
6434         struct drm_device *dev = crtc->dev;
6435         struct drm_i915_private *dev_priv = dev->dev_private;
6436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437         struct drm_i915_gem_object *obj;
6438         uint32_t addr;
6439         int ret;
6440
6441         DRM_DEBUG_KMS("\n");
6442
6443         /* if we want to turn off the cursor ignore width and height */
6444         if (!handle) {
6445                 DRM_DEBUG_KMS("cursor off\n");
6446                 addr = 0;
6447                 obj = NULL;
6448                 mutex_lock(&dev->struct_mutex);
6449                 goto finish;
6450         }
6451
6452         /* Currently we only support 64x64 cursors */
6453         if (width != 64 || height != 64) {
6454                 DRM_ERROR("we currently only support 64x64 cursors\n");
6455                 return -EINVAL;
6456         }
6457
6458         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6459         if (&obj->base == NULL)
6460                 return -ENOENT;
6461
6462         if (obj->base.size < width * height * 4) {
6463                 DRM_ERROR("buffer is to small\n");
6464                 ret = -ENOMEM;
6465                 goto fail;
6466         }
6467
6468         /* we only need to pin inside GTT if cursor is non-phy */
6469         mutex_lock(&dev->struct_mutex);
6470         if (!dev_priv->info->cursor_needs_physical) {
6471                 if (obj->tiling_mode) {
6472                         DRM_ERROR("cursor cannot be tiled\n");
6473                         ret = -EINVAL;
6474                         goto fail_locked;
6475                 }
6476
6477                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6478                 if (ret) {
6479                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6480                         goto fail_locked;
6481                 }
6482
6483                 ret = i915_gem_object_put_fence(obj);
6484                 if (ret) {
6485                         DRM_ERROR("failed to release fence for cursor");
6486                         goto fail_unpin;
6487                 }
6488
6489                 addr = obj->gtt_offset;
6490         } else {
6491                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6492                 ret = i915_gem_attach_phys_object(dev, obj,
6493                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6494                                                   align);
6495                 if (ret) {
6496                         DRM_ERROR("failed to attach phys object\n");
6497                         goto fail_locked;
6498                 }
6499                 addr = obj->phys_obj->handle->busaddr;
6500         }
6501
6502         if (IS_GEN2(dev))
6503                 I915_WRITE(CURSIZE, (height << 12) | width);
6504
6505  finish:
6506         if (intel_crtc->cursor_bo) {
6507                 if (dev_priv->info->cursor_needs_physical) {
6508                         if (intel_crtc->cursor_bo != obj)
6509                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6510                 } else
6511                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6512                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6513         }
6514
6515         mutex_unlock(&dev->struct_mutex);
6516
6517         intel_crtc->cursor_addr = addr;
6518         intel_crtc->cursor_bo = obj;
6519         intel_crtc->cursor_width = width;
6520         intel_crtc->cursor_height = height;
6521
6522         intel_crtc_update_cursor(crtc, true);
6523
6524         return 0;
6525 fail_unpin:
6526         i915_gem_object_unpin(obj);
6527 fail_locked:
6528         mutex_unlock(&dev->struct_mutex);
6529 fail:
6530         drm_gem_object_unreference_unlocked(&obj->base);
6531         return ret;
6532 }
6533
6534 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6535 {
6536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537
6538         intel_crtc->cursor_x = x;
6539         intel_crtc->cursor_y = y;
6540
6541         intel_crtc_update_cursor(crtc, true);
6542
6543         return 0;
6544 }
6545
6546 /** Sets the color ramps on behalf of RandR */
6547 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6548                                  u16 blue, int regno)
6549 {
6550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6551
6552         intel_crtc->lut_r[regno] = red >> 8;
6553         intel_crtc->lut_g[regno] = green >> 8;
6554         intel_crtc->lut_b[regno] = blue >> 8;
6555 }
6556
6557 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6558                              u16 *blue, int regno)
6559 {
6560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6561
6562         *red = intel_crtc->lut_r[regno] << 8;
6563         *green = intel_crtc->lut_g[regno] << 8;
6564         *blue = intel_crtc->lut_b[regno] << 8;
6565 }
6566
6567 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6568                                  u16 *blue, uint32_t start, uint32_t size)
6569 {
6570         int end = (start + size > 256) ? 256 : start + size, i;
6571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6572
6573         for (i = start; i < end; i++) {
6574                 intel_crtc->lut_r[i] = red[i] >> 8;
6575                 intel_crtc->lut_g[i] = green[i] >> 8;
6576                 intel_crtc->lut_b[i] = blue[i] >> 8;
6577         }
6578
6579         intel_crtc_load_lut(crtc);
6580 }
6581
6582 /**
6583  * Get a pipe with a simple mode set on it for doing load-based monitor
6584  * detection.
6585  *
6586  * It will be up to the load-detect code to adjust the pipe as appropriate for
6587  * its requirements.  The pipe will be connected to no other encoders.
6588  *
6589  * Currently this code will only succeed if there is a pipe with no encoders
6590  * configured for it.  In the future, it could choose to temporarily disable
6591  * some outputs to free up a pipe for its use.
6592  *
6593  * \return crtc, or NULL if no pipes are available.
6594  */
6595
6596 /* VESA 640x480x72Hz mode to set on the pipe */
6597 static struct drm_display_mode load_detect_mode = {
6598         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6599                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6600 };
6601
6602 static struct drm_framebuffer *
6603 intel_framebuffer_create(struct drm_device *dev,
6604                          struct drm_mode_fb_cmd2 *mode_cmd,
6605                          struct drm_i915_gem_object *obj)
6606 {
6607         struct intel_framebuffer *intel_fb;
6608         int ret;
6609
6610         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6611         if (!intel_fb) {
6612                 drm_gem_object_unreference_unlocked(&obj->base);
6613                 return ERR_PTR(-ENOMEM);
6614         }
6615
6616         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6617         if (ret) {
6618                 drm_gem_object_unreference_unlocked(&obj->base);
6619                 kfree(intel_fb);
6620                 return ERR_PTR(ret);
6621         }
6622
6623         return &intel_fb->base;
6624 }
6625
6626 static u32
6627 intel_framebuffer_pitch_for_width(int width, int bpp)
6628 {
6629         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6630         return ALIGN(pitch, 64);
6631 }
6632
6633 static u32
6634 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6635 {
6636         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6637         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6638 }
6639
6640 static struct drm_framebuffer *
6641 intel_framebuffer_create_for_mode(struct drm_device *dev,
6642                                   struct drm_display_mode *mode,
6643                                   int depth, int bpp)
6644 {
6645         struct drm_i915_gem_object *obj;
6646         struct drm_mode_fb_cmd2 mode_cmd;
6647
6648         obj = i915_gem_alloc_object(dev,
6649                                     intel_framebuffer_size_for_mode(mode, bpp));
6650         if (obj == NULL)
6651                 return ERR_PTR(-ENOMEM);
6652
6653         mode_cmd.width = mode->hdisplay;
6654         mode_cmd.height = mode->vdisplay;
6655         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6656                                                                 bpp);
6657         mode_cmd.pixel_format = 0;
6658
6659         return intel_framebuffer_create(dev, &mode_cmd, obj);
6660 }
6661
6662 static struct drm_framebuffer *
6663 mode_fits_in_fbdev(struct drm_device *dev,
6664                    struct drm_display_mode *mode)
6665 {
6666         struct drm_i915_private *dev_priv = dev->dev_private;
6667         struct drm_i915_gem_object *obj;
6668         struct drm_framebuffer *fb;
6669
6670         if (dev_priv->fbdev == NULL)
6671                 return NULL;
6672
6673         obj = dev_priv->fbdev->ifb.obj;
6674         if (obj == NULL)
6675                 return NULL;
6676
6677         fb = &dev_priv->fbdev->ifb.base;
6678         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6679                                                                fb->bits_per_pixel))
6680                 return NULL;
6681
6682         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6683                 return NULL;
6684
6685         return fb;
6686 }
6687
6688 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6689                                 struct drm_connector *connector,
6690                                 struct drm_display_mode *mode,
6691                                 struct intel_load_detect_pipe *old)
6692 {
6693         struct intel_crtc *intel_crtc;
6694         struct drm_crtc *possible_crtc;
6695         struct drm_encoder *encoder = &intel_encoder->base;
6696         struct drm_crtc *crtc = NULL;
6697         struct drm_device *dev = encoder->dev;
6698         struct drm_framebuffer *old_fb;
6699         int i = -1;
6700
6701         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6702                       connector->base.id, drm_get_connector_name(connector),
6703                       encoder->base.id, drm_get_encoder_name(encoder));
6704
6705         /*
6706          * Algorithm gets a little messy:
6707          *
6708          *   - if the connector already has an assigned crtc, use it (but make
6709          *     sure it's on first)
6710          *
6711          *   - try to find the first unused crtc that can drive this connector,
6712          *     and use that if we find one
6713          */
6714
6715         /* See if we already have a CRTC for this connector */
6716         if (encoder->crtc) {
6717                 crtc = encoder->crtc;
6718
6719                 intel_crtc = to_intel_crtc(crtc);
6720                 old->dpms_mode = intel_crtc->dpms_mode;
6721                 old->load_detect_temp = false;
6722
6723                 /* Make sure the crtc and connector are running */
6724                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6725                         struct drm_encoder_helper_funcs *encoder_funcs;
6726                         struct drm_crtc_helper_funcs *crtc_funcs;
6727
6728                         crtc_funcs = crtc->helper_private;
6729                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6730
6731                         encoder_funcs = encoder->helper_private;
6732                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6733                 }
6734
6735                 return true;
6736         }
6737
6738         /* Find an unused one (if possible) */
6739         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6740                 i++;
6741                 if (!(encoder->possible_crtcs & (1 << i)))
6742                         continue;
6743                 if (!possible_crtc->enabled) {
6744                         crtc = possible_crtc;
6745                         break;
6746                 }
6747         }
6748
6749         /*
6750          * If we didn't find an unused CRTC, don't use any.
6751          */
6752         if (!crtc) {
6753                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6754                 return false;
6755         }
6756
6757         encoder->crtc = crtc;
6758         connector->encoder = encoder;
6759
6760         intel_crtc = to_intel_crtc(crtc);
6761         old->dpms_mode = intel_crtc->dpms_mode;
6762         old->load_detect_temp = true;
6763         old->release_fb = NULL;
6764
6765         if (!mode)
6766                 mode = &load_detect_mode;
6767
6768         old_fb = crtc->fb;
6769
6770         /* We need a framebuffer large enough to accommodate all accesses
6771          * that the plane may generate whilst we perform load detection.
6772          * We can not rely on the fbcon either being present (we get called
6773          * during its initialisation to detect all boot displays, or it may
6774          * not even exist) or that it is large enough to satisfy the
6775          * requested mode.
6776          */
6777         crtc->fb = mode_fits_in_fbdev(dev, mode);
6778         if (crtc->fb == NULL) {
6779                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6780                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6781                 old->release_fb = crtc->fb;
6782         } else
6783                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6784         if (IS_ERR(crtc->fb)) {
6785                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6786                 crtc->fb = old_fb;
6787                 return false;
6788         }
6789
6790         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6791                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6792                 if (old->release_fb)
6793                         old->release_fb->funcs->destroy(old->release_fb);
6794                 crtc->fb = old_fb;
6795                 return false;
6796         }
6797
6798         /* let the connector get through one full cycle before testing */
6799         intel_wait_for_vblank(dev, intel_crtc->pipe);
6800
6801         return true;
6802 }
6803
6804 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6805                                     struct drm_connector *connector,
6806                                     struct intel_load_detect_pipe *old)
6807 {
6808         struct drm_encoder *encoder = &intel_encoder->base;
6809         struct drm_device *dev = encoder->dev;
6810         struct drm_crtc *crtc = encoder->crtc;
6811         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6812         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6813
6814         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6815                       connector->base.id, drm_get_connector_name(connector),
6816                       encoder->base.id, drm_get_encoder_name(encoder));
6817
6818         if (old->load_detect_temp) {
6819                 connector->encoder = NULL;
6820                 drm_helper_disable_unused_functions(dev);
6821
6822                 if (old->release_fb)
6823                         old->release_fb->funcs->destroy(old->release_fb);
6824
6825                 return;
6826         }
6827
6828         /* Switch crtc and encoder back off if necessary */
6829         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6830                 encoder_funcs->dpms(encoder, old->dpms_mode);
6831                 crtc_funcs->dpms(crtc, old->dpms_mode);
6832         }
6833 }
6834
6835 /* Returns the clock of the currently programmed mode of the given pipe. */
6836 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6837 {
6838         struct drm_i915_private *dev_priv = dev->dev_private;
6839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840         int pipe = intel_crtc->pipe;
6841         u32 dpll = I915_READ(DPLL(pipe));
6842         u32 fp;
6843         intel_clock_t clock;
6844
6845         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6846                 fp = I915_READ(FP0(pipe));
6847         else
6848                 fp = I915_READ(FP1(pipe));
6849
6850         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6851         if (IS_PINEVIEW(dev)) {
6852                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6853                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6854         } else {
6855                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6856                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6857         }
6858
6859         if (!IS_GEN2(dev)) {
6860                 if (IS_PINEVIEW(dev))
6861                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6862                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6863                 else
6864                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6865                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6866
6867                 switch (dpll & DPLL_MODE_MASK) {
6868                 case DPLLB_MODE_DAC_SERIAL:
6869                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6870                                 5 : 10;
6871                         break;
6872                 case DPLLB_MODE_LVDS:
6873                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6874                                 7 : 14;
6875                         break;
6876                 default:
6877                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6878                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6879                         return 0;
6880                 }
6881
6882                 /* XXX: Handle the 100Mhz refclk */
6883                 intel_clock(dev, 96000, &clock);
6884         } else {
6885                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6886
6887                 if (is_lvds) {
6888                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6889                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6890                         clock.p2 = 14;
6891
6892                         if ((dpll & PLL_REF_INPUT_MASK) ==
6893                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6894                                 /* XXX: might not be 66MHz */
6895                                 intel_clock(dev, 66000, &clock);
6896                         } else
6897                                 intel_clock(dev, 48000, &clock);
6898                 } else {
6899                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6900                                 clock.p1 = 2;
6901                         else {
6902                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6903                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6904                         }
6905                         if (dpll & PLL_P2_DIVIDE_BY_4)
6906                                 clock.p2 = 4;
6907                         else
6908                                 clock.p2 = 2;
6909
6910                         intel_clock(dev, 48000, &clock);
6911                 }
6912         }
6913
6914         /* XXX: It would be nice to validate the clocks, but we can't reuse
6915          * i830PllIsValid() because it relies on the xf86_config connector
6916          * configuration being accurate, which it isn't necessarily.
6917          */
6918
6919         return clock.dot;
6920 }
6921
6922 /** Returns the currently programmed mode of the given pipe. */
6923 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6924                                              struct drm_crtc *crtc)
6925 {
6926         struct drm_i915_private *dev_priv = dev->dev_private;
6927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6928         int pipe = intel_crtc->pipe;
6929         struct drm_display_mode *mode;
6930         int htot = I915_READ(HTOTAL(pipe));
6931         int hsync = I915_READ(HSYNC(pipe));
6932         int vtot = I915_READ(VTOTAL(pipe));
6933         int vsync = I915_READ(VSYNC(pipe));
6934
6935         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6936         if (!mode)
6937                 return NULL;
6938
6939         mode->clock = intel_crtc_clock_get(dev, crtc);
6940         mode->hdisplay = (htot & 0xffff) + 1;
6941         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6942         mode->hsync_start = (hsync & 0xffff) + 1;
6943         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6944         mode->vdisplay = (vtot & 0xffff) + 1;
6945         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6946         mode->vsync_start = (vsync & 0xffff) + 1;
6947         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6948
6949         drm_mode_set_name(mode);
6950         drm_mode_set_crtcinfo(mode, 0);
6951
6952         return mode;
6953 }
6954
6955 #define GPU_IDLE_TIMEOUT 500 /* ms */
6956
6957 /* When this timer fires, we've been idle for awhile */
6958 static void intel_gpu_idle_timer(unsigned long arg)
6959 {
6960         struct drm_device *dev = (struct drm_device *)arg;
6961         drm_i915_private_t *dev_priv = dev->dev_private;
6962
6963         if (!list_empty(&dev_priv->mm.active_list)) {
6964                 /* Still processing requests, so just re-arm the timer. */
6965                 mod_timer(&dev_priv->idle_timer, jiffies +
6966                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6967                 return;
6968         }
6969
6970         dev_priv->busy = false;
6971         queue_work(dev_priv->wq, &dev_priv->idle_work);
6972 }
6973
6974 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6975
6976 static void intel_crtc_idle_timer(unsigned long arg)
6977 {
6978         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6979         struct drm_crtc *crtc = &intel_crtc->base;
6980         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6981         struct intel_framebuffer *intel_fb;
6982
6983         intel_fb = to_intel_framebuffer(crtc->fb);
6984         if (intel_fb && intel_fb->obj->active) {
6985                 /* The framebuffer is still being accessed by the GPU. */
6986                 mod_timer(&intel_crtc->idle_timer, jiffies +
6987                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6988                 return;
6989         }
6990
6991         intel_crtc->busy = false;
6992         queue_work(dev_priv->wq, &dev_priv->idle_work);
6993 }
6994
6995 static void intel_increase_pllclock(struct drm_crtc *crtc)
6996 {
6997         struct drm_device *dev = crtc->dev;
6998         drm_i915_private_t *dev_priv = dev->dev_private;
6999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7000         int pipe = intel_crtc->pipe;
7001         int dpll_reg = DPLL(pipe);
7002         int dpll;
7003
7004         if (HAS_PCH_SPLIT(dev))
7005                 return;
7006
7007         if (!dev_priv->lvds_downclock_avail)
7008                 return;
7009
7010         dpll = I915_READ(dpll_reg);
7011         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7012                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7013
7014                 assert_panel_unlocked(dev_priv, pipe);
7015
7016                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7017                 I915_WRITE(dpll_reg, dpll);
7018                 intel_wait_for_vblank(dev, pipe);
7019
7020                 dpll = I915_READ(dpll_reg);
7021                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7022                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7023         }
7024
7025         /* Schedule downclock */
7026         mod_timer(&intel_crtc->idle_timer, jiffies +
7027                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7028 }
7029
7030 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7031 {
7032         struct drm_device *dev = crtc->dev;
7033         drm_i915_private_t *dev_priv = dev->dev_private;
7034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7035         int pipe = intel_crtc->pipe;
7036         int dpll_reg = DPLL(pipe);
7037         int dpll = I915_READ(dpll_reg);
7038
7039         if (HAS_PCH_SPLIT(dev))
7040                 return;
7041
7042         if (!dev_priv->lvds_downclock_avail)
7043                 return;
7044
7045         /*
7046          * Since this is called by a timer, we should never get here in
7047          * the manual case.
7048          */
7049         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7050                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7051
7052                 assert_panel_unlocked(dev_priv, pipe);
7053
7054                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7055                 I915_WRITE(dpll_reg, dpll);
7056                 intel_wait_for_vblank(dev, pipe);
7057                 dpll = I915_READ(dpll_reg);
7058                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7059                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7060         }
7061
7062 }
7063
7064 /**
7065  * intel_idle_update - adjust clocks for idleness
7066  * @work: work struct
7067  *
7068  * Either the GPU or display (or both) went idle.  Check the busy status
7069  * here and adjust the CRTC and GPU clocks as necessary.
7070  */
7071 static void intel_idle_update(struct work_struct *work)
7072 {
7073         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7074                                                     idle_work);
7075         struct drm_device *dev = dev_priv->dev;
7076         struct drm_crtc *crtc;
7077         struct intel_crtc *intel_crtc;
7078
7079         if (!i915_powersave)
7080                 return;
7081
7082         mutex_lock(&dev->struct_mutex);
7083
7084         i915_update_gfx_val(dev_priv);
7085
7086         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7087                 /* Skip inactive CRTCs */
7088                 if (!crtc->fb)
7089                         continue;
7090
7091                 intel_crtc = to_intel_crtc(crtc);
7092                 if (!intel_crtc->busy)
7093                         intel_decrease_pllclock(crtc);
7094         }
7095
7096
7097         mutex_unlock(&dev->struct_mutex);
7098 }
7099
7100 /**
7101  * intel_mark_busy - mark the GPU and possibly the display busy
7102  * @dev: drm device
7103  * @obj: object we're operating on
7104  *
7105  * Callers can use this function to indicate that the GPU is busy processing
7106  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7107  * buffer), we'll also mark the display as busy, so we know to increase its
7108  * clock frequency.
7109  */
7110 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7111 {
7112         drm_i915_private_t *dev_priv = dev->dev_private;
7113         struct drm_crtc *crtc = NULL;
7114         struct intel_framebuffer *intel_fb;
7115         struct intel_crtc *intel_crtc;
7116
7117         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7118                 return;
7119
7120         if (!dev_priv->busy)
7121                 dev_priv->busy = true;
7122         else
7123                 mod_timer(&dev_priv->idle_timer, jiffies +
7124                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7125
7126         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7127                 if (!crtc->fb)
7128                         continue;
7129
7130                 intel_crtc = to_intel_crtc(crtc);
7131                 intel_fb = to_intel_framebuffer(crtc->fb);
7132                 if (intel_fb->obj == obj) {
7133                         if (!intel_crtc->busy) {
7134                                 /* Non-busy -> busy, upclock */
7135                                 intel_increase_pllclock(crtc);
7136                                 intel_crtc->busy = true;
7137                         } else {
7138                                 /* Busy -> busy, put off timer */
7139                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7140                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7141                         }
7142                 }
7143         }
7144 }
7145
7146 static void intel_crtc_destroy(struct drm_crtc *crtc)
7147 {
7148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7149         struct drm_device *dev = crtc->dev;
7150         struct intel_unpin_work *work;
7151         unsigned long flags;
7152
7153         spin_lock_irqsave(&dev->event_lock, flags);
7154         work = intel_crtc->unpin_work;
7155         intel_crtc->unpin_work = NULL;
7156         spin_unlock_irqrestore(&dev->event_lock, flags);
7157
7158         if (work) {
7159                 cancel_work_sync(&work->work);
7160                 kfree(work);
7161         }
7162
7163         drm_crtc_cleanup(crtc);
7164
7165         kfree(intel_crtc);
7166 }
7167
7168 static void intel_unpin_work_fn(struct work_struct *__work)
7169 {
7170         struct intel_unpin_work *work =
7171                 container_of(__work, struct intel_unpin_work, work);
7172
7173         mutex_lock(&work->dev->struct_mutex);
7174         intel_unpin_fb_obj(work->old_fb_obj);
7175         drm_gem_object_unreference(&work->pending_flip_obj->base);
7176         drm_gem_object_unreference(&work->old_fb_obj->base);
7177
7178         intel_update_fbc(work->dev);
7179         mutex_unlock(&work->dev->struct_mutex);
7180         kfree(work);
7181 }
7182
7183 static void do_intel_finish_page_flip(struct drm_device *dev,
7184                                       struct drm_crtc *crtc)
7185 {
7186         drm_i915_private_t *dev_priv = dev->dev_private;
7187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188         struct intel_unpin_work *work;
7189         struct drm_i915_gem_object *obj;
7190         struct drm_pending_vblank_event *e;
7191         struct timeval tnow, tvbl;
7192         unsigned long flags;
7193
7194         /* Ignore early vblank irqs */
7195         if (intel_crtc == NULL)
7196                 return;
7197
7198         do_gettimeofday(&tnow);
7199
7200         spin_lock_irqsave(&dev->event_lock, flags);
7201         work = intel_crtc->unpin_work;
7202         if (work == NULL || !work->pending) {
7203                 spin_unlock_irqrestore(&dev->event_lock, flags);
7204                 return;
7205         }
7206
7207         intel_crtc->unpin_work = NULL;
7208
7209         if (work->event) {
7210                 e = work->event;
7211                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7212
7213                 /* Called before vblank count and timestamps have
7214                  * been updated for the vblank interval of flip
7215                  * completion? Need to increment vblank count and
7216                  * add one videorefresh duration to returned timestamp
7217                  * to account for this. We assume this happened if we
7218                  * get called over 0.9 frame durations after the last
7219                  * timestamped vblank.
7220                  *
7221                  * This calculation can not be used with vrefresh rates
7222                  * below 5Hz (10Hz to be on the safe side) without
7223                  * promoting to 64 integers.
7224                  */
7225                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7226                     9 * crtc->framedur_ns) {
7227                         e->event.sequence++;
7228                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7229                                              crtc->framedur_ns);
7230                 }
7231
7232                 e->event.tv_sec = tvbl.tv_sec;
7233                 e->event.tv_usec = tvbl.tv_usec;
7234
7235                 list_add_tail(&e->base.link,
7236                               &e->base.file_priv->event_list);
7237                 wake_up_interruptible(&e->base.file_priv->event_wait);
7238         }
7239
7240         drm_vblank_put(dev, intel_crtc->pipe);
7241
7242         spin_unlock_irqrestore(&dev->event_lock, flags);
7243
7244         obj = work->old_fb_obj;
7245
7246         atomic_clear_mask(1 << intel_crtc->plane,
7247                           &obj->pending_flip.counter);
7248         if (atomic_read(&obj->pending_flip) == 0)
7249                 wake_up(&dev_priv->pending_flip_queue);
7250
7251         schedule_work(&work->work);
7252
7253         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7254 }
7255
7256 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7257 {
7258         drm_i915_private_t *dev_priv = dev->dev_private;
7259         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7260
7261         do_intel_finish_page_flip(dev, crtc);
7262 }
7263
7264 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7265 {
7266         drm_i915_private_t *dev_priv = dev->dev_private;
7267         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7268
7269         do_intel_finish_page_flip(dev, crtc);
7270 }
7271
7272 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7273 {
7274         drm_i915_private_t *dev_priv = dev->dev_private;
7275         struct intel_crtc *intel_crtc =
7276                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7277         unsigned long flags;
7278
7279         spin_lock_irqsave(&dev->event_lock, flags);
7280         if (intel_crtc->unpin_work) {
7281                 if ((++intel_crtc->unpin_work->pending) > 1)
7282                         DRM_ERROR("Prepared flip multiple times\n");
7283         } else {
7284                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7285         }
7286         spin_unlock_irqrestore(&dev->event_lock, flags);
7287 }
7288
7289 static int intel_gen2_queue_flip(struct drm_device *dev,
7290                                  struct drm_crtc *crtc,
7291                                  struct drm_framebuffer *fb,
7292                                  struct drm_i915_gem_object *obj)
7293 {
7294         struct drm_i915_private *dev_priv = dev->dev_private;
7295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7296         unsigned long offset;
7297         u32 flip_mask;
7298         int ret;
7299
7300         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7301         if (ret)
7302                 goto out;
7303
7304         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7305         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7306
7307         ret = BEGIN_LP_RING(6);
7308         if (ret)
7309                 goto out;
7310
7311         /* Can't queue multiple flips, so wait for the previous
7312          * one to finish before executing the next.
7313          */
7314         if (intel_crtc->plane)
7315                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7316         else
7317                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7318         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7319         OUT_RING(MI_NOOP);
7320         OUT_RING(MI_DISPLAY_FLIP |
7321                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7322         OUT_RING(fb->pitches[0]);
7323         OUT_RING(obj->gtt_offset + offset);
7324         OUT_RING(0); /* aux display base address, unused */
7325         ADVANCE_LP_RING();
7326 out:
7327         return ret;
7328 }
7329
7330 static int intel_gen3_queue_flip(struct drm_device *dev,
7331                                  struct drm_crtc *crtc,
7332                                  struct drm_framebuffer *fb,
7333                                  struct drm_i915_gem_object *obj)
7334 {
7335         struct drm_i915_private *dev_priv = dev->dev_private;
7336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337         unsigned long offset;
7338         u32 flip_mask;
7339         int ret;
7340
7341         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7342         if (ret)
7343                 goto out;
7344
7345         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7346         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7347
7348         ret = BEGIN_LP_RING(6);
7349         if (ret)
7350                 goto out;
7351
7352         if (intel_crtc->plane)
7353                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7354         else
7355                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7356         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7357         OUT_RING(MI_NOOP);
7358         OUT_RING(MI_DISPLAY_FLIP_I915 |
7359                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7360         OUT_RING(fb->pitches[0]);
7361         OUT_RING(obj->gtt_offset + offset);
7362         OUT_RING(MI_NOOP);
7363
7364         ADVANCE_LP_RING();
7365 out:
7366         return ret;
7367 }
7368
7369 static int intel_gen4_queue_flip(struct drm_device *dev,
7370                                  struct drm_crtc *crtc,
7371                                  struct drm_framebuffer *fb,
7372                                  struct drm_i915_gem_object *obj)
7373 {
7374         struct drm_i915_private *dev_priv = dev->dev_private;
7375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7376         uint32_t pf, pipesrc;
7377         int ret;
7378
7379         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7380         if (ret)
7381                 goto out;
7382
7383         ret = BEGIN_LP_RING(4);
7384         if (ret)
7385                 goto out;
7386
7387         /* i965+ uses the linear or tiled offsets from the
7388          * Display Registers (which do not change across a page-flip)
7389          * so we need only reprogram the base address.
7390          */
7391         OUT_RING(MI_DISPLAY_FLIP |
7392                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7393         OUT_RING(fb->pitches[0]);
7394         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7395
7396         /* XXX Enabling the panel-fitter across page-flip is so far
7397          * untested on non-native modes, so ignore it for now.
7398          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7399          */
7400         pf = 0;
7401         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7402         OUT_RING(pf | pipesrc);
7403         ADVANCE_LP_RING();
7404 out:
7405         return ret;
7406 }
7407
7408 static int intel_gen6_queue_flip(struct drm_device *dev,
7409                                  struct drm_crtc *crtc,
7410                                  struct drm_framebuffer *fb,
7411                                  struct drm_i915_gem_object *obj)
7412 {
7413         struct drm_i915_private *dev_priv = dev->dev_private;
7414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415         uint32_t pf, pipesrc;
7416         int ret;
7417
7418         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7419         if (ret)
7420                 goto out;
7421
7422         ret = BEGIN_LP_RING(4);
7423         if (ret)
7424                 goto out;
7425
7426         OUT_RING(MI_DISPLAY_FLIP |
7427                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7428         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7429         OUT_RING(obj->gtt_offset);
7430
7431         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7432         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7433         OUT_RING(pf | pipesrc);
7434         ADVANCE_LP_RING();
7435 out:
7436         return ret;
7437 }
7438
7439 /*
7440  * On gen7 we currently use the blit ring because (in early silicon at least)
7441  * the render ring doesn't give us interrpts for page flip completion, which
7442  * means clients will hang after the first flip is queued.  Fortunately the
7443  * blit ring generates interrupts properly, so use it instead.
7444  */
7445 static int intel_gen7_queue_flip(struct drm_device *dev,
7446                                  struct drm_crtc *crtc,
7447                                  struct drm_framebuffer *fb,
7448                                  struct drm_i915_gem_object *obj)
7449 {
7450         struct drm_i915_private *dev_priv = dev->dev_private;
7451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7452         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7453         int ret;
7454
7455         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7456         if (ret)
7457                 goto out;
7458
7459         ret = intel_ring_begin(ring, 4);
7460         if (ret)
7461                 goto out;
7462
7463         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7464         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7465         intel_ring_emit(ring, (obj->gtt_offset));
7466         intel_ring_emit(ring, (MI_NOOP));
7467         intel_ring_advance(ring);
7468 out:
7469         return ret;
7470 }
7471
7472 static int intel_default_queue_flip(struct drm_device *dev,
7473                                     struct drm_crtc *crtc,
7474                                     struct drm_framebuffer *fb,
7475                                     struct drm_i915_gem_object *obj)
7476 {
7477         return -ENODEV;
7478 }
7479
7480 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7481                                 struct drm_framebuffer *fb,
7482                                 struct drm_pending_vblank_event *event)
7483 {
7484         struct drm_device *dev = crtc->dev;
7485         struct drm_i915_private *dev_priv = dev->dev_private;
7486         struct intel_framebuffer *intel_fb;
7487         struct drm_i915_gem_object *obj;
7488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7489         struct intel_unpin_work *work;
7490         unsigned long flags;
7491         int ret;
7492
7493         work = kzalloc(sizeof *work, GFP_KERNEL);
7494         if (work == NULL)
7495                 return -ENOMEM;
7496
7497         work->event = event;
7498         work->dev = crtc->dev;
7499         intel_fb = to_intel_framebuffer(crtc->fb);
7500         work->old_fb_obj = intel_fb->obj;
7501         INIT_WORK(&work->work, intel_unpin_work_fn);
7502
7503         ret = drm_vblank_get(dev, intel_crtc->pipe);
7504         if (ret)
7505                 goto free_work;
7506
7507         /* We borrow the event spin lock for protecting unpin_work */
7508         spin_lock_irqsave(&dev->event_lock, flags);
7509         if (intel_crtc->unpin_work) {
7510                 spin_unlock_irqrestore(&dev->event_lock, flags);
7511                 kfree(work);
7512                 drm_vblank_put(dev, intel_crtc->pipe);
7513
7514                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7515                 return -EBUSY;
7516         }
7517         intel_crtc->unpin_work = work;
7518         spin_unlock_irqrestore(&dev->event_lock, flags);
7519
7520         intel_fb = to_intel_framebuffer(fb);
7521         obj = intel_fb->obj;
7522
7523         mutex_lock(&dev->struct_mutex);
7524
7525         /* Reference the objects for the scheduled work. */
7526         drm_gem_object_reference(&work->old_fb_obj->base);
7527         drm_gem_object_reference(&obj->base);
7528
7529         crtc->fb = fb;
7530
7531         work->pending_flip_obj = obj;
7532
7533         work->enable_stall_check = true;
7534
7535         /* Block clients from rendering to the new back buffer until
7536          * the flip occurs and the object is no longer visible.
7537          */
7538         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7539
7540         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7541         if (ret)
7542                 goto cleanup_pending;
7543
7544         intel_disable_fbc(dev);
7545         mutex_unlock(&dev->struct_mutex);
7546
7547         trace_i915_flip_request(intel_crtc->plane, obj);
7548
7549         return 0;
7550
7551 cleanup_pending:
7552         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7553         drm_gem_object_unreference(&work->old_fb_obj->base);
7554         drm_gem_object_unreference(&obj->base);
7555         mutex_unlock(&dev->struct_mutex);
7556
7557         spin_lock_irqsave(&dev->event_lock, flags);
7558         intel_crtc->unpin_work = NULL;
7559         spin_unlock_irqrestore(&dev->event_lock, flags);
7560
7561         drm_vblank_put(dev, intel_crtc->pipe);
7562 free_work:
7563         kfree(work);
7564
7565         return ret;
7566 }
7567
7568 static void intel_sanitize_modesetting(struct drm_device *dev,
7569                                        int pipe, int plane)
7570 {
7571         struct drm_i915_private *dev_priv = dev->dev_private;
7572         u32 reg, val;
7573
7574         if (HAS_PCH_SPLIT(dev))
7575                 return;
7576
7577         /* Who knows what state these registers were left in by the BIOS or
7578          * grub?
7579          *
7580          * If we leave the registers in a conflicting state (e.g. with the
7581          * display plane reading from the other pipe than the one we intend
7582          * to use) then when we attempt to teardown the active mode, we will
7583          * not disable the pipes and planes in the correct order -- leaving
7584          * a plane reading from a disabled pipe and possibly leading to
7585          * undefined behaviour.
7586          */
7587
7588         reg = DSPCNTR(plane);
7589         val = I915_READ(reg);
7590
7591         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7592                 return;
7593         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7594                 return;
7595
7596         /* This display plane is active and attached to the other CPU pipe. */
7597         pipe = !pipe;
7598
7599         /* Disable the plane and wait for it to stop reading from the pipe. */
7600         intel_disable_plane(dev_priv, plane, pipe);
7601         intel_disable_pipe(dev_priv, pipe);
7602 }
7603
7604 static void intel_crtc_reset(struct drm_crtc *crtc)
7605 {
7606         struct drm_device *dev = crtc->dev;
7607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7608
7609         /* Reset flags back to the 'unknown' status so that they
7610          * will be correctly set on the initial modeset.
7611          */
7612         intel_crtc->dpms_mode = -1;
7613
7614         /* We need to fix up any BIOS configuration that conflicts with
7615          * our expectations.
7616          */
7617         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7618 }
7619
7620 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7621         .dpms = intel_crtc_dpms,
7622         .mode_fixup = intel_crtc_mode_fixup,
7623         .mode_set = intel_crtc_mode_set,
7624         .mode_set_base = intel_pipe_set_base,
7625         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7626         .load_lut = intel_crtc_load_lut,
7627         .disable = intel_crtc_disable,
7628 };
7629
7630 static const struct drm_crtc_funcs intel_crtc_funcs = {
7631         .reset = intel_crtc_reset,
7632         .cursor_set = intel_crtc_cursor_set,
7633         .cursor_move = intel_crtc_cursor_move,
7634         .gamma_set = intel_crtc_gamma_set,
7635         .set_config = drm_crtc_helper_set_config,
7636         .destroy = intel_crtc_destroy,
7637         .page_flip = intel_crtc_page_flip,
7638 };
7639
7640 static void intel_crtc_init(struct drm_device *dev, int pipe)
7641 {
7642         drm_i915_private_t *dev_priv = dev->dev_private;
7643         struct intel_crtc *intel_crtc;
7644         int i;
7645
7646         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7647         if (intel_crtc == NULL)
7648                 return;
7649
7650         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7651
7652         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7653         for (i = 0; i < 256; i++) {
7654                 intel_crtc->lut_r[i] = i;
7655                 intel_crtc->lut_g[i] = i;
7656                 intel_crtc->lut_b[i] = i;
7657         }
7658
7659         /* Swap pipes & planes for FBC on pre-965 */
7660         intel_crtc->pipe = pipe;
7661         intel_crtc->plane = pipe;
7662         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7663                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7664                 intel_crtc->plane = !pipe;
7665         }
7666
7667         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7668                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7669         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7670         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7671
7672         intel_crtc_reset(&intel_crtc->base);
7673         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7674         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7675
7676         if (HAS_PCH_SPLIT(dev)) {
7677                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7678                         intel_crtc->no_pll = true;
7679                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7680                 intel_helper_funcs.commit = ironlake_crtc_commit;
7681         } else {
7682                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7683                 intel_helper_funcs.commit = i9xx_crtc_commit;
7684         }
7685
7686         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7687
7688         intel_crtc->busy = false;
7689
7690         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7691                     (unsigned long)intel_crtc);
7692 }
7693
7694 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7695                                 struct drm_file *file)
7696 {
7697         drm_i915_private_t *dev_priv = dev->dev_private;
7698         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7699         struct drm_mode_object *drmmode_obj;
7700         struct intel_crtc *crtc;
7701
7702         if (!dev_priv) {
7703                 DRM_ERROR("called with no initialization\n");
7704                 return -EINVAL;
7705         }
7706
7707         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7708                         DRM_MODE_OBJECT_CRTC);
7709
7710         if (!drmmode_obj) {
7711                 DRM_ERROR("no such CRTC id\n");
7712                 return -EINVAL;
7713         }
7714
7715         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7716         pipe_from_crtc_id->pipe = crtc->pipe;
7717
7718         return 0;
7719 }
7720
7721 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7722 {
7723         struct intel_encoder *encoder;
7724         int index_mask = 0;
7725         int entry = 0;
7726
7727         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7728                 if (type_mask & encoder->clone_mask)
7729                         index_mask |= (1 << entry);
7730                 entry++;
7731         }
7732
7733         return index_mask;
7734 }
7735
7736 static bool has_edp_a(struct drm_device *dev)
7737 {
7738         struct drm_i915_private *dev_priv = dev->dev_private;
7739
7740         if (!IS_MOBILE(dev))
7741                 return false;
7742
7743         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7744                 return false;
7745
7746         if (IS_GEN5(dev) &&
7747             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7748                 return false;
7749
7750         return true;
7751 }
7752
7753 static void intel_setup_outputs(struct drm_device *dev)
7754 {
7755         struct drm_i915_private *dev_priv = dev->dev_private;
7756         struct intel_encoder *encoder;
7757         bool dpd_is_edp = false;
7758         bool has_lvds;
7759
7760         has_lvds = intel_lvds_init(dev);
7761         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7762                 /* disable the panel fitter on everything but LVDS */
7763                 I915_WRITE(PFIT_CONTROL, 0);
7764         }
7765
7766         if (HAS_PCH_SPLIT(dev)) {
7767                 dpd_is_edp = intel_dpd_is_edp(dev);
7768
7769                 if (has_edp_a(dev))
7770                         intel_dp_init(dev, DP_A);
7771
7772                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7773                         intel_dp_init(dev, PCH_DP_D);
7774         }
7775
7776         intel_crt_init(dev);
7777
7778         if (HAS_PCH_SPLIT(dev)) {
7779                 int found;
7780
7781                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7782                         /* PCH SDVOB multiplex with HDMIB */
7783                         found = intel_sdvo_init(dev, PCH_SDVOB);
7784                         if (!found)
7785                                 intel_hdmi_init(dev, HDMIB);
7786                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7787                                 intel_dp_init(dev, PCH_DP_B);
7788                 }
7789
7790                 if (I915_READ(HDMIC) & PORT_DETECTED)
7791                         intel_hdmi_init(dev, HDMIC);
7792
7793                 if (I915_READ(HDMID) & PORT_DETECTED)
7794                         intel_hdmi_init(dev, HDMID);
7795
7796                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7797                         intel_dp_init(dev, PCH_DP_C);
7798
7799                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7800                         intel_dp_init(dev, PCH_DP_D);
7801
7802         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7803                 bool found = false;
7804
7805                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7806                         DRM_DEBUG_KMS("probing SDVOB\n");
7807                         found = intel_sdvo_init(dev, SDVOB);
7808                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7809                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7810                                 intel_hdmi_init(dev, SDVOB);
7811                         }
7812
7813                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7814                                 DRM_DEBUG_KMS("probing DP_B\n");
7815                                 intel_dp_init(dev, DP_B);
7816                         }
7817                 }
7818
7819                 /* Before G4X SDVOC doesn't have its own detect register */
7820
7821                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7822                         DRM_DEBUG_KMS("probing SDVOC\n");
7823                         found = intel_sdvo_init(dev, SDVOC);
7824                 }
7825
7826                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7827
7828                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7829                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7830                                 intel_hdmi_init(dev, SDVOC);
7831                         }
7832                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7833                                 DRM_DEBUG_KMS("probing DP_C\n");
7834                                 intel_dp_init(dev, DP_C);
7835                         }
7836                 }
7837
7838                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7839                     (I915_READ(DP_D) & DP_DETECTED)) {
7840                         DRM_DEBUG_KMS("probing DP_D\n");
7841                         intel_dp_init(dev, DP_D);
7842                 }
7843         } else if (IS_GEN2(dev))
7844                 intel_dvo_init(dev);
7845
7846         if (SUPPORTS_TV(dev))
7847                 intel_tv_init(dev);
7848
7849         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7850                 encoder->base.possible_crtcs = encoder->crtc_mask;
7851                 encoder->base.possible_clones =
7852                         intel_encoder_clones(dev, encoder->clone_mask);
7853         }
7854
7855         /* disable all the possible outputs/crtcs before entering KMS mode */
7856         drm_helper_disable_unused_functions(dev);
7857
7858         if (HAS_PCH_SPLIT(dev))
7859                 ironlake_init_pch_refclk(dev);
7860 }
7861
7862 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7863 {
7864         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7865
7866         drm_framebuffer_cleanup(fb);
7867         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7868
7869         kfree(intel_fb);
7870 }
7871
7872 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7873                                                 struct drm_file *file,
7874                                                 unsigned int *handle)
7875 {
7876         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7877         struct drm_i915_gem_object *obj = intel_fb->obj;
7878
7879         return drm_gem_handle_create(file, &obj->base, handle);
7880 }
7881
7882 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7883         .destroy = intel_user_framebuffer_destroy,
7884         .create_handle = intel_user_framebuffer_create_handle,
7885 };
7886
7887 int intel_framebuffer_init(struct drm_device *dev,
7888                            struct intel_framebuffer *intel_fb,
7889                            struct drm_mode_fb_cmd2 *mode_cmd,
7890                            struct drm_i915_gem_object *obj)
7891 {
7892         int ret;
7893
7894         if (obj->tiling_mode == I915_TILING_Y)
7895                 return -EINVAL;
7896
7897         if (mode_cmd->pitches[0] & 63)
7898                 return -EINVAL;
7899
7900         switch (mode_cmd->pixel_format) {
7901         case DRM_FORMAT_RGB332:
7902         case DRM_FORMAT_RGB565:
7903         case DRM_FORMAT_XRGB8888:
7904         case DRM_FORMAT_ARGB8888:
7905         case DRM_FORMAT_XRGB2101010:
7906         case DRM_FORMAT_ARGB2101010:
7907                 /* RGB formats are common across chipsets */
7908                 break;
7909         case DRM_FORMAT_YUYV:
7910         case DRM_FORMAT_UYVY:
7911         case DRM_FORMAT_YVYU:
7912         case DRM_FORMAT_VYUY:
7913                 break;
7914         default:
7915                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7916                                 mode_cmd->pixel_format);
7917                 return -EINVAL;
7918         }
7919
7920         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7921         if (ret) {
7922                 DRM_ERROR("framebuffer init failed %d\n", ret);
7923                 return ret;
7924         }
7925
7926         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7927         intel_fb->obj = obj;
7928         return 0;
7929 }
7930
7931 static struct drm_framebuffer *
7932 intel_user_framebuffer_create(struct drm_device *dev,
7933                               struct drm_file *filp,
7934                               struct drm_mode_fb_cmd2 *mode_cmd)
7935 {
7936         struct drm_i915_gem_object *obj;
7937
7938         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7939                                                 mode_cmd->handles[0]));
7940         if (&obj->base == NULL)
7941                 return ERR_PTR(-ENOENT);
7942
7943         return intel_framebuffer_create(dev, mode_cmd, obj);
7944 }
7945
7946 static const struct drm_mode_config_funcs intel_mode_funcs = {
7947         .fb_create = intel_user_framebuffer_create,
7948         .output_poll_changed = intel_fb_output_poll_changed,
7949 };
7950
7951 static struct drm_i915_gem_object *
7952 intel_alloc_context_page(struct drm_device *dev)
7953 {
7954         struct drm_i915_gem_object *ctx;
7955         int ret;
7956
7957         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7958
7959         ctx = i915_gem_alloc_object(dev, 4096);
7960         if (!ctx) {
7961                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7962                 return NULL;
7963         }
7964
7965         ret = i915_gem_object_pin(ctx, 4096, true);
7966         if (ret) {
7967                 DRM_ERROR("failed to pin power context: %d\n", ret);
7968                 goto err_unref;
7969         }
7970
7971         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7972         if (ret) {
7973                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7974                 goto err_unpin;
7975         }
7976
7977         return ctx;
7978
7979 err_unpin:
7980         i915_gem_object_unpin(ctx);
7981 err_unref:
7982         drm_gem_object_unreference(&ctx->base);
7983         mutex_unlock(&dev->struct_mutex);
7984         return NULL;
7985 }
7986
7987 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7988 {
7989         struct drm_i915_private *dev_priv = dev->dev_private;
7990         u16 rgvswctl;
7991
7992         rgvswctl = I915_READ16(MEMSWCTL);
7993         if (rgvswctl & MEMCTL_CMD_STS) {
7994                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7995                 return false; /* still busy with another command */
7996         }
7997
7998         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7999                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8000         I915_WRITE16(MEMSWCTL, rgvswctl);
8001         POSTING_READ16(MEMSWCTL);
8002
8003         rgvswctl |= MEMCTL_CMD_STS;
8004         I915_WRITE16(MEMSWCTL, rgvswctl);
8005
8006         return true;
8007 }
8008
8009 void ironlake_enable_drps(struct drm_device *dev)
8010 {
8011         struct drm_i915_private *dev_priv = dev->dev_private;
8012         u32 rgvmodectl = I915_READ(MEMMODECTL);
8013         u8 fmax, fmin, fstart, vstart;
8014
8015         /* Enable temp reporting */
8016         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8017         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8018
8019         /* 100ms RC evaluation intervals */
8020         I915_WRITE(RCUPEI, 100000);
8021         I915_WRITE(RCDNEI, 100000);
8022
8023         /* Set max/min thresholds to 90ms and 80ms respectively */
8024         I915_WRITE(RCBMAXAVG, 90000);
8025         I915_WRITE(RCBMINAVG, 80000);
8026
8027         I915_WRITE(MEMIHYST, 1);
8028
8029         /* Set up min, max, and cur for interrupt handling */
8030         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8031         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8032         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8033                 MEMMODE_FSTART_SHIFT;
8034
8035         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8036                 PXVFREQ_PX_SHIFT;
8037
8038         dev_priv->fmax = fmax; /* IPS callback will increase this */
8039         dev_priv->fstart = fstart;
8040
8041         dev_priv->max_delay = fstart;
8042         dev_priv->min_delay = fmin;
8043         dev_priv->cur_delay = fstart;
8044
8045         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8046                          fmax, fmin, fstart);
8047
8048         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8049
8050         /*
8051          * Interrupts will be enabled in ironlake_irq_postinstall
8052          */
8053
8054         I915_WRITE(VIDSTART, vstart);
8055         POSTING_READ(VIDSTART);
8056
8057         rgvmodectl |= MEMMODE_SWMODE_EN;
8058         I915_WRITE(MEMMODECTL, rgvmodectl);
8059
8060         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8061                 DRM_ERROR("stuck trying to change perf mode\n");
8062         msleep(1);
8063
8064         ironlake_set_drps(dev, fstart);
8065
8066         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8067                 I915_READ(0x112e0);
8068         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8069         dev_priv->last_count2 = I915_READ(0x112f4);
8070         getrawmonotonic(&dev_priv->last_time2);
8071 }
8072
8073 void ironlake_disable_drps(struct drm_device *dev)
8074 {
8075         struct drm_i915_private *dev_priv = dev->dev_private;
8076         u16 rgvswctl = I915_READ16(MEMSWCTL);
8077
8078         /* Ack interrupts, disable EFC interrupt */
8079         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8080         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8081         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8082         I915_WRITE(DEIIR, DE_PCU_EVENT);
8083         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8084
8085         /* Go back to the starting frequency */
8086         ironlake_set_drps(dev, dev_priv->fstart);
8087         msleep(1);
8088         rgvswctl |= MEMCTL_CMD_STS;
8089         I915_WRITE(MEMSWCTL, rgvswctl);
8090         msleep(1);
8091
8092 }
8093
8094 void gen6_set_rps(struct drm_device *dev, u8 val)
8095 {
8096         struct drm_i915_private *dev_priv = dev->dev_private;
8097         u32 swreq;
8098
8099         swreq = (val & 0x3ff) << 25;
8100         I915_WRITE(GEN6_RPNSWREQ, swreq);
8101 }
8102
8103 void gen6_disable_rps(struct drm_device *dev)
8104 {
8105         struct drm_i915_private *dev_priv = dev->dev_private;
8106
8107         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8108         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8109         I915_WRITE(GEN6_PMIER, 0);
8110         /* Complete PM interrupt masking here doesn't race with the rps work
8111          * item again unmasking PM interrupts because that is using a different
8112          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8113          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8114
8115         spin_lock_irq(&dev_priv->rps_lock);
8116         dev_priv->pm_iir = 0;
8117         spin_unlock_irq(&dev_priv->rps_lock);
8118
8119         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8120 }
8121
8122 static unsigned long intel_pxfreq(u32 vidfreq)
8123 {
8124         unsigned long freq;
8125         int div = (vidfreq & 0x3f0000) >> 16;
8126         int post = (vidfreq & 0x3000) >> 12;
8127         int pre = (vidfreq & 0x7);
8128
8129         if (!pre)
8130                 return 0;
8131
8132         freq = ((div * 133333) / ((1<<post) * pre));
8133
8134         return freq;
8135 }
8136
8137 void intel_init_emon(struct drm_device *dev)
8138 {
8139         struct drm_i915_private *dev_priv = dev->dev_private;
8140         u32 lcfuse;
8141         u8 pxw[16];
8142         int i;
8143
8144         /* Disable to program */
8145         I915_WRITE(ECR, 0);
8146         POSTING_READ(ECR);
8147
8148         /* Program energy weights for various events */
8149         I915_WRITE(SDEW, 0x15040d00);
8150         I915_WRITE(CSIEW0, 0x007f0000);
8151         I915_WRITE(CSIEW1, 0x1e220004);
8152         I915_WRITE(CSIEW2, 0x04000004);
8153
8154         for (i = 0; i < 5; i++)
8155                 I915_WRITE(PEW + (i * 4), 0);
8156         for (i = 0; i < 3; i++)
8157                 I915_WRITE(DEW + (i * 4), 0);
8158
8159         /* Program P-state weights to account for frequency power adjustment */
8160         for (i = 0; i < 16; i++) {
8161                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8162                 unsigned long freq = intel_pxfreq(pxvidfreq);
8163                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8164                         PXVFREQ_PX_SHIFT;
8165                 unsigned long val;
8166
8167                 val = vid * vid;
8168                 val *= (freq / 1000);
8169                 val *= 255;
8170                 val /= (127*127*900);
8171                 if (val > 0xff)
8172                         DRM_ERROR("bad pxval: %ld\n", val);
8173                 pxw[i] = val;
8174         }
8175         /* Render standby states get 0 weight */
8176         pxw[14] = 0;
8177         pxw[15] = 0;
8178
8179         for (i = 0; i < 4; i++) {
8180                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8181                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8182                 I915_WRITE(PXW + (i * 4), val);
8183         }
8184
8185         /* Adjust magic regs to magic values (more experimental results) */
8186         I915_WRITE(OGW0, 0);
8187         I915_WRITE(OGW1, 0);
8188         I915_WRITE(EG0, 0x00007f00);
8189         I915_WRITE(EG1, 0x0000000e);
8190         I915_WRITE(EG2, 0x000e0000);
8191         I915_WRITE(EG3, 0x68000300);
8192         I915_WRITE(EG4, 0x42000000);
8193         I915_WRITE(EG5, 0x00140031);
8194         I915_WRITE(EG6, 0);
8195         I915_WRITE(EG7, 0);
8196
8197         for (i = 0; i < 8; i++)
8198                 I915_WRITE(PXWL + (i * 4), 0);
8199
8200         /* Enable PMON + select events */
8201         I915_WRITE(ECR, 0x80000019);
8202
8203         lcfuse = I915_READ(LCFUSE02);
8204
8205         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8206 }
8207
8208 static bool intel_enable_rc6(struct drm_device *dev)
8209 {
8210         /*
8211          * Respect the kernel parameter if it is set
8212          */
8213         if (i915_enable_rc6 >= 0)
8214                 return i915_enable_rc6;
8215
8216         /*
8217          * Disable RC6 on Ironlake
8218          */
8219         if (INTEL_INFO(dev)->gen == 5)
8220                 return 0;
8221
8222         /*
8223          * Disable rc6 on Sandybridge
8224          */
8225         if (INTEL_INFO(dev)->gen == 6) {
8226                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8227                 return 0;
8228         }
8229         DRM_DEBUG_DRIVER("RC6 enabled\n");
8230         return 1;
8231 }
8232
8233 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8234 {
8235         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8236         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8237         u32 pcu_mbox, rc6_mask = 0;
8238         u32 gtfifodbg;
8239         int cur_freq, min_freq, max_freq;
8240         int i;
8241
8242         /* Here begins a magic sequence of register writes to enable
8243          * auto-downclocking.
8244          *
8245          * Perhaps there might be some value in exposing these to
8246          * userspace...
8247          */
8248         I915_WRITE(GEN6_RC_STATE, 0);
8249         mutex_lock(&dev_priv->dev->struct_mutex);
8250
8251         /* Clear the DBG now so we don't confuse earlier errors */
8252         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8253                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8254                 I915_WRITE(GTFIFODBG, gtfifodbg);
8255         }
8256
8257         gen6_gt_force_wake_get(dev_priv);
8258
8259         /* disable the counters and set deterministic thresholds */
8260         I915_WRITE(GEN6_RC_CONTROL, 0);
8261
8262         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8263         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8264         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8265         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8266         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8267
8268         for (i = 0; i < I915_NUM_RINGS; i++)
8269                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8270
8271         I915_WRITE(GEN6_RC_SLEEP, 0);
8272         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8273         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8274         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8275         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8276
8277         if (intel_enable_rc6(dev_priv->dev))
8278                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8279                         GEN6_RC_CTL_RC6_ENABLE;
8280
8281         I915_WRITE(GEN6_RC_CONTROL,
8282                    rc6_mask |
8283                    GEN6_RC_CTL_EI_MODE(1) |
8284                    GEN6_RC_CTL_HW_ENABLE);
8285
8286         I915_WRITE(GEN6_RPNSWREQ,
8287                    GEN6_FREQUENCY(10) |
8288                    GEN6_OFFSET(0) |
8289                    GEN6_AGGRESSIVE_TURBO);
8290         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8291                    GEN6_FREQUENCY(12));
8292
8293         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8294         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8295                    18 << 24 |
8296                    6 << 16);
8297         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8298         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8299         I915_WRITE(GEN6_RP_UP_EI, 100000);
8300         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8301         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8302         I915_WRITE(GEN6_RP_CONTROL,
8303                    GEN6_RP_MEDIA_TURBO |
8304                    GEN6_RP_MEDIA_HW_MODE |
8305                    GEN6_RP_MEDIA_IS_GFX |
8306                    GEN6_RP_ENABLE |
8307                    GEN6_RP_UP_BUSY_AVG |
8308                    GEN6_RP_DOWN_IDLE_CONT);
8309
8310         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8311                      500))
8312                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8313
8314         I915_WRITE(GEN6_PCODE_DATA, 0);
8315         I915_WRITE(GEN6_PCODE_MAILBOX,
8316                    GEN6_PCODE_READY |
8317                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8318         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8319                      500))
8320                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8321
8322         min_freq = (rp_state_cap & 0xff0000) >> 16;
8323         max_freq = rp_state_cap & 0xff;
8324         cur_freq = (gt_perf_status & 0xff00) >> 8;
8325
8326         /* Check for overclock support */
8327         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8328                      500))
8329                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8330         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8331         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8332         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8333                      500))
8334                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8335         if (pcu_mbox & (1<<31)) { /* OC supported */
8336                 max_freq = pcu_mbox & 0xff;
8337                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8338         }
8339
8340         /* In units of 100MHz */
8341         dev_priv->max_delay = max_freq;
8342         dev_priv->min_delay = min_freq;
8343         dev_priv->cur_delay = cur_freq;
8344
8345         /* requires MSI enabled */
8346         I915_WRITE(GEN6_PMIER,
8347                    GEN6_PM_MBOX_EVENT |
8348                    GEN6_PM_THERMAL_EVENT |
8349                    GEN6_PM_RP_DOWN_TIMEOUT |
8350                    GEN6_PM_RP_UP_THRESHOLD |
8351                    GEN6_PM_RP_DOWN_THRESHOLD |
8352                    GEN6_PM_RP_UP_EI_EXPIRED |
8353                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8354         spin_lock_irq(&dev_priv->rps_lock);
8355         WARN_ON(dev_priv->pm_iir != 0);
8356         I915_WRITE(GEN6_PMIMR, 0);
8357         spin_unlock_irq(&dev_priv->rps_lock);
8358         /* enable all PM interrupts */
8359         I915_WRITE(GEN6_PMINTRMSK, 0);
8360
8361         gen6_gt_force_wake_put(dev_priv);
8362         mutex_unlock(&dev_priv->dev->struct_mutex);
8363 }
8364
8365 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8366 {
8367         int min_freq = 15;
8368         int gpu_freq, ia_freq, max_ia_freq;
8369         int scaling_factor = 180;
8370
8371         max_ia_freq = cpufreq_quick_get_max(0);
8372         /*
8373          * Default to measured freq if none found, PCU will ensure we don't go
8374          * over
8375          */
8376         if (!max_ia_freq)
8377                 max_ia_freq = tsc_khz;
8378
8379         /* Convert from kHz to MHz */
8380         max_ia_freq /= 1000;
8381
8382         mutex_lock(&dev_priv->dev->struct_mutex);
8383
8384         /*
8385          * For each potential GPU frequency, load a ring frequency we'd like
8386          * to use for memory access.  We do this by specifying the IA frequency
8387          * the PCU should use as a reference to determine the ring frequency.
8388          */
8389         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8390              gpu_freq--) {
8391                 int diff = dev_priv->max_delay - gpu_freq;
8392
8393                 /*
8394                  * For GPU frequencies less than 750MHz, just use the lowest
8395                  * ring freq.
8396                  */
8397                 if (gpu_freq < min_freq)
8398                         ia_freq = 800;
8399                 else
8400                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8401                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8402
8403                 I915_WRITE(GEN6_PCODE_DATA,
8404                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8405                            gpu_freq);
8406                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8407                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8408                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8409                               GEN6_PCODE_READY) == 0, 10)) {
8410                         DRM_ERROR("pcode write of freq table timed out\n");
8411                         continue;
8412                 }
8413         }
8414
8415         mutex_unlock(&dev_priv->dev->struct_mutex);
8416 }
8417
8418 static void ironlake_init_clock_gating(struct drm_device *dev)
8419 {
8420         struct drm_i915_private *dev_priv = dev->dev_private;
8421         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8422
8423         /* Required for FBC */
8424         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8425                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8426                 DPFDUNIT_CLOCK_GATE_DISABLE;
8427         /* Required for CxSR */
8428         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8429
8430         I915_WRITE(PCH_3DCGDIS0,
8431                    MARIUNIT_CLOCK_GATE_DISABLE |
8432                    SVSMUNIT_CLOCK_GATE_DISABLE);
8433         I915_WRITE(PCH_3DCGDIS1,
8434                    VFMUNIT_CLOCK_GATE_DISABLE);
8435
8436         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8437
8438         /*
8439          * According to the spec the following bits should be set in
8440          * order to enable memory self-refresh
8441          * The bit 22/21 of 0x42004
8442          * The bit 5 of 0x42020
8443          * The bit 15 of 0x45000
8444          */
8445         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8446                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8447                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8448         I915_WRITE(ILK_DSPCLK_GATE,
8449                    (I915_READ(ILK_DSPCLK_GATE) |
8450                     ILK_DPARB_CLK_GATE));
8451         I915_WRITE(DISP_ARB_CTL,
8452                    (I915_READ(DISP_ARB_CTL) |
8453                     DISP_FBC_WM_DIS));
8454         I915_WRITE(WM3_LP_ILK, 0);
8455         I915_WRITE(WM2_LP_ILK, 0);
8456         I915_WRITE(WM1_LP_ILK, 0);
8457
8458         /*
8459          * Based on the document from hardware guys the following bits
8460          * should be set unconditionally in order to enable FBC.
8461          * The bit 22 of 0x42000
8462          * The bit 22 of 0x42004
8463          * The bit 7,8,9 of 0x42020.
8464          */
8465         if (IS_IRONLAKE_M(dev)) {
8466                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8467                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8468                            ILK_FBCQ_DIS);
8469                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8470                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8471                            ILK_DPARB_GATE);
8472                 I915_WRITE(ILK_DSPCLK_GATE,
8473                            I915_READ(ILK_DSPCLK_GATE) |
8474                            ILK_DPFC_DIS1 |
8475                            ILK_DPFC_DIS2 |
8476                            ILK_CLK_FBC);
8477         }
8478
8479         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8480                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8481                    ILK_ELPIN_409_SELECT);
8482         I915_WRITE(_3D_CHICKEN2,
8483                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8484                    _3D_CHICKEN2_WM_READ_PIPELINED);
8485 }
8486
8487 static void gen6_init_clock_gating(struct drm_device *dev)
8488 {
8489         struct drm_i915_private *dev_priv = dev->dev_private;
8490         int pipe;
8491         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8492
8493         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8494
8495         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8496                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8497                    ILK_ELPIN_409_SELECT);
8498
8499         I915_WRITE(WM3_LP_ILK, 0);
8500         I915_WRITE(WM2_LP_ILK, 0);
8501         I915_WRITE(WM1_LP_ILK, 0);
8502
8503         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8504          * gating disable must be set.  Failure to set it results in
8505          * flickering pixels due to Z write ordering failures after
8506          * some amount of runtime in the Mesa "fire" demo, and Unigine
8507          * Sanctuary and Tropics, and apparently anything else with
8508          * alpha test or pixel discard.
8509          *
8510          * According to the spec, bit 11 (RCCUNIT) must also be set,
8511          * but we didn't debug actual testcases to find it out.
8512          */
8513         I915_WRITE(GEN6_UCGCTL2,
8514                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8515                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8516
8517         /*
8518          * According to the spec the following bits should be
8519          * set in order to enable memory self-refresh and fbc:
8520          * The bit21 and bit22 of 0x42000
8521          * The bit21 and bit22 of 0x42004
8522          * The bit5 and bit7 of 0x42020
8523          * The bit14 of 0x70180
8524          * The bit14 of 0x71180
8525          */
8526         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8527                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8528                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8529         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8530                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8531                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8532         I915_WRITE(ILK_DSPCLK_GATE,
8533                    I915_READ(ILK_DSPCLK_GATE) |
8534                    ILK_DPARB_CLK_GATE  |
8535                    ILK_DPFD_CLK_GATE);
8536
8537         for_each_pipe(pipe) {
8538                 I915_WRITE(DSPCNTR(pipe),
8539                            I915_READ(DSPCNTR(pipe)) |
8540                            DISPPLANE_TRICKLE_FEED_DISABLE);
8541                 intel_flush_display_plane(dev_priv, pipe);
8542         }
8543 }
8544
8545 static void ivybridge_init_clock_gating(struct drm_device *dev)
8546 {
8547         struct drm_i915_private *dev_priv = dev->dev_private;
8548         int pipe;
8549         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8550
8551         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8552
8553         I915_WRITE(WM3_LP_ILK, 0);
8554         I915_WRITE(WM2_LP_ILK, 0);
8555         I915_WRITE(WM1_LP_ILK, 0);
8556
8557         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8558
8559         I915_WRITE(IVB_CHICKEN3,
8560                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8561                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8562
8563         for_each_pipe(pipe) {
8564                 I915_WRITE(DSPCNTR(pipe),
8565                            I915_READ(DSPCNTR(pipe)) |
8566                            DISPPLANE_TRICKLE_FEED_DISABLE);
8567                 intel_flush_display_plane(dev_priv, pipe);
8568         }
8569 }
8570
8571 static void g4x_init_clock_gating(struct drm_device *dev)
8572 {
8573         struct drm_i915_private *dev_priv = dev->dev_private;
8574         uint32_t dspclk_gate;
8575
8576         I915_WRITE(RENCLK_GATE_D1, 0);
8577         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8578                    GS_UNIT_CLOCK_GATE_DISABLE |
8579                    CL_UNIT_CLOCK_GATE_DISABLE);
8580         I915_WRITE(RAMCLK_GATE_D, 0);
8581         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8582                 OVRUNIT_CLOCK_GATE_DISABLE |
8583                 OVCUNIT_CLOCK_GATE_DISABLE;
8584         if (IS_GM45(dev))
8585                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8586         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8587 }
8588
8589 static void crestline_init_clock_gating(struct drm_device *dev)
8590 {
8591         struct drm_i915_private *dev_priv = dev->dev_private;
8592
8593         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8594         I915_WRITE(RENCLK_GATE_D2, 0);
8595         I915_WRITE(DSPCLK_GATE_D, 0);
8596         I915_WRITE(RAMCLK_GATE_D, 0);
8597         I915_WRITE16(DEUC, 0);
8598 }
8599
8600 static void broadwater_init_clock_gating(struct drm_device *dev)
8601 {
8602         struct drm_i915_private *dev_priv = dev->dev_private;
8603
8604         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8605                    I965_RCC_CLOCK_GATE_DISABLE |
8606                    I965_RCPB_CLOCK_GATE_DISABLE |
8607                    I965_ISC_CLOCK_GATE_DISABLE |
8608                    I965_FBC_CLOCK_GATE_DISABLE);
8609         I915_WRITE(RENCLK_GATE_D2, 0);
8610 }
8611
8612 static void gen3_init_clock_gating(struct drm_device *dev)
8613 {
8614         struct drm_i915_private *dev_priv = dev->dev_private;
8615         u32 dstate = I915_READ(D_STATE);
8616
8617         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8618                 DSTATE_DOT_CLOCK_GATING;
8619         I915_WRITE(D_STATE, dstate);
8620 }
8621
8622 static void i85x_init_clock_gating(struct drm_device *dev)
8623 {
8624         struct drm_i915_private *dev_priv = dev->dev_private;
8625
8626         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8627 }
8628
8629 static void i830_init_clock_gating(struct drm_device *dev)
8630 {
8631         struct drm_i915_private *dev_priv = dev->dev_private;
8632
8633         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8634 }
8635
8636 static void ibx_init_clock_gating(struct drm_device *dev)
8637 {
8638         struct drm_i915_private *dev_priv = dev->dev_private;
8639
8640         /*
8641          * On Ibex Peak and Cougar Point, we need to disable clock
8642          * gating for the panel power sequencer or it will fail to
8643          * start up when no ports are active.
8644          */
8645         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8646 }
8647
8648 static void cpt_init_clock_gating(struct drm_device *dev)
8649 {
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         int pipe;
8652
8653         /*
8654          * On Ibex Peak and Cougar Point, we need to disable clock
8655          * gating for the panel power sequencer or it will fail to
8656          * start up when no ports are active.
8657          */
8658         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8659         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8660                    DPLS_EDP_PPS_FIX_DIS);
8661         /* Without this, mode sets may fail silently on FDI */
8662         for_each_pipe(pipe)
8663                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8664 }
8665
8666 static void ironlake_teardown_rc6(struct drm_device *dev)
8667 {
8668         struct drm_i915_private *dev_priv = dev->dev_private;
8669
8670         if (dev_priv->renderctx) {
8671                 i915_gem_object_unpin(dev_priv->renderctx);
8672                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8673                 dev_priv->renderctx = NULL;
8674         }
8675
8676         if (dev_priv->pwrctx) {
8677                 i915_gem_object_unpin(dev_priv->pwrctx);
8678                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8679                 dev_priv->pwrctx = NULL;
8680         }
8681 }
8682
8683 static void ironlake_disable_rc6(struct drm_device *dev)
8684 {
8685         struct drm_i915_private *dev_priv = dev->dev_private;
8686
8687         if (I915_READ(PWRCTXA)) {
8688                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8689                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8690                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8691                          50);
8692
8693                 I915_WRITE(PWRCTXA, 0);
8694                 POSTING_READ(PWRCTXA);
8695
8696                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8697                 POSTING_READ(RSTDBYCTL);
8698         }
8699
8700         ironlake_teardown_rc6(dev);
8701 }
8702
8703 static int ironlake_setup_rc6(struct drm_device *dev)
8704 {
8705         struct drm_i915_private *dev_priv = dev->dev_private;
8706
8707         if (dev_priv->renderctx == NULL)
8708                 dev_priv->renderctx = intel_alloc_context_page(dev);
8709         if (!dev_priv->renderctx)
8710                 return -ENOMEM;
8711
8712         if (dev_priv->pwrctx == NULL)
8713                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8714         if (!dev_priv->pwrctx) {
8715                 ironlake_teardown_rc6(dev);
8716                 return -ENOMEM;
8717         }
8718
8719         return 0;
8720 }
8721
8722 void ironlake_enable_rc6(struct drm_device *dev)
8723 {
8724         struct drm_i915_private *dev_priv = dev->dev_private;
8725         int ret;
8726
8727         /* rc6 disabled by default due to repeated reports of hanging during
8728          * boot and resume.
8729          */
8730         if (!intel_enable_rc6(dev))
8731                 return;
8732
8733         mutex_lock(&dev->struct_mutex);
8734         ret = ironlake_setup_rc6(dev);
8735         if (ret) {
8736                 mutex_unlock(&dev->struct_mutex);
8737                 return;
8738         }
8739
8740         /*
8741          * GPU can automatically power down the render unit if given a page
8742          * to save state.
8743          */
8744         ret = BEGIN_LP_RING(6);
8745         if (ret) {
8746                 ironlake_teardown_rc6(dev);
8747                 mutex_unlock(&dev->struct_mutex);
8748                 return;
8749         }
8750
8751         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8752         OUT_RING(MI_SET_CONTEXT);
8753         OUT_RING(dev_priv->renderctx->gtt_offset |
8754                  MI_MM_SPACE_GTT |
8755                  MI_SAVE_EXT_STATE_EN |
8756                  MI_RESTORE_EXT_STATE_EN |
8757                  MI_RESTORE_INHIBIT);
8758         OUT_RING(MI_SUSPEND_FLUSH);
8759         OUT_RING(MI_NOOP);
8760         OUT_RING(MI_FLUSH);
8761         ADVANCE_LP_RING();
8762
8763         /*
8764          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8765          * does an implicit flush, combined with MI_FLUSH above, it should be
8766          * safe to assume that renderctx is valid
8767          */
8768         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8769         if (ret) {
8770                 DRM_ERROR("failed to enable ironlake power power savings\n");
8771                 ironlake_teardown_rc6(dev);
8772                 mutex_unlock(&dev->struct_mutex);
8773                 return;
8774         }
8775
8776         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8777         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8778         mutex_unlock(&dev->struct_mutex);
8779 }
8780
8781 void intel_init_clock_gating(struct drm_device *dev)
8782 {
8783         struct drm_i915_private *dev_priv = dev->dev_private;
8784
8785         dev_priv->display.init_clock_gating(dev);
8786
8787         if (dev_priv->display.init_pch_clock_gating)
8788                 dev_priv->display.init_pch_clock_gating(dev);
8789 }
8790
8791 /* Set up chip specific display functions */
8792 static void intel_init_display(struct drm_device *dev)
8793 {
8794         struct drm_i915_private *dev_priv = dev->dev_private;
8795
8796         /* We always want a DPMS function */
8797         if (HAS_PCH_SPLIT(dev)) {
8798                 dev_priv->display.dpms = ironlake_crtc_dpms;
8799                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8800                 dev_priv->display.update_plane = ironlake_update_plane;
8801         } else {
8802                 dev_priv->display.dpms = i9xx_crtc_dpms;
8803                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8804                 dev_priv->display.update_plane = i9xx_update_plane;
8805         }
8806
8807         if (I915_HAS_FBC(dev)) {
8808                 if (HAS_PCH_SPLIT(dev)) {
8809                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8810                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8811                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8812                 } else if (IS_GM45(dev)) {
8813                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8814                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8815                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8816                 } else if (IS_CRESTLINE(dev)) {
8817                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8818                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8819                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8820                 }
8821                 /* 855GM needs testing */
8822         }
8823
8824         /* Returns the core display clock speed */
8825         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8826                 dev_priv->display.get_display_clock_speed =
8827                         i945_get_display_clock_speed;
8828         else if (IS_I915G(dev))
8829                 dev_priv->display.get_display_clock_speed =
8830                         i915_get_display_clock_speed;
8831         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8832                 dev_priv->display.get_display_clock_speed =
8833                         i9xx_misc_get_display_clock_speed;
8834         else if (IS_I915GM(dev))
8835                 dev_priv->display.get_display_clock_speed =
8836                         i915gm_get_display_clock_speed;
8837         else if (IS_I865G(dev))
8838                 dev_priv->display.get_display_clock_speed =
8839                         i865_get_display_clock_speed;
8840         else if (IS_I85X(dev))
8841                 dev_priv->display.get_display_clock_speed =
8842                         i855_get_display_clock_speed;
8843         else /* 852, 830 */
8844                 dev_priv->display.get_display_clock_speed =
8845                         i830_get_display_clock_speed;
8846
8847         /* For FIFO watermark updates */
8848         if (HAS_PCH_SPLIT(dev)) {
8849                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8850                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8851
8852                 /* IVB configs may use multi-threaded forcewake */
8853                 if (IS_IVYBRIDGE(dev)) {
8854                         u32     ecobus;
8855
8856                         /* A small trick here - if the bios hasn't configured MT forcewake,
8857                          * and if the device is in RC6, then force_wake_mt_get will not wake
8858                          * the device and the ECOBUS read will return zero. Which will be
8859                          * (correctly) interpreted by the test below as MT forcewake being
8860                          * disabled.
8861                          */
8862                         mutex_lock(&dev->struct_mutex);
8863                         __gen6_gt_force_wake_mt_get(dev_priv);
8864                         ecobus = I915_READ_NOTRACE(ECOBUS);
8865                         __gen6_gt_force_wake_mt_put(dev_priv);
8866                         mutex_unlock(&dev->struct_mutex);
8867
8868                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8869                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8870                                 dev_priv->display.force_wake_get =
8871                                         __gen6_gt_force_wake_mt_get;
8872                                 dev_priv->display.force_wake_put =
8873                                         __gen6_gt_force_wake_mt_put;
8874                         }
8875                 }
8876
8877                 if (HAS_PCH_IBX(dev))
8878                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8879                 else if (HAS_PCH_CPT(dev))
8880                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8881
8882                 if (IS_GEN5(dev)) {
8883                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8884                                 dev_priv->display.update_wm = ironlake_update_wm;
8885                         else {
8886                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8887                                               "Disable CxSR\n");
8888                                 dev_priv->display.update_wm = NULL;
8889                         }
8890                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8891                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8892                         dev_priv->display.write_eld = ironlake_write_eld;
8893                 } else if (IS_GEN6(dev)) {
8894                         if (SNB_READ_WM0_LATENCY()) {
8895                                 dev_priv->display.update_wm = sandybridge_update_wm;
8896                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8897                         } else {
8898                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8899                                               "Disable CxSR\n");
8900                                 dev_priv->display.update_wm = NULL;
8901                         }
8902                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8903                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8904                         dev_priv->display.write_eld = ironlake_write_eld;
8905                 } else if (IS_IVYBRIDGE(dev)) {
8906                         /* FIXME: detect B0+ stepping and use auto training */
8907                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8908                         if (SNB_READ_WM0_LATENCY()) {
8909                                 dev_priv->display.update_wm = sandybridge_update_wm;
8910                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8911                         } else {
8912                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8913                                               "Disable CxSR\n");
8914                                 dev_priv->display.update_wm = NULL;
8915                         }
8916                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8917                         dev_priv->display.write_eld = ironlake_write_eld;
8918                 } else
8919                         dev_priv->display.update_wm = NULL;
8920         } else if (IS_PINEVIEW(dev)) {
8921                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8922                                             dev_priv->is_ddr3,
8923                                             dev_priv->fsb_freq,
8924                                             dev_priv->mem_freq)) {
8925                         DRM_INFO("failed to find known CxSR latency "
8926                                  "(found ddr%s fsb freq %d, mem freq %d), "
8927                                  "disabling CxSR\n",
8928                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8929                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8930                         /* Disable CxSR and never update its watermark again */
8931                         pineview_disable_cxsr(dev);
8932                         dev_priv->display.update_wm = NULL;
8933                 } else
8934                         dev_priv->display.update_wm = pineview_update_wm;
8935                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8936         } else if (IS_G4X(dev)) {
8937                 dev_priv->display.write_eld = g4x_write_eld;
8938                 dev_priv->display.update_wm = g4x_update_wm;
8939                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8940         } else if (IS_GEN4(dev)) {
8941                 dev_priv->display.update_wm = i965_update_wm;
8942                 if (IS_CRESTLINE(dev))
8943                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8944                 else if (IS_BROADWATER(dev))
8945                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8946         } else if (IS_GEN3(dev)) {
8947                 dev_priv->display.update_wm = i9xx_update_wm;
8948                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8949                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8950         } else if (IS_I865G(dev)) {
8951                 dev_priv->display.update_wm = i830_update_wm;
8952                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8953                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8954         } else if (IS_I85X(dev)) {
8955                 dev_priv->display.update_wm = i9xx_update_wm;
8956                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8957                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8958         } else {
8959                 dev_priv->display.update_wm = i830_update_wm;
8960                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8961                 if (IS_845G(dev))
8962                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8963                 else
8964                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8965         }
8966
8967         /* Default just returns -ENODEV to indicate unsupported */
8968         dev_priv->display.queue_flip = intel_default_queue_flip;
8969
8970         switch (INTEL_INFO(dev)->gen) {
8971         case 2:
8972                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8973                 break;
8974
8975         case 3:
8976                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8977                 break;
8978
8979         case 4:
8980         case 5:
8981                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8982                 break;
8983
8984         case 6:
8985                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8986                 break;
8987         case 7:
8988                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8989                 break;
8990         }
8991 }
8992
8993 /*
8994  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8995  * resume, or other times.  This quirk makes sure that's the case for
8996  * affected systems.
8997  */
8998 static void quirk_pipea_force(struct drm_device *dev)
8999 {
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001
9002         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9003         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9004 }
9005
9006 /*
9007  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9008  */
9009 static void quirk_ssc_force_disable(struct drm_device *dev)
9010 {
9011         struct drm_i915_private *dev_priv = dev->dev_private;
9012         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9013 }
9014
9015 struct intel_quirk {
9016         int device;
9017         int subsystem_vendor;
9018         int subsystem_device;
9019         void (*hook)(struct drm_device *dev);
9020 };
9021
9022 struct intel_quirk intel_quirks[] = {
9023         /* HP Mini needs pipe A force quirk (LP: #322104) */
9024         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9025
9026         /* Thinkpad R31 needs pipe A force quirk */
9027         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9028         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9029         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9030
9031         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9032         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9033         /* ThinkPad X40 needs pipe A force quirk */
9034
9035         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9036         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9037
9038         /* 855 & before need to leave pipe A & dpll A up */
9039         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9040         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9041
9042         /* Lenovo U160 cannot use SSC on LVDS */
9043         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9044
9045         /* Sony Vaio Y cannot use SSC on LVDS */
9046         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9047 };
9048
9049 static void intel_init_quirks(struct drm_device *dev)
9050 {
9051         struct pci_dev *d = dev->pdev;
9052         int i;
9053
9054         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9055                 struct intel_quirk *q = &intel_quirks[i];
9056
9057                 if (d->device == q->device &&
9058                     (d->subsystem_vendor == q->subsystem_vendor ||
9059                      q->subsystem_vendor == PCI_ANY_ID) &&
9060                     (d->subsystem_device == q->subsystem_device ||
9061                      q->subsystem_device == PCI_ANY_ID))
9062                         q->hook(dev);
9063         }
9064 }
9065
9066 /* Disable the VGA plane that we never use */
9067 static void i915_disable_vga(struct drm_device *dev)
9068 {
9069         struct drm_i915_private *dev_priv = dev->dev_private;
9070         u8 sr1;
9071         u32 vga_reg;
9072
9073         if (HAS_PCH_SPLIT(dev))
9074                 vga_reg = CPU_VGACNTRL;
9075         else
9076                 vga_reg = VGACNTRL;
9077
9078         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9079         outb(1, VGA_SR_INDEX);
9080         sr1 = inb(VGA_SR_DATA);
9081         outb(sr1 | 1<<5, VGA_SR_DATA);
9082         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9083         udelay(300);
9084
9085         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9086         POSTING_READ(vga_reg);
9087 }
9088
9089 void intel_modeset_init(struct drm_device *dev)
9090 {
9091         struct drm_i915_private *dev_priv = dev->dev_private;
9092         int i, ret;
9093
9094         drm_mode_config_init(dev);
9095
9096         dev->mode_config.min_width = 0;
9097         dev->mode_config.min_height = 0;
9098
9099         dev->mode_config.preferred_depth = 24;
9100         dev->mode_config.prefer_shadow = 1;
9101
9102         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9103
9104         intel_init_quirks(dev);
9105
9106         intel_init_display(dev);
9107
9108         if (IS_GEN2(dev)) {
9109                 dev->mode_config.max_width = 2048;
9110                 dev->mode_config.max_height = 2048;
9111         } else if (IS_GEN3(dev)) {
9112                 dev->mode_config.max_width = 4096;
9113                 dev->mode_config.max_height = 4096;
9114         } else {
9115                 dev->mode_config.max_width = 8192;
9116                 dev->mode_config.max_height = 8192;
9117         }
9118         dev->mode_config.fb_base = dev->agp->base;
9119
9120         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9121                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9122
9123         for (i = 0; i < dev_priv->num_pipe; i++) {
9124                 intel_crtc_init(dev, i);
9125                 ret = intel_plane_init(dev, i);
9126                 if (ret)
9127                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9128         }
9129
9130         /* Just disable it once at startup */
9131         i915_disable_vga(dev);
9132         intel_setup_outputs(dev);
9133
9134         intel_init_clock_gating(dev);
9135
9136         if (IS_IRONLAKE_M(dev)) {
9137                 ironlake_enable_drps(dev);
9138                 intel_init_emon(dev);
9139         }
9140
9141         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9142                 gen6_enable_rps(dev_priv);
9143                 gen6_update_ring_freq(dev_priv);
9144         }
9145
9146         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9147         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9148                     (unsigned long)dev);
9149 }
9150
9151 void intel_modeset_gem_init(struct drm_device *dev)
9152 {
9153         if (IS_IRONLAKE_M(dev))
9154                 ironlake_enable_rc6(dev);
9155
9156         intel_setup_overlay(dev);
9157 }
9158
9159 void intel_modeset_cleanup(struct drm_device *dev)
9160 {
9161         struct drm_i915_private *dev_priv = dev->dev_private;
9162         struct drm_crtc *crtc;
9163         struct intel_crtc *intel_crtc;
9164
9165         drm_kms_helper_poll_fini(dev);
9166         mutex_lock(&dev->struct_mutex);
9167
9168         intel_unregister_dsm_handler();
9169
9170
9171         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9172                 /* Skip inactive CRTCs */
9173                 if (!crtc->fb)
9174                         continue;
9175
9176                 intel_crtc = to_intel_crtc(crtc);
9177                 intel_increase_pllclock(crtc);
9178         }
9179
9180         intel_disable_fbc(dev);
9181
9182         if (IS_IRONLAKE_M(dev))
9183                 ironlake_disable_drps(dev);
9184         if (IS_GEN6(dev) || IS_GEN7(dev))
9185                 gen6_disable_rps(dev);
9186
9187         if (IS_IRONLAKE_M(dev))
9188                 ironlake_disable_rc6(dev);
9189
9190         mutex_unlock(&dev->struct_mutex);
9191
9192         /* Disable the irq before mode object teardown, for the irq might
9193          * enqueue unpin/hotplug work. */
9194         drm_irq_uninstall(dev);
9195         cancel_work_sync(&dev_priv->hotplug_work);
9196         cancel_work_sync(&dev_priv->rps_work);
9197
9198         /* flush any delayed tasks or pending work */
9199         flush_scheduled_work();
9200
9201         /* Shut off idle work before the crtcs get freed. */
9202         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9203                 intel_crtc = to_intel_crtc(crtc);
9204                 del_timer_sync(&intel_crtc->idle_timer);
9205         }
9206         del_timer_sync(&dev_priv->idle_timer);
9207         cancel_work_sync(&dev_priv->idle_work);
9208
9209         drm_mode_config_cleanup(dev);
9210 }
9211
9212 /*
9213  * Return which encoder is currently attached for connector.
9214  */
9215 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9216 {
9217         return &intel_attached_encoder(connector)->base;
9218 }
9219
9220 void intel_connector_attach_encoder(struct intel_connector *connector,
9221                                     struct intel_encoder *encoder)
9222 {
9223         connector->encoder = encoder;
9224         drm_mode_connector_attach_encoder(&connector->base,
9225                                           &encoder->base);
9226 }
9227
9228 /*
9229  * set vga decode state - true == enable VGA decode
9230  */
9231 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9232 {
9233         struct drm_i915_private *dev_priv = dev->dev_private;
9234         u16 gmch_ctrl;
9235
9236         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9237         if (state)
9238                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9239         else
9240                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9241         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9242         return 0;
9243 }
9244
9245 #ifdef CONFIG_DEBUG_FS
9246 #include <linux/seq_file.h>
9247
9248 struct intel_display_error_state {
9249         struct intel_cursor_error_state {
9250                 u32 control;
9251                 u32 position;
9252                 u32 base;
9253                 u32 size;
9254         } cursor[2];
9255
9256         struct intel_pipe_error_state {
9257                 u32 conf;
9258                 u32 source;
9259
9260                 u32 htotal;
9261                 u32 hblank;
9262                 u32 hsync;
9263                 u32 vtotal;
9264                 u32 vblank;
9265                 u32 vsync;
9266         } pipe[2];
9267
9268         struct intel_plane_error_state {
9269                 u32 control;
9270                 u32 stride;
9271                 u32 size;
9272                 u32 pos;
9273                 u32 addr;
9274                 u32 surface;
9275                 u32 tile_offset;
9276         } plane[2];
9277 };
9278
9279 struct intel_display_error_state *
9280 intel_display_capture_error_state(struct drm_device *dev)
9281 {
9282         drm_i915_private_t *dev_priv = dev->dev_private;
9283         struct intel_display_error_state *error;
9284         int i;
9285
9286         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9287         if (error == NULL)
9288                 return NULL;
9289
9290         for (i = 0; i < 2; i++) {
9291                 error->cursor[i].control = I915_READ(CURCNTR(i));
9292                 error->cursor[i].position = I915_READ(CURPOS(i));
9293                 error->cursor[i].base = I915_READ(CURBASE(i));
9294
9295                 error->plane[i].control = I915_READ(DSPCNTR(i));
9296                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9297                 error->plane[i].size = I915_READ(DSPSIZE(i));
9298                 error->plane[i].pos = I915_READ(DSPPOS(i));
9299                 error->plane[i].addr = I915_READ(DSPADDR(i));
9300                 if (INTEL_INFO(dev)->gen >= 4) {
9301                         error->plane[i].surface = I915_READ(DSPSURF(i));
9302                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9303                 }
9304
9305                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9306                 error->pipe[i].source = I915_READ(PIPESRC(i));
9307                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9308                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9309                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9310                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9311                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9312                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9313         }
9314
9315         return error;
9316 }
9317
9318 void
9319 intel_display_print_error_state(struct seq_file *m,
9320                                 struct drm_device *dev,
9321                                 struct intel_display_error_state *error)
9322 {
9323         int i;
9324
9325         for (i = 0; i < 2; i++) {
9326                 seq_printf(m, "Pipe [%d]:\n", i);
9327                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9328                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9329                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9330                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9331                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9332                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9333                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9334                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9335
9336                 seq_printf(m, "Plane [%d]:\n", i);
9337                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9338                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9339                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9340                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9341                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9342                 if (INTEL_INFO(dev)->gen >= 4) {
9343                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9344                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9345                 }
9346
9347                 seq_printf(m, "Cursor [%d]:\n", i);
9348                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9349                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9350                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9351         }
9352 }
9353 #endif