drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = refclk * clock->m / clock->n;
 333         clock->dot = clock->vco / clock->p;
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = refclk * clock->m / clock->n;
 434         clock->dot = clock->vco / clock->p;
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = refclk * clock->m / (clock->n + 2);
 447         clock->dot = clock->vco / clock->p;
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 /*
 804  * intel_wait_for_pipe_off - wait for pipe to turn off
 805  * @dev: drm device
 806  * @pipe: pipe to wait for
 807  *
 808  * After disabling a pipe, we can't wait for vblank in the usual way,
 809  * spinning on the vblank interrupt status bit, since we won't actually
 810  * see an interrupt when the pipe is disabled.
 811  *
 812  * On Gen4 and above:
 813  *   wait for the pipe register state bit to turn off
 814  *
 815  * Otherwise:
 816  *   wait for the display line value to settle (it usually
 817  *   ends up stopping at the start of the next frame).
 818  *
 819  */
 820 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 824                                                                       pipe);
 825
 826         if (INTEL_INFO(dev)->gen >= 4) {
 827                 int reg = PIPECONF(cpu_transcoder);
 828
 829                 /* Wait for the Pipe State to go off */
 830                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 831                              100))
 832                         WARN(1, "pipe_off wait timed out\n");
 833         } else {
 834                 u32 last_line, line_mask;
 835                 int reg = PIPEDSL(pipe);
 836                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 837
 838                 if (IS_GEN2(dev))
 839                         line_mask = DSL_LINEMASK_GEN2;
 840                 else
 841                         line_mask = DSL_LINEMASK_GEN3;
 842
 843                 /* Wait for the display line to settle */
 844                 do {
 845                         last_line = I915_READ(reg) & line_mask;
 846                         mdelay(5);
 847                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 848                          time_after(timeout, jiffies));
 849                 if (time_after(jiffies, timeout))
 850                         WARN(1, "pipe_off wait timed out\n");
 851         }
 852 }
 853
 854 /*
 855  * ibx_digital_port_connected - is the specified port connected?
 856  * @dev_priv: i915 private structure
 857  * @port: the port to test
 858  *
 859  * Returns true if @port is connected, false otherwise.
 860  */
 861 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 862                                 struct intel_digital_port *port)
 863 {
 864         u32 bit;
 865
 866         if (HAS_PCH_IBX(dev_priv->dev)) {
 867                 switch(port->port) {
 868                 case PORT_B:
 869                         bit = SDE_PORTB_HOTPLUG;
 870                         break;
 871                 case PORT_C:
 872                         bit = SDE_PORTC_HOTPLUG;
 873                         break;
 874                 case PORT_D:
 875                         bit = SDE_PORTD_HOTPLUG;
 876                         break;
 877                 default:
 878                         return true;
 879                 }
 880         } else {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG_CPT;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG_CPT;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG_CPT;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         }
 895
 896         return I915_READ(SDEISR) & bit;
 897 }
 898
 899 static const char *state_string(bool enabled)
 900 {
 901         return enabled ? "on" : "off";
 902 }
 903
 904 /* Only for pre-ILK configs */
 905 void assert_pll(struct drm_i915_private *dev_priv,
 906                 enum pipe pipe, bool state)
 907 {
 908         int reg;
 909         u32 val;
 910         bool cur_state;
 911
 912         reg = DPLL(pipe);
 913         val = I915_READ(reg);
 914         cur_state = !!(val & DPLL_VCO_ENABLE);
 915         WARN(cur_state != state,
 916              "PLL state assertion failure (expected %s, current %s)\n",
 917              state_string(state), state_string(cur_state));
 918 }
 919
 920 /* XXX: the dsi pll is shared between MIPI DSI ports */
 921 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 922 {
 923         u32 val;
 924         bool cur_state;
 925
 926         mutex_lock(&dev_priv->dpio_lock);
 927         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 928         mutex_unlock(&dev_priv->dpio_lock);
 929
 930         cur_state = val & DSI_PLL_VCO_EN;
 931         WARN(cur_state != state,
 932              "DSI PLL state assertion failure (expected %s, current %s)\n",
 933              state_string(state), state_string(cur_state));
 934 }
 935 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 936 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 937
 938 struct intel_shared_dpll *
 939 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 940 {
 941         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 942
 943         if (crtc->config.shared_dpll < 0)
 944                 return NULL;
 945
 946         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 947 }
 948
 949 /* For ILK+ */
 950 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 951                         struct intel_shared_dpll *pll,
 952                         bool state)
 953 {
 954         bool cur_state;
 955         struct intel_dpll_hw_state hw_state;
 956
 957         if (HAS_PCH_LPT(dev_priv->dev)) {
 958                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 959                 return;
 960         }
 961
 962         if (WARN (!pll,
 963                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 964                 return;
 965
 966         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 967         WARN(cur_state != state,
 968              "%s assertion failure (expected %s, current %s)\n",
 969              pll->name, state_string(state), state_string(cur_state));
 970 }
 971
 972 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 973                           enum pipe pipe, bool state)
 974 {
 975         int reg;
 976         u32 val;
 977         bool cur_state;
 978         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 979                                                                       pipe);
 980
 981         if (HAS_DDI(dev_priv->dev)) {
 982                 /* DDI does not have a specific FDI_TX register */
 983                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 984                 val = I915_READ(reg);
 985                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 986         } else {
 987                 reg = FDI_TX_CTL(pipe);
 988                 val = I915_READ(reg);
 989                 cur_state = !!(val & FDI_TX_ENABLE);
 990         }
 991         WARN(cur_state != state,
 992              "FDI TX state assertion failure (expected %s, current %s)\n",
 993              state_string(state), state_string(cur_state));
 994 }
 995 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 996 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 997
 998 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004
1005         reg = FDI_RX_CTL(pipe);
1006         val = I915_READ(reg);
1007         cur_state = !!(val & FDI_RX_ENABLE);
1008         WARN(cur_state != state,
1009              "FDI RX state assertion failure (expected %s, current %s)\n",
1010              state_string(state), state_string(cur_state));
1011 }
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016                                       enum pipe pipe)
1017 {
1018         int reg;
1019         u32 val;
1020
1021         /* ILK FDI PLL is always enabled */
1022         if (dev_priv->info->gen == 5)
1023                 return;
1024
1025         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026         if (HAS_DDI(dev_priv->dev))
1027                 return;
1028
1029         reg = FDI_TX_CTL(pipe);
1030         val = I915_READ(reg);
1031         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1032 }
1033
1034 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1035                        enum pipe pipe, bool state)
1036 {
1037         int reg;
1038         u32 val;
1039         bool cur_state;
1040
1041         reg = FDI_RX_CTL(pipe);
1042         val = I915_READ(reg);
1043         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1044         WARN(cur_state != state,
1045              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046              state_string(state), state_string(cur_state));
1047 }
1048
1049 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1050                                   enum pipe pipe)
1051 {
1052         int pp_reg, lvds_reg;
1053         u32 val;
1054         enum pipe panel_pipe = PIPE_A;
1055         bool locked = true;
1056
1057         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058                 pp_reg = PCH_PP_CONTROL;
1059                 lvds_reg = PCH_LVDS;
1060         } else {
1061                 pp_reg = PP_CONTROL;
1062                 lvds_reg = LVDS;
1063         }
1064
1065         val = I915_READ(pp_reg);
1066         if (!(val & PANEL_POWER_ON) ||
1067             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1068                 locked = false;
1069
1070         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1071                 panel_pipe = PIPE_B;
1072
1073         WARN(panel_pipe == pipe && locked,
1074              "panel assertion failure, pipe %c regs locked\n",
1075              pipe_name(pipe));
1076 }
1077
1078 static void assert_cursor(struct drm_i915_private *dev_priv,
1079                           enum pipe pipe, bool state)
1080 {
1081         struct drm_device *dev = dev_priv->dev;
1082         bool cur_state;
1083
1084         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1085                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1086         else if (IS_845G(dev) || IS_I865G(dev))
1087                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1088         else
1089                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1090
1091         WARN(cur_state != state,
1092              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093              pipe_name(pipe), state_string(state), state_string(cur_state));
1094 }
1095 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1097
1098 void assert_pipe(struct drm_i915_private *dev_priv,
1099                  enum pipe pipe, bool state)
1100 {
1101         int reg;
1102         u32 val;
1103         bool cur_state;
1104         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1105                                                                       pipe);
1106
1107         /* if we need the pipe A quirk it must be always on */
1108         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1109                 state = true;
1110
1111         if (!intel_display_power_enabled(dev_priv->dev,
1112                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1113                 cur_state = false;
1114         } else {
1115                 reg = PIPECONF(cpu_transcoder);
1116                 val = I915_READ(reg);
1117                 cur_state = !!(val & PIPECONF_ENABLE);
1118         }
1119
1120         WARN(cur_state != state,
1121              "pipe %c assertion failure (expected %s, current %s)\n",
1122              pipe_name(pipe), state_string(state), state_string(cur_state));
1123 }
1124
1125 static void assert_plane(struct drm_i915_private *dev_priv,
1126                          enum plane plane, bool state)
1127 {
1128         int reg;
1129         u32 val;
1130         bool cur_state;
1131
1132         reg = DSPCNTR(plane);
1133         val = I915_READ(reg);
1134         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1135         WARN(cur_state != state,
1136              "plane %c assertion failure (expected %s, current %s)\n",
1137              plane_name(plane), state_string(state), state_string(cur_state));
1138 }
1139
1140 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1142
1143 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1144                                    enum pipe pipe)
1145 {
1146         struct drm_device *dev = dev_priv->dev;
1147         int reg, i;
1148         u32 val;
1149         int cur_pipe;
1150
1151         /* Primary planes are fixed to pipes on gen4+ */
1152         if (INTEL_INFO(dev)->gen >= 4) {
1153                 reg = DSPCNTR(pipe);
1154                 val = I915_READ(reg);
1155                 WARN((val & DISPLAY_PLANE_ENABLE),
1156                      "plane %c assertion failure, should be disabled but not\n",
1157                      plane_name(pipe));
1158                 return;
1159         }
1160
1161         /* Need to check both planes against the pipe */
1162         for_each_pipe(i) {
1163                 reg = DSPCNTR(i);
1164                 val = I915_READ(reg);
1165                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1166                         DISPPLANE_SEL_PIPE_SHIFT;
1167                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1168                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169                      plane_name(i), pipe_name(pipe));
1170         }
1171 }
1172
1173 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1174                                     enum pipe pipe)
1175 {
1176         struct drm_device *dev = dev_priv->dev;
1177         int reg, i;
1178         u32 val;
1179
1180         if (IS_VALLEYVIEW(dev)) {
1181                 for (i = 0; i < dev_priv->num_plane; i++) {
1182                         reg = SPCNTR(pipe, i);
1183                         val = I915_READ(reg);
1184                         WARN((val & SP_ENABLE),
1185                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186                              sprite_name(pipe, i), pipe_name(pipe));
1187                 }
1188         } else if (INTEL_INFO(dev)->gen >= 7) {
1189                 reg = SPRCTL(pipe);
1190                 val = I915_READ(reg);
1191                 WARN((val & SPRITE_ENABLE),
1192                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193                      plane_name(pipe), pipe_name(pipe));
1194         } else if (INTEL_INFO(dev)->gen >= 5) {
1195                 reg = DVSCNTR(pipe);
1196                 val = I915_READ(reg);
1197                 WARN((val & DVS_ENABLE),
1198                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1199                      plane_name(pipe), pipe_name(pipe));
1200         }
1201 }
1202
1203 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1204 {
1205         u32 val;
1206         bool enabled;
1207
1208         if (HAS_PCH_LPT(dev_priv->dev)) {
1209                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1210                 return;
1211         }
1212
1213         val = I915_READ(PCH_DREF_CONTROL);
1214         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1215                             DREF_SUPERSPREAD_SOURCE_MASK));
1216         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1217 }
1218
1219 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1220                                            enum pipe pipe)
1221 {
1222         int reg;
1223         u32 val;
1224         bool enabled;
1225
1226         reg = PCH_TRANSCONF(pipe);
1227         val = I915_READ(reg);
1228         enabled = !!(val & TRANS_ENABLE);
1229         WARN(enabled,
1230              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1231              pipe_name(pipe));
1232 }
1233
1234 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1235                             enum pipe pipe, u32 port_sel, u32 val)
1236 {
1237         if ((val & DP_PORT_EN) == 0)
1238                 return false;
1239
1240         if (HAS_PCH_CPT(dev_priv->dev)) {
1241                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1242                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1243                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1244                         return false;
1245         } else {
1246                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1247                         return false;
1248         }
1249         return true;
1250 }
1251
1252 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1253                               enum pipe pipe, u32 val)
1254 {
1255         if ((val & SDVO_ENABLE) == 0)
1256                 return false;
1257
1258         if (HAS_PCH_CPT(dev_priv->dev)) {
1259                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1260                         return false;
1261         } else {
1262                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1263                         return false;
1264         }
1265         return true;
1266 }
1267
1268 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1269                               enum pipe pipe, u32 val)
1270 {
1271         if ((val & LVDS_PORT_EN) == 0)
1272                 return false;
1273
1274         if (HAS_PCH_CPT(dev_priv->dev)) {
1275                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1276                         return false;
1277         } else {
1278                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1279                         return false;
1280         }
1281         return true;
1282 }
1283
1284 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1285                               enum pipe pipe, u32 val)
1286 {
1287         if ((val & ADPA_DAC_ENABLE) == 0)
1288                 return false;
1289         if (HAS_PCH_CPT(dev_priv->dev)) {
1290                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1291                         return false;
1292         } else {
1293                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1294                         return false;
1295         }
1296         return true;
1297 }
1298
1299 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1300                                    enum pipe pipe, int reg, u32 port_sel)
1301 {
1302         u32 val = I915_READ(reg);
1303         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1304              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1305              reg, pipe_name(pipe));
1306
1307         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1308              && (val & DP_PIPEB_SELECT),
1309              "IBX PCH dp port still using transcoder B\n");
1310 }
1311
1312 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1313                                      enum pipe pipe, int reg)
1314 {
1315         u32 val = I915_READ(reg);
1316         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1317              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1318              reg, pipe_name(pipe));
1319
1320         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1321              && (val & SDVO_PIPE_B_SELECT),
1322              "IBX PCH hdmi port still using transcoder B\n");
1323 }
1324
1325 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1326                                       enum pipe pipe)
1327 {
1328         int reg;
1329         u32 val;
1330
1331         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1332         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1333         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1334
1335         reg = PCH_ADPA;
1336         val = I915_READ(reg);
1337         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1338              "PCH VGA enabled on transcoder %c, should be disabled\n",
1339              pipe_name(pipe));
1340
1341         reg = PCH_LVDS;
1342         val = I915_READ(reg);
1343         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1344              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1345              pipe_name(pipe));
1346
1347         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1348         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1349         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1350 }
1351
1352 static void intel_init_dpio(struct drm_device *dev)
1353 {
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355
1356         if (!IS_VALLEYVIEW(dev))
1357                 return;
1358
1359         /*
1360          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1362          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363          *   b. The other bits such as sfr settings / modesel may all be set
1364          *      to 0.
1365          *
1366          * This should only be done on init and resume from S3 with both
1367          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1368          */
1369         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1370 }
1371
1372 static void vlv_enable_pll(struct intel_crtc *crtc)
1373 {
1374         struct drm_device *dev = crtc->base.dev;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int reg = DPLL(crtc->pipe);
1377         u32 dpll = crtc->config.dpll_hw_state.dpll;
1378
1379         assert_pipe_disabled(dev_priv, crtc->pipe);
1380
1381         /* No really, not for ILK+ */
1382         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1383
1384         /* PLL is protected by panel, make sure we can write it */
1385         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1386                 assert_panel_unlocked(dev_priv, crtc->pipe);
1387
1388         I915_WRITE(reg, dpll);
1389         POSTING_READ(reg);
1390         udelay(150);
1391
1392         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1393                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1394
1395         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1396         POSTING_READ(DPLL_MD(crtc->pipe));
1397
1398         /* We do this three times for luck */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405         I915_WRITE(reg, dpll);
1406         POSTING_READ(reg);
1407         udelay(150); /* wait for warmup */
1408 }
1409
1410 static void i9xx_enable_pll(struct intel_crtc *crtc)
1411 {
1412         struct drm_device *dev = crtc->base.dev;
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         int reg = DPLL(crtc->pipe);
1415         u32 dpll = crtc->config.dpll_hw_state.dpll;
1416
1417         assert_pipe_disabled(dev_priv, crtc->pipe);
1418
1419         /* No really, not for ILK+ */
1420         BUG_ON(dev_priv->info->gen >= 5);
1421
1422         /* PLL is protected by panel, make sure we can write it */
1423         if (IS_MOBILE(dev) && !IS_I830(dev))
1424                 assert_panel_unlocked(dev_priv, crtc->pipe);
1425
1426         I915_WRITE(reg, dpll);
1427
1428         /* Wait for the clocks to stabilize. */
1429         POSTING_READ(reg);
1430         udelay(150);
1431
1432         if (INTEL_INFO(dev)->gen >= 4) {
1433                 I915_WRITE(DPLL_MD(crtc->pipe),
1434                            crtc->config.dpll_hw_state.dpll_md);
1435         } else {
1436                 /* The pixel multiplier can only be updated once the
1437                  * DPLL is enabled and the clocks are stable.
1438                  *
1439                  * So write it again.
1440                  */
1441                 I915_WRITE(reg, dpll);
1442         }
1443
1444         /* We do this three times for luck */
1445         I915_WRITE(reg, dpll);
1446         POSTING_READ(reg);
1447         udelay(150); /* wait for warmup */
1448         I915_WRITE(reg, dpll);
1449         POSTING_READ(reg);
1450         udelay(150); /* wait for warmup */
1451         I915_WRITE(reg, dpll);
1452         POSTING_READ(reg);
1453         udelay(150); /* wait for warmup */
1454 }
1455
1456 /**
1457  * i9xx_disable_pll - disable a PLL
1458  * @dev_priv: i915 private structure
1459  * @pipe: pipe PLL to disable
1460  *
1461  * Disable the PLL for @pipe, making sure the pipe is off first.
1462  *
1463  * Note!  This is for pre-ILK only.
1464  */
1465 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1466 {
1467         /* Don't disable pipe A or pipe A PLLs if needed */
1468         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1469                 return;
1470
1471         /* Make sure the pipe isn't still relying on us */
1472         assert_pipe_disabled(dev_priv, pipe);
1473
1474         I915_WRITE(DPLL(pipe), 0);
1475         POSTING_READ(DPLL(pipe));
1476 }
1477
1478 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 {
1480         u32 val = 0;
1481
1482         /* Make sure the pipe isn't still relying on us */
1483         assert_pipe_disabled(dev_priv, pipe);
1484
1485         /* Leave integrated clock source enabled */
1486         if (pipe == PIPE_B)
1487                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1488         I915_WRITE(DPLL(pipe), val);
1489         POSTING_READ(DPLL(pipe));
1490 }
1491
1492 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1493 {
1494         u32 port_mask;
1495
1496         if (!port)
1497                 port_mask = DPLL_PORTB_READY_MASK;
1498         else
1499                 port_mask = DPLL_PORTC_READY_MASK;
1500
1501         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1502                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503                      'B' + port, I915_READ(DPLL(0)));
1504 }
1505
1506 /**
1507  * ironlake_enable_shared_dpll - enable PCH PLL
1508  * @dev_priv: i915 private structure
1509  * @pipe: pipe PLL to enable
1510  *
1511  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512  * drives the transcoder clock.
1513  */
1514 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1515 {
1516         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1517         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1518
1519         /* PCH PLLs only available on ILK, SNB and IVB */
1520         BUG_ON(dev_priv->info->gen < 5);
1521         if (WARN_ON(pll == NULL))
1522                 return;
1523
1524         if (WARN_ON(pll->refcount == 0))
1525                 return;
1526
1527         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528                       pll->name, pll->active, pll->on,
1529                       crtc->base.base.id);
1530
1531         if (pll->active++) {
1532                 WARN_ON(!pll->on);
1533                 assert_shared_dpll_enabled(dev_priv, pll);
1534                 return;
1535         }
1536         WARN_ON(pll->on);
1537
1538         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1539         pll->enable(dev_priv, pll);
1540         pll->on = true;
1541 }
1542
1543 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1544 {
1545         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1547
1548         /* PCH only available on ILK+ */
1549         BUG_ON(dev_priv->info->gen < 5);
1550         if (WARN_ON(pll == NULL))
1551                return;
1552
1553         if (WARN_ON(pll->refcount == 0))
1554                 return;
1555
1556         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557                       pll->name, pll->active, pll->on,
1558                       crtc->base.base.id);
1559
1560         if (WARN_ON(pll->active == 0)) {
1561                 assert_shared_dpll_disabled(dev_priv, pll);
1562                 return;
1563         }
1564
1565         assert_shared_dpll_enabled(dev_priv, pll);
1566         WARN_ON(!pll->on);
1567         if (--pll->active)
1568                 return;
1569
1570         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1571         pll->disable(dev_priv, pll);
1572         pll->on = false;
1573 }
1574
1575 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1576                                            enum pipe pipe)
1577 {
1578         struct drm_device *dev = dev_priv->dev;
1579         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         uint32_t reg, val, pipeconf_val;
1582
1583         /* PCH only available on ILK+ */
1584         BUG_ON(dev_priv->info->gen < 5);
1585
1586         /* Make sure PCH DPLL is enabled */
1587         assert_shared_dpll_enabled(dev_priv,
1588                                    intel_crtc_to_shared_dpll(intel_crtc));
1589
1590         /* FDI must be feeding us bits for PCH ports */
1591         assert_fdi_tx_enabled(dev_priv, pipe);
1592         assert_fdi_rx_enabled(dev_priv, pipe);
1593
1594         if (HAS_PCH_CPT(dev)) {
1595                 /* Workaround: Set the timing override bit before enabling the
1596                  * pch transcoder. */
1597                 reg = TRANS_CHICKEN2(pipe);
1598                 val = I915_READ(reg);
1599                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600                 I915_WRITE(reg, val);
1601         }
1602
1603         reg = PCH_TRANSCONF(pipe);
1604         val = I915_READ(reg);
1605         pipeconf_val = I915_READ(PIPECONF(pipe));
1606
1607         if (HAS_PCH_IBX(dev_priv->dev)) {
1608                 /*
1609                  * make the BPC in transcoder be consistent with
1610                  * that in pipeconf reg.
1611                  */
1612                 val &= ~PIPECONF_BPC_MASK;
1613                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1614         }
1615
1616         val &= ~TRANS_INTERLACE_MASK;
1617         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1618                 if (HAS_PCH_IBX(dev_priv->dev) &&
1619                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1620                         val |= TRANS_LEGACY_INTERLACED_ILK;
1621                 else
1622                         val |= TRANS_INTERLACED;
1623         else
1624                 val |= TRANS_PROGRESSIVE;
1625
1626         I915_WRITE(reg, val | TRANS_ENABLE);
1627         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1628                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1629 }
1630
1631 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1632                                       enum transcoder cpu_transcoder)
1633 {
1634         u32 val, pipeconf_val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638
1639         /* FDI must be feeding us bits for PCH ports */
1640         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1641         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1642
1643         /* Workaround: set timing override bit. */
1644         val = I915_READ(_TRANSA_CHICKEN2);
1645         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1646         I915_WRITE(_TRANSA_CHICKEN2, val);
1647
1648         val = TRANS_ENABLE;
1649         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1650
1651         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1652             PIPECONF_INTERLACED_ILK)
1653                 val |= TRANS_INTERLACED;
1654         else
1655                 val |= TRANS_PROGRESSIVE;
1656
1657         I915_WRITE(LPT_TRANSCONF, val);
1658         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1659                 DRM_ERROR("Failed to enable PCH transcoder\n");
1660 }
1661
1662 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                             enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         uint32_t reg, val;
1667
1668         /* FDI relies on the transcoder */
1669         assert_fdi_tx_disabled(dev_priv, pipe);
1670         assert_fdi_rx_disabled(dev_priv, pipe);
1671
1672         /* Ports must be off as well */
1673         assert_pch_ports_disabled(dev_priv, pipe);
1674
1675         reg = PCH_TRANSCONF(pipe);
1676         val = I915_READ(reg);
1677         val &= ~TRANS_ENABLE;
1678         I915_WRITE(reg, val);
1679         /* wait for PCH transcoder off, transcoder state */
1680         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1681                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1682
1683         if (!HAS_PCH_IBX(dev)) {
1684                 /* Workaround: Clear the timing override chicken bit again. */
1685                 reg = TRANS_CHICKEN2(pipe);
1686                 val = I915_READ(reg);
1687                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1688                 I915_WRITE(reg, val);
1689         }
1690 }
1691
1692 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1693 {
1694         u32 val;
1695
1696         val = I915_READ(LPT_TRANSCONF);
1697         val &= ~TRANS_ENABLE;
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         /* wait for PCH transcoder off, transcoder state */
1700         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1701                 DRM_ERROR("Failed to disable PCH transcoder\n");
1702
1703         /* Workaround: clear timing override bit. */
1704         val = I915_READ(_TRANSA_CHICKEN2);
1705         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1706         I915_WRITE(_TRANSA_CHICKEN2, val);
1707 }
1708
1709 /**
1710  * intel_enable_pipe - enable a pipe, asserting requirements
1711  * @dev_priv: i915 private structure
1712  * @pipe: pipe to enable
1713  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1714  *
1715  * Enable @pipe, making sure that various hardware specific requirements
1716  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1717  *
1718  * @pipe should be %PIPE_A or %PIPE_B.
1719  *
1720  * Will wait until the pipe is actually running (i.e. first vblank) before
1721  * returning.
1722  */
1723 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1724                               bool pch_port, bool dsi)
1725 {
1726         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727                                                                       pipe);
1728         enum pipe pch_transcoder;
1729         int reg;
1730         u32 val;
1731
1732         assert_planes_disabled(dev_priv, pipe);
1733         assert_cursor_disabled(dev_priv, pipe);
1734         assert_sprites_disabled(dev_priv, pipe);
1735
1736         if (HAS_PCH_LPT(dev_priv->dev))
1737                 pch_transcoder = TRANSCODER_A;
1738         else
1739                 pch_transcoder = pipe;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 if (dsi)
1748                         assert_dsi_pll_enabled(dev_priv);
1749                 else
1750                         assert_pll_enabled(dev_priv, pipe);
1751         else {
1752                 if (pch_port) {
1753                         /* if driving the PCH, we need FDI enabled */
1754                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1755                         assert_fdi_tx_pll_enabled(dev_priv,
1756                                                   (enum pipe) cpu_transcoder);
1757                 }
1758                 /* FIXME: assert CPU port conditions for SNB+ */
1759         }
1760
1761         reg = PIPECONF(cpu_transcoder);
1762         val = I915_READ(reg);
1763         if (val & PIPECONF_ENABLE)
1764                 return;
1765
1766         I915_WRITE(reg, val | PIPECONF_ENABLE);
1767         intel_wait_for_vblank(dev_priv->dev, pipe);
1768 }
1769
1770 /**
1771  * intel_disable_pipe - disable a pipe, asserting requirements
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe to disable
1774  *
1775  * Disable @pipe, making sure that various hardware specific requirements
1776  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1777  *
1778  * @pipe should be %PIPE_A or %PIPE_B.
1779  *
1780  * Will wait until the pipe has shut down before returning.
1781  */
1782 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783                                enum pipe pipe)
1784 {
1785         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1786                                                                       pipe);
1787         int reg;
1788         u32 val;
1789
1790         /*
1791          * Make sure planes won't keep trying to pump pixels to us,
1792          * or we might hang the display.
1793          */
1794         assert_planes_disabled(dev_priv, pipe);
1795         assert_cursor_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1816                                enum plane plane)
1817 {
1818         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1819
1820         I915_WRITE(reg, I915_READ(reg));
1821         POSTING_READ(reg);
1822 }
1823
1824 /**
1825  * intel_enable_primary_plane - enable the primary plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1833                                        enum plane plane, enum pipe pipe)
1834 {
1835         struct intel_crtc *intel_crtc =
1836                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1837         int reg;
1838         u32 val;
1839
1840         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841         assert_pipe_enabled(dev_priv, pipe);
1842
1843         WARN(!intel_crtc->primary_disabled, "Primary plane already enabled\n");
1844
1845         intel_crtc->primary_disabled = false;
1846
1847         reg = DSPCNTR(plane);
1848         val = I915_READ(reg);
1849         if (val & DISPLAY_PLANE_ENABLE)
1850                 return;
1851
1852         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1853         intel_flush_primary_plane(dev_priv, plane);
1854         intel_wait_for_vblank(dev_priv->dev, pipe);
1855 }
1856
1857 /**
1858  * intel_disable_primary_plane - disable the primary plane
1859  * @dev_priv: i915 private structure
1860  * @plane: plane to disable
1861  * @pipe: pipe consuming the data
1862  *
1863  * Disable @plane; should be an independent operation.
1864  */
1865 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1866                                         enum plane plane, enum pipe pipe)
1867 {
1868         struct intel_crtc *intel_crtc =
1869                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1870         int reg;
1871         u32 val;
1872
1873         WARN(intel_crtc->primary_disabled, "Primary plane already disabled\n");
1874
1875         intel_crtc->primary_disabled = true;
1876
1877         reg = DSPCNTR(plane);
1878         val = I915_READ(reg);
1879         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1880                 return;
1881
1882         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1883         intel_flush_primary_plane(dev_priv, plane);
1884         intel_wait_for_vblank(dev_priv->dev, pipe);
1885 }
1886
1887 static bool need_vtd_wa(struct drm_device *dev)
1888 {
1889 #ifdef CONFIG_INTEL_IOMMU
1890         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1891                 return true;
1892 #endif
1893         return false;
1894 }
1895
1896 int
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898                            struct drm_i915_gem_object *obj,
1899                            struct intel_ring_buffer *pipelined)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 alignment;
1903         int ret;
1904
1905         switch (obj->tiling_mode) {
1906         case I915_TILING_NONE:
1907                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908                         alignment = 128 * 1024;
1909                 else if (INTEL_INFO(dev)->gen >= 4)
1910                         alignment = 4 * 1024;
1911                 else
1912                         alignment = 64 * 1024;
1913                 break;
1914         case I915_TILING_X:
1915                 /* pin() will align the object as required by fence */
1916                 alignment = 0;
1917                 break;
1918         case I915_TILING_Y:
1919                 /* Despite that we check this in framebuffer_init userspace can
1920                  * screw us over and change the tiling after the fact. Only
1921                  * pinned buffers can't change their tiling. */
1922                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1923                 return -EINVAL;
1924         default:
1925                 BUG();
1926         }
1927
1928         /* Note that the w/a also requires 64 PTE of padding following the
1929          * bo. We currently fill all unused PTE with the shadow page and so
1930          * we should always have valid PTE following the scanout preventing
1931          * the VT-d warning.
1932          */
1933         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1934                 alignment = 256 * 1024;
1935
1936         dev_priv->mm.interruptible = false;
1937         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1938         if (ret)
1939                 goto err_interruptible;
1940
1941         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1942          * fence, whereas 965+ only requires a fence if using
1943          * framebuffer compression.  For simplicity, we always install
1944          * a fence as the cost is not that onerous.
1945          */
1946         ret = i915_gem_object_get_fence(obj);
1947         if (ret)
1948                 goto err_unpin;
1949
1950         i915_gem_object_pin_fence(obj);
1951
1952         dev_priv->mm.interruptible = true;
1953         return 0;
1954
1955 err_unpin:
1956         i915_gem_object_unpin_from_display_plane(obj);
1957 err_interruptible:
1958         dev_priv->mm.interruptible = true;
1959         return ret;
1960 }
1961
1962 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1963 {
1964         i915_gem_object_unpin_fence(obj);
1965         i915_gem_object_unpin_from_display_plane(obj);
1966 }
1967
1968 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1969  * is assumed to be a power-of-two. */
1970 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1971                                              unsigned int tiling_mode,
1972                                              unsigned int cpp,
1973                                              unsigned int pitch)
1974 {
1975         if (tiling_mode != I915_TILING_NONE) {
1976                 unsigned int tile_rows, tiles;
1977
1978                 tile_rows = *y / 8;
1979                 *y %= 8;
1980
1981                 tiles = *x / (512/cpp);
1982                 *x %= 512/cpp;
1983
1984                 return tile_rows * pitch * 8 + tiles * 4096;
1985         } else {
1986                 unsigned int offset;
1987
1988                 offset = *y * pitch + *x * cpp;
1989                 *y = 0;
1990                 *x = (offset & 4095) / cpp;
1991                 return offset & -4096;
1992         }
1993 }
1994
1995 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1996                              int x, int y)
1997 {
1998         struct drm_device *dev = crtc->dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2001         struct intel_framebuffer *intel_fb;
2002         struct drm_i915_gem_object *obj;
2003         int plane = intel_crtc->plane;
2004         unsigned long linear_offset;
2005         u32 dspcntr;
2006         u32 reg;
2007
2008         switch (plane) {
2009         case 0:
2010         case 1:
2011                 break;
2012         default:
2013                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2014                 return -EINVAL;
2015         }
2016
2017         intel_fb = to_intel_framebuffer(fb);
2018         obj = intel_fb->obj;
2019
2020         reg = DSPCNTR(plane);
2021         dspcntr = I915_READ(reg);
2022         /* Mask out pixel format bits in case we change it */
2023         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2024         switch (fb->pixel_format) {
2025         case DRM_FORMAT_C8:
2026                 dspcntr |= DISPPLANE_8BPP;
2027                 break;
2028         case DRM_FORMAT_XRGB1555:
2029         case DRM_FORMAT_ARGB1555:
2030                 dspcntr |= DISPPLANE_BGRX555;
2031                 break;
2032         case DRM_FORMAT_RGB565:
2033                 dspcntr |= DISPPLANE_BGRX565;
2034                 break;
2035         case DRM_FORMAT_XRGB8888:
2036         case DRM_FORMAT_ARGB8888:
2037                 dspcntr |= DISPPLANE_BGRX888;
2038                 break;
2039         case DRM_FORMAT_XBGR8888:
2040         case DRM_FORMAT_ABGR8888:
2041                 dspcntr |= DISPPLANE_RGBX888;
2042                 break;
2043         case DRM_FORMAT_XRGB2101010:
2044         case DRM_FORMAT_ARGB2101010:
2045                 dspcntr |= DISPPLANE_BGRX101010;
2046                 break;
2047         case DRM_FORMAT_XBGR2101010:
2048         case DRM_FORMAT_ABGR2101010:
2049                 dspcntr |= DISPPLANE_RGBX101010;
2050                 break;
2051         default:
2052                 BUG();
2053         }
2054
2055         if (INTEL_INFO(dev)->gen >= 4) {
2056                 if (obj->tiling_mode != I915_TILING_NONE)
2057                         dspcntr |= DISPPLANE_TILED;
2058                 else
2059                         dspcntr &= ~DISPPLANE_TILED;
2060         }
2061
2062         if (IS_G4X(dev))
2063                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2064
2065         I915_WRITE(reg, dspcntr);
2066
2067         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2068
2069         if (INTEL_INFO(dev)->gen >= 4) {
2070                 intel_crtc->dspaddr_offset =
2071                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2072                                                        fb->bits_per_pixel / 8,
2073                                                        fb->pitches[0]);
2074                 linear_offset -= intel_crtc->dspaddr_offset;
2075         } else {
2076                 intel_crtc->dspaddr_offset = linear_offset;
2077         }
2078
2079         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2080                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2081                       fb->pitches[0]);
2082         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2083         if (INTEL_INFO(dev)->gen >= 4) {
2084                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2085                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2086                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2088         } else
2089                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2090         POSTING_READ(reg);
2091
2092         return 0;
2093 }
2094
2095 static int ironlake_update_plane(struct drm_crtc *crtc,
2096                                  struct drm_framebuffer *fb, int x, int y)
2097 {
2098         struct drm_device *dev = crtc->dev;
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101         struct intel_framebuffer *intel_fb;
2102         struct drm_i915_gem_object *obj;
2103         int plane = intel_crtc->plane;
2104         unsigned long linear_offset;
2105         u32 dspcntr;
2106         u32 reg;
2107
2108         switch (plane) {
2109         case 0:
2110         case 1:
2111         case 2:
2112                 break;
2113         default:
2114                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2115                 return -EINVAL;
2116         }
2117
2118         intel_fb = to_intel_framebuffer(fb);
2119         obj = intel_fb->obj;
2120
2121         reg = DSPCNTR(plane);
2122         dspcntr = I915_READ(reg);
2123         /* Mask out pixel format bits in case we change it */
2124         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2125         switch (fb->pixel_format) {
2126         case DRM_FORMAT_C8:
2127                 dspcntr |= DISPPLANE_8BPP;
2128                 break;
2129         case DRM_FORMAT_RGB565:
2130                 dspcntr |= DISPPLANE_BGRX565;
2131                 break;
2132         case DRM_FORMAT_XRGB8888:
2133         case DRM_FORMAT_ARGB8888:
2134                 dspcntr |= DISPPLANE_BGRX888;
2135                 break;
2136         case DRM_FORMAT_XBGR8888:
2137         case DRM_FORMAT_ABGR8888:
2138                 dspcntr |= DISPPLANE_RGBX888;
2139                 break;
2140         case DRM_FORMAT_XRGB2101010:
2141         case DRM_FORMAT_ARGB2101010:
2142                 dspcntr |= DISPPLANE_BGRX101010;
2143                 break;
2144         case DRM_FORMAT_XBGR2101010:
2145         case DRM_FORMAT_ABGR2101010:
2146                 dspcntr |= DISPPLANE_RGBX101010;
2147                 break;
2148         default:
2149                 BUG();
2150         }
2151
2152         if (obj->tiling_mode != I915_TILING_NONE)
2153                 dspcntr |= DISPPLANE_TILED;
2154         else
2155                 dspcntr &= ~DISPPLANE_TILED;
2156
2157         if (IS_HASWELL(dev))
2158                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2159         else
2160                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2161
2162         I915_WRITE(reg, dspcntr);
2163
2164         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2165         intel_crtc->dspaddr_offset =
2166                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2167                                                fb->bits_per_pixel / 8,
2168                                                fb->pitches[0]);
2169         linear_offset -= intel_crtc->dspaddr_offset;
2170
2171         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2172                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2173                       fb->pitches[0]);
2174         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2175         I915_MODIFY_DISPBASE(DSPSURF(plane),
2176                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2177         if (IS_HASWELL(dev)) {
2178                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2179         } else {
2180                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2181                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2182         }
2183         POSTING_READ(reg);
2184
2185         return 0;
2186 }
2187
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2189 static int
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191                            int x, int y, enum mode_set_atomic state)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195
2196         if (dev_priv->display.disable_fbc)
2197                 dev_priv->display.disable_fbc(dev);
2198         intel_increase_pllclock(crtc);
2199
2200         return dev_priv->display.update_plane(crtc, fb, x, y);
2201 }
2202
2203 void intel_display_handle_reset(struct drm_device *dev)
2204 {
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         struct drm_crtc *crtc;
2207
2208         /*
2209          * Flips in the rings have been nuked by the reset,
2210          * so complete all pending flips so that user space
2211          * will get its events and not get stuck.
2212          *
2213          * Also update the base address of all primary
2214          * planes to the the last fb to make sure we're
2215          * showing the correct fb after a reset.
2216          *
2217          * Need to make two loops over the crtcs so that we
2218          * don't try to grab a crtc mutex before the
2219          * pending_flip_queue really got woken up.
2220          */
2221
2222         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2223                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2224                 enum plane plane = intel_crtc->plane;
2225
2226                 intel_prepare_page_flip(dev, plane);
2227                 intel_finish_page_flip_plane(dev, plane);
2228         }
2229
2230         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2231                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232
2233                 mutex_lock(&crtc->mutex);
2234                 if (intel_crtc->active)
2235                         dev_priv->display.update_plane(crtc, crtc->fb,
2236                                                        crtc->x, crtc->y);
2237                 mutex_unlock(&crtc->mutex);
2238         }
2239 }
2240
2241 static int
2242 intel_finish_fb(struct drm_framebuffer *old_fb)
2243 {
2244         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2245         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246         bool was_interruptible = dev_priv->mm.interruptible;
2247         int ret;
2248
2249         /* Big Hammer, we also need to ensure that any pending
2250          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251          * current scanout is retired before unpinning the old
2252          * framebuffer.
2253          *
2254          * This should only fail upon a hung GPU, in which case we
2255          * can safely continue.
2256          */
2257         dev_priv->mm.interruptible = false;
2258         ret = i915_gem_object_finish_gpu(obj);
2259         dev_priv->mm.interruptible = was_interruptible;
2260
2261         return ret;
2262 }
2263
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_master_private *master_priv;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270         if (!dev->primary->master)
2271                 return;
2272
2273         master_priv = dev->primary->master->driver_priv;
2274         if (!master_priv->sarea_priv)
2275                 return;
2276
2277         switch (intel_crtc->pipe) {
2278         case 0:
2279                 master_priv->sarea_priv->pipeA_x = x;
2280                 master_priv->sarea_priv->pipeA_y = y;
2281                 break;
2282         case 1:
2283                 master_priv->sarea_priv->pipeB_x = x;
2284                 master_priv->sarea_priv->pipeB_y = y;
2285                 break;
2286         default:
2287                 break;
2288         }
2289 }
2290
2291 static int
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293                     struct drm_framebuffer *fb)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         struct drm_framebuffer *old_fb;
2299         int ret;
2300
2301         /* no fb bound */
2302         if (!fb) {
2303                 DRM_ERROR("No FB bound\n");
2304                 return 0;
2305         }
2306
2307         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2308                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2309                           plane_name(intel_crtc->plane),
2310                           INTEL_INFO(dev)->num_pipes);
2311                 return -EINVAL;
2312         }
2313
2314         mutex_lock(&dev->struct_mutex);
2315         ret = intel_pin_and_fence_fb_obj(dev,
2316                                          to_intel_framebuffer(fb)->obj,
2317                                          NULL);
2318         if (ret != 0) {
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("pin & fence failed\n");
2321                 return ret;
2322         }
2323
2324         /*
2325          * Update pipe size and adjust fitter if needed: the reason for this is
2326          * that in compute_mode_changes we check the native mode (not the pfit
2327          * mode) to see if we can flip rather than do a full mode set. In the
2328          * fastboot case, we'll flip, but if we don't update the pipesrc and
2329          * pfit state, we'll end up with a big fb scanned out into the wrong
2330          * sized surface.
2331          *
2332          * To fix this properly, we need to hoist the checks up into
2333          * compute_mode_changes (or above), check the actual pfit state and
2334          * whether the platform allows pfit disable with pipe active, and only
2335          * then update the pipesrc and pfit state, even on the flip path.
2336          */
2337         if (i915_fastboot) {
2338                 const struct drm_display_mode *adjusted_mode =
2339                         &intel_crtc->config.adjusted_mode;
2340
2341                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2342                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2343                            (adjusted_mode->crtc_vdisplay - 1));
2344                 if (!intel_crtc->config.pch_pfit.enabled &&
2345                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2346                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2347                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2348                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2349                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2350                 }
2351         }
2352
2353         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2354         if (ret) {
2355                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2356                 mutex_unlock(&dev->struct_mutex);
2357                 DRM_ERROR("failed to update base address\n");
2358                 return ret;
2359         }
2360
2361         old_fb = crtc->fb;
2362         crtc->fb = fb;
2363         crtc->x = x;
2364         crtc->y = y;
2365
2366         if (old_fb) {
2367                 if (intel_crtc->active && old_fb != fb)
2368                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2369                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2370         }
2371
2372         intel_update_fbc(dev);
2373         intel_edp_psr_update(dev);
2374         mutex_unlock(&dev->struct_mutex);
2375
2376         intel_crtc_update_sarea_pos(crtc, x, y);
2377
2378         return 0;
2379 }
2380
2381 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2382 {
2383         struct drm_device *dev = crtc->dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386         int pipe = intel_crtc->pipe;
2387         u32 reg, temp;
2388
2389         /* enable normal train */
2390         reg = FDI_TX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         if (IS_IVYBRIDGE(dev)) {
2393                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2394                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2395         } else {
2396                 temp &= ~FDI_LINK_TRAIN_NONE;
2397                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2398         }
2399         I915_WRITE(reg, temp);
2400
2401         reg = FDI_RX_CTL(pipe);
2402         temp = I915_READ(reg);
2403         if (HAS_PCH_CPT(dev)) {
2404                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2406         } else {
2407                 temp &= ~FDI_LINK_TRAIN_NONE;
2408                 temp |= FDI_LINK_TRAIN_NONE;
2409         }
2410         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2411
2412         /* wait one idle pattern time */
2413         POSTING_READ(reg);
2414         udelay(1000);
2415
2416         /* IVB wants error correction enabled */
2417         if (IS_IVYBRIDGE(dev))
2418                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2419                            FDI_FE_ERRC_ENABLE);
2420 }
2421
2422 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2423 {
2424         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2425 }
2426
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         struct intel_crtc *pipe_B_crtc =
2431                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432         struct intel_crtc *pipe_C_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434         uint32_t temp;
2435
2436         /*
2437          * When everything is off disable fdi C so that we could enable fdi B
2438          * with all lanes. Note that we don't care about enabled pipes without
2439          * an enabled pch encoder.
2440          */
2441         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2442             !pipe_has_enabled_pch(pipe_C_crtc)) {
2443                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2444                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2445
2446                 temp = I915_READ(SOUTH_CHICKEN1);
2447                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2448                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2449                 I915_WRITE(SOUTH_CHICKEN1, temp);
2450         }
2451 }
2452
2453 /* The FDI link training functions for ILK/Ibexpeak. */
2454 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2455 {
2456         struct drm_device *dev = crtc->dev;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459         int pipe = intel_crtc->pipe;
2460         int plane = intel_crtc->plane;
2461         u32 reg, temp, tries;
2462
2463         /* FDI needs bits from pipe & plane first */
2464         assert_pipe_enabled(dev_priv, pipe);
2465         assert_plane_enabled(dev_priv, plane);
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474         I915_READ(reg);
2475         udelay(150);
2476
2477         /* enable CPU FDI TX and PCH FDI RX */
2478         reg = FDI_TX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2481         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2482         temp &= ~FDI_LINK_TRAIN_NONE;
2483         temp |= FDI_LINK_TRAIN_PATTERN_1;
2484         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2485
2486         reg = FDI_RX_CTL(pipe);
2487         temp = I915_READ(reg);
2488         temp &= ~FDI_LINK_TRAIN_NONE;
2489         temp |= FDI_LINK_TRAIN_PATTERN_1;
2490         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2491
2492         POSTING_READ(reg);
2493         udelay(150);
2494
2495         /* Ironlake workaround, enable clock pointer after FDI enable*/
2496         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2497         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2498                    FDI_RX_PHASE_SYNC_POINTER_EN);
2499
2500         reg = FDI_RX_IIR(pipe);
2501         for (tries = 0; tries < 5; tries++) {
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if ((temp & FDI_RX_BIT_LOCK)) {
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508                         break;
2509                 }
2510         }
2511         if (tries == 5)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_2;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         reg = FDI_RX_IIR(pipe);
2531         for (tries = 0; tries < 5; tries++) {
2532                 temp = I915_READ(reg);
2533                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534
2535                 if (temp & FDI_RX_SYMBOL_LOCK) {
2536                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (tries == 5)
2542                 DRM_ERROR("FDI train 2 fail!\n");
2543
2544         DRM_DEBUG_KMS("FDI train done\n");
2545
2546 }
2547
2548 static const int snb_b_fdi_train_param[] = {
2549         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2553 };
2554
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561         int pipe = intel_crtc->pipe;
2562         u32 reg, temp, i, retry;
2563
2564         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565            for train result */
2566         reg = FDI_RX_IMR(pipe);
2567         temp = I915_READ(reg);
2568         temp &= ~FDI_RX_SYMBOL_LOCK;
2569         temp &= ~FDI_RX_BIT_LOCK;
2570         I915_WRITE(reg, temp);
2571
2572         POSTING_READ(reg);
2573         udelay(150);
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2580         temp &= ~FDI_LINK_TRAIN_NONE;
2581         temp |= FDI_LINK_TRAIN_PATTERN_1;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         /* SNB-B */
2584         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         I915_WRITE(FDI_RX_MISC(pipe),
2588                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
2590         reg = FDI_RX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         if (HAS_PCH_CPT(dev)) {
2593                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2595         } else {
2596                 temp &= ~FDI_LINK_TRAIN_NONE;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2598         }
2599         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2600
2601         POSTING_READ(reg);
2602         udelay(150);
2603
2604         for (i = 0; i < 4; i++) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 for (retry = 0; retry < 5; retry++) {
2615                         reg = FDI_RX_IIR(pipe);
2616                         temp = I915_READ(reg);
2617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618                         if (temp & FDI_RX_BIT_LOCK) {
2619                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621                                 break;
2622                         }
2623                         udelay(50);
2624                 }
2625                 if (retry < 5)
2626                         break;
2627         }
2628         if (i == 4)
2629                 DRM_ERROR("FDI train 1 fail!\n");
2630
2631         /* Train 2 */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2;
2636         if (IS_GEN6(dev)) {
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 /* SNB-B */
2639                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         }
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         if (HAS_PCH_CPT(dev)) {
2646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         } else {
2649                 temp &= ~FDI_LINK_TRAIN_NONE;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         for (i = 0; i < 4; i++) {
2658                 reg = FDI_TX_CTL(pipe);
2659                 temp = I915_READ(reg);
2660                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661                 temp |= snb_b_fdi_train_param[i];
2662                 I915_WRITE(reg, temp);
2663
2664                 POSTING_READ(reg);
2665                 udelay(500);
2666
2667                 for (retry = 0; retry < 5; retry++) {
2668                         reg = FDI_RX_IIR(pipe);
2669                         temp = I915_READ(reg);
2670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671                         if (temp & FDI_RX_SYMBOL_LOCK) {
2672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674                                 break;
2675                         }
2676                         udelay(50);
2677                 }
2678                 if (retry < 5)
2679                         break;
2680         }
2681         if (i == 4)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         int pipe = intel_crtc->pipe;
2694         u32 reg, temp, i, j;
2695
2696         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697            for train result */
2698         reg = FDI_RX_IMR(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_RX_SYMBOL_LOCK;
2701         temp &= ~FDI_RX_BIT_LOCK;
2702         I915_WRITE(reg, temp);
2703
2704         POSTING_READ(reg);
2705         udelay(150);
2706
2707         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2708                       I915_READ(FDI_RX_IIR(pipe)));
2709
2710         /* Try each vswing and preemphasis setting twice before moving on */
2711         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2712                 /* disable first in case we need to retry */
2713                 reg = FDI_TX_CTL(pipe);
2714                 temp = I915_READ(reg);
2715                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2716                 temp &= ~FDI_TX_ENABLE;
2717                 I915_WRITE(reg, temp);
2718
2719                 reg = FDI_RX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 temp &= ~FDI_LINK_TRAIN_AUTO;
2722                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723                 temp &= ~FDI_RX_ENABLE;
2724                 I915_WRITE(reg, temp);
2725
2726                 /* enable CPU FDI TX and PCH FDI RX */
2727                 reg = FDI_TX_CTL(pipe);
2728                 temp = I915_READ(reg);
2729                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2730                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2731                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2732                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733                 temp |= snb_b_fdi_train_param[j/2];
2734                 temp |= FDI_COMPOSITE_SYNC;
2735                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2736
2737                 I915_WRITE(FDI_RX_MISC(pipe),
2738                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2739
2740                 reg = FDI_RX_CTL(pipe);
2741                 temp = I915_READ(reg);
2742                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2743                 temp |= FDI_COMPOSITE_SYNC;
2744                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2745
2746                 POSTING_READ(reg);
2747                 udelay(1); /* should be 0.5us */
2748
2749                 for (i = 0; i < 4; i++) {
2750                         reg = FDI_RX_IIR(pipe);
2751                         temp = I915_READ(reg);
2752                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2753
2754                         if (temp & FDI_RX_BIT_LOCK ||
2755                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2756                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2757                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2758                                               i);
2759                                 break;
2760                         }
2761                         udelay(1); /* should be 0.5us */
2762                 }
2763                 if (i == 4) {
2764                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2765                         continue;
2766                 }
2767
2768                 /* Train 2 */
2769                 reg = FDI_TX_CTL(pipe);
2770                 temp = I915_READ(reg);
2771                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2772                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2773                 I915_WRITE(reg, temp);
2774
2775                 reg = FDI_RX_CTL(pipe);
2776                 temp = I915_READ(reg);
2777                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2778                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2779                 I915_WRITE(reg, temp);
2780
2781                 POSTING_READ(reg);
2782                 udelay(2); /* should be 1.5us */
2783
2784                 for (i = 0; i < 4; i++) {
2785                         reg = FDI_RX_IIR(pipe);
2786                         temp = I915_READ(reg);
2787                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789                         if (temp & FDI_RX_SYMBOL_LOCK ||
2790                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2791                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2792                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2793                                               i);
2794                                 goto train_done;
2795                         }
2796                         udelay(2); /* should be 1.5us */
2797                 }
2798                 if (i == 4)
2799                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2800         }
2801
2802 train_done:
2803         DRM_DEBUG_KMS("FDI train done.\n");
2804 }
2805
2806 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813
2814         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2818         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2821
2822         POSTING_READ(reg);
2823         udelay(200);
2824
2825         /* Switch from Rawclk to PCDclk */
2826         temp = I915_READ(reg);
2827         I915_WRITE(reg, temp | FDI_PCDCLK);
2828
2829         POSTING_READ(reg);
2830         udelay(200);
2831
2832         /* Enable CPU FDI TX PLL, always on for Ironlake */
2833         reg = FDI_TX_CTL(pipe);
2834         temp = I915_READ(reg);
2835         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2836                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2837
2838                 POSTING_READ(reg);
2839                 udelay(100);
2840         }
2841 }
2842
2843 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2844 {
2845         struct drm_device *dev = intel_crtc->base.dev;
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         int pipe = intel_crtc->pipe;
2848         u32 reg, temp;
2849
2850         /* Switch from PCDclk to Rawclk */
2851         reg = FDI_RX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2854
2855         /* Disable CPU FDI TX PLL */
2856         reg = FDI_TX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2859
2860         POSTING_READ(reg);
2861         udelay(100);
2862
2863         reg = FDI_RX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2866
2867         /* Wait for the clocks to turn off. */
2868         POSTING_READ(reg);
2869         udelay(100);
2870 }
2871
2872 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2873 {
2874         struct drm_device *dev = crtc->dev;
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877         int pipe = intel_crtc->pipe;
2878         u32 reg, temp;
2879
2880         /* disable CPU FDI tx and PCH FDI rx */
2881         reg = FDI_TX_CTL(pipe);
2882         temp = I915_READ(reg);
2883         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2884         POSTING_READ(reg);
2885
2886         reg = FDI_RX_CTL(pipe);
2887         temp = I915_READ(reg);
2888         temp &= ~(0x7 << 16);
2889         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2890         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2891
2892         POSTING_READ(reg);
2893         udelay(100);
2894
2895         /* Ironlake workaround, disable clock pointer after downing FDI */
2896         if (HAS_PCH_IBX(dev)) {
2897                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2898         }
2899
2900         /* still set train pattern 1 */
2901         reg = FDI_TX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         temp &= ~FDI_LINK_TRAIN_NONE;
2904         temp |= FDI_LINK_TRAIN_PATTERN_1;
2905         I915_WRITE(reg, temp);
2906
2907         reg = FDI_RX_CTL(pipe);
2908         temp = I915_READ(reg);
2909         if (HAS_PCH_CPT(dev)) {
2910                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2911                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2912         } else {
2913                 temp &= ~FDI_LINK_TRAIN_NONE;
2914                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2915         }
2916         /* BPC in FDI rx is consistent with that in PIPECONF */
2917         temp &= ~(0x07 << 16);
2918         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2919         I915_WRITE(reg, temp);
2920
2921         POSTING_READ(reg);
2922         udelay(100);
2923 }
2924
2925 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930         unsigned long flags;
2931         bool pending;
2932
2933         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2934             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2935                 return false;
2936
2937         spin_lock_irqsave(&dev->event_lock, flags);
2938         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2939         spin_unlock_irqrestore(&dev->event_lock, flags);
2940
2941         return pending;
2942 }
2943
2944 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2945 {
2946         struct drm_device *dev = crtc->dev;
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948
2949         if (crtc->fb == NULL)
2950                 return;
2951
2952         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2953
2954         wait_event(dev_priv->pending_flip_queue,
2955                    !intel_crtc_has_pending_flip(crtc));
2956
2957         mutex_lock(&dev->struct_mutex);
2958         intel_finish_fb(crtc->fb);
2959         mutex_unlock(&dev->struct_mutex);
2960 }
2961
2962 /* Program iCLKIP clock to the desired frequency */
2963 static void lpt_program_iclkip(struct drm_crtc *crtc)
2964 {
2965         struct drm_device *dev = crtc->dev;
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2968         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969         u32 temp;
2970
2971         mutex_lock(&dev_priv->dpio_lock);
2972
2973         /* It is necessary to ungate the pixclk gate prior to programming
2974          * the divisors, and gate it back when it is done.
2975          */
2976         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2977
2978         /* Disable SSCCTL */
2979         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2980                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2981                                 SBI_SSCCTL_DISABLE,
2982                         SBI_ICLK);
2983
2984         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2985         if (clock == 20000) {
2986                 auxdiv = 1;
2987                 divsel = 0x41;
2988                 phaseinc = 0x20;
2989         } else {
2990                 /* The iCLK virtual clock root frequency is in MHz,
2991                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2992                  * divisors, it is necessary to divide one by another, so we
2993                  * convert the virtual clock precision to KHz here for higher
2994                  * precision.
2995                  */
2996                 u32 iclk_virtual_root_freq = 172800 * 1000;
2997                 u32 iclk_pi_range = 64;
2998                 u32 desired_divisor, msb_divisor_value, pi_value;
2999
3000                 desired_divisor = (iclk_virtual_root_freq / clock);
3001                 msb_divisor_value = desired_divisor / iclk_pi_range;
3002                 pi_value = desired_divisor % iclk_pi_range;
3003
3004                 auxdiv = 0;
3005                 divsel = msb_divisor_value - 2;
3006                 phaseinc = pi_value;
3007         }
3008
3009         /* This should not happen with any sane values */
3010         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3011                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3012         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3013                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3014
3015         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3016                         clock,
3017                         auxdiv,
3018                         divsel,
3019                         phasedir,
3020                         phaseinc);
3021
3022         /* Program SSCDIVINTPHASE6 */
3023         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3024         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3025         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3026         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3027         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3028         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3029         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3030         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031
3032         /* Program SSCAUXDIV */
3033         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3034         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3037
3038         /* Enable modulator and associated divider */
3039         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3040         temp &= ~SBI_SSCCTL_DISABLE;
3041         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3042
3043         /* Wait for initialization time */
3044         udelay(24);
3045
3046         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3047
3048         mutex_unlock(&dev_priv->dpio_lock);
3049 }
3050
3051 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3052                                                 enum pipe pch_transcoder)
3053 {
3054         struct drm_device *dev = crtc->base.dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3057
3058         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3059                    I915_READ(HTOTAL(cpu_transcoder)));
3060         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3061                    I915_READ(HBLANK(cpu_transcoder)));
3062         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3063                    I915_READ(HSYNC(cpu_transcoder)));
3064
3065         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3066                    I915_READ(VTOTAL(cpu_transcoder)));
3067         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3068                    I915_READ(VBLANK(cpu_transcoder)));
3069         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3070                    I915_READ(VSYNC(cpu_transcoder)));
3071         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3072                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3073 }
3074
3075 /*
3076  * Enable PCH resources required for PCH ports:
3077  *   - PCH PLLs
3078  *   - FDI training & RX/TX
3079  *   - update transcoder timings
3080  *   - DP transcoding bits
3081  *   - transcoder
3082  */
3083 static void ironlake_pch_enable(struct drm_crtc *crtc)
3084 {
3085         struct drm_device *dev = crtc->dev;
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3088         int pipe = intel_crtc->pipe;
3089         u32 reg, temp;
3090
3091         assert_pch_transcoder_disabled(dev_priv, pipe);
3092
3093         /* Write the TU size bits before fdi link training, so that error
3094          * detection works. */
3095         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3096                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3097
3098         /* For PCH output, training FDI link */
3099         dev_priv->display.fdi_link_train(crtc);
3100
3101         /* We need to program the right clock selection before writing the pixel
3102          * mutliplier into the DPLL. */
3103         if (HAS_PCH_CPT(dev)) {
3104                 u32 sel;
3105
3106                 temp = I915_READ(PCH_DPLL_SEL);
3107                 temp |= TRANS_DPLL_ENABLE(pipe);
3108                 sel = TRANS_DPLLB_SEL(pipe);
3109                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3110                         temp |= sel;
3111                 else
3112                         temp &= ~sel;
3113                 I915_WRITE(PCH_DPLL_SEL, temp);
3114         }
3115
3116         /* XXX: pch pll's can be enabled any time before we enable the PCH
3117          * transcoder, and we actually should do this to not upset any PCH
3118          * transcoder that already use the clock when we share it.
3119          *
3120          * Note that enable_shared_dpll tries to do the right thing, but
3121          * get_shared_dpll unconditionally resets the pll - we need that to have
3122          * the right LVDS enable sequence. */
3123         ironlake_enable_shared_dpll(intel_crtc);
3124
3125         /* set transcoder timing, panel must allow it */
3126         assert_panel_unlocked(dev_priv, pipe);
3127         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3128
3129         intel_fdi_normal_train(crtc);
3130
3131         /* For PCH DP, enable TRANS_DP_CTL */
3132         if (HAS_PCH_CPT(dev) &&
3133             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3134              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3135                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3136                 reg = TRANS_DP_CTL(pipe);
3137                 temp = I915_READ(reg);
3138                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3139                           TRANS_DP_SYNC_MASK |
3140                           TRANS_DP_BPC_MASK);
3141                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3142                          TRANS_DP_ENH_FRAMING);
3143                 temp |= bpc << 9; /* same format but at 11:9 */
3144
3145                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3146                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3147                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3148                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3149
3150                 switch (intel_trans_dp_port_sel(crtc)) {
3151                 case PCH_DP_B:
3152                         temp |= TRANS_DP_PORT_SEL_B;
3153                         break;
3154                 case PCH_DP_C:
3155                         temp |= TRANS_DP_PORT_SEL_C;
3156                         break;
3157                 case PCH_DP_D:
3158                         temp |= TRANS_DP_PORT_SEL_D;
3159                         break;
3160                 default:
3161                         BUG();
3162                 }
3163
3164                 I915_WRITE(reg, temp);
3165         }
3166
3167         ironlake_enable_pch_transcoder(dev_priv, pipe);
3168 }
3169
3170 static void lpt_pch_enable(struct drm_crtc *crtc)
3171 {
3172         struct drm_device *dev = crtc->dev;
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3175         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3176
3177         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3178
3179         lpt_program_iclkip(crtc);
3180
3181         /* Set transcoder timing. */
3182         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3183
3184         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3185 }
3186
3187 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3188 {
3189         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3190
3191         if (pll == NULL)
3192                 return;
3193
3194         if (pll->refcount == 0) {
3195                 WARN(1, "bad %s refcount\n", pll->name);
3196                 return;
3197         }
3198
3199         if (--pll->refcount == 0) {
3200                 WARN_ON(pll->on);
3201                 WARN_ON(pll->active);
3202         }
3203
3204         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3205 }
3206
3207 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3208 {
3209         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3210         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3211         enum intel_dpll_id i;
3212
3213         if (pll) {
3214                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3215                               crtc->base.base.id, pll->name);
3216                 intel_put_shared_dpll(crtc);
3217         }
3218
3219         if (HAS_PCH_IBX(dev_priv->dev)) {
3220                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3221                 i = (enum intel_dpll_id) crtc->pipe;
3222                 pll = &dev_priv->shared_dplls[i];
3223
3224                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3225                               crtc->base.base.id, pll->name);
3226
3227                 goto found;
3228         }
3229
3230         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3231                 pll = &dev_priv->shared_dplls[i];
3232
3233                 /* Only want to check enabled timings first */
3234                 if (pll->refcount == 0)
3235                         continue;
3236
3237                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3238                            sizeof(pll->hw_state)) == 0) {
3239                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3240                                       crtc->base.base.id,
3241                                       pll->name, pll->refcount, pll->active);
3242
3243                         goto found;
3244                 }
3245         }
3246
3247         /* Ok no matching timings, maybe there's a free one? */
3248         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3249                 pll = &dev_priv->shared_dplls[i];
3250                 if (pll->refcount == 0) {
3251                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3252                                       crtc->base.base.id, pll->name);
3253                         goto found;
3254                 }
3255         }
3256
3257         return NULL;
3258
3259 found:
3260         crtc->config.shared_dpll = i;
3261         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3262                          pipe_name(crtc->pipe));
3263
3264         if (pll->active == 0) {
3265                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3266                        sizeof(pll->hw_state));
3267
3268                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3269                 WARN_ON(pll->on);
3270                 assert_shared_dpll_disabled(dev_priv, pll);
3271
3272                 pll->mode_set(dev_priv, pll);
3273         }
3274         pll->refcount++;
3275
3276         return pll;
3277 }
3278
3279 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         int dslreg = PIPEDSL(pipe);
3283         u32 temp;
3284
3285         temp = I915_READ(dslreg);
3286         udelay(500);
3287         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3288                 if (wait_for(I915_READ(dslreg) != temp, 5))
3289                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3290         }
3291 }
3292
3293 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->base.dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         int pipe = crtc->pipe;
3298
3299         if (crtc->config.pch_pfit.enabled) {
3300                 /* Force use of hard-coded filter coefficients
3301                  * as some pre-programmed values are broken,
3302                  * e.g. x201.
3303                  */
3304                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3305                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3306                                                  PF_PIPE_SEL_IVB(pipe));
3307                 else
3308                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3309                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3310                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3311         }
3312 }
3313
3314 static void intel_enable_planes(struct drm_crtc *crtc)
3315 {
3316         struct drm_device *dev = crtc->dev;
3317         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3318         struct intel_plane *intel_plane;
3319
3320         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3321                 if (intel_plane->pipe == pipe)
3322                         intel_plane_restore(&intel_plane->base);
3323 }
3324
3325 static void intel_disable_planes(struct drm_crtc *crtc)
3326 {
3327         struct drm_device *dev = crtc->dev;
3328         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3329         struct intel_plane *intel_plane;
3330
3331         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3332                 if (intel_plane->pipe == pipe)
3333                         intel_plane_disable(&intel_plane->base);
3334 }
3335
3336 void hsw_enable_ips(struct intel_crtc *crtc)
3337 {
3338         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3339
3340         if (!crtc->config.ips_enabled)
3341                 return;
3342
3343         /* We can only enable IPS after we enable a plane and wait for a vblank.
3344          * We guarantee that the plane is enabled by calling intel_enable_ips
3345          * only after intel_enable_plane. And intel_enable_plane already waits
3346          * for a vblank, so all we need to do here is to enable the IPS bit. */
3347         assert_plane_enabled(dev_priv, crtc->plane);
3348         I915_WRITE(IPS_CTL, IPS_ENABLE);
3349
3350         /* The bit only becomes 1 in the next vblank, so this wait here is
3351          * essentially intel_wait_for_vblank. If we don't have this and don't
3352          * wait for vblanks until the end of crtc_enable, then the HW state
3353          * readout code will complain that the expected IPS_CTL value is not the
3354          * one we read. */
3355         if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3356                 DRM_ERROR("Timed out waiting for IPS enable\n");
3357 }
3358
3359 void hsw_disable_ips(struct intel_crtc *crtc)
3360 {
3361         struct drm_device *dev = crtc->base.dev;
3362         struct drm_i915_private *dev_priv = dev->dev_private;
3363
3364         if (!crtc->config.ips_enabled)
3365                 return;
3366
3367         assert_plane_enabled(dev_priv, crtc->plane);
3368         I915_WRITE(IPS_CTL, 0);
3369         POSTING_READ(IPS_CTL);
3370
3371         /* We need to wait for a vblank before we can disable the plane. */
3372         intel_wait_for_vblank(dev, crtc->pipe);
3373 }
3374
3375 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3376 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3377 {
3378         struct drm_device *dev = crtc->dev;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381         enum pipe pipe = intel_crtc->pipe;
3382         int palreg = PALETTE(pipe);
3383         int i;
3384         bool reenable_ips = false;
3385
3386         /* The clocks have to be on to load the palette. */
3387         if (!crtc->enabled || !intel_crtc->active)
3388                 return;
3389
3390         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3391                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3392                         assert_dsi_pll_enabled(dev_priv);
3393                 else
3394                         assert_pll_enabled(dev_priv, pipe);
3395         }
3396
3397         /* use legacy palette for Ironlake */
3398         if (HAS_PCH_SPLIT(dev))
3399                 palreg = LGC_PALETTE(pipe);
3400
3401         /* Workaround : Do not read or write the pipe palette/gamma data while
3402          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3403          */
3404         if (intel_crtc->config.ips_enabled &&
3405             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3406              GAMMA_MODE_MODE_SPLIT)) {
3407                 hsw_disable_ips(intel_crtc);
3408                 reenable_ips = true;
3409         }
3410
3411         for (i = 0; i < 256; i++) {
3412                 I915_WRITE(palreg + 4 * i,
3413                            (intel_crtc->lut_r[i] << 16) |
3414                            (intel_crtc->lut_g[i] << 8) |
3415                            intel_crtc->lut_b[i]);
3416         }
3417
3418         if (reenable_ips)
3419                 hsw_enable_ips(intel_crtc);
3420 }
3421
3422 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3423 {
3424         struct drm_device *dev = crtc->dev;
3425         struct drm_i915_private *dev_priv = dev->dev_private;
3426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427         struct intel_encoder *encoder;
3428         int pipe = intel_crtc->pipe;
3429         int plane = intel_crtc->plane;
3430
3431         WARN_ON(!crtc->enabled);
3432
3433         if (intel_crtc->active)
3434                 return;
3435
3436         intel_crtc->active = true;
3437
3438         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3439         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3440
3441         for_each_encoder_on_crtc(dev, crtc, encoder)
3442                 if (encoder->pre_enable)
3443                         encoder->pre_enable(encoder);
3444
3445         if (intel_crtc->config.has_pch_encoder) {
3446                 /* Note: FDI PLL enabling _must_ be done before we enable the
3447                  * cpu pipes, hence this is separate from all the other fdi/pch
3448                  * enabling. */
3449                 ironlake_fdi_pll_enable(intel_crtc);
3450         } else {
3451                 assert_fdi_tx_disabled(dev_priv, pipe);
3452                 assert_fdi_rx_disabled(dev_priv, pipe);
3453         }
3454
3455         ironlake_pfit_enable(intel_crtc);
3456
3457         /*
3458          * On ILK+ LUT must be loaded before the pipe is running but with
3459          * clocks enabled
3460          */
3461         intel_crtc_load_lut(crtc);
3462
3463         intel_update_watermarks(crtc);
3464         intel_enable_pipe(dev_priv, pipe,
3465                           intel_crtc->config.has_pch_encoder, false);
3466         intel_enable_primary_plane(dev_priv, plane, pipe);
3467         intel_enable_planes(crtc);
3468         intel_crtc_update_cursor(crtc, true);
3469
3470         if (intel_crtc->config.has_pch_encoder)
3471                 ironlake_pch_enable(crtc);
3472
3473         mutex_lock(&dev->struct_mutex);
3474         intel_update_fbc(dev);
3475         mutex_unlock(&dev->struct_mutex);
3476
3477         for_each_encoder_on_crtc(dev, crtc, encoder)
3478                 encoder->enable(encoder);
3479
3480         if (HAS_PCH_CPT(dev))
3481                 cpt_verify_modeset(dev, intel_crtc->pipe);
3482
3483         /*
3484          * There seems to be a race in PCH platform hw (at least on some
3485          * outputs) where an enabled pipe still completes any pageflip right
3486          * away (as if the pipe is off) instead of waiting for vblank. As soon
3487          * as the first vblank happend, everything works as expected. Hence just
3488          * wait for one vblank before returning to avoid strange things
3489          * happening.
3490          */
3491         intel_wait_for_vblank(dev, intel_crtc->pipe);
3492 }
3493
3494 /* IPS only exists on ULT machines and is tied to pipe A. */
3495 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3496 {
3497         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3498 }
3499
3500 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3501 {
3502         struct drm_device *dev = crtc->dev;
3503         struct drm_i915_private *dev_priv = dev->dev_private;
3504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505         int pipe = intel_crtc->pipe;
3506         int plane = intel_crtc->plane;
3507
3508         intel_enable_primary_plane(dev_priv, plane, pipe);
3509         intel_enable_planes(crtc);
3510         intel_crtc_update_cursor(crtc, true);
3511
3512         hsw_enable_ips(intel_crtc);
3513
3514         mutex_lock(&dev->struct_mutex);
3515         intel_update_fbc(dev);
3516         mutex_unlock(&dev->struct_mutex);
3517 }
3518
3519 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3520 {
3521         struct drm_device *dev = crtc->dev;
3522         struct drm_i915_private *dev_priv = dev->dev_private;
3523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524         int pipe = intel_crtc->pipe;
3525         int plane = intel_crtc->plane;
3526
3527         intel_crtc_wait_for_pending_flips(crtc);
3528         drm_vblank_off(dev, pipe);
3529
3530         /* FBC must be disabled before disabling the plane on HSW. */
3531         if (dev_priv->fbc.plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         hsw_disable_ips(intel_crtc);
3535
3536         intel_crtc_update_cursor(crtc, false);
3537         intel_disable_planes(crtc);
3538         intel_disable_primary_plane(dev_priv, plane, pipe);
3539 }
3540
3541 /*
3542  * This implements the workaround described in the "notes" section of the mode
3543  * set sequence documentation. When going from no pipes or single pipe to
3544  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3545  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3546  */
3547 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3548 {
3549         struct drm_device *dev = crtc->base.dev;
3550         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3551
3552         /* We want to get the other_active_crtc only if there's only 1 other
3553          * active crtc. */
3554         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3555                 if (!crtc_it->active || crtc_it == crtc)
3556                         continue;
3557
3558                 if (other_active_crtc)
3559                         return;
3560
3561                 other_active_crtc = crtc_it;
3562         }
3563         if (!other_active_crtc)
3564                 return;
3565
3566         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3567         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3568 }
3569
3570 static void haswell_crtc_enable(struct drm_crtc *crtc)
3571 {
3572         struct drm_device *dev = crtc->dev;
3573         struct drm_i915_private *dev_priv = dev->dev_private;
3574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575         struct intel_encoder *encoder;
3576         int pipe = intel_crtc->pipe;
3577
3578         WARN_ON(!crtc->enabled);
3579
3580         if (intel_crtc->active)
3581                 return;
3582
3583         intel_crtc->active = true;
3584
3585         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3586         if (intel_crtc->config.has_pch_encoder)
3587                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3588
3589         if (intel_crtc->config.has_pch_encoder)
3590                 dev_priv->display.fdi_link_train(crtc);
3591
3592         for_each_encoder_on_crtc(dev, crtc, encoder)
3593                 if (encoder->pre_enable)
3594                         encoder->pre_enable(encoder);
3595
3596         intel_ddi_enable_pipe_clock(intel_crtc);
3597
3598         ironlake_pfit_enable(intel_crtc);
3599
3600         /*
3601          * On ILK+ LUT must be loaded before the pipe is running but with
3602          * clocks enabled
3603          */
3604         intel_crtc_load_lut(crtc);
3605
3606         intel_ddi_set_pipe_settings(crtc);
3607         intel_ddi_enable_transcoder_func(crtc);
3608
3609         intel_update_watermarks(crtc);
3610         intel_enable_pipe(dev_priv, pipe,
3611                           intel_crtc->config.has_pch_encoder, false);
3612
3613         if (intel_crtc->config.has_pch_encoder)
3614                 lpt_pch_enable(crtc);
3615
3616         for_each_encoder_on_crtc(dev, crtc, encoder) {
3617                 encoder->enable(encoder);
3618                 intel_opregion_notify_encoder(encoder, true);
3619         }
3620
3621         /* If we change the relative order between pipe/planes enabling, we need
3622          * to change the workaround. */
3623         haswell_mode_set_planes_workaround(intel_crtc);
3624         haswell_crtc_enable_planes(crtc);
3625
3626         /*
3627          * There seems to be a race in PCH platform hw (at least on some
3628          * outputs) where an enabled pipe still completes any pageflip right
3629          * away (as if the pipe is off) instead of waiting for vblank. As soon
3630          * as the first vblank happend, everything works as expected. Hence just
3631          * wait for one vblank before returning to avoid strange things
3632          * happening.
3633          */
3634         intel_wait_for_vblank(dev, intel_crtc->pipe);
3635 }
3636
3637 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3638 {
3639         struct drm_device *dev = crtc->base.dev;
3640         struct drm_i915_private *dev_priv = dev->dev_private;
3641         int pipe = crtc->pipe;
3642
3643         /* To avoid upsetting the power well on haswell only disable the pfit if
3644          * it's in use. The hw state code will make sure we get this right. */
3645         if (crtc->config.pch_pfit.enabled) {
3646                 I915_WRITE(PF_CTL(pipe), 0);
3647                 I915_WRITE(PF_WIN_POS(pipe), 0);
3648                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3649         }
3650 }
3651
3652 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3653 {
3654         struct drm_device *dev = crtc->dev;
3655         struct drm_i915_private *dev_priv = dev->dev_private;
3656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657         struct intel_encoder *encoder;
3658         int pipe = intel_crtc->pipe;
3659         int plane = intel_crtc->plane;
3660         u32 reg, temp;
3661
3662
3663         if (!intel_crtc->active)
3664                 return;
3665
3666         for_each_encoder_on_crtc(dev, crtc, encoder)
3667                 encoder->disable(encoder);
3668
3669         intel_crtc_wait_for_pending_flips(crtc);
3670         drm_vblank_off(dev, pipe);
3671
3672         if (dev_priv->fbc.plane == plane)
3673                 intel_disable_fbc(dev);
3674
3675         intel_crtc_update_cursor(crtc, false);
3676         intel_disable_planes(crtc);
3677         intel_disable_primary_plane(dev_priv, plane, pipe);
3678
3679         if (intel_crtc->config.has_pch_encoder)
3680                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3681
3682         intel_disable_pipe(dev_priv, pipe);
3683
3684         ironlake_pfit_disable(intel_crtc);
3685
3686         for_each_encoder_on_crtc(dev, crtc, encoder)
3687                 if (encoder->post_disable)
3688                         encoder->post_disable(encoder);
3689
3690         if (intel_crtc->config.has_pch_encoder) {
3691                 ironlake_fdi_disable(crtc);
3692
3693                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3694                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3695
3696                 if (HAS_PCH_CPT(dev)) {
3697                         /* disable TRANS_DP_CTL */
3698                         reg = TRANS_DP_CTL(pipe);
3699                         temp = I915_READ(reg);
3700                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3701                                   TRANS_DP_PORT_SEL_MASK);
3702                         temp |= TRANS_DP_PORT_SEL_NONE;
3703                         I915_WRITE(reg, temp);
3704
3705                         /* disable DPLL_SEL */
3706                         temp = I915_READ(PCH_DPLL_SEL);
3707                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3708                         I915_WRITE(PCH_DPLL_SEL, temp);
3709                 }
3710
3711                 /* disable PCH DPLL */
3712                 intel_disable_shared_dpll(intel_crtc);
3713
3714                 ironlake_fdi_pll_disable(intel_crtc);
3715         }
3716
3717         intel_crtc->active = false;
3718         intel_update_watermarks(crtc);
3719
3720         mutex_lock(&dev->struct_mutex);
3721         intel_update_fbc(dev);
3722         mutex_unlock(&dev->struct_mutex);
3723 }
3724
3725 static void haswell_crtc_disable(struct drm_crtc *crtc)
3726 {
3727         struct drm_device *dev = crtc->dev;
3728         struct drm_i915_private *dev_priv = dev->dev_private;
3729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3730         struct intel_encoder *encoder;
3731         int pipe = intel_crtc->pipe;
3732         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3733
3734         if (!intel_crtc->active)
3735                 return;
3736
3737         haswell_crtc_disable_planes(crtc);
3738
3739         for_each_encoder_on_crtc(dev, crtc, encoder) {
3740                 intel_opregion_notify_encoder(encoder, false);
3741                 encoder->disable(encoder);
3742         }
3743
3744         if (intel_crtc->config.has_pch_encoder)
3745                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3746         intel_disable_pipe(dev_priv, pipe);
3747
3748         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3749
3750         ironlake_pfit_disable(intel_crtc);
3751
3752         intel_ddi_disable_pipe_clock(intel_crtc);
3753
3754         for_each_encoder_on_crtc(dev, crtc, encoder)
3755                 if (encoder->post_disable)
3756                         encoder->post_disable(encoder);
3757
3758         if (intel_crtc->config.has_pch_encoder) {
3759                 lpt_disable_pch_transcoder(dev_priv);
3760                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3761                 intel_ddi_fdi_disable(crtc);
3762         }
3763
3764         intel_crtc->active = false;
3765         intel_update_watermarks(crtc);
3766
3767         mutex_lock(&dev->struct_mutex);
3768         intel_update_fbc(dev);
3769         mutex_unlock(&dev->struct_mutex);
3770 }
3771
3772 static void ironlake_crtc_off(struct drm_crtc *crtc)
3773 {
3774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775         intel_put_shared_dpll(intel_crtc);
3776 }
3777
3778 static void haswell_crtc_off(struct drm_crtc *crtc)
3779 {
3780         intel_ddi_put_crtc_pll(crtc);
3781 }
3782
3783 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3784 {
3785         if (!enable && intel_crtc->overlay) {
3786                 struct drm_device *dev = intel_crtc->base.dev;
3787                 struct drm_i915_private *dev_priv = dev->dev_private;
3788
3789                 mutex_lock(&dev->struct_mutex);
3790                 dev_priv->mm.interruptible = false;
3791                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3792                 dev_priv->mm.interruptible = true;
3793                 mutex_unlock(&dev->struct_mutex);
3794         }
3795
3796         /* Let userspace switch the overlay on again. In most cases userspace
3797          * has to recompute where to put it anyway.
3798          */
3799 }
3800
3801 /**
3802  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3803  * cursor plane briefly if not already running after enabling the display
3804  * plane.
3805  * This workaround avoids occasional blank screens when self refresh is
3806  * enabled.
3807  */
3808 static void
3809 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3810 {
3811         u32 cntl = I915_READ(CURCNTR(pipe));
3812
3813         if ((cntl & CURSOR_MODE) == 0) {
3814                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3815
3816                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3817                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3818                 intel_wait_for_vblank(dev_priv->dev, pipe);
3819                 I915_WRITE(CURCNTR(pipe), cntl);
3820                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3821                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3822         }
3823 }
3824
3825 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->base.dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc_config *pipe_config = &crtc->config;
3830
3831         if (!crtc->config.gmch_pfit.control)
3832                 return;
3833
3834         /*
3835          * The panel fitter should only be adjusted whilst the pipe is disabled,
3836          * according to register description and PRM.
3837          */
3838         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3839         assert_pipe_disabled(dev_priv, crtc->pipe);
3840
3841         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3842         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3843
3844         /* Border color in case we don't scale up to the full screen. Black by
3845          * default, change to something else for debugging. */
3846         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3847 }
3848
3849 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3850 {
3851         struct drm_device *dev = crtc->dev;
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3854         struct intel_encoder *encoder;
3855         int pipe = intel_crtc->pipe;
3856         int plane = intel_crtc->plane;
3857         bool is_dsi;
3858
3859         WARN_ON(!crtc->enabled);
3860
3861         if (intel_crtc->active)
3862                 return;
3863
3864         intel_crtc->active = true;
3865
3866         for_each_encoder_on_crtc(dev, crtc, encoder)
3867                 if (encoder->pre_pll_enable)
3868                         encoder->pre_pll_enable(encoder);
3869
3870         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3871
3872         if (!is_dsi)
3873                 vlv_enable_pll(intel_crtc);
3874
3875         for_each_encoder_on_crtc(dev, crtc, encoder)
3876                 if (encoder->pre_enable)
3877                         encoder->pre_enable(encoder);
3878
3879         i9xx_pfit_enable(intel_crtc);
3880
3881         intel_crtc_load_lut(crtc);
3882
3883         intel_update_watermarks(crtc);
3884         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3885         intel_enable_primary_plane(dev_priv, plane, pipe);
3886         intel_enable_planes(crtc);
3887         intel_crtc_update_cursor(crtc, true);
3888
3889         intel_update_fbc(dev);
3890
3891         for_each_encoder_on_crtc(dev, crtc, encoder)
3892                 encoder->enable(encoder);
3893 }
3894
3895 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3896 {
3897         struct drm_device *dev = crtc->dev;
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3900         struct intel_encoder *encoder;
3901         int pipe = intel_crtc->pipe;
3902         int plane = intel_crtc->plane;
3903
3904         WARN_ON(!crtc->enabled);
3905
3906         if (intel_crtc->active)
3907                 return;
3908
3909         intel_crtc->active = true;
3910
3911         for_each_encoder_on_crtc(dev, crtc, encoder)
3912                 if (encoder->pre_enable)
3913                         encoder->pre_enable(encoder);
3914
3915         i9xx_enable_pll(intel_crtc);
3916
3917         i9xx_pfit_enable(intel_crtc);
3918
3919         intel_crtc_load_lut(crtc);
3920
3921         intel_update_watermarks(crtc);
3922         intel_enable_pipe(dev_priv, pipe, false, false);
3923         intel_enable_primary_plane(dev_priv, plane, pipe);
3924         intel_enable_planes(crtc);
3925         /* The fixup needs to happen before cursor is enabled */
3926         if (IS_G4X(dev))
3927                 g4x_fixup_plane(dev_priv, pipe);
3928         intel_crtc_update_cursor(crtc, true);
3929
3930         /* Give the overlay scaler a chance to enable if it's on this pipe */
3931         intel_crtc_dpms_overlay(intel_crtc, true);
3932
3933         intel_update_fbc(dev);
3934
3935         for_each_encoder_on_crtc(dev, crtc, encoder)
3936                 encoder->enable(encoder);
3937 }
3938
3939 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3940 {
3941         struct drm_device *dev = crtc->base.dev;
3942         struct drm_i915_private *dev_priv = dev->dev_private;
3943
3944         if (!crtc->config.gmch_pfit.control)
3945                 return;
3946
3947         assert_pipe_disabled(dev_priv, crtc->pipe);
3948
3949         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3950                          I915_READ(PFIT_CONTROL));
3951         I915_WRITE(PFIT_CONTROL, 0);
3952 }
3953
3954 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3955 {
3956         struct drm_device *dev = crtc->dev;
3957         struct drm_i915_private *dev_priv = dev->dev_private;
3958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3959         struct intel_encoder *encoder;
3960         int pipe = intel_crtc->pipe;
3961         int plane = intel_crtc->plane;
3962
3963         if (!intel_crtc->active)
3964                 return;
3965
3966         for_each_encoder_on_crtc(dev, crtc, encoder)
3967                 encoder->disable(encoder);
3968
3969         /* Give the overlay scaler a chance to disable if it's on this pipe */
3970         intel_crtc_wait_for_pending_flips(crtc);
3971         drm_vblank_off(dev, pipe);
3972
3973         if (dev_priv->fbc.plane == plane)
3974                 intel_disable_fbc(dev);
3975
3976         intel_crtc_dpms_overlay(intel_crtc, false);
3977         intel_crtc_update_cursor(crtc, false);
3978         intel_disable_planes(crtc);
3979         intel_disable_primary_plane(dev_priv, plane, pipe);
3980
3981         intel_disable_pipe(dev_priv, pipe);
3982
3983         i9xx_pfit_disable(intel_crtc);
3984
3985         for_each_encoder_on_crtc(dev, crtc, encoder)
3986                 if (encoder->post_disable)
3987                         encoder->post_disable(encoder);
3988
3989         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3990                 vlv_disable_pll(dev_priv, pipe);
3991         else if (!IS_VALLEYVIEW(dev))
3992                 i9xx_disable_pll(dev_priv, pipe);
3993
3994         intel_crtc->active = false;
3995         intel_update_watermarks(crtc);
3996
3997         intel_update_fbc(dev);
3998 }
3999
4000 static void i9xx_crtc_off(struct drm_crtc *crtc)
4001 {
4002 }
4003
4004 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4005                                     bool enabled)
4006 {
4007         struct drm_device *dev = crtc->dev;
4008         struct drm_i915_master_private *master_priv;
4009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4010         int pipe = intel_crtc->pipe;
4011
4012         if (!dev->primary->master)
4013                 return;
4014
4015         master_priv = dev->primary->master->driver_priv;
4016         if (!master_priv->sarea_priv)
4017                 return;
4018
4019         switch (pipe) {
4020         case 0:
4021                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4022                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4023                 break;
4024         case 1:
4025                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4026                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4027                 break;
4028         default:
4029                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4030                 break;
4031         }
4032 }
4033
4034 /**
4035  * Sets the power management mode of the pipe and plane.
4036  */
4037 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4038 {
4039         struct drm_device *dev = crtc->dev;
4040         struct drm_i915_private *dev_priv = dev->dev_private;
4041         struct intel_encoder *intel_encoder;
4042         bool enable = false;
4043
4044         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4045                 enable |= intel_encoder->connectors_active;
4046
4047         if (enable)
4048                 dev_priv->display.crtc_enable(crtc);
4049         else
4050                 dev_priv->display.crtc_disable(crtc);
4051
4052         intel_crtc_update_sarea(crtc, enable);
4053 }
4054
4055 static void intel_crtc_disable(struct drm_crtc *crtc)
4056 {
4057         struct drm_device *dev = crtc->dev;
4058         struct drm_connector *connector;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4061
4062         /* crtc should still be enabled when we disable it. */
4063         WARN_ON(!crtc->enabled);
4064
4065         dev_priv->display.crtc_disable(crtc);
4066         intel_crtc->eld_vld = false;
4067         intel_crtc_update_sarea(crtc, false);
4068         dev_priv->display.off(crtc);
4069
4070         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4071         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4072         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4073
4074         if (crtc->fb) {
4075                 mutex_lock(&dev->struct_mutex);
4076                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4077                 mutex_unlock(&dev->struct_mutex);
4078                 crtc->fb = NULL;
4079         }
4080
4081         /* Update computed state. */
4082         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4083                 if (!connector->encoder || !connector->encoder->crtc)
4084                         continue;
4085
4086                 if (connector->encoder->crtc != crtc)
4087                         continue;
4088
4089                 connector->dpms = DRM_MODE_DPMS_OFF;
4090                 to_intel_encoder(connector->encoder)->connectors_active = false;
4091         }
4092 }
4093
4094 void intel_encoder_destroy(struct drm_encoder *encoder)
4095 {
4096         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4097
4098         drm_encoder_cleanup(encoder);
4099         kfree(intel_encoder);
4100 }
4101
4102 /* Simple dpms helper for encoders with just one connector, no cloning and only
4103  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4104  * state of the entire output pipe. */
4105 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4106 {
4107         if (mode == DRM_MODE_DPMS_ON) {
4108                 encoder->connectors_active = true;
4109
4110                 intel_crtc_update_dpms(encoder->base.crtc);
4111         } else {
4112                 encoder->connectors_active = false;
4113
4114                 intel_crtc_update_dpms(encoder->base.crtc);
4115         }
4116 }
4117
4118 /* Cross check the actual hw state with our own modeset state tracking (and it's
4119  * internal consistency). */
4120 static void intel_connector_check_state(struct intel_connector *connector)
4121 {
4122         if (connector->get_hw_state(connector)) {
4123                 struct intel_encoder *encoder = connector->encoder;
4124                 struct drm_crtc *crtc;
4125                 bool encoder_enabled;
4126                 enum pipe pipe;
4127
4128                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4129                               connector->base.base.id,
4130                               drm_get_connector_name(&connector->base));
4131
4132                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4133                      "wrong connector dpms state\n");
4134                 WARN(connector->base.encoder != &encoder->base,
4135                      "active connector not linked to encoder\n");
4136                 WARN(!encoder->connectors_active,
4137                      "encoder->connectors_active not set\n");
4138
4139                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4140                 WARN(!encoder_enabled, "encoder not enabled\n");
4141                 if (WARN_ON(!encoder->base.crtc))
4142                         return;
4143
4144                 crtc = encoder->base.crtc;
4145
4146                 WARN(!crtc->enabled, "crtc not enabled\n");
4147                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4148                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4149                      "encoder active on the wrong pipe\n");
4150         }
4151 }
4152
4153 /* Even simpler default implementation, if there's really no special case to
4154  * consider. */
4155 void intel_connector_dpms(struct drm_connector *connector, int mode)
4156 {
4157         struct intel_encoder *encoder = intel_attached_encoder(connector);
4158
4159         /* All the simple cases only support two dpms states. */
4160         if (mode != DRM_MODE_DPMS_ON)
4161                 mode = DRM_MODE_DPMS_OFF;
4162
4163         if (mode == connector->dpms)
4164                 return;
4165
4166         connector->dpms = mode;
4167
4168         /* Only need to change hw state when actually enabled */
4169         if (encoder->base.crtc)
4170                 intel_encoder_dpms(encoder, mode);
4171         else
4172                 WARN_ON(encoder->connectors_active != false);
4173
4174         intel_modeset_check_state(connector->dev);
4175 }
4176
4177 /* Simple connector->get_hw_state implementation for encoders that support only
4178  * one connector and no cloning and hence the encoder state determines the state
4179  * of the connector. */
4180 bool intel_connector_get_hw_state(struct intel_connector *connector)
4181 {
4182         enum pipe pipe = 0;
4183         struct intel_encoder *encoder = connector->encoder;
4184
4185         return encoder->get_hw_state(encoder, &pipe);
4186 }
4187
4188 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4189                                      struct intel_crtc_config *pipe_config)
4190 {
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         struct intel_crtc *pipe_B_crtc =
4193                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4194
4195         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4196                       pipe_name(pipe), pipe_config->fdi_lanes);
4197         if (pipe_config->fdi_lanes > 4) {
4198                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4199                               pipe_name(pipe), pipe_config->fdi_lanes);
4200                 return false;
4201         }
4202
4203         if (IS_HASWELL(dev)) {
4204                 if (pipe_config->fdi_lanes > 2) {
4205                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4206                                       pipe_config->fdi_lanes);
4207                         return false;
4208                 } else {
4209                         return true;
4210                 }
4211         }
4212
4213         if (INTEL_INFO(dev)->num_pipes == 2)
4214                 return true;
4215
4216         /* Ivybridge 3 pipe is really complicated */
4217         switch (pipe) {
4218         case PIPE_A:
4219                 return true;
4220         case PIPE_B:
4221                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4222                     pipe_config->fdi_lanes > 2) {
4223                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4224                                       pipe_name(pipe), pipe_config->fdi_lanes);
4225                         return false;
4226                 }
4227                 return true;
4228         case PIPE_C:
4229                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4230                     pipe_B_crtc->config.fdi_lanes <= 2) {
4231                         if (pipe_config->fdi_lanes > 2) {
4232                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4233                                               pipe_name(pipe), pipe_config->fdi_lanes);
4234                                 return false;
4235                         }
4236                 } else {
4237                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4238                         return false;
4239                 }
4240                 return true;
4241         default:
4242                 BUG();
4243         }
4244 }
4245
4246 #define RETRY 1
4247 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4248                                        struct intel_crtc_config *pipe_config)
4249 {
4250         struct drm_device *dev = intel_crtc->base.dev;
4251         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4252         int lane, link_bw, fdi_dotclock;
4253         bool setup_ok, needs_recompute = false;
4254
4255 retry:
4256         /* FDI is a binary signal running at ~2.7GHz, encoding
4257          * each output octet as 10 bits. The actual frequency
4258          * is stored as a divider into a 100MHz clock, and the
4259          * mode pixel clock is stored in units of 1KHz.
4260          * Hence the bw of each lane in terms of the mode signal
4261          * is:
4262          */
4263         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4264
4265         fdi_dotclock = adjusted_mode->crtc_clock;
4266
4267         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4268                                            pipe_config->pipe_bpp);
4269
4270         pipe_config->fdi_lanes = lane;
4271
4272         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4273                                link_bw, &pipe_config->fdi_m_n);
4274
4275         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4276                                             intel_crtc->pipe, pipe_config);
4277         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4278                 pipe_config->pipe_bpp -= 2*3;
4279                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4280                               pipe_config->pipe_bpp);
4281                 needs_recompute = true;
4282                 pipe_config->bw_constrained = true;
4283
4284                 goto retry;
4285         }
4286
4287         if (needs_recompute)
4288                 return RETRY;
4289
4290         return setup_ok ? 0 : -EINVAL;
4291 }
4292
4293 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4294                                    struct intel_crtc_config *pipe_config)
4295 {
4296         pipe_config->ips_enabled = i915_enable_ips &&
4297                                    hsw_crtc_supports_ips(crtc) &&
4298                                    pipe_config->pipe_bpp <= 24;
4299 }
4300
4301 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4302                                      struct intel_crtc_config *pipe_config)
4303 {
4304         struct drm_device *dev = crtc->base.dev;
4305         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4306
4307         /* FIXME should check pixel clock limits on all platforms */
4308         if (INTEL_INFO(dev)->gen < 4) {
4309                 struct drm_i915_private *dev_priv = dev->dev_private;
4310                 int clock_limit =
4311                         dev_priv->display.get_display_clock_speed(dev);
4312
4313                 /*
4314                  * Enable pixel doubling when the dot clock
4315                  * is > 90% of the (display) core speed.
4316                  *
4317                  * GDG double wide on either pipe,
4318                  * otherwise pipe A only.
4319                  */
4320                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4321                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4322                         clock_limit *= 2;
4323                         pipe_config->double_wide = true;
4324                 }
4325
4326                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4327                         return -EINVAL;
4328         }
4329
4330         /*
4331          * Pipe horizontal size must be even in:
4332          * - DVO ganged mode
4333          * - LVDS dual channel mode
4334          * - Double wide pipe
4335          */
4336         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4337              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4338                 pipe_config->pipe_src_w &= ~1;
4339
4340         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4341          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4342          */
4343         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4344                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4345                 return -EINVAL;
4346
4347         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4348                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4349         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4350                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4351                  * for lvds. */
4352                 pipe_config->pipe_bpp = 8*3;
4353         }
4354
4355         if (HAS_IPS(dev))
4356                 hsw_compute_ips_config(crtc, pipe_config);
4357
4358         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4359          * clock survives for now. */
4360         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4361                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4362
4363         if (pipe_config->has_pch_encoder)
4364                 return ironlake_fdi_compute_config(crtc, pipe_config);
4365
4366         return 0;
4367 }
4368
4369 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4370 {
4371         return 400000; /* FIXME */
4372 }
4373
4374 static int i945_get_display_clock_speed(struct drm_device *dev)
4375 {
4376         return 400000;
4377 }
4378
4379 static int i915_get_display_clock_speed(struct drm_device *dev)
4380 {
4381         return 333000;
4382 }
4383
4384 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4385 {
4386         return 200000;
4387 }
4388
4389 static int pnv_get_display_clock_speed(struct drm_device *dev)
4390 {
4391         u16 gcfgc = 0;
4392
4393         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4394
4395         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4396         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4397                 return 267000;
4398         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4399                 return 333000;
4400         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4401                 return 444000;
4402         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4403                 return 200000;
4404         default:
4405                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4406         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4407                 return 133000;
4408         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4409                 return 167000;
4410         }
4411 }
4412
4413 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4414 {
4415         u16 gcfgc = 0;
4416
4417         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4418
4419         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4420                 return 133000;
4421         else {
4422                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4423                 case GC_DISPLAY_CLOCK_333_MHZ:
4424                         return 333000;
4425                 default:
4426                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4427                         return 190000;
4428                 }
4429         }
4430 }
4431
4432 static int i865_get_display_clock_speed(struct drm_device *dev)
4433 {
4434         return 266000;
4435 }
4436
4437 static int i855_get_display_clock_speed(struct drm_device *dev)
4438 {
4439         u16 hpllcc = 0;
4440         /* Assume that the hardware is in the high speed state.  This
4441          * should be the default.
4442          */
4443         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4444         case GC_CLOCK_133_200:
4445         case GC_CLOCK_100_200:
4446                 return 200000;
4447         case GC_CLOCK_166_250:
4448                 return 250000;
4449         case GC_CLOCK_100_133:
4450                 return 133000;
4451         }
4452
4453         /* Shouldn't happen */
4454         return 0;
4455 }
4456
4457 static int i830_get_display_clock_speed(struct drm_device *dev)
4458 {
4459         return 133000;
4460 }
4461
4462 static void
4463 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4464 {
4465         while (*num > DATA_LINK_M_N_MASK ||
4466                *den > DATA_LINK_M_N_MASK) {
4467                 *num >>= 1;
4468                 *den >>= 1;
4469         }
4470 }
4471
4472 static void compute_m_n(unsigned int m, unsigned int n,
4473                         uint32_t *ret_m, uint32_t *ret_n)
4474 {
4475         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4476         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4477         intel_reduce_m_n_ratio(ret_m, ret_n);
4478 }
4479
4480 void
4481 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4482                        int pixel_clock, int link_clock,
4483                        struct intel_link_m_n *m_n)
4484 {
4485         m_n->tu = 64;
4486
4487         compute_m_n(bits_per_pixel * pixel_clock,
4488                     link_clock * nlanes * 8,
4489                     &m_n->gmch_m, &m_n->gmch_n);
4490
4491         compute_m_n(pixel_clock, link_clock,
4492                     &m_n->link_m, &m_n->link_n);
4493 }
4494
4495 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4496 {
4497         if (i915_panel_use_ssc >= 0)
4498                 return i915_panel_use_ssc != 0;
4499         return dev_priv->vbt.lvds_use_ssc
4500                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4501 }
4502
4503 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4504 {
4505         struct drm_device *dev = crtc->dev;
4506         struct drm_i915_private *dev_priv = dev->dev_private;
4507         int refclk;
4508
4509         if (IS_VALLEYVIEW(dev)) {
4510                 refclk = 100000;
4511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4512             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4513                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4514                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4515                               refclk / 1000);
4516         } else if (!IS_GEN2(dev)) {
4517                 refclk = 96000;
4518         } else {
4519                 refclk = 48000;
4520         }
4521
4522         return refclk;
4523 }
4524
4525 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4526 {
4527         return (1 << dpll->n) << 16 | dpll->m2;
4528 }
4529
4530 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4531 {
4532         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4533 }
4534
4535 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4536                                      intel_clock_t *reduced_clock)
4537 {
4538         struct drm_device *dev = crtc->base.dev;
4539         struct drm_i915_private *dev_priv = dev->dev_private;
4540         int pipe = crtc->pipe;
4541         u32 fp, fp2 = 0;
4542
4543         if (IS_PINEVIEW(dev)) {
4544                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4545                 if (reduced_clock)
4546                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4547         } else {
4548                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4549                 if (reduced_clock)
4550                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4551         }
4552
4553         I915_WRITE(FP0(pipe), fp);
4554         crtc->config.dpll_hw_state.fp0 = fp;
4555
4556         crtc->lowfreq_avail = false;
4557         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4558             reduced_clock && i915_powersave) {
4559                 I915_WRITE(FP1(pipe), fp2);
4560                 crtc->config.dpll_hw_state.fp1 = fp2;
4561                 crtc->lowfreq_avail = true;
4562         } else {
4563                 I915_WRITE(FP1(pipe), fp);
4564                 crtc->config.dpll_hw_state.fp1 = fp;
4565         }
4566 }
4567
4568 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4569                 pipe)
4570 {
4571         u32 reg_val;
4572
4573         /*
4574          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4575          * and set it to a reasonable value instead.
4576          */
4577         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4578         reg_val &= 0xffffff00;
4579         reg_val |= 0x00000030;
4580         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4581
4582         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4583         reg_val &= 0x8cffffff;
4584         reg_val = 0x8c000000;
4585         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4586
4587         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4588         reg_val &= 0xffffff00;
4589         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4590
4591         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4592         reg_val &= 0x00ffffff;
4593         reg_val |= 0xb0000000;
4594         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4595 }
4596
4597 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4598                                          struct intel_link_m_n *m_n)
4599 {
4600         struct drm_device *dev = crtc->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         int pipe = crtc->pipe;
4603
4604         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4605         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4606         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4607         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4608 }
4609
4610 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4611                                          struct intel_link_m_n *m_n)
4612 {
4613         struct drm_device *dev = crtc->base.dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615         int pipe = crtc->pipe;
4616         enum transcoder transcoder = crtc->config.cpu_transcoder;
4617
4618         if (INTEL_INFO(dev)->gen >= 5) {
4619                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4620                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4621                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4622                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4623         } else {
4624                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4625                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4626                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4627                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4628         }
4629 }
4630
4631 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4632 {
4633         if (crtc->config.has_pch_encoder)
4634                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4635         else
4636                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4637 }
4638
4639 static void vlv_update_pll(struct intel_crtc *crtc)
4640 {
4641         struct drm_device *dev = crtc->base.dev;
4642         struct drm_i915_private *dev_priv = dev->dev_private;
4643         int pipe = crtc->pipe;
4644         u32 dpll, mdiv;
4645         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4646         u32 coreclk, reg_val, dpll_md;
4647
4648         mutex_lock(&dev_priv->dpio_lock);
4649
4650         bestn = crtc->config.dpll.n;
4651         bestm1 = crtc->config.dpll.m1;
4652         bestm2 = crtc->config.dpll.m2;
4653         bestp1 = crtc->config.dpll.p1;
4654         bestp2 = crtc->config.dpll.p2;
4655
4656         /* See eDP HDMI DPIO driver vbios notes doc */
4657
4658         /* PLL B needs special handling */
4659         if (pipe)
4660                 vlv_pllb_recal_opamp(dev_priv, pipe);
4661
4662         /* Set up Tx target for periodic Rcomp update */
4663         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4664
4665         /* Disable target IRef on PLL */
4666         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4667         reg_val &= 0x00ffffff;
4668         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4669
4670         /* Disable fast lock */
4671         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4672
4673         /* Set idtafcrecal before PLL is enabled */
4674         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4675         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4676         mdiv |= ((bestn << DPIO_N_SHIFT));
4677         mdiv |= (1 << DPIO_K_SHIFT);
4678
4679         /*
4680          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4681          * but we don't support that).
4682          * Note: don't use the DAC post divider as it seems unstable.
4683          */
4684         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4685         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4686
4687         mdiv |= DPIO_ENABLE_CALIBRATION;
4688         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4689
4690         /* Set HBR and RBR LPF coefficients */
4691         if (crtc->config.port_clock == 162000 ||
4692             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4693             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4694                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4695                                  0x009f0003);
4696         else
4697                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4698                                  0x00d0000f);
4699
4700         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4701             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4702                 /* Use SSC source */
4703                 if (!pipe)
4704                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4705                                          0x0df40000);
4706                 else
4707                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4708                                          0x0df70000);
4709         } else { /* HDMI or VGA */
4710                 /* Use bend source */
4711                 if (!pipe)
4712                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4713                                          0x0df70000);
4714                 else
4715                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4716                                          0x0df40000);
4717         }
4718
4719         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4720         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4721         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4722             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4723                 coreclk |= 0x01000000;
4724         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4725
4726         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4727
4728         /* Enable DPIO clock input */
4729         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4730                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4731         /* We should never disable this, set it here for state tracking */
4732         if (pipe == PIPE_B)
4733                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4734         dpll |= DPLL_VCO_ENABLE;
4735         crtc->config.dpll_hw_state.dpll = dpll;
4736
4737         dpll_md = (crtc->config.pixel_multiplier - 1)
4738                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4739         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4740
4741         if (crtc->config.has_dp_encoder)
4742                 intel_dp_set_m_n(crtc);
4743
4744         mutex_unlock(&dev_priv->dpio_lock);
4745 }
4746
4747 static void i9xx_update_pll(struct intel_crtc *crtc,
4748                             intel_clock_t *reduced_clock,
4749                             int num_connectors)
4750 {
4751         struct drm_device *dev = crtc->base.dev;
4752         struct drm_i915_private *dev_priv = dev->dev_private;
4753         u32 dpll;
4754         bool is_sdvo;
4755         struct dpll *clock = &crtc->config.dpll;
4756
4757         i9xx_update_pll_dividers(crtc, reduced_clock);
4758
4759         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4760                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4761
4762         dpll = DPLL_VGA_MODE_DIS;
4763
4764         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4765                 dpll |= DPLLB_MODE_LVDS;
4766         else
4767                 dpll |= DPLLB_MODE_DAC_SERIAL;
4768
4769         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4770                 dpll |= (crtc->config.pixel_multiplier - 1)
4771                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4772         }
4773
4774         if (is_sdvo)
4775                 dpll |= DPLL_SDVO_HIGH_SPEED;
4776
4777         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4778                 dpll |= DPLL_SDVO_HIGH_SPEED;
4779
4780         /* compute bitmask from p1 value */
4781         if (IS_PINEVIEW(dev))
4782                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4783         else {
4784                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4785                 if (IS_G4X(dev) && reduced_clock)
4786                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4787         }
4788         switch (clock->p2) {
4789         case 5:
4790                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4791                 break;
4792         case 7:
4793                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4794                 break;
4795         case 10:
4796                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4797                 break;
4798         case 14:
4799                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4800                 break;
4801         }
4802         if (INTEL_INFO(dev)->gen >= 4)
4803                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4804
4805         if (crtc->config.sdvo_tv_clock)
4806                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4807         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4808                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4809                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4810         else
4811                 dpll |= PLL_REF_INPUT_DREFCLK;
4812
4813         dpll |= DPLL_VCO_ENABLE;
4814         crtc->config.dpll_hw_state.dpll = dpll;
4815
4816         if (INTEL_INFO(dev)->gen >= 4) {
4817                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4818                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4819                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4820         }
4821
4822         if (crtc->config.has_dp_encoder)
4823                 intel_dp_set_m_n(crtc);
4824 }
4825
4826 static void i8xx_update_pll(struct intel_crtc *crtc,
4827                             intel_clock_t *reduced_clock,
4828                             int num_connectors)
4829 {
4830         struct drm_device *dev = crtc->base.dev;
4831         struct drm_i915_private *dev_priv = dev->dev_private;
4832         u32 dpll;
4833         struct dpll *clock = &crtc->config.dpll;
4834
4835         i9xx_update_pll_dividers(crtc, reduced_clock);
4836
4837         dpll = DPLL_VGA_MODE_DIS;
4838
4839         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4840                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4841         } else {
4842                 if (clock->p1 == 2)
4843                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4844                 else
4845                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4846                 if (clock->p2 == 4)
4847                         dpll |= PLL_P2_DIVIDE_BY_4;
4848         }
4849
4850         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4851                 dpll |= DPLL_DVO_2X_MODE;
4852
4853         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4854                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4855                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4856         else
4857                 dpll |= PLL_REF_INPUT_DREFCLK;
4858
4859         dpll |= DPLL_VCO_ENABLE;
4860         crtc->config.dpll_hw_state.dpll = dpll;
4861 }
4862
4863 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4864 {
4865         struct drm_device *dev = intel_crtc->base.dev;
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         enum pipe pipe = intel_crtc->pipe;
4868         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4869         struct drm_display_mode *adjusted_mode =
4870                 &intel_crtc->config.adjusted_mode;
4871         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4872
4873         /* We need to be careful not to changed the adjusted mode, for otherwise
4874          * the hw state checker will get angry at the mismatch. */
4875         crtc_vtotal = adjusted_mode->crtc_vtotal;
4876         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4877
4878         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4879                 /* the chip adds 2 halflines automatically */
4880                 crtc_vtotal -= 1;
4881                 crtc_vblank_end -= 1;
4882                 vsyncshift = adjusted_mode->crtc_hsync_start
4883                              - adjusted_mode->crtc_htotal / 2;
4884         } else {
4885                 vsyncshift = 0;
4886         }
4887
4888         if (INTEL_INFO(dev)->gen > 3)
4889                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4890
4891         I915_WRITE(HTOTAL(cpu_transcoder),
4892                    (adjusted_mode->crtc_hdisplay - 1) |
4893                    ((adjusted_mode->crtc_htotal - 1) << 16));
4894         I915_WRITE(HBLANK(cpu_transcoder),
4895                    (adjusted_mode->crtc_hblank_start - 1) |
4896                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4897         I915_WRITE(HSYNC(cpu_transcoder),
4898                    (adjusted_mode->crtc_hsync_start - 1) |
4899                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4900
4901         I915_WRITE(VTOTAL(cpu_transcoder),
4902                    (adjusted_mode->crtc_vdisplay - 1) |
4903                    ((crtc_vtotal - 1) << 16));
4904         I915_WRITE(VBLANK(cpu_transcoder),
4905                    (adjusted_mode->crtc_vblank_start - 1) |
4906                    ((crtc_vblank_end - 1) << 16));
4907         I915_WRITE(VSYNC(cpu_transcoder),
4908                    (adjusted_mode->crtc_vsync_start - 1) |
4909                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4910
4911         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4912          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4913          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4914          * bits. */
4915         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4916             (pipe == PIPE_B || pipe == PIPE_C))
4917                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4918
4919         /* pipesrc controls the size that is scaled from, which should
4920          * always be the user's requested size.
4921          */
4922         I915_WRITE(PIPESRC(pipe),
4923                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4924                    (intel_crtc->config.pipe_src_h - 1));
4925 }
4926
4927 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4928                                    struct intel_crtc_config *pipe_config)
4929 {
4930         struct drm_device *dev = crtc->base.dev;
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4933         uint32_t tmp;
4934
4935         tmp = I915_READ(HTOTAL(cpu_transcoder));
4936         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4937         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4938         tmp = I915_READ(HBLANK(cpu_transcoder));
4939         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4940         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4941         tmp = I915_READ(HSYNC(cpu_transcoder));
4942         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4943         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4944
4945         tmp = I915_READ(VTOTAL(cpu_transcoder));
4946         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4947         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4948         tmp = I915_READ(VBLANK(cpu_transcoder));
4949         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4950         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4951         tmp = I915_READ(VSYNC(cpu_transcoder));
4952         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4953         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4954
4955         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4956                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4957                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4958                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4959         }
4960
4961         tmp = I915_READ(PIPESRC(crtc->pipe));
4962         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4963         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4964
4965         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4966         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4967 }
4968
4969 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4970                                              struct intel_crtc_config *pipe_config)
4971 {
4972         struct drm_crtc *crtc = &intel_crtc->base;
4973
4974         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4975         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4976         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4977         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4978
4979         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4980         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4981         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4982         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4983
4984         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4985
4986         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4987         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4988 }
4989
4990 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4991 {
4992         struct drm_device *dev = intel_crtc->base.dev;
4993         struct drm_i915_private *dev_priv = dev->dev_private;
4994         uint32_t pipeconf;
4995
4996         pipeconf = 0;
4997
4998         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4999             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5000                 pipeconf |= PIPECONF_ENABLE;
5001
5002         if (intel_crtc->config.double_wide)
5003                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5004
5005         /* only g4x and later have fancy bpc/dither controls */
5006         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5007                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5008                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5009                         pipeconf |= PIPECONF_DITHER_EN |
5010                                     PIPECONF_DITHER_TYPE_SP;
5011
5012                 switch (intel_crtc->config.pipe_bpp) {
5013                 case 18:
5014                         pipeconf |= PIPECONF_6BPC;
5015                         break;
5016                 case 24:
5017                         pipeconf |= PIPECONF_8BPC;
5018                         break;
5019                 case 30:
5020                         pipeconf |= PIPECONF_10BPC;
5021                         break;
5022                 default:
5023                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5024                         BUG();
5025                 }
5026         }
5027
5028         if (HAS_PIPE_CXSR(dev)) {
5029                 if (intel_crtc->lowfreq_avail) {
5030                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5031                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5032                 } else {
5033                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5034                 }
5035         }
5036
5037         if (!IS_GEN2(dev) &&
5038             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5039                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5040         else
5041                 pipeconf |= PIPECONF_PROGRESSIVE;
5042
5043         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5044                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5045
5046         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5047         POSTING_READ(PIPECONF(intel_crtc->pipe));
5048 }
5049
5050 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5051                               int x, int y,
5052                               struct drm_framebuffer *fb)
5053 {
5054         struct drm_device *dev = crtc->dev;
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5057         int pipe = intel_crtc->pipe;
5058         int plane = intel_crtc->plane;
5059         int refclk, num_connectors = 0;
5060         intel_clock_t clock, reduced_clock;
5061         u32 dspcntr;
5062         bool ok, has_reduced_clock = false;
5063         bool is_lvds = false, is_dsi = false;
5064         struct intel_encoder *encoder;
5065         const intel_limit_t *limit;
5066         int ret;
5067
5068         for_each_encoder_on_crtc(dev, crtc, encoder) {
5069                 switch (encoder->type) {
5070                 case INTEL_OUTPUT_LVDS:
5071                         is_lvds = true;
5072                         break;
5073                 case INTEL_OUTPUT_DSI:
5074                         is_dsi = true;
5075                         break;
5076                 }
5077
5078                 num_connectors++;
5079         }
5080
5081         if (is_dsi)
5082                 goto skip_dpll;
5083
5084         if (!intel_crtc->config.clock_set) {
5085                 refclk = i9xx_get_refclk(crtc, num_connectors);
5086
5087                 /*
5088                  * Returns a set of divisors for the desired target clock with
5089                  * the given refclk, or FALSE.  The returned values represent
5090                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5091                  * 2) / p1 / p2.
5092                  */
5093                 limit = intel_limit(crtc, refclk);
5094                 ok = dev_priv->display.find_dpll(limit, crtc,
5095                                                  intel_crtc->config.port_clock,
5096                                                  refclk, NULL, &clock);
5097                 if (!ok) {
5098                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5099                         return -EINVAL;
5100                 }
5101
5102                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5103                         /*
5104                          * Ensure we match the reduced clock's P to the target
5105                          * clock.  If the clocks don't match, we can't switch
5106                          * the display clock by using the FP0/FP1. In such case
5107                          * we will disable the LVDS downclock feature.
5108                          */
5109                         has_reduced_clock =
5110                                 dev_priv->display.find_dpll(limit, crtc,
5111                                                             dev_priv->lvds_downclock,
5112                                                             refclk, &clock,
5113                                                             &reduced_clock);
5114                 }
5115                 /* Compat-code for transition, will disappear. */
5116                 intel_crtc->config.dpll.n = clock.n;
5117                 intel_crtc->config.dpll.m1 = clock.m1;
5118                 intel_crtc->config.dpll.m2 = clock.m2;
5119                 intel_crtc->config.dpll.p1 = clock.p1;
5120                 intel_crtc->config.dpll.p2 = clock.p2;
5121         }
5122
5123         if (IS_GEN2(dev)) {
5124                 i8xx_update_pll(intel_crtc,
5125                                 has_reduced_clock ? &reduced_clock : NULL,
5126                                 num_connectors);
5127         } else if (IS_VALLEYVIEW(dev)) {
5128                 vlv_update_pll(intel_crtc);
5129         } else {
5130                 i9xx_update_pll(intel_crtc,
5131                                 has_reduced_clock ? &reduced_clock : NULL,
5132                                 num_connectors);
5133         }
5134
5135 skip_dpll:
5136         /* Set up the display plane register */
5137         dspcntr = DISPPLANE_GAMMA_ENABLE;
5138
5139         if (!IS_VALLEYVIEW(dev)) {
5140                 if (pipe == 0)
5141                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5142                 else
5143                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5144         }
5145
5146         intel_set_pipe_timings(intel_crtc);
5147
5148         /* pipesrc and dspsize control the size that is scaled from,
5149          * which should always be the user's requested size.
5150          */
5151         I915_WRITE(DSPSIZE(plane),
5152                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5153                    (intel_crtc->config.pipe_src_w - 1));
5154         I915_WRITE(DSPPOS(plane), 0);
5155
5156         i9xx_set_pipeconf(intel_crtc);
5157
5158         I915_WRITE(DSPCNTR(plane), dspcntr);
5159         POSTING_READ(DSPCNTR(plane));
5160
5161         ret = intel_pipe_set_base(crtc, x, y, fb);
5162
5163         return ret;
5164 }
5165
5166 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5167                                  struct intel_crtc_config *pipe_config)
5168 {
5169         struct drm_device *dev = crtc->base.dev;
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         uint32_t tmp;
5172
5173         tmp = I915_READ(PFIT_CONTROL);
5174         if (!(tmp & PFIT_ENABLE))
5175                 return;
5176
5177         /* Check whether the pfit is attached to our pipe. */
5178         if (INTEL_INFO(dev)->gen < 4) {
5179                 if (crtc->pipe != PIPE_B)
5180                         return;
5181         } else {
5182                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5183                         return;
5184         }
5185
5186         pipe_config->gmch_pfit.control = tmp;
5187         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5188         if (INTEL_INFO(dev)->gen < 5)
5189                 pipe_config->gmch_pfit.lvds_border_bits =
5190                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5191 }
5192
5193 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5194                                struct intel_crtc_config *pipe_config)
5195 {
5196         struct drm_device *dev = crtc->base.dev;
5197         struct drm_i915_private *dev_priv = dev->dev_private;
5198         int pipe = pipe_config->cpu_transcoder;
5199         intel_clock_t clock;
5200         u32 mdiv;
5201         int refclk = 100000;
5202
5203         mutex_lock(&dev_priv->dpio_lock);
5204         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5205         mutex_unlock(&dev_priv->dpio_lock);
5206
5207         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5208         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5209         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5210         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5211         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5212
5213         clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5214         clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5215
5216         pipe_config->port_clock = clock.dot / 10;
5217 }
5218
5219 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5220                                  struct intel_crtc_config *pipe_config)
5221 {
5222         struct drm_device *dev = crtc->base.dev;
5223         struct drm_i915_private *dev_priv = dev->dev_private;
5224         uint32_t tmp;
5225
5226         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5227         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5228
5229         tmp = I915_READ(PIPECONF(crtc->pipe));
5230         if (!(tmp & PIPECONF_ENABLE))
5231                 return false;
5232
5233         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5234                 switch (tmp & PIPECONF_BPC_MASK) {
5235                 case PIPECONF_6BPC:
5236                         pipe_config->pipe_bpp = 18;
5237                         break;
5238                 case PIPECONF_8BPC:
5239                         pipe_config->pipe_bpp = 24;
5240                         break;
5241                 case PIPECONF_10BPC:
5242                         pipe_config->pipe_bpp = 30;
5243                         break;
5244                 default:
5245                         break;
5246                 }
5247         }
5248
5249         if (INTEL_INFO(dev)->gen < 4)
5250                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5251
5252         intel_get_pipe_timings(crtc, pipe_config);
5253
5254         i9xx_get_pfit_config(crtc, pipe_config);
5255
5256         if (INTEL_INFO(dev)->gen >= 4) {
5257                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5258                 pipe_config->pixel_multiplier =
5259                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5260                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5261                 pipe_config->dpll_hw_state.dpll_md = tmp;
5262         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5263                 tmp = I915_READ(DPLL(crtc->pipe));
5264                 pipe_config->pixel_multiplier =
5265                         ((tmp & SDVO_MULTIPLIER_MASK)
5266                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5267         } else {
5268                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5269                  * port and will be fixed up in the encoder->get_config
5270                  * function. */
5271                 pipe_config->pixel_multiplier = 1;
5272         }
5273         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5274         if (!IS_VALLEYVIEW(dev)) {
5275                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5276                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5277         } else {
5278                 /* Mask out read-only status bits. */
5279                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5280                                                      DPLL_PORTC_READY_MASK |
5281                                                      DPLL_PORTB_READY_MASK);
5282         }
5283
5284         if (IS_VALLEYVIEW(dev))
5285                 vlv_crtc_clock_get(crtc, pipe_config);
5286         else
5287                 i9xx_crtc_clock_get(crtc, pipe_config);
5288
5289         return true;
5290 }
5291
5292 static void ironlake_init_pch_refclk(struct drm_device *dev)
5293 {
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295         struct drm_mode_config *mode_config = &dev->mode_config;
5296         struct intel_encoder *encoder;
5297         u32 val, final;
5298         bool has_lvds = false;
5299         bool has_cpu_edp = false;
5300         bool has_panel = false;
5301         bool has_ck505 = false;
5302         bool can_ssc = false;
5303
5304         /* We need to take the global config into account */
5305         list_for_each_entry(encoder, &mode_config->encoder_list,
5306                             base.head) {
5307                 switch (encoder->type) {
5308                 case INTEL_OUTPUT_LVDS:
5309                         has_panel = true;
5310                         has_lvds = true;
5311                         break;
5312                 case INTEL_OUTPUT_EDP:
5313                         has_panel = true;
5314                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5315                                 has_cpu_edp = true;
5316                         break;
5317                 }
5318         }
5319
5320         if (HAS_PCH_IBX(dev)) {
5321                 has_ck505 = dev_priv->vbt.display_clock_mode;
5322                 can_ssc = has_ck505;
5323         } else {
5324                 has_ck505 = false;
5325                 can_ssc = true;
5326         }
5327
5328         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5329                       has_panel, has_lvds, has_ck505);
5330
5331         /* Ironlake: try to setup display ref clock before DPLL
5332          * enabling. This is only under driver's control after
5333          * PCH B stepping, previous chipset stepping should be
5334          * ignoring this setting.
5335          */
5336         val = I915_READ(PCH_DREF_CONTROL);
5337
5338         /* As we must carefully and slowly disable/enable each source in turn,
5339          * compute the final state we want first and check if we need to
5340          * make any changes at all.
5341          */
5342         final = val;
5343         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5344         if (has_ck505)
5345                 final |= DREF_NONSPREAD_CK505_ENABLE;
5346         else
5347                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5348
5349         final &= ~DREF_SSC_SOURCE_MASK;
5350         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5351         final &= ~DREF_SSC1_ENABLE;
5352
5353         if (has_panel) {
5354                 final |= DREF_SSC_SOURCE_ENABLE;
5355
5356                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5357                         final |= DREF_SSC1_ENABLE;
5358
5359                 if (has_cpu_edp) {
5360                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5361                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5362                         else
5363                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5364                 } else
5365                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5366         } else {
5367                 final |= DREF_SSC_SOURCE_DISABLE;
5368                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5369         }
5370
5371         if (final == val)
5372                 return;
5373
5374         /* Always enable nonspread source */
5375         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5376
5377         if (has_ck505)
5378                 val |= DREF_NONSPREAD_CK505_ENABLE;
5379         else
5380                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5381
5382         if (has_panel) {
5383                 val &= ~DREF_SSC_SOURCE_MASK;
5384                 val |= DREF_SSC_SOURCE_ENABLE;
5385
5386                 /* SSC must be turned on before enabling the CPU output  */
5387                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5388                         DRM_DEBUG_KMS("Using SSC on panel\n");
5389                         val |= DREF_SSC1_ENABLE;
5390                 } else
5391                         val &= ~DREF_SSC1_ENABLE;
5392
5393                 /* Get SSC going before enabling the outputs */
5394                 I915_WRITE(PCH_DREF_CONTROL, val);
5395                 POSTING_READ(PCH_DREF_CONTROL);
5396                 udelay(200);
5397
5398                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5399
5400                 /* Enable CPU source on CPU attached eDP */
5401                 if (has_cpu_edp) {
5402                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5403                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5404                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5405                         }
5406                         else
5407                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5408                 } else
5409                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5410
5411                 I915_WRITE(PCH_DREF_CONTROL, val);
5412                 POSTING_READ(PCH_DREF_CONTROL);
5413                 udelay(200);
5414         } else {
5415                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5416
5417                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5418
5419                 /* Turn off CPU output */
5420                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5421
5422                 I915_WRITE(PCH_DREF_CONTROL, val);
5423                 POSTING_READ(PCH_DREF_CONTROL);
5424                 udelay(200);
5425
5426                 /* Turn off the SSC source */
5427                 val &= ~DREF_SSC_SOURCE_MASK;
5428                 val |= DREF_SSC_SOURCE_DISABLE;
5429
5430                 /* Turn off SSC1 */
5431                 val &= ~DREF_SSC1_ENABLE;
5432
5433                 I915_WRITE(PCH_DREF_CONTROL, val);
5434                 POSTING_READ(PCH_DREF_CONTROL);
5435                 udelay(200);
5436         }
5437
5438         BUG_ON(val != final);
5439 }
5440
5441 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5442 {
5443         uint32_t tmp;
5444
5445         tmp = I915_READ(SOUTH_CHICKEN2);
5446         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5447         I915_WRITE(SOUTH_CHICKEN2, tmp);
5448
5449         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5450                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5451                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5452
5453         tmp = I915_READ(SOUTH_CHICKEN2);
5454         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5455         I915_WRITE(SOUTH_CHICKEN2, tmp);
5456
5457         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5458                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5459                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5460 }
5461
5462 /* WaMPhyProgramming:hsw */
5463 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5464 {
5465         uint32_t tmp;
5466
5467         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5468         tmp &= ~(0xFF << 24);
5469         tmp |= (0x12 << 24);
5470         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5471
5472         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5473         tmp |= (1 << 11);
5474         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5475
5476         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5477         tmp |= (1 << 11);
5478         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5479
5480         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5481         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5482         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5483
5484         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5485         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5486         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5487
5488         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5489         tmp &= ~(7 << 13);
5490         tmp |= (5 << 13);
5491         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5492
5493         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5494         tmp &= ~(7 << 13);
5495         tmp |= (5 << 13);
5496         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5497
5498         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5499         tmp &= ~0xFF;
5500         tmp |= 0x1C;
5501         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5502
5503         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5504         tmp &= ~0xFF;
5505         tmp |= 0x1C;
5506         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5507
5508         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5509         tmp &= ~(0xFF << 16);
5510         tmp |= (0x1C << 16);
5511         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5512
5513         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5514         tmp &= ~(0xFF << 16);
5515         tmp |= (0x1C << 16);
5516         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5517
5518         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5519         tmp |= (1 << 27);
5520         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5521
5522         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5523         tmp |= (1 << 27);
5524         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5525
5526         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5527         tmp &= ~(0xF << 28);
5528         tmp |= (4 << 28);
5529         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5530
5531         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5532         tmp &= ~(0xF << 28);
5533         tmp |= (4 << 28);
5534         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5535 }
5536
5537 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5538  * Programming" based on the parameters passed:
5539  * - Sequence to enable CLKOUT_DP
5540  * - Sequence to enable CLKOUT_DP without spread
5541  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5542  */
5543 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5544                                  bool with_fdi)
5545 {
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547         uint32_t reg, tmp;
5548
5549         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5550                 with_spread = true;
5551         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5552                  with_fdi, "LP PCH doesn't have FDI\n"))
5553                 with_fdi = false;
5554
5555         mutex_lock(&dev_priv->dpio_lock);
5556
5557         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5558         tmp &= ~SBI_SSCCTL_DISABLE;
5559         tmp |= SBI_SSCCTL_PATHALT;
5560         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5561
5562         udelay(24);
5563
5564         if (with_spread) {
5565                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5566                 tmp &= ~SBI_SSCCTL_PATHALT;
5567                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5568
5569                 if (with_fdi) {
5570                         lpt_reset_fdi_mphy(dev_priv);
5571                         lpt_program_fdi_mphy(dev_priv);
5572                 }
5573         }
5574
5575         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5576                SBI_GEN0 : SBI_DBUFF0;
5577         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5578         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5579         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5580
5581         mutex_unlock(&dev_priv->dpio_lock);
5582 }
5583
5584 /* Sequence to disable CLKOUT_DP */
5585 static void lpt_disable_clkout_dp(struct drm_device *dev)
5586 {
5587         struct drm_i915_private *dev_priv = dev->dev_private;
5588         uint32_t reg, tmp;
5589
5590         mutex_lock(&dev_priv->dpio_lock);
5591
5592         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5593                SBI_GEN0 : SBI_DBUFF0;
5594         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5595         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5596         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5597
5598         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5599         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5600                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5601                         tmp |= SBI_SSCCTL_PATHALT;
5602                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5603                         udelay(32);
5604                 }
5605                 tmp |= SBI_SSCCTL_DISABLE;
5606                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5607         }
5608
5609         mutex_unlock(&dev_priv->dpio_lock);
5610 }
5611
5612 static void lpt_init_pch_refclk(struct drm_device *dev)
5613 {
5614         struct drm_mode_config *mode_config = &dev->mode_config;
5615         struct intel_encoder *encoder;
5616         bool has_vga = false;
5617
5618         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5619                 switch (encoder->type) {
5620                 case INTEL_OUTPUT_ANALOG:
5621                         has_vga = true;
5622                         break;
5623                 }
5624         }
5625
5626         if (has_vga)
5627                 lpt_enable_clkout_dp(dev, true, true);
5628         else
5629                 lpt_disable_clkout_dp(dev);
5630 }
5631
5632 /*
5633  * Initialize reference clocks when the driver loads
5634  */
5635 void intel_init_pch_refclk(struct drm_device *dev)
5636 {
5637         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5638                 ironlake_init_pch_refclk(dev);
5639         else if (HAS_PCH_LPT(dev))
5640                 lpt_init_pch_refclk(dev);
5641 }
5642
5643 static int ironlake_get_refclk(struct drm_crtc *crtc)
5644 {
5645         struct drm_device *dev = crtc->dev;
5646         struct drm_i915_private *dev_priv = dev->dev_private;
5647         struct intel_encoder *encoder;
5648         int num_connectors = 0;
5649         bool is_lvds = false;
5650
5651         for_each_encoder_on_crtc(dev, crtc, encoder) {
5652                 switch (encoder->type) {
5653                 case INTEL_OUTPUT_LVDS:
5654                         is_lvds = true;
5655                         break;
5656                 }
5657                 num_connectors++;
5658         }
5659
5660         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5661                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5662                               dev_priv->vbt.lvds_ssc_freq);
5663                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5664         }
5665
5666         return 120000;
5667 }
5668
5669 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5670 {
5671         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673         int pipe = intel_crtc->pipe;
5674         uint32_t val;
5675
5676         val = 0;
5677
5678         switch (intel_crtc->config.pipe_bpp) {
5679         case 18:
5680                 val |= PIPECONF_6BPC;
5681                 break;
5682         case 24:
5683                 val |= PIPECONF_8BPC;
5684                 break;
5685         case 30:
5686                 val |= PIPECONF_10BPC;
5687                 break;
5688         case 36:
5689                 val |= PIPECONF_12BPC;
5690                 break;
5691         default:
5692                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5693                 BUG();
5694         }
5695
5696         if (intel_crtc->config.dither)
5697                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5698
5699         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5700                 val |= PIPECONF_INTERLACED_ILK;
5701         else
5702                 val |= PIPECONF_PROGRESSIVE;
5703
5704         if (intel_crtc->config.limited_color_range)
5705                 val |= PIPECONF_COLOR_RANGE_SELECT;
5706
5707         I915_WRITE(PIPECONF(pipe), val);
5708         POSTING_READ(PIPECONF(pipe));
5709 }
5710
5711 /*
5712  * Set up the pipe CSC unit.
5713  *
5714  * Currently only full range RGB to limited range RGB conversion
5715  * is supported, but eventually this should handle various
5716  * RGB<->YCbCr scenarios as well.
5717  */
5718 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5719 {
5720         struct drm_device *dev = crtc->dev;
5721         struct drm_i915_private *dev_priv = dev->dev_private;
5722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5723         int pipe = intel_crtc->pipe;
5724         uint16_t coeff = 0x7800; /* 1.0 */
5725
5726         /*
5727          * TODO: Check what kind of values actually come out of the pipe
5728          * with these coeff/postoff values and adjust to get the best
5729          * accuracy. Perhaps we even need to take the bpc value into
5730          * consideration.
5731          */
5732
5733         if (intel_crtc->config.limited_color_range)
5734                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5735
5736         /*
5737          * GY/GU and RY/RU should be the other way around according
5738          * to BSpec, but reality doesn't agree. Just set them up in
5739          * a way that results in the correct picture.
5740          */
5741         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5742         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5743
5744         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5745         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5746
5747         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5748         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5749
5750         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5751         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5752         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5753
5754         if (INTEL_INFO(dev)->gen > 6) {
5755                 uint16_t postoff = 0;
5756
5757                 if (intel_crtc->config.limited_color_range)
5758                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5759
5760                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5761                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5762                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5763
5764                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5765         } else {
5766                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5767
5768                 if (intel_crtc->config.limited_color_range)
5769                         mode |= CSC_BLACK_SCREEN_OFFSET;
5770
5771                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5772         }
5773 }
5774
5775 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5776 {
5777         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5779         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5780         uint32_t val;
5781
5782         val = 0;
5783
5784         if (intel_crtc->config.dither)
5785                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5786
5787         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5788                 val |= PIPECONF_INTERLACED_ILK;
5789         else
5790                 val |= PIPECONF_PROGRESSIVE;
5791
5792         I915_WRITE(PIPECONF(cpu_transcoder), val);
5793         POSTING_READ(PIPECONF(cpu_transcoder));
5794
5795         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5796         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5797 }
5798
5799 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5800                                     intel_clock_t *clock,
5801                                     bool *has_reduced_clock,
5802                                     intel_clock_t *reduced_clock)
5803 {
5804         struct drm_device *dev = crtc->dev;
5805         struct drm_i915_private *dev_priv = dev->dev_private;
5806         struct intel_encoder *intel_encoder;
5807         int refclk;
5808         const intel_limit_t *limit;
5809         bool ret, is_lvds = false;
5810
5811         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5812                 switch (intel_encoder->type) {
5813                 case INTEL_OUTPUT_LVDS:
5814                         is_lvds = true;
5815                         break;
5816                 }
5817         }
5818
5819         refclk = ironlake_get_refclk(crtc);
5820
5821         /*
5822          * Returns a set of divisors for the desired target clock with the given
5823          * refclk, or FALSE.  The returned values represent the clock equation:
5824          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5825          */
5826         limit = intel_limit(crtc, refclk);
5827         ret = dev_priv->display.find_dpll(limit, crtc,
5828                                           to_intel_crtc(crtc)->config.port_clock,
5829                                           refclk, NULL, clock);
5830         if (!ret)
5831                 return false;
5832
5833         if (is_lvds && dev_priv->lvds_downclock_avail) {
5834                 /*
5835                  * Ensure we match the reduced clock's P to the target clock.
5836                  * If the clocks don't match, we can't switch the display clock
5837                  * by using the FP0/FP1. In such case we will disable the LVDS
5838                  * downclock feature.
5839                 */
5840                 *has_reduced_clock =
5841                         dev_priv->display.find_dpll(limit, crtc,
5842                                                     dev_priv->lvds_downclock,
5843                                                     refclk, clock,
5844                                                     reduced_clock);
5845         }
5846
5847         return true;
5848 }
5849
5850 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5851 {
5852         struct drm_i915_private *dev_priv = dev->dev_private;
5853         uint32_t temp;
5854
5855         temp = I915_READ(SOUTH_CHICKEN1);
5856         if (temp & FDI_BC_BIFURCATION_SELECT)
5857                 return;
5858
5859         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5860         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5861
5862         temp |= FDI_BC_BIFURCATION_SELECT;
5863         DRM_DEBUG_KMS("enabling fdi C rx\n");
5864         I915_WRITE(SOUTH_CHICKEN1, temp);
5865         POSTING_READ(SOUTH_CHICKEN1);
5866 }
5867
5868 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5869 {
5870         struct drm_device *dev = intel_crtc->base.dev;
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872
5873         switch (intel_crtc->pipe) {
5874         case PIPE_A:
5875                 break;
5876         case PIPE_B:
5877                 if (intel_crtc->config.fdi_lanes > 2)
5878                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5879                 else
5880                         cpt_enable_fdi_bc_bifurcation(dev);
5881
5882                 break;
5883         case PIPE_C:
5884                 cpt_enable_fdi_bc_bifurcation(dev);
5885
5886                 break;
5887         default:
5888                 BUG();
5889         }
5890 }
5891
5892 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5893 {
5894         /*
5895          * Account for spread spectrum to avoid
5896          * oversubscribing the link. Max center spread
5897          * is 2.5%; use 5% for safety's sake.
5898          */
5899         u32 bps = target_clock * bpp * 21 / 20;
5900         return bps / (link_bw * 8) + 1;
5901 }
5902
5903 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5904 {
5905         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5906 }
5907
5908 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5909                                       u32 *fp,
5910                                       intel_clock_t *reduced_clock, u32 *fp2)
5911 {
5912         struct drm_crtc *crtc = &intel_crtc->base;
5913         struct drm_device *dev = crtc->dev;
5914         struct drm_i915_private *dev_priv = dev->dev_private;
5915         struct intel_encoder *intel_encoder;
5916         uint32_t dpll;
5917         int factor, num_connectors = 0;
5918         bool is_lvds = false, is_sdvo = false;
5919
5920         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5921                 switch (intel_encoder->type) {
5922                 case INTEL_OUTPUT_LVDS:
5923                         is_lvds = true;
5924                         break;
5925                 case INTEL_OUTPUT_SDVO:
5926                 case INTEL_OUTPUT_HDMI:
5927                         is_sdvo = true;
5928                         break;
5929                 }
5930
5931                 num_connectors++;
5932         }
5933
5934         /* Enable autotuning of the PLL clock (if permissible) */
5935         factor = 21;
5936         if (is_lvds) {
5937                 if ((intel_panel_use_ssc(dev_priv) &&
5938                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5939                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5940                         factor = 25;
5941         } else if (intel_crtc->config.sdvo_tv_clock)
5942                 factor = 20;
5943
5944         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5945                 *fp |= FP_CB_TUNE;
5946
5947         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5948                 *fp2 |= FP_CB_TUNE;
5949
5950         dpll = 0;
5951
5952         if (is_lvds)
5953                 dpll |= DPLLB_MODE_LVDS;
5954         else
5955                 dpll |= DPLLB_MODE_DAC_SERIAL;
5956
5957         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5958                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5959
5960         if (is_sdvo)
5961                 dpll |= DPLL_SDVO_HIGH_SPEED;
5962         if (intel_crtc->config.has_dp_encoder)
5963                 dpll |= DPLL_SDVO_HIGH_SPEED;
5964
5965         /* compute bitmask from p1 value */
5966         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5967         /* also FPA1 */
5968         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5969
5970         switch (intel_crtc->config.dpll.p2) {
5971         case 5:
5972                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5973                 break;
5974         case 7:
5975                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5976                 break;
5977         case 10:
5978                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5979                 break;
5980         case 14:
5981                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5982                 break;
5983         }
5984
5985         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5986                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5987         else
5988                 dpll |= PLL_REF_INPUT_DREFCLK;
5989
5990         return dpll | DPLL_VCO_ENABLE;
5991 }
5992
5993 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5994                                   int x, int y,
5995                                   struct drm_framebuffer *fb)
5996 {
5997         struct drm_device *dev = crtc->dev;
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000         int pipe = intel_crtc->pipe;
6001         int plane = intel_crtc->plane;
6002         int num_connectors = 0;
6003         intel_clock_t clock, reduced_clock;
6004         u32 dpll = 0, fp = 0, fp2 = 0;
6005         bool ok, has_reduced_clock = false;
6006         bool is_lvds = false;
6007         struct intel_encoder *encoder;
6008         struct intel_shared_dpll *pll;
6009         int ret;
6010
6011         for_each_encoder_on_crtc(dev, crtc, encoder) {
6012                 switch (encoder->type) {
6013                 case INTEL_OUTPUT_LVDS:
6014                         is_lvds = true;
6015                         break;
6016                 }
6017
6018                 num_connectors++;
6019         }
6020
6021         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6022              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6023
6024         ok = ironlake_compute_clocks(crtc, &clock,
6025                                      &has_reduced_clock, &reduced_clock);
6026         if (!ok && !intel_crtc->config.clock_set) {
6027                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6028                 return -EINVAL;
6029         }
6030         /* Compat-code for transition, will disappear. */
6031         if (!intel_crtc->config.clock_set) {
6032                 intel_crtc->config.dpll.n = clock.n;
6033                 intel_crtc->config.dpll.m1 = clock.m1;
6034                 intel_crtc->config.dpll.m2 = clock.m2;
6035                 intel_crtc->config.dpll.p1 = clock.p1;
6036                 intel_crtc->config.dpll.p2 = clock.p2;
6037         }
6038
6039         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6040         if (intel_crtc->config.has_pch_encoder) {
6041                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6042                 if (has_reduced_clock)
6043                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6044
6045                 dpll = ironlake_compute_dpll(intel_crtc,
6046                                              &fp, &reduced_clock,
6047                                              has_reduced_clock ? &fp2 : NULL);
6048
6049                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6050                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6051                 if (has_reduced_clock)
6052                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6053                 else
6054                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6055
6056                 pll = intel_get_shared_dpll(intel_crtc);
6057                 if (pll == NULL) {
6058                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6059                                          pipe_name(pipe));
6060                         return -EINVAL;
6061                 }
6062         } else
6063                 intel_put_shared_dpll(intel_crtc);
6064
6065         if (intel_crtc->config.has_dp_encoder)
6066                 intel_dp_set_m_n(intel_crtc);
6067
6068         if (is_lvds && has_reduced_clock && i915_powersave)
6069                 intel_crtc->lowfreq_avail = true;
6070         else
6071                 intel_crtc->lowfreq_avail = false;
6072
6073         if (intel_crtc->config.has_pch_encoder) {
6074                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6075
6076         }
6077
6078         intel_set_pipe_timings(intel_crtc);
6079
6080         if (intel_crtc->config.has_pch_encoder) {
6081                 intel_cpu_transcoder_set_m_n(intel_crtc,
6082                                              &intel_crtc->config.fdi_m_n);
6083         }
6084
6085         if (IS_IVYBRIDGE(dev))
6086                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6087
6088         ironlake_set_pipeconf(crtc);
6089
6090         /* Set up the display plane register */
6091         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6092         POSTING_READ(DSPCNTR(plane));
6093
6094         ret = intel_pipe_set_base(crtc, x, y, fb);
6095
6096         return ret;
6097 }
6098
6099 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6100                                          struct intel_link_m_n *m_n)
6101 {
6102         struct drm_device *dev = crtc->base.dev;
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         enum pipe pipe = crtc->pipe;
6105
6106         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6107         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6108         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6109                 & ~TU_SIZE_MASK;
6110         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6111         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6112                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6113 }
6114
6115 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6116                                          enum transcoder transcoder,
6117                                          struct intel_link_m_n *m_n)
6118 {
6119         struct drm_device *dev = crtc->base.dev;
6120         struct drm_i915_private *dev_priv = dev->dev_private;
6121         enum pipe pipe = crtc->pipe;
6122
6123         if (INTEL_INFO(dev)->gen >= 5) {
6124                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6125                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6126                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6127                         & ~TU_SIZE_MASK;
6128                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6129                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6130                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6131         } else {
6132                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6133                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6134                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6135                         & ~TU_SIZE_MASK;
6136                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6137                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6138                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6139         }
6140 }
6141
6142 void intel_dp_get_m_n(struct intel_crtc *crtc,
6143                       struct intel_crtc_config *pipe_config)
6144 {
6145         if (crtc->config.has_pch_encoder)
6146                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6147         else
6148                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6149                                              &pipe_config->dp_m_n);
6150 }
6151
6152 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6153                                         struct intel_crtc_config *pipe_config)
6154 {
6155         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6156                                      &pipe_config->fdi_m_n);
6157 }
6158
6159 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6160                                      struct intel_crtc_config *pipe_config)
6161 {
6162         struct drm_device *dev = crtc->base.dev;
6163         struct drm_i915_private *dev_priv = dev->dev_private;
6164         uint32_t tmp;
6165
6166         tmp = I915_READ(PF_CTL(crtc->pipe));
6167
6168         if (tmp & PF_ENABLE) {
6169                 pipe_config->pch_pfit.enabled = true;
6170                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6171                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6172
6173                 /* We currently do not free assignements of panel fitters on
6174                  * ivb/hsw (since we don't use the higher upscaling modes which
6175                  * differentiates them) so just WARN about this case for now. */
6176                 if (IS_GEN7(dev)) {
6177                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6178                                 PF_PIPE_SEL_IVB(crtc->pipe));
6179                 }
6180         }
6181 }
6182
6183 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6184                                      struct intel_crtc_config *pipe_config)
6185 {
6186         struct drm_device *dev = crtc->base.dev;
6187         struct drm_i915_private *dev_priv = dev->dev_private;
6188         uint32_t tmp;
6189
6190         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6191         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6192
6193         tmp = I915_READ(PIPECONF(crtc->pipe));
6194         if (!(tmp & PIPECONF_ENABLE))
6195                 return false;
6196
6197         switch (tmp & PIPECONF_BPC_MASK) {
6198         case PIPECONF_6BPC:
6199                 pipe_config->pipe_bpp = 18;
6200                 break;
6201         case PIPECONF_8BPC:
6202                 pipe_config->pipe_bpp = 24;
6203                 break;
6204         case PIPECONF_10BPC:
6205                 pipe_config->pipe_bpp = 30;
6206                 break;
6207         case PIPECONF_12BPC:
6208                 pipe_config->pipe_bpp = 36;
6209                 break;
6210         default:
6211                 break;
6212         }
6213
6214         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6215                 struct intel_shared_dpll *pll;
6216
6217                 pipe_config->has_pch_encoder = true;
6218
6219                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6220                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6221                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6222
6223                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6224
6225                 if (HAS_PCH_IBX(dev_priv->dev)) {
6226                         pipe_config->shared_dpll =
6227                                 (enum intel_dpll_id) crtc->pipe;
6228                 } else {
6229                         tmp = I915_READ(PCH_DPLL_SEL);
6230                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6231                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6232                         else
6233                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6234                 }
6235
6236                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6237
6238                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6239                                            &pipe_config->dpll_hw_state));
6240
6241                 tmp = pipe_config->dpll_hw_state.dpll;
6242                 pipe_config->pixel_multiplier =
6243                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6244                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6245
6246                 ironlake_pch_clock_get(crtc, pipe_config);
6247         } else {
6248                 pipe_config->pixel_multiplier = 1;
6249         }
6250
6251         intel_get_pipe_timings(crtc, pipe_config);
6252
6253         ironlake_get_pfit_config(crtc, pipe_config);
6254
6255         return true;
6256 }
6257
6258 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6259 {
6260         struct drm_device *dev = dev_priv->dev;
6261         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6262         struct intel_crtc *crtc;
6263         unsigned long irqflags;
6264         uint32_t val;
6265
6266         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6267                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6268                      pipe_name(crtc->pipe));
6269
6270         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6271         WARN(plls->spll_refcount, "SPLL enabled\n");
6272         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6273         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6274         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6275         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6276              "CPU PWM1 enabled\n");
6277         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6278              "CPU PWM2 enabled\n");
6279         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6280              "PCH PWM1 enabled\n");
6281         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6282              "Utility pin enabled\n");
6283         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6284
6285         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6286         val = I915_READ(DEIMR);
6287         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6288              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6289         val = I915_READ(SDEIMR);
6290         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6291              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6292         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6293 }
6294
6295 /*
6296  * This function implements pieces of two sequences from BSpec:
6297  * - Sequence for display software to disable LCPLL
6298  * - Sequence for display software to allow package C8+
6299  * The steps implemented here are just the steps that actually touch the LCPLL
6300  * register. Callers should take care of disabling all the display engine
6301  * functions, doing the mode unset, fixing interrupts, etc.
6302  */
6303 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6304                               bool switch_to_fclk, bool allow_power_down)
6305 {
6306         uint32_t val;
6307
6308         assert_can_disable_lcpll(dev_priv);
6309
6310         val = I915_READ(LCPLL_CTL);
6311
6312         if (switch_to_fclk) {
6313                 val |= LCPLL_CD_SOURCE_FCLK;
6314                 I915_WRITE(LCPLL_CTL, val);
6315
6316                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6317                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6318                         DRM_ERROR("Switching to FCLK failed\n");
6319
6320                 val = I915_READ(LCPLL_CTL);
6321         }
6322
6323         val |= LCPLL_PLL_DISABLE;
6324         I915_WRITE(LCPLL_CTL, val);
6325         POSTING_READ(LCPLL_CTL);
6326
6327         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6328                 DRM_ERROR("LCPLL still locked\n");
6329
6330         val = I915_READ(D_COMP);
6331         val |= D_COMP_COMP_DISABLE;
6332         mutex_lock(&dev_priv->rps.hw_lock);
6333         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6334                 DRM_ERROR("Failed to disable D_COMP\n");
6335         mutex_unlock(&dev_priv->rps.hw_lock);
6336         POSTING_READ(D_COMP);
6337         ndelay(100);
6338
6339         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6340                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6341
6342         if (allow_power_down) {
6343                 val = I915_READ(LCPLL_CTL);
6344                 val |= LCPLL_POWER_DOWN_ALLOW;
6345                 I915_WRITE(LCPLL_CTL, val);
6346                 POSTING_READ(LCPLL_CTL);
6347         }
6348 }
6349
6350 /*
6351  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6352  * source.
6353  */
6354 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6355 {
6356         uint32_t val;
6357
6358         val = I915_READ(LCPLL_CTL);
6359
6360         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6361                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6362                 return;
6363
6364         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6365          * we'll hang the machine! */
6366         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6367
6368         if (val & LCPLL_POWER_DOWN_ALLOW) {
6369                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6370                 I915_WRITE(LCPLL_CTL, val);
6371                 POSTING_READ(LCPLL_CTL);
6372         }
6373
6374         val = I915_READ(D_COMP);
6375         val |= D_COMP_COMP_FORCE;
6376         val &= ~D_COMP_COMP_DISABLE;
6377         mutex_lock(&dev_priv->rps.hw_lock);
6378         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6379                 DRM_ERROR("Failed to enable D_COMP\n");
6380         mutex_unlock(&dev_priv->rps.hw_lock);
6381         POSTING_READ(D_COMP);
6382
6383         val = I915_READ(LCPLL_CTL);
6384         val &= ~LCPLL_PLL_DISABLE;
6385         I915_WRITE(LCPLL_CTL, val);
6386
6387         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6388                 DRM_ERROR("LCPLL not locked yet\n");
6389
6390         if (val & LCPLL_CD_SOURCE_FCLK) {
6391                 val = I915_READ(LCPLL_CTL);
6392                 val &= ~LCPLL_CD_SOURCE_FCLK;
6393                 I915_WRITE(LCPLL_CTL, val);
6394
6395                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6396                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6397                         DRM_ERROR("Switching back to LCPLL failed\n");
6398         }
6399
6400         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6401 }
6402
6403 void hsw_enable_pc8_work(struct work_struct *__work)
6404 {
6405         struct drm_i915_private *dev_priv =
6406                 container_of(to_delayed_work(__work), struct drm_i915_private,
6407                              pc8.enable_work);
6408         struct drm_device *dev = dev_priv->dev;
6409         uint32_t val;
6410
6411         if (dev_priv->pc8.enabled)
6412                 return;
6413
6414         DRM_DEBUG_KMS("Enabling package C8+\n");
6415
6416         dev_priv->pc8.enabled = true;
6417
6418         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6419                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6420                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6421                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6422         }
6423
6424         lpt_disable_clkout_dp(dev);
6425         hsw_pc8_disable_interrupts(dev);
6426         hsw_disable_lcpll(dev_priv, true, true);
6427 }
6428
6429 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6430 {
6431         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6432         WARN(dev_priv->pc8.disable_count < 1,
6433              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6434
6435         dev_priv->pc8.disable_count--;
6436         if (dev_priv->pc8.disable_count != 0)
6437                 return;
6438
6439         schedule_delayed_work(&dev_priv->pc8.enable_work,
6440                               msecs_to_jiffies(i915_pc8_timeout));
6441 }
6442
6443 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6444 {
6445         struct drm_device *dev = dev_priv->dev;
6446         uint32_t val;
6447
6448         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6449         WARN(dev_priv->pc8.disable_count < 0,
6450              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6451
6452         dev_priv->pc8.disable_count++;
6453         if (dev_priv->pc8.disable_count != 1)
6454                 return;
6455
6456         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6457         if (!dev_priv->pc8.enabled)
6458                 return;
6459
6460         DRM_DEBUG_KMS("Disabling package C8+\n");
6461
6462         hsw_restore_lcpll(dev_priv);
6463         hsw_pc8_restore_interrupts(dev);
6464         lpt_init_pch_refclk(dev);
6465
6466         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6467                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6468                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6469                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6470         }
6471
6472         intel_prepare_ddi(dev);
6473         i915_gem_init_swizzling(dev);
6474         mutex_lock(&dev_priv->rps.hw_lock);
6475         gen6_update_ring_freq(dev);
6476         mutex_unlock(&dev_priv->rps.hw_lock);
6477         dev_priv->pc8.enabled = false;
6478 }
6479
6480 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6481 {
6482         mutex_lock(&dev_priv->pc8.lock);
6483         __hsw_enable_package_c8(dev_priv);
6484         mutex_unlock(&dev_priv->pc8.lock);
6485 }
6486
6487 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6488 {
6489         mutex_lock(&dev_priv->pc8.lock);
6490         __hsw_disable_package_c8(dev_priv);
6491         mutex_unlock(&dev_priv->pc8.lock);
6492 }
6493
6494 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6495 {
6496         struct drm_device *dev = dev_priv->dev;
6497         struct intel_crtc *crtc;
6498         uint32_t val;
6499
6500         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6501                 if (crtc->base.enabled)
6502                         return false;
6503
6504         /* This case is still possible since we have the i915.disable_power_well
6505          * parameter and also the KVMr or something else might be requesting the
6506          * power well. */
6507         val = I915_READ(HSW_PWR_WELL_DRIVER);
6508         if (val != 0) {
6509                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6510                 return false;
6511         }
6512
6513         return true;
6514 }
6515
6516 /* Since we're called from modeset_global_resources there's no way to
6517  * symmetrically increase and decrease the refcount, so we use
6518  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6519  * or not.
6520  */
6521 static void hsw_update_package_c8(struct drm_device *dev)
6522 {
6523         struct drm_i915_private *dev_priv = dev->dev_private;
6524         bool allow;
6525
6526         if (!i915_enable_pc8)
6527                 return;
6528
6529         mutex_lock(&dev_priv->pc8.lock);
6530
6531         allow = hsw_can_enable_package_c8(dev_priv);
6532
6533         if (allow == dev_priv->pc8.requirements_met)
6534                 goto done;
6535
6536         dev_priv->pc8.requirements_met = allow;
6537
6538         if (allow)
6539                 __hsw_enable_package_c8(dev_priv);
6540         else
6541                 __hsw_disable_package_c8(dev_priv);
6542
6543 done:
6544         mutex_unlock(&dev_priv->pc8.lock);
6545 }
6546
6547 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6548 {
6549         if (!dev_priv->pc8.gpu_idle) {
6550                 dev_priv->pc8.gpu_idle = true;
6551                 hsw_enable_package_c8(dev_priv);
6552         }
6553 }
6554
6555 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6556 {
6557         if (dev_priv->pc8.gpu_idle) {
6558                 dev_priv->pc8.gpu_idle = false;
6559                 hsw_disable_package_c8(dev_priv);
6560         }
6561 }
6562
6563 static void haswell_modeset_global_resources(struct drm_device *dev)
6564 {
6565         bool enable = false;
6566         struct intel_crtc *crtc;
6567
6568         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6569                 if (!crtc->base.enabled)
6570                         continue;
6571
6572                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6573                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6574                         enable = true;
6575         }
6576
6577         intel_set_power_well(dev, enable);
6578
6579         hsw_update_package_c8(dev);
6580 }
6581
6582 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6583                                  int x, int y,
6584                                  struct drm_framebuffer *fb)
6585 {
6586         struct drm_device *dev = crtc->dev;
6587         struct drm_i915_private *dev_priv = dev->dev_private;
6588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6589         int plane = intel_crtc->plane;
6590         int ret;
6591
6592         if (!intel_ddi_pll_mode_set(crtc))
6593                 return -EINVAL;
6594
6595         if (intel_crtc->config.has_dp_encoder)
6596                 intel_dp_set_m_n(intel_crtc);
6597
6598         intel_crtc->lowfreq_avail = false;
6599
6600         intel_set_pipe_timings(intel_crtc);
6601
6602         if (intel_crtc->config.has_pch_encoder) {
6603                 intel_cpu_transcoder_set_m_n(intel_crtc,
6604                                              &intel_crtc->config.fdi_m_n);
6605         }
6606
6607         haswell_set_pipeconf(crtc);
6608
6609         intel_set_pipe_csc(crtc);
6610
6611         /* Set up the display plane register */
6612         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6613         POSTING_READ(DSPCNTR(plane));
6614
6615         ret = intel_pipe_set_base(crtc, x, y, fb);
6616
6617         return ret;
6618 }
6619
6620 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6621                                     struct intel_crtc_config *pipe_config)
6622 {
6623         struct drm_device *dev = crtc->base.dev;
6624         struct drm_i915_private *dev_priv = dev->dev_private;
6625         enum intel_display_power_domain pfit_domain;
6626         uint32_t tmp;
6627
6628         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6629         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6630
6631         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6632         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6633                 enum pipe trans_edp_pipe;
6634                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6635                 default:
6636                         WARN(1, "unknown pipe linked to edp transcoder\n");
6637                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6638                 case TRANS_DDI_EDP_INPUT_A_ON:
6639                         trans_edp_pipe = PIPE_A;
6640                         break;
6641                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6642                         trans_edp_pipe = PIPE_B;
6643                         break;
6644                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6645                         trans_edp_pipe = PIPE_C;
6646                         break;
6647                 }
6648
6649                 if (trans_edp_pipe == crtc->pipe)
6650                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6651         }
6652
6653         if (!intel_display_power_enabled(dev,
6654                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6655                 return false;
6656
6657         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6658         if (!(tmp & PIPECONF_ENABLE))
6659                 return false;
6660
6661         /*
6662          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6663          * DDI E. So just check whether this pipe is wired to DDI E and whether
6664          * the PCH transcoder is on.
6665          */
6666         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6667         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6668             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6669                 pipe_config->has_pch_encoder = true;
6670
6671                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6672                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6673                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6674
6675                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6676         }
6677
6678         intel_get_pipe_timings(crtc, pipe_config);
6679
6680         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6681         if (intel_display_power_enabled(dev, pfit_domain))
6682                 ironlake_get_pfit_config(crtc, pipe_config);
6683
6684         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6685                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6686
6687         pipe_config->pixel_multiplier = 1;
6688
6689         return true;
6690 }
6691
6692 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6693                                int x, int y,
6694                                struct drm_framebuffer *fb)
6695 {
6696         struct drm_device *dev = crtc->dev;
6697         struct drm_i915_private *dev_priv = dev->dev_private;
6698         struct intel_encoder *encoder;
6699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6701         int pipe = intel_crtc->pipe;
6702         int ret;
6703
6704         drm_vblank_pre_modeset(dev, pipe);
6705
6706         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6707
6708         drm_vblank_post_modeset(dev, pipe);
6709
6710         if (ret != 0)
6711                 return ret;
6712
6713         for_each_encoder_on_crtc(dev, crtc, encoder) {
6714                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6715                         encoder->base.base.id,
6716                         drm_get_encoder_name(&encoder->base),
6717                         mode->base.id, mode->name);
6718                 encoder->mode_set(encoder);
6719         }
6720
6721         return 0;
6722 }
6723
6724 static bool intel_eld_uptodate(struct drm_connector *connector,
6725                                int reg_eldv, uint32_t bits_eldv,
6726                                int reg_elda, uint32_t bits_elda,
6727                                int reg_edid)
6728 {
6729         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6730         uint8_t *eld = connector->eld;
6731         uint32_t i;
6732
6733         i = I915_READ(reg_eldv);
6734         i &= bits_eldv;
6735
6736         if (!eld[0])
6737                 return !i;
6738
6739         if (!i)
6740                 return false;
6741
6742         i = I915_READ(reg_elda);
6743         i &= ~bits_elda;
6744         I915_WRITE(reg_elda, i);
6745
6746         for (i = 0; i < eld[2]; i++)
6747                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6748                         return false;
6749
6750         return true;
6751 }
6752
6753 static void g4x_write_eld(struct drm_connector *connector,
6754                           struct drm_crtc *crtc)
6755 {
6756         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6757         uint8_t *eld = connector->eld;
6758         uint32_t eldv;
6759         uint32_t len;
6760         uint32_t i;
6761
6762         i = I915_READ(G4X_AUD_VID_DID);
6763
6764         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6765                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6766         else
6767                 eldv = G4X_ELDV_DEVCTG;
6768
6769         if (intel_eld_uptodate(connector,
6770                                G4X_AUD_CNTL_ST, eldv,
6771                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6772                                G4X_HDMIW_HDMIEDID))
6773                 return;
6774
6775         i = I915_READ(G4X_AUD_CNTL_ST);
6776         i &= ~(eldv | G4X_ELD_ADDR);
6777         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6778         I915_WRITE(G4X_AUD_CNTL_ST, i);
6779
6780         if (!eld[0])
6781                 return;
6782
6783         len = min_t(uint8_t, eld[2], len);
6784         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6785         for (i = 0; i < len; i++)
6786                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6787
6788         i = I915_READ(G4X_AUD_CNTL_ST);
6789         i |= eldv;
6790         I915_WRITE(G4X_AUD_CNTL_ST, i);
6791 }
6792
6793 static void haswell_write_eld(struct drm_connector *connector,
6794                                      struct drm_crtc *crtc)
6795 {
6796         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6797         uint8_t *eld = connector->eld;
6798         struct drm_device *dev = crtc->dev;
6799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800         uint32_t eldv;
6801         uint32_t i;
6802         int len;
6803         int pipe = to_intel_crtc(crtc)->pipe;
6804         int tmp;
6805
6806         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6807         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6808         int aud_config = HSW_AUD_CFG(pipe);
6809         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6810
6811
6812         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6813
6814         /* Audio output enable */
6815         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6816         tmp = I915_READ(aud_cntrl_st2);
6817         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6818         I915_WRITE(aud_cntrl_st2, tmp);
6819
6820         /* Wait for 1 vertical blank */
6821         intel_wait_for_vblank(dev, pipe);
6822
6823         /* Set ELD valid state */
6824         tmp = I915_READ(aud_cntrl_st2);
6825         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6826         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6827         I915_WRITE(aud_cntrl_st2, tmp);
6828         tmp = I915_READ(aud_cntrl_st2);
6829         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6830
6831         /* Enable HDMI mode */
6832         tmp = I915_READ(aud_config);
6833         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6834         /* clear N_programing_enable and N_value_index */
6835         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6836         I915_WRITE(aud_config, tmp);
6837
6838         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6839
6840         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6841         intel_crtc->eld_vld = true;
6842
6843         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6844                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6845                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6846                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6847         } else
6848                 I915_WRITE(aud_config, 0);
6849
6850         if (intel_eld_uptodate(connector,
6851                                aud_cntrl_st2, eldv,
6852                                aud_cntl_st, IBX_ELD_ADDRESS,
6853                                hdmiw_hdmiedid))
6854                 return;
6855
6856         i = I915_READ(aud_cntrl_st2);
6857         i &= ~eldv;
6858         I915_WRITE(aud_cntrl_st2, i);
6859
6860         if (!eld[0])
6861                 return;
6862
6863         i = I915_READ(aud_cntl_st);
6864         i &= ~IBX_ELD_ADDRESS;
6865         I915_WRITE(aud_cntl_st, i);
6866         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6867         DRM_DEBUG_DRIVER("port num:%d\n", i);
6868
6869         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6870         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6871         for (i = 0; i < len; i++)
6872                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6873
6874         i = I915_READ(aud_cntrl_st2);
6875         i |= eldv;
6876         I915_WRITE(aud_cntrl_st2, i);
6877
6878 }
6879
6880 static void ironlake_write_eld(struct drm_connector *connector,
6881                                      struct drm_crtc *crtc)
6882 {
6883         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6884         uint8_t *eld = connector->eld;
6885         uint32_t eldv;
6886         uint32_t i;
6887         int len;
6888         int hdmiw_hdmiedid;
6889         int aud_config;
6890         int aud_cntl_st;
6891         int aud_cntrl_st2;
6892         int pipe = to_intel_crtc(crtc)->pipe;
6893
6894         if (HAS_PCH_IBX(connector->dev)) {
6895                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6896                 aud_config = IBX_AUD_CFG(pipe);
6897                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6898                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6899         } else {
6900                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6901                 aud_config = CPT_AUD_CFG(pipe);
6902                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6903                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6904         }
6905
6906         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6907
6908         i = I915_READ(aud_cntl_st);
6909         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6910         if (!i) {
6911                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6912                 /* operate blindly on all ports */
6913                 eldv = IBX_ELD_VALIDB;
6914                 eldv |= IBX_ELD_VALIDB << 4;
6915                 eldv |= IBX_ELD_VALIDB << 8;
6916         } else {
6917                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6918                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6919         }
6920
6921         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6922                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6923                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6924                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6925         } else
6926                 I915_WRITE(aud_config, 0);
6927
6928         if (intel_eld_uptodate(connector,
6929                                aud_cntrl_st2, eldv,
6930                                aud_cntl_st, IBX_ELD_ADDRESS,
6931                                hdmiw_hdmiedid))
6932                 return;
6933
6934         i = I915_READ(aud_cntrl_st2);
6935         i &= ~eldv;
6936         I915_WRITE(aud_cntrl_st2, i);
6937
6938         if (!eld[0])
6939                 return;
6940
6941         i = I915_READ(aud_cntl_st);
6942         i &= ~IBX_ELD_ADDRESS;
6943         I915_WRITE(aud_cntl_st, i);
6944
6945         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6946         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6947         for (i = 0; i < len; i++)
6948                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6949
6950         i = I915_READ(aud_cntrl_st2);
6951         i |= eldv;
6952         I915_WRITE(aud_cntrl_st2, i);
6953 }
6954
6955 void intel_write_eld(struct drm_encoder *encoder,
6956                      struct drm_display_mode *mode)
6957 {
6958         struct drm_crtc *crtc = encoder->crtc;
6959         struct drm_connector *connector;
6960         struct drm_device *dev = encoder->dev;
6961         struct drm_i915_private *dev_priv = dev->dev_private;
6962
6963         connector = drm_select_eld(encoder, mode);
6964         if (!connector)
6965                 return;
6966
6967         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6968                          connector->base.id,
6969                          drm_get_connector_name(connector),
6970                          connector->encoder->base.id,
6971                          drm_get_encoder_name(connector->encoder));
6972
6973         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6974
6975         if (dev_priv->display.write_eld)
6976                 dev_priv->display.write_eld(connector, crtc);
6977 }
6978
6979 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6980 {
6981         struct drm_device *dev = crtc->dev;
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6984         bool visible = base != 0;
6985         u32 cntl;
6986
6987         if (intel_crtc->cursor_visible == visible)
6988                 return;
6989
6990         cntl = I915_READ(_CURACNTR);
6991         if (visible) {
6992                 /* On these chipsets we can only modify the base whilst
6993                  * the cursor is disabled.
6994                  */
6995                 I915_WRITE(_CURABASE, base);
6996
6997                 cntl &= ~(CURSOR_FORMAT_MASK);
6998                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6999                 cntl |= CURSOR_ENABLE |
7000                         CURSOR_GAMMA_ENABLE |
7001                         CURSOR_FORMAT_ARGB;
7002         } else
7003                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7004         I915_WRITE(_CURACNTR, cntl);
7005
7006         intel_crtc->cursor_visible = visible;
7007 }
7008
7009 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7010 {
7011         struct drm_device *dev = crtc->dev;
7012         struct drm_i915_private *dev_priv = dev->dev_private;
7013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7014         int pipe = intel_crtc->pipe;
7015         bool visible = base != 0;
7016
7017         if (intel_crtc->cursor_visible != visible) {
7018                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7019                 if (base) {
7020                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7021                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7022                         cntl |= pipe << 28; /* Connect to correct pipe */
7023                 } else {
7024                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7025                         cntl |= CURSOR_MODE_DISABLE;
7026                 }
7027                 I915_WRITE(CURCNTR(pipe), cntl);
7028
7029                 intel_crtc->cursor_visible = visible;
7030         }
7031         /* and commit changes on next vblank */
7032         I915_WRITE(CURBASE(pipe), base);
7033 }
7034
7035 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7036 {
7037         struct drm_device *dev = crtc->dev;
7038         struct drm_i915_private *dev_priv = dev->dev_private;
7039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7040         int pipe = intel_crtc->pipe;
7041         bool visible = base != 0;
7042
7043         if (intel_crtc->cursor_visible != visible) {
7044                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7045                 if (base) {
7046                         cntl &= ~CURSOR_MODE;
7047                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7048                 } else {
7049                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7050                         cntl |= CURSOR_MODE_DISABLE;
7051                 }
7052                 if (IS_HASWELL(dev)) {
7053                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7054                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7055                 }
7056                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7057
7058                 intel_crtc->cursor_visible = visible;
7059         }
7060         /* and commit changes on next vblank */
7061         I915_WRITE(CURBASE_IVB(pipe), base);
7062 }
7063
7064 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7065 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7066                                      bool on)
7067 {
7068         struct drm_device *dev = crtc->dev;
7069         struct drm_i915_private *dev_priv = dev->dev_private;
7070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7071         int pipe = intel_crtc->pipe;
7072         int x = intel_crtc->cursor_x;
7073         int y = intel_crtc->cursor_y;
7074         u32 base = 0, pos = 0;
7075         bool visible;
7076
7077         if (on)
7078                 base = intel_crtc->cursor_addr;
7079
7080         if (x >= intel_crtc->config.pipe_src_w)
7081                 base = 0;
7082
7083         if (y >= intel_crtc->config.pipe_src_h)
7084                 base = 0;
7085
7086         if (x < 0) {
7087                 if (x + intel_crtc->cursor_width <= 0)
7088                         base = 0;
7089
7090                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7091                 x = -x;
7092         }
7093         pos |= x << CURSOR_X_SHIFT;
7094
7095         if (y < 0) {
7096                 if (y + intel_crtc->cursor_height <= 0)
7097                         base = 0;
7098
7099                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7100                 y = -y;
7101         }
7102         pos |= y << CURSOR_Y_SHIFT;
7103
7104         visible = base != 0;
7105         if (!visible && !intel_crtc->cursor_visible)
7106                 return;
7107
7108         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7109                 I915_WRITE(CURPOS_IVB(pipe), pos);
7110                 ivb_update_cursor(crtc, base);
7111         } else {
7112                 I915_WRITE(CURPOS(pipe), pos);
7113                 if (IS_845G(dev) || IS_I865G(dev))
7114                         i845_update_cursor(crtc, base);
7115                 else
7116                         i9xx_update_cursor(crtc, base);
7117         }
7118 }
7119
7120 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7121                                  struct drm_file *file,
7122                                  uint32_t handle,
7123                                  uint32_t width, uint32_t height)
7124 {
7125         struct drm_device *dev = crtc->dev;
7126         struct drm_i915_private *dev_priv = dev->dev_private;
7127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128         struct drm_i915_gem_object *obj;
7129         uint32_t addr;
7130         int ret;
7131
7132         /* if we want to turn off the cursor ignore width and height */
7133         if (!handle) {
7134                 DRM_DEBUG_KMS("cursor off\n");
7135                 addr = 0;
7136                 obj = NULL;
7137                 mutex_lock(&dev->struct_mutex);
7138                 goto finish;
7139         }
7140
7141         /* Currently we only support 64x64 cursors */
7142         if (width != 64 || height != 64) {
7143                 DRM_ERROR("we currently only support 64x64 cursors\n");
7144                 return -EINVAL;
7145         }
7146
7147         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7148         if (&obj->base == NULL)
7149                 return -ENOENT;
7150
7151         if (obj->base.size < width * height * 4) {
7152                 DRM_ERROR("buffer is to small\n");
7153                 ret = -ENOMEM;
7154                 goto fail;
7155         }
7156
7157         /* we only need to pin inside GTT if cursor is non-phy */
7158         mutex_lock(&dev->struct_mutex);
7159         if (!dev_priv->info->cursor_needs_physical) {
7160                 unsigned alignment;
7161
7162                 if (obj->tiling_mode) {
7163                         DRM_ERROR("cursor cannot be tiled\n");
7164                         ret = -EINVAL;
7165                         goto fail_locked;
7166                 }
7167
7168                 /* Note that the w/a also requires 2 PTE of padding following
7169                  * the bo. We currently fill all unused PTE with the shadow
7170                  * page and so we should always have valid PTE following the
7171                  * cursor preventing the VT-d warning.
7172                  */
7173                 alignment = 0;
7174                 if (need_vtd_wa(dev))
7175                         alignment = 64*1024;
7176
7177                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7178                 if (ret) {
7179                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7180                         goto fail_locked;
7181                 }
7182
7183                 ret = i915_gem_object_put_fence(obj);
7184                 if (ret) {
7185                         DRM_ERROR("failed to release fence for cursor");
7186                         goto fail_unpin;
7187                 }
7188
7189                 addr = i915_gem_obj_ggtt_offset(obj);
7190         } else {
7191                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7192                 ret = i915_gem_attach_phys_object(dev, obj,
7193                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7194                                                   align);
7195                 if (ret) {
7196                         DRM_ERROR("failed to attach phys object\n");
7197                         goto fail_locked;
7198                 }
7199                 addr = obj->phys_obj->handle->busaddr;
7200         }
7201
7202         if (IS_GEN2(dev))
7203                 I915_WRITE(CURSIZE, (height << 12) | width);
7204
7205  finish:
7206         if (intel_crtc->cursor_bo) {
7207                 if (dev_priv->info->cursor_needs_physical) {
7208                         if (intel_crtc->cursor_bo != obj)
7209                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7210                 } else
7211                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7212                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7213         }
7214
7215         mutex_unlock(&dev->struct_mutex);
7216
7217         intel_crtc->cursor_addr = addr;
7218         intel_crtc->cursor_bo = obj;
7219         intel_crtc->cursor_width = width;
7220         intel_crtc->cursor_height = height;
7221
7222         if (intel_crtc->active)
7223                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7224
7225         return 0;
7226 fail_unpin:
7227         i915_gem_object_unpin_from_display_plane(obj);
7228 fail_locked:
7229         mutex_unlock(&dev->struct_mutex);
7230 fail:
7231         drm_gem_object_unreference_unlocked(&obj->base);
7232         return ret;
7233 }
7234
7235 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7236 {
7237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7238
7239         intel_crtc->cursor_x = x;
7240         intel_crtc->cursor_y = y;
7241
7242         if (intel_crtc->active)
7243                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7244
7245         return 0;
7246 }
7247
7248 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7249                                  u16 *blue, uint32_t start, uint32_t size)
7250 {
7251         int end = (start + size > 256) ? 256 : start + size, i;
7252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253
7254         for (i = start; i < end; i++) {
7255                 intel_crtc->lut_r[i] = red[i] >> 8;
7256                 intel_crtc->lut_g[i] = green[i] >> 8;
7257                 intel_crtc->lut_b[i] = blue[i] >> 8;
7258         }
7259
7260         intel_crtc_load_lut(crtc);
7261 }
7262
7263 /* VESA 640x480x72Hz mode to set on the pipe */
7264 static struct drm_display_mode load_detect_mode = {
7265         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7266                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7267 };
7268
7269 static struct drm_framebuffer *
7270 intel_framebuffer_create(struct drm_device *dev,
7271                          struct drm_mode_fb_cmd2 *mode_cmd,
7272                          struct drm_i915_gem_object *obj)
7273 {
7274         struct intel_framebuffer *intel_fb;
7275         int ret;
7276
7277         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7278         if (!intel_fb) {
7279                 drm_gem_object_unreference_unlocked(&obj->base);
7280                 return ERR_PTR(-ENOMEM);
7281         }
7282
7283         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7284         if (ret) {
7285                 drm_gem_object_unreference_unlocked(&obj->base);
7286                 kfree(intel_fb);
7287                 return ERR_PTR(ret);
7288         }
7289
7290         return &intel_fb->base;
7291 }
7292
7293 static u32
7294 intel_framebuffer_pitch_for_width(int width, int bpp)
7295 {
7296         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7297         return ALIGN(pitch, 64);
7298 }
7299
7300 static u32
7301 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7302 {
7303         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7304         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7305 }
7306
7307 static struct drm_framebuffer *
7308 intel_framebuffer_create_for_mode(struct drm_device *dev,
7309                                   struct drm_display_mode *mode,
7310                                   int depth, int bpp)
7311 {
7312         struct drm_i915_gem_object *obj;
7313         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7314
7315         obj = i915_gem_alloc_object(dev,
7316                                     intel_framebuffer_size_for_mode(mode, bpp));
7317         if (obj == NULL)
7318                 return ERR_PTR(-ENOMEM);
7319
7320         mode_cmd.width = mode->hdisplay;
7321         mode_cmd.height = mode->vdisplay;
7322         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7323                                                                 bpp);
7324         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7325
7326         return intel_framebuffer_create(dev, &mode_cmd, obj);
7327 }
7328
7329 static struct drm_framebuffer *
7330 mode_fits_in_fbdev(struct drm_device *dev,
7331                    struct drm_display_mode *mode)
7332 {
7333         struct drm_i915_private *dev_priv = dev->dev_private;
7334         struct drm_i915_gem_object *obj;
7335         struct drm_framebuffer *fb;
7336
7337         if (dev_priv->fbdev == NULL)
7338                 return NULL;
7339
7340         obj = dev_priv->fbdev->ifb.obj;
7341         if (obj == NULL)
7342                 return NULL;
7343
7344         fb = &dev_priv->fbdev->ifb.base;
7345         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7346                                                                fb->bits_per_pixel))
7347                 return NULL;
7348
7349         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7350                 return NULL;
7351
7352         return fb;
7353 }
7354
7355 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7356                                 struct drm_display_mode *mode,
7357                                 struct intel_load_detect_pipe *old)
7358 {
7359         struct intel_crtc *intel_crtc;
7360         struct intel_encoder *intel_encoder =
7361                 intel_attached_encoder(connector);
7362         struct drm_crtc *possible_crtc;
7363         struct drm_encoder *encoder = &intel_encoder->base;
7364         struct drm_crtc *crtc = NULL;
7365         struct drm_device *dev = encoder->dev;
7366         struct drm_framebuffer *fb;
7367         int i = -1;
7368
7369         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7370                       connector->base.id, drm_get_connector_name(connector),
7371                       encoder->base.id, drm_get_encoder_name(encoder));
7372
7373         /*
7374          * Algorithm gets a little messy:
7375          *
7376          *   - if the connector already has an assigned crtc, use it (but make
7377          *     sure it's on first)
7378          *
7379          *   - try to find the first unused crtc that can drive this connector,
7380          *     and use that if we find one
7381          */
7382
7383         /* See if we already have a CRTC for this connector */
7384         if (encoder->crtc) {
7385                 crtc = encoder->crtc;
7386
7387                 mutex_lock(&crtc->mutex);
7388
7389                 old->dpms_mode = connector->dpms;
7390                 old->load_detect_temp = false;
7391
7392                 /* Make sure the crtc and connector are running */
7393                 if (connector->dpms != DRM_MODE_DPMS_ON)
7394                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7395
7396                 return true;
7397         }
7398
7399         /* Find an unused one (if possible) */
7400         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7401                 i++;
7402                 if (!(encoder->possible_crtcs & (1 << i)))
7403                         continue;
7404                 if (!possible_crtc->enabled) {
7405                         crtc = possible_crtc;
7406                         break;
7407                 }
7408         }
7409
7410         /*
7411          * If we didn't find an unused CRTC, don't use any.
7412          */
7413         if (!crtc) {
7414                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7415                 return false;
7416         }
7417
7418         mutex_lock(&crtc->mutex);
7419         intel_encoder->new_crtc = to_intel_crtc(crtc);
7420         to_intel_connector(connector)->new_encoder = intel_encoder;
7421
7422         intel_crtc = to_intel_crtc(crtc);
7423         old->dpms_mode = connector->dpms;
7424         old->load_detect_temp = true;
7425         old->release_fb = NULL;
7426
7427         if (!mode)
7428                 mode = &load_detect_mode;
7429
7430         /* We need a framebuffer large enough to accommodate all accesses
7431          * that the plane may generate whilst we perform load detection.
7432          * We can not rely on the fbcon either being present (we get called
7433          * during its initialisation to detect all boot displays, or it may
7434          * not even exist) or that it is large enough to satisfy the
7435          * requested mode.
7436          */
7437         fb = mode_fits_in_fbdev(dev, mode);
7438         if (fb == NULL) {
7439                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7440                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7441                 old->release_fb = fb;
7442         } else
7443                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7444         if (IS_ERR(fb)) {
7445                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7446                 mutex_unlock(&crtc->mutex);
7447                 return false;
7448         }
7449
7450         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7451                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7452                 if (old->release_fb)
7453                         old->release_fb->funcs->destroy(old->release_fb);
7454                 mutex_unlock(&crtc->mutex);
7455                 return false;
7456         }
7457
7458         /* let the connector get through one full cycle before testing */
7459         intel_wait_for_vblank(dev, intel_crtc->pipe);
7460         return true;
7461 }
7462
7463 void intel_release_load_detect_pipe(struct drm_connector *connector,
7464                                     struct intel_load_detect_pipe *old)
7465 {
7466         struct intel_encoder *intel_encoder =
7467                 intel_attached_encoder(connector);
7468         struct drm_encoder *encoder = &intel_encoder->base;
7469         struct drm_crtc *crtc = encoder->crtc;
7470
7471         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7472                       connector->base.id, drm_get_connector_name(connector),
7473                       encoder->base.id, drm_get_encoder_name(encoder));
7474
7475         if (old->load_detect_temp) {
7476                 to_intel_connector(connector)->new_encoder = NULL;
7477                 intel_encoder->new_crtc = NULL;
7478                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7479
7480                 if (old->release_fb) {
7481                         drm_framebuffer_unregister_private(old->release_fb);
7482                         drm_framebuffer_unreference(old->release_fb);
7483                 }
7484
7485                 mutex_unlock(&crtc->mutex);
7486                 return;
7487         }
7488
7489         /* Switch crtc and encoder back off if necessary */
7490         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7491                 connector->funcs->dpms(connector, old->dpms_mode);
7492
7493         mutex_unlock(&crtc->mutex);
7494 }
7495
7496 static int i9xx_pll_refclk(struct drm_device *dev,
7497                            const struct intel_crtc_config *pipe_config)
7498 {
7499         struct drm_i915_private *dev_priv = dev->dev_private;
7500         u32 dpll = pipe_config->dpll_hw_state.dpll;
7501
7502         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7503                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7504         else if (HAS_PCH_SPLIT(dev))
7505                 return 120000;
7506         else if (!IS_GEN2(dev))
7507                 return 96000;
7508         else
7509                 return 48000;
7510 }
7511
7512 /* Returns the clock of the currently programmed mode of the given pipe. */
7513 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7514                                 struct intel_crtc_config *pipe_config)
7515 {
7516         struct drm_device *dev = crtc->base.dev;
7517         struct drm_i915_private *dev_priv = dev->dev_private;
7518         int pipe = pipe_config->cpu_transcoder;
7519         u32 dpll = pipe_config->dpll_hw_state.dpll;
7520         u32 fp;
7521         intel_clock_t clock;
7522         int refclk = i9xx_pll_refclk(dev, pipe_config);
7523
7524         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7525                 fp = pipe_config->dpll_hw_state.fp0;
7526         else
7527                 fp = pipe_config->dpll_hw_state.fp1;
7528
7529         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7530         if (IS_PINEVIEW(dev)) {
7531                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7532                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7533         } else {
7534                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7535                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7536         }
7537
7538         if (!IS_GEN2(dev)) {
7539                 if (IS_PINEVIEW(dev))
7540                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7541                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7542                 else
7543                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7544                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7545
7546                 switch (dpll & DPLL_MODE_MASK) {
7547                 case DPLLB_MODE_DAC_SERIAL:
7548                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7549                                 5 : 10;
7550                         break;
7551                 case DPLLB_MODE_LVDS:
7552                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7553                                 7 : 14;
7554                         break;
7555                 default:
7556                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7557                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7558                         return;
7559                 }
7560
7561                 if (IS_PINEVIEW(dev))
7562                         pineview_clock(refclk, &clock);
7563                 else
7564                         i9xx_clock(refclk, &clock);
7565         } else {
7566                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7567
7568                 if (is_lvds) {
7569                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7570                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7571                         clock.p2 = 14;
7572                 } else {
7573                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7574                                 clock.p1 = 2;
7575                         else {
7576                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7577                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7578                         }
7579                         if (dpll & PLL_P2_DIVIDE_BY_4)
7580                                 clock.p2 = 4;
7581                         else
7582                                 clock.p2 = 2;
7583                 }
7584
7585                 i9xx_clock(refclk, &clock);
7586         }
7587
7588         /*
7589          * This value includes pixel_multiplier. We will use
7590          * port_clock to compute adjusted_mode.crtc_clock in the
7591          * encoder's get_config() function.
7592          */
7593         pipe_config->port_clock = clock.dot;
7594 }
7595
7596 int intel_dotclock_calculate(int link_freq,
7597                              const struct intel_link_m_n *m_n)
7598 {
7599         /*
7600          * The calculation for the data clock is:
7601          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7602          * But we want to avoid losing precison if possible, so:
7603          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7604          *
7605          * and the link clock is simpler:
7606          * link_clock = (m * link_clock) / n
7607          */
7608
7609         if (!m_n->link_n)
7610                 return 0;
7611
7612         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7613 }
7614
7615 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7616                                    struct intel_crtc_config *pipe_config)
7617 {
7618         struct drm_device *dev = crtc->base.dev;
7619
7620         /* read out port_clock from the DPLL */
7621         i9xx_crtc_clock_get(crtc, pipe_config);
7622
7623         /*
7624          * This value does not include pixel_multiplier.
7625          * We will check that port_clock and adjusted_mode.crtc_clock
7626          * agree once we know their relationship in the encoder's
7627          * get_config() function.
7628          */
7629         pipe_config->adjusted_mode.crtc_clock =
7630                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7631                                          &pipe_config->fdi_m_n);
7632 }
7633
7634 /** Returns the currently programmed mode of the given pipe. */
7635 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7636                                              struct drm_crtc *crtc)
7637 {
7638         struct drm_i915_private *dev_priv = dev->dev_private;
7639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7640         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7641         struct drm_display_mode *mode;
7642         struct intel_crtc_config pipe_config;
7643         int htot = I915_READ(HTOTAL(cpu_transcoder));
7644         int hsync = I915_READ(HSYNC(cpu_transcoder));
7645         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7646         int vsync = I915_READ(VSYNC(cpu_transcoder));
7647         enum pipe pipe = intel_crtc->pipe;
7648
7649         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7650         if (!mode)
7651                 return NULL;
7652
7653         /*
7654          * Construct a pipe_config sufficient for getting the clock info
7655          * back out of crtc_clock_get.
7656          *
7657          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7658          * to use a real value here instead.
7659          */
7660         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7661         pipe_config.pixel_multiplier = 1;
7662         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7663         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7664         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7665         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7666
7667         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7668         mode->hdisplay = (htot & 0xffff) + 1;
7669         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7670         mode->hsync_start = (hsync & 0xffff) + 1;
7671         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7672         mode->vdisplay = (vtot & 0xffff) + 1;
7673         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7674         mode->vsync_start = (vsync & 0xffff) + 1;
7675         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7676
7677         drm_mode_set_name(mode);
7678
7679         return mode;
7680 }
7681
7682 static void intel_increase_pllclock(struct drm_crtc *crtc)
7683 {
7684         struct drm_device *dev = crtc->dev;
7685         drm_i915_private_t *dev_priv = dev->dev_private;
7686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7687         int pipe = intel_crtc->pipe;
7688         int dpll_reg = DPLL(pipe);
7689         int dpll;
7690
7691         if (HAS_PCH_SPLIT(dev))
7692                 return;
7693
7694         if (!dev_priv->lvds_downclock_avail)
7695                 return;
7696
7697         dpll = I915_READ(dpll_reg);
7698         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7699                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7700
7701                 assert_panel_unlocked(dev_priv, pipe);
7702
7703                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7704                 I915_WRITE(dpll_reg, dpll);
7705                 intel_wait_for_vblank(dev, pipe);
7706
7707                 dpll = I915_READ(dpll_reg);
7708                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7709                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7710         }
7711 }
7712
7713 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7714 {
7715         struct drm_device *dev = crtc->dev;
7716         drm_i915_private_t *dev_priv = dev->dev_private;
7717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7718
7719         if (HAS_PCH_SPLIT(dev))
7720                 return;
7721
7722         if (!dev_priv->lvds_downclock_avail)
7723                 return;
7724
7725         /*
7726          * Since this is called by a timer, we should never get here in
7727          * the manual case.
7728          */
7729         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7730                 int pipe = intel_crtc->pipe;
7731                 int dpll_reg = DPLL(pipe);
7732                 int dpll;
7733
7734                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7735
7736                 assert_panel_unlocked(dev_priv, pipe);
7737
7738                 dpll = I915_READ(dpll_reg);
7739                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7740                 I915_WRITE(dpll_reg, dpll);
7741                 intel_wait_for_vblank(dev, pipe);
7742                 dpll = I915_READ(dpll_reg);
7743                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7744                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7745         }
7746
7747 }
7748
7749 void intel_mark_busy(struct drm_device *dev)
7750 {
7751         struct drm_i915_private *dev_priv = dev->dev_private;
7752
7753         hsw_package_c8_gpu_busy(dev_priv);
7754         i915_update_gfx_val(dev_priv);
7755 }
7756
7757 void intel_mark_idle(struct drm_device *dev)
7758 {
7759         struct drm_i915_private *dev_priv = dev->dev_private;
7760         struct drm_crtc *crtc;
7761
7762         hsw_package_c8_gpu_idle(dev_priv);
7763
7764         if (!i915_powersave)
7765                 return;
7766
7767         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7768                 if (!crtc->fb)
7769                         continue;
7770
7771                 intel_decrease_pllclock(crtc);
7772         }
7773
7774         if (dev_priv->info->gen >= 6)
7775                 gen6_rps_idle(dev->dev_private);
7776 }
7777
7778 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7779                         struct intel_ring_buffer *ring)
7780 {
7781         struct drm_device *dev = obj->base.dev;
7782         struct drm_crtc *crtc;
7783
7784         if (!i915_powersave)
7785                 return;
7786
7787         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7788                 if (!crtc->fb)
7789                         continue;
7790
7791                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7792                         continue;
7793
7794                 intel_increase_pllclock(crtc);
7795                 if (ring && intel_fbc_enabled(dev))
7796                         ring->fbc_dirty = true;
7797         }
7798 }
7799
7800 static void intel_crtc_destroy(struct drm_crtc *crtc)
7801 {
7802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7803         struct drm_device *dev = crtc->dev;
7804         struct intel_unpin_work *work;
7805         unsigned long flags;
7806
7807         spin_lock_irqsave(&dev->event_lock, flags);
7808         work = intel_crtc->unpin_work;
7809         intel_crtc->unpin_work = NULL;
7810         spin_unlock_irqrestore(&dev->event_lock, flags);
7811
7812         if (work) {
7813                 cancel_work_sync(&work->work);
7814                 kfree(work);
7815         }
7816
7817         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7818
7819         drm_crtc_cleanup(crtc);
7820
7821         kfree(intel_crtc);
7822 }
7823
7824 static void intel_unpin_work_fn(struct work_struct *__work)
7825 {
7826         struct intel_unpin_work *work =
7827                 container_of(__work, struct intel_unpin_work, work);
7828         struct drm_device *dev = work->crtc->dev;
7829
7830         mutex_lock(&dev->struct_mutex);
7831         intel_unpin_fb_obj(work->old_fb_obj);
7832         drm_gem_object_unreference(&work->pending_flip_obj->base);
7833         drm_gem_object_unreference(&work->old_fb_obj->base);
7834
7835         intel_update_fbc(dev);
7836         mutex_unlock(&dev->struct_mutex);
7837
7838         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7839         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7840
7841         kfree(work);
7842 }
7843
7844 static void do_intel_finish_page_flip(struct drm_device *dev,
7845                                       struct drm_crtc *crtc)
7846 {
7847         drm_i915_private_t *dev_priv = dev->dev_private;
7848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7849         struct intel_unpin_work *work;
7850         unsigned long flags;
7851
7852         /* Ignore early vblank irqs */
7853         if (intel_crtc == NULL)
7854                 return;
7855
7856         spin_lock_irqsave(&dev->event_lock, flags);
7857         work = intel_crtc->unpin_work;
7858
7859         /* Ensure we don't miss a work->pending update ... */
7860         smp_rmb();
7861
7862         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7863                 spin_unlock_irqrestore(&dev->event_lock, flags);
7864                 return;
7865         }
7866
7867         /* and that the unpin work is consistent wrt ->pending. */
7868         smp_rmb();
7869
7870         intel_crtc->unpin_work = NULL;
7871
7872         if (work->event)
7873                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7874
7875         drm_vblank_put(dev, intel_crtc->pipe);
7876
7877         spin_unlock_irqrestore(&dev->event_lock, flags);
7878
7879         wake_up_all(&dev_priv->pending_flip_queue);
7880
7881         queue_work(dev_priv->wq, &work->work);
7882
7883         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7884 }
7885
7886 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7887 {
7888         drm_i915_private_t *dev_priv = dev->dev_private;
7889         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7890
7891         do_intel_finish_page_flip(dev, crtc);
7892 }
7893
7894 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7895 {
7896         drm_i915_private_t *dev_priv = dev->dev_private;
7897         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7898
7899         do_intel_finish_page_flip(dev, crtc);
7900 }
7901
7902 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7903 {
7904         drm_i915_private_t *dev_priv = dev->dev_private;
7905         struct intel_crtc *intel_crtc =
7906                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7907         unsigned long flags;
7908
7909         /* NB: An MMIO update of the plane base pointer will also
7910          * generate a page-flip completion irq, i.e. every modeset
7911          * is also accompanied by a spurious intel_prepare_page_flip().
7912          */
7913         spin_lock_irqsave(&dev->event_lock, flags);
7914         if (intel_crtc->unpin_work)
7915                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7916         spin_unlock_irqrestore(&dev->event_lock, flags);
7917 }
7918
7919 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7920 {
7921         /* Ensure that the work item is consistent when activating it ... */
7922         smp_wmb();
7923         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7924         /* and that it is marked active as soon as the irq could fire. */
7925         smp_wmb();
7926 }
7927
7928 static int intel_gen2_queue_flip(struct drm_device *dev,
7929                                  struct drm_crtc *crtc,
7930                                  struct drm_framebuffer *fb,
7931                                  struct drm_i915_gem_object *obj,
7932                                  uint32_t flags)
7933 {
7934         struct drm_i915_private *dev_priv = dev->dev_private;
7935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7936         u32 flip_mask;
7937         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7938         int ret;
7939
7940         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7941         if (ret)
7942                 goto err;
7943
7944         ret = intel_ring_begin(ring, 6);
7945         if (ret)
7946                 goto err_unpin;
7947
7948         /* Can't queue multiple flips, so wait for the previous
7949          * one to finish before executing the next.
7950          */
7951         if (intel_crtc->plane)
7952                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7953         else
7954                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7955         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7956         intel_ring_emit(ring, MI_NOOP);
7957         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7958                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7959         intel_ring_emit(ring, fb->pitches[0]);
7960         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7961         intel_ring_emit(ring, 0); /* aux display base address, unused */
7962
7963         intel_mark_page_flip_active(intel_crtc);
7964         __intel_ring_advance(ring);
7965         return 0;
7966
7967 err_unpin:
7968         intel_unpin_fb_obj(obj);
7969 err:
7970         return ret;
7971 }
7972
7973 static int intel_gen3_queue_flip(struct drm_device *dev,
7974                                  struct drm_crtc *crtc,
7975                                  struct drm_framebuffer *fb,
7976                                  struct drm_i915_gem_object *obj,
7977                                  uint32_t flags)
7978 {
7979         struct drm_i915_private *dev_priv = dev->dev_private;
7980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7981         u32 flip_mask;
7982         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7983         int ret;
7984
7985         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7986         if (ret)
7987                 goto err;
7988
7989         ret = intel_ring_begin(ring, 6);
7990         if (ret)
7991                 goto err_unpin;
7992
7993         if (intel_crtc->plane)
7994                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7995         else
7996                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7997         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7998         intel_ring_emit(ring, MI_NOOP);
7999         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8000                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8001         intel_ring_emit(ring, fb->pitches[0]);
8002         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8003         intel_ring_emit(ring, MI_NOOP);
8004
8005         intel_mark_page_flip_active(intel_crtc);
8006         __intel_ring_advance(ring);
8007         return 0;
8008
8009 err_unpin:
8010         intel_unpin_fb_obj(obj);
8011 err:
8012         return ret;
8013 }
8014
8015 static int intel_gen4_queue_flip(struct drm_device *dev,
8016                                  struct drm_crtc *crtc,
8017                                  struct drm_framebuffer *fb,
8018                                  struct drm_i915_gem_object *obj,
8019                                  uint32_t flags)
8020 {
8021         struct drm_i915_private *dev_priv = dev->dev_private;
8022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8023         uint32_t pf, pipesrc;
8024         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8025         int ret;
8026
8027         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8028         if (ret)
8029                 goto err;
8030
8031         ret = intel_ring_begin(ring, 4);
8032         if (ret)
8033                 goto err_unpin;
8034
8035         /* i965+ uses the linear or tiled offsets from the
8036          * Display Registers (which do not change across a page-flip)
8037          * so we need only reprogram the base address.
8038          */
8039         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8040                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8041         intel_ring_emit(ring, fb->pitches[0]);
8042         intel_ring_emit(ring,
8043                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8044                         obj->tiling_mode);
8045
8046         /* XXX Enabling the panel-fitter across page-flip is so far
8047          * untested on non-native modes, so ignore it for now.
8048          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8049          */
8050         pf = 0;
8051         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8052         intel_ring_emit(ring, pf | pipesrc);
8053
8054         intel_mark_page_flip_active(intel_crtc);
8055         __intel_ring_advance(ring);
8056         return 0;
8057
8058 err_unpin:
8059         intel_unpin_fb_obj(obj);
8060 err:
8061         return ret;
8062 }
8063
8064 static int intel_gen6_queue_flip(struct drm_device *dev,
8065                                  struct drm_crtc *crtc,
8066                                  struct drm_framebuffer *fb,
8067                                  struct drm_i915_gem_object *obj,
8068                                  uint32_t flags)
8069 {
8070         struct drm_i915_private *dev_priv = dev->dev_private;
8071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8072         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8073         uint32_t pf, pipesrc;
8074         int ret;
8075
8076         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8077         if (ret)
8078                 goto err;
8079
8080         ret = intel_ring_begin(ring, 4);
8081         if (ret)
8082                 goto err_unpin;
8083
8084         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8085                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8086         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8087         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8088
8089         /* Contrary to the suggestions in the documentation,
8090          * "Enable Panel Fitter" does not seem to be required when page
8091          * flipping with a non-native mode, and worse causes a normal
8092          * modeset to fail.
8093          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8094          */
8095         pf = 0;
8096         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8097         intel_ring_emit(ring, pf | pipesrc);
8098
8099         intel_mark_page_flip_active(intel_crtc);
8100         __intel_ring_advance(ring);
8101         return 0;
8102
8103 err_unpin:
8104         intel_unpin_fb_obj(obj);
8105 err:
8106         return ret;
8107 }
8108
8109 static int intel_gen7_queue_flip(struct drm_device *dev,
8110                                  struct drm_crtc *crtc,
8111                                  struct drm_framebuffer *fb,
8112                                  struct drm_i915_gem_object *obj,
8113                                  uint32_t flags)
8114 {
8115         struct drm_i915_private *dev_priv = dev->dev_private;
8116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8117         struct intel_ring_buffer *ring;
8118         uint32_t plane_bit = 0;
8119         int len, ret;
8120
8121         ring = obj->ring;
8122         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8123                 ring = &dev_priv->ring[BCS];
8124
8125         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8126         if (ret)
8127                 goto err;
8128
8129         switch(intel_crtc->plane) {
8130         case PLANE_A:
8131                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8132                 break;
8133         case PLANE_B:
8134                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8135                 break;
8136         case PLANE_C:
8137                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8138                 break;
8139         default:
8140                 WARN_ONCE(1, "unknown plane in flip command\n");
8141                 ret = -ENODEV;
8142                 goto err_unpin;
8143         }
8144
8145         len = 4;
8146         if (ring->id == RCS)
8147                 len += 6;
8148
8149         ret = intel_ring_begin(ring, len);
8150         if (ret)
8151                 goto err_unpin;
8152
8153         /* Unmask the flip-done completion message. Note that the bspec says that
8154          * we should do this for both the BCS and RCS, and that we must not unmask
8155          * more than one flip event at any time (or ensure that one flip message
8156          * can be sent by waiting for flip-done prior to queueing new flips).
8157          * Experimentation says that BCS works despite DERRMR masking all
8158          * flip-done completion events and that unmasking all planes at once
8159          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8160          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8161          */
8162         if (ring->id == RCS) {
8163                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8164                 intel_ring_emit(ring, DERRMR);
8165                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8166                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8167                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8168                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8169                 intel_ring_emit(ring, DERRMR);
8170                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8171         }
8172
8173         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8174         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8175         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8176         intel_ring_emit(ring, (MI_NOOP));
8177
8178         intel_mark_page_flip_active(intel_crtc);
8179         __intel_ring_advance(ring);
8180         return 0;
8181
8182 err_unpin:
8183         intel_unpin_fb_obj(obj);
8184 err:
8185         return ret;
8186 }
8187
8188 static int intel_default_queue_flip(struct drm_device *dev,
8189                                     struct drm_crtc *crtc,
8190                                     struct drm_framebuffer *fb,
8191                                     struct drm_i915_gem_object *obj,
8192                                     uint32_t flags)
8193 {
8194         return -ENODEV;
8195 }
8196
8197 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8198                                 struct drm_framebuffer *fb,
8199                                 struct drm_pending_vblank_event *event,
8200                                 uint32_t page_flip_flags)
8201 {
8202         struct drm_device *dev = crtc->dev;
8203         struct drm_i915_private *dev_priv = dev->dev_private;
8204         struct drm_framebuffer *old_fb = crtc->fb;
8205         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207         struct intel_unpin_work *work;
8208         unsigned long flags;
8209         int ret;
8210
8211         /* Can't change pixel format via MI display flips. */
8212         if (fb->pixel_format != crtc->fb->pixel_format)
8213                 return -EINVAL;
8214
8215         /*
8216          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8217          * Note that pitch changes could also affect these register.
8218          */
8219         if (INTEL_INFO(dev)->gen > 3 &&
8220             (fb->offsets[0] != crtc->fb->offsets[0] ||
8221              fb->pitches[0] != crtc->fb->pitches[0]))
8222                 return -EINVAL;
8223
8224         work = kzalloc(sizeof(*work), GFP_KERNEL);
8225         if (work == NULL)
8226                 return -ENOMEM;
8227
8228         work->event = event;
8229         work->crtc = crtc;
8230         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8231         INIT_WORK(&work->work, intel_unpin_work_fn);
8232
8233         ret = drm_vblank_get(dev, intel_crtc->pipe);
8234         if (ret)
8235                 goto free_work;
8236
8237         /* We borrow the event spin lock for protecting unpin_work */
8238         spin_lock_irqsave(&dev->event_lock, flags);
8239         if (intel_crtc->unpin_work) {
8240                 spin_unlock_irqrestore(&dev->event_lock, flags);
8241                 kfree(work);
8242                 drm_vblank_put(dev, intel_crtc->pipe);
8243
8244                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8245                 return -EBUSY;
8246         }
8247         intel_crtc->unpin_work = work;
8248         spin_unlock_irqrestore(&dev->event_lock, flags);
8249
8250         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8251                 flush_workqueue(dev_priv->wq);
8252
8253         ret = i915_mutex_lock_interruptible(dev);
8254         if (ret)
8255                 goto cleanup;
8256
8257         /* Reference the objects for the scheduled work. */
8258         drm_gem_object_reference(&work->old_fb_obj->base);
8259         drm_gem_object_reference(&obj->base);
8260
8261         crtc->fb = fb;
8262
8263         work->pending_flip_obj = obj;
8264
8265         work->enable_stall_check = true;
8266
8267         atomic_inc(&intel_crtc->unpin_work_count);
8268         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8269
8270         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8271         if (ret)
8272                 goto cleanup_pending;
8273
8274         intel_disable_fbc(dev);
8275         intel_mark_fb_busy(obj, NULL);
8276         mutex_unlock(&dev->struct_mutex);
8277
8278         trace_i915_flip_request(intel_crtc->plane, obj);
8279
8280         return 0;
8281
8282 cleanup_pending:
8283         atomic_dec(&intel_crtc->unpin_work_count);
8284         crtc->fb = old_fb;
8285         drm_gem_object_unreference(&work->old_fb_obj->base);
8286         drm_gem_object_unreference(&obj->base);
8287         mutex_unlock(&dev->struct_mutex);
8288
8289 cleanup:
8290         spin_lock_irqsave(&dev->event_lock, flags);
8291         intel_crtc->unpin_work = NULL;
8292         spin_unlock_irqrestore(&dev->event_lock, flags);
8293
8294         drm_vblank_put(dev, intel_crtc->pipe);
8295 free_work:
8296         kfree(work);
8297
8298         return ret;
8299 }
8300
8301 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8302         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8303         .load_lut = intel_crtc_load_lut,
8304 };
8305
8306 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8307                                   struct drm_crtc *crtc)
8308 {
8309         struct drm_device *dev;
8310         struct drm_crtc *tmp;
8311         int crtc_mask = 1;
8312
8313         WARN(!crtc, "checking null crtc?\n");
8314
8315         dev = crtc->dev;
8316
8317         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8318                 if (tmp == crtc)
8319                         break;
8320                 crtc_mask <<= 1;
8321         }
8322
8323         if (encoder->possible_crtcs & crtc_mask)
8324                 return true;
8325         return false;
8326 }
8327
8328 /**
8329  * intel_modeset_update_staged_output_state
8330  *
8331  * Updates the staged output configuration state, e.g. after we've read out the
8332  * current hw state.
8333  */
8334 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8335 {
8336         struct intel_encoder *encoder;
8337         struct intel_connector *connector;
8338
8339         list_for_each_entry(connector, &dev->mode_config.connector_list,
8340                             base.head) {
8341                 connector->new_encoder =
8342                         to_intel_encoder(connector->base.encoder);
8343         }
8344
8345         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8346                             base.head) {
8347                 encoder->new_crtc =
8348                         to_intel_crtc(encoder->base.crtc);
8349         }
8350 }
8351
8352 /**
8353  * intel_modeset_commit_output_state
8354  *
8355  * This function copies the stage display pipe configuration to the real one.
8356  */
8357 static void intel_modeset_commit_output_state(struct drm_device *dev)
8358 {
8359         struct intel_encoder *encoder;
8360         struct intel_connector *connector;
8361
8362         list_for_each_entry(connector, &dev->mode_config.connector_list,
8363                             base.head) {
8364                 connector->base.encoder = &connector->new_encoder->base;
8365         }
8366
8367         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8368                             base.head) {
8369                 encoder->base.crtc = &encoder->new_crtc->base;
8370         }
8371 }
8372
8373 static void
8374 connected_sink_compute_bpp(struct intel_connector * connector,
8375                            struct intel_crtc_config *pipe_config)
8376 {
8377         int bpp = pipe_config->pipe_bpp;
8378
8379         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8380                 connector->base.base.id,
8381                 drm_get_connector_name(&connector->base));
8382
8383         /* Don't use an invalid EDID bpc value */
8384         if (connector->base.display_info.bpc &&
8385             connector->base.display_info.bpc * 3 < bpp) {
8386                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8387                               bpp, connector->base.display_info.bpc*3);
8388                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8389         }
8390
8391         /* Clamp bpp to 8 on screens without EDID 1.4 */
8392         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8393                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8394                               bpp);
8395                 pipe_config->pipe_bpp = 24;
8396         }
8397 }
8398
8399 static int
8400 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8401                           struct drm_framebuffer *fb,
8402                           struct intel_crtc_config *pipe_config)
8403 {
8404         struct drm_device *dev = crtc->base.dev;
8405         struct intel_connector *connector;
8406         int bpp;
8407
8408         switch (fb->pixel_format) {
8409         case DRM_FORMAT_C8:
8410                 bpp = 8*3; /* since we go through a colormap */
8411                 break;
8412         case DRM_FORMAT_XRGB1555:
8413         case DRM_FORMAT_ARGB1555:
8414                 /* checked in intel_framebuffer_init already */
8415                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8416                         return -EINVAL;
8417         case DRM_FORMAT_RGB565:
8418                 bpp = 6*3; /* min is 18bpp */
8419                 break;
8420         case DRM_FORMAT_XBGR8888:
8421         case DRM_FORMAT_ABGR8888:
8422                 /* checked in intel_framebuffer_init already */
8423                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8424                         return -EINVAL;
8425         case DRM_FORMAT_XRGB8888:
8426         case DRM_FORMAT_ARGB8888:
8427                 bpp = 8*3;
8428                 break;
8429         case DRM_FORMAT_XRGB2101010:
8430         case DRM_FORMAT_ARGB2101010:
8431         case DRM_FORMAT_XBGR2101010:
8432         case DRM_FORMAT_ABGR2101010:
8433                 /* checked in intel_framebuffer_init already */
8434                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8435                         return -EINVAL;
8436                 bpp = 10*3;
8437                 break;
8438         /* TODO: gen4+ supports 16 bpc floating point, too. */
8439         default:
8440                 DRM_DEBUG_KMS("unsupported depth\n");
8441                 return -EINVAL;
8442         }
8443
8444         pipe_config->pipe_bpp = bpp;
8445
8446         /* Clamp display bpp to EDID value */
8447         list_for_each_entry(connector, &dev->mode_config.connector_list,
8448                             base.head) {
8449                 if (!connector->new_encoder ||
8450                     connector->new_encoder->new_crtc != crtc)
8451                         continue;
8452
8453                 connected_sink_compute_bpp(connector, pipe_config);
8454         }
8455
8456         return bpp;
8457 }
8458
8459 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8460 {
8461         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8462                         "type: 0x%x flags: 0x%x\n",
8463                 mode->crtc_clock,
8464                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8465                 mode->crtc_hsync_end, mode->crtc_htotal,
8466                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8467                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8468 }
8469
8470 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8471                                    struct intel_crtc_config *pipe_config,
8472                                    const char *context)
8473 {
8474         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8475                       context, pipe_name(crtc->pipe));
8476
8477         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8478         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8479                       pipe_config->pipe_bpp, pipe_config->dither);
8480         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8481                       pipe_config->has_pch_encoder,
8482                       pipe_config->fdi_lanes,
8483                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8484                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8485                       pipe_config->fdi_m_n.tu);
8486         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8487                       pipe_config->has_dp_encoder,
8488                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8489                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8490                       pipe_config->dp_m_n.tu);
8491         DRM_DEBUG_KMS("requested mode:\n");
8492         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8493         DRM_DEBUG_KMS("adjusted mode:\n");
8494         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8495         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8496         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8497         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8498                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8499         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8500                       pipe_config->gmch_pfit.control,
8501                       pipe_config->gmch_pfit.pgm_ratios,
8502                       pipe_config->gmch_pfit.lvds_border_bits);
8503         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8504                       pipe_config->pch_pfit.pos,
8505                       pipe_config->pch_pfit.size,
8506                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8507         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8508         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8509 }
8510
8511 static bool check_encoder_cloning(struct drm_crtc *crtc)
8512 {
8513         int num_encoders = 0;
8514         bool uncloneable_encoders = false;
8515         struct intel_encoder *encoder;
8516
8517         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8518                             base.head) {
8519                 if (&encoder->new_crtc->base != crtc)
8520                         continue;
8521
8522                 num_encoders++;
8523                 if (!encoder->cloneable)
8524                         uncloneable_encoders = true;
8525         }
8526
8527         return !(num_encoders > 1 && uncloneable_encoders);
8528 }
8529
8530 static struct intel_crtc_config *
8531 intel_modeset_pipe_config(struct drm_crtc *crtc,
8532                           struct drm_framebuffer *fb,
8533                           struct drm_display_mode *mode)
8534 {
8535         struct drm_device *dev = crtc->dev;
8536         struct intel_encoder *encoder;
8537         struct intel_crtc_config *pipe_config;
8538         int plane_bpp, ret = -EINVAL;
8539         bool retry = true;
8540
8541         if (!check_encoder_cloning(crtc)) {
8542                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8543                 return ERR_PTR(-EINVAL);
8544         }
8545
8546         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8547         if (!pipe_config)
8548                 return ERR_PTR(-ENOMEM);
8549
8550         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8551         drm_mode_copy(&pipe_config->requested_mode, mode);
8552
8553         pipe_config->cpu_transcoder =
8554                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8555         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8556
8557         /*
8558          * Sanitize sync polarity flags based on requested ones. If neither
8559          * positive or negative polarity is requested, treat this as meaning
8560          * negative polarity.
8561          */
8562         if (!(pipe_config->adjusted_mode.flags &
8563               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8564                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8565
8566         if (!(pipe_config->adjusted_mode.flags &
8567               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8568                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8569
8570         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8571          * plane pixel format and any sink constraints into account. Returns the
8572          * source plane bpp so that dithering can be selected on mismatches
8573          * after encoders and crtc also have had their say. */
8574         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8575                                               fb, pipe_config);
8576         if (plane_bpp < 0)
8577                 goto fail;
8578
8579         /*
8580          * Determine the real pipe dimensions. Note that stereo modes can
8581          * increase the actual pipe size due to the frame doubling and
8582          * insertion of additional space for blanks between the frame. This
8583          * is stored in the crtc timings. We use the requested mode to do this
8584          * computation to clearly distinguish it from the adjusted mode, which
8585          * can be changed by the connectors in the below retry loop.
8586          */
8587         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8588         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8589         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8590
8591 encoder_retry:
8592         /* Ensure the port clock defaults are reset when retrying. */
8593         pipe_config->port_clock = 0;
8594         pipe_config->pixel_multiplier = 1;
8595
8596         /* Fill in default crtc timings, allow encoders to overwrite them. */
8597         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8598
8599         /* Pass our mode to the connectors and the CRTC to give them a chance to
8600          * adjust it according to limitations or connector properties, and also
8601          * a chance to reject the mode entirely.
8602          */
8603         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8604                             base.head) {
8605
8606                 if (&encoder->new_crtc->base != crtc)
8607                         continue;
8608
8609                 if (!(encoder->compute_config(encoder, pipe_config))) {
8610                         DRM_DEBUG_KMS("Encoder config failure\n");
8611                         goto fail;
8612                 }
8613         }
8614
8615         /* Set default port clock if not overwritten by the encoder. Needs to be
8616          * done afterwards in case the encoder adjusts the mode. */
8617         if (!pipe_config->port_clock)
8618                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8619                         * pipe_config->pixel_multiplier;
8620
8621         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8622         if (ret < 0) {
8623                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8624                 goto fail;
8625         }
8626
8627         if (ret == RETRY) {
8628                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8629                         ret = -EINVAL;
8630                         goto fail;
8631                 }
8632
8633                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8634                 retry = false;
8635                 goto encoder_retry;
8636         }
8637
8638         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8639         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8640                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8641
8642         return pipe_config;
8643 fail:
8644         kfree(pipe_config);
8645         return ERR_PTR(ret);
8646 }
8647
8648 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8649  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8650 static void
8651 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8652                              unsigned *prepare_pipes, unsigned *disable_pipes)
8653 {
8654         struct intel_crtc *intel_crtc;
8655         struct drm_device *dev = crtc->dev;
8656         struct intel_encoder *encoder;
8657         struct intel_connector *connector;
8658         struct drm_crtc *tmp_crtc;
8659
8660         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8661
8662         /* Check which crtcs have changed outputs connected to them, these need
8663          * to be part of the prepare_pipes mask. We don't (yet) support global
8664          * modeset across multiple crtcs, so modeset_pipes will only have one
8665          * bit set at most. */
8666         list_for_each_entry(connector, &dev->mode_config.connector_list,
8667                             base.head) {
8668                 if (connector->base.encoder == &connector->new_encoder->base)
8669                         continue;
8670
8671                 if (connector->base.encoder) {
8672                         tmp_crtc = connector->base.encoder->crtc;
8673
8674                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8675                 }
8676
8677                 if (connector->new_encoder)
8678                         *prepare_pipes |=
8679                                 1 << connector->new_encoder->new_crtc->pipe;
8680         }
8681
8682         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8683                             base.head) {
8684                 if (encoder->base.crtc == &encoder->new_crtc->base)
8685                         continue;
8686
8687                 if (encoder->base.crtc) {
8688                         tmp_crtc = encoder->base.crtc;
8689
8690                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8691                 }
8692
8693                 if (encoder->new_crtc)
8694                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8695         }
8696
8697         /* Check for any pipes that will be fully disabled ... */
8698         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8699                             base.head) {
8700                 bool used = false;
8701
8702                 /* Don't try to disable disabled crtcs. */
8703                 if (!intel_crtc->base.enabled)
8704                         continue;
8705
8706                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8707                                     base.head) {
8708                         if (encoder->new_crtc == intel_crtc)
8709                                 used = true;
8710                 }
8711
8712                 if (!used)
8713                         *disable_pipes |= 1 << intel_crtc->pipe;
8714         }
8715
8716
8717         /* set_mode is also used to update properties on life display pipes. */
8718         intel_crtc = to_intel_crtc(crtc);
8719         if (crtc->enabled)
8720                 *prepare_pipes |= 1 << intel_crtc->pipe;
8721
8722         /*
8723          * For simplicity do a full modeset on any pipe where the output routing
8724          * changed. We could be more clever, but that would require us to be
8725          * more careful with calling the relevant encoder->mode_set functions.
8726          */
8727         if (*prepare_pipes)
8728                 *modeset_pipes = *prepare_pipes;
8729
8730         /* ... and mask these out. */
8731         *modeset_pipes &= ~(*disable_pipes);
8732         *prepare_pipes &= ~(*disable_pipes);
8733
8734         /*
8735          * HACK: We don't (yet) fully support global modesets. intel_set_config
8736          * obies this rule, but the modeset restore mode of
8737          * intel_modeset_setup_hw_state does not.
8738          */
8739         *modeset_pipes &= 1 << intel_crtc->pipe;
8740         *prepare_pipes &= 1 << intel_crtc->pipe;
8741
8742         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8743                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8744 }
8745
8746 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8747 {
8748         struct drm_encoder *encoder;
8749         struct drm_device *dev = crtc->dev;
8750
8751         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8752                 if (encoder->crtc == crtc)
8753                         return true;
8754
8755         return false;
8756 }
8757
8758 static void
8759 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8760 {
8761         struct intel_encoder *intel_encoder;
8762         struct intel_crtc *intel_crtc;
8763         struct drm_connector *connector;
8764
8765         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8766                             base.head) {
8767                 if (!intel_encoder->base.crtc)
8768                         continue;
8769
8770                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8771
8772                 if (prepare_pipes & (1 << intel_crtc->pipe))
8773                         intel_encoder->connectors_active = false;
8774         }
8775
8776         intel_modeset_commit_output_state(dev);
8777
8778         /* Update computed state. */
8779         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8780                             base.head) {
8781                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8782         }
8783
8784         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8785                 if (!connector->encoder || !connector->encoder->crtc)
8786                         continue;
8787
8788                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8789
8790                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8791                         struct drm_property *dpms_property =
8792                                 dev->mode_config.dpms_property;
8793
8794                         connector->dpms = DRM_MODE_DPMS_ON;
8795                         drm_object_property_set_value(&connector->base,
8796                                                          dpms_property,
8797                                                          DRM_MODE_DPMS_ON);
8798
8799                         intel_encoder = to_intel_encoder(connector->encoder);
8800                         intel_encoder->connectors_active = true;
8801                 }
8802         }
8803
8804 }
8805
8806 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8807 {
8808         int diff;
8809
8810         if (clock1 == clock2)
8811                 return true;
8812
8813         if (!clock1 || !clock2)
8814                 return false;
8815
8816         diff = abs(clock1 - clock2);
8817
8818         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8819                 return true;
8820
8821         return false;
8822 }
8823
8824 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8825         list_for_each_entry((intel_crtc), \
8826                             &(dev)->mode_config.crtc_list, \
8827                             base.head) \
8828                 if (mask & (1 <<(intel_crtc)->pipe))
8829
8830 static bool
8831 intel_pipe_config_compare(struct drm_device *dev,
8832                           struct intel_crtc_config *current_config,
8833                           struct intel_crtc_config *pipe_config)
8834 {
8835 #define PIPE_CONF_CHECK_X(name) \
8836         if (current_config->name != pipe_config->name) { \
8837                 DRM_ERROR("mismatch in " #name " " \
8838                           "(expected 0x%08x, found 0x%08x)\n", \
8839                           current_config->name, \
8840                           pipe_config->name); \
8841                 return false; \
8842         }
8843
8844 #define PIPE_CONF_CHECK_I(name) \
8845         if (current_config->name != pipe_config->name) { \
8846                 DRM_ERROR("mismatch in " #name " " \
8847                           "(expected %i, found %i)\n", \
8848                           current_config->name, \
8849                           pipe_config->name); \
8850                 return false; \
8851         }
8852
8853 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8854         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8855                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8856                           "(expected %i, found %i)\n", \
8857                           current_config->name & (mask), \
8858                           pipe_config->name & (mask)); \
8859                 return false; \
8860         }
8861
8862 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8863         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8864                 DRM_ERROR("mismatch in " #name " " \
8865                           "(expected %i, found %i)\n", \
8866                           current_config->name, \
8867                           pipe_config->name); \
8868                 return false; \
8869         }
8870
8871 #define PIPE_CONF_QUIRK(quirk)  \
8872         ((current_config->quirks | pipe_config->quirks) & (quirk))
8873
8874         PIPE_CONF_CHECK_I(cpu_transcoder);
8875
8876         PIPE_CONF_CHECK_I(has_pch_encoder);
8877         PIPE_CONF_CHECK_I(fdi_lanes);
8878         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8879         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8880         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8881         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8882         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8883
8884         PIPE_CONF_CHECK_I(has_dp_encoder);
8885         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8886         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8887         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8888         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8889         PIPE_CONF_CHECK_I(dp_m_n.tu);
8890
8891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8896         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8897
8898         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8899         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8901         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8903         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8904
8905         PIPE_CONF_CHECK_I(pixel_multiplier);
8906
8907         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8908                               DRM_MODE_FLAG_INTERLACE);
8909
8910         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8911                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8912                                       DRM_MODE_FLAG_PHSYNC);
8913                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8914                                       DRM_MODE_FLAG_NHSYNC);
8915                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8916                                       DRM_MODE_FLAG_PVSYNC);
8917                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8918                                       DRM_MODE_FLAG_NVSYNC);
8919         }
8920
8921         PIPE_CONF_CHECK_I(pipe_src_w);
8922         PIPE_CONF_CHECK_I(pipe_src_h);
8923
8924         PIPE_CONF_CHECK_I(gmch_pfit.control);
8925         /* pfit ratios are autocomputed by the hw on gen4+ */
8926         if (INTEL_INFO(dev)->gen < 4)
8927                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8928         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8929         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8930         if (current_config->pch_pfit.enabled) {
8931                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8932                 PIPE_CONF_CHECK_I(pch_pfit.size);
8933         }
8934
8935         PIPE_CONF_CHECK_I(ips_enabled);
8936
8937         PIPE_CONF_CHECK_I(double_wide);
8938
8939         PIPE_CONF_CHECK_I(shared_dpll);
8940         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8941         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8942         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8943         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8944
8945         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8946                 PIPE_CONF_CHECK_I(pipe_bpp);
8947
8948         if (!IS_HASWELL(dev)) {
8949                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8950                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8951         }
8952
8953 #undef PIPE_CONF_CHECK_X
8954 #undef PIPE_CONF_CHECK_I
8955 #undef PIPE_CONF_CHECK_FLAGS
8956 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8957 #undef PIPE_CONF_QUIRK
8958
8959         return true;
8960 }
8961
8962 static void
8963 check_connector_state(struct drm_device *dev)
8964 {
8965         struct intel_connector *connector;
8966
8967         list_for_each_entry(connector, &dev->mode_config.connector_list,
8968                             base.head) {
8969                 /* This also checks the encoder/connector hw state with the
8970                  * ->get_hw_state callbacks. */
8971                 intel_connector_check_state(connector);
8972
8973                 WARN(&connector->new_encoder->base != connector->base.encoder,
8974                      "connector's staged encoder doesn't match current encoder\n");
8975         }
8976 }
8977
8978 static void
8979 check_encoder_state(struct drm_device *dev)
8980 {
8981         struct intel_encoder *encoder;
8982         struct intel_connector *connector;
8983
8984         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8985                             base.head) {
8986                 bool enabled = false;
8987                 bool active = false;
8988                 enum pipe pipe, tracked_pipe;
8989
8990                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8991                               encoder->base.base.id,
8992                               drm_get_encoder_name(&encoder->base));
8993
8994                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8995                      "encoder's stage crtc doesn't match current crtc\n");
8996                 WARN(encoder->connectors_active && !encoder->base.crtc,
8997                      "encoder's active_connectors set, but no crtc\n");
8998
8999                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9000                                     base.head) {
9001                         if (connector->base.encoder != &encoder->base)
9002                                 continue;
9003                         enabled = true;
9004                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9005                                 active = true;
9006                 }
9007                 WARN(!!encoder->base.crtc != enabled,
9008                      "encoder's enabled state mismatch "
9009                      "(expected %i, found %i)\n",
9010                      !!encoder->base.crtc, enabled);
9011                 WARN(active && !encoder->base.crtc,
9012                      "active encoder with no crtc\n");
9013
9014                 WARN(encoder->connectors_active != active,
9015                      "encoder's computed active state doesn't match tracked active state "
9016                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9017
9018                 active = encoder->get_hw_state(encoder, &pipe);
9019                 WARN(active != encoder->connectors_active,
9020                      "encoder's hw state doesn't match sw tracking "
9021                      "(expected %i, found %i)\n",
9022                      encoder->connectors_active, active);
9023
9024                 if (!encoder->base.crtc)
9025                         continue;
9026
9027                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9028                 WARN(active && pipe != tracked_pipe,
9029                      "active encoder's pipe doesn't match"
9030                      "(expected %i, found %i)\n",
9031                      tracked_pipe, pipe);
9032
9033         }
9034 }
9035
9036 static void
9037 check_crtc_state(struct drm_device *dev)
9038 {
9039         drm_i915_private_t *dev_priv = dev->dev_private;
9040         struct intel_crtc *crtc;
9041         struct intel_encoder *encoder;
9042         struct intel_crtc_config pipe_config;
9043
9044         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9045                             base.head) {
9046                 bool enabled = false;
9047                 bool active = false;
9048
9049                 memset(&pipe_config, 0, sizeof(pipe_config));
9050
9051                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9052                               crtc->base.base.id);
9053
9054                 WARN(crtc->active && !crtc->base.enabled,
9055                      "active crtc, but not enabled in sw tracking\n");
9056
9057                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9058                                     base.head) {
9059                         if (encoder->base.crtc != &crtc->base)
9060                                 continue;
9061                         enabled = true;
9062                         if (encoder->connectors_active)
9063                                 active = true;
9064                 }
9065
9066                 WARN(active != crtc->active,
9067                      "crtc's computed active state doesn't match tracked active state "
9068                      "(expected %i, found %i)\n", active, crtc->active);
9069                 WARN(enabled != crtc->base.enabled,
9070                      "crtc's computed enabled state doesn't match tracked enabled state "
9071                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9072
9073                 active = dev_priv->display.get_pipe_config(crtc,
9074                                                            &pipe_config);
9075
9076                 /* hw state is inconsistent with the pipe A quirk */
9077                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9078                         active = crtc->active;
9079
9080                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9081                                     base.head) {
9082                         enum pipe pipe;
9083                         if (encoder->base.crtc != &crtc->base)
9084                                 continue;
9085                         if (encoder->get_config &&
9086                             encoder->get_hw_state(encoder, &pipe))
9087                                 encoder->get_config(encoder, &pipe_config);
9088                 }
9089
9090                 WARN(crtc->active != active,
9091                      "crtc active state doesn't match with hw state "
9092                      "(expected %i, found %i)\n", crtc->active, active);
9093
9094                 if (active &&
9095                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9096                         WARN(1, "pipe state doesn't match!\n");
9097                         intel_dump_pipe_config(crtc, &pipe_config,
9098                                                "[hw state]");
9099                         intel_dump_pipe_config(crtc, &crtc->config,
9100                                                "[sw state]");
9101                 }
9102         }
9103 }
9104
9105 static void
9106 check_shared_dpll_state(struct drm_device *dev)
9107 {
9108         drm_i915_private_t *dev_priv = dev->dev_private;
9109         struct intel_crtc *crtc;
9110         struct intel_dpll_hw_state dpll_hw_state;
9111         int i;
9112
9113         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9114                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9115                 int enabled_crtcs = 0, active_crtcs = 0;
9116                 bool active;
9117
9118                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9119
9120                 DRM_DEBUG_KMS("%s\n", pll->name);
9121
9122                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9123
9124                 WARN(pll->active > pll->refcount,
9125                      "more active pll users than references: %i vs %i\n",
9126                      pll->active, pll->refcount);
9127                 WARN(pll->active && !pll->on,
9128                      "pll in active use but not on in sw tracking\n");
9129                 WARN(pll->on && !pll->active,
9130                      "pll in on but not on in use in sw tracking\n");
9131                 WARN(pll->on != active,
9132                      "pll on state mismatch (expected %i, found %i)\n",
9133                      pll->on, active);
9134
9135                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9136                                     base.head) {
9137                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9138                                 enabled_crtcs++;
9139                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9140                                 active_crtcs++;
9141                 }
9142                 WARN(pll->active != active_crtcs,
9143                      "pll active crtcs mismatch (expected %i, found %i)\n",
9144                      pll->active, active_crtcs);
9145                 WARN(pll->refcount != enabled_crtcs,
9146                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9147                      pll->refcount, enabled_crtcs);
9148
9149                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9150                                        sizeof(dpll_hw_state)),
9151                      "pll hw state mismatch\n");
9152         }
9153 }
9154
9155 void
9156 intel_modeset_check_state(struct drm_device *dev)
9157 {
9158         check_connector_state(dev);
9159         check_encoder_state(dev);
9160         check_crtc_state(dev);
9161         check_shared_dpll_state(dev);
9162 }
9163
9164 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9165                                      int dotclock)
9166 {
9167         /*
9168          * FDI already provided one idea for the dotclock.
9169          * Yell if the encoder disagrees.
9170          */
9171         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9172              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9173              pipe_config->adjusted_mode.crtc_clock, dotclock);
9174 }
9175
9176 static int __intel_set_mode(struct drm_crtc *crtc,
9177                             struct drm_display_mode *mode,
9178                             int x, int y, struct drm_framebuffer *fb)
9179 {
9180         struct drm_device *dev = crtc->dev;
9181         drm_i915_private_t *dev_priv = dev->dev_private;
9182         struct drm_display_mode *saved_mode, *saved_hwmode;
9183         struct intel_crtc_config *pipe_config = NULL;
9184         struct intel_crtc *intel_crtc;
9185         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9186         int ret = 0;
9187
9188         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9189         if (!saved_mode)
9190                 return -ENOMEM;
9191         saved_hwmode = saved_mode + 1;
9192
9193         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9194                                      &prepare_pipes, &disable_pipes);
9195
9196         *saved_hwmode = crtc->hwmode;
9197         *saved_mode = crtc->mode;
9198
9199         /* Hack: Because we don't (yet) support global modeset on multiple
9200          * crtcs, we don't keep track of the new mode for more than one crtc.
9201          * Hence simply check whether any bit is set in modeset_pipes in all the
9202          * pieces of code that are not yet converted to deal with mutliple crtcs
9203          * changing their mode at the same time. */
9204         if (modeset_pipes) {
9205                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9206                 if (IS_ERR(pipe_config)) {
9207                         ret = PTR_ERR(pipe_config);
9208                         pipe_config = NULL;
9209
9210                         goto out;
9211                 }
9212                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9213                                        "[modeset]");
9214         }
9215
9216         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9217                 intel_crtc_disable(&intel_crtc->base);
9218
9219         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9220                 if (intel_crtc->base.enabled)
9221                         dev_priv->display.crtc_disable(&intel_crtc->base);
9222         }
9223
9224         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9225          * to set it here already despite that we pass it down the callchain.
9226          */
9227         if (modeset_pipes) {
9228                 crtc->mode = *mode;
9229                 /* mode_set/enable/disable functions rely on a correct pipe
9230                  * config. */
9231                 to_intel_crtc(crtc)->config = *pipe_config;
9232         }
9233
9234         /* Only after disabling all output pipelines that will be changed can we
9235          * update the the output configuration. */
9236         intel_modeset_update_state(dev, prepare_pipes);
9237
9238         if (dev_priv->display.modeset_global_resources)
9239                 dev_priv->display.modeset_global_resources(dev);
9240
9241         /* Set up the DPLL and any encoders state that needs to adjust or depend
9242          * on the DPLL.
9243          */
9244         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9245                 ret = intel_crtc_mode_set(&intel_crtc->base,
9246                                           x, y, fb);
9247                 if (ret)
9248                         goto done;
9249         }
9250
9251         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9252         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9253                 dev_priv->display.crtc_enable(&intel_crtc->base);
9254
9255         if (modeset_pipes) {
9256                 /* Store real post-adjustment hardware mode. */
9257                 crtc->hwmode = pipe_config->adjusted_mode;
9258
9259                 /* Calculate and store various constants which
9260                  * are later needed by vblank and swap-completion
9261                  * timestamping. They are derived from true hwmode.
9262                  */
9263                 drm_calc_timestamping_constants(crtc);
9264         }
9265
9266         /* FIXME: add subpixel order */
9267 done:
9268         if (ret && crtc->enabled) {
9269                 crtc->hwmode = *saved_hwmode;
9270                 crtc->mode = *saved_mode;
9271         }
9272
9273 out:
9274         kfree(pipe_config);
9275         kfree(saved_mode);
9276         return ret;
9277 }
9278
9279 static int intel_set_mode(struct drm_crtc *crtc,
9280                           struct drm_display_mode *mode,
9281                           int x, int y, struct drm_framebuffer *fb)
9282 {
9283         int ret;
9284
9285         ret = __intel_set_mode(crtc, mode, x, y, fb);
9286
9287         if (ret == 0)
9288                 intel_modeset_check_state(crtc->dev);
9289
9290         return ret;
9291 }
9292
9293 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9294 {
9295         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9296 }
9297
9298 #undef for_each_intel_crtc_masked
9299
9300 static void intel_set_config_free(struct intel_set_config *config)
9301 {
9302         if (!config)
9303                 return;
9304
9305         kfree(config->save_connector_encoders);
9306         kfree(config->save_encoder_crtcs);
9307         kfree(config);
9308 }
9309
9310 static int intel_set_config_save_state(struct drm_device *dev,
9311                                        struct intel_set_config *config)
9312 {
9313         struct drm_encoder *encoder;
9314         struct drm_connector *connector;
9315         int count;
9316
9317         config->save_encoder_crtcs =
9318                 kcalloc(dev->mode_config.num_encoder,
9319                         sizeof(struct drm_crtc *), GFP_KERNEL);
9320         if (!config->save_encoder_crtcs)
9321                 return -ENOMEM;
9322
9323         config->save_connector_encoders =
9324                 kcalloc(dev->mode_config.num_connector,
9325                         sizeof(struct drm_encoder *), GFP_KERNEL);
9326         if (!config->save_connector_encoders)
9327                 return -ENOMEM;
9328
9329         /* Copy data. Note that driver private data is not affected.
9330          * Should anything bad happen only the expected state is
9331          * restored, not the drivers personal bookkeeping.
9332          */
9333         count = 0;
9334         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9335                 config->save_encoder_crtcs[count++] = encoder->crtc;
9336         }
9337
9338         count = 0;
9339         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9340                 config->save_connector_encoders[count++] = connector->encoder;
9341         }
9342
9343         return 0;
9344 }
9345
9346 static void intel_set_config_restore_state(struct drm_device *dev,
9347                                            struct intel_set_config *config)
9348 {
9349         struct intel_encoder *encoder;
9350         struct intel_connector *connector;
9351         int count;
9352
9353         count = 0;
9354         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9355                 encoder->new_crtc =
9356                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9357         }
9358
9359         count = 0;
9360         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9361                 connector->new_encoder =
9362                         to_intel_encoder(config->save_connector_encoders[count++]);
9363         }
9364 }
9365
9366 static bool
9367 is_crtc_connector_off(struct drm_mode_set *set)
9368 {
9369         int i;
9370
9371         if (set->num_connectors == 0)
9372                 return false;
9373
9374         if (WARN_ON(set->connectors == NULL))
9375                 return false;
9376
9377         for (i = 0; i < set->num_connectors; i++)
9378                 if (set->connectors[i]->encoder &&
9379                     set->connectors[i]->encoder->crtc == set->crtc &&
9380                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9381                         return true;
9382
9383         return false;
9384 }
9385
9386 static void
9387 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9388                                       struct intel_set_config *config)
9389 {
9390
9391         /* We should be able to check here if the fb has the same properties
9392          * and then just flip_or_move it */
9393         if (is_crtc_connector_off(set)) {
9394                 config->mode_changed = true;
9395         } else if (set->crtc->fb != set->fb) {
9396                 /* If we have no fb then treat it as a full mode set */
9397                 if (set->crtc->fb == NULL) {
9398                         struct intel_crtc *intel_crtc =
9399                                 to_intel_crtc(set->crtc);
9400
9401                         if (intel_crtc->active && i915_fastboot) {
9402                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9403                                 config->fb_changed = true;
9404                         } else {
9405                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9406                                 config->mode_changed = true;
9407                         }
9408                 } else if (set->fb == NULL) {
9409                         config->mode_changed = true;
9410                 } else if (set->fb->pixel_format !=
9411                            set->crtc->fb->pixel_format) {
9412                         config->mode_changed = true;
9413                 } else {
9414                         config->fb_changed = true;
9415                 }
9416         }
9417
9418         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9419                 config->fb_changed = true;
9420
9421         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9422                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9423                 drm_mode_debug_printmodeline(&set->crtc->mode);
9424                 drm_mode_debug_printmodeline(set->mode);
9425                 config->mode_changed = true;
9426         }
9427
9428         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9429                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9430 }
9431
9432 static int
9433 intel_modeset_stage_output_state(struct drm_device *dev,
9434                                  struct drm_mode_set *set,
9435                                  struct intel_set_config *config)
9436 {
9437         struct drm_crtc *new_crtc;
9438         struct intel_connector *connector;
9439         struct intel_encoder *encoder;
9440         int ro;
9441
9442         /* The upper layers ensure that we either disable a crtc or have a list
9443          * of connectors. For paranoia, double-check this. */
9444         WARN_ON(!set->fb && (set->num_connectors != 0));
9445         WARN_ON(set->fb && (set->num_connectors == 0));
9446
9447         list_for_each_entry(connector, &dev->mode_config.connector_list,
9448                             base.head) {
9449                 /* Otherwise traverse passed in connector list and get encoders
9450                  * for them. */
9451                 for (ro = 0; ro < set->num_connectors; ro++) {
9452                         if (set->connectors[ro] == &connector->base) {
9453                                 connector->new_encoder = connector->encoder;
9454                                 break;
9455                         }
9456                 }
9457
9458                 /* If we disable the crtc, disable all its connectors. Also, if
9459                  * the connector is on the changing crtc but not on the new
9460                  * connector list, disable it. */
9461                 if ((!set->fb || ro == set->num_connectors) &&
9462                     connector->base.encoder &&
9463                     connector->base.encoder->crtc == set->crtc) {
9464                         connector->new_encoder = NULL;
9465
9466                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9467                                 connector->base.base.id,
9468                                 drm_get_connector_name(&connector->base));
9469                 }
9470
9471
9472                 if (&connector->new_encoder->base != connector->base.encoder) {
9473                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9474                         config->mode_changed = true;
9475                 }
9476         }
9477         /* connector->new_encoder is now updated for all connectors. */
9478
9479         /* Update crtc of enabled connectors. */
9480         list_for_each_entry(connector, &dev->mode_config.connector_list,
9481                             base.head) {
9482                 if (!connector->new_encoder)
9483                         continue;
9484
9485                 new_crtc = connector->new_encoder->base.crtc;
9486
9487                 for (ro = 0; ro < set->num_connectors; ro++) {
9488                         if (set->connectors[ro] == &connector->base)
9489                                 new_crtc = set->crtc;
9490                 }
9491
9492                 /* Make sure the new CRTC will work with the encoder */
9493                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9494                                            new_crtc)) {
9495                         return -EINVAL;
9496                 }
9497                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9498
9499                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9500                         connector->base.base.id,
9501                         drm_get_connector_name(&connector->base),
9502                         new_crtc->base.id);
9503         }
9504
9505         /* Check for any encoders that needs to be disabled. */
9506         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9507                             base.head) {
9508                 list_for_each_entry(connector,
9509                                     &dev->mode_config.connector_list,
9510                                     base.head) {
9511                         if (connector->new_encoder == encoder) {
9512                                 WARN_ON(!connector->new_encoder->new_crtc);
9513
9514                                 goto next_encoder;
9515                         }
9516                 }
9517                 encoder->new_crtc = NULL;
9518 next_encoder:
9519                 /* Only now check for crtc changes so we don't miss encoders
9520                  * that will be disabled. */
9521                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9522                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9523                         config->mode_changed = true;
9524                 }
9525         }
9526         /* Now we've also updated encoder->new_crtc for all encoders. */
9527
9528         return 0;
9529 }
9530
9531 static int intel_crtc_set_config(struct drm_mode_set *set)
9532 {
9533         struct drm_device *dev;
9534         struct drm_mode_set save_set;
9535         struct intel_set_config *config;
9536         int ret;
9537
9538         BUG_ON(!set);
9539         BUG_ON(!set->crtc);
9540         BUG_ON(!set->crtc->helper_private);
9541
9542         /* Enforce sane interface api - has been abused by the fb helper. */
9543         BUG_ON(!set->mode && set->fb);
9544         BUG_ON(set->fb && set->num_connectors == 0);
9545
9546         if (set->fb) {
9547                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9548                                 set->crtc->base.id, set->fb->base.id,
9549                                 (int)set->num_connectors, set->x, set->y);
9550         } else {
9551                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9552         }
9553
9554         dev = set->crtc->dev;
9555
9556         ret = -ENOMEM;
9557         config = kzalloc(sizeof(*config), GFP_KERNEL);
9558         if (!config)
9559                 goto out_config;
9560
9561         ret = intel_set_config_save_state(dev, config);
9562         if (ret)
9563                 goto out_config;
9564
9565         save_set.crtc = set->crtc;
9566         save_set.mode = &set->crtc->mode;
9567         save_set.x = set->crtc->x;
9568         save_set.y = set->crtc->y;
9569         save_set.fb = set->crtc->fb;
9570
9571         /* Compute whether we need a full modeset, only an fb base update or no
9572          * change at all. In the future we might also check whether only the
9573          * mode changed, e.g. for LVDS where we only change the panel fitter in
9574          * such cases. */
9575         intel_set_config_compute_mode_changes(set, config);
9576
9577         ret = intel_modeset_stage_output_state(dev, set, config);
9578         if (ret)
9579                 goto fail;
9580
9581         if (config->mode_changed) {
9582                 ret = intel_set_mode(set->crtc, set->mode,
9583                                      set->x, set->y, set->fb);
9584         } else if (config->fb_changed) {
9585                 intel_crtc_wait_for_pending_flips(set->crtc);
9586
9587                 ret = intel_pipe_set_base(set->crtc,
9588                                           set->x, set->y, set->fb);
9589         }
9590
9591         if (ret) {
9592                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9593                               set->crtc->base.id, ret);
9594 fail:
9595                 intel_set_config_restore_state(dev, config);
9596
9597                 /* Try to restore the config */
9598                 if (config->mode_changed &&
9599                     intel_set_mode(save_set.crtc, save_set.mode,
9600                                    save_set.x, save_set.y, save_set.fb))
9601                         DRM_ERROR("failed to restore config after modeset failure\n");
9602         }
9603
9604 out_config:
9605         intel_set_config_free(config);
9606         return ret;
9607 }
9608
9609 static const struct drm_crtc_funcs intel_crtc_funcs = {
9610         .cursor_set = intel_crtc_cursor_set,
9611         .cursor_move = intel_crtc_cursor_move,
9612         .gamma_set = intel_crtc_gamma_set,
9613         .set_config = intel_crtc_set_config,
9614         .destroy = intel_crtc_destroy,
9615         .page_flip = intel_crtc_page_flip,
9616 };
9617
9618 static void intel_cpu_pll_init(struct drm_device *dev)
9619 {
9620         if (HAS_DDI(dev))
9621                 intel_ddi_pll_init(dev);
9622 }
9623
9624 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9625                                       struct intel_shared_dpll *pll,
9626                                       struct intel_dpll_hw_state *hw_state)
9627 {
9628         uint32_t val;
9629
9630         val = I915_READ(PCH_DPLL(pll->id));
9631         hw_state->dpll = val;
9632         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9633         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9634
9635         return val & DPLL_VCO_ENABLE;
9636 }
9637
9638 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9639                                   struct intel_shared_dpll *pll)
9640 {
9641         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9642         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9643 }
9644
9645 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9646                                 struct intel_shared_dpll *pll)
9647 {
9648         /* PCH refclock must be enabled first */
9649         assert_pch_refclk_enabled(dev_priv);
9650
9651         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9652
9653         /* Wait for the clocks to stabilize. */
9654         POSTING_READ(PCH_DPLL(pll->id));
9655         udelay(150);
9656
9657         /* The pixel multiplier can only be updated once the
9658          * DPLL is enabled and the clocks are stable.
9659          *
9660          * So write it again.
9661          */
9662         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9663         POSTING_READ(PCH_DPLL(pll->id));
9664         udelay(200);
9665 }
9666
9667 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9668                                  struct intel_shared_dpll *pll)
9669 {
9670         struct drm_device *dev = dev_priv->dev;
9671         struct intel_crtc *crtc;
9672
9673         /* Make sure no transcoder isn't still depending on us. */
9674         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9675                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9676                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9677         }
9678
9679         I915_WRITE(PCH_DPLL(pll->id), 0);
9680         POSTING_READ(PCH_DPLL(pll->id));
9681         udelay(200);
9682 }
9683
9684 static char *ibx_pch_dpll_names[] = {
9685         "PCH DPLL A",
9686         "PCH DPLL B",
9687 };
9688
9689 static void ibx_pch_dpll_init(struct drm_device *dev)
9690 {
9691         struct drm_i915_private *dev_priv = dev->dev_private;
9692         int i;
9693
9694         dev_priv->num_shared_dpll = 2;
9695
9696         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9697                 dev_priv->shared_dplls[i].id = i;
9698                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9699                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9700                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9701                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9702                 dev_priv->shared_dplls[i].get_hw_state =
9703                         ibx_pch_dpll_get_hw_state;
9704         }
9705 }
9706
9707 static void intel_shared_dpll_init(struct drm_device *dev)
9708 {
9709         struct drm_i915_private *dev_priv = dev->dev_private;
9710
9711         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9712                 ibx_pch_dpll_init(dev);
9713         else
9714                 dev_priv->num_shared_dpll = 0;
9715
9716         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9717         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9718                       dev_priv->num_shared_dpll);
9719 }
9720
9721 static void intel_crtc_init(struct drm_device *dev, int pipe)
9722 {
9723         drm_i915_private_t *dev_priv = dev->dev_private;
9724         struct intel_crtc *intel_crtc;
9725         int i;
9726
9727         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9728         if (intel_crtc == NULL)
9729                 return;
9730
9731         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9732
9733         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9734         for (i = 0; i < 256; i++) {
9735                 intel_crtc->lut_r[i] = i;
9736                 intel_crtc->lut_g[i] = i;
9737                 intel_crtc->lut_b[i] = i;
9738         }
9739
9740         /* Swap pipes & planes for FBC on pre-965 */
9741         intel_crtc->pipe = pipe;
9742         intel_crtc->plane = pipe;
9743         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9744                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9745                 intel_crtc->plane = !pipe;
9746         }
9747
9748         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9749                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9750         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9751         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9752
9753         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9754 }
9755
9756 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9757                                 struct drm_file *file)
9758 {
9759         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9760         struct drm_mode_object *drmmode_obj;
9761         struct intel_crtc *crtc;
9762
9763         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9764                 return -ENODEV;
9765
9766         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9767                         DRM_MODE_OBJECT_CRTC);
9768
9769         if (!drmmode_obj) {
9770                 DRM_ERROR("no such CRTC id\n");
9771                 return -EINVAL;
9772         }
9773
9774         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9775         pipe_from_crtc_id->pipe = crtc->pipe;
9776
9777         return 0;
9778 }
9779
9780 static int intel_encoder_clones(struct intel_encoder *encoder)
9781 {
9782         struct drm_device *dev = encoder->base.dev;
9783         struct intel_encoder *source_encoder;
9784         int index_mask = 0;
9785         int entry = 0;
9786
9787         list_for_each_entry(source_encoder,
9788                             &dev->mode_config.encoder_list, base.head) {
9789
9790                 if (encoder == source_encoder)
9791                         index_mask |= (1 << entry);
9792
9793                 /* Intel hw has only one MUX where enocoders could be cloned. */
9794                 if (encoder->cloneable && source_encoder->cloneable)
9795                         index_mask |= (1 << entry);
9796
9797                 entry++;
9798         }
9799
9800         return index_mask;
9801 }
9802
9803 static bool has_edp_a(struct drm_device *dev)
9804 {
9805         struct drm_i915_private *dev_priv = dev->dev_private;
9806
9807         if (!IS_MOBILE(dev))
9808                 return false;
9809
9810         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9811                 return false;
9812
9813         if (IS_GEN5(dev) &&
9814             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9815                 return false;
9816
9817         return true;
9818 }
9819
9820 static void intel_setup_outputs(struct drm_device *dev)
9821 {
9822         struct drm_i915_private *dev_priv = dev->dev_private;
9823         struct intel_encoder *encoder;
9824         bool dpd_is_edp = false;
9825
9826         intel_lvds_init(dev);
9827
9828         if (!IS_ULT(dev))
9829                 intel_crt_init(dev);
9830
9831         if (HAS_DDI(dev)) {
9832                 int found;
9833
9834                 /* Haswell uses DDI functions to detect digital outputs */
9835                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9836                 /* DDI A only supports eDP */
9837                 if (found)
9838                         intel_ddi_init(dev, PORT_A);
9839
9840                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9841                  * register */
9842                 found = I915_READ(SFUSE_STRAP);
9843
9844                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9845                         intel_ddi_init(dev, PORT_B);
9846                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9847                         intel_ddi_init(dev, PORT_C);
9848                 if (found & SFUSE_STRAP_DDID_DETECTED)
9849                         intel_ddi_init(dev, PORT_D);
9850         } else if (HAS_PCH_SPLIT(dev)) {
9851                 int found;
9852                 dpd_is_edp = intel_dpd_is_edp(dev);
9853
9854                 if (has_edp_a(dev))
9855                         intel_dp_init(dev, DP_A, PORT_A);
9856
9857                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9858                         /* PCH SDVOB multiplex with HDMIB */
9859                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9860                         if (!found)
9861                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9862                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9863                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9864                 }
9865
9866                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9867                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9868
9869                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9870                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9871
9872                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9873                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9874
9875                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9876                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9877         } else if (IS_VALLEYVIEW(dev)) {
9878                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9879                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9880                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9881                                         PORT_C);
9882                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9883                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9884                                               PORT_C);
9885                 }
9886
9887                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9888                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9889                                         PORT_B);
9890                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9891                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9892                 }
9893
9894                 intel_dsi_init(dev);
9895         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9896                 bool found = false;
9897
9898                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9899                         DRM_DEBUG_KMS("probing SDVOB\n");
9900                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9901                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9902                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9903                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9904                         }
9905
9906                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9907                                 intel_dp_init(dev, DP_B, PORT_B);
9908                 }
9909
9910                 /* Before G4X SDVOC doesn't have its own detect register */
9911
9912                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9913                         DRM_DEBUG_KMS("probing SDVOC\n");
9914                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9915                 }
9916
9917                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9918
9919                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9920                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9921                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9922                         }
9923                         if (SUPPORTS_INTEGRATED_DP(dev))
9924                                 intel_dp_init(dev, DP_C, PORT_C);
9925                 }
9926
9927                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9928                     (I915_READ(DP_D) & DP_DETECTED))
9929                         intel_dp_init(dev, DP_D, PORT_D);
9930         } else if (IS_GEN2(dev))
9931                 intel_dvo_init(dev);
9932
9933         if (SUPPORTS_TV(dev))
9934                 intel_tv_init(dev);
9935
9936         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9937                 encoder->base.possible_crtcs = encoder->crtc_mask;
9938                 encoder->base.possible_clones =
9939                         intel_encoder_clones(encoder);
9940         }
9941
9942         intel_init_pch_refclk(dev);
9943
9944         drm_helper_move_panel_connectors_to_head(dev);
9945 }
9946
9947 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9948 {
9949         drm_framebuffer_cleanup(&fb->base);
9950         drm_gem_object_unreference_unlocked(&fb->obj->base);
9951 }
9952
9953 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9954 {
9955         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9956
9957         intel_framebuffer_fini(intel_fb);
9958         kfree(intel_fb);
9959 }
9960
9961 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9962                                                 struct drm_file *file,
9963                                                 unsigned int *handle)
9964 {
9965         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9966         struct drm_i915_gem_object *obj = intel_fb->obj;
9967
9968         return drm_gem_handle_create(file, &obj->base, handle);
9969 }
9970
9971 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9972         .destroy = intel_user_framebuffer_destroy,
9973         .create_handle = intel_user_framebuffer_create_handle,
9974 };
9975
9976 int intel_framebuffer_init(struct drm_device *dev,
9977                            struct intel_framebuffer *intel_fb,
9978                            struct drm_mode_fb_cmd2 *mode_cmd,
9979                            struct drm_i915_gem_object *obj)
9980 {
9981         int pitch_limit;
9982         int ret;
9983
9984         if (obj->tiling_mode == I915_TILING_Y) {
9985                 DRM_DEBUG("hardware does not support tiling Y\n");
9986                 return -EINVAL;
9987         }
9988
9989         if (mode_cmd->pitches[0] & 63) {
9990                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9991                           mode_cmd->pitches[0]);
9992                 return -EINVAL;
9993         }
9994
9995         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9996                 pitch_limit = 32*1024;
9997         } else if (INTEL_INFO(dev)->gen >= 4) {
9998                 if (obj->tiling_mode)
9999                         pitch_limit = 16*1024;
10000                 else
10001                         pitch_limit = 32*1024;
10002         } else if (INTEL_INFO(dev)->gen >= 3) {
10003                 if (obj->tiling_mode)
10004                         pitch_limit = 8*1024;
10005                 else
10006                         pitch_limit = 16*1024;
10007         } else
10008                 /* XXX DSPC is limited to 4k tiled */
10009                 pitch_limit = 8*1024;
10010
10011         if (mode_cmd->pitches[0] > pitch_limit) {
10012                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10013                           obj->tiling_mode ? "tiled" : "linear",
10014                           mode_cmd->pitches[0], pitch_limit);
10015                 return -EINVAL;
10016         }
10017
10018         if (obj->tiling_mode != I915_TILING_NONE &&
10019             mode_cmd->pitches[0] != obj->stride) {
10020                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10021                           mode_cmd->pitches[0], obj->stride);
10022                 return -EINVAL;
10023         }
10024
10025         /* Reject formats not supported by any plane early. */
10026         switch (mode_cmd->pixel_format) {
10027         case DRM_FORMAT_C8:
10028         case DRM_FORMAT_RGB565:
10029         case DRM_FORMAT_XRGB8888:
10030         case DRM_FORMAT_ARGB8888:
10031                 break;
10032         case DRM_FORMAT_XRGB1555:
10033         case DRM_FORMAT_ARGB1555:
10034                 if (INTEL_INFO(dev)->gen > 3) {
10035                         DRM_DEBUG("unsupported pixel format: %s\n",
10036                                   drm_get_format_name(mode_cmd->pixel_format));
10037                         return -EINVAL;
10038                 }
10039                 break;
10040         case DRM_FORMAT_XBGR8888:
10041         case DRM_FORMAT_ABGR8888:
10042         case DRM_FORMAT_XRGB2101010:
10043         case DRM_FORMAT_ARGB2101010:
10044         case DRM_FORMAT_XBGR2101010:
10045         case DRM_FORMAT_ABGR2101010:
10046                 if (INTEL_INFO(dev)->gen < 4) {
10047                         DRM_DEBUG("unsupported pixel format: %s\n",
10048                                   drm_get_format_name(mode_cmd->pixel_format));
10049                         return -EINVAL;
10050                 }
10051                 break;
10052         case DRM_FORMAT_YUYV:
10053         case DRM_FORMAT_UYVY:
10054         case DRM_FORMAT_YVYU:
10055         case DRM_FORMAT_VYUY:
10056                 if (INTEL_INFO(dev)->gen < 5) {
10057                         DRM_DEBUG("unsupported pixel format: %s\n",
10058                                   drm_get_format_name(mode_cmd->pixel_format));
10059                         return -EINVAL;
10060                 }
10061                 break;
10062         default:
10063                 DRM_DEBUG("unsupported pixel format: %s\n",
10064                           drm_get_format_name(mode_cmd->pixel_format));
10065                 return -EINVAL;
10066         }
10067
10068         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10069         if (mode_cmd->offsets[0] != 0)
10070                 return -EINVAL;
10071
10072         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10073         intel_fb->obj = obj;
10074
10075         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10076         if (ret) {
10077                 DRM_ERROR("framebuffer init failed %d\n", ret);
10078                 return ret;
10079         }
10080
10081         return 0;
10082 }
10083
10084 static struct drm_framebuffer *
10085 intel_user_framebuffer_create(struct drm_device *dev,
10086                               struct drm_file *filp,
10087                               struct drm_mode_fb_cmd2 *mode_cmd)
10088 {
10089         struct drm_i915_gem_object *obj;
10090
10091         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10092                                                 mode_cmd->handles[0]));
10093         if (&obj->base == NULL)
10094                 return ERR_PTR(-ENOENT);
10095
10096         return intel_framebuffer_create(dev, mode_cmd, obj);
10097 }
10098
10099 static const struct drm_mode_config_funcs intel_mode_funcs = {
10100         .fb_create = intel_user_framebuffer_create,
10101         .output_poll_changed = intel_fb_output_poll_changed,
10102 };
10103
10104 /* Set up chip specific display functions */
10105 static void intel_init_display(struct drm_device *dev)
10106 {
10107         struct drm_i915_private *dev_priv = dev->dev_private;
10108
10109         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10110                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10111         else if (IS_VALLEYVIEW(dev))
10112                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10113         else if (IS_PINEVIEW(dev))
10114                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10115         else
10116                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10117
10118         if (HAS_DDI(dev)) {
10119                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10120                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10121                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10122                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10123                 dev_priv->display.off = haswell_crtc_off;
10124                 dev_priv->display.update_plane = ironlake_update_plane;
10125         } else if (HAS_PCH_SPLIT(dev)) {
10126                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10127                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10128                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10129                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10130                 dev_priv->display.off = ironlake_crtc_off;
10131                 dev_priv->display.update_plane = ironlake_update_plane;
10132         } else if (IS_VALLEYVIEW(dev)) {
10133                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10134                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10135                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10136                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10137                 dev_priv->display.off = i9xx_crtc_off;
10138                 dev_priv->display.update_plane = i9xx_update_plane;
10139         } else {
10140                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10141                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10142                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10143                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10144                 dev_priv->display.off = i9xx_crtc_off;
10145                 dev_priv->display.update_plane = i9xx_update_plane;
10146         }
10147
10148         /* Returns the core display clock speed */
10149         if (IS_VALLEYVIEW(dev))
10150                 dev_priv->display.get_display_clock_speed =
10151                         valleyview_get_display_clock_speed;
10152         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10153                 dev_priv->display.get_display_clock_speed =
10154                         i945_get_display_clock_speed;
10155         else if (IS_I915G(dev))
10156                 dev_priv->display.get_display_clock_speed =
10157                         i915_get_display_clock_speed;
10158         else if (IS_I945GM(dev) || IS_845G(dev))
10159                 dev_priv->display.get_display_clock_speed =
10160                         i9xx_misc_get_display_clock_speed;
10161         else if (IS_PINEVIEW(dev))
10162                 dev_priv->display.get_display_clock_speed =
10163                         pnv_get_display_clock_speed;
10164         else if (IS_I915GM(dev))
10165                 dev_priv->display.get_display_clock_speed =
10166                         i915gm_get_display_clock_speed;
10167         else if (IS_I865G(dev))
10168                 dev_priv->display.get_display_clock_speed =
10169                         i865_get_display_clock_speed;
10170         else if (IS_I85X(dev))
10171                 dev_priv->display.get_display_clock_speed =
10172                         i855_get_display_clock_speed;
10173         else /* 852, 830 */
10174                 dev_priv->display.get_display_clock_speed =
10175                         i830_get_display_clock_speed;
10176
10177         if (HAS_PCH_SPLIT(dev)) {
10178                 if (IS_GEN5(dev)) {
10179                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10180                         dev_priv->display.write_eld = ironlake_write_eld;
10181                 } else if (IS_GEN6(dev)) {
10182                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10183                         dev_priv->display.write_eld = ironlake_write_eld;
10184                 } else if (IS_IVYBRIDGE(dev)) {
10185                         /* FIXME: detect B0+ stepping and use auto training */
10186                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10187                         dev_priv->display.write_eld = ironlake_write_eld;
10188                         dev_priv->display.modeset_global_resources =
10189                                 ivb_modeset_global_resources;
10190                 } else if (IS_HASWELL(dev)) {
10191                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10192                         dev_priv->display.write_eld = haswell_write_eld;
10193                         dev_priv->display.modeset_global_resources =
10194                                 haswell_modeset_global_resources;
10195                 }
10196         } else if (IS_G4X(dev)) {
10197                 dev_priv->display.write_eld = g4x_write_eld;
10198         }
10199
10200         /* Default just returns -ENODEV to indicate unsupported */
10201         dev_priv->display.queue_flip = intel_default_queue_flip;
10202
10203         switch (INTEL_INFO(dev)->gen) {
10204         case 2:
10205                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10206                 break;
10207
10208         case 3:
10209                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10210                 break;
10211
10212         case 4:
10213         case 5:
10214                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10215                 break;
10216
10217         case 6:
10218                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10219                 break;
10220         case 7:
10221                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10222                 break;
10223         }
10224 }
10225
10226 /*
10227  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10228  * resume, or other times.  This quirk makes sure that's the case for
10229  * affected systems.
10230  */
10231 static void quirk_pipea_force(struct drm_device *dev)
10232 {
10233         struct drm_i915_private *dev_priv = dev->dev_private;
10234
10235         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10236         DRM_INFO("applying pipe a force quirk\n");
10237 }
10238
10239 /*
10240  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10241  */
10242 static void quirk_ssc_force_disable(struct drm_device *dev)
10243 {
10244         struct drm_i915_private *dev_priv = dev->dev_private;
10245         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10246         DRM_INFO("applying lvds SSC disable quirk\n");
10247 }
10248
10249 /*
10250  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10251  * brightness value
10252  */
10253 static void quirk_invert_brightness(struct drm_device *dev)
10254 {
10255         struct drm_i915_private *dev_priv = dev->dev_private;
10256         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10257         DRM_INFO("applying inverted panel brightness quirk\n");
10258 }
10259
10260 /*
10261  * Some machines (Dell XPS13) suffer broken backlight controls if
10262  * BLM_PCH_PWM_ENABLE is set.
10263  */
10264 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10265 {
10266         struct drm_i915_private *dev_priv = dev->dev_private;
10267         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10268         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10269 }
10270
10271 struct intel_quirk {
10272         int device;
10273         int subsystem_vendor;
10274         int subsystem_device;
10275         void (*hook)(struct drm_device *dev);
10276 };
10277
10278 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10279 struct intel_dmi_quirk {
10280         void (*hook)(struct drm_device *dev);
10281         const struct dmi_system_id (*dmi_id_list)[];
10282 };
10283
10284 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10285 {
10286         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10287         return 1;
10288 }
10289
10290 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10291         {
10292                 .dmi_id_list = &(const struct dmi_system_id[]) {
10293                         {
10294                                 .callback = intel_dmi_reverse_brightness,
10295                                 .ident = "NCR Corporation",
10296                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10297                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10298                                 },
10299                         },
10300                         { }  /* terminating entry */
10301                 },
10302                 .hook = quirk_invert_brightness,
10303         },
10304 };
10305
10306 static struct intel_quirk intel_quirks[] = {
10307         /* HP Mini needs pipe A force quirk (LP: #322104) */
10308         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10309
10310         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10311         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10312
10313         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10314         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10315
10316         /* 830 needs to leave pipe A & dpll A up */
10317         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10318
10319         /* Lenovo U160 cannot use SSC on LVDS */
10320         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10321
10322         /* Sony Vaio Y cannot use SSC on LVDS */
10323         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10324
10325         /*
10326          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10327          * seem to use inverted backlight PWM.
10328          */
10329         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10330
10331         /* Dell XPS13 HD Sandy Bridge */
10332         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10333         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10334         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10335 };
10336
10337 static void intel_init_quirks(struct drm_device *dev)
10338 {
10339         struct pci_dev *d = dev->pdev;
10340         int i;
10341
10342         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10343                 struct intel_quirk *q = &intel_quirks[i];
10344
10345                 if (d->device == q->device &&
10346                     (d->subsystem_vendor == q->subsystem_vendor ||
10347                      q->subsystem_vendor == PCI_ANY_ID) &&
10348                     (d->subsystem_device == q->subsystem_device ||
10349                      q->subsystem_device == PCI_ANY_ID))
10350                         q->hook(dev);
10351         }
10352         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10353                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10354                         intel_dmi_quirks[i].hook(dev);
10355         }
10356 }
10357
10358 /* Disable the VGA plane that we never use */
10359 static void i915_disable_vga(struct drm_device *dev)
10360 {
10361         struct drm_i915_private *dev_priv = dev->dev_private;
10362         u8 sr1;
10363         u32 vga_reg = i915_vgacntrl_reg(dev);
10364
10365         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10366         outb(SR01, VGA_SR_INDEX);
10367         sr1 = inb(VGA_SR_DATA);
10368         outb(sr1 | 1<<5, VGA_SR_DATA);
10369         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10370         udelay(300);
10371
10372         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10373         POSTING_READ(vga_reg);
10374 }
10375
10376 static void i915_enable_vga_mem(struct drm_device *dev)
10377 {
10378         /* Enable VGA memory on Intel HD */
10379         if (HAS_PCH_SPLIT(dev)) {
10380                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10381                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10382                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10383                                                    VGA_RSRC_LEGACY_MEM |
10384                                                    VGA_RSRC_NORMAL_IO |
10385                                                    VGA_RSRC_NORMAL_MEM);
10386                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10387         }
10388 }
10389
10390 void i915_disable_vga_mem(struct drm_device *dev)
10391 {
10392         /* Disable VGA memory on Intel HD */
10393         if (HAS_PCH_SPLIT(dev)) {
10394                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10395                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10396                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10397                                                    VGA_RSRC_NORMAL_IO |
10398                                                    VGA_RSRC_NORMAL_MEM);
10399                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10400         }
10401 }
10402
10403 void intel_modeset_init_hw(struct drm_device *dev)
10404 {
10405         struct drm_i915_private *dev_priv = dev->dev_private;
10406
10407         intel_prepare_ddi(dev);
10408
10409         intel_init_clock_gating(dev);
10410
10411         /* Enable the CRI clock source so we can get at the display */
10412         if (IS_VALLEYVIEW(dev))
10413                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10414                            DPLL_INTEGRATED_CRI_CLK_VLV);
10415
10416         intel_init_dpio(dev);
10417
10418         mutex_lock(&dev->struct_mutex);
10419         intel_enable_gt_powersave(dev);
10420         mutex_unlock(&dev->struct_mutex);
10421 }
10422
10423 void intel_modeset_suspend_hw(struct drm_device *dev)
10424 {
10425         intel_suspend_hw(dev);
10426 }
10427
10428 void intel_modeset_init(struct drm_device *dev)
10429 {
10430         struct drm_i915_private *dev_priv = dev->dev_private;
10431         int i, j, ret;
10432
10433         drm_mode_config_init(dev);
10434
10435         dev->mode_config.min_width = 0;
10436         dev->mode_config.min_height = 0;
10437
10438         dev->mode_config.preferred_depth = 24;
10439         dev->mode_config.prefer_shadow = 1;
10440
10441         dev->mode_config.funcs = &intel_mode_funcs;
10442
10443         intel_init_quirks(dev);
10444
10445         intel_init_pm(dev);
10446
10447         if (INTEL_INFO(dev)->num_pipes == 0)
10448                 return;
10449
10450         intel_init_display(dev);
10451
10452         if (IS_GEN2(dev)) {
10453                 dev->mode_config.max_width = 2048;
10454                 dev->mode_config.max_height = 2048;
10455         } else if (IS_GEN3(dev)) {
10456                 dev->mode_config.max_width = 4096;
10457                 dev->mode_config.max_height = 4096;
10458         } else {
10459                 dev->mode_config.max_width = 8192;
10460                 dev->mode_config.max_height = 8192;
10461         }
10462         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10463
10464         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10465                       INTEL_INFO(dev)->num_pipes,
10466                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10467
10468         for_each_pipe(i) {
10469                 intel_crtc_init(dev, i);
10470                 for (j = 0; j < dev_priv->num_plane; j++) {
10471                         ret = intel_plane_init(dev, i, j);
10472                         if (ret)
10473                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10474                                               pipe_name(i), sprite_name(i, j), ret);
10475                 }
10476         }
10477
10478         intel_cpu_pll_init(dev);
10479         intel_shared_dpll_init(dev);
10480
10481         /* Just disable it once at startup */
10482         i915_disable_vga(dev);
10483         intel_setup_outputs(dev);
10484
10485         /* Just in case the BIOS is doing something questionable. */
10486         intel_disable_fbc(dev);
10487 }
10488
10489 static void
10490 intel_connector_break_all_links(struct intel_connector *connector)
10491 {
10492         connector->base.dpms = DRM_MODE_DPMS_OFF;
10493         connector->base.encoder = NULL;
10494         connector->encoder->connectors_active = false;
10495         connector->encoder->base.crtc = NULL;
10496 }
10497
10498 static void intel_enable_pipe_a(struct drm_device *dev)
10499 {
10500         struct intel_connector *connector;
10501         struct drm_connector *crt = NULL;
10502         struct intel_load_detect_pipe load_detect_temp;
10503
10504         /* We can't just switch on the pipe A, we need to set things up with a
10505          * proper mode and output configuration. As a gross hack, enable pipe A
10506          * by enabling the load detect pipe once. */
10507         list_for_each_entry(connector,
10508                             &dev->mode_config.connector_list,
10509                             base.head) {
10510                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10511                         crt = &connector->base;
10512                         break;
10513                 }
10514         }
10515
10516         if (!crt)
10517                 return;
10518
10519         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10520                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10521
10522
10523 }
10524
10525 static bool
10526 intel_check_plane_mapping(struct intel_crtc *crtc)
10527 {
10528         struct drm_device *dev = crtc->base.dev;
10529         struct drm_i915_private *dev_priv = dev->dev_private;
10530         u32 reg, val;
10531
10532         if (INTEL_INFO(dev)->num_pipes == 1)
10533                 return true;
10534
10535         reg = DSPCNTR(!crtc->plane);
10536         val = I915_READ(reg);
10537
10538         if ((val & DISPLAY_PLANE_ENABLE) &&
10539             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10540                 return false;
10541
10542         return true;
10543 }
10544
10545 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10546 {
10547         struct drm_device *dev = crtc->base.dev;
10548         struct drm_i915_private *dev_priv = dev->dev_private;
10549         u32 reg;
10550
10551         /* Clear any frame start delays used for debugging left by the BIOS */
10552         reg = PIPECONF(crtc->config.cpu_transcoder);
10553         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10554
10555         /* We need to sanitize the plane -> pipe mapping first because this will
10556          * disable the crtc (and hence change the state) if it is wrong. Note
10557          * that gen4+ has a fixed plane -> pipe mapping.  */
10558         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10559                 struct intel_connector *connector;
10560                 bool plane;
10561
10562                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10563                               crtc->base.base.id);
10564
10565                 /* Pipe has the wrong plane attached and the plane is active.
10566                  * Temporarily change the plane mapping and disable everything
10567                  * ...  */
10568                 plane = crtc->plane;
10569                 crtc->plane = !plane;
10570                 dev_priv->display.crtc_disable(&crtc->base);
10571                 crtc->plane = plane;
10572
10573                 /* ... and break all links. */
10574                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10575                                     base.head) {
10576                         if (connector->encoder->base.crtc != &crtc->base)
10577                                 continue;
10578
10579                         intel_connector_break_all_links(connector);
10580                 }
10581
10582                 WARN_ON(crtc->active);
10583                 crtc->base.enabled = false;
10584         }
10585
10586         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10587             crtc->pipe == PIPE_A && !crtc->active) {
10588                 /* BIOS forgot to enable pipe A, this mostly happens after
10589                  * resume. Force-enable the pipe to fix this, the update_dpms
10590                  * call below we restore the pipe to the right state, but leave
10591                  * the required bits on. */
10592                 intel_enable_pipe_a(dev);
10593         }
10594
10595         /* Adjust the state of the output pipe according to whether we
10596          * have active connectors/encoders. */
10597         intel_crtc_update_dpms(&crtc->base);
10598
10599         if (crtc->active != crtc->base.enabled) {
10600                 struct intel_encoder *encoder;
10601
10602                 /* This can happen either due to bugs in the get_hw_state
10603                  * functions or because the pipe is force-enabled due to the
10604                  * pipe A quirk. */
10605                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10606                               crtc->base.base.id,
10607                               crtc->base.enabled ? "enabled" : "disabled",
10608                               crtc->active ? "enabled" : "disabled");
10609
10610                 crtc->base.enabled = crtc->active;
10611
10612                 /* Because we only establish the connector -> encoder ->
10613                  * crtc links if something is active, this means the
10614                  * crtc is now deactivated. Break the links. connector
10615                  * -> encoder links are only establish when things are
10616                  *  actually up, hence no need to break them. */
10617                 WARN_ON(crtc->active);
10618
10619                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10620                         WARN_ON(encoder->connectors_active);
10621                         encoder->base.crtc = NULL;
10622                 }
10623         }
10624 }
10625
10626 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10627 {
10628         struct intel_connector *connector;
10629         struct drm_device *dev = encoder->base.dev;
10630
10631         /* We need to check both for a crtc link (meaning that the
10632          * encoder is active and trying to read from a pipe) and the
10633          * pipe itself being active. */
10634         bool has_active_crtc = encoder->base.crtc &&
10635                 to_intel_crtc(encoder->base.crtc)->active;
10636
10637         if (encoder->connectors_active && !has_active_crtc) {
10638                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10639                               encoder->base.base.id,
10640                               drm_get_encoder_name(&encoder->base));
10641
10642                 /* Connector is active, but has no active pipe. This is
10643                  * fallout from our resume register restoring. Disable
10644                  * the encoder manually again. */
10645                 if (encoder->base.crtc) {
10646                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10647                                       encoder->base.base.id,
10648                                       drm_get_encoder_name(&encoder->base));
10649                         encoder->disable(encoder);
10650                 }
10651
10652                 /* Inconsistent output/port/pipe state happens presumably due to
10653                  * a bug in one of the get_hw_state functions. Or someplace else
10654                  * in our code, like the register restore mess on resume. Clamp
10655                  * things to off as a safer default. */
10656                 list_for_each_entry(connector,
10657                                     &dev->mode_config.connector_list,
10658                                     base.head) {
10659                         if (connector->encoder != encoder)
10660                                 continue;
10661
10662                         intel_connector_break_all_links(connector);
10663                 }
10664         }
10665         /* Enabled encoders without active connectors will be fixed in
10666          * the crtc fixup. */
10667 }
10668
10669 void i915_redisable_vga(struct drm_device *dev)
10670 {
10671         struct drm_i915_private *dev_priv = dev->dev_private;
10672         u32 vga_reg = i915_vgacntrl_reg(dev);
10673
10674         /* This function can be called both from intel_modeset_setup_hw_state or
10675          * at a very early point in our resume sequence, where the power well
10676          * structures are not yet restored. Since this function is at a very
10677          * paranoid "someone might have enabled VGA while we were not looking"
10678          * level, just check if the power well is enabled instead of trying to
10679          * follow the "don't touch the power well if we don't need it" policy
10680          * the rest of the driver uses. */
10681         if (HAS_POWER_WELL(dev) &&
10682             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10683                 return;
10684
10685         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10686                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10687                 i915_disable_vga(dev);
10688                 i915_disable_vga_mem(dev);
10689         }
10690 }
10691
10692 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10693 {
10694         struct drm_i915_private *dev_priv = dev->dev_private;
10695         enum pipe pipe;
10696         struct intel_crtc *crtc;
10697         struct intel_encoder *encoder;
10698         struct intel_connector *connector;
10699         int i;
10700
10701         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10702                             base.head) {
10703                 memset(&crtc->config, 0, sizeof(crtc->config));
10704
10705                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10706                                                                  &crtc->config);
10707
10708                 crtc->base.enabled = crtc->active;
10709
10710                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10711                               crtc->base.base.id,
10712                               crtc->active ? "enabled" : "disabled");
10713         }
10714
10715         /* FIXME: Smash this into the new shared dpll infrastructure. */
10716         if (HAS_DDI(dev))
10717                 intel_ddi_setup_hw_pll_state(dev);
10718
10719         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10720                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10721
10722                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10723                 pll->active = 0;
10724                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10725                                     base.head) {
10726                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10727                                 pll->active++;
10728                 }
10729                 pll->refcount = pll->active;
10730
10731                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10732                               pll->name, pll->refcount, pll->on);
10733         }
10734
10735         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10736                             base.head) {
10737                 pipe = 0;
10738
10739                 if (encoder->get_hw_state(encoder, &pipe)) {
10740                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10741                         encoder->base.crtc = &crtc->base;
10742                         if (encoder->get_config)
10743                                 encoder->get_config(encoder, &crtc->config);
10744                 } else {
10745                         encoder->base.crtc = NULL;
10746                 }
10747
10748                 encoder->connectors_active = false;
10749                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10750                               encoder->base.base.id,
10751                               drm_get_encoder_name(&encoder->base),
10752                               encoder->base.crtc ? "enabled" : "disabled",
10753                               pipe);
10754         }
10755
10756         list_for_each_entry(connector, &dev->mode_config.connector_list,
10757                             base.head) {
10758                 if (connector->get_hw_state(connector)) {
10759                         connector->base.dpms = DRM_MODE_DPMS_ON;
10760                         connector->encoder->connectors_active = true;
10761                         connector->base.encoder = &connector->encoder->base;
10762                 } else {
10763                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10764                         connector->base.encoder = NULL;
10765                 }
10766                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10767                               connector->base.base.id,
10768                               drm_get_connector_name(&connector->base),
10769                               connector->base.encoder ? "enabled" : "disabled");
10770         }
10771 }
10772
10773 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10774  * and i915 state tracking structures. */
10775 void intel_modeset_setup_hw_state(struct drm_device *dev,
10776                                   bool force_restore)
10777 {
10778         struct drm_i915_private *dev_priv = dev->dev_private;
10779         enum pipe pipe;
10780         struct intel_crtc *crtc;
10781         struct intel_encoder *encoder;
10782         int i;
10783
10784         intel_modeset_readout_hw_state(dev);
10785
10786         /*
10787          * Now that we have the config, copy it to each CRTC struct
10788          * Note that this could go away if we move to using crtc_config
10789          * checking everywhere.
10790          */
10791         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10792                             base.head) {
10793                 if (crtc->active && i915_fastboot) {
10794                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10795
10796                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10797                                       crtc->base.base.id);
10798                         drm_mode_debug_printmodeline(&crtc->base.mode);
10799                 }
10800         }
10801
10802         /* HW state is read out, now we need to sanitize this mess. */
10803         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10804                             base.head) {
10805                 intel_sanitize_encoder(encoder);
10806         }
10807
10808         for_each_pipe(pipe) {
10809                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10810                 intel_sanitize_crtc(crtc);
10811                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10812         }
10813
10814         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10815                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10816
10817                 if (!pll->on || pll->active)
10818                         continue;
10819
10820                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10821
10822                 pll->disable(dev_priv, pll);
10823                 pll->on = false;
10824         }
10825
10826         if (force_restore) {
10827                 i915_redisable_vga(dev);
10828
10829                 /*
10830                  * We need to use raw interfaces for restoring state to avoid
10831                  * checking (bogus) intermediate states.
10832                  */
10833                 for_each_pipe(pipe) {
10834                         struct drm_crtc *crtc =
10835                                 dev_priv->pipe_to_crtc_mapping[pipe];
10836
10837                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10838                                          crtc->fb);
10839                 }
10840         } else {
10841                 intel_modeset_update_staged_output_state(dev);
10842         }
10843
10844         intel_modeset_check_state(dev);
10845
10846         drm_mode_config_reset(dev);
10847 }
10848
10849 void intel_modeset_gem_init(struct drm_device *dev)
10850 {
10851         intel_modeset_init_hw(dev);
10852
10853         intel_setup_overlay(dev);
10854
10855         intel_modeset_setup_hw_state(dev, false);
10856 }
10857
10858 void intel_modeset_cleanup(struct drm_device *dev)
10859 {
10860         struct drm_i915_private *dev_priv = dev->dev_private;
10861         struct drm_crtc *crtc;
10862         struct drm_connector *connector;
10863
10864         /*
10865          * Interrupts and polling as the first thing to avoid creating havoc.
10866          * Too much stuff here (turning of rps, connectors, ...) would
10867          * experience fancy races otherwise.
10868          */
10869         drm_irq_uninstall(dev);
10870         cancel_work_sync(&dev_priv->hotplug_work);
10871         /*
10872          * Due to the hpd irq storm handling the hotplug work can re-arm the
10873          * poll handlers. Hence disable polling after hpd handling is shut down.
10874          */
10875         drm_kms_helper_poll_fini(dev);
10876
10877         mutex_lock(&dev->struct_mutex);
10878
10879         intel_unregister_dsm_handler();
10880
10881         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10882                 /* Skip inactive CRTCs */
10883                 if (!crtc->fb)
10884                         continue;
10885
10886                 intel_increase_pllclock(crtc);
10887         }
10888
10889         intel_disable_fbc(dev);
10890
10891         i915_enable_vga_mem(dev);
10892
10893         intel_disable_gt_powersave(dev);
10894
10895         ironlake_teardown_rc6(dev);
10896
10897         mutex_unlock(&dev->struct_mutex);
10898
10899         /* flush any delayed tasks or pending work */
10900         flush_scheduled_work();
10901
10902         /* destroy backlight, if any, before the connectors */
10903         intel_panel_destroy_backlight(dev);
10904
10905         /* destroy the sysfs files before encoders/connectors */
10906         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10907                 drm_sysfs_connector_remove(connector);
10908
10909         drm_mode_config_cleanup(dev);
10910
10911         intel_cleanup_overlay(dev);
10912 }
10913
10914 /*
10915  * Return which encoder is currently attached for connector.
10916  */
10917 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10918 {
10919         return &intel_attached_encoder(connector)->base;
10920 }
10921
10922 void intel_connector_attach_encoder(struct intel_connector *connector,
10923                                     struct intel_encoder *encoder)
10924 {
10925         connector->encoder = encoder;
10926         drm_mode_connector_attach_encoder(&connector->base,
10927                                           &encoder->base);
10928 }
10929
10930 /*
10931  * set vga decode state - true == enable VGA decode
10932  */
10933 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10934 {
10935         struct drm_i915_private *dev_priv = dev->dev_private;
10936         u16 gmch_ctrl;
10937
10938         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10939         if (state)
10940                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10941         else
10942                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10943         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10944         return 0;
10945 }
10946
10947 struct intel_display_error_state {
10948
10949         u32 power_well_driver;
10950
10951         int num_transcoders;
10952
10953         struct intel_cursor_error_state {
10954                 u32 control;
10955                 u32 position;
10956                 u32 base;
10957                 u32 size;
10958         } cursor[I915_MAX_PIPES];
10959
10960         struct intel_pipe_error_state {
10961                 u32 source;
10962         } pipe[I915_MAX_PIPES];
10963
10964         struct intel_plane_error_state {
10965                 u32 control;
10966                 u32 stride;
10967                 u32 size;
10968                 u32 pos;
10969                 u32 addr;
10970                 u32 surface;
10971                 u32 tile_offset;
10972         } plane[I915_MAX_PIPES];
10973
10974         struct intel_transcoder_error_state {
10975                 enum transcoder cpu_transcoder;
10976
10977                 u32 conf;
10978
10979                 u32 htotal;
10980                 u32 hblank;
10981                 u32 hsync;
10982                 u32 vtotal;
10983                 u32 vblank;
10984                 u32 vsync;
10985         } transcoder[4];
10986 };
10987
10988 struct intel_display_error_state *
10989 intel_display_capture_error_state(struct drm_device *dev)
10990 {
10991         drm_i915_private_t *dev_priv = dev->dev_private;
10992         struct intel_display_error_state *error;
10993         int transcoders[] = {
10994                 TRANSCODER_A,
10995                 TRANSCODER_B,
10996                 TRANSCODER_C,
10997                 TRANSCODER_EDP,
10998         };
10999         int i;
11000
11001         if (INTEL_INFO(dev)->num_pipes == 0)
11002                 return NULL;
11003
11004         error = kmalloc(sizeof(*error), GFP_ATOMIC);
11005         if (error == NULL)
11006                 return NULL;
11007
11008         if (HAS_POWER_WELL(dev))
11009                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11010
11011         for_each_pipe(i) {
11012                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11013                         error->cursor[i].control = I915_READ(CURCNTR(i));
11014                         error->cursor[i].position = I915_READ(CURPOS(i));
11015                         error->cursor[i].base = I915_READ(CURBASE(i));
11016                 } else {
11017                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11018                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11019                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11020                 }
11021
11022                 error->plane[i].control = I915_READ(DSPCNTR(i));
11023                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11024                 if (INTEL_INFO(dev)->gen <= 3) {
11025                         error->plane[i].size = I915_READ(DSPSIZE(i));
11026                         error->plane[i].pos = I915_READ(DSPPOS(i));
11027                 }
11028                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11029                         error->plane[i].addr = I915_READ(DSPADDR(i));
11030                 if (INTEL_INFO(dev)->gen >= 4) {
11031                         error->plane[i].surface = I915_READ(DSPSURF(i));
11032                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11033                 }
11034
11035                 error->pipe[i].source = I915_READ(PIPESRC(i));
11036         }
11037
11038         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11039         if (HAS_DDI(dev_priv->dev))
11040                 error->num_transcoders++; /* Account for eDP. */
11041
11042         for (i = 0; i < error->num_transcoders; i++) {
11043                 enum transcoder cpu_transcoder = transcoders[i];
11044
11045                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11046
11047                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11048                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11049                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11050                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11051                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11052                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11053                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11054         }
11055
11056         /* In the code above we read the registers without checking if the power
11057          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11058          * prevent the next I915_WRITE from detecting it and printing an error
11059          * message. */
11060         intel_uncore_clear_errors(dev);
11061
11062         return error;
11063 }
11064
11065 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11066
11067 void
11068 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11069                                 struct drm_device *dev,
11070                                 struct intel_display_error_state *error)
11071 {
11072         int i;
11073
11074         if (!error)
11075                 return;
11076
11077         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11078         if (HAS_POWER_WELL(dev))
11079                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11080                            error->power_well_driver);
11081         for_each_pipe(i) {
11082                 err_printf(m, "Pipe [%d]:\n", i);
11083                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11084
11085                 err_printf(m, "Plane [%d]:\n", i);
11086                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11087                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11088                 if (INTEL_INFO(dev)->gen <= 3) {
11089                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11090                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11091                 }
11092                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11093                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11094                 if (INTEL_INFO(dev)->gen >= 4) {
11095                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11096                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11097                 }
11098
11099                 err_printf(m, "Cursor [%d]:\n", i);
11100                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11101                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11102                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11103         }
11104
11105         for (i = 0; i < error->num_transcoders; i++) {
11106                 err_printf(m, "  CPU transcoder: %c\n",
11107                            transcoder_name(error->transcoder[i].cpu_transcoder));
11108                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11109                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11110                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11111                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11112                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11113                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11114                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11115         }
11116 }