drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void vlv_init_dpio(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         /* Reset the DPIO config */
 392         I915_WRITE(DPIO_CTL, 0);
 393         POSTING_READ(DPIO_CTL);
 394         I915_WRITE(DPIO_CTL, 1);
 395         POSTING_READ(DPIO_CTL);
 396 }
 397
 398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 399 {
 400         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 401         return 1;
 402 }
 403
 404 static const struct dmi_system_id intel_dual_link_lvds[] = {
 405         {
 406                 .callback = intel_dual_link_lvds_callback,
 407                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 408                 .matches = {
 409                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 410                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 411                 },
 412         },
 413         { }     /* terminating entry */
 414 };
 415
 416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 417                               unsigned int reg)
 418 {
 419         unsigned int val;
 420
 421         /* use the module option value if specified */
 422         if (i915_lvds_channel_mode > 0)
 423                 return i915_lvds_channel_mode == 2;
 424
 425         if (dmi_check_system(intel_dual_link_lvds))
 426                 return true;
 427
 428         if (dev_priv->lvds_val)
 429                 val = dev_priv->lvds_val;
 430         else {
 431                 /* BIOS should set the proper LVDS register value at boot, but
 432                  * in reality, it doesn't set the value when the lid is closed;
 433                  * we need to check "the value to be set" in VBT when LVDS
 434                  * register is uninitialized.
 435                  */
 436                 val = I915_READ(reg);
 437                 if (!(val & ~LVDS_DETECTED))
 438                         val = dev_priv->bios_lvds_val;
 439                 dev_priv->lvds_val = val;
 440         }
 441         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 453                         /* LVDS dual channel */
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 465                         HAS_eDP)
 466                 limit = &intel_limits_ironlake_display_port;
 467         else
 468                 limit = &intel_limits_ironlake_dac;
 469
 470         return limit;
 471 }
 472
 473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 474 {
 475         struct drm_device *dev = crtc->dev;
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 480                 if (is_dual_link_lvds(dev_priv, LVDS))
 481                         /* LVDS with dual channel */
 482                         limit = &intel_limits_g4x_dual_channel_lvds;
 483                 else
 484                         /* LVDS with dual channel */
 485                         limit = &intel_limits_g4x_single_channel_lvds;
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 487                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 488                 limit = &intel_limits_g4x_hdmi;
 489         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 490                 limit = &intel_limits_g4x_sdvo;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 492                 limit = &intel_limits_g4x_display_port;
 493         } else /* The option is for other outputs */
 494                 limit = &intel_limits_i9xx_sdvo;
 495
 496         return limit;
 497 }
 498
 499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 limit = intel_ironlake_limit(crtc, refclk);
 506         else if (IS_G4X(dev)) {
 507                 limit = intel_g4x_limit(crtc);
 508         } else if (IS_PINEVIEW(dev)) {
 509                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_pineview_lvds;
 511                 else
 512                         limit = &intel_limits_pineview_sdvo;
 513         } else if (!IS_GEN2(dev)) {
 514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i9xx_lvds;
 516                 else
 517                         limit = &intel_limits_i9xx_sdvo;
 518         } else {
 519                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 520                         limit = &intel_limits_i8xx_lvds;
 521                 else
 522                         limit = &intel_limits_i8xx_dvo;
 523         }
 524         return limit;
 525 }
 526
 527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 528 static void pineview_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m2 + 2;
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / clock->n;
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 537 {
 538         if (IS_PINEVIEW(dev)) {
 539                 pineview_clock(refclk, clock);
 540                 return;
 541         }
 542         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 543         clock->p = clock->p1 * clock->p2;
 544         clock->vco = refclk * clock->m / (clock->n + 2);
 545         clock->dot = clock->vco / clock->p;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe is of the specified type
 550  */
 551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct intel_encoder *encoder;
 556
 557         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 558                 if (encoder->base.crtc == crtc && encoder->type == type)
 559                         return true;
 560
 561         return false;
 562 }
 563
 564 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 565 /**
 566  * Returns whether the given set of divisors are valid for a given refclk with
 567  * the given connectors.
 568  */
 569
 570 static bool intel_PLL_is_valid(struct drm_device *dev,
 571                                const intel_limit_t *limit,
 572                                const intel_clock_t *clock)
 573 {
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 577                 INTELPllInvalid("p out of range\n");
 578         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 579                 INTELPllInvalid("m2 out of range\n");
 580         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 581                 INTELPllInvalid("m1 out of range\n");
 582         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 583                 INTELPllInvalid("m1 <= m2\n");
 584         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 585                 INTELPllInvalid("m out of range\n");
 586         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 587                 INTELPllInvalid("n out of range\n");
 588         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 589                 INTELPllInvalid("vco out of range\n");
 590         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 591          * connector, etc., rather than just a single range.
 592          */
 593         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 594                 INTELPllInvalid("dot out of range\n");
 595
 596         return true;
 597 }
 598
 599 static bool
 600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 601                     int target, int refclk, intel_clock_t *match_clock,
 602                     intel_clock_t *best_clock)
 603
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 611             (I915_READ(LVDS)) != 0) {
 612                 /*
 613                  * For LVDS, if the panel is on, just rely on its current
 614                  * settings for dual-channel.  We haven't figured out how to
 615                  * reliably set up different single/dual channel state, if we
 616                  * even can.
 617                  */
 618                 if (is_dual_link_lvds(dev_priv, LVDS))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         /* m1 is always 0 in Pineview */
 636                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 637                                 break;
 638                         for (clock.n = limit->n.min;
 639                              clock.n <= limit->n.max; clock.n++) {
 640                                 for (clock.p1 = limit->p1.min;
 641                                         clock.p1 <= limit->p1.max; clock.p1++) {
 642                                         int this_err;
 643
 644                                         intel_clock(dev, refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648                                         if (match_clock &&
 649                                             clock.p != match_clock->p)
 650                                                 continue;
 651
 652                                         this_err = abs(clock.dot - target);
 653                                         if (this_err < err) {
 654                                                 *best_clock = clock;
 655                                                 err = this_err;
 656                                         }
 657                                 }
 658                         }
 659                 }
 660         }
 661
 662         return (err != target);
 663 }
 664
 665 static bool
 666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 667                         int target, int refclk, intel_clock_t *match_clock,
 668                         intel_clock_t *best_clock)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         intel_clock_t clock;
 673         int max_n;
 674         bool found;
 675         /* approximately equals target * 0.00585 */
 676         int err_most = (target >> 8) + (target >> 9);
 677         found = false;
 678
 679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 680                 int lvds_reg;
 681
 682                 if (HAS_PCH_SPLIT(dev))
 683                         lvds_reg = PCH_LVDS;
 684                 else
 685                         lvds_reg = LVDS;
 686                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 687                     LVDS_CLKB_POWER_UP)
 688                         clock.p2 = limit->p2.p2_fast;
 689                 else
 690                         clock.p2 = limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         clock.p2 = limit->p2.p2_slow;
 694                 else
 695                         clock.p2 = limit->p2.p2_fast;
 696         }
 697
 698         memset(best_clock, 0, sizeof(*best_clock));
 699         max_n = limit->n.max;
 700         /* based on hardware requirement, prefer smaller n to precision */
 701         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 702                 /* based on hardware requirement, prefere larger m1,m2 */
 703                 for (clock.m1 = limit->m1.max;
 704                      clock.m1 >= limit->m1.min; clock.m1--) {
 705                         for (clock.m2 = limit->m2.max;
 706                              clock.m2 >= limit->m2.min; clock.m2--) {
 707                                 for (clock.p1 = limit->p1.max;
 708                                      clock.p1 >= limit->p1.min; clock.p1--) {
 709                                         int this_err;
 710
 711                                         intel_clock(dev, refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err_most) {
 721                                                 *best_clock = clock;
 722                                                 err_most = this_err;
 723                                                 max_n = clock.n;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730         return found;
 731 }
 732
 733 static bool
 734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 735                            int target, int refclk, intel_clock_t *match_clock,
 736                            intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         intel_clock_t clock;
 740
 741         if (target < 200000) {
 742                 clock.n = 1;
 743                 clock.p1 = 2;
 744                 clock.p2 = 10;
 745                 clock.m1 = 12;
 746                 clock.m2 = 9;
 747         } else {
 748                 clock.n = 2;
 749                 clock.p1 = 1;
 750                 clock.p2 = 10;
 751                 clock.m1 = 14;
 752                 clock.m2 = 8;
 753         }
 754         intel_clock(dev, refclk, &clock);
 755         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 756         return true;
 757 }
 758
 759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 760 static bool
 761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                       int target, int refclk, intel_clock_t *match_clock,
 763                       intel_clock_t *best_clock)
 764 {
 765         intel_clock_t clock;
 766         if (target < 200000) {
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.n = 2;
 770                 clock.m1 = 23;
 771                 clock.m2 = 8;
 772         } else {
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.n = 1;
 776                 clock.m1 = 14;
 777                 clock.m2 = 2;
 778         }
 779         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 780         clock.p = (clock.p1 * clock.p2);
 781         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 782         clock.vco = 0;
 783         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 784         return true;
 785 }
 786
 787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 frame, frame_reg = PIPEFRAME(pipe);
 791
 792         frame = I915_READ(frame_reg);
 793
 794         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /**
 799  * intel_wait_for_vblank - wait for vblank on a given pipe
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 804  * mode setting code.
 805  */
 806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         int pipestat_reg = PIPESTAT(pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 5) {
 812                 ironlake_wait_for_vblank(dev, pipe);
 813                 return;
 814         }
 815
 816         /* Clear existing vblank status. Note this will clear any other
 817          * sticky status fields as well.
 818          *
 819          * This races with i915_driver_irq_handler() with the result
 820          * that either function could miss a vblank event.  Here it is not
 821          * fatal, as we will either wait upon the next vblank interrupt or
 822          * timeout.  Generally speaking intel_wait_for_vblank() is only
 823          * called during modeset at which time the GPU should be idle and
 824          * should *not* be performing page flips and thus not waiting on
 825          * vblanks...
 826          * Currently, the result of us stealing a vblank from the irq
 827          * handler is that a single frame will be skipped during swapbuffers.
 828          */
 829         I915_WRITE(pipestat_reg,
 830                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 831
 832         /* Wait for vblank interrupt bit to set */
 833         if (wait_for(I915_READ(pipestat_reg) &
 834                      PIPE_VBLANK_INTERRUPT_STATUS,
 835                      50))
 836                 DRM_DEBUG_KMS("vblank wait timed out\n");
 837 }
 838
 839 /*
 840  * intel_wait_for_pipe_off - wait for pipe to turn off
 841  * @dev: drm device
 842  * @pipe: pipe to wait for
 843  *
 844  * After disabling a pipe, we can't wait for vblank in the usual way,
 845  * spinning on the vblank interrupt status bit, since we won't actually
 846  * see an interrupt when the pipe is disabled.
 847  *
 848  * On Gen4 and above:
 849  *   wait for the pipe register state bit to turn off
 850  *
 851  * Otherwise:
 852  *   wait for the display line value to settle (it usually
 853  *   ends up stopping at the start of the next frame).
 854  *
 855  */
 856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859
 860         if (INTEL_INFO(dev)->gen >= 4) {
 861                 int reg = PIPECONF(pipe);
 862
 863                 /* Wait for the Pipe State to go off */
 864                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 865                              100))
 866                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 867         } else {
 868                 u32 last_line, line_mask;
 869                 int reg = PIPEDSL(pipe);
 870                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 871
 872                 if (IS_GEN2(dev))
 873                         line_mask = DSL_LINEMASK_GEN2;
 874                 else
 875                         line_mask = DSL_LINEMASK_GEN3;
 876
 877                 /* Wait for the display line to settle */
 878                 do {
 879                         last_line = I915_READ(reg) & line_mask;
 880                         mdelay(5);
 881                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 882                          time_after(timeout, jiffies));
 883                 if (time_after(jiffies, timeout))
 884                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 885         }
 886 }
 887
 888 static const char *state_string(bool enabled)
 889 {
 890         return enabled ? "on" : "off";
 891 }
 892
 893 /* Only for pre-ILK configs */
 894 static void assert_pll(struct drm_i915_private *dev_priv,
 895                        enum pipe pipe, bool state)
 896 {
 897         int reg;
 898         u32 val;
 899         bool cur_state;
 900
 901         reg = DPLL(pipe);
 902         val = I915_READ(reg);
 903         cur_state = !!(val & DPLL_VCO_ENABLE);
 904         WARN(cur_state != state,
 905              "PLL state assertion failure (expected %s, current %s)\n",
 906              state_string(state), state_string(cur_state));
 907 }
 908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 910
 911 /* For ILK+ */
 912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 913                            struct intel_crtc *intel_crtc, bool state)
 914 {
 915         int reg;
 916         u32 val;
 917         bool cur_state;
 918
 919         if (HAS_PCH_LPT(dev_priv->dev)) {
 920                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 921                 return;
 922         }
 923
 924         if (!intel_crtc->pch_pll) {
 925                 WARN(1, "asserting PCH PLL enabled with no PLL\n");
 926                 return;
 927         }
 928
 929         if (HAS_PCH_CPT(dev_priv->dev)) {
 930                 u32 pch_dpll;
 931
 932                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 933
 934                 /* Make sure the selected PLL is enabled to the transcoder */
 935                 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
 936                      "transcoder %d PLL not enabled\n", intel_crtc->pipe);
 937         }
 938
 939         reg = intel_crtc->pch_pll->pll_reg;
 940         val = I915_READ(reg);
 941         cur_state = !!(val & DPLL_VCO_ENABLE);
 942         WARN(cur_state != state,
 943              "PCH PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 947 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 948
 949 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 950                           enum pipe pipe, bool state)
 951 {
 952         int reg;
 953         u32 val;
 954         bool cur_state;
 955
 956         if (IS_HASWELL(dev_priv->dev)) {
 957                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
 958                 reg = DDI_FUNC_CTL(pipe);
 959                 val = I915_READ(reg);
 960                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
 961         } else {
 962                 reg = FDI_TX_CTL(pipe);
 963                 val = I915_READ(reg);
 964                 cur_state = !!(val & FDI_TX_ENABLE);
 965         }
 966         WARN(cur_state != state,
 967              "FDI TX state assertion failure (expected %s, current %s)\n",
 968              state_string(state), state_string(cur_state));
 969 }
 970 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 971 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 972
 973 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 974                           enum pipe pipe, bool state)
 975 {
 976         int reg;
 977         u32 val;
 978         bool cur_state;
 979
 980         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
 981                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
 982                         return;
 983         } else {
 984                 reg = FDI_RX_CTL(pipe);
 985                 val = I915_READ(reg);
 986                 cur_state = !!(val & FDI_RX_ENABLE);
 987         }
 988         WARN(cur_state != state,
 989              "FDI RX state assertion failure (expected %s, current %s)\n",
 990              state_string(state), state_string(cur_state));
 991 }
 992 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 993 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 994
 995 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 996                                       enum pipe pipe)
 997 {
 998         int reg;
 999         u32 val;
1000
1001         /* ILK FDI PLL is always enabled */
1002         if (dev_priv->info->gen == 5)
1003                 return;
1004
1005         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1006         if (IS_HASWELL(dev_priv->dev))
1007                 return;
1008
1009         reg = FDI_TX_CTL(pipe);
1010         val = I915_READ(reg);
1011         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1012 }
1013
1014 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1015                                       enum pipe pipe)
1016 {
1017         int reg;
1018         u32 val;
1019
1020         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1021                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1022                 return;
1023         }
1024         reg = FDI_RX_CTL(pipe);
1025         val = I915_READ(reg);
1026         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1027 }
1028
1029 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1030                                   enum pipe pipe)
1031 {
1032         int pp_reg, lvds_reg;
1033         u32 val;
1034         enum pipe panel_pipe = PIPE_A;
1035         bool locked = true;
1036
1037         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1038                 pp_reg = PCH_PP_CONTROL;
1039                 lvds_reg = PCH_LVDS;
1040         } else {
1041                 pp_reg = PP_CONTROL;
1042                 lvds_reg = LVDS;
1043         }
1044
1045         val = I915_READ(pp_reg);
1046         if (!(val & PANEL_POWER_ON) ||
1047             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1048                 locked = false;
1049
1050         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1051                 panel_pipe = PIPE_B;
1052
1053         WARN(panel_pipe == pipe && locked,
1054              "panel assertion failure, pipe %c regs locked\n",
1055              pipe_name(pipe));
1056 }
1057
1058 void assert_pipe(struct drm_i915_private *dev_priv,
1059                  enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         /* if we need the pipe A quirk it must be always on */
1066         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1067                 state = true;
1068
1069         reg = PIPECONF(pipe);
1070         val = I915_READ(reg);
1071         cur_state = !!(val & PIPECONF_ENABLE);
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         int reg, i;
1099         u32 val;
1100         int cur_pipe;
1101
1102         /* Planes are fixed to pipes on ILK+ */
1103         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1104                 reg = DSPCNTR(pipe);
1105                 val = I915_READ(reg);
1106                 WARN((val & DISPLAY_PLANE_ENABLE),
1107                      "plane %c assertion failure, should be disabled but not\n",
1108                      plane_name(pipe));
1109                 return;
1110         }
1111
1112         /* Need to check both planes against the pipe */
1113         for (i = 0; i < 2; i++) {
1114                 reg = DSPCNTR(i);
1115                 val = I915_READ(reg);
1116                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1117                         DISPPLANE_SEL_PIPE_SHIFT;
1118                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1119                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1120                      plane_name(i), pipe_name(pipe));
1121         }
1122 }
1123
1124 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1125 {
1126         u32 val;
1127         bool enabled;
1128
1129         if (HAS_PCH_LPT(dev_priv->dev)) {
1130                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1131                 return;
1132         }
1133
1134         val = I915_READ(PCH_DREF_CONTROL);
1135         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1136                             DREF_SUPERSPREAD_SOURCE_MASK));
1137         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1138 }
1139
1140 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1141                                        enum pipe pipe)
1142 {
1143         int reg;
1144         u32 val;
1145         bool enabled;
1146
1147         reg = TRANSCONF(pipe);
1148         val = I915_READ(reg);
1149         enabled = !!(val & TRANS_ENABLE);
1150         WARN(enabled,
1151              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1152              pipe_name(pipe));
1153 }
1154
1155 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1156                             enum pipe pipe, u32 port_sel, u32 val)
1157 {
1158         if ((val & DP_PORT_EN) == 0)
1159                 return false;
1160
1161         if (HAS_PCH_CPT(dev_priv->dev)) {
1162                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1163                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1164                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1165                         return false;
1166         } else {
1167                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1168                         return false;
1169         }
1170         return true;
1171 }
1172
1173 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1174                               enum pipe pipe, u32 val)
1175 {
1176         if ((val & PORT_ENABLE) == 0)
1177                 return false;
1178
1179         if (HAS_PCH_CPT(dev_priv->dev)) {
1180                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181                         return false;
1182         } else {
1183                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1184                         return false;
1185         }
1186         return true;
1187 }
1188
1189 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1190                               enum pipe pipe, u32 val)
1191 {
1192         if ((val & LVDS_PORT_EN) == 0)
1193                 return false;
1194
1195         if (HAS_PCH_CPT(dev_priv->dev)) {
1196                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1197                         return false;
1198         } else {
1199                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1200                         return false;
1201         }
1202         return true;
1203 }
1204
1205 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1206                               enum pipe pipe, u32 val)
1207 {
1208         if ((val & ADPA_DAC_ENABLE) == 0)
1209                 return false;
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1221                                    enum pipe pipe, int reg, u32 port_sel)
1222 {
1223         u32 val = I915_READ(reg);
1224         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1225              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1226              reg, pipe_name(pipe));
1227 }
1228
1229 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1230                                      enum pipe pipe, int reg)
1231 {
1232         u32 val = I915_READ(reg);
1233         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1234              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1235              reg, pipe_name(pipe));
1236 }
1237
1238 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1239                                       enum pipe pipe)
1240 {
1241         int reg;
1242         u32 val;
1243
1244         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1245         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1246         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1247
1248         reg = PCH_ADPA;
1249         val = I915_READ(reg);
1250         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1251              "PCH VGA enabled on transcoder %c, should be disabled\n",
1252              pipe_name(pipe));
1253
1254         reg = PCH_LVDS;
1255         val = I915_READ(reg);
1256         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1257              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1258              pipe_name(pipe));
1259
1260         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1261         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1262         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1263 }
1264
1265 /**
1266  * intel_enable_pll - enable a PLL
1267  * @dev_priv: i915 private structure
1268  * @pipe: pipe PLL to enable
1269  *
1270  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1271  * make sure the PLL reg is writable first though, since the panel write
1272  * protect mechanism may be enabled.
1273  *
1274  * Note!  This is for pre-ILK only.
1275  */
1276 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1277 {
1278         int reg;
1279         u32 val;
1280
1281         /* No really, not for ILK+ */
1282         BUG_ON(dev_priv->info->gen >= 5);
1283
1284         /* PLL is protected by panel, make sure we can write it */
1285         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1286                 assert_panel_unlocked(dev_priv, pipe);
1287
1288         reg = DPLL(pipe);
1289         val = I915_READ(reg);
1290         val |= DPLL_VCO_ENABLE;
1291
1292         /* We do this three times for luck */
1293         I915_WRITE(reg, val);
1294         POSTING_READ(reg);
1295         udelay(150); /* wait for warmup */
1296         I915_WRITE(reg, val);
1297         POSTING_READ(reg);
1298         udelay(150); /* wait for warmup */
1299         I915_WRITE(reg, val);
1300         POSTING_READ(reg);
1301         udelay(150); /* wait for warmup */
1302 }
1303
1304 /**
1305  * intel_disable_pll - disable a PLL
1306  * @dev_priv: i915 private structure
1307  * @pipe: pipe PLL to disable
1308  *
1309  * Disable the PLL for @pipe, making sure the pipe is off first.
1310  *
1311  * Note!  This is for pre-ILK only.
1312  */
1313 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1314 {
1315         int reg;
1316         u32 val;
1317
1318         /* Don't disable pipe A or pipe A PLLs if needed */
1319         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1320                 return;
1321
1322         /* Make sure the pipe isn't still relying on us */
1323         assert_pipe_disabled(dev_priv, pipe);
1324
1325         reg = DPLL(pipe);
1326         val = I915_READ(reg);
1327         val &= ~DPLL_VCO_ENABLE;
1328         I915_WRITE(reg, val);
1329         POSTING_READ(reg);
1330 }
1331
1332 /* SBI access */
1333 static void
1334 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1335 {
1336         unsigned long flags;
1337
1338         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1339         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1340                                 100)) {
1341                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1342                 goto out_unlock;
1343         }
1344
1345         I915_WRITE(SBI_ADDR,
1346                         (reg << 16));
1347         I915_WRITE(SBI_DATA,
1348                         value);
1349         I915_WRITE(SBI_CTL_STAT,
1350                         SBI_BUSY |
1351                         SBI_CTL_OP_CRWR);
1352
1353         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1354                                 100)) {
1355                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1356                 goto out_unlock;
1357         }
1358
1359 out_unlock:
1360         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1361 }
1362
1363 static u32
1364 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1365 {
1366         unsigned long flags;
1367         u32 value;
1368
1369         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1370         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1371                                 100)) {
1372                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1373                 goto out_unlock;
1374         }
1375
1376         I915_WRITE(SBI_ADDR,
1377                         (reg << 16));
1378         I915_WRITE(SBI_CTL_STAT,
1379                         SBI_BUSY |
1380                         SBI_CTL_OP_CRRD);
1381
1382         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1383                                 100)) {
1384                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1385                 goto out_unlock;
1386         }
1387
1388         value = I915_READ(SBI_DATA);
1389
1390 out_unlock:
1391         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1392         return value;
1393 }
1394
1395 /**
1396  * intel_enable_pch_pll - enable PCH PLL
1397  * @dev_priv: i915 private structure
1398  * @pipe: pipe PLL to enable
1399  *
1400  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1401  * drives the transcoder clock.
1402  */
1403 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1404 {
1405         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1406         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1407         int reg;
1408         u32 val;
1409
1410         /* PCH only available on ILK+ */
1411         BUG_ON(dev_priv->info->gen < 5);
1412         BUG_ON(pll == NULL);
1413         BUG_ON(pll->refcount == 0);
1414
1415         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1416                       pll->pll_reg, pll->active, pll->on,
1417                       intel_crtc->base.base.id);
1418
1419         /* PCH refclock must be enabled first */
1420         assert_pch_refclk_enabled(dev_priv);
1421
1422         if (pll->active++ && pll->on) {
1423                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1424                 return;
1425         }
1426
1427         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1428
1429         reg = pll->pll_reg;
1430         val = I915_READ(reg);
1431         val |= DPLL_VCO_ENABLE;
1432         I915_WRITE(reg, val);
1433         POSTING_READ(reg);
1434         udelay(200);
1435
1436         pll->on = true;
1437 }
1438
1439 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1440 {
1441         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1442         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1443         int reg;
1444         u32 val;
1445
1446         /* PCH only available on ILK+ */
1447         BUG_ON(dev_priv->info->gen < 5);
1448         if (pll == NULL)
1449                return;
1450
1451         BUG_ON(pll->refcount == 0);
1452
1453         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1454                       pll->pll_reg, pll->active, pll->on,
1455                       intel_crtc->base.base.id);
1456
1457         BUG_ON(pll->active == 0);
1458         if (--pll->active) {
1459                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1460                 return;
1461         }
1462
1463         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1464
1465         /* Make sure transcoder isn't still depending on us */
1466         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1467
1468         reg = pll->pll_reg;
1469         val = I915_READ(reg);
1470         val &= ~DPLL_VCO_ENABLE;
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(200);
1474
1475         pll->on = false;
1476 }
1477
1478 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1479                                     enum pipe pipe)
1480 {
1481         int reg;
1482         u32 val, pipeconf_val;
1483         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1484
1485         /* PCH only available on ILK+ */
1486         BUG_ON(dev_priv->info->gen < 5);
1487
1488         /* Make sure PCH DPLL is enabled */
1489         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1490
1491         /* FDI must be feeding us bits for PCH ports */
1492         assert_fdi_tx_enabled(dev_priv, pipe);
1493         assert_fdi_rx_enabled(dev_priv, pipe);
1494
1495         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1496                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1497                 return;
1498         }
1499         reg = TRANSCONF(pipe);
1500         val = I915_READ(reg);
1501         pipeconf_val = I915_READ(PIPECONF(pipe));
1502
1503         if (HAS_PCH_IBX(dev_priv->dev)) {
1504                 /*
1505                  * make the BPC in transcoder be consistent with
1506                  * that in pipeconf reg.
1507                  */
1508                 val &= ~PIPE_BPC_MASK;
1509                 val |= pipeconf_val & PIPE_BPC_MASK;
1510         }
1511
1512         val &= ~TRANS_INTERLACE_MASK;
1513         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1514                 if (HAS_PCH_IBX(dev_priv->dev) &&
1515                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1516                         val |= TRANS_LEGACY_INTERLACED_ILK;
1517                 else
1518                         val |= TRANS_INTERLACED;
1519         else
1520                 val |= TRANS_PROGRESSIVE;
1521
1522         I915_WRITE(reg, val | TRANS_ENABLE);
1523         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1524                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1525 }
1526
1527 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1528                                      enum pipe pipe)
1529 {
1530         int reg;
1531         u32 val;
1532
1533         /* FDI relies on the transcoder */
1534         assert_fdi_tx_disabled(dev_priv, pipe);
1535         assert_fdi_rx_disabled(dev_priv, pipe);
1536
1537         /* Ports must be off as well */
1538         assert_pch_ports_disabled(dev_priv, pipe);
1539
1540         reg = TRANSCONF(pipe);
1541         val = I915_READ(reg);
1542         val &= ~TRANS_ENABLE;
1543         I915_WRITE(reg, val);
1544         /* wait for PCH transcoder off, transcoder state */
1545         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1546                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1547 }
1548
1549 /**
1550  * intel_enable_pipe - enable a pipe, asserting requirements
1551  * @dev_priv: i915 private structure
1552  * @pipe: pipe to enable
1553  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1554  *
1555  * Enable @pipe, making sure that various hardware specific requirements
1556  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1557  *
1558  * @pipe should be %PIPE_A or %PIPE_B.
1559  *
1560  * Will wait until the pipe is actually running (i.e. first vblank) before
1561  * returning.
1562  */
1563 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1564                               bool pch_port)
1565 {
1566         int reg;
1567         u32 val;
1568
1569         /*
1570          * A pipe without a PLL won't actually be able to drive bits from
1571          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1572          * need the check.
1573          */
1574         if (!HAS_PCH_SPLIT(dev_priv->dev))
1575                 assert_pll_enabled(dev_priv, pipe);
1576         else {
1577                 if (pch_port) {
1578                         /* if driving the PCH, we need FDI enabled */
1579                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1580                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1581                 }
1582                 /* FIXME: assert CPU port conditions for SNB+ */
1583         }
1584
1585         reg = PIPECONF(pipe);
1586         val = I915_READ(reg);
1587         if (val & PIPECONF_ENABLE)
1588                 return;
1589
1590         I915_WRITE(reg, val | PIPECONF_ENABLE);
1591         intel_wait_for_vblank(dev_priv->dev, pipe);
1592 }
1593
1594 /**
1595  * intel_disable_pipe - disable a pipe, asserting requirements
1596  * @dev_priv: i915 private structure
1597  * @pipe: pipe to disable
1598  *
1599  * Disable @pipe, making sure that various hardware specific requirements
1600  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1601  *
1602  * @pipe should be %PIPE_A or %PIPE_B.
1603  *
1604  * Will wait until the pipe has shut down before returning.
1605  */
1606 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1607                                enum pipe pipe)
1608 {
1609         int reg;
1610         u32 val;
1611
1612         /*
1613          * Make sure planes won't keep trying to pump pixels to us,
1614          * or we might hang the display.
1615          */
1616         assert_planes_disabled(dev_priv, pipe);
1617
1618         /* Don't disable pipe A or pipe A PLLs if needed */
1619         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1620                 return;
1621
1622         reg = PIPECONF(pipe);
1623         val = I915_READ(reg);
1624         if ((val & PIPECONF_ENABLE) == 0)
1625                 return;
1626
1627         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1628         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1629 }
1630
1631 /*
1632  * Plane regs are double buffered, going from enabled->disabled needs a
1633  * trigger in order to latch.  The display address reg provides this.
1634  */
1635 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1636                                       enum plane plane)
1637 {
1638         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1639         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1640 }
1641
1642 /**
1643  * intel_enable_plane - enable a display plane on a given pipe
1644  * @dev_priv: i915 private structure
1645  * @plane: plane to enable
1646  * @pipe: pipe being fed
1647  *
1648  * Enable @plane on @pipe, making sure that @pipe is running first.
1649  */
1650 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1651                                enum plane plane, enum pipe pipe)
1652 {
1653         int reg;
1654         u32 val;
1655
1656         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1657         assert_pipe_enabled(dev_priv, pipe);
1658
1659         reg = DSPCNTR(plane);
1660         val = I915_READ(reg);
1661         if (val & DISPLAY_PLANE_ENABLE)
1662                 return;
1663
1664         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1665         intel_flush_display_plane(dev_priv, plane);
1666         intel_wait_for_vblank(dev_priv->dev, pipe);
1667 }
1668
1669 /**
1670  * intel_disable_plane - disable a display plane
1671  * @dev_priv: i915 private structure
1672  * @plane: plane to disable
1673  * @pipe: pipe consuming the data
1674  *
1675  * Disable @plane; should be an independent operation.
1676  */
1677 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1678                                 enum plane plane, enum pipe pipe)
1679 {
1680         int reg;
1681         u32 val;
1682
1683         reg = DSPCNTR(plane);
1684         val = I915_READ(reg);
1685         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1686                 return;
1687
1688         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1689         intel_flush_display_plane(dev_priv, plane);
1690         intel_wait_for_vblank(dev_priv->dev, pipe);
1691 }
1692
1693 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1694                            enum pipe pipe, int reg, u32 port_sel)
1695 {
1696         u32 val = I915_READ(reg);
1697         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1698                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1699                 I915_WRITE(reg, val & ~DP_PORT_EN);
1700         }
1701 }
1702
1703 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1704                              enum pipe pipe, int reg)
1705 {
1706         u32 val = I915_READ(reg);
1707         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1708                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1709                               reg, pipe);
1710                 I915_WRITE(reg, val & ~PORT_ENABLE);
1711         }
1712 }
1713
1714 /* Disable any ports connected to this transcoder */
1715 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1716                                     enum pipe pipe)
1717 {
1718         u32 reg, val;
1719
1720         val = I915_READ(PCH_PP_CONTROL);
1721         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1722
1723         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1724         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1725         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1726
1727         reg = PCH_ADPA;
1728         val = I915_READ(reg);
1729         if (adpa_pipe_enabled(dev_priv, val, pipe))
1730                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1731
1732         reg = PCH_LVDS;
1733         val = I915_READ(reg);
1734         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1735                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1736                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1737                 POSTING_READ(reg);
1738                 udelay(100);
1739         }
1740
1741         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1742         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1743         disable_pch_hdmi(dev_priv, pipe, HDMID);
1744 }
1745
1746 int
1747 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1748                            struct drm_i915_gem_object *obj,
1749                            struct intel_ring_buffer *pipelined)
1750 {
1751         struct drm_i915_private *dev_priv = dev->dev_private;
1752         u32 alignment;
1753         int ret;
1754
1755         switch (obj->tiling_mode) {
1756         case I915_TILING_NONE:
1757                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1758                         alignment = 128 * 1024;
1759                 else if (INTEL_INFO(dev)->gen >= 4)
1760                         alignment = 4 * 1024;
1761                 else
1762                         alignment = 64 * 1024;
1763                 break;
1764         case I915_TILING_X:
1765                 /* pin() will align the object as required by fence */
1766                 alignment = 0;
1767                 break;
1768         case I915_TILING_Y:
1769                 /* FIXME: Is this true? */
1770                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1771                 return -EINVAL;
1772         default:
1773                 BUG();
1774         }
1775
1776         dev_priv->mm.interruptible = false;
1777         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1778         if (ret)
1779                 goto err_interruptible;
1780
1781         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1782          * fence, whereas 965+ only requires a fence if using
1783          * framebuffer compression.  For simplicity, we always install
1784          * a fence as the cost is not that onerous.
1785          */
1786         ret = i915_gem_object_get_fence(obj);
1787         if (ret)
1788                 goto err_unpin;
1789
1790         i915_gem_object_pin_fence(obj);
1791
1792         dev_priv->mm.interruptible = true;
1793         return 0;
1794
1795 err_unpin:
1796         i915_gem_object_unpin(obj);
1797 err_interruptible:
1798         dev_priv->mm.interruptible = true;
1799         return ret;
1800 }
1801
1802 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1803 {
1804         i915_gem_object_unpin_fence(obj);
1805         i915_gem_object_unpin(obj);
1806 }
1807
1808 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1809                              int x, int y)
1810 {
1811         struct drm_device *dev = crtc->dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1814         struct intel_framebuffer *intel_fb;
1815         struct drm_i915_gem_object *obj;
1816         int plane = intel_crtc->plane;
1817         unsigned long Start, Offset;
1818         u32 dspcntr;
1819         u32 reg;
1820
1821         switch (plane) {
1822         case 0:
1823         case 1:
1824                 break;
1825         default:
1826                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1827                 return -EINVAL;
1828         }
1829
1830         intel_fb = to_intel_framebuffer(fb);
1831         obj = intel_fb->obj;
1832
1833         reg = DSPCNTR(plane);
1834         dspcntr = I915_READ(reg);
1835         /* Mask out pixel format bits in case we change it */
1836         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1837         switch (fb->bits_per_pixel) {
1838         case 8:
1839                 dspcntr |= DISPPLANE_8BPP;
1840                 break;
1841         case 16:
1842                 if (fb->depth == 15)
1843                         dspcntr |= DISPPLANE_15_16BPP;
1844                 else
1845                         dspcntr |= DISPPLANE_16BPP;
1846                 break;
1847         case 24:
1848         case 32:
1849                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1850                 break;
1851         default:
1852                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1853                 return -EINVAL;
1854         }
1855         if (INTEL_INFO(dev)->gen >= 4) {
1856                 if (obj->tiling_mode != I915_TILING_NONE)
1857                         dspcntr |= DISPPLANE_TILED;
1858                 else
1859                         dspcntr &= ~DISPPLANE_TILED;
1860         }
1861
1862         I915_WRITE(reg, dspcntr);
1863
1864         Start = obj->gtt_offset;
1865         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1866
1867         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1868                       Start, Offset, x, y, fb->pitches[0]);
1869         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1870         if (INTEL_INFO(dev)->gen >= 4) {
1871                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1873                 I915_WRITE(DSPADDR(plane), Offset);
1874         } else
1875                 I915_WRITE(DSPADDR(plane), Start + Offset);
1876         POSTING_READ(reg);
1877
1878         return 0;
1879 }
1880
1881 static int ironlake_update_plane(struct drm_crtc *crtc,
1882                                  struct drm_framebuffer *fb, int x, int y)
1883 {
1884         struct drm_device *dev = crtc->dev;
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1887         struct intel_framebuffer *intel_fb;
1888         struct drm_i915_gem_object *obj;
1889         int plane = intel_crtc->plane;
1890         unsigned long Start, Offset;
1891         u32 dspcntr;
1892         u32 reg;
1893
1894         switch (plane) {
1895         case 0:
1896         case 1:
1897         case 2:
1898                 break;
1899         default:
1900                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1901                 return -EINVAL;
1902         }
1903
1904         intel_fb = to_intel_framebuffer(fb);
1905         obj = intel_fb->obj;
1906
1907         reg = DSPCNTR(plane);
1908         dspcntr = I915_READ(reg);
1909         /* Mask out pixel format bits in case we change it */
1910         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911         switch (fb->bits_per_pixel) {
1912         case 8:
1913                 dspcntr |= DISPPLANE_8BPP;
1914                 break;
1915         case 16:
1916                 if (fb->depth != 16)
1917                         return -EINVAL;
1918
1919                 dspcntr |= DISPPLANE_16BPP;
1920                 break;
1921         case 24:
1922         case 32:
1923                 if (fb->depth == 24)
1924                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1925                 else if (fb->depth == 30)
1926                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1927                 else
1928                         return -EINVAL;
1929                 break;
1930         default:
1931                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1932                 return -EINVAL;
1933         }
1934
1935         if (obj->tiling_mode != I915_TILING_NONE)
1936                 dspcntr |= DISPPLANE_TILED;
1937         else
1938                 dspcntr &= ~DISPPLANE_TILED;
1939
1940         /* must disable */
1941         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1942
1943         I915_WRITE(reg, dspcntr);
1944
1945         Start = obj->gtt_offset;
1946         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1947
1948         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1949                       Start, Offset, x, y, fb->pitches[0]);
1950         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1951         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1952         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1953         I915_WRITE(DSPADDR(plane), Offset);
1954         POSTING_READ(reg);
1955
1956         return 0;
1957 }
1958
1959 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1960 static int
1961 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1962                            int x, int y, enum mode_set_atomic state)
1963 {
1964         struct drm_device *dev = crtc->dev;
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966
1967         if (dev_priv->display.disable_fbc)
1968                 dev_priv->display.disable_fbc(dev);
1969         intel_increase_pllclock(crtc);
1970
1971         return dev_priv->display.update_plane(crtc, fb, x, y);
1972 }
1973
1974 static int
1975 intel_finish_fb(struct drm_framebuffer *old_fb)
1976 {
1977         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1978         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1979         bool was_interruptible = dev_priv->mm.interruptible;
1980         int ret;
1981
1982         wait_event(dev_priv->pending_flip_queue,
1983                    atomic_read(&dev_priv->mm.wedged) ||
1984                    atomic_read(&obj->pending_flip) == 0);
1985
1986         /* Big Hammer, we also need to ensure that any pending
1987          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1988          * current scanout is retired before unpinning the old
1989          * framebuffer.
1990          *
1991          * This should only fail upon a hung GPU, in which case we
1992          * can safely continue.
1993          */
1994         dev_priv->mm.interruptible = false;
1995         ret = i915_gem_object_finish_gpu(obj);
1996         dev_priv->mm.interruptible = was_interruptible;
1997
1998         return ret;
1999 }
2000
2001 static int
2002 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2003                     struct drm_framebuffer *old_fb)
2004 {
2005         struct drm_device *dev = crtc->dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         struct drm_i915_master_private *master_priv;
2008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2009         int ret;
2010
2011         /* no fb bound */
2012         if (!crtc->fb) {
2013                 DRM_ERROR("No FB bound\n");
2014                 return 0;
2015         }
2016
2017         if(intel_crtc->plane > dev_priv->num_pipe) {
2018                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2019                                 intel_crtc->plane,
2020                                 dev_priv->num_pipe);
2021                 return -EINVAL;
2022         }
2023
2024         mutex_lock(&dev->struct_mutex);
2025         ret = intel_pin_and_fence_fb_obj(dev,
2026                                          to_intel_framebuffer(crtc->fb)->obj,
2027                                          NULL);
2028         if (ret != 0) {
2029                 mutex_unlock(&dev->struct_mutex);
2030                 DRM_ERROR("pin & fence failed\n");
2031                 return ret;
2032         }
2033
2034         if (old_fb)
2035                 intel_finish_fb(old_fb);
2036
2037         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2038         if (ret) {
2039                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2040                 mutex_unlock(&dev->struct_mutex);
2041                 DRM_ERROR("failed to update base address\n");
2042                 return ret;
2043         }
2044
2045         if (old_fb) {
2046                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2047                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2048         }
2049
2050         intel_update_fbc(dev);
2051         mutex_unlock(&dev->struct_mutex);
2052
2053         if (!dev->primary->master)
2054                 return 0;
2055
2056         master_priv = dev->primary->master->driver_priv;
2057         if (!master_priv->sarea_priv)
2058                 return 0;
2059
2060         if (intel_crtc->pipe) {
2061                 master_priv->sarea_priv->pipeB_x = x;
2062                 master_priv->sarea_priv->pipeB_y = y;
2063         } else {
2064                 master_priv->sarea_priv->pipeA_x = x;
2065                 master_priv->sarea_priv->pipeA_y = y;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2072 {
2073         struct drm_device *dev = crtc->dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075         u32 dpa_ctl;
2076
2077         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2078         dpa_ctl = I915_READ(DP_A);
2079         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2080
2081         if (clock < 200000) {
2082                 u32 temp;
2083                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2084                 /* workaround for 160Mhz:
2085                    1) program 0x4600c bits 15:0 = 0x8124
2086                    2) program 0x46010 bit 0 = 1
2087                    3) program 0x46034 bit 24 = 1
2088                    4) program 0x64000 bit 14 = 1
2089                    */
2090                 temp = I915_READ(0x4600c);
2091                 temp &= 0xffff0000;
2092                 I915_WRITE(0x4600c, temp | 0x8124);
2093
2094                 temp = I915_READ(0x46010);
2095                 I915_WRITE(0x46010, temp | 1);
2096
2097                 temp = I915_READ(0x46034);
2098                 I915_WRITE(0x46034, temp | (1 << 24));
2099         } else {
2100                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2101         }
2102         I915_WRITE(DP_A, dpa_ctl);
2103
2104         POSTING_READ(DP_A);
2105         udelay(500);
2106 }
2107
2108 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2113         int pipe = intel_crtc->pipe;
2114         u32 reg, temp;
2115
2116         /* enable normal train */
2117         reg = FDI_TX_CTL(pipe);
2118         temp = I915_READ(reg);
2119         if (IS_IVYBRIDGE(dev)) {
2120                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2121                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2122         } else {
2123                 temp &= ~FDI_LINK_TRAIN_NONE;
2124                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2125         }
2126         I915_WRITE(reg, temp);
2127
2128         reg = FDI_RX_CTL(pipe);
2129         temp = I915_READ(reg);
2130         if (HAS_PCH_CPT(dev)) {
2131                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2132                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2133         } else {
2134                 temp &= ~FDI_LINK_TRAIN_NONE;
2135                 temp |= FDI_LINK_TRAIN_NONE;
2136         }
2137         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2138
2139         /* wait one idle pattern time */
2140         POSTING_READ(reg);
2141         udelay(1000);
2142
2143         /* IVB wants error correction enabled */
2144         if (IS_IVYBRIDGE(dev))
2145                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2146                            FDI_FE_ERRC_ENABLE);
2147 }
2148
2149 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2150 {
2151         struct drm_i915_private *dev_priv = dev->dev_private;
2152         u32 flags = I915_READ(SOUTH_CHICKEN1);
2153
2154         flags |= FDI_PHASE_SYNC_OVR(pipe);
2155         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2156         flags |= FDI_PHASE_SYNC_EN(pipe);
2157         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2158         POSTING_READ(SOUTH_CHICKEN1);
2159 }
2160
2161 /* The FDI link training functions for ILK/Ibexpeak. */
2162 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = crtc->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167         int pipe = intel_crtc->pipe;
2168         int plane = intel_crtc->plane;
2169         u32 reg, temp, tries;
2170
2171         /* FDI needs bits from pipe & plane first */
2172         assert_pipe_enabled(dev_priv, pipe);
2173         assert_plane_enabled(dev_priv, plane);
2174
2175         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2176            for train result */
2177         reg = FDI_RX_IMR(pipe);
2178         temp = I915_READ(reg);
2179         temp &= ~FDI_RX_SYMBOL_LOCK;
2180         temp &= ~FDI_RX_BIT_LOCK;
2181         I915_WRITE(reg, temp);
2182         I915_READ(reg);
2183         udelay(150);
2184
2185         /* enable CPU FDI TX and PCH FDI RX */
2186         reg = FDI_TX_CTL(pipe);
2187         temp = I915_READ(reg);
2188         temp &= ~(7 << 19);
2189         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2190         temp &= ~FDI_LINK_TRAIN_NONE;
2191         temp |= FDI_LINK_TRAIN_PATTERN_1;
2192         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2193
2194         reg = FDI_RX_CTL(pipe);
2195         temp = I915_READ(reg);
2196         temp &= ~FDI_LINK_TRAIN_NONE;
2197         temp |= FDI_LINK_TRAIN_PATTERN_1;
2198         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2199
2200         POSTING_READ(reg);
2201         udelay(150);
2202
2203         /* Ironlake workaround, enable clock pointer after FDI enable*/
2204         if (HAS_PCH_IBX(dev)) {
2205                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2206                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2207                            FDI_RX_PHASE_SYNC_POINTER_EN);
2208         }
2209
2210         reg = FDI_RX_IIR(pipe);
2211         for (tries = 0; tries < 5; tries++) {
2212                 temp = I915_READ(reg);
2213                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2214
2215                 if ((temp & FDI_RX_BIT_LOCK)) {
2216                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2217                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2218                         break;
2219                 }
2220         }
2221         if (tries == 5)
2222                 DRM_ERROR("FDI train 1 fail!\n");
2223
2224         /* Train 2 */
2225         reg = FDI_TX_CTL(pipe);
2226         temp = I915_READ(reg);
2227         temp &= ~FDI_LINK_TRAIN_NONE;
2228         temp |= FDI_LINK_TRAIN_PATTERN_2;
2229         I915_WRITE(reg, temp);
2230
2231         reg = FDI_RX_CTL(pipe);
2232         temp = I915_READ(reg);
2233         temp &= ~FDI_LINK_TRAIN_NONE;
2234         temp |= FDI_LINK_TRAIN_PATTERN_2;
2235         I915_WRITE(reg, temp);
2236
2237         POSTING_READ(reg);
2238         udelay(150);
2239
2240         reg = FDI_RX_IIR(pipe);
2241         for (tries = 0; tries < 5; tries++) {
2242                 temp = I915_READ(reg);
2243                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2244
2245                 if (temp & FDI_RX_SYMBOL_LOCK) {
2246                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2247                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2248                         break;
2249                 }
2250         }
2251         if (tries == 5)
2252                 DRM_ERROR("FDI train 2 fail!\n");
2253
2254         DRM_DEBUG_KMS("FDI train done\n");
2255
2256 }
2257
2258 static const int snb_b_fdi_train_param[] = {
2259         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2260         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2261         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2262         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2263 };
2264
2265 /* The FDI link training functions for SNB/Cougarpoint. */
2266 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271         int pipe = intel_crtc->pipe;
2272         u32 reg, temp, i, retry;
2273
2274         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2275            for train result */
2276         reg = FDI_RX_IMR(pipe);
2277         temp = I915_READ(reg);
2278         temp &= ~FDI_RX_SYMBOL_LOCK;
2279         temp &= ~FDI_RX_BIT_LOCK;
2280         I915_WRITE(reg, temp);
2281
2282         POSTING_READ(reg);
2283         udelay(150);
2284
2285         /* enable CPU FDI TX and PCH FDI RX */
2286         reg = FDI_TX_CTL(pipe);
2287         temp = I915_READ(reg);
2288         temp &= ~(7 << 19);
2289         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2290         temp &= ~FDI_LINK_TRAIN_NONE;
2291         temp |= FDI_LINK_TRAIN_PATTERN_1;
2292         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2293         /* SNB-B */
2294         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2295         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2296
2297         reg = FDI_RX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         if (HAS_PCH_CPT(dev)) {
2300                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2302         } else {
2303                 temp &= ~FDI_LINK_TRAIN_NONE;
2304                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2305         }
2306         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2307
2308         POSTING_READ(reg);
2309         udelay(150);
2310
2311         if (HAS_PCH_CPT(dev))
2312                 cpt_phase_pointer_enable(dev, pipe);
2313
2314         for (i = 0; i < 4; i++) {
2315                 reg = FDI_TX_CTL(pipe);
2316                 temp = I915_READ(reg);
2317                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318                 temp |= snb_b_fdi_train_param[i];
2319                 I915_WRITE(reg, temp);
2320
2321                 POSTING_READ(reg);
2322                 udelay(500);
2323
2324                 for (retry = 0; retry < 5; retry++) {
2325                         reg = FDI_RX_IIR(pipe);
2326                         temp = I915_READ(reg);
2327                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2328                         if (temp & FDI_RX_BIT_LOCK) {
2329                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2330                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2331                                 break;
2332                         }
2333                         udelay(50);
2334                 }
2335                 if (retry < 5)
2336                         break;
2337         }
2338         if (i == 4)
2339                 DRM_ERROR("FDI train 1 fail!\n");
2340
2341         /* Train 2 */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~FDI_LINK_TRAIN_NONE;
2345         temp |= FDI_LINK_TRAIN_PATTERN_2;
2346         if (IS_GEN6(dev)) {
2347                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2348                 /* SNB-B */
2349                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2350         }
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (HAS_PCH_CPT(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2361         }
2362         I915_WRITE(reg, temp);
2363
2364         POSTING_READ(reg);
2365         udelay(150);
2366
2367         for (i = 0; i < 4; i++) {
2368                 reg = FDI_TX_CTL(pipe);
2369                 temp = I915_READ(reg);
2370                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2371                 temp |= snb_b_fdi_train_param[i];
2372                 I915_WRITE(reg, temp);
2373
2374                 POSTING_READ(reg);
2375                 udelay(500);
2376
2377                 for (retry = 0; retry < 5; retry++) {
2378                         reg = FDI_RX_IIR(pipe);
2379                         temp = I915_READ(reg);
2380                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381                         if (temp & FDI_RX_SYMBOL_LOCK) {
2382                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2384                                 break;
2385                         }
2386                         udelay(50);
2387                 }
2388                 if (retry < 5)
2389                         break;
2390         }
2391         if (i == 4)
2392                 DRM_ERROR("FDI train 2 fail!\n");
2393
2394         DRM_DEBUG_KMS("FDI train done.\n");
2395 }
2396
2397 /* Manual link training for Ivy Bridge A0 parts */
2398 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         u32 reg, temp, i;
2405
2406         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2407            for train result */
2408         reg = FDI_RX_IMR(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_RX_SYMBOL_LOCK;
2411         temp &= ~FDI_RX_BIT_LOCK;
2412         I915_WRITE(reg, temp);
2413
2414         POSTING_READ(reg);
2415         udelay(150);
2416
2417         /* enable CPU FDI TX and PCH FDI RX */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~(7 << 19);
2421         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2422         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2423         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2424         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2426         temp |= FDI_COMPOSITE_SYNC;
2427         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2428
2429         reg = FDI_RX_CTL(pipe);
2430         temp = I915_READ(reg);
2431         temp &= ~FDI_LINK_TRAIN_AUTO;
2432         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2434         temp |= FDI_COMPOSITE_SYNC;
2435         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         if (HAS_PCH_CPT(dev))
2441                 cpt_phase_pointer_enable(dev, pipe);
2442
2443         for (i = 0; i < 4; i++) {
2444                 reg = FDI_TX_CTL(pipe);
2445                 temp = I915_READ(reg);
2446                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447                 temp |= snb_b_fdi_train_param[i];
2448                 I915_WRITE(reg, temp);
2449
2450                 POSTING_READ(reg);
2451                 udelay(500);
2452
2453                 reg = FDI_RX_IIR(pipe);
2454                 temp = I915_READ(reg);
2455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457                 if (temp & FDI_RX_BIT_LOCK ||
2458                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2459                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2460                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2461                         break;
2462                 }
2463         }
2464         if (i == 4)
2465                 DRM_ERROR("FDI train 1 fail!\n");
2466
2467         /* Train 2 */
2468         reg = FDI_TX_CTL(pipe);
2469         temp = I915_READ(reg);
2470         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2471         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2472         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         for (i = 0; i < 4; i++) {
2486                 reg = FDI_TX_CTL(pipe);
2487                 temp = I915_READ(reg);
2488                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2489                 temp |= snb_b_fdi_train_param[i];
2490                 I915_WRITE(reg, temp);
2491
2492                 POSTING_READ(reg);
2493                 udelay(500);
2494
2495                 reg = FDI_RX_IIR(pipe);
2496                 temp = I915_READ(reg);
2497                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499                 if (temp & FDI_RX_SYMBOL_LOCK) {
2500                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2501                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2502                         break;
2503                 }
2504         }
2505         if (i == 4)
2506                 DRM_ERROR("FDI train 2 fail!\n");
2507
2508         DRM_DEBUG_KMS("FDI train done.\n");
2509 }
2510
2511 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp;
2518
2519         /* Write the TU size bits so error detection works */
2520         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2521                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2522
2523         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2524         reg = FDI_RX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~((0x7 << 19) | (0x7 << 16));
2527         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2528         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2529         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2530
2531         POSTING_READ(reg);
2532         udelay(200);
2533
2534         /* Switch from Rawclk to PCDclk */
2535         temp = I915_READ(reg);
2536         I915_WRITE(reg, temp | FDI_PCDCLK);
2537
2538         POSTING_READ(reg);
2539         udelay(200);
2540
2541         /* On Haswell, the PLL configuration for ports and pipes is handled
2542          * separately, as part of DDI setup */
2543         if (!IS_HASWELL(dev)) {
2544                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2545                 reg = FDI_TX_CTL(pipe);
2546                 temp = I915_READ(reg);
2547                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2548                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2549
2550                         POSTING_READ(reg);
2551                         udelay(100);
2552                 }
2553         }
2554 }
2555
2556 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2557 {
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         u32 flags = I915_READ(SOUTH_CHICKEN1);
2560
2561         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2562         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2563         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2564         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2565         POSTING_READ(SOUTH_CHICKEN1);
2566 }
2567 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct drm_i915_private *dev_priv = dev->dev_private;
2571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572         int pipe = intel_crtc->pipe;
2573         u32 reg, temp;
2574
2575         /* disable CPU FDI tx and PCH FDI rx */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2579         POSTING_READ(reg);
2580
2581         reg = FDI_RX_CTL(pipe);
2582         temp = I915_READ(reg);
2583         temp &= ~(0x7 << 16);
2584         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2585         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2586
2587         POSTING_READ(reg);
2588         udelay(100);
2589
2590         /* Ironlake workaround, disable clock pointer after downing FDI */
2591         if (HAS_PCH_IBX(dev)) {
2592                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2593                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2594                            I915_READ(FDI_RX_CHICKEN(pipe) &
2595                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2596         } else if (HAS_PCH_CPT(dev)) {
2597                 cpt_phase_pointer_disable(dev, pipe);
2598         }
2599
2600         /* still set train pattern 1 */
2601         reg = FDI_TX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_LINK_TRAIN_NONE;
2604         temp |= FDI_LINK_TRAIN_PATTERN_1;
2605         I915_WRITE(reg, temp);
2606
2607         reg = FDI_RX_CTL(pipe);
2608         temp = I915_READ(reg);
2609         if (HAS_PCH_CPT(dev)) {
2610                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2612         } else {
2613                 temp &= ~FDI_LINK_TRAIN_NONE;
2614                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2615         }
2616         /* BPC in FDI rx is consistent with that in PIPECONF */
2617         temp &= ~(0x07 << 16);
2618         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2619         I915_WRITE(reg, temp);
2620
2621         POSTING_READ(reg);
2622         udelay(100);
2623 }
2624
2625 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2626 {
2627         struct drm_device *dev = crtc->dev;
2628
2629         if (crtc->fb == NULL)
2630                 return;
2631
2632         mutex_lock(&dev->struct_mutex);
2633         intel_finish_fb(crtc->fb);
2634         mutex_unlock(&dev->struct_mutex);
2635 }
2636
2637 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2638 {
2639         struct drm_device *dev = crtc->dev;
2640         struct drm_mode_config *mode_config = &dev->mode_config;
2641         struct intel_encoder *encoder;
2642
2643         /*
2644          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2645          * must be driven by its own crtc; no sharing is possible.
2646          */
2647         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2648                 if (encoder->base.crtc != crtc)
2649                         continue;
2650
2651                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2652                  * CPU handles all others */
2653                 if (IS_HASWELL(dev)) {
2654                         /* It is still unclear how this will work on PPT, so throw up a warning */
2655                         WARN_ON(!HAS_PCH_LPT(dev));
2656
2657                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2658                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2659                                 return true;
2660                         } else {
2661                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2662                                                 encoder->type);
2663                                 return false;
2664                         }
2665                 }
2666
2667                 switch (encoder->type) {
2668                 case INTEL_OUTPUT_EDP:
2669                         if (!intel_encoder_is_pch_edp(&encoder->base))
2670                                 return false;
2671                         continue;
2672                 }
2673         }
2674
2675         return true;
2676 }
2677
2678 /*
2679  * Enable PCH resources required for PCH ports:
2680  *   - PCH PLLs
2681  *   - FDI training & RX/TX
2682  *   - update transcoder timings
2683  *   - DP transcoding bits
2684  *   - transcoder
2685  */
2686 static void ironlake_pch_enable(struct drm_crtc *crtc)
2687 {
2688         struct drm_device *dev = crtc->dev;
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691         int pipe = intel_crtc->pipe;
2692         u32 reg, temp;
2693
2694         /* For PCH output, training FDI link */
2695         dev_priv->display.fdi_link_train(crtc);
2696
2697         intel_enable_pch_pll(intel_crtc);
2698
2699         if (HAS_PCH_CPT(dev)) {
2700                 u32 sel;
2701
2702                 temp = I915_READ(PCH_DPLL_SEL);
2703                 switch (pipe) {
2704                 default:
2705                 case 0:
2706                         temp |= TRANSA_DPLL_ENABLE;
2707                         sel = TRANSA_DPLLB_SEL;
2708                         break;
2709                 case 1:
2710                         temp |= TRANSB_DPLL_ENABLE;
2711                         sel = TRANSB_DPLLB_SEL;
2712                         break;
2713                 case 2:
2714                         temp |= TRANSC_DPLL_ENABLE;
2715                         sel = TRANSC_DPLLB_SEL;
2716                         break;
2717                 }
2718                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2719                         temp |= sel;
2720                 else
2721                         temp &= ~sel;
2722                 I915_WRITE(PCH_DPLL_SEL, temp);
2723         }
2724
2725         /* set transcoder timing, panel must allow it */
2726         assert_panel_unlocked(dev_priv, pipe);
2727         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2728         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2729         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2730
2731         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2732         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2733         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2734         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2735
2736         if (!IS_HASWELL(dev))
2737                 intel_fdi_normal_train(crtc);
2738
2739         /* For PCH DP, enable TRANS_DP_CTL */
2740         if (HAS_PCH_CPT(dev) &&
2741             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2742              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2743                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2744                 reg = TRANS_DP_CTL(pipe);
2745                 temp = I915_READ(reg);
2746                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2747                           TRANS_DP_SYNC_MASK |
2748                           TRANS_DP_BPC_MASK);
2749                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2750                          TRANS_DP_ENH_FRAMING);
2751                 temp |= bpc << 9; /* same format but at 11:9 */
2752
2753                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2754                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2755                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2756                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2757
2758                 switch (intel_trans_dp_port_sel(crtc)) {
2759                 case PCH_DP_B:
2760                         temp |= TRANS_DP_PORT_SEL_B;
2761                         break;
2762                 case PCH_DP_C:
2763                         temp |= TRANS_DP_PORT_SEL_C;
2764                         break;
2765                 case PCH_DP_D:
2766                         temp |= TRANS_DP_PORT_SEL_D;
2767                         break;
2768                 default:
2769                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2770                         temp |= TRANS_DP_PORT_SEL_B;
2771                         break;
2772                 }
2773
2774                 I915_WRITE(reg, temp);
2775         }
2776
2777         intel_enable_transcoder(dev_priv, pipe);
2778 }
2779
2780 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2781 {
2782         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2783
2784         if (pll == NULL)
2785                 return;
2786
2787         if (pll->refcount == 0) {
2788                 WARN(1, "bad PCH PLL refcount\n");
2789                 return;
2790         }
2791
2792         --pll->refcount;
2793         intel_crtc->pch_pll = NULL;
2794 }
2795
2796 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2797 {
2798         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2799         struct intel_pch_pll *pll;
2800         int i;
2801
2802         pll = intel_crtc->pch_pll;
2803         if (pll) {
2804                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2805                               intel_crtc->base.base.id, pll->pll_reg);
2806                 goto prepare;
2807         }
2808
2809         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2810                 pll = &dev_priv->pch_plls[i];
2811
2812                 /* Only want to check enabled timings first */
2813                 if (pll->refcount == 0)
2814                         continue;
2815
2816                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2817                     fp == I915_READ(pll->fp0_reg)) {
2818                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2819                                       intel_crtc->base.base.id,
2820                                       pll->pll_reg, pll->refcount, pll->active);
2821
2822                         goto found;
2823                 }
2824         }
2825
2826         /* Ok no matching timings, maybe there's a free one? */
2827         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2828                 pll = &dev_priv->pch_plls[i];
2829                 if (pll->refcount == 0) {
2830                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2831                                       intel_crtc->base.base.id, pll->pll_reg);
2832                         goto found;
2833                 }
2834         }
2835
2836         return NULL;
2837
2838 found:
2839         intel_crtc->pch_pll = pll;
2840         pll->refcount++;
2841         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2842 prepare: /* separate function? */
2843         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2844
2845         /* Wait for the clocks to stabilize before rewriting the regs */
2846         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2847         POSTING_READ(pll->pll_reg);
2848         udelay(150);
2849
2850         I915_WRITE(pll->fp0_reg, fp);
2851         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2852         pll->on = false;
2853         return pll;
2854 }
2855
2856 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2857 {
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2860         u32 temp;
2861
2862         temp = I915_READ(dslreg);
2863         udelay(500);
2864         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2865                 /* Without this, mode sets may fail silently on FDI */
2866                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2867                 udelay(250);
2868                 I915_WRITE(tc2reg, 0);
2869                 if (wait_for(I915_READ(dslreg) != temp, 5))
2870                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2871         }
2872 }
2873
2874 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879         int pipe = intel_crtc->pipe;
2880         int plane = intel_crtc->plane;
2881         u32 temp;
2882         bool is_pch_port;
2883
2884         if (intel_crtc->active)
2885                 return;
2886
2887         intel_crtc->active = true;
2888         intel_update_watermarks(dev);
2889
2890         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2891                 temp = I915_READ(PCH_LVDS);
2892                 if ((temp & LVDS_PORT_EN) == 0)
2893                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2894         }
2895
2896         is_pch_port = intel_crtc_driving_pch(crtc);
2897
2898         if (is_pch_port)
2899                 ironlake_fdi_pll_enable(crtc);
2900         else
2901                 ironlake_fdi_disable(crtc);
2902
2903         /* Enable panel fitting for LVDS */
2904         if (dev_priv->pch_pf_size &&
2905             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2906                 /* Force use of hard-coded filter coefficients
2907                  * as some pre-programmed values are broken,
2908                  * e.g. x201.
2909                  */
2910                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2911                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2912                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2913         }
2914
2915         /*
2916          * On ILK+ LUT must be loaded before the pipe is running but with
2917          * clocks enabled
2918          */
2919         intel_crtc_load_lut(crtc);
2920
2921         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2922         intel_enable_plane(dev_priv, plane, pipe);
2923
2924         if (is_pch_port)
2925                 ironlake_pch_enable(crtc);
2926
2927         mutex_lock(&dev->struct_mutex);
2928         intel_update_fbc(dev);
2929         mutex_unlock(&dev->struct_mutex);
2930
2931         intel_crtc_update_cursor(crtc, true);
2932 }
2933
2934 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2935 {
2936         struct drm_device *dev = crtc->dev;
2937         struct drm_i915_private *dev_priv = dev->dev_private;
2938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2939         int pipe = intel_crtc->pipe;
2940         int plane = intel_crtc->plane;
2941         u32 reg, temp;
2942
2943         if (!intel_crtc->active)
2944                 return;
2945
2946         intel_crtc_wait_for_pending_flips(crtc);
2947         drm_vblank_off(dev, pipe);
2948         intel_crtc_update_cursor(crtc, false);
2949
2950         intel_disable_plane(dev_priv, plane, pipe);
2951
2952         if (dev_priv->cfb_plane == plane)
2953                 intel_disable_fbc(dev);
2954
2955         intel_disable_pipe(dev_priv, pipe);
2956
2957         /* Disable PF */
2958         I915_WRITE(PF_CTL(pipe), 0);
2959         I915_WRITE(PF_WIN_SZ(pipe), 0);
2960
2961         ironlake_fdi_disable(crtc);
2962
2963         /* This is a horrible layering violation; we should be doing this in
2964          * the connector/encoder ->prepare instead, but we don't always have
2965          * enough information there about the config to know whether it will
2966          * actually be necessary or just cause undesired flicker.
2967          */
2968         intel_disable_pch_ports(dev_priv, pipe);
2969
2970         intel_disable_transcoder(dev_priv, pipe);
2971
2972         if (HAS_PCH_CPT(dev)) {
2973                 /* disable TRANS_DP_CTL */
2974                 reg = TRANS_DP_CTL(pipe);
2975                 temp = I915_READ(reg);
2976                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2977                 temp |= TRANS_DP_PORT_SEL_NONE;
2978                 I915_WRITE(reg, temp);
2979
2980                 /* disable DPLL_SEL */
2981                 temp = I915_READ(PCH_DPLL_SEL);
2982                 switch (pipe) {
2983                 case 0:
2984                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2985                         break;
2986                 case 1:
2987                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2988                         break;
2989                 case 2:
2990                         /* C shares PLL A or B */
2991                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2992                         break;
2993                 default:
2994                         BUG(); /* wtf */
2995                 }
2996                 I915_WRITE(PCH_DPLL_SEL, temp);
2997         }
2998
2999         /* disable PCH DPLL */
3000         intel_disable_pch_pll(intel_crtc);
3001
3002         /* Switch from PCDclk to Rawclk */
3003         reg = FDI_RX_CTL(pipe);
3004         temp = I915_READ(reg);
3005         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3006
3007         /* Disable CPU FDI TX PLL */
3008         reg = FDI_TX_CTL(pipe);
3009         temp = I915_READ(reg);
3010         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3011
3012         POSTING_READ(reg);
3013         udelay(100);
3014
3015         reg = FDI_RX_CTL(pipe);
3016         temp = I915_READ(reg);
3017         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3018
3019         /* Wait for the clocks to turn off. */
3020         POSTING_READ(reg);
3021         udelay(100);
3022
3023         intel_crtc->active = false;
3024         intel_update_watermarks(dev);
3025
3026         mutex_lock(&dev->struct_mutex);
3027         intel_update_fbc(dev);
3028         mutex_unlock(&dev->struct_mutex);
3029 }
3030
3031 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3032 {
3033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034         int pipe = intel_crtc->pipe;
3035         int plane = intel_crtc->plane;
3036
3037         /* XXX: When our outputs are all unaware of DPMS modes other than off
3038          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3039          */
3040         switch (mode) {
3041         case DRM_MODE_DPMS_ON:
3042         case DRM_MODE_DPMS_STANDBY:
3043         case DRM_MODE_DPMS_SUSPEND:
3044                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3045                 ironlake_crtc_enable(crtc);
3046                 break;
3047
3048         case DRM_MODE_DPMS_OFF:
3049                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3050                 ironlake_crtc_disable(crtc);
3051                 break;
3052         }
3053 }
3054
3055 static void ironlake_crtc_off(struct drm_crtc *crtc)
3056 {
3057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058         intel_put_pch_pll(intel_crtc);
3059 }
3060
3061 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3062 {
3063         if (!enable && intel_crtc->overlay) {
3064                 struct drm_device *dev = intel_crtc->base.dev;
3065                 struct drm_i915_private *dev_priv = dev->dev_private;
3066
3067                 mutex_lock(&dev->struct_mutex);
3068                 dev_priv->mm.interruptible = false;
3069                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3070                 dev_priv->mm.interruptible = true;
3071                 mutex_unlock(&dev->struct_mutex);
3072         }
3073
3074         /* Let userspace switch the overlay on again. In most cases userspace
3075          * has to recompute where to put it anyway.
3076          */
3077 }
3078
3079 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3080 {
3081         struct drm_device *dev = crtc->dev;
3082         struct drm_i915_private *dev_priv = dev->dev_private;
3083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084         int pipe = intel_crtc->pipe;
3085         int plane = intel_crtc->plane;
3086
3087         if (intel_crtc->active)
3088                 return;
3089
3090         intel_crtc->active = true;
3091         intel_update_watermarks(dev);
3092
3093         intel_enable_pll(dev_priv, pipe);
3094         intel_enable_pipe(dev_priv, pipe, false);
3095         intel_enable_plane(dev_priv, plane, pipe);
3096
3097         intel_crtc_load_lut(crtc);
3098         intel_update_fbc(dev);
3099
3100         /* Give the overlay scaler a chance to enable if it's on this pipe */
3101         intel_crtc_dpms_overlay(intel_crtc, true);
3102         intel_crtc_update_cursor(crtc, true);
3103 }
3104
3105 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3106 {
3107         struct drm_device *dev = crtc->dev;
3108         struct drm_i915_private *dev_priv = dev->dev_private;
3109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110         int pipe = intel_crtc->pipe;
3111         int plane = intel_crtc->plane;
3112
3113         if (!intel_crtc->active)
3114                 return;
3115
3116         /* Give the overlay scaler a chance to disable if it's on this pipe */
3117         intel_crtc_wait_for_pending_flips(crtc);
3118         drm_vblank_off(dev, pipe);
3119         intel_crtc_dpms_overlay(intel_crtc, false);
3120         intel_crtc_update_cursor(crtc, false);
3121
3122         if (dev_priv->cfb_plane == plane)
3123                 intel_disable_fbc(dev);
3124
3125         intel_disable_plane(dev_priv, plane, pipe);
3126         intel_disable_pipe(dev_priv, pipe);
3127         intel_disable_pll(dev_priv, pipe);
3128
3129         intel_crtc->active = false;
3130         intel_update_fbc(dev);
3131         intel_update_watermarks(dev);
3132 }
3133
3134 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3135 {
3136         /* XXX: When our outputs are all unaware of DPMS modes other than off
3137          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3138          */
3139         switch (mode) {
3140         case DRM_MODE_DPMS_ON:
3141         case DRM_MODE_DPMS_STANDBY:
3142         case DRM_MODE_DPMS_SUSPEND:
3143                 i9xx_crtc_enable(crtc);
3144                 break;
3145         case DRM_MODE_DPMS_OFF:
3146                 i9xx_crtc_disable(crtc);
3147                 break;
3148         }
3149 }
3150
3151 static void i9xx_crtc_off(struct drm_crtc *crtc)
3152 {
3153 }
3154
3155 /**
3156  * Sets the power management mode of the pipe and plane.
3157  */
3158 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         struct drm_i915_master_private *master_priv;
3163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164         int pipe = intel_crtc->pipe;
3165         bool enabled;
3166
3167         if (intel_crtc->dpms_mode == mode)
3168                 return;
3169
3170         intel_crtc->dpms_mode = mode;
3171
3172         dev_priv->display.dpms(crtc, mode);
3173
3174         if (!dev->primary->master)
3175                 return;
3176
3177         master_priv = dev->primary->master->driver_priv;
3178         if (!master_priv->sarea_priv)
3179                 return;
3180
3181         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3182
3183         switch (pipe) {
3184         case 0:
3185                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3186                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3187                 break;
3188         case 1:
3189                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3190                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3191                 break;
3192         default:
3193                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3194                 break;
3195         }
3196 }
3197
3198 static void intel_crtc_disable(struct drm_crtc *crtc)
3199 {
3200         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3201         struct drm_device *dev = crtc->dev;
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203
3204         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3205         dev_priv->display.off(crtc);
3206
3207         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3208         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3209
3210         if (crtc->fb) {
3211                 mutex_lock(&dev->struct_mutex);
3212                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3213                 mutex_unlock(&dev->struct_mutex);
3214         }
3215 }
3216
3217 /* Prepare for a mode set.
3218  *
3219  * Note we could be a lot smarter here.  We need to figure out which outputs
3220  * will be enabled, which disabled (in short, how the config will changes)
3221  * and perform the minimum necessary steps to accomplish that, e.g. updating
3222  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3223  * panel fitting is in the proper state, etc.
3224  */
3225 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3226 {
3227         i9xx_crtc_disable(crtc);
3228 }
3229
3230 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3231 {
3232         i9xx_crtc_enable(crtc);
3233 }
3234
3235 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3236 {
3237         ironlake_crtc_disable(crtc);
3238 }
3239
3240 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3241 {
3242         ironlake_crtc_enable(crtc);
3243 }
3244
3245 void intel_encoder_prepare(struct drm_encoder *encoder)
3246 {
3247         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3248         /* lvds has its own version of prepare see intel_lvds_prepare */
3249         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3250 }
3251
3252 void intel_encoder_commit(struct drm_encoder *encoder)
3253 {
3254         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3255         struct drm_device *dev = encoder->dev;
3256         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3257
3258         /* lvds has its own version of commit see intel_lvds_commit */
3259         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3260
3261         if (HAS_PCH_CPT(dev))
3262                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3263 }
3264
3265 void intel_encoder_destroy(struct drm_encoder *encoder)
3266 {
3267         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3268
3269         drm_encoder_cleanup(encoder);
3270         kfree(intel_encoder);
3271 }
3272
3273 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3274                                   struct drm_display_mode *mode,
3275                                   struct drm_display_mode *adjusted_mode)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278
3279         if (HAS_PCH_SPLIT(dev)) {
3280                 /* FDI link clock is fixed at 2.7G */
3281                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3282                         return false;
3283         }
3284
3285         /* All interlaced capable intel hw wants timings in frames. Note though
3286          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3287          * timings, so we need to be careful not to clobber these.*/
3288         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3289                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3290
3291         return true;
3292 }
3293
3294 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3295 {
3296         return 400000; /* FIXME */
3297 }
3298
3299 static int i945_get_display_clock_speed(struct drm_device *dev)
3300 {
3301         return 400000;
3302 }
3303
3304 static int i915_get_display_clock_speed(struct drm_device *dev)
3305 {
3306         return 333000;
3307 }
3308
3309 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3310 {
3311         return 200000;
3312 }
3313
3314 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3315 {
3316         u16 gcfgc = 0;
3317
3318         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3319
3320         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3321                 return 133000;
3322         else {
3323                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3324                 case GC_DISPLAY_CLOCK_333_MHZ:
3325                         return 333000;
3326                 default:
3327                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3328                         return 190000;
3329                 }
3330         }
3331 }
3332
3333 static int i865_get_display_clock_speed(struct drm_device *dev)
3334 {
3335         return 266000;
3336 }
3337
3338 static int i855_get_display_clock_speed(struct drm_device *dev)
3339 {
3340         u16 hpllcc = 0;
3341         /* Assume that the hardware is in the high speed state.  This
3342          * should be the default.
3343          */
3344         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3345         case GC_CLOCK_133_200:
3346         case GC_CLOCK_100_200:
3347                 return 200000;
3348         case GC_CLOCK_166_250:
3349                 return 250000;
3350         case GC_CLOCK_100_133:
3351                 return 133000;
3352         }
3353
3354         /* Shouldn't happen */
3355         return 0;
3356 }
3357
3358 static int i830_get_display_clock_speed(struct drm_device *dev)
3359 {
3360         return 133000;
3361 }
3362
3363 struct fdi_m_n {
3364         u32        tu;
3365         u32        gmch_m;
3366         u32        gmch_n;
3367         u32        link_m;
3368         u32        link_n;
3369 };
3370
3371 static void
3372 fdi_reduce_ratio(u32 *num, u32 *den)
3373 {
3374         while (*num > 0xffffff || *den > 0xffffff) {
3375                 *num >>= 1;
3376                 *den >>= 1;
3377         }
3378 }
3379
3380 static void
3381 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3382                      int link_clock, struct fdi_m_n *m_n)
3383 {
3384         m_n->tu = 64; /* default size */
3385
3386         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3387         m_n->gmch_m = bits_per_pixel * pixel_clock;
3388         m_n->gmch_n = link_clock * nlanes * 8;
3389         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3390
3391         m_n->link_m = pixel_clock;
3392         m_n->link_n = link_clock;
3393         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3394 }
3395
3396 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3397 {
3398         if (i915_panel_use_ssc >= 0)
3399                 return i915_panel_use_ssc != 0;
3400         return dev_priv->lvds_use_ssc
3401                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3402 }
3403
3404 /**
3405  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3406  * @crtc: CRTC structure
3407  * @mode: requested mode
3408  *
3409  * A pipe may be connected to one or more outputs.  Based on the depth of the
3410  * attached framebuffer, choose a good color depth to use on the pipe.
3411  *
3412  * If possible, match the pipe depth to the fb depth.  In some cases, this
3413  * isn't ideal, because the connected output supports a lesser or restricted
3414  * set of depths.  Resolve that here:
3415  *    LVDS typically supports only 6bpc, so clamp down in that case
3416  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3417  *    Displays may support a restricted set as well, check EDID and clamp as
3418  *      appropriate.
3419  *    DP may want to dither down to 6bpc to fit larger modes
3420  *
3421  * RETURNS:
3422  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3423  * true if they don't match).
3424  */
3425 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3426                                          unsigned int *pipe_bpp,
3427                                          struct drm_display_mode *mode)
3428 {
3429         struct drm_device *dev = crtc->dev;
3430         struct drm_i915_private *dev_priv = dev->dev_private;
3431         struct drm_encoder *encoder;
3432         struct drm_connector *connector;
3433         unsigned int display_bpc = UINT_MAX, bpc;
3434
3435         /* Walk the encoders & connectors on this crtc, get min bpc */
3436         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3437                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3438
3439                 if (encoder->crtc != crtc)
3440                         continue;
3441
3442                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3443                         unsigned int lvds_bpc;
3444
3445                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3446                             LVDS_A3_POWER_UP)
3447                                 lvds_bpc = 8;
3448                         else
3449                                 lvds_bpc = 6;
3450
3451                         if (lvds_bpc < display_bpc) {
3452                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3453                                 display_bpc = lvds_bpc;
3454                         }
3455                         continue;
3456                 }
3457
3458                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3459                         /* Use VBT settings if we have an eDP panel */
3460                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3461
3462                         if (edp_bpc < display_bpc) {
3463                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3464                                 display_bpc = edp_bpc;
3465                         }
3466                         continue;
3467                 }
3468
3469                 /* Not one of the known troublemakers, check the EDID */
3470                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3471                                     head) {
3472                         if (connector->encoder != encoder)
3473                                 continue;
3474
3475                         /* Don't use an invalid EDID bpc value */
3476                         if (connector->display_info.bpc &&
3477                             connector->display_info.bpc < display_bpc) {
3478                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3479                                 display_bpc = connector->display_info.bpc;
3480                         }
3481                 }
3482
3483                 /*
3484                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3485                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3486                  */
3487                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3488                         if (display_bpc > 8 && display_bpc < 12) {
3489                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3490                                 display_bpc = 12;
3491                         } else {
3492                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3493                                 display_bpc = 8;
3494                         }
3495                 }
3496         }
3497
3498         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3499                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3500                 display_bpc = 6;
3501         }
3502
3503         /*
3504          * We could just drive the pipe at the highest bpc all the time and
3505          * enable dithering as needed, but that costs bandwidth.  So choose
3506          * the minimum value that expresses the full color range of the fb but
3507          * also stays within the max display bpc discovered above.
3508          */
3509
3510         switch (crtc->fb->depth) {
3511         case 8:
3512                 bpc = 8; /* since we go through a colormap */
3513                 break;
3514         case 15:
3515         case 16:
3516                 bpc = 6; /* min is 18bpp */
3517                 break;
3518         case 24:
3519                 bpc = 8;
3520                 break;
3521         case 30:
3522                 bpc = 10;
3523                 break;
3524         case 48:
3525                 bpc = 12;
3526                 break;
3527         default:
3528                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3529                 bpc = min((unsigned int)8, display_bpc);
3530                 break;
3531         }
3532
3533         display_bpc = min(display_bpc, bpc);
3534
3535         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3536                       bpc, display_bpc);
3537
3538         *pipe_bpp = display_bpc * 3;
3539
3540         return display_bpc != bpc;
3541 }
3542
3543 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3544 {
3545         struct drm_device *dev = crtc->dev;
3546         struct drm_i915_private *dev_priv = dev->dev_private;
3547         int refclk;
3548
3549         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3550             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3551                 refclk = dev_priv->lvds_ssc_freq * 1000;
3552                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3553                               refclk / 1000);
3554         } else if (!IS_GEN2(dev)) {
3555                 refclk = 96000;
3556         } else {
3557                 refclk = 48000;
3558         }
3559
3560         return refclk;
3561 }
3562
3563 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3564                                       intel_clock_t *clock)
3565 {
3566         /* SDVO TV has fixed PLL values depend on its clock range,
3567            this mirrors vbios setting. */
3568         if (adjusted_mode->clock >= 100000
3569             && adjusted_mode->clock < 140500) {
3570                 clock->p1 = 2;
3571                 clock->p2 = 10;
3572                 clock->n = 3;
3573                 clock->m1 = 16;
3574                 clock->m2 = 8;
3575         } else if (adjusted_mode->clock >= 140500
3576                    && adjusted_mode->clock <= 200000) {
3577                 clock->p1 = 1;
3578                 clock->p2 = 10;
3579                 clock->n = 6;
3580                 clock->m1 = 12;
3581                 clock->m2 = 8;
3582         }
3583 }
3584
3585 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3586                                      intel_clock_t *clock,
3587                                      intel_clock_t *reduced_clock)
3588 {
3589         struct drm_device *dev = crtc->dev;
3590         struct drm_i915_private *dev_priv = dev->dev_private;
3591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592         int pipe = intel_crtc->pipe;
3593         u32 fp, fp2 = 0;
3594
3595         if (IS_PINEVIEW(dev)) {
3596                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3597                 if (reduced_clock)
3598                         fp2 = (1 << reduced_clock->n) << 16 |
3599                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3600         } else {
3601                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3602                 if (reduced_clock)
3603                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3604                                 reduced_clock->m2;
3605         }
3606
3607         I915_WRITE(FP0(pipe), fp);
3608
3609         intel_crtc->lowfreq_avail = false;
3610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3611             reduced_clock && i915_powersave) {
3612                 I915_WRITE(FP1(pipe), fp2);
3613                 intel_crtc->lowfreq_avail = true;
3614         } else {
3615                 I915_WRITE(FP1(pipe), fp);
3616         }
3617 }
3618
3619 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3620                               struct drm_display_mode *adjusted_mode)
3621 {
3622         struct drm_device *dev = crtc->dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625         int pipe = intel_crtc->pipe;
3626         u32 temp;
3627
3628         temp = I915_READ(LVDS);
3629         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3630         if (pipe == 1) {
3631                 temp |= LVDS_PIPEB_SELECT;
3632         } else {
3633                 temp &= ~LVDS_PIPEB_SELECT;
3634         }
3635         /* set the corresponsding LVDS_BORDER bit */
3636         temp |= dev_priv->lvds_border_bits;
3637         /* Set the B0-B3 data pairs corresponding to whether we're going to
3638          * set the DPLLs for dual-channel mode or not.
3639          */
3640         if (clock->p2 == 7)
3641                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3642         else
3643                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3644
3645         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3646          * appropriately here, but we need to look more thoroughly into how
3647          * panels behave in the two modes.
3648          */
3649         /* set the dithering flag on LVDS as needed */
3650         if (INTEL_INFO(dev)->gen >= 4) {
3651                 if (dev_priv->lvds_dither)
3652                         temp |= LVDS_ENABLE_DITHER;
3653                 else
3654                         temp &= ~LVDS_ENABLE_DITHER;
3655         }
3656         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3657         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3658                 temp |= LVDS_HSYNC_POLARITY;
3659         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3660                 temp |= LVDS_VSYNC_POLARITY;
3661         I915_WRITE(LVDS, temp);
3662 }
3663
3664 static void i9xx_update_pll(struct drm_crtc *crtc,
3665                             struct drm_display_mode *mode,
3666                             struct drm_display_mode *adjusted_mode,
3667                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3668                             int num_connectors)
3669 {
3670         struct drm_device *dev = crtc->dev;
3671         struct drm_i915_private *dev_priv = dev->dev_private;
3672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3673         int pipe = intel_crtc->pipe;
3674         u32 dpll;
3675         bool is_sdvo;
3676
3677         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3678                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3679
3680         dpll = DPLL_VGA_MODE_DIS;
3681
3682         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3683                 dpll |= DPLLB_MODE_LVDS;
3684         else
3685                 dpll |= DPLLB_MODE_DAC_SERIAL;
3686         if (is_sdvo) {
3687                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3688                 if (pixel_multiplier > 1) {
3689                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3690                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3691                 }
3692                 dpll |= DPLL_DVO_HIGH_SPEED;
3693         }
3694         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3695                 dpll |= DPLL_DVO_HIGH_SPEED;
3696
3697         /* compute bitmask from p1 value */
3698         if (IS_PINEVIEW(dev))
3699                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3700         else {
3701                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3702                 if (IS_G4X(dev) && reduced_clock)
3703                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3704         }
3705         switch (clock->p2) {
3706         case 5:
3707                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3708                 break;
3709         case 7:
3710                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3711                 break;
3712         case 10:
3713                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3714                 break;
3715         case 14:
3716                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3717                 break;
3718         }
3719         if (INTEL_INFO(dev)->gen >= 4)
3720                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3721
3722         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3723                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3724         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3725                 /* XXX: just matching BIOS for now */
3726                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3727                 dpll |= 3;
3728         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3729                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3730                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3731         else
3732                 dpll |= PLL_REF_INPUT_DREFCLK;
3733
3734         dpll |= DPLL_VCO_ENABLE;
3735         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3736         POSTING_READ(DPLL(pipe));
3737         udelay(150);
3738
3739         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3740          * This is an exception to the general rule that mode_set doesn't turn
3741          * things on.
3742          */
3743         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3744                 intel_update_lvds(crtc, clock, adjusted_mode);
3745
3746         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3747                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3748
3749         I915_WRITE(DPLL(pipe), dpll);
3750
3751         /* Wait for the clocks to stabilize. */
3752         POSTING_READ(DPLL(pipe));
3753         udelay(150);
3754
3755         if (INTEL_INFO(dev)->gen >= 4) {
3756                 u32 temp = 0;
3757                 if (is_sdvo) {
3758                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3759                         if (temp > 1)
3760                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3761                         else
3762                                 temp = 0;
3763                 }
3764                 I915_WRITE(DPLL_MD(pipe), temp);
3765         } else {
3766                 /* The pixel multiplier can only be updated once the
3767                  * DPLL is enabled and the clocks are stable.
3768                  *
3769                  * So write it again.
3770                  */
3771                 I915_WRITE(DPLL(pipe), dpll);
3772         }
3773 }
3774
3775 static void i8xx_update_pll(struct drm_crtc *crtc,
3776                             struct drm_display_mode *adjusted_mode,
3777                             intel_clock_t *clock,
3778                             int num_connectors)
3779 {
3780         struct drm_device *dev = crtc->dev;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783         int pipe = intel_crtc->pipe;
3784         u32 dpll;
3785
3786         dpll = DPLL_VGA_MODE_DIS;
3787
3788         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3789                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3790         } else {
3791                 if (clock->p1 == 2)
3792                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3793                 else
3794                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3795                 if (clock->p2 == 4)
3796                         dpll |= PLL_P2_DIVIDE_BY_4;
3797         }
3798
3799         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3800                 /* XXX: just matching BIOS for now */
3801                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3802                 dpll |= 3;
3803         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3804                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3805                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3806         else
3807                 dpll |= PLL_REF_INPUT_DREFCLK;
3808
3809         dpll |= DPLL_VCO_ENABLE;
3810         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3811         POSTING_READ(DPLL(pipe));
3812         udelay(150);
3813
3814         I915_WRITE(DPLL(pipe), dpll);
3815
3816         /* Wait for the clocks to stabilize. */
3817         POSTING_READ(DPLL(pipe));
3818         udelay(150);
3819
3820         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3821          * This is an exception to the general rule that mode_set doesn't turn
3822          * things on.
3823          */
3824         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3825                 intel_update_lvds(crtc, clock, adjusted_mode);
3826
3827         /* The pixel multiplier can only be updated once the
3828          * DPLL is enabled and the clocks are stable.
3829          *
3830          * So write it again.
3831          */
3832         I915_WRITE(DPLL(pipe), dpll);
3833 }
3834
3835 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3836                               struct drm_display_mode *mode,
3837                               struct drm_display_mode *adjusted_mode,
3838                               int x, int y,
3839                               struct drm_framebuffer *old_fb)
3840 {
3841         struct drm_device *dev = crtc->dev;
3842         struct drm_i915_private *dev_priv = dev->dev_private;
3843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844         int pipe = intel_crtc->pipe;
3845         int plane = intel_crtc->plane;
3846         int refclk, num_connectors = 0;
3847         intel_clock_t clock, reduced_clock;
3848         u32 dspcntr, pipeconf, vsyncshift;
3849         bool ok, has_reduced_clock = false, is_sdvo = false;
3850         bool is_lvds = false, is_tv = false, is_dp = false;
3851         struct drm_mode_config *mode_config = &dev->mode_config;
3852         struct intel_encoder *encoder;
3853         const intel_limit_t *limit;
3854         int ret;
3855
3856         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3857                 if (encoder->base.crtc != crtc)
3858                         continue;
3859
3860                 switch (encoder->type) {
3861                 case INTEL_OUTPUT_LVDS:
3862                         is_lvds = true;
3863                         break;
3864                 case INTEL_OUTPUT_SDVO:
3865                 case INTEL_OUTPUT_HDMI:
3866                         is_sdvo = true;
3867                         if (encoder->needs_tv_clock)
3868                                 is_tv = true;
3869                         break;
3870                 case INTEL_OUTPUT_TVOUT:
3871                         is_tv = true;
3872                         break;
3873                 case INTEL_OUTPUT_DISPLAYPORT:
3874                         is_dp = true;
3875                         break;
3876                 }
3877
3878                 num_connectors++;
3879         }
3880
3881         refclk = i9xx_get_refclk(crtc, num_connectors);
3882
3883         /*
3884          * Returns a set of divisors for the desired target clock with the given
3885          * refclk, or FALSE.  The returned values represent the clock equation:
3886          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3887          */
3888         limit = intel_limit(crtc, refclk);
3889         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3890                              &clock);
3891         if (!ok) {
3892                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3893                 return -EINVAL;
3894         }
3895
3896         /* Ensure that the cursor is valid for the new mode before changing... */
3897         intel_crtc_update_cursor(crtc, true);
3898
3899         if (is_lvds && dev_priv->lvds_downclock_avail) {
3900                 /*
3901                  * Ensure we match the reduced clock's P to the target clock.
3902                  * If the clocks don't match, we can't switch the display clock
3903                  * by using the FP0/FP1. In such case we will disable the LVDS
3904                  * downclock feature.
3905                 */
3906                 has_reduced_clock = limit->find_pll(limit, crtc,
3907                                                     dev_priv->lvds_downclock,
3908                                                     refclk,
3909                                                     &clock,
3910                                                     &reduced_clock);
3911         }
3912
3913         if (is_sdvo && is_tv)
3914                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3915
3916         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3917                                  &reduced_clock : NULL);
3918
3919         if (IS_GEN2(dev))
3920                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3921         else
3922                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3923                                 has_reduced_clock ? &reduced_clock : NULL,
3924                                 num_connectors);
3925
3926         /* setup pipeconf */
3927         pipeconf = I915_READ(PIPECONF(pipe));
3928
3929         /* Set up the display plane register */
3930         dspcntr = DISPPLANE_GAMMA_ENABLE;
3931
3932         if (pipe == 0)
3933                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3934         else
3935                 dspcntr |= DISPPLANE_SEL_PIPE_B;
3936
3937         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3938                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3939                  * core speed.
3940                  *
3941                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3942                  * pipe == 0 check?
3943                  */
3944                 if (mode->clock >
3945                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3946                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3947                 else
3948                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3949         }
3950
3951         /* default to 8bpc */
3952         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3953         if (is_dp) {
3954                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3955                         pipeconf |= PIPECONF_BPP_6 |
3956                                     PIPECONF_DITHER_EN |
3957                                     PIPECONF_DITHER_TYPE_SP;
3958                 }
3959         }
3960
3961         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3962         drm_mode_debug_printmodeline(mode);
3963
3964         if (HAS_PIPE_CXSR(dev)) {
3965                 if (intel_crtc->lowfreq_avail) {
3966                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3967                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3968                 } else {
3969                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3970                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3971                 }
3972         }
3973
3974         pipeconf &= ~PIPECONF_INTERLACE_MASK;
3975         if (!IS_GEN2(dev) &&
3976             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3977                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3978                 /* the chip adds 2 halflines automatically */
3979                 adjusted_mode->crtc_vtotal -= 1;
3980                 adjusted_mode->crtc_vblank_end -= 1;
3981                 vsyncshift = adjusted_mode->crtc_hsync_start
3982                              - adjusted_mode->crtc_htotal/2;
3983         } else {
3984                 pipeconf |= PIPECONF_PROGRESSIVE;
3985                 vsyncshift = 0;
3986         }
3987
3988         if (!IS_GEN3(dev))
3989                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3990
3991         I915_WRITE(HTOTAL(pipe),
3992                    (adjusted_mode->crtc_hdisplay - 1) |
3993                    ((adjusted_mode->crtc_htotal - 1) << 16));
3994         I915_WRITE(HBLANK(pipe),
3995                    (adjusted_mode->crtc_hblank_start - 1) |
3996                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3997         I915_WRITE(HSYNC(pipe),
3998                    (adjusted_mode->crtc_hsync_start - 1) |
3999                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4000
4001         I915_WRITE(VTOTAL(pipe),
4002                    (adjusted_mode->crtc_vdisplay - 1) |
4003                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4004         I915_WRITE(VBLANK(pipe),
4005                    (adjusted_mode->crtc_vblank_start - 1) |
4006                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4007         I915_WRITE(VSYNC(pipe),
4008                    (adjusted_mode->crtc_vsync_start - 1) |
4009                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4010
4011         /* pipesrc and dspsize control the size that is scaled from,
4012          * which should always be the user's requested size.
4013          */
4014         I915_WRITE(DSPSIZE(plane),
4015                    ((mode->vdisplay - 1) << 16) |
4016                    (mode->hdisplay - 1));
4017         I915_WRITE(DSPPOS(plane), 0);
4018         I915_WRITE(PIPESRC(pipe),
4019                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4020
4021         I915_WRITE(PIPECONF(pipe), pipeconf);
4022         POSTING_READ(PIPECONF(pipe));
4023         intel_enable_pipe(dev_priv, pipe, false);
4024
4025         intel_wait_for_vblank(dev, pipe);
4026
4027         I915_WRITE(DSPCNTR(plane), dspcntr);
4028         POSTING_READ(DSPCNTR(plane));
4029
4030         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4031
4032         intel_update_watermarks(dev);
4033
4034         return ret;
4035 }
4036
4037 /*
4038  * Initialize reference clocks when the driver loads
4039  */
4040 void ironlake_init_pch_refclk(struct drm_device *dev)
4041 {
4042         struct drm_i915_private *dev_priv = dev->dev_private;
4043         struct drm_mode_config *mode_config = &dev->mode_config;
4044         struct intel_encoder *encoder;
4045         u32 temp;
4046         bool has_lvds = false;
4047         bool has_cpu_edp = false;
4048         bool has_pch_edp = false;
4049         bool has_panel = false;
4050         bool has_ck505 = false;
4051         bool can_ssc = false;
4052
4053         /* We need to take the global config into account */
4054         list_for_each_entry(encoder, &mode_config->encoder_list,
4055                             base.head) {
4056                 switch (encoder->type) {
4057                 case INTEL_OUTPUT_LVDS:
4058                         has_panel = true;
4059                         has_lvds = true;
4060                         break;
4061                 case INTEL_OUTPUT_EDP:
4062                         has_panel = true;
4063                         if (intel_encoder_is_pch_edp(&encoder->base))
4064                                 has_pch_edp = true;
4065                         else
4066                                 has_cpu_edp = true;
4067                         break;
4068                 }
4069         }
4070
4071         if (HAS_PCH_IBX(dev)) {
4072                 has_ck505 = dev_priv->display_clock_mode;
4073                 can_ssc = has_ck505;
4074         } else {
4075                 has_ck505 = false;
4076                 can_ssc = true;
4077         }
4078
4079         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4080                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4081                       has_ck505);
4082
4083         /* Ironlake: try to setup display ref clock before DPLL
4084          * enabling. This is only under driver's control after
4085          * PCH B stepping, previous chipset stepping should be
4086          * ignoring this setting.
4087          */
4088         temp = I915_READ(PCH_DREF_CONTROL);
4089         /* Always enable nonspread source */
4090         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4091
4092         if (has_ck505)
4093                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4094         else
4095                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4096
4097         if (has_panel) {
4098                 temp &= ~DREF_SSC_SOURCE_MASK;
4099                 temp |= DREF_SSC_SOURCE_ENABLE;
4100
4101                 /* SSC must be turned on before enabling the CPU output  */
4102                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4103                         DRM_DEBUG_KMS("Using SSC on panel\n");
4104                         temp |= DREF_SSC1_ENABLE;
4105                 } else
4106                         temp &= ~DREF_SSC1_ENABLE;
4107
4108                 /* Get SSC going before enabling the outputs */
4109                 I915_WRITE(PCH_DREF_CONTROL, temp);
4110                 POSTING_READ(PCH_DREF_CONTROL);
4111                 udelay(200);
4112
4113                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4114
4115                 /* Enable CPU source on CPU attached eDP */
4116                 if (has_cpu_edp) {
4117                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4118                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4119                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4120                         }
4121                         else
4122                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4123                 } else
4124                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4125
4126                 I915_WRITE(PCH_DREF_CONTROL, temp);
4127                 POSTING_READ(PCH_DREF_CONTROL);
4128                 udelay(200);
4129         } else {
4130                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4131
4132                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4133
4134                 /* Turn off CPU output */
4135                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4136
4137                 I915_WRITE(PCH_DREF_CONTROL, temp);
4138                 POSTING_READ(PCH_DREF_CONTROL);
4139                 udelay(200);
4140
4141                 /* Turn off the SSC source */
4142                 temp &= ~DREF_SSC_SOURCE_MASK;
4143                 temp |= DREF_SSC_SOURCE_DISABLE;
4144
4145                 /* Turn off SSC1 */
4146                 temp &= ~ DREF_SSC1_ENABLE;
4147
4148                 I915_WRITE(PCH_DREF_CONTROL, temp);
4149                 POSTING_READ(PCH_DREF_CONTROL);
4150                 udelay(200);
4151         }
4152 }
4153
4154 static int ironlake_get_refclk(struct drm_crtc *crtc)
4155 {
4156         struct drm_device *dev = crtc->dev;
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct intel_encoder *encoder;
4159         struct drm_mode_config *mode_config = &dev->mode_config;
4160         struct intel_encoder *edp_encoder = NULL;
4161         int num_connectors = 0;
4162         bool is_lvds = false;
4163
4164         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4165                 if (encoder->base.crtc != crtc)
4166                         continue;
4167
4168                 switch (encoder->type) {
4169                 case INTEL_OUTPUT_LVDS:
4170                         is_lvds = true;
4171                         break;
4172                 case INTEL_OUTPUT_EDP:
4173                         edp_encoder = encoder;
4174                         break;
4175                 }
4176                 num_connectors++;
4177         }
4178
4179         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4180                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4181                               dev_priv->lvds_ssc_freq);
4182                 return dev_priv->lvds_ssc_freq * 1000;
4183         }
4184
4185         return 120000;
4186 }
4187
4188 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4189                                   struct drm_display_mode *mode,
4190                                   struct drm_display_mode *adjusted_mode,
4191                                   int x, int y,
4192                                   struct drm_framebuffer *old_fb)
4193 {
4194         struct drm_device *dev = crtc->dev;
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197         int pipe = intel_crtc->pipe;
4198         int plane = intel_crtc->plane;
4199         int refclk, num_connectors = 0;
4200         intel_clock_t clock, reduced_clock;
4201         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4202         bool ok, has_reduced_clock = false, is_sdvo = false;
4203         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4204         struct drm_mode_config *mode_config = &dev->mode_config;
4205         struct intel_encoder *encoder, *edp_encoder = NULL;
4206         const intel_limit_t *limit;
4207         int ret;
4208         struct fdi_m_n m_n = {0};
4209         u32 temp;
4210         int target_clock, pixel_multiplier, lane, link_bw, factor;
4211         unsigned int pipe_bpp;
4212         bool dither;
4213         bool is_cpu_edp = false, is_pch_edp = false;
4214
4215         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4216                 if (encoder->base.crtc != crtc)
4217                         continue;
4218
4219                 switch (encoder->type) {
4220                 case INTEL_OUTPUT_LVDS:
4221                         is_lvds = true;
4222                         break;
4223                 case INTEL_OUTPUT_SDVO:
4224                 case INTEL_OUTPUT_HDMI:
4225                         is_sdvo = true;
4226                         if (encoder->needs_tv_clock)
4227                                 is_tv = true;
4228                         break;
4229                 case INTEL_OUTPUT_TVOUT:
4230                         is_tv = true;
4231                         break;
4232                 case INTEL_OUTPUT_ANALOG:
4233                         is_crt = true;
4234                         break;
4235                 case INTEL_OUTPUT_DISPLAYPORT:
4236                         is_dp = true;
4237                         break;
4238                 case INTEL_OUTPUT_EDP:
4239                         is_dp = true;
4240                         if (intel_encoder_is_pch_edp(&encoder->base))
4241                                 is_pch_edp = true;
4242                         else
4243                                 is_cpu_edp = true;
4244                         edp_encoder = encoder;
4245                         break;
4246                 }
4247
4248                 num_connectors++;
4249         }
4250
4251         refclk = ironlake_get_refclk(crtc);
4252
4253         /*
4254          * Returns a set of divisors for the desired target clock with the given
4255          * refclk, or FALSE.  The returned values represent the clock equation:
4256          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4257          */
4258         limit = intel_limit(crtc, refclk);
4259         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4260                              &clock);
4261         if (!ok) {
4262                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4263                 return -EINVAL;
4264         }
4265
4266         /* Ensure that the cursor is valid for the new mode before changing... */
4267         intel_crtc_update_cursor(crtc, true);
4268
4269         if (is_lvds && dev_priv->lvds_downclock_avail) {
4270                 /*
4271                  * Ensure we match the reduced clock's P to the target clock.
4272                  * If the clocks don't match, we can't switch the display clock
4273                  * by using the FP0/FP1. In such case we will disable the LVDS
4274                  * downclock feature.
4275                 */
4276                 has_reduced_clock = limit->find_pll(limit, crtc,
4277                                                     dev_priv->lvds_downclock,
4278                                                     refclk,
4279                                                     &clock,
4280                                                     &reduced_clock);
4281         }
4282         /* SDVO TV has fixed PLL values depend on its clock range,
4283            this mirrors vbios setting. */
4284         if (is_sdvo && is_tv) {
4285                 if (adjusted_mode->clock >= 100000
4286                     && adjusted_mode->clock < 140500) {
4287                         clock.p1 = 2;
4288                         clock.p2 = 10;
4289                         clock.n = 3;
4290                         clock.m1 = 16;
4291                         clock.m2 = 8;
4292                 } else if (adjusted_mode->clock >= 140500
4293                            && adjusted_mode->clock <= 200000) {
4294                         clock.p1 = 1;
4295                         clock.p2 = 10;
4296                         clock.n = 6;
4297                         clock.m1 = 12;
4298                         clock.m2 = 8;
4299                 }
4300         }
4301
4302         /* FDI link */
4303         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4304         lane = 0;
4305         /* CPU eDP doesn't require FDI link, so just set DP M/N
4306            according to current link config */
4307         if (is_cpu_edp) {
4308                 target_clock = mode->clock;
4309                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4310         } else {
4311                 /* [e]DP over FDI requires target mode clock
4312                    instead of link clock */
4313                 if (is_dp)
4314                         target_clock = mode->clock;
4315                 else
4316                         target_clock = adjusted_mode->clock;
4317
4318                 /* FDI is a binary signal running at ~2.7GHz, encoding
4319                  * each output octet as 10 bits. The actual frequency
4320                  * is stored as a divider into a 100MHz clock, and the
4321                  * mode pixel clock is stored in units of 1KHz.
4322                  * Hence the bw of each lane in terms of the mode signal
4323                  * is:
4324                  */
4325                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4326         }
4327
4328         /* determine panel color depth */
4329         temp = I915_READ(PIPECONF(pipe));
4330         temp &= ~PIPE_BPC_MASK;
4331         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4332         switch (pipe_bpp) {
4333         case 18:
4334                 temp |= PIPE_6BPC;
4335                 break;
4336         case 24:
4337                 temp |= PIPE_8BPC;
4338                 break;
4339         case 30:
4340                 temp |= PIPE_10BPC;
4341                 break;
4342         case 36:
4343                 temp |= PIPE_12BPC;
4344                 break;
4345         default:
4346                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4347                         pipe_bpp);
4348                 temp |= PIPE_8BPC;
4349                 pipe_bpp = 24;
4350                 break;
4351         }
4352
4353         intel_crtc->bpp = pipe_bpp;
4354         I915_WRITE(PIPECONF(pipe), temp);
4355
4356         if (!lane) {
4357                 /*
4358                  * Account for spread spectrum to avoid
4359                  * oversubscribing the link. Max center spread
4360                  * is 2.5%; use 5% for safety's sake.
4361                  */
4362                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4363                 lane = bps / (link_bw * 8) + 1;
4364         }
4365
4366         intel_crtc->fdi_lanes = lane;
4367
4368         if (pixel_multiplier > 1)
4369                 link_bw *= pixel_multiplier;
4370         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4371                              &m_n);
4372
4373         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4374         if (has_reduced_clock)
4375                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4376                         reduced_clock.m2;
4377
4378         /* Enable autotuning of the PLL clock (if permissible) */
4379         factor = 21;
4380         if (is_lvds) {
4381                 if ((intel_panel_use_ssc(dev_priv) &&
4382                      dev_priv->lvds_ssc_freq == 100) ||
4383                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4384                         factor = 25;
4385         } else if (is_sdvo && is_tv)
4386                 factor = 20;
4387
4388         if (clock.m < factor * clock.n)
4389                 fp |= FP_CB_TUNE;
4390
4391         dpll = 0;
4392
4393         if (is_lvds)
4394                 dpll |= DPLLB_MODE_LVDS;
4395         else
4396                 dpll |= DPLLB_MODE_DAC_SERIAL;
4397         if (is_sdvo) {
4398                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4399                 if (pixel_multiplier > 1) {
4400                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4401                 }
4402                 dpll |= DPLL_DVO_HIGH_SPEED;
4403         }
4404         if (is_dp && !is_cpu_edp)
4405                 dpll |= DPLL_DVO_HIGH_SPEED;
4406
4407         /* compute bitmask from p1 value */
4408         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4409         /* also FPA1 */
4410         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4411
4412         switch (clock.p2) {
4413         case 5:
4414                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4415                 break;
4416         case 7:
4417                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4418                 break;
4419         case 10:
4420                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4421                 break;
4422         case 14:
4423                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4424                 break;
4425         }
4426
4427         if (is_sdvo && is_tv)
4428                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4429         else if (is_tv)
4430                 /* XXX: just matching BIOS for now */
4431                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4432                 dpll |= 3;
4433         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4434                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4435         else
4436                 dpll |= PLL_REF_INPUT_DREFCLK;
4437
4438         /* setup pipeconf */
4439         pipeconf = I915_READ(PIPECONF(pipe));
4440
4441         /* Set up the display plane register */
4442         dspcntr = DISPPLANE_GAMMA_ENABLE;
4443
4444         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4445         drm_mode_debug_printmodeline(mode);
4446
4447         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4448          * pre-Haswell/LPT generation */
4449         if (HAS_PCH_LPT(dev)) {
4450                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4451                                 pipe);
4452         } else if (!is_cpu_edp) {
4453                 struct intel_pch_pll *pll;
4454
4455                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4456                 if (pll == NULL) {
4457                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4458                                          pipe);
4459                         return -EINVAL;
4460                 }
4461         } else
4462                 intel_put_pch_pll(intel_crtc);
4463
4464         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4465          * This is an exception to the general rule that mode_set doesn't turn
4466          * things on.
4467          */
4468         if (is_lvds) {
4469                 temp = I915_READ(PCH_LVDS);
4470                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4471                 if (HAS_PCH_CPT(dev)) {
4472                         temp &= ~PORT_TRANS_SEL_MASK;
4473                         temp |= PORT_TRANS_SEL_CPT(pipe);
4474                 } else {
4475                         if (pipe == 1)
4476                                 temp |= LVDS_PIPEB_SELECT;
4477                         else
4478                                 temp &= ~LVDS_PIPEB_SELECT;
4479                 }
4480
4481                 /* set the corresponsding LVDS_BORDER bit */
4482                 temp |= dev_priv->lvds_border_bits;
4483                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4484                  * set the DPLLs for dual-channel mode or not.
4485                  */
4486                 if (clock.p2 == 7)
4487                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4488                 else
4489                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4490
4491                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4492                  * appropriately here, but we need to look more thoroughly into how
4493                  * panels behave in the two modes.
4494                  */
4495                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4496                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4497                         temp |= LVDS_HSYNC_POLARITY;
4498                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4499                         temp |= LVDS_VSYNC_POLARITY;
4500                 I915_WRITE(PCH_LVDS, temp);
4501         }
4502
4503         pipeconf &= ~PIPECONF_DITHER_EN;
4504         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4505         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4506                 pipeconf |= PIPECONF_DITHER_EN;
4507                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4508         }
4509         if (is_dp && !is_cpu_edp) {
4510                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4511         } else {
4512                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4513                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4514                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4515                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4516                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4517         }
4518
4519         if (intel_crtc->pch_pll) {
4520                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4521
4522                 /* Wait for the clocks to stabilize. */
4523                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4524                 udelay(150);
4525
4526                 /* The pixel multiplier can only be updated once the
4527                  * DPLL is enabled and the clocks are stable.
4528                  *
4529                  * So write it again.
4530                  */
4531                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4532         }
4533
4534         intel_crtc->lowfreq_avail = false;
4535         if (intel_crtc->pch_pll) {
4536                 if (is_lvds && has_reduced_clock && i915_powersave) {
4537                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4538                         intel_crtc->lowfreq_avail = true;
4539                         if (HAS_PIPE_CXSR(dev)) {
4540                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4541                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4542                         }
4543                 } else {
4544                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4545                         if (HAS_PIPE_CXSR(dev)) {
4546                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4547                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4548                         }
4549                 }
4550         }
4551
4552         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4553         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4554                 pipeconf |= PIPECONF_INTERLACED_ILK;
4555                 /* the chip adds 2 halflines automatically */
4556                 adjusted_mode->crtc_vtotal -= 1;
4557                 adjusted_mode->crtc_vblank_end -= 1;
4558                 I915_WRITE(VSYNCSHIFT(pipe),
4559                            adjusted_mode->crtc_hsync_start
4560                            - adjusted_mode->crtc_htotal/2);
4561         } else {
4562                 pipeconf |= PIPECONF_PROGRESSIVE;
4563                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4564         }
4565
4566         I915_WRITE(HTOTAL(pipe),
4567                    (adjusted_mode->crtc_hdisplay - 1) |
4568                    ((adjusted_mode->crtc_htotal - 1) << 16));
4569         I915_WRITE(HBLANK(pipe),
4570                    (adjusted_mode->crtc_hblank_start - 1) |
4571                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4572         I915_WRITE(HSYNC(pipe),
4573                    (adjusted_mode->crtc_hsync_start - 1) |
4574                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4575
4576         I915_WRITE(VTOTAL(pipe),
4577                    (adjusted_mode->crtc_vdisplay - 1) |
4578                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4579         I915_WRITE(VBLANK(pipe),
4580                    (adjusted_mode->crtc_vblank_start - 1) |
4581                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4582         I915_WRITE(VSYNC(pipe),
4583                    (adjusted_mode->crtc_vsync_start - 1) |
4584                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4585
4586         /* pipesrc controls the size that is scaled from, which should
4587          * always be the user's requested size.
4588          */
4589         I915_WRITE(PIPESRC(pipe),
4590                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4591
4592         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4593         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4594         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4595         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4596
4597         if (is_cpu_edp)
4598                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4599
4600         I915_WRITE(PIPECONF(pipe), pipeconf);
4601         POSTING_READ(PIPECONF(pipe));
4602
4603         intel_wait_for_vblank(dev, pipe);
4604
4605         I915_WRITE(DSPCNTR(plane), dspcntr);
4606         POSTING_READ(DSPCNTR(plane));
4607
4608         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4609
4610         intel_update_watermarks(dev);
4611
4612         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4613
4614         return ret;
4615 }
4616
4617 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4618                                struct drm_display_mode *mode,
4619                                struct drm_display_mode *adjusted_mode,
4620                                int x, int y,
4621                                struct drm_framebuffer *old_fb)
4622 {
4623         struct drm_device *dev = crtc->dev;
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         int pipe = intel_crtc->pipe;
4627         int ret;
4628
4629         drm_vblank_pre_modeset(dev, pipe);
4630
4631         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4632                                               x, y, old_fb);
4633         drm_vblank_post_modeset(dev, pipe);
4634
4635         if (ret)
4636                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4637         else
4638                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4639
4640         return ret;
4641 }
4642
4643 static bool intel_eld_uptodate(struct drm_connector *connector,
4644                                int reg_eldv, uint32_t bits_eldv,
4645                                int reg_elda, uint32_t bits_elda,
4646                                int reg_edid)
4647 {
4648         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4649         uint8_t *eld = connector->eld;
4650         uint32_t i;
4651
4652         i = I915_READ(reg_eldv);
4653         i &= bits_eldv;
4654
4655         if (!eld[0])
4656                 return !i;
4657
4658         if (!i)
4659                 return false;
4660
4661         i = I915_READ(reg_elda);
4662         i &= ~bits_elda;
4663         I915_WRITE(reg_elda, i);
4664
4665         for (i = 0; i < eld[2]; i++)
4666                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4667                         return false;
4668
4669         return true;
4670 }
4671
4672 static void g4x_write_eld(struct drm_connector *connector,
4673                           struct drm_crtc *crtc)
4674 {
4675         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4676         uint8_t *eld = connector->eld;
4677         uint32_t eldv;
4678         uint32_t len;
4679         uint32_t i;
4680
4681         i = I915_READ(G4X_AUD_VID_DID);
4682
4683         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4684                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4685         else
4686                 eldv = G4X_ELDV_DEVCTG;
4687
4688         if (intel_eld_uptodate(connector,
4689                                G4X_AUD_CNTL_ST, eldv,
4690                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4691                                G4X_HDMIW_HDMIEDID))
4692                 return;
4693
4694         i = I915_READ(G4X_AUD_CNTL_ST);
4695         i &= ~(eldv | G4X_ELD_ADDR);
4696         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4697         I915_WRITE(G4X_AUD_CNTL_ST, i);
4698
4699         if (!eld[0])
4700                 return;
4701
4702         len = min_t(uint8_t, eld[2], len);
4703         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4704         for (i = 0; i < len; i++)
4705                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4706
4707         i = I915_READ(G4X_AUD_CNTL_ST);
4708         i |= eldv;
4709         I915_WRITE(G4X_AUD_CNTL_ST, i);
4710 }
4711
4712 static void ironlake_write_eld(struct drm_connector *connector,
4713                                      struct drm_crtc *crtc)
4714 {
4715         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4716         uint8_t *eld = connector->eld;
4717         uint32_t eldv;
4718         uint32_t i;
4719         int len;
4720         int hdmiw_hdmiedid;
4721         int aud_config;
4722         int aud_cntl_st;
4723         int aud_cntrl_st2;
4724
4725         if (HAS_PCH_IBX(connector->dev)) {
4726                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4727                 aud_config = IBX_AUD_CONFIG_A;
4728                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4729                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4730         } else {
4731                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4732                 aud_config = CPT_AUD_CONFIG_A;
4733                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4734                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4735         }
4736
4737         i = to_intel_crtc(crtc)->pipe;
4738         hdmiw_hdmiedid += i * 0x100;
4739         aud_cntl_st += i * 0x100;
4740         aud_config += i * 0x100;
4741
4742         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4743
4744         i = I915_READ(aud_cntl_st);
4745         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4746         if (!i) {
4747                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4748                 /* operate blindly on all ports */
4749                 eldv = IBX_ELD_VALIDB;
4750                 eldv |= IBX_ELD_VALIDB << 4;
4751                 eldv |= IBX_ELD_VALIDB << 8;
4752         } else {
4753                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4754                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4755         }
4756
4757         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4758                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4759                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4760                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4761         } else
4762                 I915_WRITE(aud_config, 0);
4763
4764         if (intel_eld_uptodate(connector,
4765                                aud_cntrl_st2, eldv,
4766                                aud_cntl_st, IBX_ELD_ADDRESS,
4767                                hdmiw_hdmiedid))
4768                 return;
4769
4770         i = I915_READ(aud_cntrl_st2);
4771         i &= ~eldv;
4772         I915_WRITE(aud_cntrl_st2, i);
4773
4774         if (!eld[0])
4775                 return;
4776
4777         i = I915_READ(aud_cntl_st);
4778         i &= ~IBX_ELD_ADDRESS;
4779         I915_WRITE(aud_cntl_st, i);
4780
4781         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4782         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4783         for (i = 0; i < len; i++)
4784                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4785
4786         i = I915_READ(aud_cntrl_st2);
4787         i |= eldv;
4788         I915_WRITE(aud_cntrl_st2, i);
4789 }
4790
4791 void intel_write_eld(struct drm_encoder *encoder,
4792                      struct drm_display_mode *mode)
4793 {
4794         struct drm_crtc *crtc = encoder->crtc;
4795         struct drm_connector *connector;
4796         struct drm_device *dev = encoder->dev;
4797         struct drm_i915_private *dev_priv = dev->dev_private;
4798
4799         connector = drm_select_eld(encoder, mode);
4800         if (!connector)
4801                 return;
4802
4803         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4804                          connector->base.id,
4805                          drm_get_connector_name(connector),
4806                          connector->encoder->base.id,
4807                          drm_get_encoder_name(connector->encoder));
4808
4809         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4810
4811         if (dev_priv->display.write_eld)
4812                 dev_priv->display.write_eld(connector, crtc);
4813 }
4814
4815 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4816 void intel_crtc_load_lut(struct drm_crtc *crtc)
4817 {
4818         struct drm_device *dev = crtc->dev;
4819         struct drm_i915_private *dev_priv = dev->dev_private;
4820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821         int palreg = PALETTE(intel_crtc->pipe);
4822         int i;
4823
4824         /* The clocks have to be on to load the palette. */
4825         if (!crtc->enabled || !intel_crtc->active)
4826                 return;
4827
4828         /* use legacy palette for Ironlake */
4829         if (HAS_PCH_SPLIT(dev))
4830                 palreg = LGC_PALETTE(intel_crtc->pipe);
4831
4832         for (i = 0; i < 256; i++) {
4833                 I915_WRITE(palreg + 4 * i,
4834                            (intel_crtc->lut_r[i] << 16) |
4835                            (intel_crtc->lut_g[i] << 8) |
4836                            intel_crtc->lut_b[i]);
4837         }
4838 }
4839
4840 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4841 {
4842         struct drm_device *dev = crtc->dev;
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4845         bool visible = base != 0;
4846         u32 cntl;
4847
4848         if (intel_crtc->cursor_visible == visible)
4849                 return;
4850
4851         cntl = I915_READ(_CURACNTR);
4852         if (visible) {
4853                 /* On these chipsets we can only modify the base whilst
4854                  * the cursor is disabled.
4855                  */
4856                 I915_WRITE(_CURABASE, base);
4857
4858                 cntl &= ~(CURSOR_FORMAT_MASK);
4859                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4860                 cntl |= CURSOR_ENABLE |
4861                         CURSOR_GAMMA_ENABLE |
4862                         CURSOR_FORMAT_ARGB;
4863         } else
4864                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4865         I915_WRITE(_CURACNTR, cntl);
4866
4867         intel_crtc->cursor_visible = visible;
4868 }
4869
4870 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4871 {
4872         struct drm_device *dev = crtc->dev;
4873         struct drm_i915_private *dev_priv = dev->dev_private;
4874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875         int pipe = intel_crtc->pipe;
4876         bool visible = base != 0;
4877
4878         if (intel_crtc->cursor_visible != visible) {
4879                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4880                 if (base) {
4881                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4882                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4883                         cntl |= pipe << 28; /* Connect to correct pipe */
4884                 } else {
4885                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4886                         cntl |= CURSOR_MODE_DISABLE;
4887                 }
4888                 I915_WRITE(CURCNTR(pipe), cntl);
4889
4890                 intel_crtc->cursor_visible = visible;
4891         }
4892         /* and commit changes on next vblank */
4893         I915_WRITE(CURBASE(pipe), base);
4894 }
4895
4896 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4897 {
4898         struct drm_device *dev = crtc->dev;
4899         struct drm_i915_private *dev_priv = dev->dev_private;
4900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901         int pipe = intel_crtc->pipe;
4902         bool visible = base != 0;
4903
4904         if (intel_crtc->cursor_visible != visible) {
4905                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4906                 if (base) {
4907                         cntl &= ~CURSOR_MODE;
4908                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4909                 } else {
4910                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4911                         cntl |= CURSOR_MODE_DISABLE;
4912                 }
4913                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4914
4915                 intel_crtc->cursor_visible = visible;
4916         }
4917         /* and commit changes on next vblank */
4918         I915_WRITE(CURBASE_IVB(pipe), base);
4919 }
4920
4921 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4922 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4923                                      bool on)
4924 {
4925         struct drm_device *dev = crtc->dev;
4926         struct drm_i915_private *dev_priv = dev->dev_private;
4927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4928         int pipe = intel_crtc->pipe;
4929         int x = intel_crtc->cursor_x;
4930         int y = intel_crtc->cursor_y;
4931         u32 base, pos;
4932         bool visible;
4933
4934         pos = 0;
4935
4936         if (on && crtc->enabled && crtc->fb) {
4937                 base = intel_crtc->cursor_addr;
4938                 if (x > (int) crtc->fb->width)
4939                         base = 0;
4940
4941                 if (y > (int) crtc->fb->height)
4942                         base = 0;
4943         } else
4944                 base = 0;
4945
4946         if (x < 0) {
4947                 if (x + intel_crtc->cursor_width < 0)
4948                         base = 0;
4949
4950                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4951                 x = -x;
4952         }
4953         pos |= x << CURSOR_X_SHIFT;
4954
4955         if (y < 0) {
4956                 if (y + intel_crtc->cursor_height < 0)
4957                         base = 0;
4958
4959                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4960                 y = -y;
4961         }
4962         pos |= y << CURSOR_Y_SHIFT;
4963
4964         visible = base != 0;
4965         if (!visible && !intel_crtc->cursor_visible)
4966                 return;
4967
4968         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4969                 I915_WRITE(CURPOS_IVB(pipe), pos);
4970                 ivb_update_cursor(crtc, base);
4971         } else {
4972                 I915_WRITE(CURPOS(pipe), pos);
4973                 if (IS_845G(dev) || IS_I865G(dev))
4974                         i845_update_cursor(crtc, base);
4975                 else
4976                         i9xx_update_cursor(crtc, base);
4977         }
4978 }
4979
4980 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4981                                  struct drm_file *file,
4982                                  uint32_t handle,
4983                                  uint32_t width, uint32_t height)
4984 {
4985         struct drm_device *dev = crtc->dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4988         struct drm_i915_gem_object *obj;
4989         uint32_t addr;
4990         int ret;
4991
4992         DRM_DEBUG_KMS("\n");
4993
4994         /* if we want to turn off the cursor ignore width and height */
4995         if (!handle) {
4996                 DRM_DEBUG_KMS("cursor off\n");
4997                 addr = 0;
4998                 obj = NULL;
4999                 mutex_lock(&dev->struct_mutex);
5000                 goto finish;
5001         }
5002
5003         /* Currently we only support 64x64 cursors */
5004         if (width != 64 || height != 64) {
5005                 DRM_ERROR("we currently only support 64x64 cursors\n");
5006                 return -EINVAL;
5007         }
5008
5009         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5010         if (&obj->base == NULL)
5011                 return -ENOENT;
5012
5013         if (obj->base.size < width * height * 4) {
5014                 DRM_ERROR("buffer is to small\n");
5015                 ret = -ENOMEM;
5016                 goto fail;
5017         }
5018
5019         /* we only need to pin inside GTT if cursor is non-phy */
5020         mutex_lock(&dev->struct_mutex);
5021         if (!dev_priv->info->cursor_needs_physical) {
5022                 if (obj->tiling_mode) {
5023                         DRM_ERROR("cursor cannot be tiled\n");
5024                         ret = -EINVAL;
5025                         goto fail_locked;
5026                 }
5027
5028                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5029                 if (ret) {
5030                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5031                         goto fail_locked;
5032                 }
5033
5034                 ret = i915_gem_object_put_fence(obj);
5035                 if (ret) {
5036                         DRM_ERROR("failed to release fence for cursor");
5037                         goto fail_unpin;
5038                 }
5039
5040                 addr = obj->gtt_offset;
5041         } else {
5042                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5043                 ret = i915_gem_attach_phys_object(dev, obj,
5044                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5045                                                   align);
5046                 if (ret) {
5047                         DRM_ERROR("failed to attach phys object\n");
5048                         goto fail_locked;
5049                 }
5050                 addr = obj->phys_obj->handle->busaddr;
5051         }
5052
5053         if (IS_GEN2(dev))
5054                 I915_WRITE(CURSIZE, (height << 12) | width);
5055
5056  finish:
5057         if (intel_crtc->cursor_bo) {
5058                 if (dev_priv->info->cursor_needs_physical) {
5059                         if (intel_crtc->cursor_bo != obj)
5060                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5061                 } else
5062                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5063                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5064         }
5065
5066         mutex_unlock(&dev->struct_mutex);
5067
5068         intel_crtc->cursor_addr = addr;
5069         intel_crtc->cursor_bo = obj;
5070         intel_crtc->cursor_width = width;
5071         intel_crtc->cursor_height = height;
5072
5073         intel_crtc_update_cursor(crtc, true);
5074
5075         return 0;
5076 fail_unpin:
5077         i915_gem_object_unpin(obj);
5078 fail_locked:
5079         mutex_unlock(&dev->struct_mutex);
5080 fail:
5081         drm_gem_object_unreference_unlocked(&obj->base);
5082         return ret;
5083 }
5084
5085 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5086 {
5087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088
5089         intel_crtc->cursor_x = x;
5090         intel_crtc->cursor_y = y;
5091
5092         intel_crtc_update_cursor(crtc, true);
5093
5094         return 0;
5095 }
5096
5097 /** Sets the color ramps on behalf of RandR */
5098 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5099                                  u16 blue, int regno)
5100 {
5101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102
5103         intel_crtc->lut_r[regno] = red >> 8;
5104         intel_crtc->lut_g[regno] = green >> 8;
5105         intel_crtc->lut_b[regno] = blue >> 8;
5106 }
5107
5108 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5109                              u16 *blue, int regno)
5110 {
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112
5113         *red = intel_crtc->lut_r[regno] << 8;
5114         *green = intel_crtc->lut_g[regno] << 8;
5115         *blue = intel_crtc->lut_b[regno] << 8;
5116 }
5117
5118 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5119                                  u16 *blue, uint32_t start, uint32_t size)
5120 {
5121         int end = (start + size > 256) ? 256 : start + size, i;
5122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123
5124         for (i = start; i < end; i++) {
5125                 intel_crtc->lut_r[i] = red[i] >> 8;
5126                 intel_crtc->lut_g[i] = green[i] >> 8;
5127                 intel_crtc->lut_b[i] = blue[i] >> 8;
5128         }
5129
5130         intel_crtc_load_lut(crtc);
5131 }
5132
5133 /**
5134  * Get a pipe with a simple mode set on it for doing load-based monitor
5135  * detection.
5136  *
5137  * It will be up to the load-detect code to adjust the pipe as appropriate for
5138  * its requirements.  The pipe will be connected to no other encoders.
5139  *
5140  * Currently this code will only succeed if there is a pipe with no encoders
5141  * configured for it.  In the future, it could choose to temporarily disable
5142  * some outputs to free up a pipe for its use.
5143  *
5144  * \return crtc, or NULL if no pipes are available.
5145  */
5146
5147 /* VESA 640x480x72Hz mode to set on the pipe */
5148 static struct drm_display_mode load_detect_mode = {
5149         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5150                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5151 };
5152
5153 static struct drm_framebuffer *
5154 intel_framebuffer_create(struct drm_device *dev,
5155                          struct drm_mode_fb_cmd2 *mode_cmd,
5156                          struct drm_i915_gem_object *obj)
5157 {
5158         struct intel_framebuffer *intel_fb;
5159         int ret;
5160
5161         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5162         if (!intel_fb) {
5163                 drm_gem_object_unreference_unlocked(&obj->base);
5164                 return ERR_PTR(-ENOMEM);
5165         }
5166
5167         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5168         if (ret) {
5169                 drm_gem_object_unreference_unlocked(&obj->base);
5170                 kfree(intel_fb);
5171                 return ERR_PTR(ret);
5172         }
5173
5174         return &intel_fb->base;
5175 }
5176
5177 static u32
5178 intel_framebuffer_pitch_for_width(int width, int bpp)
5179 {
5180         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5181         return ALIGN(pitch, 64);
5182 }
5183
5184 static u32
5185 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5186 {
5187         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5188         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5189 }
5190
5191 static struct drm_framebuffer *
5192 intel_framebuffer_create_for_mode(struct drm_device *dev,
5193                                   struct drm_display_mode *mode,
5194                                   int depth, int bpp)
5195 {
5196         struct drm_i915_gem_object *obj;
5197         struct drm_mode_fb_cmd2 mode_cmd;
5198
5199         obj = i915_gem_alloc_object(dev,
5200                                     intel_framebuffer_size_for_mode(mode, bpp));
5201         if (obj == NULL)
5202                 return ERR_PTR(-ENOMEM);
5203
5204         mode_cmd.width = mode->hdisplay;
5205         mode_cmd.height = mode->vdisplay;
5206         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5207                                                                 bpp);
5208         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5209
5210         return intel_framebuffer_create(dev, &mode_cmd, obj);
5211 }
5212
5213 static struct drm_framebuffer *
5214 mode_fits_in_fbdev(struct drm_device *dev,
5215                    struct drm_display_mode *mode)
5216 {
5217         struct drm_i915_private *dev_priv = dev->dev_private;
5218         struct drm_i915_gem_object *obj;
5219         struct drm_framebuffer *fb;
5220
5221         if (dev_priv->fbdev == NULL)
5222                 return NULL;
5223
5224         obj = dev_priv->fbdev->ifb.obj;
5225         if (obj == NULL)
5226                 return NULL;
5227
5228         fb = &dev_priv->fbdev->ifb.base;
5229         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5230                                                                fb->bits_per_pixel))
5231                 return NULL;
5232
5233         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5234                 return NULL;
5235
5236         return fb;
5237 }
5238
5239 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5240                                 struct drm_connector *connector,
5241                                 struct drm_display_mode *mode,
5242                                 struct intel_load_detect_pipe *old)
5243 {
5244         struct intel_crtc *intel_crtc;
5245         struct drm_crtc *possible_crtc;
5246         struct drm_encoder *encoder = &intel_encoder->base;
5247         struct drm_crtc *crtc = NULL;
5248         struct drm_device *dev = encoder->dev;
5249         struct drm_framebuffer *old_fb;
5250         int i = -1;
5251
5252         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5253                       connector->base.id, drm_get_connector_name(connector),
5254                       encoder->base.id, drm_get_encoder_name(encoder));
5255
5256         /*
5257          * Algorithm gets a little messy:
5258          *
5259          *   - if the connector already has an assigned crtc, use it (but make
5260          *     sure it's on first)
5261          *
5262          *   - try to find the first unused crtc that can drive this connector,
5263          *     and use that if we find one
5264          */
5265
5266         /* See if we already have a CRTC for this connector */
5267         if (encoder->crtc) {
5268                 crtc = encoder->crtc;
5269
5270                 intel_crtc = to_intel_crtc(crtc);
5271                 old->dpms_mode = intel_crtc->dpms_mode;
5272                 old->load_detect_temp = false;
5273
5274                 /* Make sure the crtc and connector are running */
5275                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5276                         struct drm_encoder_helper_funcs *encoder_funcs;
5277                         struct drm_crtc_helper_funcs *crtc_funcs;
5278
5279                         crtc_funcs = crtc->helper_private;
5280                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5281
5282                         encoder_funcs = encoder->helper_private;
5283                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5284                 }
5285
5286                 return true;
5287         }
5288
5289         /* Find an unused one (if possible) */
5290         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5291                 i++;
5292                 if (!(encoder->possible_crtcs & (1 << i)))
5293                         continue;
5294                 if (!possible_crtc->enabled) {
5295                         crtc = possible_crtc;
5296                         break;
5297                 }
5298         }
5299
5300         /*
5301          * If we didn't find an unused CRTC, don't use any.
5302          */
5303         if (!crtc) {
5304                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5305                 return false;
5306         }
5307
5308         encoder->crtc = crtc;
5309         connector->encoder = encoder;
5310
5311         intel_crtc = to_intel_crtc(crtc);
5312         old->dpms_mode = intel_crtc->dpms_mode;
5313         old->load_detect_temp = true;
5314         old->release_fb = NULL;
5315
5316         if (!mode)
5317                 mode = &load_detect_mode;
5318
5319         old_fb = crtc->fb;
5320
5321         /* We need a framebuffer large enough to accommodate all accesses
5322          * that the plane may generate whilst we perform load detection.
5323          * We can not rely on the fbcon either being present (we get called
5324          * during its initialisation to detect all boot displays, or it may
5325          * not even exist) or that it is large enough to satisfy the
5326          * requested mode.
5327          */
5328         crtc->fb = mode_fits_in_fbdev(dev, mode);
5329         if (crtc->fb == NULL) {
5330                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5331                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5332                 old->release_fb = crtc->fb;
5333         } else
5334                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5335         if (IS_ERR(crtc->fb)) {
5336                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5337                 crtc->fb = old_fb;
5338                 return false;
5339         }
5340
5341         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5342                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5343                 if (old->release_fb)
5344                         old->release_fb->funcs->destroy(old->release_fb);
5345                 crtc->fb = old_fb;
5346                 return false;
5347         }
5348
5349         /* let the connector get through one full cycle before testing */
5350         intel_wait_for_vblank(dev, intel_crtc->pipe);
5351
5352         return true;
5353 }
5354
5355 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5356                                     struct drm_connector *connector,
5357                                     struct intel_load_detect_pipe *old)
5358 {
5359         struct drm_encoder *encoder = &intel_encoder->base;
5360         struct drm_device *dev = encoder->dev;
5361         struct drm_crtc *crtc = encoder->crtc;
5362         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5363         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5364
5365         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5366                       connector->base.id, drm_get_connector_name(connector),
5367                       encoder->base.id, drm_get_encoder_name(encoder));
5368
5369         if (old->load_detect_temp) {
5370                 connector->encoder = NULL;
5371                 drm_helper_disable_unused_functions(dev);
5372
5373                 if (old->release_fb)
5374                         old->release_fb->funcs->destroy(old->release_fb);
5375
5376                 return;
5377         }
5378
5379         /* Switch crtc and encoder back off if necessary */
5380         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5381                 encoder_funcs->dpms(encoder, old->dpms_mode);
5382                 crtc_funcs->dpms(crtc, old->dpms_mode);
5383         }
5384 }
5385
5386 /* Returns the clock of the currently programmed mode of the given pipe. */
5387 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5388 {
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391         int pipe = intel_crtc->pipe;
5392         u32 dpll = I915_READ(DPLL(pipe));
5393         u32 fp;
5394         intel_clock_t clock;
5395
5396         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5397                 fp = I915_READ(FP0(pipe));
5398         else
5399                 fp = I915_READ(FP1(pipe));
5400
5401         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5402         if (IS_PINEVIEW(dev)) {
5403                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5404                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5405         } else {
5406                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5407                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5408         }
5409
5410         if (!IS_GEN2(dev)) {
5411                 if (IS_PINEVIEW(dev))
5412                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5413                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5414                 else
5415                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5416                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5417
5418                 switch (dpll & DPLL_MODE_MASK) {
5419                 case DPLLB_MODE_DAC_SERIAL:
5420                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5421                                 5 : 10;
5422                         break;
5423                 case DPLLB_MODE_LVDS:
5424                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5425                                 7 : 14;
5426                         break;
5427                 default:
5428                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5429                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5430                         return 0;
5431                 }
5432
5433                 /* XXX: Handle the 100Mhz refclk */
5434                 intel_clock(dev, 96000, &clock);
5435         } else {
5436                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5437
5438                 if (is_lvds) {
5439                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5440                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5441                         clock.p2 = 14;
5442
5443                         if ((dpll & PLL_REF_INPUT_MASK) ==
5444                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5445                                 /* XXX: might not be 66MHz */
5446                                 intel_clock(dev, 66000, &clock);
5447                         } else
5448                                 intel_clock(dev, 48000, &clock);
5449                 } else {
5450                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5451                                 clock.p1 = 2;
5452                         else {
5453                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5454                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5455                         }
5456                         if (dpll & PLL_P2_DIVIDE_BY_4)
5457                                 clock.p2 = 4;
5458                         else
5459                                 clock.p2 = 2;
5460
5461                         intel_clock(dev, 48000, &clock);
5462                 }
5463         }
5464
5465         /* XXX: It would be nice to validate the clocks, but we can't reuse
5466          * i830PllIsValid() because it relies on the xf86_config connector
5467          * configuration being accurate, which it isn't necessarily.
5468          */
5469
5470         return clock.dot;
5471 }
5472
5473 /** Returns the currently programmed mode of the given pipe. */
5474 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5475                                              struct drm_crtc *crtc)
5476 {
5477         struct drm_i915_private *dev_priv = dev->dev_private;
5478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5479         int pipe = intel_crtc->pipe;
5480         struct drm_display_mode *mode;
5481         int htot = I915_READ(HTOTAL(pipe));
5482         int hsync = I915_READ(HSYNC(pipe));
5483         int vtot = I915_READ(VTOTAL(pipe));
5484         int vsync = I915_READ(VSYNC(pipe));
5485
5486         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5487         if (!mode)
5488                 return NULL;
5489
5490         mode->clock = intel_crtc_clock_get(dev, crtc);
5491         mode->hdisplay = (htot & 0xffff) + 1;
5492         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5493         mode->hsync_start = (hsync & 0xffff) + 1;
5494         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5495         mode->vdisplay = (vtot & 0xffff) + 1;
5496         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5497         mode->vsync_start = (vsync & 0xffff) + 1;
5498         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5499
5500         drm_mode_set_name(mode);
5501
5502         return mode;
5503 }
5504
5505 #define GPU_IDLE_TIMEOUT 500 /* ms */
5506
5507 /* When this timer fires, we've been idle for awhile */
5508 static void intel_gpu_idle_timer(unsigned long arg)
5509 {
5510         struct drm_device *dev = (struct drm_device *)arg;
5511         drm_i915_private_t *dev_priv = dev->dev_private;
5512
5513         if (!list_empty(&dev_priv->mm.active_list)) {
5514                 /* Still processing requests, so just re-arm the timer. */
5515                 mod_timer(&dev_priv->idle_timer, jiffies +
5516                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5517                 return;
5518         }
5519
5520         dev_priv->busy = false;
5521         queue_work(dev_priv->wq, &dev_priv->idle_work);
5522 }
5523
5524 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5525
5526 static void intel_crtc_idle_timer(unsigned long arg)
5527 {
5528         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5529         struct drm_crtc *crtc = &intel_crtc->base;
5530         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5531         struct intel_framebuffer *intel_fb;
5532
5533         intel_fb = to_intel_framebuffer(crtc->fb);
5534         if (intel_fb && intel_fb->obj->active) {
5535                 /* The framebuffer is still being accessed by the GPU. */
5536                 mod_timer(&intel_crtc->idle_timer, jiffies +
5537                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5538                 return;
5539         }
5540
5541         intel_crtc->busy = false;
5542         queue_work(dev_priv->wq, &dev_priv->idle_work);
5543 }
5544
5545 static void intel_increase_pllclock(struct drm_crtc *crtc)
5546 {
5547         struct drm_device *dev = crtc->dev;
5548         drm_i915_private_t *dev_priv = dev->dev_private;
5549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5550         int pipe = intel_crtc->pipe;
5551         int dpll_reg = DPLL(pipe);
5552         int dpll;
5553
5554         if (HAS_PCH_SPLIT(dev))
5555                 return;
5556
5557         if (!dev_priv->lvds_downclock_avail)
5558                 return;
5559
5560         dpll = I915_READ(dpll_reg);
5561         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5562                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5563
5564                 assert_panel_unlocked(dev_priv, pipe);
5565
5566                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5567                 I915_WRITE(dpll_reg, dpll);
5568                 intel_wait_for_vblank(dev, pipe);
5569
5570                 dpll = I915_READ(dpll_reg);
5571                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5572                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5573         }
5574
5575         /* Schedule downclock */
5576         mod_timer(&intel_crtc->idle_timer, jiffies +
5577                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5578 }
5579
5580 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5581 {
5582         struct drm_device *dev = crtc->dev;
5583         drm_i915_private_t *dev_priv = dev->dev_private;
5584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5585
5586         if (HAS_PCH_SPLIT(dev))
5587                 return;
5588
5589         if (!dev_priv->lvds_downclock_avail)
5590                 return;
5591
5592         /*
5593          * Since this is called by a timer, we should never get here in
5594          * the manual case.
5595          */
5596         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5597                 int pipe = intel_crtc->pipe;
5598                 int dpll_reg = DPLL(pipe);
5599                 int dpll;
5600
5601                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5602
5603                 assert_panel_unlocked(dev_priv, pipe);
5604
5605                 dpll = I915_READ(dpll_reg);
5606                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5607                 I915_WRITE(dpll_reg, dpll);
5608                 intel_wait_for_vblank(dev, pipe);
5609                 dpll = I915_READ(dpll_reg);
5610                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5611                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5612         }
5613
5614 }
5615
5616 /**
5617  * intel_idle_update - adjust clocks for idleness
5618  * @work: work struct
5619  *
5620  * Either the GPU or display (or both) went idle.  Check the busy status
5621  * here and adjust the CRTC and GPU clocks as necessary.
5622  */
5623 static void intel_idle_update(struct work_struct *work)
5624 {
5625         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5626                                                     idle_work);
5627         struct drm_device *dev = dev_priv->dev;
5628         struct drm_crtc *crtc;
5629         struct intel_crtc *intel_crtc;
5630
5631         if (!i915_powersave)
5632                 return;
5633
5634         mutex_lock(&dev->struct_mutex);
5635
5636         i915_update_gfx_val(dev_priv);
5637
5638         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5639                 /* Skip inactive CRTCs */
5640                 if (!crtc->fb)
5641                         continue;
5642
5643                 intel_crtc = to_intel_crtc(crtc);
5644                 if (!intel_crtc->busy)
5645                         intel_decrease_pllclock(crtc);
5646         }
5647
5648
5649         mutex_unlock(&dev->struct_mutex);
5650 }
5651
5652 /**
5653  * intel_mark_busy - mark the GPU and possibly the display busy
5654  * @dev: drm device
5655  * @obj: object we're operating on
5656  *
5657  * Callers can use this function to indicate that the GPU is busy processing
5658  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5659  * buffer), we'll also mark the display as busy, so we know to increase its
5660  * clock frequency.
5661  */
5662 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5663 {
5664         drm_i915_private_t *dev_priv = dev->dev_private;
5665         struct drm_crtc *crtc = NULL;
5666         struct intel_framebuffer *intel_fb;
5667         struct intel_crtc *intel_crtc;
5668
5669         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5670                 return;
5671
5672         if (!dev_priv->busy) {
5673                 intel_sanitize_pm(dev);
5674                 dev_priv->busy = true;
5675         } else
5676                 mod_timer(&dev_priv->idle_timer, jiffies +
5677                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5678
5679         if (obj == NULL)
5680                 return;
5681
5682         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5683                 if (!crtc->fb)
5684                         continue;
5685
5686                 intel_crtc = to_intel_crtc(crtc);
5687                 intel_fb = to_intel_framebuffer(crtc->fb);
5688                 if (intel_fb->obj == obj) {
5689                         if (!intel_crtc->busy) {
5690                                 /* Non-busy -> busy, upclock */
5691                                 intel_increase_pllclock(crtc);
5692                                 intel_crtc->busy = true;
5693                         } else {
5694                                 /* Busy -> busy, put off timer */
5695                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5696                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5697                         }
5698                 }
5699         }
5700 }
5701
5702 static void intel_crtc_destroy(struct drm_crtc *crtc)
5703 {
5704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5705         struct drm_device *dev = crtc->dev;
5706         struct intel_unpin_work *work;
5707         unsigned long flags;
5708
5709         spin_lock_irqsave(&dev->event_lock, flags);
5710         work = intel_crtc->unpin_work;
5711         intel_crtc->unpin_work = NULL;
5712         spin_unlock_irqrestore(&dev->event_lock, flags);
5713
5714         if (work) {
5715                 cancel_work_sync(&work->work);
5716                 kfree(work);
5717         }
5718
5719         drm_crtc_cleanup(crtc);
5720
5721         kfree(intel_crtc);
5722 }
5723
5724 static void intel_unpin_work_fn(struct work_struct *__work)
5725 {
5726         struct intel_unpin_work *work =
5727                 container_of(__work, struct intel_unpin_work, work);
5728
5729         mutex_lock(&work->dev->struct_mutex);
5730         intel_unpin_fb_obj(work->old_fb_obj);
5731         drm_gem_object_unreference(&work->pending_flip_obj->base);
5732         drm_gem_object_unreference(&work->old_fb_obj->base);
5733
5734         intel_update_fbc(work->dev);
5735         mutex_unlock(&work->dev->struct_mutex);
5736         kfree(work);
5737 }
5738
5739 static void do_intel_finish_page_flip(struct drm_device *dev,
5740                                       struct drm_crtc *crtc)
5741 {
5742         drm_i915_private_t *dev_priv = dev->dev_private;
5743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5744         struct intel_unpin_work *work;
5745         struct drm_i915_gem_object *obj;
5746         struct drm_pending_vblank_event *e;
5747         struct timeval tnow, tvbl;
5748         unsigned long flags;
5749
5750         /* Ignore early vblank irqs */
5751         if (intel_crtc == NULL)
5752                 return;
5753
5754         do_gettimeofday(&tnow);
5755
5756         spin_lock_irqsave(&dev->event_lock, flags);
5757         work = intel_crtc->unpin_work;
5758         if (work == NULL || !work->pending) {
5759                 spin_unlock_irqrestore(&dev->event_lock, flags);
5760                 return;
5761         }
5762
5763         intel_crtc->unpin_work = NULL;
5764
5765         if (work->event) {
5766                 e = work->event;
5767                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5768
5769                 /* Called before vblank count and timestamps have
5770                  * been updated for the vblank interval of flip
5771                  * completion? Need to increment vblank count and
5772                  * add one videorefresh duration to returned timestamp
5773                  * to account for this. We assume this happened if we
5774                  * get called over 0.9 frame durations after the last
5775                  * timestamped vblank.
5776                  *
5777                  * This calculation can not be used with vrefresh rates
5778                  * below 5Hz (10Hz to be on the safe side) without
5779                  * promoting to 64 integers.
5780                  */
5781                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5782                     9 * crtc->framedur_ns) {
5783                         e->event.sequence++;
5784                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5785                                              crtc->framedur_ns);
5786                 }
5787
5788                 e->event.tv_sec = tvbl.tv_sec;
5789                 e->event.tv_usec = tvbl.tv_usec;
5790
5791                 list_add_tail(&e->base.link,
5792                               &e->base.file_priv->event_list);
5793                 wake_up_interruptible(&e->base.file_priv->event_wait);
5794         }
5795
5796         drm_vblank_put(dev, intel_crtc->pipe);
5797
5798         spin_unlock_irqrestore(&dev->event_lock, flags);
5799
5800         obj = work->old_fb_obj;
5801
5802         atomic_clear_mask(1 << intel_crtc->plane,
5803                           &obj->pending_flip.counter);
5804         if (atomic_read(&obj->pending_flip) == 0)
5805                 wake_up(&dev_priv->pending_flip_queue);
5806
5807         schedule_work(&work->work);
5808
5809         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5810 }
5811
5812 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5813 {
5814         drm_i915_private_t *dev_priv = dev->dev_private;
5815         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5816
5817         do_intel_finish_page_flip(dev, crtc);
5818 }
5819
5820 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5821 {
5822         drm_i915_private_t *dev_priv = dev->dev_private;
5823         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5824
5825         do_intel_finish_page_flip(dev, crtc);
5826 }
5827
5828 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5829 {
5830         drm_i915_private_t *dev_priv = dev->dev_private;
5831         struct intel_crtc *intel_crtc =
5832                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5833         unsigned long flags;
5834
5835         spin_lock_irqsave(&dev->event_lock, flags);
5836         if (intel_crtc->unpin_work) {
5837                 if ((++intel_crtc->unpin_work->pending) > 1)
5838                         DRM_ERROR("Prepared flip multiple times\n");
5839         } else {
5840                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5841         }
5842         spin_unlock_irqrestore(&dev->event_lock, flags);
5843 }
5844
5845 static int intel_gen2_queue_flip(struct drm_device *dev,
5846                                  struct drm_crtc *crtc,
5847                                  struct drm_framebuffer *fb,
5848                                  struct drm_i915_gem_object *obj)
5849 {
5850         struct drm_i915_private *dev_priv = dev->dev_private;
5851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5852         unsigned long offset;
5853         u32 flip_mask;
5854         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5855         int ret;
5856
5857         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5858         if (ret)
5859                 goto err;
5860
5861         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5862         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5863
5864         ret = intel_ring_begin(ring, 6);
5865         if (ret)
5866                 goto err_unpin;
5867
5868         /* Can't queue multiple flips, so wait for the previous
5869          * one to finish before executing the next.
5870          */
5871         if (intel_crtc->plane)
5872                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5873         else
5874                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5875         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5876         intel_ring_emit(ring, MI_NOOP);
5877         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5878                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5879         intel_ring_emit(ring, fb->pitches[0]);
5880         intel_ring_emit(ring, obj->gtt_offset + offset);
5881         intel_ring_emit(ring, 0); /* aux display base address, unused */
5882         intel_ring_advance(ring);
5883         return 0;
5884
5885 err_unpin:
5886         intel_unpin_fb_obj(obj);
5887 err:
5888         return ret;
5889 }
5890
5891 static int intel_gen3_queue_flip(struct drm_device *dev,
5892                                  struct drm_crtc *crtc,
5893                                  struct drm_framebuffer *fb,
5894                                  struct drm_i915_gem_object *obj)
5895 {
5896         struct drm_i915_private *dev_priv = dev->dev_private;
5897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898         unsigned long offset;
5899         u32 flip_mask;
5900         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5901         int ret;
5902
5903         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5904         if (ret)
5905                 goto err;
5906
5907         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5908         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5909
5910         ret = intel_ring_begin(ring, 6);
5911         if (ret)
5912                 goto err_unpin;
5913
5914         if (intel_crtc->plane)
5915                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5916         else
5917                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5918         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5919         intel_ring_emit(ring, MI_NOOP);
5920         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5921                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5922         intel_ring_emit(ring, fb->pitches[0]);
5923         intel_ring_emit(ring, obj->gtt_offset + offset);
5924         intel_ring_emit(ring, MI_NOOP);
5925
5926         intel_ring_advance(ring);
5927         return 0;
5928
5929 err_unpin:
5930         intel_unpin_fb_obj(obj);
5931 err:
5932         return ret;
5933 }
5934
5935 static int intel_gen4_queue_flip(struct drm_device *dev,
5936                                  struct drm_crtc *crtc,
5937                                  struct drm_framebuffer *fb,
5938                                  struct drm_i915_gem_object *obj)
5939 {
5940         struct drm_i915_private *dev_priv = dev->dev_private;
5941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942         uint32_t pf, pipesrc;
5943         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5944         int ret;
5945
5946         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5947         if (ret)
5948                 goto err;
5949
5950         ret = intel_ring_begin(ring, 4);
5951         if (ret)
5952                 goto err_unpin;
5953
5954         /* i965+ uses the linear or tiled offsets from the
5955          * Display Registers (which do not change across a page-flip)
5956          * so we need only reprogram the base address.
5957          */
5958         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5959                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5960         intel_ring_emit(ring, fb->pitches[0]);
5961         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5962
5963         /* XXX Enabling the panel-fitter across page-flip is so far
5964          * untested on non-native modes, so ignore it for now.
5965          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5966          */
5967         pf = 0;
5968         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5969         intel_ring_emit(ring, pf | pipesrc);
5970         intel_ring_advance(ring);
5971         return 0;
5972
5973 err_unpin:
5974         intel_unpin_fb_obj(obj);
5975 err:
5976         return ret;
5977 }
5978
5979 static int intel_gen6_queue_flip(struct drm_device *dev,
5980                                  struct drm_crtc *crtc,
5981                                  struct drm_framebuffer *fb,
5982                                  struct drm_i915_gem_object *obj)
5983 {
5984         struct drm_i915_private *dev_priv = dev->dev_private;
5985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5986         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5987         uint32_t pf, pipesrc;
5988         int ret;
5989
5990         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5991         if (ret)
5992                 goto err;
5993
5994         ret = intel_ring_begin(ring, 4);
5995         if (ret)
5996                 goto err_unpin;
5997
5998         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5999                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6000         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6001         intel_ring_emit(ring, obj->gtt_offset);
6002
6003         /* Contrary to the suggestions in the documentation,
6004          * "Enable Panel Fitter" does not seem to be required when page
6005          * flipping with a non-native mode, and worse causes a normal
6006          * modeset to fail.
6007          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6008          */
6009         pf = 0;
6010         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6011         intel_ring_emit(ring, pf | pipesrc);
6012         intel_ring_advance(ring);
6013         return 0;
6014
6015 err_unpin:
6016         intel_unpin_fb_obj(obj);
6017 err:
6018         return ret;
6019 }
6020
6021 /*
6022  * On gen7 we currently use the blit ring because (in early silicon at least)
6023  * the render ring doesn't give us interrpts for page flip completion, which
6024  * means clients will hang after the first flip is queued.  Fortunately the
6025  * blit ring generates interrupts properly, so use it instead.
6026  */
6027 static int intel_gen7_queue_flip(struct drm_device *dev,
6028                                  struct drm_crtc *crtc,
6029                                  struct drm_framebuffer *fb,
6030                                  struct drm_i915_gem_object *obj)
6031 {
6032         struct drm_i915_private *dev_priv = dev->dev_private;
6033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6034         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6035         int ret;
6036
6037         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6038         if (ret)
6039                 goto err;
6040
6041         ret = intel_ring_begin(ring, 4);
6042         if (ret)
6043                 goto err_unpin;
6044
6045         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6046         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6047         intel_ring_emit(ring, (obj->gtt_offset));
6048         intel_ring_emit(ring, (MI_NOOP));
6049         intel_ring_advance(ring);
6050         return 0;
6051
6052 err_unpin:
6053         intel_unpin_fb_obj(obj);
6054 err:
6055         return ret;
6056 }
6057
6058 static int intel_default_queue_flip(struct drm_device *dev,
6059                                     struct drm_crtc *crtc,
6060                                     struct drm_framebuffer *fb,
6061                                     struct drm_i915_gem_object *obj)
6062 {
6063         return -ENODEV;
6064 }
6065
6066 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6067                                 struct drm_framebuffer *fb,
6068                                 struct drm_pending_vblank_event *event)
6069 {
6070         struct drm_device *dev = crtc->dev;
6071         struct drm_i915_private *dev_priv = dev->dev_private;
6072         struct intel_framebuffer *intel_fb;
6073         struct drm_i915_gem_object *obj;
6074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075         struct intel_unpin_work *work;
6076         unsigned long flags;
6077         int ret;
6078
6079         work = kzalloc(sizeof *work, GFP_KERNEL);
6080         if (work == NULL)
6081                 return -ENOMEM;
6082
6083         work->event = event;
6084         work->dev = crtc->dev;
6085         intel_fb = to_intel_framebuffer(crtc->fb);
6086         work->old_fb_obj = intel_fb->obj;
6087         INIT_WORK(&work->work, intel_unpin_work_fn);
6088
6089         ret = drm_vblank_get(dev, intel_crtc->pipe);
6090         if (ret)
6091                 goto free_work;
6092
6093         /* We borrow the event spin lock for protecting unpin_work */
6094         spin_lock_irqsave(&dev->event_lock, flags);
6095         if (intel_crtc->unpin_work) {
6096                 spin_unlock_irqrestore(&dev->event_lock, flags);
6097                 kfree(work);
6098                 drm_vblank_put(dev, intel_crtc->pipe);
6099
6100                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6101                 return -EBUSY;
6102         }
6103         intel_crtc->unpin_work = work;
6104         spin_unlock_irqrestore(&dev->event_lock, flags);
6105
6106         intel_fb = to_intel_framebuffer(fb);
6107         obj = intel_fb->obj;
6108
6109         mutex_lock(&dev->struct_mutex);
6110
6111         /* Reference the objects for the scheduled work. */
6112         drm_gem_object_reference(&work->old_fb_obj->base);
6113         drm_gem_object_reference(&obj->base);
6114
6115         crtc->fb = fb;
6116
6117         work->pending_flip_obj = obj;
6118
6119         work->enable_stall_check = true;
6120
6121         /* Block clients from rendering to the new back buffer until
6122          * the flip occurs and the object is no longer visible.
6123          */
6124         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6125
6126         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6127         if (ret)
6128                 goto cleanup_pending;
6129
6130         intel_disable_fbc(dev);
6131         intel_mark_busy(dev, obj);
6132         mutex_unlock(&dev->struct_mutex);
6133
6134         trace_i915_flip_request(intel_crtc->plane, obj);
6135
6136         return 0;
6137
6138 cleanup_pending:
6139         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6140         drm_gem_object_unreference(&work->old_fb_obj->base);
6141         drm_gem_object_unreference(&obj->base);
6142         mutex_unlock(&dev->struct_mutex);
6143
6144         spin_lock_irqsave(&dev->event_lock, flags);
6145         intel_crtc->unpin_work = NULL;
6146         spin_unlock_irqrestore(&dev->event_lock, flags);
6147
6148         drm_vblank_put(dev, intel_crtc->pipe);
6149 free_work:
6150         kfree(work);
6151
6152         return ret;
6153 }
6154
6155 static void intel_sanitize_modesetting(struct drm_device *dev,
6156                                        int pipe, int plane)
6157 {
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         u32 reg, val;
6160
6161         /* Clear any frame start delays used for debugging left by the BIOS */
6162         for_each_pipe(pipe) {
6163                 reg = PIPECONF(pipe);
6164                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6165         }
6166
6167         if (HAS_PCH_SPLIT(dev))
6168                 return;
6169
6170         /* Who knows what state these registers were left in by the BIOS or
6171          * grub?
6172          *
6173          * If we leave the registers in a conflicting state (e.g. with the
6174          * display plane reading from the other pipe than the one we intend
6175          * to use) then when we attempt to teardown the active mode, we will
6176          * not disable the pipes and planes in the correct order -- leaving
6177          * a plane reading from a disabled pipe and possibly leading to
6178          * undefined behaviour.
6179          */
6180
6181         reg = DSPCNTR(plane);
6182         val = I915_READ(reg);
6183
6184         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6185                 return;
6186         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6187                 return;
6188
6189         /* This display plane is active and attached to the other CPU pipe. */
6190         pipe = !pipe;
6191
6192         /* Disable the plane and wait for it to stop reading from the pipe. */
6193         intel_disable_plane(dev_priv, plane, pipe);
6194         intel_disable_pipe(dev_priv, pipe);
6195 }
6196
6197 static void intel_crtc_reset(struct drm_crtc *crtc)
6198 {
6199         struct drm_device *dev = crtc->dev;
6200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6201
6202         /* Reset flags back to the 'unknown' status so that they
6203          * will be correctly set on the initial modeset.
6204          */
6205         intel_crtc->dpms_mode = -1;
6206
6207         /* We need to fix up any BIOS configuration that conflicts with
6208          * our expectations.
6209          */
6210         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6211 }
6212
6213 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6214         .dpms = intel_crtc_dpms,
6215         .mode_fixup = intel_crtc_mode_fixup,
6216         .mode_set = intel_crtc_mode_set,
6217         .mode_set_base = intel_pipe_set_base,
6218         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6219         .load_lut = intel_crtc_load_lut,
6220         .disable = intel_crtc_disable,
6221 };
6222
6223 static const struct drm_crtc_funcs intel_crtc_funcs = {
6224         .reset = intel_crtc_reset,
6225         .cursor_set = intel_crtc_cursor_set,
6226         .cursor_move = intel_crtc_cursor_move,
6227         .gamma_set = intel_crtc_gamma_set,
6228         .set_config = drm_crtc_helper_set_config,
6229         .destroy = intel_crtc_destroy,
6230         .page_flip = intel_crtc_page_flip,
6231 };
6232
6233 static void intel_pch_pll_init(struct drm_device *dev)
6234 {
6235         drm_i915_private_t *dev_priv = dev->dev_private;
6236         int i;
6237
6238         if (dev_priv->num_pch_pll == 0) {
6239                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6240                 return;
6241         }
6242
6243         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6244                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6245                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6246                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6247         }
6248 }
6249
6250 static void intel_crtc_init(struct drm_device *dev, int pipe)
6251 {
6252         drm_i915_private_t *dev_priv = dev->dev_private;
6253         struct intel_crtc *intel_crtc;
6254         int i;
6255
6256         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6257         if (intel_crtc == NULL)
6258                 return;
6259
6260         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6261
6262         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6263         for (i = 0; i < 256; i++) {
6264                 intel_crtc->lut_r[i] = i;
6265                 intel_crtc->lut_g[i] = i;
6266                 intel_crtc->lut_b[i] = i;
6267         }
6268
6269         /* Swap pipes & planes for FBC on pre-965 */
6270         intel_crtc->pipe = pipe;
6271         intel_crtc->plane = pipe;
6272         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6273                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6274                 intel_crtc->plane = !pipe;
6275         }
6276
6277         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6278                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6279         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6280         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6281
6282         intel_crtc_reset(&intel_crtc->base);
6283         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6284         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6285
6286         if (HAS_PCH_SPLIT(dev)) {
6287                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6288                 intel_helper_funcs.commit = ironlake_crtc_commit;
6289         } else {
6290                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6291                 intel_helper_funcs.commit = i9xx_crtc_commit;
6292         }
6293
6294         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6295
6296         intel_crtc->busy = false;
6297
6298         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6299                     (unsigned long)intel_crtc);
6300 }
6301
6302 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6303                                 struct drm_file *file)
6304 {
6305         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6306         struct drm_mode_object *drmmode_obj;
6307         struct intel_crtc *crtc;
6308
6309         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6310                 return -ENODEV;
6311
6312         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6313                         DRM_MODE_OBJECT_CRTC);
6314
6315         if (!drmmode_obj) {
6316                 DRM_ERROR("no such CRTC id\n");
6317                 return -EINVAL;
6318         }
6319
6320         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6321         pipe_from_crtc_id->pipe = crtc->pipe;
6322
6323         return 0;
6324 }
6325
6326 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6327 {
6328         struct intel_encoder *encoder;
6329         int index_mask = 0;
6330         int entry = 0;
6331
6332         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6333                 if (type_mask & encoder->clone_mask)
6334                         index_mask |= (1 << entry);
6335                 entry++;
6336         }
6337
6338         return index_mask;
6339 }
6340
6341 static bool has_edp_a(struct drm_device *dev)
6342 {
6343         struct drm_i915_private *dev_priv = dev->dev_private;
6344
6345         if (!IS_MOBILE(dev))
6346                 return false;
6347
6348         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6349                 return false;
6350
6351         if (IS_GEN5(dev) &&
6352             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6353                 return false;
6354
6355         return true;
6356 }
6357
6358 static void intel_setup_outputs(struct drm_device *dev)
6359 {
6360         struct drm_i915_private *dev_priv = dev->dev_private;
6361         struct intel_encoder *encoder;
6362         bool dpd_is_edp = false;
6363         bool has_lvds;
6364
6365         has_lvds = intel_lvds_init(dev);
6366         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6367                 /* disable the panel fitter on everything but LVDS */
6368                 I915_WRITE(PFIT_CONTROL, 0);
6369         }
6370
6371         if (HAS_PCH_SPLIT(dev)) {
6372                 dpd_is_edp = intel_dpd_is_edp(dev);
6373
6374                 if (has_edp_a(dev))
6375                         intel_dp_init(dev, DP_A);
6376
6377                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6378                         intel_dp_init(dev, PCH_DP_D);
6379         }
6380
6381         intel_crt_init(dev);
6382
6383         if (HAS_PCH_SPLIT(dev)) {
6384                 int found;
6385
6386                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6387                         /* PCH SDVOB multiplex with HDMIB */
6388                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6389                         if (!found)
6390                                 intel_hdmi_init(dev, HDMIB);
6391                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6392                                 intel_dp_init(dev, PCH_DP_B);
6393                 }
6394
6395                 if (I915_READ(HDMIC) & PORT_DETECTED)
6396                         intel_hdmi_init(dev, HDMIC);
6397
6398                 if (I915_READ(HDMID) & PORT_DETECTED)
6399                         intel_hdmi_init(dev, HDMID);
6400
6401                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6402                         intel_dp_init(dev, PCH_DP_C);
6403
6404                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6405                         intel_dp_init(dev, PCH_DP_D);
6406
6407         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6408                 bool found = false;
6409
6410                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6411                         DRM_DEBUG_KMS("probing SDVOB\n");
6412                         found = intel_sdvo_init(dev, SDVOB, true);
6413                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6414                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6415                                 intel_hdmi_init(dev, SDVOB);
6416                         }
6417
6418                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6419                                 DRM_DEBUG_KMS("probing DP_B\n");
6420                                 intel_dp_init(dev, DP_B);
6421                         }
6422                 }
6423
6424                 /* Before G4X SDVOC doesn't have its own detect register */
6425
6426                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6427                         DRM_DEBUG_KMS("probing SDVOC\n");
6428                         found = intel_sdvo_init(dev, SDVOC, false);
6429                 }
6430
6431                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6432
6433                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6434                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6435                                 intel_hdmi_init(dev, SDVOC);
6436                         }
6437                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6438                                 DRM_DEBUG_KMS("probing DP_C\n");
6439                                 intel_dp_init(dev, DP_C);
6440                         }
6441                 }
6442
6443                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6444                     (I915_READ(DP_D) & DP_DETECTED)) {
6445                         DRM_DEBUG_KMS("probing DP_D\n");
6446                         intel_dp_init(dev, DP_D);
6447                 }
6448         } else if (IS_GEN2(dev))
6449                 intel_dvo_init(dev);
6450
6451         if (SUPPORTS_TV(dev))
6452                 intel_tv_init(dev);
6453
6454         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6455                 encoder->base.possible_crtcs = encoder->crtc_mask;
6456                 encoder->base.possible_clones =
6457                         intel_encoder_clones(dev, encoder->clone_mask);
6458         }
6459
6460         /* disable all the possible outputs/crtcs before entering KMS mode */
6461         drm_helper_disable_unused_functions(dev);
6462
6463         if (HAS_PCH_SPLIT(dev))
6464                 ironlake_init_pch_refclk(dev);
6465 }
6466
6467 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6468 {
6469         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6470
6471         drm_framebuffer_cleanup(fb);
6472         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6473
6474         kfree(intel_fb);
6475 }
6476
6477 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6478                                                 struct drm_file *file,
6479                                                 unsigned int *handle)
6480 {
6481         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6482         struct drm_i915_gem_object *obj = intel_fb->obj;
6483
6484         return drm_gem_handle_create(file, &obj->base, handle);
6485 }
6486
6487 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6488         .destroy = intel_user_framebuffer_destroy,
6489         .create_handle = intel_user_framebuffer_create_handle,
6490 };
6491
6492 int intel_framebuffer_init(struct drm_device *dev,
6493                            struct intel_framebuffer *intel_fb,
6494                            struct drm_mode_fb_cmd2 *mode_cmd,
6495                            struct drm_i915_gem_object *obj)
6496 {
6497         int ret;
6498
6499         if (obj->tiling_mode == I915_TILING_Y)
6500                 return -EINVAL;
6501
6502         if (mode_cmd->pitches[0] & 63)
6503                 return -EINVAL;
6504
6505         switch (mode_cmd->pixel_format) {
6506         case DRM_FORMAT_RGB332:
6507         case DRM_FORMAT_RGB565:
6508         case DRM_FORMAT_XRGB8888:
6509         case DRM_FORMAT_XBGR8888:
6510         case DRM_FORMAT_ARGB8888:
6511         case DRM_FORMAT_XRGB2101010:
6512         case DRM_FORMAT_ARGB2101010:
6513                 /* RGB formats are common across chipsets */
6514                 break;
6515         case DRM_FORMAT_YUYV:
6516         case DRM_FORMAT_UYVY:
6517         case DRM_FORMAT_YVYU:
6518         case DRM_FORMAT_VYUY:
6519                 break;
6520         default:
6521                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6522                                 mode_cmd->pixel_format);
6523                 return -EINVAL;
6524         }
6525
6526         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6527         if (ret) {
6528                 DRM_ERROR("framebuffer init failed %d\n", ret);
6529                 return ret;
6530         }
6531
6532         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6533         intel_fb->obj = obj;
6534         return 0;
6535 }
6536
6537 static struct drm_framebuffer *
6538 intel_user_framebuffer_create(struct drm_device *dev,
6539                               struct drm_file *filp,
6540                               struct drm_mode_fb_cmd2 *mode_cmd)
6541 {
6542         struct drm_i915_gem_object *obj;
6543
6544         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6545                                                 mode_cmd->handles[0]));
6546         if (&obj->base == NULL)
6547                 return ERR_PTR(-ENOENT);
6548
6549         return intel_framebuffer_create(dev, mode_cmd, obj);
6550 }
6551
6552 static const struct drm_mode_config_funcs intel_mode_funcs = {
6553         .fb_create = intel_user_framebuffer_create,
6554         .output_poll_changed = intel_fb_output_poll_changed,
6555 };
6556
6557 /* Set up chip specific display functions */
6558 static void intel_init_display(struct drm_device *dev)
6559 {
6560         struct drm_i915_private *dev_priv = dev->dev_private;
6561
6562         /* We always want a DPMS function */
6563         if (HAS_PCH_SPLIT(dev)) {
6564                 dev_priv->display.dpms = ironlake_crtc_dpms;
6565                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6566                 dev_priv->display.off = ironlake_crtc_off;
6567                 dev_priv->display.update_plane = ironlake_update_plane;
6568         } else {
6569                 dev_priv->display.dpms = i9xx_crtc_dpms;
6570                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6571                 dev_priv->display.off = i9xx_crtc_off;
6572                 dev_priv->display.update_plane = i9xx_update_plane;
6573         }
6574
6575         /* Returns the core display clock speed */
6576         if (IS_VALLEYVIEW(dev))
6577                 dev_priv->display.get_display_clock_speed =
6578                         valleyview_get_display_clock_speed;
6579         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6580                 dev_priv->display.get_display_clock_speed =
6581                         i945_get_display_clock_speed;
6582         else if (IS_I915G(dev))
6583                 dev_priv->display.get_display_clock_speed =
6584                         i915_get_display_clock_speed;
6585         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6586                 dev_priv->display.get_display_clock_speed =
6587                         i9xx_misc_get_display_clock_speed;
6588         else if (IS_I915GM(dev))
6589                 dev_priv->display.get_display_clock_speed =
6590                         i915gm_get_display_clock_speed;
6591         else if (IS_I865G(dev))
6592                 dev_priv->display.get_display_clock_speed =
6593                         i865_get_display_clock_speed;
6594         else if (IS_I85X(dev))
6595                 dev_priv->display.get_display_clock_speed =
6596                         i855_get_display_clock_speed;
6597         else /* 852, 830 */
6598                 dev_priv->display.get_display_clock_speed =
6599                         i830_get_display_clock_speed;
6600
6601         if (HAS_PCH_SPLIT(dev)) {
6602                 if (IS_GEN5(dev)) {
6603                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6604                         dev_priv->display.write_eld = ironlake_write_eld;
6605                 } else if (IS_GEN6(dev)) {
6606                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6607                         dev_priv->display.write_eld = ironlake_write_eld;
6608                 } else if (IS_IVYBRIDGE(dev)) {
6609                         /* FIXME: detect B0+ stepping and use auto training */
6610                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6611                         dev_priv->display.write_eld = ironlake_write_eld;
6612                 } else if (IS_HASWELL(dev)) {
6613                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6614                         dev_priv->display.write_eld = ironlake_write_eld;
6615                 } else
6616                         dev_priv->display.update_wm = NULL;
6617         } else if (IS_VALLEYVIEW(dev)) {
6618                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6619                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6620         } else if (IS_G4X(dev)) {
6621                 dev_priv->display.write_eld = g4x_write_eld;
6622         }
6623
6624         /* Default just returns -ENODEV to indicate unsupported */
6625         dev_priv->display.queue_flip = intel_default_queue_flip;
6626
6627         switch (INTEL_INFO(dev)->gen) {
6628         case 2:
6629                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6630                 break;
6631
6632         case 3:
6633                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6634                 break;
6635
6636         case 4:
6637         case 5:
6638                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6639                 break;
6640
6641         case 6:
6642                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6643                 break;
6644         case 7:
6645                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6646                 break;
6647         }
6648 }
6649
6650 /*
6651  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6652  * resume, or other times.  This quirk makes sure that's the case for
6653  * affected systems.
6654  */
6655 static void quirk_pipea_force(struct drm_device *dev)
6656 {
6657         struct drm_i915_private *dev_priv = dev->dev_private;
6658
6659         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6660         DRM_INFO("applying pipe a force quirk\n");
6661 }
6662
6663 /*
6664  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6665  */
6666 static void quirk_ssc_force_disable(struct drm_device *dev)
6667 {
6668         struct drm_i915_private *dev_priv = dev->dev_private;
6669         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6670         DRM_INFO("applying lvds SSC disable quirk\n");
6671 }
6672
6673 /*
6674  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6675  * brightness value
6676  */
6677 static void quirk_invert_brightness(struct drm_device *dev)
6678 {
6679         struct drm_i915_private *dev_priv = dev->dev_private;
6680         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6681         DRM_INFO("applying inverted panel brightness quirk\n");
6682 }
6683
6684 struct intel_quirk {
6685         int device;
6686         int subsystem_vendor;
6687         int subsystem_device;
6688         void (*hook)(struct drm_device *dev);
6689 };
6690
6691 static struct intel_quirk intel_quirks[] = {
6692         /* HP Mini needs pipe A force quirk (LP: #322104) */
6693         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6694
6695         /* Thinkpad R31 needs pipe A force quirk */
6696         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6697         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6698         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6699
6700         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6701         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6702         /* ThinkPad X40 needs pipe A force quirk */
6703
6704         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6705         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6706
6707         /* 855 & before need to leave pipe A & dpll A up */
6708         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6709         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6710
6711         /* Lenovo U160 cannot use SSC on LVDS */
6712         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6713
6714         /* Sony Vaio Y cannot use SSC on LVDS */
6715         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6716
6717         /* Acer Aspire 5734Z must invert backlight brightness */
6718         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6719 };
6720
6721 static void intel_init_quirks(struct drm_device *dev)
6722 {
6723         struct pci_dev *d = dev->pdev;
6724         int i;
6725
6726         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6727                 struct intel_quirk *q = &intel_quirks[i];
6728
6729                 if (d->device == q->device &&
6730                     (d->subsystem_vendor == q->subsystem_vendor ||
6731                      q->subsystem_vendor == PCI_ANY_ID) &&
6732                     (d->subsystem_device == q->subsystem_device ||
6733                      q->subsystem_device == PCI_ANY_ID))
6734                         q->hook(dev);
6735         }
6736 }
6737
6738 /* Disable the VGA plane that we never use */
6739 static void i915_disable_vga(struct drm_device *dev)
6740 {
6741         struct drm_i915_private *dev_priv = dev->dev_private;
6742         u8 sr1;
6743         u32 vga_reg;
6744
6745         if (HAS_PCH_SPLIT(dev))
6746                 vga_reg = CPU_VGACNTRL;
6747         else
6748                 vga_reg = VGACNTRL;
6749
6750         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6751         outb(SR01, VGA_SR_INDEX);
6752         sr1 = inb(VGA_SR_DATA);
6753         outb(sr1 | 1<<5, VGA_SR_DATA);
6754         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6755         udelay(300);
6756
6757         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6758         POSTING_READ(vga_reg);
6759 }
6760
6761 static void ivb_pch_pwm_override(struct drm_device *dev)
6762 {
6763         struct drm_i915_private *dev_priv = dev->dev_private;
6764
6765         /*
6766          * IVB has CPU eDP backlight regs too, set things up to let the
6767          * PCH regs control the backlight
6768          */
6769         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6770         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6771         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6772 }
6773
6774 void intel_modeset_init_hw(struct drm_device *dev)
6775 {
6776         struct drm_i915_private *dev_priv = dev->dev_private;
6777
6778         intel_init_clock_gating(dev);
6779
6780         if (IS_IRONLAKE_M(dev)) {
6781                 ironlake_enable_drps(dev);
6782                 ironlake_enable_rc6(dev);
6783                 intel_init_emon(dev);
6784         }
6785
6786         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6787                 gen6_enable_rps(dev_priv);
6788                 gen6_update_ring_freq(dev_priv);
6789         }
6790
6791         if (IS_IVYBRIDGE(dev))
6792                 ivb_pch_pwm_override(dev);
6793 }
6794
6795 void intel_modeset_init(struct drm_device *dev)
6796 {
6797         struct drm_i915_private *dev_priv = dev->dev_private;
6798         int i, ret;
6799
6800         drm_mode_config_init(dev);
6801
6802         dev->mode_config.min_width = 0;
6803         dev->mode_config.min_height = 0;
6804
6805         dev->mode_config.preferred_depth = 24;
6806         dev->mode_config.prefer_shadow = 1;
6807
6808         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6809
6810         intel_init_quirks(dev);
6811
6812         intel_init_pm(dev);
6813
6814         intel_prepare_ddi(dev);
6815
6816         intel_init_display(dev);
6817
6818         if (IS_GEN2(dev)) {
6819                 dev->mode_config.max_width = 2048;
6820                 dev->mode_config.max_height = 2048;
6821         } else if (IS_GEN3(dev)) {
6822                 dev->mode_config.max_width = 4096;
6823                 dev->mode_config.max_height = 4096;
6824         } else {
6825                 dev->mode_config.max_width = 8192;
6826                 dev->mode_config.max_height = 8192;
6827         }
6828         dev->mode_config.fb_base = dev->agp->base;
6829
6830         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6831                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6832
6833         for (i = 0; i < dev_priv->num_pipe; i++) {
6834                 intel_crtc_init(dev, i);
6835                 ret = intel_plane_init(dev, i);
6836                 if (ret)
6837                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6838         }
6839
6840         intel_pch_pll_init(dev);
6841
6842         /* Just disable it once at startup */
6843         i915_disable_vga(dev);
6844         intel_setup_outputs(dev);
6845
6846         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6847         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6848                     (unsigned long)dev);
6849 }
6850
6851 void intel_modeset_gem_init(struct drm_device *dev)
6852 {
6853         intel_modeset_init_hw(dev);
6854
6855         intel_setup_overlay(dev);
6856 }
6857
6858 void intel_modeset_cleanup(struct drm_device *dev)
6859 {
6860         struct drm_i915_private *dev_priv = dev->dev_private;
6861         struct drm_crtc *crtc;
6862         struct intel_crtc *intel_crtc;
6863
6864         drm_kms_helper_poll_fini(dev);
6865         mutex_lock(&dev->struct_mutex);
6866
6867         intel_unregister_dsm_handler();
6868
6869
6870         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6871                 /* Skip inactive CRTCs */
6872                 if (!crtc->fb)
6873                         continue;
6874
6875                 intel_crtc = to_intel_crtc(crtc);
6876                 intel_increase_pllclock(crtc);
6877         }
6878
6879         intel_disable_fbc(dev);
6880
6881         if (IS_IRONLAKE_M(dev))
6882                 ironlake_disable_drps(dev);
6883         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6884                 gen6_disable_rps(dev);
6885
6886         if (IS_IRONLAKE_M(dev))
6887                 ironlake_disable_rc6(dev);
6888
6889         if (IS_VALLEYVIEW(dev))
6890                 vlv_init_dpio(dev);
6891
6892         mutex_unlock(&dev->struct_mutex);
6893
6894         /* Disable the irq before mode object teardown, for the irq might
6895          * enqueue unpin/hotplug work. */
6896         drm_irq_uninstall(dev);
6897         cancel_work_sync(&dev_priv->hotplug_work);
6898         cancel_work_sync(&dev_priv->rps_work);
6899
6900         /* flush any delayed tasks or pending work */
6901         flush_scheduled_work();
6902
6903         /* Shut off idle work before the crtcs get freed. */
6904         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6905                 intel_crtc = to_intel_crtc(crtc);
6906                 del_timer_sync(&intel_crtc->idle_timer);
6907         }
6908         del_timer_sync(&dev_priv->idle_timer);
6909         cancel_work_sync(&dev_priv->idle_work);
6910
6911         drm_mode_config_cleanup(dev);
6912 }
6913
6914 /*
6915  * Return which encoder is currently attached for connector.
6916  */
6917 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6918 {
6919         return &intel_attached_encoder(connector)->base;
6920 }
6921
6922 void intel_connector_attach_encoder(struct intel_connector *connector,
6923                                     struct intel_encoder *encoder)
6924 {
6925         connector->encoder = encoder;
6926         drm_mode_connector_attach_encoder(&connector->base,
6927                                           &encoder->base);
6928 }
6929
6930 /*
6931  * set vga decode state - true == enable VGA decode
6932  */
6933 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6934 {
6935         struct drm_i915_private *dev_priv = dev->dev_private;
6936         u16 gmch_ctrl;
6937
6938         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6939         if (state)
6940                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6941         else
6942                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6943         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6944         return 0;
6945 }
6946
6947 #ifdef CONFIG_DEBUG_FS
6948 #include <linux/seq_file.h>
6949
6950 struct intel_display_error_state {
6951         struct intel_cursor_error_state {
6952                 u32 control;
6953                 u32 position;
6954                 u32 base;
6955                 u32 size;
6956         } cursor[2];
6957
6958         struct intel_pipe_error_state {
6959                 u32 conf;
6960                 u32 source;
6961
6962                 u32 htotal;
6963                 u32 hblank;
6964                 u32 hsync;
6965                 u32 vtotal;
6966                 u32 vblank;
6967                 u32 vsync;
6968         } pipe[2];
6969
6970         struct intel_plane_error_state {
6971                 u32 control;
6972                 u32 stride;
6973                 u32 size;
6974                 u32 pos;
6975                 u32 addr;
6976                 u32 surface;
6977                 u32 tile_offset;
6978         } plane[2];
6979 };
6980
6981 struct intel_display_error_state *
6982 intel_display_capture_error_state(struct drm_device *dev)
6983 {
6984         drm_i915_private_t *dev_priv = dev->dev_private;
6985         struct intel_display_error_state *error;
6986         int i;
6987
6988         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6989         if (error == NULL)
6990                 return NULL;
6991
6992         for (i = 0; i < 2; i++) {
6993                 error->cursor[i].control = I915_READ(CURCNTR(i));
6994                 error->cursor[i].position = I915_READ(CURPOS(i));
6995                 error->cursor[i].base = I915_READ(CURBASE(i));
6996
6997                 error->plane[i].control = I915_READ(DSPCNTR(i));
6998                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6999                 error->plane[i].size = I915_READ(DSPSIZE(i));
7000                 error->plane[i].pos = I915_READ(DSPPOS(i));
7001                 error->plane[i].addr = I915_READ(DSPADDR(i));
7002                 if (INTEL_INFO(dev)->gen >= 4) {
7003                         error->plane[i].surface = I915_READ(DSPSURF(i));
7004                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7005                 }
7006
7007                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7008                 error->pipe[i].source = I915_READ(PIPESRC(i));
7009                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7010                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7011                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7012                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7013                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7014                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7015         }
7016
7017         return error;
7018 }
7019
7020 void
7021 intel_display_print_error_state(struct seq_file *m,
7022                                 struct drm_device *dev,
7023                                 struct intel_display_error_state *error)
7024 {
7025         int i;
7026
7027         for (i = 0; i < 2; i++) {
7028                 seq_printf(m, "Pipe [%d]:\n", i);
7029                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7030                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7031                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7032                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7033                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7034                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7035                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7036                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7037
7038                 seq_printf(m, "Plane [%d]:\n", i);
7039                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7040                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7041                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7042                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7043                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7044                 if (INTEL_INFO(dev)->gen >= 4) {
7045                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7046                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7047                 }
7048
7049                 seq_printf(m, "Cursor [%d]:\n", i);
7050                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7051                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7052                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7053         }
7054 }
7055 #endif