drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /*
1371          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1372          * CHV x1 PHY (DP/HDMI D)
1373          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1374          */
1375         if (IS_CHERRYVIEW(dev)) {
1376                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1377                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1378         } else {
1379                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1380         }
1381 }
1382
1383 static void intel_reset_dpio(struct drm_device *dev)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386
1387         if (!IS_VALLEYVIEW(dev))
1388                 return;
1389
1390         /*
1391          * Enable the CRI clock source so we can get at the display and the
1392          * reference clock for VGA hotplug / manual detection.
1393          */
1394         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1395                    DPLL_REFA_CLK_ENABLE_VLV |
1396                    DPLL_INTEGRATED_CRI_CLK_VLV);
1397
1398         /*
1399          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1400          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1401          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1402          *   b. The other bits such as sfr settings / modesel may all be set
1403          *      to 0.
1404          *
1405          * This should only be done on init and resume from S3 with both
1406          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1407          */
1408         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1409 }
1410
1411 static void vlv_enable_pll(struct intel_crtc *crtc)
1412 {
1413         struct drm_device *dev = crtc->base.dev;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         int reg = DPLL(crtc->pipe);
1416         u32 dpll = crtc->config.dpll_hw_state.dpll;
1417
1418         assert_pipe_disabled(dev_priv, crtc->pipe);
1419
1420         /* No really, not for ILK+ */
1421         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1422
1423         /* PLL is protected by panel, make sure we can write it */
1424         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1425                 assert_panel_unlocked(dev_priv, crtc->pipe);
1426
1427         I915_WRITE(reg, dpll);
1428         POSTING_READ(reg);
1429         udelay(150);
1430
1431         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1432                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1433
1434         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1435         POSTING_READ(DPLL_MD(crtc->pipe));
1436
1437         /* We do this three times for luck */
1438         I915_WRITE(reg, dpll);
1439         POSTING_READ(reg);
1440         udelay(150); /* wait for warmup */
1441         I915_WRITE(reg, dpll);
1442         POSTING_READ(reg);
1443         udelay(150); /* wait for warmup */
1444         I915_WRITE(reg, dpll);
1445         POSTING_READ(reg);
1446         udelay(150); /* wait for warmup */
1447 }
1448
1449 static void i9xx_enable_pll(struct intel_crtc *crtc)
1450 {
1451         struct drm_device *dev = crtc->base.dev;
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         int reg = DPLL(crtc->pipe);
1454         u32 dpll = crtc->config.dpll_hw_state.dpll;
1455
1456         assert_pipe_disabled(dev_priv, crtc->pipe);
1457
1458         /* No really, not for ILK+ */
1459         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1460
1461         /* PLL is protected by panel, make sure we can write it */
1462         if (IS_MOBILE(dev) && !IS_I830(dev))
1463                 assert_panel_unlocked(dev_priv, crtc->pipe);
1464
1465         I915_WRITE(reg, dpll);
1466
1467         /* Wait for the clocks to stabilize. */
1468         POSTING_READ(reg);
1469         udelay(150);
1470
1471         if (INTEL_INFO(dev)->gen >= 4) {
1472                 I915_WRITE(DPLL_MD(crtc->pipe),
1473                            crtc->config.dpll_hw_state.dpll_md);
1474         } else {
1475                 /* The pixel multiplier can only be updated once the
1476                  * DPLL is enabled and the clocks are stable.
1477                  *
1478                  * So write it again.
1479                  */
1480                 I915_WRITE(reg, dpll);
1481         }
1482
1483         /* We do this three times for luck */
1484         I915_WRITE(reg, dpll);
1485         POSTING_READ(reg);
1486         udelay(150); /* wait for warmup */
1487         I915_WRITE(reg, dpll);
1488         POSTING_READ(reg);
1489         udelay(150); /* wait for warmup */
1490         I915_WRITE(reg, dpll);
1491         POSTING_READ(reg);
1492         udelay(150); /* wait for warmup */
1493 }
1494
1495 /**
1496  * i9xx_disable_pll - disable a PLL
1497  * @dev_priv: i915 private structure
1498  * @pipe: pipe PLL to disable
1499  *
1500  * Disable the PLL for @pipe, making sure the pipe is off first.
1501  *
1502  * Note!  This is for pre-ILK only.
1503  */
1504 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         /* Don't disable pipe A or pipe A PLLs if needed */
1507         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1508                 return;
1509
1510         /* Make sure the pipe isn't still relying on us */
1511         assert_pipe_disabled(dev_priv, pipe);
1512
1513         I915_WRITE(DPLL(pipe), 0);
1514         POSTING_READ(DPLL(pipe));
1515 }
1516
1517 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1518 {
1519         u32 val = 0;
1520
1521         /* Make sure the pipe isn't still relying on us */
1522         assert_pipe_disabled(dev_priv, pipe);
1523
1524         /*
1525          * Leave integrated clock source and reference clock enabled for pipe B.
1526          * The latter is needed for VGA hotplug / manual detection.
1527          */
1528         if (pipe == PIPE_B)
1529                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1530         I915_WRITE(DPLL(pipe), val);
1531         POSTING_READ(DPLL(pipe));
1532 }
1533
1534 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1535                 struct intel_digital_port *dport)
1536 {
1537         u32 port_mask;
1538         int dpll_reg;
1539
1540         switch (dport->port) {
1541         case PORT_B:
1542                 port_mask = DPLL_PORTB_READY_MASK;
1543                 dpll_reg = DPLL(0);
1544                 break;
1545         case PORT_C:
1546                 port_mask = DPLL_PORTC_READY_MASK;
1547                 dpll_reg = DPLL(0);
1548                 break;
1549         case PORT_D:
1550                 port_mask = DPLL_PORTD_READY_MASK;
1551                 dpll_reg = DPIO_PHY_STATUS;
1552                 break;
1553         default:
1554                 BUG();
1555         }
1556
1557         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1558                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1559                      port_name(dport->port), I915_READ(dpll_reg));
1560 }
1561
1562 /**
1563  * ironlake_enable_shared_dpll - enable PCH PLL
1564  * @dev_priv: i915 private structure
1565  * @pipe: pipe PLL to enable
1566  *
1567  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1568  * drives the transcoder clock.
1569  */
1570 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1571 {
1572         struct drm_device *dev = crtc->base.dev;
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1575
1576         /* PCH PLLs only available on ILK, SNB and IVB */
1577         BUG_ON(INTEL_INFO(dev)->gen < 5);
1578         if (WARN_ON(pll == NULL))
1579                 return;
1580
1581         if (WARN_ON(pll->refcount == 0))
1582                 return;
1583
1584         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1585                       pll->name, pll->active, pll->on,
1586                       crtc->base.base.id);
1587
1588         if (pll->active++) {
1589                 WARN_ON(!pll->on);
1590                 assert_shared_dpll_enabled(dev_priv, pll);
1591                 return;
1592         }
1593         WARN_ON(pll->on);
1594
1595         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1596         pll->enable(dev_priv, pll);
1597         pll->on = true;
1598 }
1599
1600 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1605
1606         /* PCH only available on ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen < 5);
1608         if (WARN_ON(pll == NULL))
1609                return;
1610
1611         if (WARN_ON(pll->refcount == 0))
1612                 return;
1613
1614         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1615                       pll->name, pll->active, pll->on,
1616                       crtc->base.base.id);
1617
1618         if (WARN_ON(pll->active == 0)) {
1619                 assert_shared_dpll_disabled(dev_priv, pll);
1620                 return;
1621         }
1622
1623         assert_shared_dpll_enabled(dev_priv, pll);
1624         WARN_ON(!pll->on);
1625         if (--pll->active)
1626                 return;
1627
1628         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1629         pll->disable(dev_priv, pll);
1630         pll->on = false;
1631 }
1632
1633 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1634                                            enum pipe pipe)
1635 {
1636         struct drm_device *dev = dev_priv->dev;
1637         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1639         uint32_t reg, val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(INTEL_INFO(dev)->gen < 5);
1643
1644         /* Make sure PCH DPLL is enabled */
1645         assert_shared_dpll_enabled(dev_priv,
1646                                    intel_crtc_to_shared_dpll(intel_crtc));
1647
1648         /* FDI must be feeding us bits for PCH ports */
1649         assert_fdi_tx_enabled(dev_priv, pipe);
1650         assert_fdi_rx_enabled(dev_priv, pipe);
1651
1652         if (HAS_PCH_CPT(dev)) {
1653                 /* Workaround: Set the timing override bit before enabling the
1654                  * pch transcoder. */
1655                 reg = TRANS_CHICKEN2(pipe);
1656                 val = I915_READ(reg);
1657                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1658                 I915_WRITE(reg, val);
1659         }
1660
1661         reg = PCH_TRANSCONF(pipe);
1662         val = I915_READ(reg);
1663         pipeconf_val = I915_READ(PIPECONF(pipe));
1664
1665         if (HAS_PCH_IBX(dev_priv->dev)) {
1666                 /*
1667                  * make the BPC in transcoder be consistent with
1668                  * that in pipeconf reg.
1669                  */
1670                 val &= ~PIPECONF_BPC_MASK;
1671                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1672         }
1673
1674         val &= ~TRANS_INTERLACE_MASK;
1675         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1676                 if (HAS_PCH_IBX(dev_priv->dev) &&
1677                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1678                         val |= TRANS_LEGACY_INTERLACED_ILK;
1679                 else
1680                         val |= TRANS_INTERLACED;
1681         else
1682                 val |= TRANS_PROGRESSIVE;
1683
1684         I915_WRITE(reg, val | TRANS_ENABLE);
1685         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1686                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1687 }
1688
1689 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1690                                       enum transcoder cpu_transcoder)
1691 {
1692         u32 val, pipeconf_val;
1693
1694         /* PCH only available on ILK+ */
1695         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1696
1697         /* FDI must be feeding us bits for PCH ports */
1698         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1699         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1700
1701         /* Workaround: set timing override bit. */
1702         val = I915_READ(_TRANSA_CHICKEN2);
1703         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1704         I915_WRITE(_TRANSA_CHICKEN2, val);
1705
1706         val = TRANS_ENABLE;
1707         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1708
1709         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1710             PIPECONF_INTERLACED_ILK)
1711                 val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(LPT_TRANSCONF, val);
1716         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("Failed to enable PCH transcoder\n");
1718 }
1719
1720 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                             enum pipe pipe)
1722 {
1723         struct drm_device *dev = dev_priv->dev;
1724         uint32_t reg, val;
1725
1726         /* FDI relies on the transcoder */
1727         assert_fdi_tx_disabled(dev_priv, pipe);
1728         assert_fdi_rx_disabled(dev_priv, pipe);
1729
1730         /* Ports must be off as well */
1731         assert_pch_ports_disabled(dev_priv, pipe);
1732
1733         reg = PCH_TRANSCONF(pipe);
1734         val = I915_READ(reg);
1735         val &= ~TRANS_ENABLE;
1736         I915_WRITE(reg, val);
1737         /* wait for PCH transcoder off, transcoder state */
1738         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1739                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1740
1741         if (!HAS_PCH_IBX(dev)) {
1742                 /* Workaround: Clear the timing override chicken bit again. */
1743                 reg = TRANS_CHICKEN2(pipe);
1744                 val = I915_READ(reg);
1745                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1746                 I915_WRITE(reg, val);
1747         }
1748 }
1749
1750 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1751 {
1752         u32 val;
1753
1754         val = I915_READ(LPT_TRANSCONF);
1755         val &= ~TRANS_ENABLE;
1756         I915_WRITE(LPT_TRANSCONF, val);
1757         /* wait for PCH transcoder off, transcoder state */
1758         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1759                 DRM_ERROR("Failed to disable PCH transcoder\n");
1760
1761         /* Workaround: clear timing override bit. */
1762         val = I915_READ(_TRANSA_CHICKEN2);
1763         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1764         I915_WRITE(_TRANSA_CHICKEN2, val);
1765 }
1766
1767 /**
1768  * intel_enable_pipe - enable a pipe, asserting requirements
1769  * @crtc: crtc responsible for the pipe
1770  *
1771  * Enable @crtc's pipe, making sure that various hardware specific requirements
1772  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1773  */
1774 static void intel_enable_pipe(struct intel_crtc *crtc)
1775 {
1776         struct drm_device *dev = crtc->base.dev;
1777         struct drm_i915_private *dev_priv = dev->dev_private;
1778         enum pipe pipe = crtc->pipe;
1779         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1780                                                                       pipe);
1781         enum pipe pch_transcoder;
1782         int reg;
1783         u32 val;
1784
1785         assert_planes_disabled(dev_priv, pipe);
1786         assert_cursor_disabled(dev_priv, pipe);
1787         assert_sprites_disabled(dev_priv, pipe);
1788
1789         if (HAS_PCH_LPT(dev_priv->dev))
1790                 pch_transcoder = TRANSCODER_A;
1791         else
1792                 pch_transcoder = pipe;
1793
1794         /*
1795          * A pipe without a PLL won't actually be able to drive bits from
1796          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1797          * need the check.
1798          */
1799         if (!HAS_PCH_SPLIT(dev_priv->dev))
1800                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1801                         assert_dsi_pll_enabled(dev_priv);
1802                 else
1803                         assert_pll_enabled(dev_priv, pipe);
1804         else {
1805                 if (crtc->config.has_pch_encoder) {
1806                         /* if driving the PCH, we need FDI enabled */
1807                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1808                         assert_fdi_tx_pll_enabled(dev_priv,
1809                                                   (enum pipe) cpu_transcoder);
1810                 }
1811                 /* FIXME: assert CPU port conditions for SNB+ */
1812         }
1813
1814         reg = PIPECONF(cpu_transcoder);
1815         val = I915_READ(reg);
1816         if (val & PIPECONF_ENABLE) {
1817                 WARN_ON(!(pipe == PIPE_A &&
1818                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1819                 return;
1820         }
1821
1822         I915_WRITE(reg, val | PIPECONF_ENABLE);
1823         POSTING_READ(reg);
1824 }
1825
1826 /**
1827  * intel_disable_pipe - disable a pipe, asserting requirements
1828  * @dev_priv: i915 private structure
1829  * @pipe: pipe to disable
1830  *
1831  * Disable @pipe, making sure that various hardware specific requirements
1832  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1833  *
1834  * @pipe should be %PIPE_A or %PIPE_B.
1835  *
1836  * Will wait until the pipe has shut down before returning.
1837  */
1838 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1839                                enum pipe pipe)
1840 {
1841         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1842                                                                       pipe);
1843         int reg;
1844         u32 val;
1845
1846         /*
1847          * Make sure planes won't keep trying to pump pixels to us,
1848          * or we might hang the display.
1849          */
1850         assert_planes_disabled(dev_priv, pipe);
1851         assert_cursor_disabled(dev_priv, pipe);
1852         assert_sprites_disabled(dev_priv, pipe);
1853
1854         /* Don't disable pipe A or pipe A PLLs if needed */
1855         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1856                 return;
1857
1858         reg = PIPECONF(cpu_transcoder);
1859         val = I915_READ(reg);
1860         if ((val & PIPECONF_ENABLE) == 0)
1861                 return;
1862
1863         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1864         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1865 }
1866
1867 /*
1868  * Plane regs are double buffered, going from enabled->disabled needs a
1869  * trigger in order to latch.  The display address reg provides this.
1870  */
1871 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1872                                enum plane plane)
1873 {
1874         struct drm_device *dev = dev_priv->dev;
1875         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1876
1877         I915_WRITE(reg, I915_READ(reg));
1878         POSTING_READ(reg);
1879 }
1880
1881 /**
1882  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1883  * @dev_priv: i915 private structure
1884  * @plane: plane to enable
1885  * @pipe: pipe being fed
1886  *
1887  * Enable @plane on @pipe, making sure that @pipe is running first.
1888  */
1889 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1890                                           enum plane plane, enum pipe pipe)
1891 {
1892         struct intel_crtc *intel_crtc =
1893                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1894         int reg;
1895         u32 val;
1896
1897         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1898         assert_pipe_enabled(dev_priv, pipe);
1899
1900         if (intel_crtc->primary_enabled)
1901                 return;
1902
1903         intel_crtc->primary_enabled = true;
1904
1905         reg = DSPCNTR(plane);
1906         val = I915_READ(reg);
1907         WARN_ON(val & DISPLAY_PLANE_ENABLE);
1908
1909         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1910         intel_flush_primary_plane(dev_priv, plane);
1911         intel_wait_for_vblank(dev_priv->dev, pipe);
1912 }
1913
1914 /**
1915  * intel_disable_primary_hw_plane - disable the primary hardware plane
1916  * @dev_priv: i915 private structure
1917  * @plane: plane to disable
1918  * @pipe: pipe consuming the data
1919  *
1920  * Disable @plane; should be an independent operation.
1921  */
1922 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1923                                            enum plane plane, enum pipe pipe)
1924 {
1925         struct intel_crtc *intel_crtc =
1926                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1927         int reg;
1928         u32 val;
1929
1930         if (!intel_crtc->primary_enabled)
1931                 return;
1932
1933         intel_crtc->primary_enabled = false;
1934
1935         reg = DSPCNTR(plane);
1936         val = I915_READ(reg);
1937         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
1938
1939         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1940         intel_flush_primary_plane(dev_priv, plane);
1941         intel_wait_for_vblank(dev_priv->dev, pipe);
1942 }
1943
1944 static bool need_vtd_wa(struct drm_device *dev)
1945 {
1946 #ifdef CONFIG_INTEL_IOMMU
1947         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1948                 return true;
1949 #endif
1950         return false;
1951 }
1952
1953 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1954 {
1955         int tile_height;
1956
1957         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1958         return ALIGN(height, tile_height);
1959 }
1960
1961 int
1962 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1963                            struct drm_i915_gem_object *obj,
1964                            struct intel_ring_buffer *pipelined)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         u32 alignment;
1968         int ret;
1969
1970         switch (obj->tiling_mode) {
1971         case I915_TILING_NONE:
1972                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1973                         alignment = 128 * 1024;
1974                 else if (INTEL_INFO(dev)->gen >= 4)
1975                         alignment = 4 * 1024;
1976                 else
1977                         alignment = 64 * 1024;
1978                 break;
1979         case I915_TILING_X:
1980                 /* pin() will align the object as required by fence */
1981                 alignment = 0;
1982                 break;
1983         case I915_TILING_Y:
1984                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1985                 return -EINVAL;
1986         default:
1987                 BUG();
1988         }
1989
1990         /* Note that the w/a also requires 64 PTE of padding following the
1991          * bo. We currently fill all unused PTE with the shadow page and so
1992          * we should always have valid PTE following the scanout preventing
1993          * the VT-d warning.
1994          */
1995         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1996                 alignment = 256 * 1024;
1997
1998         dev_priv->mm.interruptible = false;
1999         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2000         if (ret)
2001                 goto err_interruptible;
2002
2003         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2004          * fence, whereas 965+ only requires a fence if using
2005          * framebuffer compression.  For simplicity, we always install
2006          * a fence as the cost is not that onerous.
2007          */
2008         ret = i915_gem_object_get_fence(obj);
2009         if (ret)
2010                 goto err_unpin;
2011
2012         i915_gem_object_pin_fence(obj);
2013
2014         dev_priv->mm.interruptible = true;
2015         return 0;
2016
2017 err_unpin:
2018         i915_gem_object_unpin_from_display_plane(obj);
2019 err_interruptible:
2020         dev_priv->mm.interruptible = true;
2021         return ret;
2022 }
2023
2024 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2025 {
2026         i915_gem_object_unpin_fence(obj);
2027         i915_gem_object_unpin_from_display_plane(obj);
2028 }
2029
2030 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2031  * is assumed to be a power-of-two. */
2032 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2033                                              unsigned int tiling_mode,
2034                                              unsigned int cpp,
2035                                              unsigned int pitch)
2036 {
2037         if (tiling_mode != I915_TILING_NONE) {
2038                 unsigned int tile_rows, tiles;
2039
2040                 tile_rows = *y / 8;
2041                 *y %= 8;
2042
2043                 tiles = *x / (512/cpp);
2044                 *x %= 512/cpp;
2045
2046                 return tile_rows * pitch * 8 + tiles * 4096;
2047         } else {
2048                 unsigned int offset;
2049
2050                 offset = *y * pitch + *x * cpp;
2051                 *y = 0;
2052                 *x = (offset & 4095) / cpp;
2053                 return offset & -4096;
2054         }
2055 }
2056
2057 int intel_format_to_fourcc(int format)
2058 {
2059         switch (format) {
2060         case DISPPLANE_8BPP:
2061                 return DRM_FORMAT_C8;
2062         case DISPPLANE_BGRX555:
2063                 return DRM_FORMAT_XRGB1555;
2064         case DISPPLANE_BGRX565:
2065                 return DRM_FORMAT_RGB565;
2066         default:
2067         case DISPPLANE_BGRX888:
2068                 return DRM_FORMAT_XRGB8888;
2069         case DISPPLANE_RGBX888:
2070                 return DRM_FORMAT_XBGR8888;
2071         case DISPPLANE_BGRX101010:
2072                 return DRM_FORMAT_XRGB2101010;
2073         case DISPPLANE_RGBX101010:
2074                 return DRM_FORMAT_XBGR2101010;
2075         }
2076 }
2077
2078 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2079                                   struct intel_plane_config *plane_config)
2080 {
2081         struct drm_device *dev = crtc->base.dev;
2082         struct drm_i915_gem_object *obj = NULL;
2083         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2084         u32 base = plane_config->base;
2085
2086         if (plane_config->size == 0)
2087                 return false;
2088
2089         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2090                                                              plane_config->size);
2091         if (!obj)
2092                 return false;
2093
2094         if (plane_config->tiled) {
2095                 obj->tiling_mode = I915_TILING_X;
2096                 obj->stride = crtc->base.primary->fb->pitches[0];
2097         }
2098
2099         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2100         mode_cmd.width = crtc->base.primary->fb->width;
2101         mode_cmd.height = crtc->base.primary->fb->height;
2102         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2103
2104         mutex_lock(&dev->struct_mutex);
2105
2106         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2107                                    &mode_cmd, obj)) {
2108                 DRM_DEBUG_KMS("intel fb init failed\n");
2109                 goto out_unref_obj;
2110         }
2111
2112         mutex_unlock(&dev->struct_mutex);
2113
2114         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2115         return true;
2116
2117 out_unref_obj:
2118         drm_gem_object_unreference(&obj->base);
2119         mutex_unlock(&dev->struct_mutex);
2120         return false;
2121 }
2122
2123 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2124                                  struct intel_plane_config *plane_config)
2125 {
2126         struct drm_device *dev = intel_crtc->base.dev;
2127         struct drm_crtc *c;
2128         struct intel_crtc *i;
2129         struct intel_framebuffer *fb;
2130
2131         if (!intel_crtc->base.primary->fb)
2132                 return;
2133
2134         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2135                 return;
2136
2137         kfree(intel_crtc->base.primary->fb);
2138         intel_crtc->base.primary->fb = NULL;
2139
2140         /*
2141          * Failed to alloc the obj, check to see if we should share
2142          * an fb with another CRTC instead
2143          */
2144         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2145                 i = to_intel_crtc(c);
2146
2147                 if (c == &intel_crtc->base)
2148                         continue;
2149
2150                 if (!i->active || !c->primary->fb)
2151                         continue;
2152
2153                 fb = to_intel_framebuffer(c->primary->fb);
2154                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2155                         drm_framebuffer_reference(c->primary->fb);
2156                         intel_crtc->base.primary->fb = c->primary->fb;
2157                         break;
2158                 }
2159         }
2160 }
2161
2162 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2163                                      struct drm_framebuffer *fb,
2164                                      int x, int y)
2165 {
2166         struct drm_device *dev = crtc->dev;
2167         struct drm_i915_private *dev_priv = dev->dev_private;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169         struct intel_framebuffer *intel_fb;
2170         struct drm_i915_gem_object *obj;
2171         int plane = intel_crtc->plane;
2172         unsigned long linear_offset;
2173         u32 dspcntr;
2174         u32 reg;
2175
2176         intel_fb = to_intel_framebuffer(fb);
2177         obj = intel_fb->obj;
2178
2179         reg = DSPCNTR(plane);
2180         dspcntr = I915_READ(reg);
2181         /* Mask out pixel format bits in case we change it */
2182         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2183         switch (fb->pixel_format) {
2184         case DRM_FORMAT_C8:
2185                 dspcntr |= DISPPLANE_8BPP;
2186                 break;
2187         case DRM_FORMAT_XRGB1555:
2188         case DRM_FORMAT_ARGB1555:
2189                 dspcntr |= DISPPLANE_BGRX555;
2190                 break;
2191         case DRM_FORMAT_RGB565:
2192                 dspcntr |= DISPPLANE_BGRX565;
2193                 break;
2194         case DRM_FORMAT_XRGB8888:
2195         case DRM_FORMAT_ARGB8888:
2196                 dspcntr |= DISPPLANE_BGRX888;
2197                 break;
2198         case DRM_FORMAT_XBGR8888:
2199         case DRM_FORMAT_ABGR8888:
2200                 dspcntr |= DISPPLANE_RGBX888;
2201                 break;
2202         case DRM_FORMAT_XRGB2101010:
2203         case DRM_FORMAT_ARGB2101010:
2204                 dspcntr |= DISPPLANE_BGRX101010;
2205                 break;
2206         case DRM_FORMAT_XBGR2101010:
2207         case DRM_FORMAT_ABGR2101010:
2208                 dspcntr |= DISPPLANE_RGBX101010;
2209                 break;
2210         default:
2211                 BUG();
2212         }
2213
2214         if (INTEL_INFO(dev)->gen >= 4) {
2215                 if (obj->tiling_mode != I915_TILING_NONE)
2216                         dspcntr |= DISPPLANE_TILED;
2217                 else
2218                         dspcntr &= ~DISPPLANE_TILED;
2219         }
2220
2221         if (IS_G4X(dev))
2222                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2223
2224         I915_WRITE(reg, dspcntr);
2225
2226         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2227
2228         if (INTEL_INFO(dev)->gen >= 4) {
2229                 intel_crtc->dspaddr_offset =
2230                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2231                                                        fb->bits_per_pixel / 8,
2232                                                        fb->pitches[0]);
2233                 linear_offset -= intel_crtc->dspaddr_offset;
2234         } else {
2235                 intel_crtc->dspaddr_offset = linear_offset;
2236         }
2237
2238         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2239                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2240                       fb->pitches[0]);
2241         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2242         if (INTEL_INFO(dev)->gen >= 4) {
2243                 I915_WRITE(DSPSURF(plane),
2244                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2245                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2246                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2247         } else
2248                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2249         POSTING_READ(reg);
2250
2251         return 0;
2252 }
2253
2254 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2255                                          struct drm_framebuffer *fb,
2256                                          int x, int y)
2257 {
2258         struct drm_device *dev = crtc->dev;
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2261         struct intel_framebuffer *intel_fb;
2262         struct drm_i915_gem_object *obj;
2263         int plane = intel_crtc->plane;
2264         unsigned long linear_offset;
2265         u32 dspcntr;
2266         u32 reg;
2267
2268         intel_fb = to_intel_framebuffer(fb);
2269         obj = intel_fb->obj;
2270
2271         reg = DSPCNTR(plane);
2272         dspcntr = I915_READ(reg);
2273         /* Mask out pixel format bits in case we change it */
2274         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2275         switch (fb->pixel_format) {
2276         case DRM_FORMAT_C8:
2277                 dspcntr |= DISPPLANE_8BPP;
2278                 break;
2279         case DRM_FORMAT_RGB565:
2280                 dspcntr |= DISPPLANE_BGRX565;
2281                 break;
2282         case DRM_FORMAT_XRGB8888:
2283         case DRM_FORMAT_ARGB8888:
2284                 dspcntr |= DISPPLANE_BGRX888;
2285                 break;
2286         case DRM_FORMAT_XBGR8888:
2287         case DRM_FORMAT_ABGR8888:
2288                 dspcntr |= DISPPLANE_RGBX888;
2289                 break;
2290         case DRM_FORMAT_XRGB2101010:
2291         case DRM_FORMAT_ARGB2101010:
2292                 dspcntr |= DISPPLANE_BGRX101010;
2293                 break;
2294         case DRM_FORMAT_XBGR2101010:
2295         case DRM_FORMAT_ABGR2101010:
2296                 dspcntr |= DISPPLANE_RGBX101010;
2297                 break;
2298         default:
2299                 BUG();
2300         }
2301
2302         if (obj->tiling_mode != I915_TILING_NONE)
2303                 dspcntr |= DISPPLANE_TILED;
2304         else
2305                 dspcntr &= ~DISPPLANE_TILED;
2306
2307         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2308                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2309         else
2310                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2311
2312         I915_WRITE(reg, dspcntr);
2313
2314         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2315         intel_crtc->dspaddr_offset =
2316                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2317                                                fb->bits_per_pixel / 8,
2318                                                fb->pitches[0]);
2319         linear_offset -= intel_crtc->dspaddr_offset;
2320
2321         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2322                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2323                       fb->pitches[0]);
2324         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2325         I915_WRITE(DSPSURF(plane),
2326                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2327         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2328                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2329         } else {
2330                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2331                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2332         }
2333         POSTING_READ(reg);
2334
2335         return 0;
2336 }
2337
2338 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2339 static int
2340 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2341                            int x, int y, enum mode_set_atomic state)
2342 {
2343         struct drm_device *dev = crtc->dev;
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345
2346         if (dev_priv->display.disable_fbc)
2347                 dev_priv->display.disable_fbc(dev);
2348         intel_increase_pllclock(crtc);
2349
2350         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2351 }
2352
2353 void intel_display_handle_reset(struct drm_device *dev)
2354 {
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         struct drm_crtc *crtc;
2357
2358         /*
2359          * Flips in the rings have been nuked by the reset,
2360          * so complete all pending flips so that user space
2361          * will get its events and not get stuck.
2362          *
2363          * Also update the base address of all primary
2364          * planes to the the last fb to make sure we're
2365          * showing the correct fb after a reset.
2366          *
2367          * Need to make two loops over the crtcs so that we
2368          * don't try to grab a crtc mutex before the
2369          * pending_flip_queue really got woken up.
2370          */
2371
2372         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2373                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2374                 enum plane plane = intel_crtc->plane;
2375
2376                 intel_prepare_page_flip(dev, plane);
2377                 intel_finish_page_flip_plane(dev, plane);
2378         }
2379
2380         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2381                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382
2383                 mutex_lock(&crtc->mutex);
2384                 /*
2385                  * FIXME: Once we have proper support for primary planes (and
2386                  * disabling them without disabling the entire crtc) allow again
2387                  * a NULL crtc->primary->fb.
2388                  */
2389                 if (intel_crtc->active && crtc->primary->fb)
2390                         dev_priv->display.update_primary_plane(crtc,
2391                                                                crtc->primary->fb,
2392                                                                crtc->x,
2393                                                                crtc->y);
2394                 mutex_unlock(&crtc->mutex);
2395         }
2396 }
2397
2398 static int
2399 intel_finish_fb(struct drm_framebuffer *old_fb)
2400 {
2401         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2402         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2403         bool was_interruptible = dev_priv->mm.interruptible;
2404         int ret;
2405
2406         /* Big Hammer, we also need to ensure that any pending
2407          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2408          * current scanout is retired before unpinning the old
2409          * framebuffer.
2410          *
2411          * This should only fail upon a hung GPU, in which case we
2412          * can safely continue.
2413          */
2414         dev_priv->mm.interruptible = false;
2415         ret = i915_gem_object_finish_gpu(obj);
2416         dev_priv->mm.interruptible = was_interruptible;
2417
2418         return ret;
2419 }
2420
2421 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         unsigned long flags;
2427         bool pending;
2428
2429         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2430             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2431                 return false;
2432
2433         spin_lock_irqsave(&dev->event_lock, flags);
2434         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2435         spin_unlock_irqrestore(&dev->event_lock, flags);
2436
2437         return pending;
2438 }
2439
2440 static int
2441 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2442                     struct drm_framebuffer *fb)
2443 {
2444         struct drm_device *dev = crtc->dev;
2445         struct drm_i915_private *dev_priv = dev->dev_private;
2446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447         struct drm_framebuffer *old_fb;
2448         int ret;
2449
2450         if (intel_crtc_has_pending_flip(crtc)) {
2451                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2452                 return -EBUSY;
2453         }
2454
2455         /* no fb bound */
2456         if (!fb) {
2457                 DRM_ERROR("No FB bound\n");
2458                 return 0;
2459         }
2460
2461         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2462                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2463                           plane_name(intel_crtc->plane),
2464                           INTEL_INFO(dev)->num_pipes);
2465                 return -EINVAL;
2466         }
2467
2468         mutex_lock(&dev->struct_mutex);
2469         ret = intel_pin_and_fence_fb_obj(dev,
2470                                          to_intel_framebuffer(fb)->obj,
2471                                          NULL);
2472         mutex_unlock(&dev->struct_mutex);
2473         if (ret != 0) {
2474                 DRM_ERROR("pin & fence failed\n");
2475                 return ret;
2476         }
2477
2478         /*
2479          * Update pipe size and adjust fitter if needed: the reason for this is
2480          * that in compute_mode_changes we check the native mode (not the pfit
2481          * mode) to see if we can flip rather than do a full mode set. In the
2482          * fastboot case, we'll flip, but if we don't update the pipesrc and
2483          * pfit state, we'll end up with a big fb scanned out into the wrong
2484          * sized surface.
2485          *
2486          * To fix this properly, we need to hoist the checks up into
2487          * compute_mode_changes (or above), check the actual pfit state and
2488          * whether the platform allows pfit disable with pipe active, and only
2489          * then update the pipesrc and pfit state, even on the flip path.
2490          */
2491         if (i915.fastboot) {
2492                 const struct drm_display_mode *adjusted_mode =
2493                         &intel_crtc->config.adjusted_mode;
2494
2495                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2496                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2497                            (adjusted_mode->crtc_vdisplay - 1));
2498                 if (!intel_crtc->config.pch_pfit.enabled &&
2499                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2500                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2501                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2502                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2503                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2504                 }
2505                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2506                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2507         }
2508
2509         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2510         if (ret) {
2511                 mutex_lock(&dev->struct_mutex);
2512                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2513                 mutex_unlock(&dev->struct_mutex);
2514                 DRM_ERROR("failed to update base address\n");
2515                 return ret;
2516         }
2517
2518         old_fb = crtc->primary->fb;
2519         crtc->primary->fb = fb;
2520         crtc->x = x;
2521         crtc->y = y;
2522
2523         if (old_fb) {
2524                 if (intel_crtc->active && old_fb != fb)
2525                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2526                 mutex_lock(&dev->struct_mutex);
2527                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2528                 mutex_unlock(&dev->struct_mutex);
2529         }
2530
2531         mutex_lock(&dev->struct_mutex);
2532         intel_update_fbc(dev);
2533         intel_edp_psr_update(dev);
2534         mutex_unlock(&dev->struct_mutex);
2535
2536         return 0;
2537 }
2538
2539 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2540 {
2541         struct drm_device *dev = crtc->dev;
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2544         int pipe = intel_crtc->pipe;
2545         u32 reg, temp;
2546
2547         /* enable normal train */
2548         reg = FDI_TX_CTL(pipe);
2549         temp = I915_READ(reg);
2550         if (IS_IVYBRIDGE(dev)) {
2551                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2552                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2553         } else {
2554                 temp &= ~FDI_LINK_TRAIN_NONE;
2555                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2556         }
2557         I915_WRITE(reg, temp);
2558
2559         reg = FDI_RX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         if (HAS_PCH_CPT(dev)) {
2562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2564         } else {
2565                 temp &= ~FDI_LINK_TRAIN_NONE;
2566                 temp |= FDI_LINK_TRAIN_NONE;
2567         }
2568         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2569
2570         /* wait one idle pattern time */
2571         POSTING_READ(reg);
2572         udelay(1000);
2573
2574         /* IVB wants error correction enabled */
2575         if (IS_IVYBRIDGE(dev))
2576                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2577                            FDI_FE_ERRC_ENABLE);
2578 }
2579
2580 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2581 {
2582         return crtc->base.enabled && crtc->active &&
2583                 crtc->config.has_pch_encoder;
2584 }
2585
2586 static void ivb_modeset_global_resources(struct drm_device *dev)
2587 {
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct intel_crtc *pipe_B_crtc =
2590                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2591         struct intel_crtc *pipe_C_crtc =
2592                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2593         uint32_t temp;
2594
2595         /*
2596          * When everything is off disable fdi C so that we could enable fdi B
2597          * with all lanes. Note that we don't care about enabled pipes without
2598          * an enabled pch encoder.
2599          */
2600         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2601             !pipe_has_enabled_pch(pipe_C_crtc)) {
2602                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2603                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2604
2605                 temp = I915_READ(SOUTH_CHICKEN1);
2606                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2607                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2608                 I915_WRITE(SOUTH_CHICKEN1, temp);
2609         }
2610 }
2611
2612 /* The FDI link training functions for ILK/Ibexpeak. */
2613 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2614 {
2615         struct drm_device *dev = crtc->dev;
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         int pipe = intel_crtc->pipe;
2619         u32 reg, temp, tries;
2620
2621         /* FDI needs bits from pipe first */
2622         assert_pipe_enabled(dev_priv, pipe);
2623
2624         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2625            for train result */
2626         reg = FDI_RX_IMR(pipe);
2627         temp = I915_READ(reg);
2628         temp &= ~FDI_RX_SYMBOL_LOCK;
2629         temp &= ~FDI_RX_BIT_LOCK;
2630         I915_WRITE(reg, temp);
2631         I915_READ(reg);
2632         udelay(150);
2633
2634         /* enable CPU FDI TX and PCH FDI RX */
2635         reg = FDI_TX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2638         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2639         temp &= ~FDI_LINK_TRAIN_NONE;
2640         temp |= FDI_LINK_TRAIN_PATTERN_1;
2641         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE;
2646         temp |= FDI_LINK_TRAIN_PATTERN_1;
2647         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         /* Ironlake workaround, enable clock pointer after FDI enable*/
2653         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2654         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2655                    FDI_RX_PHASE_SYNC_POINTER_EN);
2656
2657         reg = FDI_RX_IIR(pipe);
2658         for (tries = 0; tries < 5; tries++) {
2659                 temp = I915_READ(reg);
2660                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662                 if ((temp & FDI_RX_BIT_LOCK)) {
2663                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2664                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665                         break;
2666                 }
2667         }
2668         if (tries == 5)
2669                 DRM_ERROR("FDI train 1 fail!\n");
2670
2671         /* Train 2 */
2672         reg = FDI_TX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_NONE;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2;
2676         I915_WRITE(reg, temp);
2677
2678         reg = FDI_RX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_NONE;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2;
2682         I915_WRITE(reg, temp);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         reg = FDI_RX_IIR(pipe);
2688         for (tries = 0; tries < 5; tries++) {
2689                 temp = I915_READ(reg);
2690                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692                 if (temp & FDI_RX_SYMBOL_LOCK) {
2693                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2694                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2695                         break;
2696                 }
2697         }
2698         if (tries == 5)
2699                 DRM_ERROR("FDI train 2 fail!\n");
2700
2701         DRM_DEBUG_KMS("FDI train done\n");
2702
2703 }
2704
2705 static const int snb_b_fdi_train_param[] = {
2706         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2707         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2708         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2709         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2710 };
2711
2712 /* The FDI link training functions for SNB/Cougarpoint. */
2713 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2714 {
2715         struct drm_device *dev = crtc->dev;
2716         struct drm_i915_private *dev_priv = dev->dev_private;
2717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718         int pipe = intel_crtc->pipe;
2719         u32 reg, temp, i, retry;
2720
2721         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2722            for train result */
2723         reg = FDI_RX_IMR(pipe);
2724         temp = I915_READ(reg);
2725         temp &= ~FDI_RX_SYMBOL_LOCK;
2726         temp &= ~FDI_RX_BIT_LOCK;
2727         I915_WRITE(reg, temp);
2728
2729         POSTING_READ(reg);
2730         udelay(150);
2731
2732         /* enable CPU FDI TX and PCH FDI RX */
2733         reg = FDI_TX_CTL(pipe);
2734         temp = I915_READ(reg);
2735         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2736         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2737         temp &= ~FDI_LINK_TRAIN_NONE;
2738         temp |= FDI_LINK_TRAIN_PATTERN_1;
2739         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2740         /* SNB-B */
2741         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2742         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2743
2744         I915_WRITE(FDI_RX_MISC(pipe),
2745                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2746
2747         reg = FDI_RX_CTL(pipe);
2748         temp = I915_READ(reg);
2749         if (HAS_PCH_CPT(dev)) {
2750                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2751                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2752         } else {
2753                 temp &= ~FDI_LINK_TRAIN_NONE;
2754                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2755         }
2756         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2757
2758         POSTING_READ(reg);
2759         udelay(150);
2760
2761         for (i = 0; i < 4; i++) {
2762                 reg = FDI_TX_CTL(pipe);
2763                 temp = I915_READ(reg);
2764                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2765                 temp |= snb_b_fdi_train_param[i];
2766                 I915_WRITE(reg, temp);
2767
2768                 POSTING_READ(reg);
2769                 udelay(500);
2770
2771                 for (retry = 0; retry < 5; retry++) {
2772                         reg = FDI_RX_IIR(pipe);
2773                         temp = I915_READ(reg);
2774                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2775                         if (temp & FDI_RX_BIT_LOCK) {
2776                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2777                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2778                                 break;
2779                         }
2780                         udelay(50);
2781                 }
2782                 if (retry < 5)
2783                         break;
2784         }
2785         if (i == 4)
2786                 DRM_ERROR("FDI train 1 fail!\n");
2787
2788         /* Train 2 */
2789         reg = FDI_TX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         temp &= ~FDI_LINK_TRAIN_NONE;
2792         temp |= FDI_LINK_TRAIN_PATTERN_2;
2793         if (IS_GEN6(dev)) {
2794                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795                 /* SNB-B */
2796                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2797         }
2798         I915_WRITE(reg, temp);
2799
2800         reg = FDI_RX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         if (HAS_PCH_CPT(dev)) {
2803                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2805         } else {
2806                 temp &= ~FDI_LINK_TRAIN_NONE;
2807                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2808         }
2809         I915_WRITE(reg, temp);
2810
2811         POSTING_READ(reg);
2812         udelay(150);
2813
2814         for (i = 0; i < 4; i++) {
2815                 reg = FDI_TX_CTL(pipe);
2816                 temp = I915_READ(reg);
2817                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2818                 temp |= snb_b_fdi_train_param[i];
2819                 I915_WRITE(reg, temp);
2820
2821                 POSTING_READ(reg);
2822                 udelay(500);
2823
2824                 for (retry = 0; retry < 5; retry++) {
2825                         reg = FDI_RX_IIR(pipe);
2826                         temp = I915_READ(reg);
2827                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2828                         if (temp & FDI_RX_SYMBOL_LOCK) {
2829                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2830                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2831                                 break;
2832                         }
2833                         udelay(50);
2834                 }
2835                 if (retry < 5)
2836                         break;
2837         }
2838         if (i == 4)
2839                 DRM_ERROR("FDI train 2 fail!\n");
2840
2841         DRM_DEBUG_KMS("FDI train done.\n");
2842 }
2843
2844 /* Manual link training for Ivy Bridge A0 parts */
2845 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp, i, j;
2852
2853         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2854            for train result */
2855         reg = FDI_RX_IMR(pipe);
2856         temp = I915_READ(reg);
2857         temp &= ~FDI_RX_SYMBOL_LOCK;
2858         temp &= ~FDI_RX_BIT_LOCK;
2859         I915_WRITE(reg, temp);
2860
2861         POSTING_READ(reg);
2862         udelay(150);
2863
2864         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2865                       I915_READ(FDI_RX_IIR(pipe)));
2866
2867         /* Try each vswing and preemphasis setting twice before moving on */
2868         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2869                 /* disable first in case we need to retry */
2870                 reg = FDI_TX_CTL(pipe);
2871                 temp = I915_READ(reg);
2872                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2873                 temp &= ~FDI_TX_ENABLE;
2874                 I915_WRITE(reg, temp);
2875
2876                 reg = FDI_RX_CTL(pipe);
2877                 temp = I915_READ(reg);
2878                 temp &= ~FDI_LINK_TRAIN_AUTO;
2879                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2880                 temp &= ~FDI_RX_ENABLE;
2881                 I915_WRITE(reg, temp);
2882
2883                 /* enable CPU FDI TX and PCH FDI RX */
2884                 reg = FDI_TX_CTL(pipe);
2885                 temp = I915_READ(reg);
2886                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2887                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2888                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2889                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2890                 temp |= snb_b_fdi_train_param[j/2];
2891                 temp |= FDI_COMPOSITE_SYNC;
2892                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2893
2894                 I915_WRITE(FDI_RX_MISC(pipe),
2895                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2896
2897                 reg = FDI_RX_CTL(pipe);
2898                 temp = I915_READ(reg);
2899                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2900                 temp |= FDI_COMPOSITE_SYNC;
2901                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2902
2903                 POSTING_READ(reg);
2904                 udelay(1); /* should be 0.5us */
2905
2906                 for (i = 0; i < 4; i++) {
2907                         reg = FDI_RX_IIR(pipe);
2908                         temp = I915_READ(reg);
2909                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2910
2911                         if (temp & FDI_RX_BIT_LOCK ||
2912                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2913                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2914                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2915                                               i);
2916                                 break;
2917                         }
2918                         udelay(1); /* should be 0.5us */
2919                 }
2920                 if (i == 4) {
2921                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2922                         continue;
2923                 }
2924
2925                 /* Train 2 */
2926                 reg = FDI_TX_CTL(pipe);
2927                 temp = I915_READ(reg);
2928                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2929                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2930                 I915_WRITE(reg, temp);
2931
2932                 reg = FDI_RX_CTL(pipe);
2933                 temp = I915_READ(reg);
2934                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2935                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2936                 I915_WRITE(reg, temp);
2937
2938                 POSTING_READ(reg);
2939                 udelay(2); /* should be 1.5us */
2940
2941                 for (i = 0; i < 4; i++) {
2942                         reg = FDI_RX_IIR(pipe);
2943                         temp = I915_READ(reg);
2944                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2945
2946                         if (temp & FDI_RX_SYMBOL_LOCK ||
2947                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2948                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2949                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2950                                               i);
2951                                 goto train_done;
2952                         }
2953                         udelay(2); /* should be 1.5us */
2954                 }
2955                 if (i == 4)
2956                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2957         }
2958
2959 train_done:
2960         DRM_DEBUG_KMS("FDI train done.\n");
2961 }
2962
2963 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2964 {
2965         struct drm_device *dev = intel_crtc->base.dev;
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967         int pipe = intel_crtc->pipe;
2968         u32 reg, temp;
2969
2970
2971         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2972         reg = FDI_RX_CTL(pipe);
2973         temp = I915_READ(reg);
2974         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2975         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2976         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2977         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2978
2979         POSTING_READ(reg);
2980         udelay(200);
2981
2982         /* Switch from Rawclk to PCDclk */
2983         temp = I915_READ(reg);
2984         I915_WRITE(reg, temp | FDI_PCDCLK);
2985
2986         POSTING_READ(reg);
2987         udelay(200);
2988
2989         /* Enable CPU FDI TX PLL, always on for Ironlake */
2990         reg = FDI_TX_CTL(pipe);
2991         temp = I915_READ(reg);
2992         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2993                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2994
2995                 POSTING_READ(reg);
2996                 udelay(100);
2997         }
2998 }
2999
3000 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3001 {
3002         struct drm_device *dev = intel_crtc->base.dev;
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         int pipe = intel_crtc->pipe;
3005         u32 reg, temp;
3006
3007         /* Switch from PCDclk to Rawclk */
3008         reg = FDI_RX_CTL(pipe);
3009         temp = I915_READ(reg);
3010         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3011
3012         /* Disable CPU FDI TX PLL */
3013         reg = FDI_TX_CTL(pipe);
3014         temp = I915_READ(reg);
3015         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3016
3017         POSTING_READ(reg);
3018         udelay(100);
3019
3020         reg = FDI_RX_CTL(pipe);
3021         temp = I915_READ(reg);
3022         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3023
3024         /* Wait for the clocks to turn off. */
3025         POSTING_READ(reg);
3026         udelay(100);
3027 }
3028
3029 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3030 {
3031         struct drm_device *dev = crtc->dev;
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034         int pipe = intel_crtc->pipe;
3035         u32 reg, temp;
3036
3037         /* disable CPU FDI tx and PCH FDI rx */
3038         reg = FDI_TX_CTL(pipe);
3039         temp = I915_READ(reg);
3040         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3041         POSTING_READ(reg);
3042
3043         reg = FDI_RX_CTL(pipe);
3044         temp = I915_READ(reg);
3045         temp &= ~(0x7 << 16);
3046         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3047         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3048
3049         POSTING_READ(reg);
3050         udelay(100);
3051
3052         /* Ironlake workaround, disable clock pointer after downing FDI */
3053         if (HAS_PCH_IBX(dev)) {
3054                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3055         }
3056
3057         /* still set train pattern 1 */
3058         reg = FDI_TX_CTL(pipe);
3059         temp = I915_READ(reg);
3060         temp &= ~FDI_LINK_TRAIN_NONE;
3061         temp |= FDI_LINK_TRAIN_PATTERN_1;
3062         I915_WRITE(reg, temp);
3063
3064         reg = FDI_RX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         if (HAS_PCH_CPT(dev)) {
3067                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3068                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3069         } else {
3070                 temp &= ~FDI_LINK_TRAIN_NONE;
3071                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3072         }
3073         /* BPC in FDI rx is consistent with that in PIPECONF */
3074         temp &= ~(0x07 << 16);
3075         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3076         I915_WRITE(reg, temp);
3077
3078         POSTING_READ(reg);
3079         udelay(100);
3080 }
3081
3082 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3083 {
3084         struct intel_crtc *crtc;
3085
3086         /* Note that we don't need to be called with mode_config.lock here
3087          * as our list of CRTC objects is static for the lifetime of the
3088          * device and so cannot disappear as we iterate. Similarly, we can
3089          * happily treat the predicates as racy, atomic checks as userspace
3090          * cannot claim and pin a new fb without at least acquring the
3091          * struct_mutex and so serialising with us.
3092          */
3093         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3094                 if (atomic_read(&crtc->unpin_work_count) == 0)
3095                         continue;
3096
3097                 if (crtc->unpin_work)
3098                         intel_wait_for_vblank(dev, crtc->pipe);
3099
3100                 return true;
3101         }
3102
3103         return false;
3104 }
3105
3106 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3107 {
3108         struct drm_device *dev = crtc->dev;
3109         struct drm_i915_private *dev_priv = dev->dev_private;
3110
3111         if (crtc->primary->fb == NULL)
3112                 return;
3113
3114         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3115
3116         wait_event(dev_priv->pending_flip_queue,
3117                    !intel_crtc_has_pending_flip(crtc));
3118
3119         mutex_lock(&dev->struct_mutex);
3120         intel_finish_fb(crtc->primary->fb);
3121         mutex_unlock(&dev->struct_mutex);
3122 }
3123
3124 /* Program iCLKIP clock to the desired frequency */
3125 static void lpt_program_iclkip(struct drm_crtc *crtc)
3126 {
3127         struct drm_device *dev = crtc->dev;
3128         struct drm_i915_private *dev_priv = dev->dev_private;
3129         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3130         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3131         u32 temp;
3132
3133         mutex_lock(&dev_priv->dpio_lock);
3134
3135         /* It is necessary to ungate the pixclk gate prior to programming
3136          * the divisors, and gate it back when it is done.
3137          */
3138         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3139
3140         /* Disable SSCCTL */
3141         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3142                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3143                                 SBI_SSCCTL_DISABLE,
3144                         SBI_ICLK);
3145
3146         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3147         if (clock == 20000) {
3148                 auxdiv = 1;
3149                 divsel = 0x41;
3150                 phaseinc = 0x20;
3151         } else {
3152                 /* The iCLK virtual clock root frequency is in MHz,
3153                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3154                  * divisors, it is necessary to divide one by another, so we
3155                  * convert the virtual clock precision to KHz here for higher
3156                  * precision.
3157                  */
3158                 u32 iclk_virtual_root_freq = 172800 * 1000;
3159                 u32 iclk_pi_range = 64;
3160                 u32 desired_divisor, msb_divisor_value, pi_value;
3161
3162                 desired_divisor = (iclk_virtual_root_freq / clock);
3163                 msb_divisor_value = desired_divisor / iclk_pi_range;
3164                 pi_value = desired_divisor % iclk_pi_range;
3165
3166                 auxdiv = 0;
3167                 divsel = msb_divisor_value - 2;
3168                 phaseinc = pi_value;
3169         }
3170
3171         /* This should not happen with any sane values */
3172         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3173                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3174         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3175                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3176
3177         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3178                         clock,
3179                         auxdiv,
3180                         divsel,
3181                         phasedir,
3182                         phaseinc);
3183
3184         /* Program SSCDIVINTPHASE6 */
3185         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3186         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3187         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3188         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3189         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3190         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3191         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3192         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3193
3194         /* Program SSCAUXDIV */
3195         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3196         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3197         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3198         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3199
3200         /* Enable modulator and associated divider */
3201         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3202         temp &= ~SBI_SSCCTL_DISABLE;
3203         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3204
3205         /* Wait for initialization time */
3206         udelay(24);
3207
3208         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3209
3210         mutex_unlock(&dev_priv->dpio_lock);
3211 }
3212
3213 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3214                                                 enum pipe pch_transcoder)
3215 {
3216         struct drm_device *dev = crtc->base.dev;
3217         struct drm_i915_private *dev_priv = dev->dev_private;
3218         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3219
3220         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3221                    I915_READ(HTOTAL(cpu_transcoder)));
3222         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3223                    I915_READ(HBLANK(cpu_transcoder)));
3224         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3225                    I915_READ(HSYNC(cpu_transcoder)));
3226
3227         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3228                    I915_READ(VTOTAL(cpu_transcoder)));
3229         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3230                    I915_READ(VBLANK(cpu_transcoder)));
3231         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3232                    I915_READ(VSYNC(cpu_transcoder)));
3233         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3234                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3235 }
3236
3237 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         uint32_t temp;
3241
3242         temp = I915_READ(SOUTH_CHICKEN1);
3243         if (temp & FDI_BC_BIFURCATION_SELECT)
3244                 return;
3245
3246         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3247         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3248
3249         temp |= FDI_BC_BIFURCATION_SELECT;
3250         DRM_DEBUG_KMS("enabling fdi C rx\n");
3251         I915_WRITE(SOUTH_CHICKEN1, temp);
3252         POSTING_READ(SOUTH_CHICKEN1);
3253 }
3254
3255 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3256 {
3257         struct drm_device *dev = intel_crtc->base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259
3260         switch (intel_crtc->pipe) {
3261         case PIPE_A:
3262                 break;
3263         case PIPE_B:
3264                 if (intel_crtc->config.fdi_lanes > 2)
3265                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3266                 else
3267                         cpt_enable_fdi_bc_bifurcation(dev);
3268
3269                 break;
3270         case PIPE_C:
3271                 cpt_enable_fdi_bc_bifurcation(dev);
3272
3273                 break;
3274         default:
3275                 BUG();
3276         }
3277 }
3278
3279 /*
3280  * Enable PCH resources required for PCH ports:
3281  *   - PCH PLLs
3282  *   - FDI training & RX/TX
3283  *   - update transcoder timings
3284  *   - DP transcoding bits
3285  *   - transcoder
3286  */
3287 static void ironlake_pch_enable(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         int pipe = intel_crtc->pipe;
3293         u32 reg, temp;
3294
3295         assert_pch_transcoder_disabled(dev_priv, pipe);
3296
3297         if (IS_IVYBRIDGE(dev))
3298                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3299
3300         /* Write the TU size bits before fdi link training, so that error
3301          * detection works. */
3302         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3303                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3304
3305         /* For PCH output, training FDI link */
3306         dev_priv->display.fdi_link_train(crtc);
3307
3308         /* We need to program the right clock selection before writing the pixel
3309          * mutliplier into the DPLL. */
3310         if (HAS_PCH_CPT(dev)) {
3311                 u32 sel;
3312
3313                 temp = I915_READ(PCH_DPLL_SEL);
3314                 temp |= TRANS_DPLL_ENABLE(pipe);
3315                 sel = TRANS_DPLLB_SEL(pipe);
3316                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3317                         temp |= sel;
3318                 else
3319                         temp &= ~sel;
3320                 I915_WRITE(PCH_DPLL_SEL, temp);
3321         }
3322
3323         /* XXX: pch pll's can be enabled any time before we enable the PCH
3324          * transcoder, and we actually should do this to not upset any PCH
3325          * transcoder that already use the clock when we share it.
3326          *
3327          * Note that enable_shared_dpll tries to do the right thing, but
3328          * get_shared_dpll unconditionally resets the pll - we need that to have
3329          * the right LVDS enable sequence. */
3330         ironlake_enable_shared_dpll(intel_crtc);
3331
3332         /* set transcoder timing, panel must allow it */
3333         assert_panel_unlocked(dev_priv, pipe);
3334         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3335
3336         intel_fdi_normal_train(crtc);
3337
3338         /* For PCH DP, enable TRANS_DP_CTL */
3339         if (HAS_PCH_CPT(dev) &&
3340             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3341              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3342                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3343                 reg = TRANS_DP_CTL(pipe);
3344                 temp = I915_READ(reg);
3345                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3346                           TRANS_DP_SYNC_MASK |
3347                           TRANS_DP_BPC_MASK);
3348                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3349                          TRANS_DP_ENH_FRAMING);
3350                 temp |= bpc << 9; /* same format but at 11:9 */
3351
3352                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3353                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3354                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3355                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3356
3357                 switch (intel_trans_dp_port_sel(crtc)) {
3358                 case PCH_DP_B:
3359                         temp |= TRANS_DP_PORT_SEL_B;
3360                         break;
3361                 case PCH_DP_C:
3362                         temp |= TRANS_DP_PORT_SEL_C;
3363                         break;
3364                 case PCH_DP_D:
3365                         temp |= TRANS_DP_PORT_SEL_D;
3366                         break;
3367                 default:
3368                         BUG();
3369                 }
3370
3371                 I915_WRITE(reg, temp);
3372         }
3373
3374         ironlake_enable_pch_transcoder(dev_priv, pipe);
3375 }
3376
3377 static void lpt_pch_enable(struct drm_crtc *crtc)
3378 {
3379         struct drm_device *dev = crtc->dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3383
3384         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3385
3386         lpt_program_iclkip(crtc);
3387
3388         /* Set transcoder timing. */
3389         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3390
3391         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3392 }
3393
3394 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3395 {
3396         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3397
3398         if (pll == NULL)
3399                 return;
3400
3401         if (pll->refcount == 0) {
3402                 WARN(1, "bad %s refcount\n", pll->name);
3403                 return;
3404         }
3405
3406         if (--pll->refcount == 0) {
3407                 WARN_ON(pll->on);
3408                 WARN_ON(pll->active);
3409         }
3410
3411         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3412 }
3413
3414 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3415 {
3416         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3417         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3418         enum intel_dpll_id i;
3419
3420         if (pll) {
3421                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3422                               crtc->base.base.id, pll->name);
3423                 intel_put_shared_dpll(crtc);
3424         }
3425
3426         if (HAS_PCH_IBX(dev_priv->dev)) {
3427                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3428                 i = (enum intel_dpll_id) crtc->pipe;
3429                 pll = &dev_priv->shared_dplls[i];
3430
3431                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3432                               crtc->base.base.id, pll->name);
3433
3434                 goto found;
3435         }
3436
3437         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3438                 pll = &dev_priv->shared_dplls[i];
3439
3440                 /* Only want to check enabled timings first */
3441                 if (pll->refcount == 0)
3442                         continue;
3443
3444                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3445                            sizeof(pll->hw_state)) == 0) {
3446                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3447                                       crtc->base.base.id,
3448                                       pll->name, pll->refcount, pll->active);
3449
3450                         goto found;
3451                 }
3452         }
3453
3454         /* Ok no matching timings, maybe there's a free one? */
3455         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3456                 pll = &dev_priv->shared_dplls[i];
3457                 if (pll->refcount == 0) {
3458                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3459                                       crtc->base.base.id, pll->name);
3460                         goto found;
3461                 }
3462         }
3463
3464         return NULL;
3465
3466 found:
3467         crtc->config.shared_dpll = i;
3468         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3469                          pipe_name(crtc->pipe));
3470
3471         if (pll->active == 0) {
3472                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3473                        sizeof(pll->hw_state));
3474
3475                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3476                 WARN_ON(pll->on);
3477                 assert_shared_dpll_disabled(dev_priv, pll);
3478
3479                 pll->mode_set(dev_priv, pll);
3480         }
3481         pll->refcount++;
3482
3483         return pll;
3484 }
3485
3486 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3487 {
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         int dslreg = PIPEDSL(pipe);
3490         u32 temp;
3491
3492         temp = I915_READ(dslreg);
3493         udelay(500);
3494         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3495                 if (wait_for(I915_READ(dslreg) != temp, 5))
3496                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3497         }
3498 }
3499
3500 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3501 {
3502         struct drm_device *dev = crtc->base.dev;
3503         struct drm_i915_private *dev_priv = dev->dev_private;
3504         int pipe = crtc->pipe;
3505
3506         if (crtc->config.pch_pfit.enabled) {
3507                 /* Force use of hard-coded filter coefficients
3508                  * as some pre-programmed values are broken,
3509                  * e.g. x201.
3510                  */
3511                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3512                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3513                                                  PF_PIPE_SEL_IVB(pipe));
3514                 else
3515                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3516                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3517                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3518         }
3519 }
3520
3521 static void intel_enable_planes(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3525         struct drm_plane *plane;
3526         struct intel_plane *intel_plane;
3527
3528         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3529                 intel_plane = to_intel_plane(plane);
3530                 if (intel_plane->pipe == pipe)
3531                         intel_plane_restore(&intel_plane->base);
3532         }
3533 }
3534
3535 static void intel_disable_planes(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3539         struct drm_plane *plane;
3540         struct intel_plane *intel_plane;
3541
3542         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3543                 intel_plane = to_intel_plane(plane);
3544                 if (intel_plane->pipe == pipe)
3545                         intel_plane_disable(&intel_plane->base);
3546         }
3547 }
3548
3549 void hsw_enable_ips(struct intel_crtc *crtc)
3550 {
3551         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3552
3553         if (!crtc->config.ips_enabled)
3554                 return;
3555
3556         /* We can only enable IPS after we enable a plane and wait for a vblank.
3557          * We guarantee that the plane is enabled by calling intel_enable_ips
3558          * only after intel_enable_plane. And intel_enable_plane already waits
3559          * for a vblank, so all we need to do here is to enable the IPS bit. */
3560         assert_plane_enabled(dev_priv, crtc->plane);
3561         if (IS_BROADWELL(crtc->base.dev)) {
3562                 mutex_lock(&dev_priv->rps.hw_lock);
3563                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3564                 mutex_unlock(&dev_priv->rps.hw_lock);
3565                 /* Quoting Art Runyan: "its not safe to expect any particular
3566                  * value in IPS_CTL bit 31 after enabling IPS through the
3567                  * mailbox." Moreover, the mailbox may return a bogus state,
3568                  * so we need to just enable it and continue on.
3569                  */
3570         } else {
3571                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3572                 /* The bit only becomes 1 in the next vblank, so this wait here
3573                  * is essentially intel_wait_for_vblank. If we don't have this
3574                  * and don't wait for vblanks until the end of crtc_enable, then
3575                  * the HW state readout code will complain that the expected
3576                  * IPS_CTL value is not the one we read. */
3577                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3578                         DRM_ERROR("Timed out waiting for IPS enable\n");
3579         }
3580 }
3581
3582 void hsw_disable_ips(struct intel_crtc *crtc)
3583 {
3584         struct drm_device *dev = crtc->base.dev;
3585         struct drm_i915_private *dev_priv = dev->dev_private;
3586
3587         if (!crtc->config.ips_enabled)
3588                 return;
3589
3590         assert_plane_enabled(dev_priv, crtc->plane);
3591         if (IS_BROADWELL(dev)) {
3592                 mutex_lock(&dev_priv->rps.hw_lock);
3593                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3594                 mutex_unlock(&dev_priv->rps.hw_lock);
3595                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3596                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3597                         DRM_ERROR("Timed out waiting for IPS disable\n");
3598         } else {
3599                 I915_WRITE(IPS_CTL, 0);
3600                 POSTING_READ(IPS_CTL);
3601         }
3602
3603         /* We need to wait for a vblank before we can disable the plane. */
3604         intel_wait_for_vblank(dev, crtc->pipe);
3605 }
3606
3607 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3608 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3609 {
3610         struct drm_device *dev = crtc->dev;
3611         struct drm_i915_private *dev_priv = dev->dev_private;
3612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3613         enum pipe pipe = intel_crtc->pipe;
3614         int palreg = PALETTE(pipe);
3615         int i;
3616         bool reenable_ips = false;
3617
3618         /* The clocks have to be on to load the palette. */
3619         if (!crtc->enabled || !intel_crtc->active)
3620                 return;
3621
3622         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3623                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3624                         assert_dsi_pll_enabled(dev_priv);
3625                 else
3626                         assert_pll_enabled(dev_priv, pipe);
3627         }
3628
3629         /* use legacy palette for Ironlake */
3630         if (HAS_PCH_SPLIT(dev))
3631                 palreg = LGC_PALETTE(pipe);
3632
3633         /* Workaround : Do not read or write the pipe palette/gamma data while
3634          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3635          */
3636         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3637             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3638              GAMMA_MODE_MODE_SPLIT)) {
3639                 hsw_disable_ips(intel_crtc);
3640                 reenable_ips = true;
3641         }
3642
3643         for (i = 0; i < 256; i++) {
3644                 I915_WRITE(palreg + 4 * i,
3645                            (intel_crtc->lut_r[i] << 16) |
3646                            (intel_crtc->lut_g[i] << 8) |
3647                            intel_crtc->lut_b[i]);
3648         }
3649
3650         if (reenable_ips)
3651                 hsw_enable_ips(intel_crtc);
3652 }
3653
3654 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3655 {
3656         if (!enable && intel_crtc->overlay) {
3657                 struct drm_device *dev = intel_crtc->base.dev;
3658                 struct drm_i915_private *dev_priv = dev->dev_private;
3659
3660                 mutex_lock(&dev->struct_mutex);
3661                 dev_priv->mm.interruptible = false;
3662                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3663                 dev_priv->mm.interruptible = true;
3664                 mutex_unlock(&dev->struct_mutex);
3665         }
3666
3667         /* Let userspace switch the overlay on again. In most cases userspace
3668          * has to recompute where to put it anyway.
3669          */
3670 }
3671
3672 /**
3673  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3674  * cursor plane briefly if not already running after enabling the display
3675  * plane.
3676  * This workaround avoids occasional blank screens when self refresh is
3677  * enabled.
3678  */
3679 static void
3680 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3681 {
3682         u32 cntl = I915_READ(CURCNTR(pipe));
3683
3684         if ((cntl & CURSOR_MODE) == 0) {
3685                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3686
3687                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3688                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3689                 intel_wait_for_vblank(dev_priv->dev, pipe);
3690                 I915_WRITE(CURCNTR(pipe), cntl);
3691                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3692                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3693         }
3694 }
3695
3696 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3697 {
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         int pipe = intel_crtc->pipe;
3702         int plane = intel_crtc->plane;
3703
3704         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3705         intel_enable_planes(crtc);
3706         /* The fixup needs to happen before cursor is enabled */
3707         if (IS_G4X(dev))
3708                 g4x_fixup_plane(dev_priv, pipe);
3709         intel_crtc_update_cursor(crtc, true);
3710         intel_crtc_dpms_overlay(intel_crtc, true);
3711
3712         hsw_enable_ips(intel_crtc);
3713
3714         mutex_lock(&dev->struct_mutex);
3715         intel_update_fbc(dev);
3716         mutex_unlock(&dev->struct_mutex);
3717 }
3718
3719 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3720 {
3721         struct drm_device *dev = crtc->dev;
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3724         int pipe = intel_crtc->pipe;
3725         int plane = intel_crtc->plane;
3726
3727         intel_crtc_wait_for_pending_flips(crtc);
3728         drm_vblank_off(dev, pipe);
3729
3730         if (dev_priv->fbc.plane == plane)
3731                 intel_disable_fbc(dev);
3732
3733         hsw_disable_ips(intel_crtc);
3734
3735         intel_crtc_dpms_overlay(intel_crtc, false);
3736         intel_crtc_update_cursor(crtc, false);
3737         intel_disable_planes(crtc);
3738         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3739 }
3740
3741 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3742 {
3743         struct drm_device *dev = crtc->dev;
3744         struct drm_i915_private *dev_priv = dev->dev_private;
3745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746         struct intel_encoder *encoder;
3747         int pipe = intel_crtc->pipe;
3748
3749         WARN_ON(!crtc->enabled);
3750
3751         if (intel_crtc->active)
3752                 return;
3753
3754         intel_crtc->active = true;
3755
3756         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3757         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3758
3759         for_each_encoder_on_crtc(dev, crtc, encoder)
3760                 if (encoder->pre_enable)
3761                         encoder->pre_enable(encoder);
3762
3763         if (intel_crtc->config.has_pch_encoder) {
3764                 /* Note: FDI PLL enabling _must_ be done before we enable the
3765                  * cpu pipes, hence this is separate from all the other fdi/pch
3766                  * enabling. */
3767                 ironlake_fdi_pll_enable(intel_crtc);
3768         } else {
3769                 assert_fdi_tx_disabled(dev_priv, pipe);
3770                 assert_fdi_rx_disabled(dev_priv, pipe);
3771         }
3772
3773         ironlake_pfit_enable(intel_crtc);
3774
3775         /*
3776          * On ILK+ LUT must be loaded before the pipe is running but with
3777          * clocks enabled
3778          */
3779         intel_crtc_load_lut(crtc);
3780
3781         intel_update_watermarks(crtc);
3782         intel_enable_pipe(intel_crtc);
3783
3784         if (intel_crtc->config.has_pch_encoder)
3785                 ironlake_pch_enable(crtc);
3786
3787         for_each_encoder_on_crtc(dev, crtc, encoder)
3788                 encoder->enable(encoder);
3789
3790         if (HAS_PCH_CPT(dev))
3791                 cpt_verify_modeset(dev, intel_crtc->pipe);
3792
3793         intel_crtc_enable_planes(crtc);
3794
3795         /*
3796          * There seems to be a race in PCH platform hw (at least on some
3797          * outputs) where an enabled pipe still completes any pageflip right
3798          * away (as if the pipe is off) instead of waiting for vblank. As soon
3799          * as the first vblank happend, everything works as expected. Hence just
3800          * wait for one vblank before returning to avoid strange things
3801          * happening.
3802          */
3803         intel_wait_for_vblank(dev, intel_crtc->pipe);
3804 }
3805
3806 /* IPS only exists on ULT machines and is tied to pipe A. */
3807 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3808 {
3809         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3810 }
3811
3812 /*
3813  * This implements the workaround described in the "notes" section of the mode
3814  * set sequence documentation. When going from no pipes or single pipe to
3815  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3816  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3817  */
3818 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->base.dev;
3821         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3822
3823         /* We want to get the other_active_crtc only if there's only 1 other
3824          * active crtc. */
3825         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3826                 if (!crtc_it->active || crtc_it == crtc)
3827                         continue;
3828
3829                 if (other_active_crtc)
3830                         return;
3831
3832                 other_active_crtc = crtc_it;
3833         }
3834         if (!other_active_crtc)
3835                 return;
3836
3837         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3838         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3839 }
3840
3841 static void haswell_crtc_enable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         struct intel_encoder *encoder;
3847         int pipe = intel_crtc->pipe;
3848
3849         WARN_ON(!crtc->enabled);
3850
3851         if (intel_crtc->active)
3852                 return;
3853
3854         intel_crtc->active = true;
3855
3856         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3857         if (intel_crtc->config.has_pch_encoder)
3858                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3859
3860         if (intel_crtc->config.has_pch_encoder)
3861                 dev_priv->display.fdi_link_train(crtc);
3862
3863         for_each_encoder_on_crtc(dev, crtc, encoder)
3864                 if (encoder->pre_enable)
3865                         encoder->pre_enable(encoder);
3866
3867         intel_ddi_enable_pipe_clock(intel_crtc);
3868
3869         ironlake_pfit_enable(intel_crtc);
3870
3871         /*
3872          * On ILK+ LUT must be loaded before the pipe is running but with
3873          * clocks enabled
3874          */
3875         intel_crtc_load_lut(crtc);
3876
3877         intel_ddi_set_pipe_settings(crtc);
3878         intel_ddi_enable_transcoder_func(crtc);
3879
3880         intel_update_watermarks(crtc);
3881         intel_enable_pipe(intel_crtc);
3882
3883         if (intel_crtc->config.has_pch_encoder)
3884                 lpt_pch_enable(crtc);
3885
3886         for_each_encoder_on_crtc(dev, crtc, encoder) {
3887                 encoder->enable(encoder);
3888                 intel_opregion_notify_encoder(encoder, true);
3889         }
3890
3891         /* If we change the relative order between pipe/planes enabling, we need
3892          * to change the workaround. */
3893         haswell_mode_set_planes_workaround(intel_crtc);
3894         intel_crtc_enable_planes(crtc);
3895 }
3896
3897 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3898 {
3899         struct drm_device *dev = crtc->base.dev;
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         int pipe = crtc->pipe;
3902
3903         /* To avoid upsetting the power well on haswell only disable the pfit if
3904          * it's in use. The hw state code will make sure we get this right. */
3905         if (crtc->config.pch_pfit.enabled) {
3906                 I915_WRITE(PF_CTL(pipe), 0);
3907                 I915_WRITE(PF_WIN_POS(pipe), 0);
3908                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3909         }
3910 }
3911
3912 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         struct intel_encoder *encoder;
3918         int pipe = intel_crtc->pipe;
3919         u32 reg, temp;
3920
3921         if (!intel_crtc->active)
3922                 return;
3923
3924         intel_crtc_disable_planes(crtc);
3925
3926         for_each_encoder_on_crtc(dev, crtc, encoder)
3927                 encoder->disable(encoder);
3928
3929         if (intel_crtc->config.has_pch_encoder)
3930                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3931
3932         intel_disable_pipe(dev_priv, pipe);
3933
3934         ironlake_pfit_disable(intel_crtc);
3935
3936         for_each_encoder_on_crtc(dev, crtc, encoder)
3937                 if (encoder->post_disable)
3938                         encoder->post_disable(encoder);
3939
3940         if (intel_crtc->config.has_pch_encoder) {
3941                 ironlake_fdi_disable(crtc);
3942
3943                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3944                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3945
3946                 if (HAS_PCH_CPT(dev)) {
3947                         /* disable TRANS_DP_CTL */
3948                         reg = TRANS_DP_CTL(pipe);
3949                         temp = I915_READ(reg);
3950                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3951                                   TRANS_DP_PORT_SEL_MASK);
3952                         temp |= TRANS_DP_PORT_SEL_NONE;
3953                         I915_WRITE(reg, temp);
3954
3955                         /* disable DPLL_SEL */
3956                         temp = I915_READ(PCH_DPLL_SEL);
3957                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3958                         I915_WRITE(PCH_DPLL_SEL, temp);
3959                 }
3960
3961                 /* disable PCH DPLL */
3962                 intel_disable_shared_dpll(intel_crtc);
3963
3964                 ironlake_fdi_pll_disable(intel_crtc);
3965         }
3966
3967         intel_crtc->active = false;
3968         intel_update_watermarks(crtc);
3969
3970         mutex_lock(&dev->struct_mutex);
3971         intel_update_fbc(dev);
3972         mutex_unlock(&dev->struct_mutex);
3973 }
3974
3975 static void haswell_crtc_disable(struct drm_crtc *crtc)
3976 {
3977         struct drm_device *dev = crtc->dev;
3978         struct drm_i915_private *dev_priv = dev->dev_private;
3979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3980         struct intel_encoder *encoder;
3981         int pipe = intel_crtc->pipe;
3982         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3983
3984         if (!intel_crtc->active)
3985                 return;
3986
3987         intel_crtc_disable_planes(crtc);
3988
3989         for_each_encoder_on_crtc(dev, crtc, encoder) {
3990                 intel_opregion_notify_encoder(encoder, false);
3991                 encoder->disable(encoder);
3992         }
3993
3994         if (intel_crtc->config.has_pch_encoder)
3995                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3996         intel_disable_pipe(dev_priv, pipe);
3997
3998         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3999
4000         ironlake_pfit_disable(intel_crtc);
4001
4002         intel_ddi_disable_pipe_clock(intel_crtc);
4003
4004         for_each_encoder_on_crtc(dev, crtc, encoder)
4005                 if (encoder->post_disable)
4006                         encoder->post_disable(encoder);
4007
4008         if (intel_crtc->config.has_pch_encoder) {
4009                 lpt_disable_pch_transcoder(dev_priv);
4010                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4011                 intel_ddi_fdi_disable(crtc);
4012         }
4013
4014         intel_crtc->active = false;
4015         intel_update_watermarks(crtc);
4016
4017         mutex_lock(&dev->struct_mutex);
4018         intel_update_fbc(dev);
4019         mutex_unlock(&dev->struct_mutex);
4020 }
4021
4022 static void ironlake_crtc_off(struct drm_crtc *crtc)
4023 {
4024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4025         intel_put_shared_dpll(intel_crtc);
4026 }
4027
4028 static void haswell_crtc_off(struct drm_crtc *crtc)
4029 {
4030         intel_ddi_put_crtc_pll(crtc);
4031 }
4032
4033 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         struct intel_crtc_config *pipe_config = &crtc->config;
4038
4039         if (!crtc->config.gmch_pfit.control)
4040                 return;
4041
4042         /*
4043          * The panel fitter should only be adjusted whilst the pipe is disabled,
4044          * according to register description and PRM.
4045          */
4046         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4047         assert_pipe_disabled(dev_priv, crtc->pipe);
4048
4049         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4050         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4051
4052         /* Border color in case we don't scale up to the full screen. Black by
4053          * default, change to something else for debugging. */
4054         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4055 }
4056
4057 #define for_each_power_domain(domain, mask)                             \
4058         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4059                 if ((1 << (domain)) & (mask))
4060
4061 enum intel_display_power_domain
4062 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4063 {
4064         struct drm_device *dev = intel_encoder->base.dev;
4065         struct intel_digital_port *intel_dig_port;
4066
4067         switch (intel_encoder->type) {
4068         case INTEL_OUTPUT_UNKNOWN:
4069                 /* Only DDI platforms should ever use this output type */
4070                 WARN_ON_ONCE(!HAS_DDI(dev));
4071         case INTEL_OUTPUT_DISPLAYPORT:
4072         case INTEL_OUTPUT_HDMI:
4073         case INTEL_OUTPUT_EDP:
4074                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4075                 switch (intel_dig_port->port) {
4076                 case PORT_A:
4077                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4078                 case PORT_B:
4079                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4080                 case PORT_C:
4081                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4082                 case PORT_D:
4083                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4084                 default:
4085                         WARN_ON_ONCE(1);
4086                         return POWER_DOMAIN_PORT_OTHER;
4087                 }
4088         case INTEL_OUTPUT_ANALOG:
4089                 return POWER_DOMAIN_PORT_CRT;
4090         case INTEL_OUTPUT_DSI:
4091                 return POWER_DOMAIN_PORT_DSI;
4092         default:
4093                 return POWER_DOMAIN_PORT_OTHER;
4094         }
4095 }
4096
4097 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4098 {
4099         struct drm_device *dev = crtc->dev;
4100         struct intel_encoder *intel_encoder;
4101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102         enum pipe pipe = intel_crtc->pipe;
4103         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4104         unsigned long mask;
4105         enum transcoder transcoder;
4106
4107         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4108
4109         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4110         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4111         if (pfit_enabled)
4112                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4113
4114         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4115                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4116
4117         return mask;
4118 }
4119
4120 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4121                                   bool enable)
4122 {
4123         if (dev_priv->power_domains.init_power_on == enable)
4124                 return;
4125
4126         if (enable)
4127                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4128         else
4129                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4130
4131         dev_priv->power_domains.init_power_on = enable;
4132 }
4133
4134 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4135 {
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4138         struct intel_crtc *crtc;
4139
4140         /*
4141          * First get all needed power domains, then put all unneeded, to avoid
4142          * any unnecessary toggling of the power wells.
4143          */
4144         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4145                 enum intel_display_power_domain domain;
4146
4147                 if (!crtc->base.enabled)
4148                         continue;
4149
4150                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4151
4152                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4153                         intel_display_power_get(dev_priv, domain);
4154         }
4155
4156         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4157                 enum intel_display_power_domain domain;
4158
4159                 for_each_power_domain(domain, crtc->enabled_power_domains)
4160                         intel_display_power_put(dev_priv, domain);
4161
4162                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4163         }
4164
4165         intel_display_set_init_power(dev_priv, false);
4166 }
4167
4168 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4169 {
4170         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4171
4172         /* Obtain SKU information */
4173         mutex_lock(&dev_priv->dpio_lock);
4174         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4175                 CCK_FUSE_HPLL_FREQ_MASK;
4176         mutex_unlock(&dev_priv->dpio_lock);
4177
4178         return vco_freq[hpll_freq];
4179 }
4180
4181 /* Adjust CDclk dividers to allow high res or save power if possible */
4182 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4183 {
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         u32 val, cmd;
4186
4187         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4188         dev_priv->vlv_cdclk_freq = cdclk;
4189
4190         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4191                 cmd = 2;
4192         else if (cdclk == 266)
4193                 cmd = 1;
4194         else
4195                 cmd = 0;
4196
4197         mutex_lock(&dev_priv->rps.hw_lock);
4198         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4199         val &= ~DSPFREQGUAR_MASK;
4200         val |= (cmd << DSPFREQGUAR_SHIFT);
4201         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4202         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4203                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4204                      50)) {
4205                 DRM_ERROR("timed out waiting for CDclk change\n");
4206         }
4207         mutex_unlock(&dev_priv->rps.hw_lock);
4208
4209         if (cdclk == 400) {
4210                 u32 divider, vco;
4211
4212                 vco = valleyview_get_vco(dev_priv);
4213                 divider = ((vco << 1) / cdclk) - 1;
4214
4215                 mutex_lock(&dev_priv->dpio_lock);
4216                 /* adjust cdclk divider */
4217                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4218                 val &= ~0xf;
4219                 val |= divider;
4220                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4221                 mutex_unlock(&dev_priv->dpio_lock);
4222         }
4223
4224         mutex_lock(&dev_priv->dpio_lock);
4225         /* adjust self-refresh exit latency value */
4226         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4227         val &= ~0x7f;
4228
4229         /*
4230          * For high bandwidth configs, we set a higher latency in the bunit
4231          * so that the core display fetch happens in time to avoid underruns.
4232          */
4233         if (cdclk == 400)
4234                 val |= 4500 / 250; /* 4.5 usec */
4235         else
4236                 val |= 3000 / 250; /* 3.0 usec */
4237         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4238         mutex_unlock(&dev_priv->dpio_lock);
4239
4240         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4241         intel_i2c_reset(dev);
4242 }
4243
4244 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4245 {
4246         int cur_cdclk, vco;
4247         int divider;
4248
4249         vco = valleyview_get_vco(dev_priv);
4250
4251         mutex_lock(&dev_priv->dpio_lock);
4252         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4253         mutex_unlock(&dev_priv->dpio_lock);
4254
4255         divider &= 0xf;
4256
4257         cur_cdclk = (vco << 1) / (divider + 1);
4258
4259         return cur_cdclk;
4260 }
4261
4262 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4263                                  int max_pixclk)
4264 {
4265         /*
4266          * Really only a few cases to deal with, as only 4 CDclks are supported:
4267          *   200MHz
4268          *   267MHz
4269          *   320MHz
4270          *   400MHz
4271          * So we check to see whether we're above 90% of the lower bin and
4272          * adjust if needed.
4273          */
4274         if (max_pixclk > 288000) {
4275                 return 400;
4276         } else if (max_pixclk > 240000) {
4277                 return 320;
4278         } else
4279                 return 266;
4280         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4281 }
4282
4283 /* compute the max pixel clock for new configuration */
4284 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4285 {
4286         struct drm_device *dev = dev_priv->dev;
4287         struct intel_crtc *intel_crtc;
4288         int max_pixclk = 0;
4289
4290         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4291                             base.head) {
4292                 if (intel_crtc->new_enabled)
4293                         max_pixclk = max(max_pixclk,
4294                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4295         }
4296
4297         return max_pixclk;
4298 }
4299
4300 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4301                                             unsigned *prepare_pipes)
4302 {
4303         struct drm_i915_private *dev_priv = dev->dev_private;
4304         struct intel_crtc *intel_crtc;
4305         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4306
4307         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4308             dev_priv->vlv_cdclk_freq)
4309                 return;
4310
4311         /* disable/enable all currently active pipes while we change cdclk */
4312         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4313                             base.head)
4314                 if (intel_crtc->base.enabled)
4315                         *prepare_pipes |= (1 << intel_crtc->pipe);
4316 }
4317
4318 static void valleyview_modeset_global_resources(struct drm_device *dev)
4319 {
4320         struct drm_i915_private *dev_priv = dev->dev_private;
4321         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4322         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4323
4324         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4325                 valleyview_set_cdclk(dev, req_cdclk);
4326         modeset_update_crtc_power_domains(dev);
4327 }
4328
4329 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4330 {
4331         struct drm_device *dev = crtc->dev;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4334         struct intel_encoder *encoder;
4335         int pipe = intel_crtc->pipe;
4336         bool is_dsi;
4337
4338         WARN_ON(!crtc->enabled);
4339
4340         if (intel_crtc->active)
4341                 return;
4342
4343         intel_crtc->active = true;
4344
4345         for_each_encoder_on_crtc(dev, crtc, encoder)
4346                 if (encoder->pre_pll_enable)
4347                         encoder->pre_pll_enable(encoder);
4348
4349         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4350
4351         if (!is_dsi)
4352                 vlv_enable_pll(intel_crtc);
4353
4354         for_each_encoder_on_crtc(dev, crtc, encoder)
4355                 if (encoder->pre_enable)
4356                         encoder->pre_enable(encoder);
4357
4358         i9xx_pfit_enable(intel_crtc);
4359
4360         intel_crtc_load_lut(crtc);
4361
4362         intel_update_watermarks(crtc);
4363         intel_enable_pipe(intel_crtc);
4364         intel_wait_for_vblank(dev_priv->dev, pipe);
4365         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4366
4367         intel_crtc_enable_planes(crtc);
4368
4369         for_each_encoder_on_crtc(dev, crtc, encoder)
4370                 encoder->enable(encoder);
4371 }
4372
4373 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4374 {
4375         struct drm_device *dev = crtc->dev;
4376         struct drm_i915_private *dev_priv = dev->dev_private;
4377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4378         struct intel_encoder *encoder;
4379         int pipe = intel_crtc->pipe;
4380
4381         WARN_ON(!crtc->enabled);
4382
4383         if (intel_crtc->active)
4384                 return;
4385
4386         intel_crtc->active = true;
4387
4388         for_each_encoder_on_crtc(dev, crtc, encoder)
4389                 if (encoder->pre_enable)
4390                         encoder->pre_enable(encoder);
4391
4392         i9xx_enable_pll(intel_crtc);
4393
4394         i9xx_pfit_enable(intel_crtc);
4395
4396         intel_crtc_load_lut(crtc);
4397
4398         intel_update_watermarks(crtc);
4399         intel_enable_pipe(intel_crtc);
4400         intel_wait_for_vblank(dev_priv->dev, pipe);
4401         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4402
4403         intel_crtc_enable_planes(crtc);
4404
4405         for_each_encoder_on_crtc(dev, crtc, encoder)
4406                 encoder->enable(encoder);
4407 }
4408
4409 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4410 {
4411         struct drm_device *dev = crtc->base.dev;
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413
4414         if (!crtc->config.gmch_pfit.control)
4415                 return;
4416
4417         assert_pipe_disabled(dev_priv, crtc->pipe);
4418
4419         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4420                          I915_READ(PFIT_CONTROL));
4421         I915_WRITE(PFIT_CONTROL, 0);
4422 }
4423
4424 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4425 {
4426         struct drm_device *dev = crtc->dev;
4427         struct drm_i915_private *dev_priv = dev->dev_private;
4428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4429         struct intel_encoder *encoder;
4430         int pipe = intel_crtc->pipe;
4431
4432         if (!intel_crtc->active)
4433                 return;
4434
4435         for_each_encoder_on_crtc(dev, crtc, encoder)
4436                 encoder->disable(encoder);
4437
4438         intel_crtc_disable_planes(crtc);
4439
4440         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4441         intel_disable_pipe(dev_priv, pipe);
4442
4443         i9xx_pfit_disable(intel_crtc);
4444
4445         for_each_encoder_on_crtc(dev, crtc, encoder)
4446                 if (encoder->post_disable)
4447                         encoder->post_disable(encoder);
4448
4449         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4450                 vlv_disable_pll(dev_priv, pipe);
4451         else if (!IS_VALLEYVIEW(dev))
4452                 i9xx_disable_pll(dev_priv, pipe);
4453
4454         intel_crtc->active = false;
4455         intel_update_watermarks(crtc);
4456
4457         intel_update_fbc(dev);
4458 }
4459
4460 static void i9xx_crtc_off(struct drm_crtc *crtc)
4461 {
4462 }
4463
4464 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4465                                     bool enabled)
4466 {
4467         struct drm_device *dev = crtc->dev;
4468         struct drm_i915_master_private *master_priv;
4469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4470         int pipe = intel_crtc->pipe;
4471
4472         if (!dev->primary->master)
4473                 return;
4474
4475         master_priv = dev->primary->master->driver_priv;
4476         if (!master_priv->sarea_priv)
4477                 return;
4478
4479         switch (pipe) {
4480         case 0:
4481                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4482                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4483                 break;
4484         case 1:
4485                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4486                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4487                 break;
4488         default:
4489                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4490                 break;
4491         }
4492 }
4493
4494 /**
4495  * Sets the power management mode of the pipe and plane.
4496  */
4497 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4498 {
4499         struct drm_device *dev = crtc->dev;
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         struct intel_encoder *intel_encoder;
4502         bool enable = false;
4503
4504         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4505                 enable |= intel_encoder->connectors_active;
4506
4507         if (enable)
4508                 dev_priv->display.crtc_enable(crtc);
4509         else
4510                 dev_priv->display.crtc_disable(crtc);
4511
4512         intel_crtc_update_sarea(crtc, enable);
4513 }
4514
4515 static void intel_crtc_disable(struct drm_crtc *crtc)
4516 {
4517         struct drm_device *dev = crtc->dev;
4518         struct drm_connector *connector;
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4521
4522         /* crtc should still be enabled when we disable it. */
4523         WARN_ON(!crtc->enabled);
4524
4525         dev_priv->display.crtc_disable(crtc);
4526         intel_crtc->eld_vld = false;
4527         intel_crtc_update_sarea(crtc, false);
4528         dev_priv->display.off(crtc);
4529
4530         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4531         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4532         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4533
4534         if (crtc->primary->fb) {
4535                 mutex_lock(&dev->struct_mutex);
4536                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4537                 mutex_unlock(&dev->struct_mutex);
4538                 crtc->primary->fb = NULL;
4539         }
4540
4541         /* Update computed state. */
4542         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4543                 if (!connector->encoder || !connector->encoder->crtc)
4544                         continue;
4545
4546                 if (connector->encoder->crtc != crtc)
4547                         continue;
4548
4549                 connector->dpms = DRM_MODE_DPMS_OFF;
4550                 to_intel_encoder(connector->encoder)->connectors_active = false;
4551         }
4552 }
4553
4554 void intel_encoder_destroy(struct drm_encoder *encoder)
4555 {
4556         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4557
4558         drm_encoder_cleanup(encoder);
4559         kfree(intel_encoder);
4560 }
4561
4562 /* Simple dpms helper for encoders with just one connector, no cloning and only
4563  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4564  * state of the entire output pipe. */
4565 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4566 {
4567         if (mode == DRM_MODE_DPMS_ON) {
4568                 encoder->connectors_active = true;
4569
4570                 intel_crtc_update_dpms(encoder->base.crtc);
4571         } else {
4572                 encoder->connectors_active = false;
4573
4574                 intel_crtc_update_dpms(encoder->base.crtc);
4575         }
4576 }
4577
4578 /* Cross check the actual hw state with our own modeset state tracking (and it's
4579  * internal consistency). */
4580 static void intel_connector_check_state(struct intel_connector *connector)
4581 {
4582         if (connector->get_hw_state(connector)) {
4583                 struct intel_encoder *encoder = connector->encoder;
4584                 struct drm_crtc *crtc;
4585                 bool encoder_enabled;
4586                 enum pipe pipe;
4587
4588                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4589                               connector->base.base.id,
4590                               drm_get_connector_name(&connector->base));
4591
4592                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4593                      "wrong connector dpms state\n");
4594                 WARN(connector->base.encoder != &encoder->base,
4595                      "active connector not linked to encoder\n");
4596                 WARN(!encoder->connectors_active,
4597                      "encoder->connectors_active not set\n");
4598
4599                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4600                 WARN(!encoder_enabled, "encoder not enabled\n");
4601                 if (WARN_ON(!encoder->base.crtc))
4602                         return;
4603
4604                 crtc = encoder->base.crtc;
4605
4606                 WARN(!crtc->enabled, "crtc not enabled\n");
4607                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4608                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4609                      "encoder active on the wrong pipe\n");
4610         }
4611 }
4612
4613 /* Even simpler default implementation, if there's really no special case to
4614  * consider. */
4615 void intel_connector_dpms(struct drm_connector *connector, int mode)
4616 {
4617         /* All the simple cases only support two dpms states. */
4618         if (mode != DRM_MODE_DPMS_ON)
4619                 mode = DRM_MODE_DPMS_OFF;
4620
4621         if (mode == connector->dpms)
4622                 return;
4623
4624         connector->dpms = mode;
4625
4626         /* Only need to change hw state when actually enabled */
4627         if (connector->encoder)
4628                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4629
4630         intel_modeset_check_state(connector->dev);
4631 }
4632
4633 /* Simple connector->get_hw_state implementation for encoders that support only
4634  * one connector and no cloning and hence the encoder state determines the state
4635  * of the connector. */
4636 bool intel_connector_get_hw_state(struct intel_connector *connector)
4637 {
4638         enum pipe pipe = 0;
4639         struct intel_encoder *encoder = connector->encoder;
4640
4641         return encoder->get_hw_state(encoder, &pipe);
4642 }
4643
4644 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4645                                      struct intel_crtc_config *pipe_config)
4646 {
4647         struct drm_i915_private *dev_priv = dev->dev_private;
4648         struct intel_crtc *pipe_B_crtc =
4649                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4650
4651         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4652                       pipe_name(pipe), pipe_config->fdi_lanes);
4653         if (pipe_config->fdi_lanes > 4) {
4654                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4655                               pipe_name(pipe), pipe_config->fdi_lanes);
4656                 return false;
4657         }
4658
4659         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4660                 if (pipe_config->fdi_lanes > 2) {
4661                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4662                                       pipe_config->fdi_lanes);
4663                         return false;
4664                 } else {
4665                         return true;
4666                 }
4667         }
4668
4669         if (INTEL_INFO(dev)->num_pipes == 2)
4670                 return true;
4671
4672         /* Ivybridge 3 pipe is really complicated */
4673         switch (pipe) {
4674         case PIPE_A:
4675                 return true;
4676         case PIPE_B:
4677                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4678                     pipe_config->fdi_lanes > 2) {
4679                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4680                                       pipe_name(pipe), pipe_config->fdi_lanes);
4681                         return false;
4682                 }
4683                 return true;
4684         case PIPE_C:
4685                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4686                     pipe_B_crtc->config.fdi_lanes <= 2) {
4687                         if (pipe_config->fdi_lanes > 2) {
4688                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4689                                               pipe_name(pipe), pipe_config->fdi_lanes);
4690                                 return false;
4691                         }
4692                 } else {
4693                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4694                         return false;
4695                 }
4696                 return true;
4697         default:
4698                 BUG();
4699         }
4700 }
4701
4702 #define RETRY 1
4703 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4704                                        struct intel_crtc_config *pipe_config)
4705 {
4706         struct drm_device *dev = intel_crtc->base.dev;
4707         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4708         int lane, link_bw, fdi_dotclock;
4709         bool setup_ok, needs_recompute = false;
4710
4711 retry:
4712         /* FDI is a binary signal running at ~2.7GHz, encoding
4713          * each output octet as 10 bits. The actual frequency
4714          * is stored as a divider into a 100MHz clock, and the
4715          * mode pixel clock is stored in units of 1KHz.
4716          * Hence the bw of each lane in terms of the mode signal
4717          * is:
4718          */
4719         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4720
4721         fdi_dotclock = adjusted_mode->crtc_clock;
4722
4723         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4724                                            pipe_config->pipe_bpp);
4725
4726         pipe_config->fdi_lanes = lane;
4727
4728         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4729                                link_bw, &pipe_config->fdi_m_n);
4730
4731         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4732                                             intel_crtc->pipe, pipe_config);
4733         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4734                 pipe_config->pipe_bpp -= 2*3;
4735                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4736                               pipe_config->pipe_bpp);
4737                 needs_recompute = true;
4738                 pipe_config->bw_constrained = true;
4739
4740                 goto retry;
4741         }
4742
4743         if (needs_recompute)
4744                 return RETRY;
4745
4746         return setup_ok ? 0 : -EINVAL;
4747 }
4748
4749 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4750                                    struct intel_crtc_config *pipe_config)
4751 {
4752         pipe_config->ips_enabled = i915.enable_ips &&
4753                                    hsw_crtc_supports_ips(crtc) &&
4754                                    pipe_config->pipe_bpp <= 24;
4755 }
4756
4757 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4758                                      struct intel_crtc_config *pipe_config)
4759 {
4760         struct drm_device *dev = crtc->base.dev;
4761         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4762
4763         /* FIXME should check pixel clock limits on all platforms */
4764         if (INTEL_INFO(dev)->gen < 4) {
4765                 struct drm_i915_private *dev_priv = dev->dev_private;
4766                 int clock_limit =
4767                         dev_priv->display.get_display_clock_speed(dev);
4768
4769                 /*
4770                  * Enable pixel doubling when the dot clock
4771                  * is > 90% of the (display) core speed.
4772                  *
4773                  * GDG double wide on either pipe,
4774                  * otherwise pipe A only.
4775                  */
4776                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4777                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4778                         clock_limit *= 2;
4779                         pipe_config->double_wide = true;
4780                 }
4781
4782                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4783                         return -EINVAL;
4784         }
4785
4786         /*
4787          * Pipe horizontal size must be even in:
4788          * - DVO ganged mode
4789          * - LVDS dual channel mode
4790          * - Double wide pipe
4791          */
4792         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4793              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4794                 pipe_config->pipe_src_w &= ~1;
4795
4796         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4797          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4798          */
4799         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4800                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4801                 return -EINVAL;
4802
4803         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4804                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4805         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4806                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4807                  * for lvds. */
4808                 pipe_config->pipe_bpp = 8*3;
4809         }
4810
4811         if (HAS_IPS(dev))
4812                 hsw_compute_ips_config(crtc, pipe_config);
4813
4814         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4815          * clock survives for now. */
4816         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4817                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4818
4819         if (pipe_config->has_pch_encoder)
4820                 return ironlake_fdi_compute_config(crtc, pipe_config);
4821
4822         return 0;
4823 }
4824
4825 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4826 {
4827         return 400000; /* FIXME */
4828 }
4829
4830 static int i945_get_display_clock_speed(struct drm_device *dev)
4831 {
4832         return 400000;
4833 }
4834
4835 static int i915_get_display_clock_speed(struct drm_device *dev)
4836 {
4837         return 333000;
4838 }
4839
4840 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4841 {
4842         return 200000;
4843 }
4844
4845 static int pnv_get_display_clock_speed(struct drm_device *dev)
4846 {
4847         u16 gcfgc = 0;
4848
4849         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4850
4851         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4852         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4853                 return 267000;
4854         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4855                 return 333000;
4856         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4857                 return 444000;
4858         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4859                 return 200000;
4860         default:
4861                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4862         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4863                 return 133000;
4864         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4865                 return 167000;
4866         }
4867 }
4868
4869 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4870 {
4871         u16 gcfgc = 0;
4872
4873         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4874
4875         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4876                 return 133000;
4877         else {
4878                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4879                 case GC_DISPLAY_CLOCK_333_MHZ:
4880                         return 333000;
4881                 default:
4882                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4883                         return 190000;
4884                 }
4885         }
4886 }
4887
4888 static int i865_get_display_clock_speed(struct drm_device *dev)
4889 {
4890         return 266000;
4891 }
4892
4893 static int i855_get_display_clock_speed(struct drm_device *dev)
4894 {
4895         u16 hpllcc = 0;
4896         /* Assume that the hardware is in the high speed state.  This
4897          * should be the default.
4898          */
4899         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4900         case GC_CLOCK_133_200:
4901         case GC_CLOCK_100_200:
4902                 return 200000;
4903         case GC_CLOCK_166_250:
4904                 return 250000;
4905         case GC_CLOCK_100_133:
4906                 return 133000;
4907         }
4908
4909         /* Shouldn't happen */
4910         return 0;
4911 }
4912
4913 static int i830_get_display_clock_speed(struct drm_device *dev)
4914 {
4915         return 133000;
4916 }
4917
4918 static void
4919 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4920 {
4921         while (*num > DATA_LINK_M_N_MASK ||
4922                *den > DATA_LINK_M_N_MASK) {
4923                 *num >>= 1;
4924                 *den >>= 1;
4925         }
4926 }
4927
4928 static void compute_m_n(unsigned int m, unsigned int n,
4929                         uint32_t *ret_m, uint32_t *ret_n)
4930 {
4931         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4932         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4933         intel_reduce_m_n_ratio(ret_m, ret_n);
4934 }
4935
4936 void
4937 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4938                        int pixel_clock, int link_clock,
4939                        struct intel_link_m_n *m_n)
4940 {
4941         m_n->tu = 64;
4942
4943         compute_m_n(bits_per_pixel * pixel_clock,
4944                     link_clock * nlanes * 8,
4945                     &m_n->gmch_m, &m_n->gmch_n);
4946
4947         compute_m_n(pixel_clock, link_clock,
4948                     &m_n->link_m, &m_n->link_n);
4949 }
4950
4951 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4952 {
4953         if (i915.panel_use_ssc >= 0)
4954                 return i915.panel_use_ssc != 0;
4955         return dev_priv->vbt.lvds_use_ssc
4956                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4957 }
4958
4959 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4960 {
4961         struct drm_device *dev = crtc->dev;
4962         struct drm_i915_private *dev_priv = dev->dev_private;
4963         int refclk;
4964
4965         if (IS_VALLEYVIEW(dev)) {
4966                 refclk = 100000;
4967         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4968             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4969                 refclk = dev_priv->vbt.lvds_ssc_freq;
4970                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4971         } else if (!IS_GEN2(dev)) {
4972                 refclk = 96000;
4973         } else {
4974                 refclk = 48000;
4975         }
4976
4977         return refclk;
4978 }
4979
4980 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4981 {
4982         return (1 << dpll->n) << 16 | dpll->m2;
4983 }
4984
4985 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4986 {
4987         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4988 }
4989
4990 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4991                                      intel_clock_t *reduced_clock)
4992 {
4993         struct drm_device *dev = crtc->base.dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995         int pipe = crtc->pipe;
4996         u32 fp, fp2 = 0;
4997
4998         if (IS_PINEVIEW(dev)) {
4999                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5000                 if (reduced_clock)
5001                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5002         } else {
5003                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5004                 if (reduced_clock)
5005                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5006         }
5007
5008         I915_WRITE(FP0(pipe), fp);
5009         crtc->config.dpll_hw_state.fp0 = fp;
5010
5011         crtc->lowfreq_avail = false;
5012         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5013             reduced_clock && i915.powersave) {
5014                 I915_WRITE(FP1(pipe), fp2);
5015                 crtc->config.dpll_hw_state.fp1 = fp2;
5016                 crtc->lowfreq_avail = true;
5017         } else {
5018                 I915_WRITE(FP1(pipe), fp);
5019                 crtc->config.dpll_hw_state.fp1 = fp;
5020         }
5021 }
5022
5023 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5024                 pipe)
5025 {
5026         u32 reg_val;
5027
5028         /*
5029          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5030          * and set it to a reasonable value instead.
5031          */
5032         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5033         reg_val &= 0xffffff00;
5034         reg_val |= 0x00000030;
5035         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5036
5037         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5038         reg_val &= 0x8cffffff;
5039         reg_val = 0x8c000000;
5040         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5041
5042         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5043         reg_val &= 0xffffff00;
5044         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5045
5046         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5047         reg_val &= 0x00ffffff;
5048         reg_val |= 0xb0000000;
5049         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5050 }
5051
5052 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5053                                          struct intel_link_m_n *m_n)
5054 {
5055         struct drm_device *dev = crtc->base.dev;
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         int pipe = crtc->pipe;
5058
5059         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5060         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5061         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5062         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5063 }
5064
5065 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5066                                          struct intel_link_m_n *m_n)
5067 {
5068         struct drm_device *dev = crtc->base.dev;
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         int pipe = crtc->pipe;
5071         enum transcoder transcoder = crtc->config.cpu_transcoder;
5072
5073         if (INTEL_INFO(dev)->gen >= 5) {
5074                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5075                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5076                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5077                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5078         } else {
5079                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5080                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5081                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5082                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5083         }
5084 }
5085
5086 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5087 {
5088         if (crtc->config.has_pch_encoder)
5089                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5090         else
5091                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5092 }
5093
5094 static void vlv_update_pll(struct intel_crtc *crtc)
5095 {
5096         struct drm_device *dev = crtc->base.dev;
5097         struct drm_i915_private *dev_priv = dev->dev_private;
5098         int pipe = crtc->pipe;
5099         u32 dpll, mdiv;
5100         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5101         u32 coreclk, reg_val, dpll_md;
5102
5103         mutex_lock(&dev_priv->dpio_lock);
5104
5105         bestn = crtc->config.dpll.n;
5106         bestm1 = crtc->config.dpll.m1;
5107         bestm2 = crtc->config.dpll.m2;
5108         bestp1 = crtc->config.dpll.p1;
5109         bestp2 = crtc->config.dpll.p2;
5110
5111         /* See eDP HDMI DPIO driver vbios notes doc */
5112
5113         /* PLL B needs special handling */
5114         if (pipe)
5115                 vlv_pllb_recal_opamp(dev_priv, pipe);
5116
5117         /* Set up Tx target for periodic Rcomp update */
5118         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5119
5120         /* Disable target IRef on PLL */
5121         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5122         reg_val &= 0x00ffffff;
5123         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5124
5125         /* Disable fast lock */
5126         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5127
5128         /* Set idtafcrecal before PLL is enabled */
5129         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5130         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5131         mdiv |= ((bestn << DPIO_N_SHIFT));
5132         mdiv |= (1 << DPIO_K_SHIFT);
5133
5134         /*
5135          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5136          * but we don't support that).
5137          * Note: don't use the DAC post divider as it seems unstable.
5138          */
5139         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5140         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5141
5142         mdiv |= DPIO_ENABLE_CALIBRATION;
5143         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5144
5145         /* Set HBR and RBR LPF coefficients */
5146         if (crtc->config.port_clock == 162000 ||
5147             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5148             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5149                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5150                                  0x009f0003);
5151         else
5152                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5153                                  0x00d0000f);
5154
5155         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5156             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5157                 /* Use SSC source */
5158                 if (!pipe)
5159                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5160                                          0x0df40000);
5161                 else
5162                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5163                                          0x0df70000);
5164         } else { /* HDMI or VGA */
5165                 /* Use bend source */
5166                 if (!pipe)
5167                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5168                                          0x0df70000);
5169                 else
5170                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5171                                          0x0df40000);
5172         }
5173
5174         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5175         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5176         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5177             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5178                 coreclk |= 0x01000000;
5179         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5180
5181         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5182
5183         /*
5184          * Enable DPIO clock input. We should never disable the reference
5185          * clock for pipe B, since VGA hotplug / manual detection depends
5186          * on it.
5187          */
5188         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5189                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5190         /* We should never disable this, set it here for state tracking */
5191         if (pipe == PIPE_B)
5192                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5193         dpll |= DPLL_VCO_ENABLE;
5194         crtc->config.dpll_hw_state.dpll = dpll;
5195
5196         dpll_md = (crtc->config.pixel_multiplier - 1)
5197                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5198         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5199
5200         mutex_unlock(&dev_priv->dpio_lock);
5201 }
5202
5203 static void i9xx_update_pll(struct intel_crtc *crtc,
5204                             intel_clock_t *reduced_clock,
5205                             int num_connectors)
5206 {
5207         struct drm_device *dev = crtc->base.dev;
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         u32 dpll;
5210         bool is_sdvo;
5211         struct dpll *clock = &crtc->config.dpll;
5212
5213         i9xx_update_pll_dividers(crtc, reduced_clock);
5214
5215         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5216                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5217
5218         dpll = DPLL_VGA_MODE_DIS;
5219
5220         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5221                 dpll |= DPLLB_MODE_LVDS;
5222         else
5223                 dpll |= DPLLB_MODE_DAC_SERIAL;
5224
5225         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5226                 dpll |= (crtc->config.pixel_multiplier - 1)
5227                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5228         }
5229
5230         if (is_sdvo)
5231                 dpll |= DPLL_SDVO_HIGH_SPEED;
5232
5233         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5234                 dpll |= DPLL_SDVO_HIGH_SPEED;
5235
5236         /* compute bitmask from p1 value */
5237         if (IS_PINEVIEW(dev))
5238                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5239         else {
5240                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5241                 if (IS_G4X(dev) && reduced_clock)
5242                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5243         }
5244         switch (clock->p2) {
5245         case 5:
5246                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5247                 break;
5248         case 7:
5249                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5250                 break;
5251         case 10:
5252                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5253                 break;
5254         case 14:
5255                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5256                 break;
5257         }
5258         if (INTEL_INFO(dev)->gen >= 4)
5259                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5260
5261         if (crtc->config.sdvo_tv_clock)
5262                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5263         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5264                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5265                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5266         else
5267                 dpll |= PLL_REF_INPUT_DREFCLK;
5268
5269         dpll |= DPLL_VCO_ENABLE;
5270         crtc->config.dpll_hw_state.dpll = dpll;
5271
5272         if (INTEL_INFO(dev)->gen >= 4) {
5273                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5274                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5275                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5276         }
5277 }
5278
5279 static void i8xx_update_pll(struct intel_crtc *crtc,
5280                             intel_clock_t *reduced_clock,
5281                             int num_connectors)
5282 {
5283         struct drm_device *dev = crtc->base.dev;
5284         struct drm_i915_private *dev_priv = dev->dev_private;
5285         u32 dpll;
5286         struct dpll *clock = &crtc->config.dpll;
5287
5288         i9xx_update_pll_dividers(crtc, reduced_clock);
5289
5290         dpll = DPLL_VGA_MODE_DIS;
5291
5292         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5293                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5294         } else {
5295                 if (clock->p1 == 2)
5296                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5297                 else
5298                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5299                 if (clock->p2 == 4)
5300                         dpll |= PLL_P2_DIVIDE_BY_4;
5301         }
5302
5303         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5304                 dpll |= DPLL_DVO_2X_MODE;
5305
5306         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5307                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5308                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5309         else
5310                 dpll |= PLL_REF_INPUT_DREFCLK;
5311
5312         dpll |= DPLL_VCO_ENABLE;
5313         crtc->config.dpll_hw_state.dpll = dpll;
5314 }
5315
5316 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5317 {
5318         struct drm_device *dev = intel_crtc->base.dev;
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320         enum pipe pipe = intel_crtc->pipe;
5321         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5322         struct drm_display_mode *adjusted_mode =
5323                 &intel_crtc->config.adjusted_mode;
5324         uint32_t crtc_vtotal, crtc_vblank_end;
5325         int vsyncshift = 0;
5326
5327         /* We need to be careful not to changed the adjusted mode, for otherwise
5328          * the hw state checker will get angry at the mismatch. */
5329         crtc_vtotal = adjusted_mode->crtc_vtotal;
5330         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5331
5332         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5333                 /* the chip adds 2 halflines automatically */
5334                 crtc_vtotal -= 1;
5335                 crtc_vblank_end -= 1;
5336
5337                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5338                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5339                 else
5340                         vsyncshift = adjusted_mode->crtc_hsync_start -
5341                                 adjusted_mode->crtc_htotal / 2;
5342                 if (vsyncshift < 0)
5343                         vsyncshift += adjusted_mode->crtc_htotal;
5344         }
5345
5346         if (INTEL_INFO(dev)->gen > 3)
5347                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5348
5349         I915_WRITE(HTOTAL(cpu_transcoder),
5350                    (adjusted_mode->crtc_hdisplay - 1) |
5351                    ((adjusted_mode->crtc_htotal - 1) << 16));
5352         I915_WRITE(HBLANK(cpu_transcoder),
5353                    (adjusted_mode->crtc_hblank_start - 1) |
5354                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5355         I915_WRITE(HSYNC(cpu_transcoder),
5356                    (adjusted_mode->crtc_hsync_start - 1) |
5357                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5358
5359         I915_WRITE(VTOTAL(cpu_transcoder),
5360                    (adjusted_mode->crtc_vdisplay - 1) |
5361                    ((crtc_vtotal - 1) << 16));
5362         I915_WRITE(VBLANK(cpu_transcoder),
5363                    (adjusted_mode->crtc_vblank_start - 1) |
5364                    ((crtc_vblank_end - 1) << 16));
5365         I915_WRITE(VSYNC(cpu_transcoder),
5366                    (adjusted_mode->crtc_vsync_start - 1) |
5367                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5368
5369         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5370          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5371          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5372          * bits. */
5373         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5374             (pipe == PIPE_B || pipe == PIPE_C))
5375                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5376
5377         /* pipesrc controls the size that is scaled from, which should
5378          * always be the user's requested size.
5379          */
5380         I915_WRITE(PIPESRC(pipe),
5381                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5382                    (intel_crtc->config.pipe_src_h - 1));
5383 }
5384
5385 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5386                                    struct intel_crtc_config *pipe_config)
5387 {
5388         struct drm_device *dev = crtc->base.dev;
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5391         uint32_t tmp;
5392
5393         tmp = I915_READ(HTOTAL(cpu_transcoder));
5394         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5395         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5396         tmp = I915_READ(HBLANK(cpu_transcoder));
5397         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5398         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5399         tmp = I915_READ(HSYNC(cpu_transcoder));
5400         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5401         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5402
5403         tmp = I915_READ(VTOTAL(cpu_transcoder));
5404         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5405         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5406         tmp = I915_READ(VBLANK(cpu_transcoder));
5407         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5408         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5409         tmp = I915_READ(VSYNC(cpu_transcoder));
5410         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5411         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5412
5413         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5414                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5415                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5416                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5417         }
5418
5419         tmp = I915_READ(PIPESRC(crtc->pipe));
5420         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5421         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5422
5423         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5424         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5425 }
5426
5427 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5428                                  struct intel_crtc_config *pipe_config)
5429 {
5430         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5431         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5432         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5433         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5434
5435         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5436         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5437         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5438         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5439
5440         mode->flags = pipe_config->adjusted_mode.flags;
5441
5442         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5443         mode->flags |= pipe_config->adjusted_mode.flags;
5444 }
5445
5446 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5447 {
5448         struct drm_device *dev = intel_crtc->base.dev;
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450         uint32_t pipeconf;
5451
5452         pipeconf = 0;
5453
5454         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5455             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5456                 pipeconf |= PIPECONF_ENABLE;
5457
5458         if (intel_crtc->config.double_wide)
5459                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5460
5461         /* only g4x and later have fancy bpc/dither controls */
5462         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5463                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5464                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5465                         pipeconf |= PIPECONF_DITHER_EN |
5466                                     PIPECONF_DITHER_TYPE_SP;
5467
5468                 switch (intel_crtc->config.pipe_bpp) {
5469                 case 18:
5470                         pipeconf |= PIPECONF_6BPC;
5471                         break;
5472                 case 24:
5473                         pipeconf |= PIPECONF_8BPC;
5474                         break;
5475                 case 30:
5476                         pipeconf |= PIPECONF_10BPC;
5477                         break;
5478                 default:
5479                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5480                         BUG();
5481                 }
5482         }
5483
5484         if (HAS_PIPE_CXSR(dev)) {
5485                 if (intel_crtc->lowfreq_avail) {
5486                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5487                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5488                 } else {
5489                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5490                 }
5491         }
5492
5493         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5494                 if (INTEL_INFO(dev)->gen < 4 ||
5495                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5496                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5497                 else
5498                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5499         } else
5500                 pipeconf |= PIPECONF_PROGRESSIVE;
5501
5502         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5503                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5504
5505         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5506         POSTING_READ(PIPECONF(intel_crtc->pipe));
5507 }
5508
5509 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5510                               int x, int y,
5511                               struct drm_framebuffer *fb)
5512 {
5513         struct drm_device *dev = crtc->dev;
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5516         int pipe = intel_crtc->pipe;
5517         int plane = intel_crtc->plane;
5518         int refclk, num_connectors = 0;
5519         intel_clock_t clock, reduced_clock;
5520         u32 dspcntr;
5521         bool ok, has_reduced_clock = false;
5522         bool is_lvds = false, is_dsi = false;
5523         struct intel_encoder *encoder;
5524         const intel_limit_t *limit;
5525         int ret;
5526
5527         for_each_encoder_on_crtc(dev, crtc, encoder) {
5528                 switch (encoder->type) {
5529                 case INTEL_OUTPUT_LVDS:
5530                         is_lvds = true;
5531                         break;
5532                 case INTEL_OUTPUT_DSI:
5533                         is_dsi = true;
5534                         break;
5535                 }
5536
5537                 num_connectors++;
5538         }
5539
5540         if (is_dsi)
5541                 goto skip_dpll;
5542
5543         if (!intel_crtc->config.clock_set) {
5544                 refclk = i9xx_get_refclk(crtc, num_connectors);
5545
5546                 /*
5547                  * Returns a set of divisors for the desired target clock with
5548                  * the given refclk, or FALSE.  The returned values represent
5549                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5550                  * 2) / p1 / p2.
5551                  */
5552                 limit = intel_limit(crtc, refclk);
5553                 ok = dev_priv->display.find_dpll(limit, crtc,
5554                                                  intel_crtc->config.port_clock,
5555                                                  refclk, NULL, &clock);
5556                 if (!ok) {
5557                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5558                         return -EINVAL;
5559                 }
5560
5561                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5562                         /*
5563                          * Ensure we match the reduced clock's P to the target
5564                          * clock.  If the clocks don't match, we can't switch
5565                          * the display clock by using the FP0/FP1. In such case
5566                          * we will disable the LVDS downclock feature.
5567                          */
5568                         has_reduced_clock =
5569                                 dev_priv->display.find_dpll(limit, crtc,
5570                                                             dev_priv->lvds_downclock,
5571                                                             refclk, &clock,
5572                                                             &reduced_clock);
5573                 }
5574                 /* Compat-code for transition, will disappear. */
5575                 intel_crtc->config.dpll.n = clock.n;
5576                 intel_crtc->config.dpll.m1 = clock.m1;
5577                 intel_crtc->config.dpll.m2 = clock.m2;
5578                 intel_crtc->config.dpll.p1 = clock.p1;
5579                 intel_crtc->config.dpll.p2 = clock.p2;
5580         }
5581
5582         if (IS_GEN2(dev)) {
5583                 i8xx_update_pll(intel_crtc,
5584                                 has_reduced_clock ? &reduced_clock : NULL,
5585                                 num_connectors);
5586         } else if (IS_VALLEYVIEW(dev)) {
5587                 vlv_update_pll(intel_crtc);
5588         } else {
5589                 i9xx_update_pll(intel_crtc,
5590                                 has_reduced_clock ? &reduced_clock : NULL,
5591                                 num_connectors);
5592         }
5593
5594 skip_dpll:
5595         /* Set up the display plane register */
5596         dspcntr = DISPPLANE_GAMMA_ENABLE;
5597
5598         if (!IS_VALLEYVIEW(dev)) {
5599                 if (pipe == 0)
5600                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5601                 else
5602                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5603         }
5604
5605         if (intel_crtc->config.has_dp_encoder)
5606                 intel_dp_set_m_n(intel_crtc);
5607
5608         intel_set_pipe_timings(intel_crtc);
5609
5610         /* pipesrc and dspsize control the size that is scaled from,
5611          * which should always be the user's requested size.
5612          */
5613         I915_WRITE(DSPSIZE(plane),
5614                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5615                    (intel_crtc->config.pipe_src_w - 1));
5616         I915_WRITE(DSPPOS(plane), 0);
5617
5618         i9xx_set_pipeconf(intel_crtc);
5619
5620         I915_WRITE(DSPCNTR(plane), dspcntr);
5621         POSTING_READ(DSPCNTR(plane));
5622
5623         ret = intel_pipe_set_base(crtc, x, y, fb);
5624
5625         return ret;
5626 }
5627
5628 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5629                                  struct intel_crtc_config *pipe_config)
5630 {
5631         struct drm_device *dev = crtc->base.dev;
5632         struct drm_i915_private *dev_priv = dev->dev_private;
5633         uint32_t tmp;
5634
5635         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5636                 return;
5637
5638         tmp = I915_READ(PFIT_CONTROL);
5639         if (!(tmp & PFIT_ENABLE))
5640                 return;
5641
5642         /* Check whether the pfit is attached to our pipe. */
5643         if (INTEL_INFO(dev)->gen < 4) {
5644                 if (crtc->pipe != PIPE_B)
5645                         return;
5646         } else {
5647                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5648                         return;
5649         }
5650
5651         pipe_config->gmch_pfit.control = tmp;
5652         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5653         if (INTEL_INFO(dev)->gen < 5)
5654                 pipe_config->gmch_pfit.lvds_border_bits =
5655                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5656 }
5657
5658 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5659                                struct intel_crtc_config *pipe_config)
5660 {
5661         struct drm_device *dev = crtc->base.dev;
5662         struct drm_i915_private *dev_priv = dev->dev_private;
5663         int pipe = pipe_config->cpu_transcoder;
5664         intel_clock_t clock;
5665         u32 mdiv;
5666         int refclk = 100000;
5667
5668         mutex_lock(&dev_priv->dpio_lock);
5669         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5670         mutex_unlock(&dev_priv->dpio_lock);
5671
5672         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5673         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5674         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5675         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5676         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5677
5678         vlv_clock(refclk, &clock);
5679
5680         /* clock.dot is the fast clock */
5681         pipe_config->port_clock = clock.dot / 5;
5682 }
5683
5684 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5685                                   struct intel_plane_config *plane_config)
5686 {
5687         struct drm_device *dev = crtc->base.dev;
5688         struct drm_i915_private *dev_priv = dev->dev_private;
5689         u32 val, base, offset;
5690         int pipe = crtc->pipe, plane = crtc->plane;
5691         int fourcc, pixel_format;
5692         int aligned_height;
5693
5694         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5695         if (!crtc->base.primary->fb) {
5696                 DRM_DEBUG_KMS("failed to alloc fb\n");
5697                 return;
5698         }
5699
5700         val = I915_READ(DSPCNTR(plane));
5701
5702         if (INTEL_INFO(dev)->gen >= 4)
5703                 if (val & DISPPLANE_TILED)
5704                         plane_config->tiled = true;
5705
5706         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5707         fourcc = intel_format_to_fourcc(pixel_format);
5708         crtc->base.primary->fb->pixel_format = fourcc;
5709         crtc->base.primary->fb->bits_per_pixel =
5710                 drm_format_plane_cpp(fourcc, 0) * 8;
5711
5712         if (INTEL_INFO(dev)->gen >= 4) {
5713                 if (plane_config->tiled)
5714                         offset = I915_READ(DSPTILEOFF(plane));
5715                 else
5716                         offset = I915_READ(DSPLINOFF(plane));
5717                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5718         } else {
5719                 base = I915_READ(DSPADDR(plane));
5720         }
5721         plane_config->base = base;
5722
5723         val = I915_READ(PIPESRC(pipe));
5724         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5725         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5726
5727         val = I915_READ(DSPSTRIDE(pipe));
5728         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5729
5730         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5731                                             plane_config->tiled);
5732
5733         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5734                                    aligned_height, PAGE_SIZE);
5735
5736         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5737                       pipe, plane, crtc->base.primary->fb->width,
5738                       crtc->base.primary->fb->height,
5739                       crtc->base.primary->fb->bits_per_pixel, base,
5740                       crtc->base.primary->fb->pitches[0],
5741                       plane_config->size);
5742
5743 }
5744
5745 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5746                                  struct intel_crtc_config *pipe_config)
5747 {
5748         struct drm_device *dev = crtc->base.dev;
5749         struct drm_i915_private *dev_priv = dev->dev_private;
5750         uint32_t tmp;
5751
5752         if (!intel_display_power_enabled(dev_priv,
5753                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5754                 return false;
5755
5756         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5757         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5758
5759         tmp = I915_READ(PIPECONF(crtc->pipe));
5760         if (!(tmp & PIPECONF_ENABLE))
5761                 return false;
5762
5763         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5764                 switch (tmp & PIPECONF_BPC_MASK) {
5765                 case PIPECONF_6BPC:
5766                         pipe_config->pipe_bpp = 18;
5767                         break;
5768                 case PIPECONF_8BPC:
5769                         pipe_config->pipe_bpp = 24;
5770                         break;
5771                 case PIPECONF_10BPC:
5772                         pipe_config->pipe_bpp = 30;
5773                         break;
5774                 default:
5775                         break;
5776                 }
5777         }
5778
5779         if (INTEL_INFO(dev)->gen < 4)
5780                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5781
5782         intel_get_pipe_timings(crtc, pipe_config);
5783
5784         i9xx_get_pfit_config(crtc, pipe_config);
5785
5786         if (INTEL_INFO(dev)->gen >= 4) {
5787                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5788                 pipe_config->pixel_multiplier =
5789                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5790                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5791                 pipe_config->dpll_hw_state.dpll_md = tmp;
5792         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5793                 tmp = I915_READ(DPLL(crtc->pipe));
5794                 pipe_config->pixel_multiplier =
5795                         ((tmp & SDVO_MULTIPLIER_MASK)
5796                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5797         } else {
5798                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5799                  * port and will be fixed up in the encoder->get_config
5800                  * function. */
5801                 pipe_config->pixel_multiplier = 1;
5802         }
5803         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5804         if (!IS_VALLEYVIEW(dev)) {
5805                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5806                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5807         } else {
5808                 /* Mask out read-only status bits. */
5809                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5810                                                      DPLL_PORTC_READY_MASK |
5811                                                      DPLL_PORTB_READY_MASK);
5812         }
5813
5814         if (IS_VALLEYVIEW(dev))
5815                 vlv_crtc_clock_get(crtc, pipe_config);
5816         else
5817                 i9xx_crtc_clock_get(crtc, pipe_config);
5818
5819         return true;
5820 }
5821
5822 static void ironlake_init_pch_refclk(struct drm_device *dev)
5823 {
5824         struct drm_i915_private *dev_priv = dev->dev_private;
5825         struct drm_mode_config *mode_config = &dev->mode_config;
5826         struct intel_encoder *encoder;
5827         u32 val, final;
5828         bool has_lvds = false;
5829         bool has_cpu_edp = false;
5830         bool has_panel = false;
5831         bool has_ck505 = false;
5832         bool can_ssc = false;
5833
5834         /* We need to take the global config into account */
5835         list_for_each_entry(encoder, &mode_config->encoder_list,
5836                             base.head) {
5837                 switch (encoder->type) {
5838                 case INTEL_OUTPUT_LVDS:
5839                         has_panel = true;
5840                         has_lvds = true;
5841                         break;
5842                 case INTEL_OUTPUT_EDP:
5843                         has_panel = true;
5844                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5845                                 has_cpu_edp = true;
5846                         break;
5847                 }
5848         }
5849
5850         if (HAS_PCH_IBX(dev)) {
5851                 has_ck505 = dev_priv->vbt.display_clock_mode;
5852                 can_ssc = has_ck505;
5853         } else {
5854                 has_ck505 = false;
5855                 can_ssc = true;
5856         }
5857
5858         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5859                       has_panel, has_lvds, has_ck505);
5860
5861         /* Ironlake: try to setup display ref clock before DPLL
5862          * enabling. This is only under driver's control after
5863          * PCH B stepping, previous chipset stepping should be
5864          * ignoring this setting.
5865          */
5866         val = I915_READ(PCH_DREF_CONTROL);
5867
5868         /* As we must carefully and slowly disable/enable each source in turn,
5869          * compute the final state we want first and check if we need to
5870          * make any changes at all.
5871          */
5872         final = val;
5873         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5874         if (has_ck505)
5875                 final |= DREF_NONSPREAD_CK505_ENABLE;
5876         else
5877                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5878
5879         final &= ~DREF_SSC_SOURCE_MASK;
5880         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5881         final &= ~DREF_SSC1_ENABLE;
5882
5883         if (has_panel) {
5884                 final |= DREF_SSC_SOURCE_ENABLE;
5885
5886                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5887                         final |= DREF_SSC1_ENABLE;
5888
5889                 if (has_cpu_edp) {
5890                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5891                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5892                         else
5893                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5894                 } else
5895                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5896         } else {
5897                 final |= DREF_SSC_SOURCE_DISABLE;
5898                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5899         }
5900
5901         if (final == val)
5902                 return;
5903
5904         /* Always enable nonspread source */
5905         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5906
5907         if (has_ck505)
5908                 val |= DREF_NONSPREAD_CK505_ENABLE;
5909         else
5910                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5911
5912         if (has_panel) {
5913                 val &= ~DREF_SSC_SOURCE_MASK;
5914                 val |= DREF_SSC_SOURCE_ENABLE;
5915
5916                 /* SSC must be turned on before enabling the CPU output  */
5917                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5918                         DRM_DEBUG_KMS("Using SSC on panel\n");
5919                         val |= DREF_SSC1_ENABLE;
5920                 } else
5921                         val &= ~DREF_SSC1_ENABLE;
5922
5923                 /* Get SSC going before enabling the outputs */
5924                 I915_WRITE(PCH_DREF_CONTROL, val);
5925                 POSTING_READ(PCH_DREF_CONTROL);
5926                 udelay(200);
5927
5928                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5929
5930                 /* Enable CPU source on CPU attached eDP */
5931                 if (has_cpu_edp) {
5932                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5933                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5934                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5935                         }
5936                         else
5937                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5938                 } else
5939                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5940
5941                 I915_WRITE(PCH_DREF_CONTROL, val);
5942                 POSTING_READ(PCH_DREF_CONTROL);
5943                 udelay(200);
5944         } else {
5945                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5946
5947                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5948
5949                 /* Turn off CPU output */
5950                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5951
5952                 I915_WRITE(PCH_DREF_CONTROL, val);
5953                 POSTING_READ(PCH_DREF_CONTROL);
5954                 udelay(200);
5955
5956                 /* Turn off the SSC source */
5957                 val &= ~DREF_SSC_SOURCE_MASK;
5958                 val |= DREF_SSC_SOURCE_DISABLE;
5959
5960                 /* Turn off SSC1 */
5961                 val &= ~DREF_SSC1_ENABLE;
5962
5963                 I915_WRITE(PCH_DREF_CONTROL, val);
5964                 POSTING_READ(PCH_DREF_CONTROL);
5965                 udelay(200);
5966         }
5967
5968         BUG_ON(val != final);
5969 }
5970
5971 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5972 {
5973         uint32_t tmp;
5974
5975         tmp = I915_READ(SOUTH_CHICKEN2);
5976         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5977         I915_WRITE(SOUTH_CHICKEN2, tmp);
5978
5979         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5980                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5981                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5982
5983         tmp = I915_READ(SOUTH_CHICKEN2);
5984         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5985         I915_WRITE(SOUTH_CHICKEN2, tmp);
5986
5987         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5988                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5989                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5990 }
5991
5992 /* WaMPhyProgramming:hsw */
5993 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5994 {
5995         uint32_t tmp;
5996
5997         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5998         tmp &= ~(0xFF << 24);
5999         tmp |= (0x12 << 24);
6000         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6001
6002         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6003         tmp |= (1 << 11);
6004         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6005
6006         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6007         tmp |= (1 << 11);
6008         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6009
6010         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6011         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6012         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6013
6014         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6015         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6016         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6017
6018         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6019         tmp &= ~(7 << 13);
6020         tmp |= (5 << 13);
6021         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6022
6023         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6024         tmp &= ~(7 << 13);
6025         tmp |= (5 << 13);
6026         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6027
6028         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6029         tmp &= ~0xFF;
6030         tmp |= 0x1C;
6031         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6032
6033         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6034         tmp &= ~0xFF;
6035         tmp |= 0x1C;
6036         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6037
6038         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6039         tmp &= ~(0xFF << 16);
6040         tmp |= (0x1C << 16);
6041         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6042
6043         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6044         tmp &= ~(0xFF << 16);
6045         tmp |= (0x1C << 16);
6046         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6047
6048         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6049         tmp |= (1 << 27);
6050         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6051
6052         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6053         tmp |= (1 << 27);
6054         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6055
6056         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6057         tmp &= ~(0xF << 28);
6058         tmp |= (4 << 28);
6059         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6060
6061         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6062         tmp &= ~(0xF << 28);
6063         tmp |= (4 << 28);
6064         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6065 }
6066
6067 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6068  * Programming" based on the parameters passed:
6069  * - Sequence to enable CLKOUT_DP
6070  * - Sequence to enable CLKOUT_DP without spread
6071  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6072  */
6073 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6074                                  bool with_fdi)
6075 {
6076         struct drm_i915_private *dev_priv = dev->dev_private;
6077         uint32_t reg, tmp;
6078
6079         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6080                 with_spread = true;
6081         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6082                  with_fdi, "LP PCH doesn't have FDI\n"))
6083                 with_fdi = false;
6084
6085         mutex_lock(&dev_priv->dpio_lock);
6086
6087         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6088         tmp &= ~SBI_SSCCTL_DISABLE;
6089         tmp |= SBI_SSCCTL_PATHALT;
6090         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6091
6092         udelay(24);
6093
6094         if (with_spread) {
6095                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6096                 tmp &= ~SBI_SSCCTL_PATHALT;
6097                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6098
6099                 if (with_fdi) {
6100                         lpt_reset_fdi_mphy(dev_priv);
6101                         lpt_program_fdi_mphy(dev_priv);
6102                 }
6103         }
6104
6105         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6106                SBI_GEN0 : SBI_DBUFF0;
6107         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6108         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6109         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6110
6111         mutex_unlock(&dev_priv->dpio_lock);
6112 }
6113
6114 /* Sequence to disable CLKOUT_DP */
6115 static void lpt_disable_clkout_dp(struct drm_device *dev)
6116 {
6117         struct drm_i915_private *dev_priv = dev->dev_private;
6118         uint32_t reg, tmp;
6119
6120         mutex_lock(&dev_priv->dpio_lock);
6121
6122         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6123                SBI_GEN0 : SBI_DBUFF0;
6124         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6125         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6126         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6127
6128         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6129         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6130                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6131                         tmp |= SBI_SSCCTL_PATHALT;
6132                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6133                         udelay(32);
6134                 }
6135                 tmp |= SBI_SSCCTL_DISABLE;
6136                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6137         }
6138
6139         mutex_unlock(&dev_priv->dpio_lock);
6140 }
6141
6142 static void lpt_init_pch_refclk(struct drm_device *dev)
6143 {
6144         struct drm_mode_config *mode_config = &dev->mode_config;
6145         struct intel_encoder *encoder;
6146         bool has_vga = false;
6147
6148         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6149                 switch (encoder->type) {
6150                 case INTEL_OUTPUT_ANALOG:
6151                         has_vga = true;
6152                         break;
6153                 }
6154         }
6155
6156         if (has_vga)
6157                 lpt_enable_clkout_dp(dev, true, true);
6158         else
6159                 lpt_disable_clkout_dp(dev);
6160 }
6161
6162 /*
6163  * Initialize reference clocks when the driver loads
6164  */
6165 void intel_init_pch_refclk(struct drm_device *dev)
6166 {
6167         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6168                 ironlake_init_pch_refclk(dev);
6169         else if (HAS_PCH_LPT(dev))
6170                 lpt_init_pch_refclk(dev);
6171 }
6172
6173 static int ironlake_get_refclk(struct drm_crtc *crtc)
6174 {
6175         struct drm_device *dev = crtc->dev;
6176         struct drm_i915_private *dev_priv = dev->dev_private;
6177         struct intel_encoder *encoder;
6178         int num_connectors = 0;
6179         bool is_lvds = false;
6180
6181         for_each_encoder_on_crtc(dev, crtc, encoder) {
6182                 switch (encoder->type) {
6183                 case INTEL_OUTPUT_LVDS:
6184                         is_lvds = true;
6185                         break;
6186                 }
6187                 num_connectors++;
6188         }
6189
6190         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6191                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6192                               dev_priv->vbt.lvds_ssc_freq);
6193                 return dev_priv->vbt.lvds_ssc_freq;
6194         }
6195
6196         return 120000;
6197 }
6198
6199 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6200 {
6201         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203         int pipe = intel_crtc->pipe;
6204         uint32_t val;
6205
6206         val = 0;
6207
6208         switch (intel_crtc->config.pipe_bpp) {
6209         case 18:
6210                 val |= PIPECONF_6BPC;
6211                 break;
6212         case 24:
6213                 val |= PIPECONF_8BPC;
6214                 break;
6215         case 30:
6216                 val |= PIPECONF_10BPC;
6217                 break;
6218         case 36:
6219                 val |= PIPECONF_12BPC;
6220                 break;
6221         default:
6222                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6223                 BUG();
6224         }
6225
6226         if (intel_crtc->config.dither)
6227                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6228
6229         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6230                 val |= PIPECONF_INTERLACED_ILK;
6231         else
6232                 val |= PIPECONF_PROGRESSIVE;
6233
6234         if (intel_crtc->config.limited_color_range)
6235                 val |= PIPECONF_COLOR_RANGE_SELECT;
6236
6237         I915_WRITE(PIPECONF(pipe), val);
6238         POSTING_READ(PIPECONF(pipe));
6239 }
6240
6241 /*
6242  * Set up the pipe CSC unit.
6243  *
6244  * Currently only full range RGB to limited range RGB conversion
6245  * is supported, but eventually this should handle various
6246  * RGB<->YCbCr scenarios as well.
6247  */
6248 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6249 {
6250         struct drm_device *dev = crtc->dev;
6251         struct drm_i915_private *dev_priv = dev->dev_private;
6252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6253         int pipe = intel_crtc->pipe;
6254         uint16_t coeff = 0x7800; /* 1.0 */
6255
6256         /*
6257          * TODO: Check what kind of values actually come out of the pipe
6258          * with these coeff/postoff values and adjust to get the best
6259          * accuracy. Perhaps we even need to take the bpc value into
6260          * consideration.
6261          */
6262
6263         if (intel_crtc->config.limited_color_range)
6264                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6265
6266         /*
6267          * GY/GU and RY/RU should be the other way around according
6268          * to BSpec, but reality doesn't agree. Just set them up in
6269          * a way that results in the correct picture.
6270          */
6271         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6272         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6273
6274         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6275         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6276
6277         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6278         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6279
6280         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6281         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6282         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6283
6284         if (INTEL_INFO(dev)->gen > 6) {
6285                 uint16_t postoff = 0;
6286
6287                 if (intel_crtc->config.limited_color_range)
6288                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6289
6290                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6291                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6292                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6293
6294                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6295         } else {
6296                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6297
6298                 if (intel_crtc->config.limited_color_range)
6299                         mode |= CSC_BLACK_SCREEN_OFFSET;
6300
6301                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6302         }
6303 }
6304
6305 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6306 {
6307         struct drm_device *dev = crtc->dev;
6308         struct drm_i915_private *dev_priv = dev->dev_private;
6309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6310         enum pipe pipe = intel_crtc->pipe;
6311         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6312         uint32_t val;
6313
6314         val = 0;
6315
6316         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6317                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6318
6319         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6320                 val |= PIPECONF_INTERLACED_ILK;
6321         else
6322                 val |= PIPECONF_PROGRESSIVE;
6323
6324         I915_WRITE(PIPECONF(cpu_transcoder), val);
6325         POSTING_READ(PIPECONF(cpu_transcoder));
6326
6327         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6328         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6329
6330         if (IS_BROADWELL(dev)) {
6331                 val = 0;
6332
6333                 switch (intel_crtc->config.pipe_bpp) {
6334                 case 18:
6335                         val |= PIPEMISC_DITHER_6_BPC;
6336                         break;
6337                 case 24:
6338                         val |= PIPEMISC_DITHER_8_BPC;
6339                         break;
6340                 case 30:
6341                         val |= PIPEMISC_DITHER_10_BPC;
6342                         break;
6343                 case 36:
6344                         val |= PIPEMISC_DITHER_12_BPC;
6345                         break;
6346                 default:
6347                         /* Case prevented by pipe_config_set_bpp. */
6348                         BUG();
6349                 }
6350
6351                 if (intel_crtc->config.dither)
6352                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6353
6354                 I915_WRITE(PIPEMISC(pipe), val);
6355         }
6356 }
6357
6358 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6359                                     intel_clock_t *clock,
6360                                     bool *has_reduced_clock,
6361                                     intel_clock_t *reduced_clock)
6362 {
6363         struct drm_device *dev = crtc->dev;
6364         struct drm_i915_private *dev_priv = dev->dev_private;
6365         struct intel_encoder *intel_encoder;
6366         int refclk;
6367         const intel_limit_t *limit;
6368         bool ret, is_lvds = false;
6369
6370         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6371                 switch (intel_encoder->type) {
6372                 case INTEL_OUTPUT_LVDS:
6373                         is_lvds = true;
6374                         break;
6375                 }
6376         }
6377
6378         refclk = ironlake_get_refclk(crtc);
6379
6380         /*
6381          * Returns a set of divisors for the desired target clock with the given
6382          * refclk, or FALSE.  The returned values represent the clock equation:
6383          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6384          */
6385         limit = intel_limit(crtc, refclk);
6386         ret = dev_priv->display.find_dpll(limit, crtc,
6387                                           to_intel_crtc(crtc)->config.port_clock,
6388                                           refclk, NULL, clock);
6389         if (!ret)
6390                 return false;
6391
6392         if (is_lvds && dev_priv->lvds_downclock_avail) {
6393                 /*
6394                  * Ensure we match the reduced clock's P to the target clock.
6395                  * If the clocks don't match, we can't switch the display clock
6396                  * by using the FP0/FP1. In such case we will disable the LVDS
6397                  * downclock feature.
6398                 */
6399                 *has_reduced_clock =
6400                         dev_priv->display.find_dpll(limit, crtc,
6401                                                     dev_priv->lvds_downclock,
6402                                                     refclk, clock,
6403                                                     reduced_clock);
6404         }
6405
6406         return true;
6407 }
6408
6409 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6410 {
6411         /*
6412          * Account for spread spectrum to avoid
6413          * oversubscribing the link. Max center spread
6414          * is 2.5%; use 5% for safety's sake.
6415          */
6416         u32 bps = target_clock * bpp * 21 / 20;
6417         return DIV_ROUND_UP(bps, link_bw * 8);
6418 }
6419
6420 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6421 {
6422         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6423 }
6424
6425 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6426                                       u32 *fp,
6427                                       intel_clock_t *reduced_clock, u32 *fp2)
6428 {
6429         struct drm_crtc *crtc = &intel_crtc->base;
6430         struct drm_device *dev = crtc->dev;
6431         struct drm_i915_private *dev_priv = dev->dev_private;
6432         struct intel_encoder *intel_encoder;
6433         uint32_t dpll;
6434         int factor, num_connectors = 0;
6435         bool is_lvds = false, is_sdvo = false;
6436
6437         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6438                 switch (intel_encoder->type) {
6439                 case INTEL_OUTPUT_LVDS:
6440                         is_lvds = true;
6441                         break;
6442                 case INTEL_OUTPUT_SDVO:
6443                 case INTEL_OUTPUT_HDMI:
6444                         is_sdvo = true;
6445                         break;
6446                 }
6447
6448                 num_connectors++;
6449         }
6450
6451         /* Enable autotuning of the PLL clock (if permissible) */
6452         factor = 21;
6453         if (is_lvds) {
6454                 if ((intel_panel_use_ssc(dev_priv) &&
6455                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6456                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6457                         factor = 25;
6458         } else if (intel_crtc->config.sdvo_tv_clock)
6459                 factor = 20;
6460
6461         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6462                 *fp |= FP_CB_TUNE;
6463
6464         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6465                 *fp2 |= FP_CB_TUNE;
6466
6467         dpll = 0;
6468
6469         if (is_lvds)
6470                 dpll |= DPLLB_MODE_LVDS;
6471         else
6472                 dpll |= DPLLB_MODE_DAC_SERIAL;
6473
6474         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6475                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6476
6477         if (is_sdvo)
6478                 dpll |= DPLL_SDVO_HIGH_SPEED;
6479         if (intel_crtc->config.has_dp_encoder)
6480                 dpll |= DPLL_SDVO_HIGH_SPEED;
6481
6482         /* compute bitmask from p1 value */
6483         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6484         /* also FPA1 */
6485         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6486
6487         switch (intel_crtc->config.dpll.p2) {
6488         case 5:
6489                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6490                 break;
6491         case 7:
6492                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6493                 break;
6494         case 10:
6495                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6496                 break;
6497         case 14:
6498                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6499                 break;
6500         }
6501
6502         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6503                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6504         else
6505                 dpll |= PLL_REF_INPUT_DREFCLK;
6506
6507         return dpll | DPLL_VCO_ENABLE;
6508 }
6509
6510 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6511                                   int x, int y,
6512                                   struct drm_framebuffer *fb)
6513 {
6514         struct drm_device *dev = crtc->dev;
6515         struct drm_i915_private *dev_priv = dev->dev_private;
6516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6517         int pipe = intel_crtc->pipe;
6518         int plane = intel_crtc->plane;
6519         int num_connectors = 0;
6520         intel_clock_t clock, reduced_clock;
6521         u32 dpll = 0, fp = 0, fp2 = 0;
6522         bool ok, has_reduced_clock = false;
6523         bool is_lvds = false;
6524         struct intel_encoder *encoder;
6525         struct intel_shared_dpll *pll;
6526         int ret;
6527
6528         for_each_encoder_on_crtc(dev, crtc, encoder) {
6529                 switch (encoder->type) {
6530                 case INTEL_OUTPUT_LVDS:
6531                         is_lvds = true;
6532                         break;
6533                 }
6534
6535                 num_connectors++;
6536         }
6537
6538         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6539              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6540
6541         ok = ironlake_compute_clocks(crtc, &clock,
6542                                      &has_reduced_clock, &reduced_clock);
6543         if (!ok && !intel_crtc->config.clock_set) {
6544                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6545                 return -EINVAL;
6546         }
6547         /* Compat-code for transition, will disappear. */
6548         if (!intel_crtc->config.clock_set) {
6549                 intel_crtc->config.dpll.n = clock.n;
6550                 intel_crtc->config.dpll.m1 = clock.m1;
6551                 intel_crtc->config.dpll.m2 = clock.m2;
6552                 intel_crtc->config.dpll.p1 = clock.p1;
6553                 intel_crtc->config.dpll.p2 = clock.p2;
6554         }
6555
6556         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6557         if (intel_crtc->config.has_pch_encoder) {
6558                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6559                 if (has_reduced_clock)
6560                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6561
6562                 dpll = ironlake_compute_dpll(intel_crtc,
6563                                              &fp, &reduced_clock,
6564                                              has_reduced_clock ? &fp2 : NULL);
6565
6566                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6567                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6568                 if (has_reduced_clock)
6569                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6570                 else
6571                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6572
6573                 pll = intel_get_shared_dpll(intel_crtc);
6574                 if (pll == NULL) {
6575                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6576                                          pipe_name(pipe));
6577                         return -EINVAL;
6578                 }
6579         } else
6580                 intel_put_shared_dpll(intel_crtc);
6581
6582         if (intel_crtc->config.has_dp_encoder)
6583                 intel_dp_set_m_n(intel_crtc);
6584
6585         if (is_lvds && has_reduced_clock && i915.powersave)
6586                 intel_crtc->lowfreq_avail = true;
6587         else
6588                 intel_crtc->lowfreq_avail = false;
6589
6590         intel_set_pipe_timings(intel_crtc);
6591
6592         if (intel_crtc->config.has_pch_encoder) {
6593                 intel_cpu_transcoder_set_m_n(intel_crtc,
6594                                              &intel_crtc->config.fdi_m_n);
6595         }
6596
6597         ironlake_set_pipeconf(crtc);
6598
6599         /* Set up the display plane register */
6600         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6601         POSTING_READ(DSPCNTR(plane));
6602
6603         ret = intel_pipe_set_base(crtc, x, y, fb);
6604
6605         return ret;
6606 }
6607
6608 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6609                                          struct intel_link_m_n *m_n)
6610 {
6611         struct drm_device *dev = crtc->base.dev;
6612         struct drm_i915_private *dev_priv = dev->dev_private;
6613         enum pipe pipe = crtc->pipe;
6614
6615         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6616         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6617         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6618                 & ~TU_SIZE_MASK;
6619         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6620         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6621                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6622 }
6623
6624 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6625                                          enum transcoder transcoder,
6626                                          struct intel_link_m_n *m_n)
6627 {
6628         struct drm_device *dev = crtc->base.dev;
6629         struct drm_i915_private *dev_priv = dev->dev_private;
6630         enum pipe pipe = crtc->pipe;
6631
6632         if (INTEL_INFO(dev)->gen >= 5) {
6633                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6634                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6635                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6636                         & ~TU_SIZE_MASK;
6637                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6638                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6639                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6640         } else {
6641                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6642                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6643                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6644                         & ~TU_SIZE_MASK;
6645                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6646                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6647                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6648         }
6649 }
6650
6651 void intel_dp_get_m_n(struct intel_crtc *crtc,
6652                       struct intel_crtc_config *pipe_config)
6653 {
6654         if (crtc->config.has_pch_encoder)
6655                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6656         else
6657                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6658                                              &pipe_config->dp_m_n);
6659 }
6660
6661 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6662                                         struct intel_crtc_config *pipe_config)
6663 {
6664         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6665                                      &pipe_config->fdi_m_n);
6666 }
6667
6668 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6669                                      struct intel_crtc_config *pipe_config)
6670 {
6671         struct drm_device *dev = crtc->base.dev;
6672         struct drm_i915_private *dev_priv = dev->dev_private;
6673         uint32_t tmp;
6674
6675         tmp = I915_READ(PF_CTL(crtc->pipe));
6676
6677         if (tmp & PF_ENABLE) {
6678                 pipe_config->pch_pfit.enabled = true;
6679                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6680                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6681
6682                 /* We currently do not free assignements of panel fitters on
6683                  * ivb/hsw (since we don't use the higher upscaling modes which
6684                  * differentiates them) so just WARN about this case for now. */
6685                 if (IS_GEN7(dev)) {
6686                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6687                                 PF_PIPE_SEL_IVB(crtc->pipe));
6688                 }
6689         }
6690 }
6691
6692 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6693                                       struct intel_plane_config *plane_config)
6694 {
6695         struct drm_device *dev = crtc->base.dev;
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697         u32 val, base, offset;
6698         int pipe = crtc->pipe, plane = crtc->plane;
6699         int fourcc, pixel_format;
6700         int aligned_height;
6701
6702         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6703         if (!crtc->base.primary->fb) {
6704                 DRM_DEBUG_KMS("failed to alloc fb\n");
6705                 return;
6706         }
6707
6708         val = I915_READ(DSPCNTR(plane));
6709
6710         if (INTEL_INFO(dev)->gen >= 4)
6711                 if (val & DISPPLANE_TILED)
6712                         plane_config->tiled = true;
6713
6714         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6715         fourcc = intel_format_to_fourcc(pixel_format);
6716         crtc->base.primary->fb->pixel_format = fourcc;
6717         crtc->base.primary->fb->bits_per_pixel =
6718                 drm_format_plane_cpp(fourcc, 0) * 8;
6719
6720         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6721         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6722                 offset = I915_READ(DSPOFFSET(plane));
6723         } else {
6724                 if (plane_config->tiled)
6725                         offset = I915_READ(DSPTILEOFF(plane));
6726                 else
6727                         offset = I915_READ(DSPLINOFF(plane));
6728         }
6729         plane_config->base = base;
6730
6731         val = I915_READ(PIPESRC(pipe));
6732         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6733         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6734
6735         val = I915_READ(DSPSTRIDE(pipe));
6736         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6737
6738         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6739                                             plane_config->tiled);
6740
6741         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6742                                    aligned_height, PAGE_SIZE);
6743
6744         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6745                       pipe, plane, crtc->base.primary->fb->width,
6746                       crtc->base.primary->fb->height,
6747                       crtc->base.primary->fb->bits_per_pixel, base,
6748                       crtc->base.primary->fb->pitches[0],
6749                       plane_config->size);
6750 }
6751
6752 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6753                                      struct intel_crtc_config *pipe_config)
6754 {
6755         struct drm_device *dev = crtc->base.dev;
6756         struct drm_i915_private *dev_priv = dev->dev_private;
6757         uint32_t tmp;
6758
6759         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6760         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6761
6762         tmp = I915_READ(PIPECONF(crtc->pipe));
6763         if (!(tmp & PIPECONF_ENABLE))
6764                 return false;
6765
6766         switch (tmp & PIPECONF_BPC_MASK) {
6767         case PIPECONF_6BPC:
6768                 pipe_config->pipe_bpp = 18;
6769                 break;
6770         case PIPECONF_8BPC:
6771                 pipe_config->pipe_bpp = 24;
6772                 break;
6773         case PIPECONF_10BPC:
6774                 pipe_config->pipe_bpp = 30;
6775                 break;
6776         case PIPECONF_12BPC:
6777                 pipe_config->pipe_bpp = 36;
6778                 break;
6779         default:
6780                 break;
6781         }
6782
6783         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6784                 struct intel_shared_dpll *pll;
6785
6786                 pipe_config->has_pch_encoder = true;
6787
6788                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6789                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6790                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6791
6792                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6793
6794                 if (HAS_PCH_IBX(dev_priv->dev)) {
6795                         pipe_config->shared_dpll =
6796                                 (enum intel_dpll_id) crtc->pipe;
6797                 } else {
6798                         tmp = I915_READ(PCH_DPLL_SEL);
6799                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6800                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6801                         else
6802                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6803                 }
6804
6805                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6806
6807                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6808                                            &pipe_config->dpll_hw_state));
6809
6810                 tmp = pipe_config->dpll_hw_state.dpll;
6811                 pipe_config->pixel_multiplier =
6812                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6813                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6814
6815                 ironlake_pch_clock_get(crtc, pipe_config);
6816         } else {
6817                 pipe_config->pixel_multiplier = 1;
6818         }
6819
6820         intel_get_pipe_timings(crtc, pipe_config);
6821
6822         ironlake_get_pfit_config(crtc, pipe_config);
6823
6824         return true;
6825 }
6826
6827 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6828 {
6829         struct drm_device *dev = dev_priv->dev;
6830         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6831         struct intel_crtc *crtc;
6832
6833         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6834                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6835                      pipe_name(crtc->pipe));
6836
6837         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6838         WARN(plls->spll_refcount, "SPLL enabled\n");
6839         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6840         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6841         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6842         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6843              "CPU PWM1 enabled\n");
6844         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6845              "CPU PWM2 enabled\n");
6846         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6847              "PCH PWM1 enabled\n");
6848         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6849              "Utility pin enabled\n");
6850         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6851
6852         /*
6853          * In theory we can still leave IRQs enabled, as long as only the HPD
6854          * interrupts remain enabled. We used to check for that, but since it's
6855          * gen-specific and since we only disable LCPLL after we fully disable
6856          * the interrupts, the check below should be enough.
6857          */
6858         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6859 }
6860
6861 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6862 {
6863         struct drm_device *dev = dev_priv->dev;
6864
6865         if (IS_HASWELL(dev)) {
6866                 mutex_lock(&dev_priv->rps.hw_lock);
6867                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6868                                             val))
6869                         DRM_ERROR("Failed to disable D_COMP\n");
6870                 mutex_unlock(&dev_priv->rps.hw_lock);
6871         } else {
6872                 I915_WRITE(D_COMP, val);
6873         }
6874         POSTING_READ(D_COMP);
6875 }
6876
6877 /*
6878  * This function implements pieces of two sequences from BSpec:
6879  * - Sequence for display software to disable LCPLL
6880  * - Sequence for display software to allow package C8+
6881  * The steps implemented here are just the steps that actually touch the LCPLL
6882  * register. Callers should take care of disabling all the display engine
6883  * functions, doing the mode unset, fixing interrupts, etc.
6884  */
6885 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6886                               bool switch_to_fclk, bool allow_power_down)
6887 {
6888         uint32_t val;
6889
6890         assert_can_disable_lcpll(dev_priv);
6891
6892         val = I915_READ(LCPLL_CTL);
6893
6894         if (switch_to_fclk) {
6895                 val |= LCPLL_CD_SOURCE_FCLK;
6896                 I915_WRITE(LCPLL_CTL, val);
6897
6898                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6899                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6900                         DRM_ERROR("Switching to FCLK failed\n");
6901
6902                 val = I915_READ(LCPLL_CTL);
6903         }
6904
6905         val |= LCPLL_PLL_DISABLE;
6906         I915_WRITE(LCPLL_CTL, val);
6907         POSTING_READ(LCPLL_CTL);
6908
6909         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6910                 DRM_ERROR("LCPLL still locked\n");
6911
6912         val = I915_READ(D_COMP);
6913         val |= D_COMP_COMP_DISABLE;
6914         hsw_write_dcomp(dev_priv, val);
6915         ndelay(100);
6916
6917         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6918                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6919
6920         if (allow_power_down) {
6921                 val = I915_READ(LCPLL_CTL);
6922                 val |= LCPLL_POWER_DOWN_ALLOW;
6923                 I915_WRITE(LCPLL_CTL, val);
6924                 POSTING_READ(LCPLL_CTL);
6925         }
6926 }
6927
6928 /*
6929  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6930  * source.
6931  */
6932 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6933 {
6934         uint32_t val;
6935         unsigned long irqflags;
6936
6937         val = I915_READ(LCPLL_CTL);
6938
6939         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6940                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6941                 return;
6942
6943         /*
6944          * Make sure we're not on PC8 state before disabling PC8, otherwise
6945          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6946          *
6947          * The other problem is that hsw_restore_lcpll() is called as part of
6948          * the runtime PM resume sequence, so we can't just call
6949          * gen6_gt_force_wake_get() because that function calls
6950          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6951          * while we are on the resume sequence. So to solve this problem we have
6952          * to call special forcewake code that doesn't touch runtime PM and
6953          * doesn't enable the forcewake delayed work.
6954          */
6955         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6956         if (dev_priv->uncore.forcewake_count++ == 0)
6957                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6958         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6959
6960         if (val & LCPLL_POWER_DOWN_ALLOW) {
6961                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6962                 I915_WRITE(LCPLL_CTL, val);
6963                 POSTING_READ(LCPLL_CTL);
6964         }
6965
6966         val = I915_READ(D_COMP);
6967         val |= D_COMP_COMP_FORCE;
6968         val &= ~D_COMP_COMP_DISABLE;
6969         hsw_write_dcomp(dev_priv, val);
6970
6971         val = I915_READ(LCPLL_CTL);
6972         val &= ~LCPLL_PLL_DISABLE;
6973         I915_WRITE(LCPLL_CTL, val);
6974
6975         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6976                 DRM_ERROR("LCPLL not locked yet\n");
6977
6978         if (val & LCPLL_CD_SOURCE_FCLK) {
6979                 val = I915_READ(LCPLL_CTL);
6980                 val &= ~LCPLL_CD_SOURCE_FCLK;
6981                 I915_WRITE(LCPLL_CTL, val);
6982
6983                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6984                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6985                         DRM_ERROR("Switching back to LCPLL failed\n");
6986         }
6987
6988         /* See the big comment above. */
6989         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6990         if (--dev_priv->uncore.forcewake_count == 0)
6991                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6992         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6993 }
6994
6995 /*
6996  * Package states C8 and deeper are really deep PC states that can only be
6997  * reached when all the devices on the system allow it, so even if the graphics
6998  * device allows PC8+, it doesn't mean the system will actually get to these
6999  * states. Our driver only allows PC8+ when going into runtime PM.
7000  *
7001  * The requirements for PC8+ are that all the outputs are disabled, the power
7002  * well is disabled and most interrupts are disabled, and these are also
7003  * requirements for runtime PM. When these conditions are met, we manually do
7004  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7005  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7006  * hang the machine.
7007  *
7008  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7009  * the state of some registers, so when we come back from PC8+ we need to
7010  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7011  * need to take care of the registers kept by RC6. Notice that this happens even
7012  * if we don't put the device in PCI D3 state (which is what currently happens
7013  * because of the runtime PM support).
7014  *
7015  * For more, read "Display Sequences for Package C8" on the hardware
7016  * documentation.
7017  */
7018 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7019 {
7020         struct drm_device *dev = dev_priv->dev;
7021         uint32_t val;
7022
7023         DRM_DEBUG_KMS("Enabling package C8+\n");
7024
7025         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7026                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7027                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7028                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7029         }
7030
7031         lpt_disable_clkout_dp(dev);
7032         hsw_disable_lcpll(dev_priv, true, true);
7033 }
7034
7035 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7036 {
7037         struct drm_device *dev = dev_priv->dev;
7038         uint32_t val;
7039
7040         DRM_DEBUG_KMS("Disabling package C8+\n");
7041
7042         hsw_restore_lcpll(dev_priv);
7043         lpt_init_pch_refclk(dev);
7044
7045         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7046                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7047                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7048                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7049         }
7050
7051         intel_prepare_ddi(dev);
7052 }
7053
7054 static void snb_modeset_global_resources(struct drm_device *dev)
7055 {
7056         modeset_update_crtc_power_domains(dev);
7057 }
7058
7059 static void haswell_modeset_global_resources(struct drm_device *dev)
7060 {
7061         modeset_update_crtc_power_domains(dev);
7062 }
7063
7064 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7065                                  int x, int y,
7066                                  struct drm_framebuffer *fb)
7067 {
7068         struct drm_device *dev = crtc->dev;
7069         struct drm_i915_private *dev_priv = dev->dev_private;
7070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7071         int plane = intel_crtc->plane;
7072         int ret;
7073
7074         if (!intel_ddi_pll_select(intel_crtc))
7075                 return -EINVAL;
7076         intel_ddi_pll_enable(intel_crtc);
7077
7078         if (intel_crtc->config.has_dp_encoder)
7079                 intel_dp_set_m_n(intel_crtc);
7080
7081         intel_crtc->lowfreq_avail = false;
7082
7083         intel_set_pipe_timings(intel_crtc);
7084
7085         if (intel_crtc->config.has_pch_encoder) {
7086                 intel_cpu_transcoder_set_m_n(intel_crtc,
7087                                              &intel_crtc->config.fdi_m_n);
7088         }
7089
7090         haswell_set_pipeconf(crtc);
7091
7092         intel_set_pipe_csc(crtc);
7093
7094         /* Set up the display plane register */
7095         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7096         POSTING_READ(DSPCNTR(plane));
7097
7098         ret = intel_pipe_set_base(crtc, x, y, fb);
7099
7100         return ret;
7101 }
7102
7103 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7104                                     struct intel_crtc_config *pipe_config)
7105 {
7106         struct drm_device *dev = crtc->base.dev;
7107         struct drm_i915_private *dev_priv = dev->dev_private;
7108         enum intel_display_power_domain pfit_domain;
7109         uint32_t tmp;
7110
7111         if (!intel_display_power_enabled(dev_priv,
7112                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7113                 return false;
7114
7115         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7116         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7117
7118         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7119         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7120                 enum pipe trans_edp_pipe;
7121                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7122                 default:
7123                         WARN(1, "unknown pipe linked to edp transcoder\n");
7124                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7125                 case TRANS_DDI_EDP_INPUT_A_ON:
7126                         trans_edp_pipe = PIPE_A;
7127                         break;
7128                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7129                         trans_edp_pipe = PIPE_B;
7130                         break;
7131                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7132                         trans_edp_pipe = PIPE_C;
7133                         break;
7134                 }
7135
7136                 if (trans_edp_pipe == crtc->pipe)
7137                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7138         }
7139
7140         if (!intel_display_power_enabled(dev_priv,
7141                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7142                 return false;
7143
7144         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7145         if (!(tmp & PIPECONF_ENABLE))
7146                 return false;
7147
7148         /*
7149          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7150          * DDI E. So just check whether this pipe is wired to DDI E and whether
7151          * the PCH transcoder is on.
7152          */
7153         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7154         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7155             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7156                 pipe_config->has_pch_encoder = true;
7157
7158                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7159                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7160                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7161
7162                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7163         }
7164
7165         intel_get_pipe_timings(crtc, pipe_config);
7166
7167         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7168         if (intel_display_power_enabled(dev_priv, pfit_domain))
7169                 ironlake_get_pfit_config(crtc, pipe_config);
7170
7171         if (IS_HASWELL(dev))
7172                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7173                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7174
7175         pipe_config->pixel_multiplier = 1;
7176
7177         return true;
7178 }
7179
7180 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7181                                int x, int y,
7182                                struct drm_framebuffer *fb)
7183 {
7184         struct drm_device *dev = crtc->dev;
7185         struct drm_i915_private *dev_priv = dev->dev_private;
7186         struct intel_encoder *encoder;
7187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7189         int pipe = intel_crtc->pipe;
7190         int ret;
7191
7192         drm_vblank_pre_modeset(dev, pipe);
7193
7194         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7195
7196         drm_vblank_post_modeset(dev, pipe);
7197
7198         if (ret != 0)
7199                 return ret;
7200
7201         for_each_encoder_on_crtc(dev, crtc, encoder) {
7202                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7203                         encoder->base.base.id,
7204                         drm_get_encoder_name(&encoder->base),
7205                         mode->base.id, mode->name);
7206
7207                 if (encoder->mode_set)
7208                         encoder->mode_set(encoder);
7209         }
7210
7211         return 0;
7212 }
7213
7214 static struct {
7215         int clock;
7216         u32 config;
7217 } hdmi_audio_clock[] = {
7218         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7219         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7220         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7221         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7222         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7223         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7224         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7225         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7226         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7227         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7228 };
7229
7230 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7231 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7232 {
7233         int i;
7234
7235         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7236                 if (mode->clock == hdmi_audio_clock[i].clock)
7237                         break;
7238         }
7239
7240         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7241                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7242                 i = 1;
7243         }
7244
7245         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7246                       hdmi_audio_clock[i].clock,
7247                       hdmi_audio_clock[i].config);
7248
7249         return hdmi_audio_clock[i].config;
7250 }
7251
7252 static bool intel_eld_uptodate(struct drm_connector *connector,
7253                                int reg_eldv, uint32_t bits_eldv,
7254                                int reg_elda, uint32_t bits_elda,
7255                                int reg_edid)
7256 {
7257         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7258         uint8_t *eld = connector->eld;
7259         uint32_t i;
7260
7261         i = I915_READ(reg_eldv);
7262         i &= bits_eldv;
7263
7264         if (!eld[0])
7265                 return !i;
7266
7267         if (!i)
7268                 return false;
7269
7270         i = I915_READ(reg_elda);
7271         i &= ~bits_elda;
7272         I915_WRITE(reg_elda, i);
7273
7274         for (i = 0; i < eld[2]; i++)
7275                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7276                         return false;
7277
7278         return true;
7279 }
7280
7281 static void g4x_write_eld(struct drm_connector *connector,
7282                           struct drm_crtc *crtc,
7283                           struct drm_display_mode *mode)
7284 {
7285         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7286         uint8_t *eld = connector->eld;
7287         uint32_t eldv;
7288         uint32_t len;
7289         uint32_t i;
7290
7291         i = I915_READ(G4X_AUD_VID_DID);
7292
7293         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7294                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7295         else
7296                 eldv = G4X_ELDV_DEVCTG;
7297
7298         if (intel_eld_uptodate(connector,
7299                                G4X_AUD_CNTL_ST, eldv,
7300                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7301                                G4X_HDMIW_HDMIEDID))
7302                 return;
7303
7304         i = I915_READ(G4X_AUD_CNTL_ST);
7305         i &= ~(eldv | G4X_ELD_ADDR);
7306         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7307         I915_WRITE(G4X_AUD_CNTL_ST, i);
7308
7309         if (!eld[0])
7310                 return;
7311
7312         len = min_t(uint8_t, eld[2], len);
7313         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7314         for (i = 0; i < len; i++)
7315                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7316
7317         i = I915_READ(G4X_AUD_CNTL_ST);
7318         i |= eldv;
7319         I915_WRITE(G4X_AUD_CNTL_ST, i);
7320 }
7321
7322 static void haswell_write_eld(struct drm_connector *connector,
7323                               struct drm_crtc *crtc,
7324                               struct drm_display_mode *mode)
7325 {
7326         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7327         uint8_t *eld = connector->eld;
7328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329         uint32_t eldv;
7330         uint32_t i;
7331         int len;
7332         int pipe = to_intel_crtc(crtc)->pipe;
7333         int tmp;
7334
7335         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7336         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7337         int aud_config = HSW_AUD_CFG(pipe);
7338         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7339
7340         /* Audio output enable */
7341         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7342         tmp = I915_READ(aud_cntrl_st2);
7343         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7344         I915_WRITE(aud_cntrl_st2, tmp);
7345         POSTING_READ(aud_cntrl_st2);
7346
7347         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7348
7349         /* Set ELD valid state */
7350         tmp = I915_READ(aud_cntrl_st2);
7351         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7352         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7353         I915_WRITE(aud_cntrl_st2, tmp);
7354         tmp = I915_READ(aud_cntrl_st2);
7355         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7356
7357         /* Enable HDMI mode */
7358         tmp = I915_READ(aud_config);
7359         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7360         /* clear N_programing_enable and N_value_index */
7361         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7362         I915_WRITE(aud_config, tmp);
7363
7364         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7365
7366         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7367         intel_crtc->eld_vld = true;
7368
7369         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7370                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7371                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7372                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7373         } else {
7374                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7375         }
7376
7377         if (intel_eld_uptodate(connector,
7378                                aud_cntrl_st2, eldv,
7379                                aud_cntl_st, IBX_ELD_ADDRESS,
7380                                hdmiw_hdmiedid))
7381                 return;
7382
7383         i = I915_READ(aud_cntrl_st2);
7384         i &= ~eldv;
7385         I915_WRITE(aud_cntrl_st2, i);
7386
7387         if (!eld[0])
7388                 return;
7389
7390         i = I915_READ(aud_cntl_st);
7391         i &= ~IBX_ELD_ADDRESS;
7392         I915_WRITE(aud_cntl_st, i);
7393         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7394         DRM_DEBUG_DRIVER("port num:%d\n", i);
7395
7396         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7397         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7398         for (i = 0; i < len; i++)
7399                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7400
7401         i = I915_READ(aud_cntrl_st2);
7402         i |= eldv;
7403         I915_WRITE(aud_cntrl_st2, i);
7404
7405 }
7406
7407 static void ironlake_write_eld(struct drm_connector *connector,
7408                                struct drm_crtc *crtc,
7409                                struct drm_display_mode *mode)
7410 {
7411         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7412         uint8_t *eld = connector->eld;
7413         uint32_t eldv;
7414         uint32_t i;
7415         int len;
7416         int hdmiw_hdmiedid;
7417         int aud_config;
7418         int aud_cntl_st;
7419         int aud_cntrl_st2;
7420         int pipe = to_intel_crtc(crtc)->pipe;
7421
7422         if (HAS_PCH_IBX(connector->dev)) {
7423                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7424                 aud_config = IBX_AUD_CFG(pipe);
7425                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7426                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7427         } else if (IS_VALLEYVIEW(connector->dev)) {
7428                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7429                 aud_config = VLV_AUD_CFG(pipe);
7430                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7431                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7432         } else {
7433                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7434                 aud_config = CPT_AUD_CFG(pipe);
7435                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7436                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7437         }
7438
7439         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7440
7441         if (IS_VALLEYVIEW(connector->dev))  {
7442                 struct intel_encoder *intel_encoder;
7443                 struct intel_digital_port *intel_dig_port;
7444
7445                 intel_encoder = intel_attached_encoder(connector);
7446                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7447                 i = intel_dig_port->port;
7448         } else {
7449                 i = I915_READ(aud_cntl_st);
7450                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7451                 /* DIP_Port_Select, 0x1 = PortB */
7452         }
7453
7454         if (!i) {
7455                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7456                 /* operate blindly on all ports */
7457                 eldv = IBX_ELD_VALIDB;
7458                 eldv |= IBX_ELD_VALIDB << 4;
7459                 eldv |= IBX_ELD_VALIDB << 8;
7460         } else {
7461                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7462                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7463         }
7464
7465         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7466                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7467                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7468                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7469         } else {
7470                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7471         }
7472
7473         if (intel_eld_uptodate(connector,
7474                                aud_cntrl_st2, eldv,
7475                                aud_cntl_st, IBX_ELD_ADDRESS,
7476                                hdmiw_hdmiedid))
7477                 return;
7478
7479         i = I915_READ(aud_cntrl_st2);
7480         i &= ~eldv;
7481         I915_WRITE(aud_cntrl_st2, i);
7482
7483         if (!eld[0])
7484                 return;
7485
7486         i = I915_READ(aud_cntl_st);
7487         i &= ~IBX_ELD_ADDRESS;
7488         I915_WRITE(aud_cntl_st, i);
7489
7490         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7491         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7492         for (i = 0; i < len; i++)
7493                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7494
7495         i = I915_READ(aud_cntrl_st2);
7496         i |= eldv;
7497         I915_WRITE(aud_cntrl_st2, i);
7498 }
7499
7500 void intel_write_eld(struct drm_encoder *encoder,
7501                      struct drm_display_mode *mode)
7502 {
7503         struct drm_crtc *crtc = encoder->crtc;
7504         struct drm_connector *connector;
7505         struct drm_device *dev = encoder->dev;
7506         struct drm_i915_private *dev_priv = dev->dev_private;
7507
7508         connector = drm_select_eld(encoder, mode);
7509         if (!connector)
7510                 return;
7511
7512         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7513                          connector->base.id,
7514                          drm_get_connector_name(connector),
7515                          connector->encoder->base.id,
7516                          drm_get_encoder_name(connector->encoder));
7517
7518         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7519
7520         if (dev_priv->display.write_eld)
7521                 dev_priv->display.write_eld(connector, crtc, mode);
7522 }
7523
7524 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7525 {
7526         struct drm_device *dev = crtc->dev;
7527         struct drm_i915_private *dev_priv = dev->dev_private;
7528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529         bool visible = base != 0;
7530         u32 cntl;
7531
7532         if (intel_crtc->cursor_visible == visible)
7533                 return;
7534
7535         cntl = I915_READ(_CURACNTR);
7536         if (visible) {
7537                 /* On these chipsets we can only modify the base whilst
7538                  * the cursor is disabled.
7539                  */
7540                 I915_WRITE(_CURABASE, base);
7541
7542                 cntl &= ~(CURSOR_FORMAT_MASK);
7543                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7544                 cntl |= CURSOR_ENABLE |
7545                         CURSOR_GAMMA_ENABLE |
7546                         CURSOR_FORMAT_ARGB;
7547         } else
7548                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7549         I915_WRITE(_CURACNTR, cntl);
7550
7551         intel_crtc->cursor_visible = visible;
7552 }
7553
7554 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7555 {
7556         struct drm_device *dev = crtc->dev;
7557         struct drm_i915_private *dev_priv = dev->dev_private;
7558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7559         int pipe = intel_crtc->pipe;
7560         bool visible = base != 0;
7561
7562         if (intel_crtc->cursor_visible != visible) {
7563                 int16_t width = intel_crtc->cursor_width;
7564                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7565                 if (base) {
7566                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7567                         cntl |= MCURSOR_GAMMA_ENABLE;
7568
7569                         switch (width) {
7570                         case 64:
7571                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7572                                 break;
7573                         case 128:
7574                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7575                                 break;
7576                         case 256:
7577                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7578                                 break;
7579                         default:
7580                                 WARN_ON(1);
7581                                 return;
7582                         }
7583                         cntl |= pipe << 28; /* Connect to correct pipe */
7584                 } else {
7585                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7586                         cntl |= CURSOR_MODE_DISABLE;
7587                 }
7588                 I915_WRITE(CURCNTR(pipe), cntl);
7589
7590                 intel_crtc->cursor_visible = visible;
7591         }
7592         /* and commit changes on next vblank */
7593         POSTING_READ(CURCNTR(pipe));
7594         I915_WRITE(CURBASE(pipe), base);
7595         POSTING_READ(CURBASE(pipe));
7596 }
7597
7598 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7599 {
7600         struct drm_device *dev = crtc->dev;
7601         struct drm_i915_private *dev_priv = dev->dev_private;
7602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603         int pipe = intel_crtc->pipe;
7604         bool visible = base != 0;
7605
7606         if (intel_crtc->cursor_visible != visible) {
7607                 int16_t width = intel_crtc->cursor_width;
7608                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7609                 if (base) {
7610                         cntl &= ~CURSOR_MODE;
7611                         cntl |= MCURSOR_GAMMA_ENABLE;
7612                         switch (width) {
7613                         case 64:
7614                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7615                                 break;
7616                         case 128:
7617                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7618                                 break;
7619                         case 256:
7620                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7621                                 break;
7622                         default:
7623                                 WARN_ON(1);
7624                                 return;
7625                         }
7626                 } else {
7627                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7628                         cntl |= CURSOR_MODE_DISABLE;
7629                 }
7630                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7631                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7632                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7633                 }
7634                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7635
7636                 intel_crtc->cursor_visible = visible;
7637         }
7638         /* and commit changes on next vblank */
7639         POSTING_READ(CURCNTR_IVB(pipe));
7640         I915_WRITE(CURBASE_IVB(pipe), base);
7641         POSTING_READ(CURBASE_IVB(pipe));
7642 }
7643
7644 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7645 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7646                                      bool on)
7647 {
7648         struct drm_device *dev = crtc->dev;
7649         struct drm_i915_private *dev_priv = dev->dev_private;
7650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7651         int pipe = intel_crtc->pipe;
7652         int x = intel_crtc->cursor_x;
7653         int y = intel_crtc->cursor_y;
7654         u32 base = 0, pos = 0;
7655         bool visible;
7656
7657         if (on)
7658                 base = intel_crtc->cursor_addr;
7659
7660         if (x >= intel_crtc->config.pipe_src_w)
7661                 base = 0;
7662
7663         if (y >= intel_crtc->config.pipe_src_h)
7664                 base = 0;
7665
7666         if (x < 0) {
7667                 if (x + intel_crtc->cursor_width <= 0)
7668                         base = 0;
7669
7670                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7671                 x = -x;
7672         }
7673         pos |= x << CURSOR_X_SHIFT;
7674
7675         if (y < 0) {
7676                 if (y + intel_crtc->cursor_height <= 0)
7677                         base = 0;
7678
7679                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7680                 y = -y;
7681         }
7682         pos |= y << CURSOR_Y_SHIFT;
7683
7684         visible = base != 0;
7685         if (!visible && !intel_crtc->cursor_visible)
7686                 return;
7687
7688         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7689                 I915_WRITE(CURPOS_IVB(pipe), pos);
7690                 ivb_update_cursor(crtc, base);
7691         } else {
7692                 I915_WRITE(CURPOS(pipe), pos);
7693                 if (IS_845G(dev) || IS_I865G(dev))
7694                         i845_update_cursor(crtc, base);
7695                 else
7696                         i9xx_update_cursor(crtc, base);
7697         }
7698 }
7699
7700 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7701                                  struct drm_file *file,
7702                                  uint32_t handle,
7703                                  uint32_t width, uint32_t height)
7704 {
7705         struct drm_device *dev = crtc->dev;
7706         struct drm_i915_private *dev_priv = dev->dev_private;
7707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7708         struct drm_i915_gem_object *obj;
7709         unsigned old_width;
7710         uint32_t addr;
7711         int ret;
7712
7713         /* if we want to turn off the cursor ignore width and height */
7714         if (!handle) {
7715                 DRM_DEBUG_KMS("cursor off\n");
7716                 addr = 0;
7717                 obj = NULL;
7718                 mutex_lock(&dev->struct_mutex);
7719                 goto finish;
7720         }
7721
7722         /* Check for which cursor types we support */
7723         if (!((width == 64 && height == 64) ||
7724                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7725                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7726                 DRM_DEBUG("Cursor dimension not supported\n");
7727                 return -EINVAL;
7728         }
7729
7730         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7731         if (&obj->base == NULL)
7732                 return -ENOENT;
7733
7734         if (obj->base.size < width * height * 4) {
7735                 DRM_DEBUG_KMS("buffer is to small\n");
7736                 ret = -ENOMEM;
7737                 goto fail;
7738         }
7739
7740         /* we only need to pin inside GTT if cursor is non-phy */
7741         mutex_lock(&dev->struct_mutex);
7742         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7743                 unsigned alignment;
7744
7745                 if (obj->tiling_mode) {
7746                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7747                         ret = -EINVAL;
7748                         goto fail_locked;
7749                 }
7750
7751                 /* Note that the w/a also requires 2 PTE of padding following
7752                  * the bo. We currently fill all unused PTE with the shadow
7753                  * page and so we should always have valid PTE following the
7754                  * cursor preventing the VT-d warning.
7755                  */
7756                 alignment = 0;
7757                 if (need_vtd_wa(dev))
7758                         alignment = 64*1024;
7759
7760                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7761                 if (ret) {
7762                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7763                         goto fail_locked;
7764                 }
7765
7766                 ret = i915_gem_object_put_fence(obj);
7767                 if (ret) {
7768                         DRM_DEBUG_KMS("failed to release fence for cursor");
7769                         goto fail_unpin;
7770                 }
7771
7772                 addr = i915_gem_obj_ggtt_offset(obj);
7773         } else {
7774                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7775                 ret = i915_gem_attach_phys_object(dev, obj,
7776                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7777                                                   align);
7778                 if (ret) {
7779                         DRM_DEBUG_KMS("failed to attach phys object\n");
7780                         goto fail_locked;
7781                 }
7782                 addr = obj->phys_obj->handle->busaddr;
7783         }
7784
7785         if (IS_GEN2(dev))
7786                 I915_WRITE(CURSIZE, (height << 12) | width);
7787
7788  finish:
7789         if (intel_crtc->cursor_bo) {
7790                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7791                         if (intel_crtc->cursor_bo != obj)
7792                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7793                 } else
7794                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7795                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7796         }
7797
7798         mutex_unlock(&dev->struct_mutex);
7799
7800         old_width = intel_crtc->cursor_width;
7801
7802         intel_crtc->cursor_addr = addr;
7803         intel_crtc->cursor_bo = obj;
7804         intel_crtc->cursor_width = width;
7805         intel_crtc->cursor_height = height;
7806
7807         if (intel_crtc->active) {
7808                 if (old_width != width)
7809                         intel_update_watermarks(crtc);
7810                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7811         }
7812
7813         return 0;
7814 fail_unpin:
7815         i915_gem_object_unpin_from_display_plane(obj);
7816 fail_locked:
7817         mutex_unlock(&dev->struct_mutex);
7818 fail:
7819         drm_gem_object_unreference_unlocked(&obj->base);
7820         return ret;
7821 }
7822
7823 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7824 {
7825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7826
7827         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7828         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7829
7830         if (intel_crtc->active)
7831                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7832
7833         return 0;
7834 }
7835
7836 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7837                                  u16 *blue, uint32_t start, uint32_t size)
7838 {
7839         int end = (start + size > 256) ? 256 : start + size, i;
7840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7841
7842         for (i = start; i < end; i++) {
7843                 intel_crtc->lut_r[i] = red[i] >> 8;
7844                 intel_crtc->lut_g[i] = green[i] >> 8;
7845                 intel_crtc->lut_b[i] = blue[i] >> 8;
7846         }
7847
7848         intel_crtc_load_lut(crtc);
7849 }
7850
7851 /* VESA 640x480x72Hz mode to set on the pipe */
7852 static struct drm_display_mode load_detect_mode = {
7853         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7854                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7855 };
7856
7857 struct drm_framebuffer *
7858 __intel_framebuffer_create(struct drm_device *dev,
7859                            struct drm_mode_fb_cmd2 *mode_cmd,
7860                            struct drm_i915_gem_object *obj)
7861 {
7862         struct intel_framebuffer *intel_fb;
7863         int ret;
7864
7865         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7866         if (!intel_fb) {
7867                 drm_gem_object_unreference_unlocked(&obj->base);
7868                 return ERR_PTR(-ENOMEM);
7869         }
7870
7871         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7872         if (ret)
7873                 goto err;
7874
7875         return &intel_fb->base;
7876 err:
7877         drm_gem_object_unreference_unlocked(&obj->base);
7878         kfree(intel_fb);
7879
7880         return ERR_PTR(ret);
7881 }
7882
7883 static struct drm_framebuffer *
7884 intel_framebuffer_create(struct drm_device *dev,
7885                          struct drm_mode_fb_cmd2 *mode_cmd,
7886                          struct drm_i915_gem_object *obj)
7887 {
7888         struct drm_framebuffer *fb;
7889         int ret;
7890
7891         ret = i915_mutex_lock_interruptible(dev);
7892         if (ret)
7893                 return ERR_PTR(ret);
7894         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7895         mutex_unlock(&dev->struct_mutex);
7896
7897         return fb;
7898 }
7899
7900 static u32
7901 intel_framebuffer_pitch_for_width(int width, int bpp)
7902 {
7903         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7904         return ALIGN(pitch, 64);
7905 }
7906
7907 static u32
7908 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7909 {
7910         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7911         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7912 }
7913
7914 static struct drm_framebuffer *
7915 intel_framebuffer_create_for_mode(struct drm_device *dev,
7916                                   struct drm_display_mode *mode,
7917                                   int depth, int bpp)
7918 {
7919         struct drm_i915_gem_object *obj;
7920         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7921
7922         obj = i915_gem_alloc_object(dev,
7923                                     intel_framebuffer_size_for_mode(mode, bpp));
7924         if (obj == NULL)
7925                 return ERR_PTR(-ENOMEM);
7926
7927         mode_cmd.width = mode->hdisplay;
7928         mode_cmd.height = mode->vdisplay;
7929         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7930                                                                 bpp);
7931         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7932
7933         return intel_framebuffer_create(dev, &mode_cmd, obj);
7934 }
7935
7936 static struct drm_framebuffer *
7937 mode_fits_in_fbdev(struct drm_device *dev,
7938                    struct drm_display_mode *mode)
7939 {
7940 #ifdef CONFIG_DRM_I915_FBDEV
7941         struct drm_i915_private *dev_priv = dev->dev_private;
7942         struct drm_i915_gem_object *obj;
7943         struct drm_framebuffer *fb;
7944
7945         if (!dev_priv->fbdev)
7946                 return NULL;
7947
7948         if (!dev_priv->fbdev->fb)
7949                 return NULL;
7950
7951         obj = dev_priv->fbdev->fb->obj;
7952         BUG_ON(!obj);
7953
7954         fb = &dev_priv->fbdev->fb->base;
7955         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7956                                                                fb->bits_per_pixel))
7957                 return NULL;
7958
7959         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7960                 return NULL;
7961
7962         return fb;
7963 #else
7964         return NULL;
7965 #endif
7966 }
7967
7968 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7969                                 struct drm_display_mode *mode,
7970                                 struct intel_load_detect_pipe *old)
7971 {
7972         struct intel_crtc *intel_crtc;
7973         struct intel_encoder *intel_encoder =
7974                 intel_attached_encoder(connector);
7975         struct drm_crtc *possible_crtc;
7976         struct drm_encoder *encoder = &intel_encoder->base;
7977         struct drm_crtc *crtc = NULL;
7978         struct drm_device *dev = encoder->dev;
7979         struct drm_framebuffer *fb;
7980         int i = -1;
7981
7982         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7983                       connector->base.id, drm_get_connector_name(connector),
7984                       encoder->base.id, drm_get_encoder_name(encoder));
7985
7986         /*
7987          * Algorithm gets a little messy:
7988          *
7989          *   - if the connector already has an assigned crtc, use it (but make
7990          *     sure it's on first)
7991          *
7992          *   - try to find the first unused crtc that can drive this connector,
7993          *     and use that if we find one
7994          */
7995
7996         /* See if we already have a CRTC for this connector */
7997         if (encoder->crtc) {
7998                 crtc = encoder->crtc;
7999
8000                 mutex_lock(&crtc->mutex);
8001
8002                 old->dpms_mode = connector->dpms;
8003                 old->load_detect_temp = false;
8004
8005                 /* Make sure the crtc and connector are running */
8006                 if (connector->dpms != DRM_MODE_DPMS_ON)
8007                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8008
8009                 return true;
8010         }
8011
8012         /* Find an unused one (if possible) */
8013         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8014                 i++;
8015                 if (!(encoder->possible_crtcs & (1 << i)))
8016                         continue;
8017                 if (!possible_crtc->enabled) {
8018                         crtc = possible_crtc;
8019                         break;
8020                 }
8021         }
8022
8023         /*
8024          * If we didn't find an unused CRTC, don't use any.
8025          */
8026         if (!crtc) {
8027                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8028                 return false;
8029         }
8030
8031         mutex_lock(&crtc->mutex);
8032         intel_encoder->new_crtc = to_intel_crtc(crtc);
8033         to_intel_connector(connector)->new_encoder = intel_encoder;
8034
8035         intel_crtc = to_intel_crtc(crtc);
8036         intel_crtc->new_enabled = true;
8037         intel_crtc->new_config = &intel_crtc->config;
8038         old->dpms_mode = connector->dpms;
8039         old->load_detect_temp = true;
8040         old->release_fb = NULL;
8041
8042         if (!mode)
8043                 mode = &load_detect_mode;
8044
8045         /* We need a framebuffer large enough to accommodate all accesses
8046          * that the plane may generate whilst we perform load detection.
8047          * We can not rely on the fbcon either being present (we get called
8048          * during its initialisation to detect all boot displays, or it may
8049          * not even exist) or that it is large enough to satisfy the
8050          * requested mode.
8051          */
8052         fb = mode_fits_in_fbdev(dev, mode);
8053         if (fb == NULL) {
8054                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8055                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8056                 old->release_fb = fb;
8057         } else
8058                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8059         if (IS_ERR(fb)) {
8060                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8061                 goto fail;
8062         }
8063
8064         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8065                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8066                 if (old->release_fb)
8067                         old->release_fb->funcs->destroy(old->release_fb);
8068                 goto fail;
8069         }
8070
8071         /* let the connector get through one full cycle before testing */
8072         intel_wait_for_vblank(dev, intel_crtc->pipe);
8073         return true;
8074
8075  fail:
8076         intel_crtc->new_enabled = crtc->enabled;
8077         if (intel_crtc->new_enabled)
8078                 intel_crtc->new_config = &intel_crtc->config;
8079         else
8080                 intel_crtc->new_config = NULL;
8081         mutex_unlock(&crtc->mutex);
8082         return false;
8083 }
8084
8085 void intel_release_load_detect_pipe(struct drm_connector *connector,
8086                                     struct intel_load_detect_pipe *old)
8087 {
8088         struct intel_encoder *intel_encoder =
8089                 intel_attached_encoder(connector);
8090         struct drm_encoder *encoder = &intel_encoder->base;
8091         struct drm_crtc *crtc = encoder->crtc;
8092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8093
8094         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8095                       connector->base.id, drm_get_connector_name(connector),
8096                       encoder->base.id, drm_get_encoder_name(encoder));
8097
8098         if (old->load_detect_temp) {
8099                 to_intel_connector(connector)->new_encoder = NULL;
8100                 intel_encoder->new_crtc = NULL;
8101                 intel_crtc->new_enabled = false;
8102                 intel_crtc->new_config = NULL;
8103                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8104
8105                 if (old->release_fb) {
8106                         drm_framebuffer_unregister_private(old->release_fb);
8107                         drm_framebuffer_unreference(old->release_fb);
8108                 }
8109
8110                 mutex_unlock(&crtc->mutex);
8111                 return;
8112         }
8113
8114         /* Switch crtc and encoder back off if necessary */
8115         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8116                 connector->funcs->dpms(connector, old->dpms_mode);
8117
8118         mutex_unlock(&crtc->mutex);
8119 }
8120
8121 static int i9xx_pll_refclk(struct drm_device *dev,
8122                            const struct intel_crtc_config *pipe_config)
8123 {
8124         struct drm_i915_private *dev_priv = dev->dev_private;
8125         u32 dpll = pipe_config->dpll_hw_state.dpll;
8126
8127         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8128                 return dev_priv->vbt.lvds_ssc_freq;
8129         else if (HAS_PCH_SPLIT(dev))
8130                 return 120000;
8131         else if (!IS_GEN2(dev))
8132                 return 96000;
8133         else
8134                 return 48000;
8135 }
8136
8137 /* Returns the clock of the currently programmed mode of the given pipe. */
8138 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8139                                 struct intel_crtc_config *pipe_config)
8140 {
8141         struct drm_device *dev = crtc->base.dev;
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143         int pipe = pipe_config->cpu_transcoder;
8144         u32 dpll = pipe_config->dpll_hw_state.dpll;
8145         u32 fp;
8146         intel_clock_t clock;
8147         int refclk = i9xx_pll_refclk(dev, pipe_config);
8148
8149         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8150                 fp = pipe_config->dpll_hw_state.fp0;
8151         else
8152                 fp = pipe_config->dpll_hw_state.fp1;
8153
8154         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8155         if (IS_PINEVIEW(dev)) {
8156                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8157                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8158         } else {
8159                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8160                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8161         }
8162
8163         if (!IS_GEN2(dev)) {
8164                 if (IS_PINEVIEW(dev))
8165                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8166                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8167                 else
8168                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8169                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8170
8171                 switch (dpll & DPLL_MODE_MASK) {
8172                 case DPLLB_MODE_DAC_SERIAL:
8173                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8174                                 5 : 10;
8175                         break;
8176                 case DPLLB_MODE_LVDS:
8177                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8178                                 7 : 14;
8179                         break;
8180                 default:
8181                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8182                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8183                         return;
8184                 }
8185
8186                 if (IS_PINEVIEW(dev))
8187                         pineview_clock(refclk, &clock);
8188                 else
8189                         i9xx_clock(refclk, &clock);
8190         } else {
8191                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8192                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8193
8194                 if (is_lvds) {
8195                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8196                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8197
8198                         if (lvds & LVDS_CLKB_POWER_UP)
8199                                 clock.p2 = 7;
8200                         else
8201                                 clock.p2 = 14;
8202                 } else {
8203                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8204                                 clock.p1 = 2;
8205                         else {
8206                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8207                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8208                         }
8209                         if (dpll & PLL_P2_DIVIDE_BY_4)
8210                                 clock.p2 = 4;
8211                         else
8212                                 clock.p2 = 2;
8213                 }
8214
8215                 i9xx_clock(refclk, &clock);
8216         }
8217
8218         /*
8219          * This value includes pixel_multiplier. We will use
8220          * port_clock to compute adjusted_mode.crtc_clock in the
8221          * encoder's get_config() function.
8222          */
8223         pipe_config->port_clock = clock.dot;
8224 }
8225
8226 int intel_dotclock_calculate(int link_freq,
8227                              const struct intel_link_m_n *m_n)
8228 {
8229         /*
8230          * The calculation for the data clock is:
8231          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8232          * But we want to avoid losing precison if possible, so:
8233          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8234          *
8235          * and the link clock is simpler:
8236          * link_clock = (m * link_clock) / n
8237          */
8238
8239         if (!m_n->link_n)
8240                 return 0;
8241
8242         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8243 }
8244
8245 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8246                                    struct intel_crtc_config *pipe_config)
8247 {
8248         struct drm_device *dev = crtc->base.dev;
8249
8250         /* read out port_clock from the DPLL */
8251         i9xx_crtc_clock_get(crtc, pipe_config);
8252
8253         /*
8254          * This value does not include pixel_multiplier.
8255          * We will check that port_clock and adjusted_mode.crtc_clock
8256          * agree once we know their relationship in the encoder's
8257          * get_config() function.
8258          */
8259         pipe_config->adjusted_mode.crtc_clock =
8260                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8261                                          &pipe_config->fdi_m_n);
8262 }
8263
8264 /** Returns the currently programmed mode of the given pipe. */
8265 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8266                                              struct drm_crtc *crtc)
8267 {
8268         struct drm_i915_private *dev_priv = dev->dev_private;
8269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8270         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8271         struct drm_display_mode *mode;
8272         struct intel_crtc_config pipe_config;
8273         int htot = I915_READ(HTOTAL(cpu_transcoder));
8274         int hsync = I915_READ(HSYNC(cpu_transcoder));
8275         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8276         int vsync = I915_READ(VSYNC(cpu_transcoder));
8277         enum pipe pipe = intel_crtc->pipe;
8278
8279         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8280         if (!mode)
8281                 return NULL;
8282
8283         /*
8284          * Construct a pipe_config sufficient for getting the clock info
8285          * back out of crtc_clock_get.
8286          *
8287          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8288          * to use a real value here instead.
8289          */
8290         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8291         pipe_config.pixel_multiplier = 1;
8292         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8293         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8294         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8295         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8296
8297         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8298         mode->hdisplay = (htot & 0xffff) + 1;
8299         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8300         mode->hsync_start = (hsync & 0xffff) + 1;
8301         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8302         mode->vdisplay = (vtot & 0xffff) + 1;
8303         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8304         mode->vsync_start = (vsync & 0xffff) + 1;
8305         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8306
8307         drm_mode_set_name(mode);
8308
8309         return mode;
8310 }
8311
8312 static void intel_increase_pllclock(struct drm_crtc *crtc)
8313 {
8314         struct drm_device *dev = crtc->dev;
8315         struct drm_i915_private *dev_priv = dev->dev_private;
8316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8317         int pipe = intel_crtc->pipe;
8318         int dpll_reg = DPLL(pipe);
8319         int dpll;
8320
8321         if (HAS_PCH_SPLIT(dev))
8322                 return;
8323
8324         if (!dev_priv->lvds_downclock_avail)
8325                 return;
8326
8327         dpll = I915_READ(dpll_reg);
8328         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8329                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8330
8331                 assert_panel_unlocked(dev_priv, pipe);
8332
8333                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8334                 I915_WRITE(dpll_reg, dpll);
8335                 intel_wait_for_vblank(dev, pipe);
8336
8337                 dpll = I915_READ(dpll_reg);
8338                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8339                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8340         }
8341 }
8342
8343 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8344 {
8345         struct drm_device *dev = crtc->dev;
8346         struct drm_i915_private *dev_priv = dev->dev_private;
8347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8348
8349         if (HAS_PCH_SPLIT(dev))
8350                 return;
8351
8352         if (!dev_priv->lvds_downclock_avail)
8353                 return;
8354
8355         /*
8356          * Since this is called by a timer, we should never get here in
8357          * the manual case.
8358          */
8359         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8360                 int pipe = intel_crtc->pipe;
8361                 int dpll_reg = DPLL(pipe);
8362                 int dpll;
8363
8364                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8365
8366                 assert_panel_unlocked(dev_priv, pipe);
8367
8368                 dpll = I915_READ(dpll_reg);
8369                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8370                 I915_WRITE(dpll_reg, dpll);
8371                 intel_wait_for_vblank(dev, pipe);
8372                 dpll = I915_READ(dpll_reg);
8373                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8374                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8375         }
8376
8377 }
8378
8379 void intel_mark_busy(struct drm_device *dev)
8380 {
8381         struct drm_i915_private *dev_priv = dev->dev_private;
8382
8383         if (dev_priv->mm.busy)
8384                 return;
8385
8386         intel_runtime_pm_get(dev_priv);
8387         i915_update_gfx_val(dev_priv);
8388         dev_priv->mm.busy = true;
8389 }
8390
8391 void intel_mark_idle(struct drm_device *dev)
8392 {
8393         struct drm_i915_private *dev_priv = dev->dev_private;
8394         struct drm_crtc *crtc;
8395
8396         if (!dev_priv->mm.busy)
8397                 return;
8398
8399         dev_priv->mm.busy = false;
8400
8401         if (!i915.powersave)
8402                 goto out;
8403
8404         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8405                 if (!crtc->primary->fb)
8406                         continue;
8407
8408                 intel_decrease_pllclock(crtc);
8409         }
8410
8411         if (INTEL_INFO(dev)->gen >= 6)
8412                 gen6_rps_idle(dev->dev_private);
8413
8414 out:
8415         intel_runtime_pm_put(dev_priv);
8416 }
8417
8418 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8419                         struct intel_ring_buffer *ring)
8420 {
8421         struct drm_device *dev = obj->base.dev;
8422         struct drm_crtc *crtc;
8423
8424         if (!i915.powersave)
8425                 return;
8426
8427         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8428                 if (!crtc->primary->fb)
8429                         continue;
8430
8431                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8432                         continue;
8433
8434                 intel_increase_pllclock(crtc);
8435                 if (ring && intel_fbc_enabled(dev))
8436                         ring->fbc_dirty = true;
8437         }
8438 }
8439
8440 static void intel_crtc_destroy(struct drm_crtc *crtc)
8441 {
8442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8443         struct drm_device *dev = crtc->dev;
8444         struct intel_unpin_work *work;
8445         unsigned long flags;
8446
8447         spin_lock_irqsave(&dev->event_lock, flags);
8448         work = intel_crtc->unpin_work;
8449         intel_crtc->unpin_work = NULL;
8450         spin_unlock_irqrestore(&dev->event_lock, flags);
8451
8452         if (work) {
8453                 cancel_work_sync(&work->work);
8454                 kfree(work);
8455         }
8456
8457         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8458
8459         drm_crtc_cleanup(crtc);
8460
8461         kfree(intel_crtc);
8462 }
8463
8464 static void intel_unpin_work_fn(struct work_struct *__work)
8465 {
8466         struct intel_unpin_work *work =
8467                 container_of(__work, struct intel_unpin_work, work);
8468         struct drm_device *dev = work->crtc->dev;
8469
8470         mutex_lock(&dev->struct_mutex);
8471         intel_unpin_fb_obj(work->old_fb_obj);
8472         drm_gem_object_unreference(&work->pending_flip_obj->base);
8473         drm_gem_object_unreference(&work->old_fb_obj->base);
8474
8475         intel_update_fbc(dev);
8476         mutex_unlock(&dev->struct_mutex);
8477
8478         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8479         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8480
8481         kfree(work);
8482 }
8483
8484 static void do_intel_finish_page_flip(struct drm_device *dev,
8485                                       struct drm_crtc *crtc)
8486 {
8487         struct drm_i915_private *dev_priv = dev->dev_private;
8488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8489         struct intel_unpin_work *work;
8490         unsigned long flags;
8491
8492         /* Ignore early vblank irqs */
8493         if (intel_crtc == NULL)
8494                 return;
8495
8496         spin_lock_irqsave(&dev->event_lock, flags);
8497         work = intel_crtc->unpin_work;
8498
8499         /* Ensure we don't miss a work->pending update ... */
8500         smp_rmb();
8501
8502         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8503                 spin_unlock_irqrestore(&dev->event_lock, flags);
8504                 return;
8505         }
8506
8507         /* and that the unpin work is consistent wrt ->pending. */
8508         smp_rmb();
8509
8510         intel_crtc->unpin_work = NULL;
8511
8512         if (work->event)
8513                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8514
8515         drm_vblank_put(dev, intel_crtc->pipe);
8516
8517         spin_unlock_irqrestore(&dev->event_lock, flags);
8518
8519         wake_up_all(&dev_priv->pending_flip_queue);
8520
8521         queue_work(dev_priv->wq, &work->work);
8522
8523         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8524 }
8525
8526 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8527 {
8528         struct drm_i915_private *dev_priv = dev->dev_private;
8529         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8530
8531         do_intel_finish_page_flip(dev, crtc);
8532 }
8533
8534 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8535 {
8536         struct drm_i915_private *dev_priv = dev->dev_private;
8537         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8538
8539         do_intel_finish_page_flip(dev, crtc);
8540 }
8541
8542 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8543 {
8544         struct drm_i915_private *dev_priv = dev->dev_private;
8545         struct intel_crtc *intel_crtc =
8546                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8547         unsigned long flags;
8548
8549         /* NB: An MMIO update of the plane base pointer will also
8550          * generate a page-flip completion irq, i.e. every modeset
8551          * is also accompanied by a spurious intel_prepare_page_flip().
8552          */
8553         spin_lock_irqsave(&dev->event_lock, flags);
8554         if (intel_crtc->unpin_work)
8555                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8556         spin_unlock_irqrestore(&dev->event_lock, flags);
8557 }
8558
8559 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8560 {
8561         /* Ensure that the work item is consistent when activating it ... */
8562         smp_wmb();
8563         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8564         /* and that it is marked active as soon as the irq could fire. */
8565         smp_wmb();
8566 }
8567
8568 static int intel_gen2_queue_flip(struct drm_device *dev,
8569                                  struct drm_crtc *crtc,
8570                                  struct drm_framebuffer *fb,
8571                                  struct drm_i915_gem_object *obj,
8572                                  uint32_t flags)
8573 {
8574         struct drm_i915_private *dev_priv = dev->dev_private;
8575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8576         u32 flip_mask;
8577         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8578         int ret;
8579
8580         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8581         if (ret)
8582                 goto err;
8583
8584         ret = intel_ring_begin(ring, 6);
8585         if (ret)
8586                 goto err_unpin;
8587
8588         /* Can't queue multiple flips, so wait for the previous
8589          * one to finish before executing the next.
8590          */
8591         if (intel_crtc->plane)
8592                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8593         else
8594                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8595         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8596         intel_ring_emit(ring, MI_NOOP);
8597         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8598                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8599         intel_ring_emit(ring, fb->pitches[0]);
8600         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8601         intel_ring_emit(ring, 0); /* aux display base address, unused */
8602
8603         intel_mark_page_flip_active(intel_crtc);
8604         __intel_ring_advance(ring);
8605         return 0;
8606
8607 err_unpin:
8608         intel_unpin_fb_obj(obj);
8609 err:
8610         return ret;
8611 }
8612
8613 static int intel_gen3_queue_flip(struct drm_device *dev,
8614                                  struct drm_crtc *crtc,
8615                                  struct drm_framebuffer *fb,
8616                                  struct drm_i915_gem_object *obj,
8617                                  uint32_t flags)
8618 {
8619         struct drm_i915_private *dev_priv = dev->dev_private;
8620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8621         u32 flip_mask;
8622         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8623         int ret;
8624
8625         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8626         if (ret)
8627                 goto err;
8628
8629         ret = intel_ring_begin(ring, 6);
8630         if (ret)
8631                 goto err_unpin;
8632
8633         if (intel_crtc->plane)
8634                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8635         else
8636                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8637         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8638         intel_ring_emit(ring, MI_NOOP);
8639         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8640                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8641         intel_ring_emit(ring, fb->pitches[0]);
8642         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8643         intel_ring_emit(ring, MI_NOOP);
8644
8645         intel_mark_page_flip_active(intel_crtc);
8646         __intel_ring_advance(ring);
8647         return 0;
8648
8649 err_unpin:
8650         intel_unpin_fb_obj(obj);
8651 err:
8652         return ret;
8653 }
8654
8655 static int intel_gen4_queue_flip(struct drm_device *dev,
8656                                  struct drm_crtc *crtc,
8657                                  struct drm_framebuffer *fb,
8658                                  struct drm_i915_gem_object *obj,
8659                                  uint32_t flags)
8660 {
8661         struct drm_i915_private *dev_priv = dev->dev_private;
8662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8663         uint32_t pf, pipesrc;
8664         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8665         int ret;
8666
8667         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8668         if (ret)
8669                 goto err;
8670
8671         ret = intel_ring_begin(ring, 4);
8672         if (ret)
8673                 goto err_unpin;
8674
8675         /* i965+ uses the linear or tiled offsets from the
8676          * Display Registers (which do not change across a page-flip)
8677          * so we need only reprogram the base address.
8678          */
8679         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8680                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8681         intel_ring_emit(ring, fb->pitches[0]);
8682         intel_ring_emit(ring,
8683                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8684                         obj->tiling_mode);
8685
8686         /* XXX Enabling the panel-fitter across page-flip is so far
8687          * untested on non-native modes, so ignore it for now.
8688          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8689          */
8690         pf = 0;
8691         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8692         intel_ring_emit(ring, pf | pipesrc);
8693
8694         intel_mark_page_flip_active(intel_crtc);
8695         __intel_ring_advance(ring);
8696         return 0;
8697
8698 err_unpin:
8699         intel_unpin_fb_obj(obj);
8700 err:
8701         return ret;
8702 }
8703
8704 static int intel_gen6_queue_flip(struct drm_device *dev,
8705                                  struct drm_crtc *crtc,
8706                                  struct drm_framebuffer *fb,
8707                                  struct drm_i915_gem_object *obj,
8708                                  uint32_t flags)
8709 {
8710         struct drm_i915_private *dev_priv = dev->dev_private;
8711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8712         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8713         uint32_t pf, pipesrc;
8714         int ret;
8715
8716         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8717         if (ret)
8718                 goto err;
8719
8720         ret = intel_ring_begin(ring, 4);
8721         if (ret)
8722                 goto err_unpin;
8723
8724         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8725                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8726         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8727         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8728
8729         /* Contrary to the suggestions in the documentation,
8730          * "Enable Panel Fitter" does not seem to be required when page
8731          * flipping with a non-native mode, and worse causes a normal
8732          * modeset to fail.
8733          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8734          */
8735         pf = 0;
8736         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8737         intel_ring_emit(ring, pf | pipesrc);
8738
8739         intel_mark_page_flip_active(intel_crtc);
8740         __intel_ring_advance(ring);
8741         return 0;
8742
8743 err_unpin:
8744         intel_unpin_fb_obj(obj);
8745 err:
8746         return ret;
8747 }
8748
8749 static int intel_gen7_queue_flip(struct drm_device *dev,
8750                                  struct drm_crtc *crtc,
8751                                  struct drm_framebuffer *fb,
8752                                  struct drm_i915_gem_object *obj,
8753                                  uint32_t flags)
8754 {
8755         struct drm_i915_private *dev_priv = dev->dev_private;
8756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8757         struct intel_ring_buffer *ring;
8758         uint32_t plane_bit = 0;
8759         int len, ret;
8760
8761         ring = obj->ring;
8762         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8763                 ring = &dev_priv->ring[BCS];
8764
8765         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8766         if (ret)
8767                 goto err;
8768
8769         switch(intel_crtc->plane) {
8770         case PLANE_A:
8771                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8772                 break;
8773         case PLANE_B:
8774                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8775                 break;
8776         case PLANE_C:
8777                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8778                 break;
8779         default:
8780                 WARN_ONCE(1, "unknown plane in flip command\n");
8781                 ret = -ENODEV;
8782                 goto err_unpin;
8783         }
8784
8785         len = 4;
8786         if (ring->id == RCS) {
8787                 len += 6;
8788                 /*
8789                  * On Gen 8, SRM is now taking an extra dword to accommodate
8790                  * 48bits addresses, and we need a NOOP for the batch size to
8791                  * stay even.
8792                  */
8793                 if (IS_GEN8(dev))
8794                         len += 2;
8795         }
8796
8797         /*
8798          * BSpec MI_DISPLAY_FLIP for IVB:
8799          * "The full packet must be contained within the same cache line."
8800          *
8801          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8802          * cacheline, if we ever start emitting more commands before
8803          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8804          * then do the cacheline alignment, and finally emit the
8805          * MI_DISPLAY_FLIP.
8806          */
8807         ret = intel_ring_cacheline_align(ring);
8808         if (ret)
8809                 goto err_unpin;
8810
8811         ret = intel_ring_begin(ring, len);
8812         if (ret)
8813                 goto err_unpin;
8814
8815         /* Unmask the flip-done completion message. Note that the bspec says that
8816          * we should do this for both the BCS and RCS, and that we must not unmask
8817          * more than one flip event at any time (or ensure that one flip message
8818          * can be sent by waiting for flip-done prior to queueing new flips).
8819          * Experimentation says that BCS works despite DERRMR masking all
8820          * flip-done completion events and that unmasking all planes at once
8821          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8822          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8823          */
8824         if (ring->id == RCS) {
8825                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8826                 intel_ring_emit(ring, DERRMR);
8827                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8828                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8829                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8830                 if (IS_GEN8(dev))
8831                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8832                                               MI_SRM_LRM_GLOBAL_GTT);
8833                 else
8834                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8835                                               MI_SRM_LRM_GLOBAL_GTT);
8836                 intel_ring_emit(ring, DERRMR);
8837                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8838                 if (IS_GEN8(dev)) {
8839                         intel_ring_emit(ring, 0);
8840                         intel_ring_emit(ring, MI_NOOP);
8841                 }
8842         }
8843
8844         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8845         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8846         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8847         intel_ring_emit(ring, (MI_NOOP));
8848
8849         intel_mark_page_flip_active(intel_crtc);
8850         __intel_ring_advance(ring);
8851         return 0;
8852
8853 err_unpin:
8854         intel_unpin_fb_obj(obj);
8855 err:
8856         return ret;
8857 }
8858
8859 static int intel_default_queue_flip(struct drm_device *dev,
8860                                     struct drm_crtc *crtc,
8861                                     struct drm_framebuffer *fb,
8862                                     struct drm_i915_gem_object *obj,
8863                                     uint32_t flags)
8864 {
8865         return -ENODEV;
8866 }
8867
8868 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8869                                 struct drm_framebuffer *fb,
8870                                 struct drm_pending_vblank_event *event,
8871                                 uint32_t page_flip_flags)
8872 {
8873         struct drm_device *dev = crtc->dev;
8874         struct drm_i915_private *dev_priv = dev->dev_private;
8875         struct drm_framebuffer *old_fb = crtc->primary->fb;
8876         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8878         struct intel_unpin_work *work;
8879         unsigned long flags;
8880         int ret;
8881
8882         /* Can't change pixel format via MI display flips. */
8883         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8884                 return -EINVAL;
8885
8886         /*
8887          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8888          * Note that pitch changes could also affect these register.
8889          */
8890         if (INTEL_INFO(dev)->gen > 3 &&
8891             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8892              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8893                 return -EINVAL;
8894
8895         if (i915_terminally_wedged(&dev_priv->gpu_error))
8896                 goto out_hang;
8897
8898         work = kzalloc(sizeof(*work), GFP_KERNEL);
8899         if (work == NULL)
8900                 return -ENOMEM;
8901
8902         work->event = event;
8903         work->crtc = crtc;
8904         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8905         INIT_WORK(&work->work, intel_unpin_work_fn);
8906
8907         ret = drm_vblank_get(dev, intel_crtc->pipe);
8908         if (ret)
8909                 goto free_work;
8910
8911         /* We borrow the event spin lock for protecting unpin_work */
8912         spin_lock_irqsave(&dev->event_lock, flags);
8913         if (intel_crtc->unpin_work) {
8914                 spin_unlock_irqrestore(&dev->event_lock, flags);
8915                 kfree(work);
8916                 drm_vblank_put(dev, intel_crtc->pipe);
8917
8918                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8919                 return -EBUSY;
8920         }
8921         intel_crtc->unpin_work = work;
8922         spin_unlock_irqrestore(&dev->event_lock, flags);
8923
8924         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8925                 flush_workqueue(dev_priv->wq);
8926
8927         ret = i915_mutex_lock_interruptible(dev);
8928         if (ret)
8929                 goto cleanup;
8930
8931         /* Reference the objects for the scheduled work. */
8932         drm_gem_object_reference(&work->old_fb_obj->base);
8933         drm_gem_object_reference(&obj->base);
8934
8935         crtc->primary->fb = fb;
8936
8937         work->pending_flip_obj = obj;
8938
8939         work->enable_stall_check = true;
8940
8941         atomic_inc(&intel_crtc->unpin_work_count);
8942         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8943
8944         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8945         if (ret)
8946                 goto cleanup_pending;
8947
8948         intel_disable_fbc(dev);
8949         intel_mark_fb_busy(obj, NULL);
8950         mutex_unlock(&dev->struct_mutex);
8951
8952         trace_i915_flip_request(intel_crtc->plane, obj);
8953
8954         return 0;
8955
8956 cleanup_pending:
8957         atomic_dec(&intel_crtc->unpin_work_count);
8958         crtc->primary->fb = old_fb;
8959         drm_gem_object_unreference(&work->old_fb_obj->base);
8960         drm_gem_object_unreference(&obj->base);
8961         mutex_unlock(&dev->struct_mutex);
8962
8963 cleanup:
8964         spin_lock_irqsave(&dev->event_lock, flags);
8965         intel_crtc->unpin_work = NULL;
8966         spin_unlock_irqrestore(&dev->event_lock, flags);
8967
8968         drm_vblank_put(dev, intel_crtc->pipe);
8969 free_work:
8970         kfree(work);
8971
8972         if (ret == -EIO) {
8973 out_hang:
8974                 intel_crtc_wait_for_pending_flips(crtc);
8975                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8976                 if (ret == 0 && event)
8977                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8978         }
8979         return ret;
8980 }
8981
8982 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8983         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8984         .load_lut = intel_crtc_load_lut,
8985 };
8986
8987 /**
8988  * intel_modeset_update_staged_output_state
8989  *
8990  * Updates the staged output configuration state, e.g. after we've read out the
8991  * current hw state.
8992  */
8993 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8994 {
8995         struct intel_crtc *crtc;
8996         struct intel_encoder *encoder;
8997         struct intel_connector *connector;
8998
8999         list_for_each_entry(connector, &dev->mode_config.connector_list,
9000                             base.head) {
9001                 connector->new_encoder =
9002                         to_intel_encoder(connector->base.encoder);
9003         }
9004
9005         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9006                             base.head) {
9007                 encoder->new_crtc =
9008                         to_intel_crtc(encoder->base.crtc);
9009         }
9010
9011         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9012                             base.head) {
9013                 crtc->new_enabled = crtc->base.enabled;
9014
9015                 if (crtc->new_enabled)
9016                         crtc->new_config = &crtc->config;
9017                 else
9018                         crtc->new_config = NULL;
9019         }
9020 }
9021
9022 /**
9023  * intel_modeset_commit_output_state
9024  *
9025  * This function copies the stage display pipe configuration to the real one.
9026  */
9027 static void intel_modeset_commit_output_state(struct drm_device *dev)
9028 {
9029         struct intel_crtc *crtc;
9030         struct intel_encoder *encoder;
9031         struct intel_connector *connector;
9032
9033         list_for_each_entry(connector, &dev->mode_config.connector_list,
9034                             base.head) {
9035                 connector->base.encoder = &connector->new_encoder->base;
9036         }
9037
9038         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9039                             base.head) {
9040                 encoder->base.crtc = &encoder->new_crtc->base;
9041         }
9042
9043         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9044                             base.head) {
9045                 crtc->base.enabled = crtc->new_enabled;
9046         }
9047 }
9048
9049 static void
9050 connected_sink_compute_bpp(struct intel_connector * connector,
9051                            struct intel_crtc_config *pipe_config)
9052 {
9053         int bpp = pipe_config->pipe_bpp;
9054
9055         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9056                 connector->base.base.id,
9057                 drm_get_connector_name(&connector->base));
9058
9059         /* Don't use an invalid EDID bpc value */
9060         if (connector->base.display_info.bpc &&
9061             connector->base.display_info.bpc * 3 < bpp) {
9062                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9063                               bpp, connector->base.display_info.bpc*3);
9064                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9065         }
9066
9067         /* Clamp bpp to 8 on screens without EDID 1.4 */
9068         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9069                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9070                               bpp);
9071                 pipe_config->pipe_bpp = 24;
9072         }
9073 }
9074
9075 static int
9076 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9077                           struct drm_framebuffer *fb,
9078                           struct intel_crtc_config *pipe_config)
9079 {
9080         struct drm_device *dev = crtc->base.dev;
9081         struct intel_connector *connector;
9082         int bpp;
9083
9084         switch (fb->pixel_format) {
9085         case DRM_FORMAT_C8:
9086                 bpp = 8*3; /* since we go through a colormap */
9087                 break;
9088         case DRM_FORMAT_XRGB1555:
9089         case DRM_FORMAT_ARGB1555:
9090                 /* checked in intel_framebuffer_init already */
9091                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9092                         return -EINVAL;
9093         case DRM_FORMAT_RGB565:
9094                 bpp = 6*3; /* min is 18bpp */
9095                 break;
9096         case DRM_FORMAT_XBGR8888:
9097         case DRM_FORMAT_ABGR8888:
9098                 /* checked in intel_framebuffer_init already */
9099                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9100                         return -EINVAL;
9101         case DRM_FORMAT_XRGB8888:
9102         case DRM_FORMAT_ARGB8888:
9103                 bpp = 8*3;
9104                 break;
9105         case DRM_FORMAT_XRGB2101010:
9106         case DRM_FORMAT_ARGB2101010:
9107         case DRM_FORMAT_XBGR2101010:
9108         case DRM_FORMAT_ABGR2101010:
9109                 /* checked in intel_framebuffer_init already */
9110                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9111                         return -EINVAL;
9112                 bpp = 10*3;
9113                 break;
9114         /* TODO: gen4+ supports 16 bpc floating point, too. */
9115         default:
9116                 DRM_DEBUG_KMS("unsupported depth\n");
9117                 return -EINVAL;
9118         }
9119
9120         pipe_config->pipe_bpp = bpp;
9121
9122         /* Clamp display bpp to EDID value */
9123         list_for_each_entry(connector, &dev->mode_config.connector_list,
9124                             base.head) {
9125                 if (!connector->new_encoder ||
9126                     connector->new_encoder->new_crtc != crtc)
9127                         continue;
9128
9129                 connected_sink_compute_bpp(connector, pipe_config);
9130         }
9131
9132         return bpp;
9133 }
9134
9135 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9136 {
9137         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9138                         "type: 0x%x flags: 0x%x\n",
9139                 mode->crtc_clock,
9140                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9141                 mode->crtc_hsync_end, mode->crtc_htotal,
9142                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9143                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9144 }
9145
9146 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9147                                    struct intel_crtc_config *pipe_config,
9148                                    const char *context)
9149 {
9150         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9151                       context, pipe_name(crtc->pipe));
9152
9153         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9154         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9155                       pipe_config->pipe_bpp, pipe_config->dither);
9156         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9157                       pipe_config->has_pch_encoder,
9158                       pipe_config->fdi_lanes,
9159                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9160                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9161                       pipe_config->fdi_m_n.tu);
9162         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9163                       pipe_config->has_dp_encoder,
9164                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9165                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9166                       pipe_config->dp_m_n.tu);
9167         DRM_DEBUG_KMS("requested mode:\n");
9168         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9169         DRM_DEBUG_KMS("adjusted mode:\n");
9170         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9171         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9172         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9173         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9174                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9175         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9176                       pipe_config->gmch_pfit.control,
9177                       pipe_config->gmch_pfit.pgm_ratios,
9178                       pipe_config->gmch_pfit.lvds_border_bits);
9179         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9180                       pipe_config->pch_pfit.pos,
9181                       pipe_config->pch_pfit.size,
9182                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9183         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9184         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9185 }
9186
9187 static bool encoders_cloneable(const struct intel_encoder *a,
9188                                const struct intel_encoder *b)
9189 {
9190         /* masks could be asymmetric, so check both ways */
9191         return a == b || (a->cloneable & (1 << b->type) &&
9192                           b->cloneable & (1 << a->type));
9193 }
9194
9195 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9196                                          struct intel_encoder *encoder)
9197 {
9198         struct drm_device *dev = crtc->base.dev;
9199         struct intel_encoder *source_encoder;
9200
9201         list_for_each_entry(source_encoder,
9202                             &dev->mode_config.encoder_list, base.head) {
9203                 if (source_encoder->new_crtc != crtc)
9204                         continue;
9205
9206                 if (!encoders_cloneable(encoder, source_encoder))
9207                         return false;
9208         }
9209
9210         return true;
9211 }
9212
9213 static bool check_encoder_cloning(struct intel_crtc *crtc)
9214 {
9215         struct drm_device *dev = crtc->base.dev;
9216         struct intel_encoder *encoder;
9217
9218         list_for_each_entry(encoder,
9219                             &dev->mode_config.encoder_list, base.head) {
9220                 if (encoder->new_crtc != crtc)
9221                         continue;
9222
9223                 if (!check_single_encoder_cloning(crtc, encoder))
9224                         return false;
9225         }
9226
9227         return true;
9228 }
9229
9230 static struct intel_crtc_config *
9231 intel_modeset_pipe_config(struct drm_crtc *crtc,
9232                           struct drm_framebuffer *fb,
9233                           struct drm_display_mode *mode)
9234 {
9235         struct drm_device *dev = crtc->dev;
9236         struct intel_encoder *encoder;
9237         struct intel_crtc_config *pipe_config;
9238         int plane_bpp, ret = -EINVAL;
9239         bool retry = true;
9240
9241         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9242                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9243                 return ERR_PTR(-EINVAL);
9244         }
9245
9246         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9247         if (!pipe_config)
9248                 return ERR_PTR(-ENOMEM);
9249
9250         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9251         drm_mode_copy(&pipe_config->requested_mode, mode);
9252
9253         pipe_config->cpu_transcoder =
9254                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9255         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9256
9257         /*
9258          * Sanitize sync polarity flags based on requested ones. If neither
9259          * positive or negative polarity is requested, treat this as meaning
9260          * negative polarity.
9261          */
9262         if (!(pipe_config->adjusted_mode.flags &
9263               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9264                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9265
9266         if (!(pipe_config->adjusted_mode.flags &
9267               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9268                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9269
9270         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9271          * plane pixel format and any sink constraints into account. Returns the
9272          * source plane bpp so that dithering can be selected on mismatches
9273          * after encoders and crtc also have had their say. */
9274         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9275                                               fb, pipe_config);
9276         if (plane_bpp < 0)
9277                 goto fail;
9278
9279         /*
9280          * Determine the real pipe dimensions. Note that stereo modes can
9281          * increase the actual pipe size due to the frame doubling and
9282          * insertion of additional space for blanks between the frame. This
9283          * is stored in the crtc timings. We use the requested mode to do this
9284          * computation to clearly distinguish it from the adjusted mode, which
9285          * can be changed by the connectors in the below retry loop.
9286          */
9287         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9288         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9289         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9290
9291 encoder_retry:
9292         /* Ensure the port clock defaults are reset when retrying. */
9293         pipe_config->port_clock = 0;
9294         pipe_config->pixel_multiplier = 1;
9295
9296         /* Fill in default crtc timings, allow encoders to overwrite them. */
9297         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9298
9299         /* Pass our mode to the connectors and the CRTC to give them a chance to
9300          * adjust it according to limitations or connector properties, and also
9301          * a chance to reject the mode entirely.
9302          */
9303         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9304                             base.head) {
9305
9306                 if (&encoder->new_crtc->base != crtc)
9307                         continue;
9308
9309                 if (!(encoder->compute_config(encoder, pipe_config))) {
9310                         DRM_DEBUG_KMS("Encoder config failure\n");
9311                         goto fail;
9312                 }
9313         }
9314
9315         /* Set default port clock if not overwritten by the encoder. Needs to be
9316          * done afterwards in case the encoder adjusts the mode. */
9317         if (!pipe_config->port_clock)
9318                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9319                         * pipe_config->pixel_multiplier;
9320
9321         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9322         if (ret < 0) {
9323                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9324                 goto fail;
9325         }
9326
9327         if (ret == RETRY) {
9328                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9329                         ret = -EINVAL;
9330                         goto fail;
9331                 }
9332
9333                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9334                 retry = false;
9335                 goto encoder_retry;
9336         }
9337
9338         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9339         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9340                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9341
9342         return pipe_config;
9343 fail:
9344         kfree(pipe_config);
9345         return ERR_PTR(ret);
9346 }
9347
9348 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9349  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9350 static void
9351 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9352                              unsigned *prepare_pipes, unsigned *disable_pipes)
9353 {
9354         struct intel_crtc *intel_crtc;
9355         struct drm_device *dev = crtc->dev;
9356         struct intel_encoder *encoder;
9357         struct intel_connector *connector;
9358         struct drm_crtc *tmp_crtc;
9359
9360         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9361
9362         /* Check which crtcs have changed outputs connected to them, these need
9363          * to be part of the prepare_pipes mask. We don't (yet) support global
9364          * modeset across multiple crtcs, so modeset_pipes will only have one
9365          * bit set at most. */
9366         list_for_each_entry(connector, &dev->mode_config.connector_list,
9367                             base.head) {
9368                 if (connector->base.encoder == &connector->new_encoder->base)
9369                         continue;
9370
9371                 if (connector->base.encoder) {
9372                         tmp_crtc = connector->base.encoder->crtc;
9373
9374                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9375                 }
9376
9377                 if (connector->new_encoder)
9378                         *prepare_pipes |=
9379                                 1 << connector->new_encoder->new_crtc->pipe;
9380         }
9381
9382         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9383                             base.head) {
9384                 if (encoder->base.crtc == &encoder->new_crtc->base)
9385                         continue;
9386
9387                 if (encoder->base.crtc) {
9388                         tmp_crtc = encoder->base.crtc;
9389
9390                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9391                 }
9392
9393                 if (encoder->new_crtc)
9394                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9395         }
9396
9397         /* Check for pipes that will be enabled/disabled ... */
9398         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9399                             base.head) {
9400                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9401                         continue;
9402
9403                 if (!intel_crtc->new_enabled)
9404                         *disable_pipes |= 1 << intel_crtc->pipe;
9405                 else
9406                         *prepare_pipes |= 1 << intel_crtc->pipe;
9407         }
9408
9409
9410         /* set_mode is also used to update properties on life display pipes. */
9411         intel_crtc = to_intel_crtc(crtc);
9412         if (intel_crtc->new_enabled)
9413                 *prepare_pipes |= 1 << intel_crtc->pipe;
9414
9415         /*
9416          * For simplicity do a full modeset on any pipe where the output routing
9417          * changed. We could be more clever, but that would require us to be
9418          * more careful with calling the relevant encoder->mode_set functions.
9419          */
9420         if (*prepare_pipes)
9421                 *modeset_pipes = *prepare_pipes;
9422
9423         /* ... and mask these out. */
9424         *modeset_pipes &= ~(*disable_pipes);
9425         *prepare_pipes &= ~(*disable_pipes);
9426
9427         /*
9428          * HACK: We don't (yet) fully support global modesets. intel_set_config
9429          * obies this rule, but the modeset restore mode of
9430          * intel_modeset_setup_hw_state does not.
9431          */
9432         *modeset_pipes &= 1 << intel_crtc->pipe;
9433         *prepare_pipes &= 1 << intel_crtc->pipe;
9434
9435         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9436                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9437 }
9438
9439 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9440 {
9441         struct drm_encoder *encoder;
9442         struct drm_device *dev = crtc->dev;
9443
9444         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9445                 if (encoder->crtc == crtc)
9446                         return true;
9447
9448         return false;
9449 }
9450
9451 static void
9452 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9453 {
9454         struct intel_encoder *intel_encoder;
9455         struct intel_crtc *intel_crtc;
9456         struct drm_connector *connector;
9457
9458         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9459                             base.head) {
9460                 if (!intel_encoder->base.crtc)
9461                         continue;
9462
9463                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9464
9465                 if (prepare_pipes & (1 << intel_crtc->pipe))
9466                         intel_encoder->connectors_active = false;
9467         }
9468
9469         intel_modeset_commit_output_state(dev);
9470
9471         /* Double check state. */
9472         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9473                             base.head) {
9474                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9475                 WARN_ON(intel_crtc->new_config &&
9476                         intel_crtc->new_config != &intel_crtc->config);
9477                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9478         }
9479
9480         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9481                 if (!connector->encoder || !connector->encoder->crtc)
9482                         continue;
9483
9484                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9485
9486                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9487                         struct drm_property *dpms_property =
9488                                 dev->mode_config.dpms_property;
9489
9490                         connector->dpms = DRM_MODE_DPMS_ON;
9491                         drm_object_property_set_value(&connector->base,
9492                                                          dpms_property,
9493                                                          DRM_MODE_DPMS_ON);
9494
9495                         intel_encoder = to_intel_encoder(connector->encoder);
9496                         intel_encoder->connectors_active = true;
9497                 }
9498         }
9499
9500 }
9501
9502 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9503 {
9504         int diff;
9505
9506         if (clock1 == clock2)
9507                 return true;
9508
9509         if (!clock1 || !clock2)
9510                 return false;
9511
9512         diff = abs(clock1 - clock2);
9513
9514         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9515                 return true;
9516
9517         return false;
9518 }
9519
9520 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9521         list_for_each_entry((intel_crtc), \
9522                             &(dev)->mode_config.crtc_list, \
9523                             base.head) \
9524                 if (mask & (1 <<(intel_crtc)->pipe))
9525
9526 static bool
9527 intel_pipe_config_compare(struct drm_device *dev,
9528                           struct intel_crtc_config *current_config,
9529                           struct intel_crtc_config *pipe_config)
9530 {
9531 #define PIPE_CONF_CHECK_X(name) \
9532         if (current_config->name != pipe_config->name) { \
9533                 DRM_ERROR("mismatch in " #name " " \
9534                           "(expected 0x%08x, found 0x%08x)\n", \
9535                           current_config->name, \
9536                           pipe_config->name); \
9537                 return false; \
9538         }
9539
9540 #define PIPE_CONF_CHECK_I(name) \
9541         if (current_config->name != pipe_config->name) { \
9542                 DRM_ERROR("mismatch in " #name " " \
9543                           "(expected %i, found %i)\n", \
9544                           current_config->name, \
9545                           pipe_config->name); \
9546                 return false; \
9547         }
9548
9549 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9550         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9551                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9552                           "(expected %i, found %i)\n", \
9553                           current_config->name & (mask), \
9554                           pipe_config->name & (mask)); \
9555                 return false; \
9556         }
9557
9558 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9559         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9560                 DRM_ERROR("mismatch in " #name " " \
9561                           "(expected %i, found %i)\n", \
9562                           current_config->name, \
9563                           pipe_config->name); \
9564                 return false; \
9565         }
9566
9567 #define PIPE_CONF_QUIRK(quirk)  \
9568         ((current_config->quirks | pipe_config->quirks) & (quirk))
9569
9570         PIPE_CONF_CHECK_I(cpu_transcoder);
9571
9572         PIPE_CONF_CHECK_I(has_pch_encoder);
9573         PIPE_CONF_CHECK_I(fdi_lanes);
9574         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9575         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9576         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9577         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9578         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9579
9580         PIPE_CONF_CHECK_I(has_dp_encoder);
9581         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9582         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9583         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9584         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9585         PIPE_CONF_CHECK_I(dp_m_n.tu);
9586
9587         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9588         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9589         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9590         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9591         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9592         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9593
9594         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9595         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9596         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9597         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9598         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9599         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9600
9601         PIPE_CONF_CHECK_I(pixel_multiplier);
9602
9603         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9604                               DRM_MODE_FLAG_INTERLACE);
9605
9606         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9607                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9608                                       DRM_MODE_FLAG_PHSYNC);
9609                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9610                                       DRM_MODE_FLAG_NHSYNC);
9611                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9612                                       DRM_MODE_FLAG_PVSYNC);
9613                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9614                                       DRM_MODE_FLAG_NVSYNC);
9615         }
9616
9617         PIPE_CONF_CHECK_I(pipe_src_w);
9618         PIPE_CONF_CHECK_I(pipe_src_h);
9619
9620         /*
9621          * FIXME: BIOS likes to set up a cloned config with lvds+external
9622          * screen. Since we don't yet re-compute the pipe config when moving
9623          * just the lvds port away to another pipe the sw tracking won't match.
9624          *
9625          * Proper atomic modesets with recomputed global state will fix this.
9626          * Until then just don't check gmch state for inherited modes.
9627          */
9628         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9629                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9630                 /* pfit ratios are autocomputed by the hw on gen4+ */
9631                 if (INTEL_INFO(dev)->gen < 4)
9632                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9633                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9634         }
9635
9636         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9637         if (current_config->pch_pfit.enabled) {
9638                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9639                 PIPE_CONF_CHECK_I(pch_pfit.size);
9640         }
9641
9642         /* BDW+ don't expose a synchronous way to read the state */
9643         if (IS_HASWELL(dev))
9644                 PIPE_CONF_CHECK_I(ips_enabled);
9645
9646         PIPE_CONF_CHECK_I(double_wide);
9647
9648         PIPE_CONF_CHECK_I(shared_dpll);
9649         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9650         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9651         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9652         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9653
9654         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9655                 PIPE_CONF_CHECK_I(pipe_bpp);
9656
9657         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9658         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9659
9660 #undef PIPE_CONF_CHECK_X
9661 #undef PIPE_CONF_CHECK_I
9662 #undef PIPE_CONF_CHECK_FLAGS
9663 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9664 #undef PIPE_CONF_QUIRK
9665
9666         return true;
9667 }
9668
9669 static void
9670 check_connector_state(struct drm_device *dev)
9671 {
9672         struct intel_connector *connector;
9673
9674         list_for_each_entry(connector, &dev->mode_config.connector_list,
9675                             base.head) {
9676                 /* This also checks the encoder/connector hw state with the
9677                  * ->get_hw_state callbacks. */
9678                 intel_connector_check_state(connector);
9679
9680                 WARN(&connector->new_encoder->base != connector->base.encoder,
9681                      "connector's staged encoder doesn't match current encoder\n");
9682         }
9683 }
9684
9685 static void
9686 check_encoder_state(struct drm_device *dev)
9687 {
9688         struct intel_encoder *encoder;
9689         struct intel_connector *connector;
9690
9691         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9692                             base.head) {
9693                 bool enabled = false;
9694                 bool active = false;
9695                 enum pipe pipe, tracked_pipe;
9696
9697                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9698                               encoder->base.base.id,
9699                               drm_get_encoder_name(&encoder->base));
9700
9701                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9702                      "encoder's stage crtc doesn't match current crtc\n");
9703                 WARN(encoder->connectors_active && !encoder->base.crtc,
9704                      "encoder's active_connectors set, but no crtc\n");
9705
9706                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9707                                     base.head) {
9708                         if (connector->base.encoder != &encoder->base)
9709                                 continue;
9710                         enabled = true;
9711                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9712                                 active = true;
9713                 }
9714                 WARN(!!encoder->base.crtc != enabled,
9715                      "encoder's enabled state mismatch "
9716                      "(expected %i, found %i)\n",
9717                      !!encoder->base.crtc, enabled);
9718                 WARN(active && !encoder->base.crtc,
9719                      "active encoder with no crtc\n");
9720
9721                 WARN(encoder->connectors_active != active,
9722                      "encoder's computed active state doesn't match tracked active state "
9723                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9724
9725                 active = encoder->get_hw_state(encoder, &pipe);
9726                 WARN(active != encoder->connectors_active,
9727                      "encoder's hw state doesn't match sw tracking "
9728                      "(expected %i, found %i)\n",
9729                      encoder->connectors_active, active);
9730
9731                 if (!encoder->base.crtc)
9732                         continue;
9733
9734                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9735                 WARN(active && pipe != tracked_pipe,
9736                      "active encoder's pipe doesn't match"
9737                      "(expected %i, found %i)\n",
9738                      tracked_pipe, pipe);
9739
9740         }
9741 }
9742
9743 static void
9744 check_crtc_state(struct drm_device *dev)
9745 {
9746         struct drm_i915_private *dev_priv = dev->dev_private;
9747         struct intel_crtc *crtc;
9748         struct intel_encoder *encoder;
9749         struct intel_crtc_config pipe_config;
9750
9751         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9752                             base.head) {
9753                 bool enabled = false;
9754                 bool active = false;
9755
9756                 memset(&pipe_config, 0, sizeof(pipe_config));
9757
9758                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9759                               crtc->base.base.id);
9760
9761                 WARN(crtc->active && !crtc->base.enabled,
9762                      "active crtc, but not enabled in sw tracking\n");
9763
9764                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9765                                     base.head) {
9766                         if (encoder->base.crtc != &crtc->base)
9767                                 continue;
9768                         enabled = true;
9769                         if (encoder->connectors_active)
9770                                 active = true;
9771                 }
9772
9773                 WARN(active != crtc->active,
9774                      "crtc's computed active state doesn't match tracked active state "
9775                      "(expected %i, found %i)\n", active, crtc->active);
9776                 WARN(enabled != crtc->base.enabled,
9777                      "crtc's computed enabled state doesn't match tracked enabled state "
9778                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9779
9780                 active = dev_priv->display.get_pipe_config(crtc,
9781                                                            &pipe_config);
9782
9783                 /* hw state is inconsistent with the pipe A quirk */
9784                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9785                         active = crtc->active;
9786
9787                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9788                                     base.head) {
9789                         enum pipe pipe;
9790                         if (encoder->base.crtc != &crtc->base)
9791                                 continue;
9792                         if (encoder->get_hw_state(encoder, &pipe))
9793                                 encoder->get_config(encoder, &pipe_config);
9794                 }
9795
9796                 WARN(crtc->active != active,
9797                      "crtc active state doesn't match with hw state "
9798                      "(expected %i, found %i)\n", crtc->active, active);
9799
9800                 if (active &&
9801                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9802                         WARN(1, "pipe state doesn't match!\n");
9803                         intel_dump_pipe_config(crtc, &pipe_config,
9804                                                "[hw state]");
9805                         intel_dump_pipe_config(crtc, &crtc->config,
9806                                                "[sw state]");
9807                 }
9808         }
9809 }
9810
9811 static void
9812 check_shared_dpll_state(struct drm_device *dev)
9813 {
9814         struct drm_i915_private *dev_priv = dev->dev_private;
9815         struct intel_crtc *crtc;
9816         struct intel_dpll_hw_state dpll_hw_state;
9817         int i;
9818
9819         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9820                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9821                 int enabled_crtcs = 0, active_crtcs = 0;
9822                 bool active;
9823
9824                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9825
9826                 DRM_DEBUG_KMS("%s\n", pll->name);
9827
9828                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9829
9830                 WARN(pll->active > pll->refcount,
9831                      "more active pll users than references: %i vs %i\n",
9832                      pll->active, pll->refcount);
9833                 WARN(pll->active && !pll->on,
9834                      "pll in active use but not on in sw tracking\n");
9835                 WARN(pll->on && !pll->active,
9836                      "pll in on but not on in use in sw tracking\n");
9837                 WARN(pll->on != active,
9838                      "pll on state mismatch (expected %i, found %i)\n",
9839                      pll->on, active);
9840
9841                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9842                                     base.head) {
9843                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9844                                 enabled_crtcs++;
9845                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9846                                 active_crtcs++;
9847                 }
9848                 WARN(pll->active != active_crtcs,
9849                      "pll active crtcs mismatch (expected %i, found %i)\n",
9850                      pll->active, active_crtcs);
9851                 WARN(pll->refcount != enabled_crtcs,
9852                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9853                      pll->refcount, enabled_crtcs);
9854
9855                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9856                                        sizeof(dpll_hw_state)),
9857                      "pll hw state mismatch\n");
9858         }
9859 }
9860
9861 void
9862 intel_modeset_check_state(struct drm_device *dev)
9863 {
9864         check_connector_state(dev);
9865         check_encoder_state(dev);
9866         check_crtc_state(dev);
9867         check_shared_dpll_state(dev);
9868 }
9869
9870 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9871                                      int dotclock)
9872 {
9873         /*
9874          * FDI already provided one idea for the dotclock.
9875          * Yell if the encoder disagrees.
9876          */
9877         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9878              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9879              pipe_config->adjusted_mode.crtc_clock, dotclock);
9880 }
9881
9882 static int __intel_set_mode(struct drm_crtc *crtc,
9883                             struct drm_display_mode *mode,
9884                             int x, int y, struct drm_framebuffer *fb)
9885 {
9886         struct drm_device *dev = crtc->dev;
9887         struct drm_i915_private *dev_priv = dev->dev_private;
9888         struct drm_display_mode *saved_mode;
9889         struct intel_crtc_config *pipe_config = NULL;
9890         struct intel_crtc *intel_crtc;
9891         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9892         int ret = 0;
9893
9894         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9895         if (!saved_mode)
9896                 return -ENOMEM;
9897
9898         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9899                                      &prepare_pipes, &disable_pipes);
9900
9901         *saved_mode = crtc->mode;
9902
9903         /* Hack: Because we don't (yet) support global modeset on multiple
9904          * crtcs, we don't keep track of the new mode for more than one crtc.
9905          * Hence simply check whether any bit is set in modeset_pipes in all the
9906          * pieces of code that are not yet converted to deal with mutliple crtcs
9907          * changing their mode at the same time. */
9908         if (modeset_pipes) {
9909                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9910                 if (IS_ERR(pipe_config)) {
9911                         ret = PTR_ERR(pipe_config);
9912                         pipe_config = NULL;
9913
9914                         goto out;
9915                 }
9916                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9917                                        "[modeset]");
9918                 to_intel_crtc(crtc)->new_config = pipe_config;
9919         }
9920
9921         /*
9922          * See if the config requires any additional preparation, e.g.
9923          * to adjust global state with pipes off.  We need to do this
9924          * here so we can get the modeset_pipe updated config for the new
9925          * mode set on this crtc.  For other crtcs we need to use the
9926          * adjusted_mode bits in the crtc directly.
9927          */
9928         if (IS_VALLEYVIEW(dev)) {
9929                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9930
9931                 /* may have added more to prepare_pipes than we should */
9932                 prepare_pipes &= ~disable_pipes;
9933         }
9934
9935         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9936                 intel_crtc_disable(&intel_crtc->base);
9937
9938         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9939                 if (intel_crtc->base.enabled)
9940                         dev_priv->display.crtc_disable(&intel_crtc->base);
9941         }
9942
9943         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9944          * to set it here already despite that we pass it down the callchain.
9945          */
9946         if (modeset_pipes) {
9947                 crtc->mode = *mode;
9948                 /* mode_set/enable/disable functions rely on a correct pipe
9949                  * config. */
9950                 to_intel_crtc(crtc)->config = *pipe_config;
9951                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9952
9953                 /*
9954                  * Calculate and store various constants which
9955                  * are later needed by vblank and swap-completion
9956                  * timestamping. They are derived from true hwmode.
9957                  */
9958                 drm_calc_timestamping_constants(crtc,
9959                                                 &pipe_config->adjusted_mode);
9960         }
9961
9962         /* Only after disabling all output pipelines that will be changed can we
9963          * update the the output configuration. */
9964         intel_modeset_update_state(dev, prepare_pipes);
9965
9966         if (dev_priv->display.modeset_global_resources)
9967                 dev_priv->display.modeset_global_resources(dev);
9968
9969         /* Set up the DPLL and any encoders state that needs to adjust or depend
9970          * on the DPLL.
9971          */
9972         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9973                 ret = intel_crtc_mode_set(&intel_crtc->base,
9974                                           x, y, fb);
9975                 if (ret)
9976                         goto done;
9977         }
9978
9979         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9980         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9981                 dev_priv->display.crtc_enable(&intel_crtc->base);
9982
9983         /* FIXME: add subpixel order */
9984 done:
9985         if (ret && crtc->enabled)
9986                 crtc->mode = *saved_mode;
9987
9988 out:
9989         kfree(pipe_config);
9990         kfree(saved_mode);
9991         return ret;
9992 }
9993
9994 static int intel_set_mode(struct drm_crtc *crtc,
9995                           struct drm_display_mode *mode,
9996                           int x, int y, struct drm_framebuffer *fb)
9997 {
9998         int ret;
9999
10000         ret = __intel_set_mode(crtc, mode, x, y, fb);
10001
10002         if (ret == 0)
10003                 intel_modeset_check_state(crtc->dev);
10004
10005         return ret;
10006 }
10007
10008 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10009 {
10010         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10011 }
10012
10013 #undef for_each_intel_crtc_masked
10014
10015 static void intel_set_config_free(struct intel_set_config *config)
10016 {
10017         if (!config)
10018                 return;
10019
10020         kfree(config->save_connector_encoders);
10021         kfree(config->save_encoder_crtcs);
10022         kfree(config->save_crtc_enabled);
10023         kfree(config);
10024 }
10025
10026 static int intel_set_config_save_state(struct drm_device *dev,
10027                                        struct intel_set_config *config)
10028 {
10029         struct drm_crtc *crtc;
10030         struct drm_encoder *encoder;
10031         struct drm_connector *connector;
10032         int count;
10033
10034         config->save_crtc_enabled =
10035                 kcalloc(dev->mode_config.num_crtc,
10036                         sizeof(bool), GFP_KERNEL);
10037         if (!config->save_crtc_enabled)
10038                 return -ENOMEM;
10039
10040         config->save_encoder_crtcs =
10041                 kcalloc(dev->mode_config.num_encoder,
10042                         sizeof(struct drm_crtc *), GFP_KERNEL);
10043         if (!config->save_encoder_crtcs)
10044                 return -ENOMEM;
10045
10046         config->save_connector_encoders =
10047                 kcalloc(dev->mode_config.num_connector,
10048                         sizeof(struct drm_encoder *), GFP_KERNEL);
10049         if (!config->save_connector_encoders)
10050                 return -ENOMEM;
10051
10052         /* Copy data. Note that driver private data is not affected.
10053          * Should anything bad happen only the expected state is
10054          * restored, not the drivers personal bookkeeping.
10055          */
10056         count = 0;
10057         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10058                 config->save_crtc_enabled[count++] = crtc->enabled;
10059         }
10060
10061         count = 0;
10062         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10063                 config->save_encoder_crtcs[count++] = encoder->crtc;
10064         }
10065
10066         count = 0;
10067         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10068                 config->save_connector_encoders[count++] = connector->encoder;
10069         }
10070
10071         return 0;
10072 }
10073
10074 static void intel_set_config_restore_state(struct drm_device *dev,
10075                                            struct intel_set_config *config)
10076 {
10077         struct intel_crtc *crtc;
10078         struct intel_encoder *encoder;
10079         struct intel_connector *connector;
10080         int count;
10081
10082         count = 0;
10083         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10084                 crtc->new_enabled = config->save_crtc_enabled[count++];
10085
10086                 if (crtc->new_enabled)
10087                         crtc->new_config = &crtc->config;
10088                 else
10089                         crtc->new_config = NULL;
10090         }
10091
10092         count = 0;
10093         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10094                 encoder->new_crtc =
10095                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10096         }
10097
10098         count = 0;
10099         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10100                 connector->new_encoder =
10101                         to_intel_encoder(config->save_connector_encoders[count++]);
10102         }
10103 }
10104
10105 static bool
10106 is_crtc_connector_off(struct drm_mode_set *set)
10107 {
10108         int i;
10109
10110         if (set->num_connectors == 0)
10111                 return false;
10112
10113         if (WARN_ON(set->connectors == NULL))
10114                 return false;
10115
10116         for (i = 0; i < set->num_connectors; i++)
10117                 if (set->connectors[i]->encoder &&
10118                     set->connectors[i]->encoder->crtc == set->crtc &&
10119                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10120                         return true;
10121
10122         return false;
10123 }
10124
10125 static void
10126 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10127                                       struct intel_set_config *config)
10128 {
10129
10130         /* We should be able to check here if the fb has the same properties
10131          * and then just flip_or_move it */
10132         if (is_crtc_connector_off(set)) {
10133                 config->mode_changed = true;
10134         } else if (set->crtc->primary->fb != set->fb) {
10135                 /* If we have no fb then treat it as a full mode set */
10136                 if (set->crtc->primary->fb == NULL) {
10137                         struct intel_crtc *intel_crtc =
10138                                 to_intel_crtc(set->crtc);
10139
10140                         if (intel_crtc->active && i915.fastboot) {
10141                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10142                                 config->fb_changed = true;
10143                         } else {
10144                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10145                                 config->mode_changed = true;
10146                         }
10147                 } else if (set->fb == NULL) {
10148                         config->mode_changed = true;
10149                 } else if (set->fb->pixel_format !=
10150                            set->crtc->primary->fb->pixel_format) {
10151                         config->mode_changed = true;
10152                 } else {
10153                         config->fb_changed = true;
10154                 }
10155         }
10156
10157         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10158                 config->fb_changed = true;
10159
10160         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10161                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10162                 drm_mode_debug_printmodeline(&set->crtc->mode);
10163                 drm_mode_debug_printmodeline(set->mode);
10164                 config->mode_changed = true;
10165         }
10166
10167         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10168                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10169 }
10170
10171 static int
10172 intel_modeset_stage_output_state(struct drm_device *dev,
10173                                  struct drm_mode_set *set,
10174                                  struct intel_set_config *config)
10175 {
10176         struct intel_connector *connector;
10177         struct intel_encoder *encoder;
10178         struct intel_crtc *crtc;
10179         int ro;
10180
10181         /* The upper layers ensure that we either disable a crtc or have a list
10182          * of connectors. For paranoia, double-check this. */
10183         WARN_ON(!set->fb && (set->num_connectors != 0));
10184         WARN_ON(set->fb && (set->num_connectors == 0));
10185
10186         list_for_each_entry(connector, &dev->mode_config.connector_list,
10187                             base.head) {
10188                 /* Otherwise traverse passed in connector list and get encoders
10189                  * for them. */
10190                 for (ro = 0; ro < set->num_connectors; ro++) {
10191                         if (set->connectors[ro] == &connector->base) {
10192                                 connector->new_encoder = connector->encoder;
10193                                 break;
10194                         }
10195                 }
10196
10197                 /* If we disable the crtc, disable all its connectors. Also, if
10198                  * the connector is on the changing crtc but not on the new
10199                  * connector list, disable it. */
10200                 if ((!set->fb || ro == set->num_connectors) &&
10201                     connector->base.encoder &&
10202                     connector->base.encoder->crtc == set->crtc) {
10203                         connector->new_encoder = NULL;
10204
10205                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10206                                 connector->base.base.id,
10207                                 drm_get_connector_name(&connector->base));
10208                 }
10209
10210
10211                 if (&connector->new_encoder->base != connector->base.encoder) {
10212                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10213                         config->mode_changed = true;
10214                 }
10215         }
10216         /* connector->new_encoder is now updated for all connectors. */
10217
10218         /* Update crtc of enabled connectors. */
10219         list_for_each_entry(connector, &dev->mode_config.connector_list,
10220                             base.head) {
10221                 struct drm_crtc *new_crtc;
10222
10223                 if (!connector->new_encoder)
10224                         continue;
10225
10226                 new_crtc = connector->new_encoder->base.crtc;
10227
10228                 for (ro = 0; ro < set->num_connectors; ro++) {
10229                         if (set->connectors[ro] == &connector->base)
10230                                 new_crtc = set->crtc;
10231                 }
10232
10233                 /* Make sure the new CRTC will work with the encoder */
10234                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10235                                          new_crtc)) {
10236                         return -EINVAL;
10237                 }
10238                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10239
10240                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10241                         connector->base.base.id,
10242                         drm_get_connector_name(&connector->base),
10243                         new_crtc->base.id);
10244         }
10245
10246         /* Check for any encoders that needs to be disabled. */
10247         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10248                             base.head) {
10249                 int num_connectors = 0;
10250                 list_for_each_entry(connector,
10251                                     &dev->mode_config.connector_list,
10252                                     base.head) {
10253                         if (connector->new_encoder == encoder) {
10254                                 WARN_ON(!connector->new_encoder->new_crtc);
10255                                 num_connectors++;
10256                         }
10257                 }
10258
10259                 if (num_connectors == 0)
10260                         encoder->new_crtc = NULL;
10261                 else if (num_connectors > 1)
10262                         return -EINVAL;
10263
10264                 /* Only now check for crtc changes so we don't miss encoders
10265                  * that will be disabled. */
10266                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10267                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10268                         config->mode_changed = true;
10269                 }
10270         }
10271         /* Now we've also updated encoder->new_crtc for all encoders. */
10272
10273         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10274                             base.head) {
10275                 crtc->new_enabled = false;
10276
10277                 list_for_each_entry(encoder,
10278                                     &dev->mode_config.encoder_list,
10279                                     base.head) {
10280                         if (encoder->new_crtc == crtc) {
10281                                 crtc->new_enabled = true;
10282                                 break;
10283                         }
10284                 }
10285
10286                 if (crtc->new_enabled != crtc->base.enabled) {
10287                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10288                                       crtc->new_enabled ? "en" : "dis");
10289                         config->mode_changed = true;
10290                 }
10291
10292                 if (crtc->new_enabled)
10293                         crtc->new_config = &crtc->config;
10294                 else
10295                         crtc->new_config = NULL;
10296         }
10297
10298         return 0;
10299 }
10300
10301 static void disable_crtc_nofb(struct intel_crtc *crtc)
10302 {
10303         struct drm_device *dev = crtc->base.dev;
10304         struct intel_encoder *encoder;
10305         struct intel_connector *connector;
10306
10307         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10308                       pipe_name(crtc->pipe));
10309
10310         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10311                 if (connector->new_encoder &&
10312                     connector->new_encoder->new_crtc == crtc)
10313                         connector->new_encoder = NULL;
10314         }
10315
10316         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10317                 if (encoder->new_crtc == crtc)
10318                         encoder->new_crtc = NULL;
10319         }
10320
10321         crtc->new_enabled = false;
10322         crtc->new_config = NULL;
10323 }
10324
10325 static int intel_crtc_set_config(struct drm_mode_set *set)
10326 {
10327         struct drm_device *dev;
10328         struct drm_mode_set save_set;
10329         struct intel_set_config *config;
10330         int ret;
10331
10332         BUG_ON(!set);
10333         BUG_ON(!set->crtc);
10334         BUG_ON(!set->crtc->helper_private);
10335
10336         /* Enforce sane interface api - has been abused by the fb helper. */
10337         BUG_ON(!set->mode && set->fb);
10338         BUG_ON(set->fb && set->num_connectors == 0);
10339
10340         if (set->fb) {
10341                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10342                                 set->crtc->base.id, set->fb->base.id,
10343                                 (int)set->num_connectors, set->x, set->y);
10344         } else {
10345                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10346         }
10347
10348         dev = set->crtc->dev;
10349
10350         ret = -ENOMEM;
10351         config = kzalloc(sizeof(*config), GFP_KERNEL);
10352         if (!config)
10353                 goto out_config;
10354
10355         ret = intel_set_config_save_state(dev, config);
10356         if (ret)
10357                 goto out_config;
10358
10359         save_set.crtc = set->crtc;
10360         save_set.mode = &set->crtc->mode;
10361         save_set.x = set->crtc->x;
10362         save_set.y = set->crtc->y;
10363         save_set.fb = set->crtc->primary->fb;
10364
10365         /* Compute whether we need a full modeset, only an fb base update or no
10366          * change at all. In the future we might also check whether only the
10367          * mode changed, e.g. for LVDS where we only change the panel fitter in
10368          * such cases. */
10369         intel_set_config_compute_mode_changes(set, config);
10370
10371         ret = intel_modeset_stage_output_state(dev, set, config);
10372         if (ret)
10373                 goto fail;
10374
10375         if (config->mode_changed) {
10376                 ret = intel_set_mode(set->crtc, set->mode,
10377                                      set->x, set->y, set->fb);
10378         } else if (config->fb_changed) {
10379                 intel_crtc_wait_for_pending_flips(set->crtc);
10380
10381                 ret = intel_pipe_set_base(set->crtc,
10382                                           set->x, set->y, set->fb);
10383                 /*
10384                  * In the fastboot case this may be our only check of the
10385                  * state after boot.  It would be better to only do it on
10386                  * the first update, but we don't have a nice way of doing that
10387                  * (and really, set_config isn't used much for high freq page
10388                  * flipping, so increasing its cost here shouldn't be a big
10389                  * deal).
10390                  */
10391                 if (i915.fastboot && ret == 0)
10392                         intel_modeset_check_state(set->crtc->dev);
10393         }
10394
10395         if (ret) {
10396                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10397                               set->crtc->base.id, ret);
10398 fail:
10399                 intel_set_config_restore_state(dev, config);
10400
10401                 /*
10402                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10403                  * force the pipe off to avoid oopsing in the modeset code
10404                  * due to fb==NULL. This should only happen during boot since
10405                  * we don't yet reconstruct the FB from the hardware state.
10406                  */
10407                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10408                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10409
10410                 /* Try to restore the config */
10411                 if (config->mode_changed &&
10412                     intel_set_mode(save_set.crtc, save_set.mode,
10413                                    save_set.x, save_set.y, save_set.fb))
10414                         DRM_ERROR("failed to restore config after modeset failure\n");
10415         }
10416
10417 out_config:
10418         intel_set_config_free(config);
10419         return ret;
10420 }
10421
10422 static const struct drm_crtc_funcs intel_crtc_funcs = {
10423         .cursor_set = intel_crtc_cursor_set,
10424         .cursor_move = intel_crtc_cursor_move,
10425         .gamma_set = intel_crtc_gamma_set,
10426         .set_config = intel_crtc_set_config,
10427         .destroy = intel_crtc_destroy,
10428         .page_flip = intel_crtc_page_flip,
10429 };
10430
10431 static void intel_cpu_pll_init(struct drm_device *dev)
10432 {
10433         if (HAS_DDI(dev))
10434                 intel_ddi_pll_init(dev);
10435 }
10436
10437 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10438                                       struct intel_shared_dpll *pll,
10439                                       struct intel_dpll_hw_state *hw_state)
10440 {
10441         uint32_t val;
10442
10443         val = I915_READ(PCH_DPLL(pll->id));
10444         hw_state->dpll = val;
10445         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10446         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10447
10448         return val & DPLL_VCO_ENABLE;
10449 }
10450
10451 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10452                                   struct intel_shared_dpll *pll)
10453 {
10454         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10455         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10456 }
10457
10458 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10459                                 struct intel_shared_dpll *pll)
10460 {
10461         /* PCH refclock must be enabled first */
10462         ibx_assert_pch_refclk_enabled(dev_priv);
10463
10464         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10465
10466         /* Wait for the clocks to stabilize. */
10467         POSTING_READ(PCH_DPLL(pll->id));
10468         udelay(150);
10469
10470         /* The pixel multiplier can only be updated once the
10471          * DPLL is enabled and the clocks are stable.
10472          *
10473          * So write it again.
10474          */
10475         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10476         POSTING_READ(PCH_DPLL(pll->id));
10477         udelay(200);
10478 }
10479
10480 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10481                                  struct intel_shared_dpll *pll)
10482 {
10483         struct drm_device *dev = dev_priv->dev;
10484         struct intel_crtc *crtc;
10485
10486         /* Make sure no transcoder isn't still depending on us. */
10487         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10488                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10489                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10490         }
10491
10492         I915_WRITE(PCH_DPLL(pll->id), 0);
10493         POSTING_READ(PCH_DPLL(pll->id));
10494         udelay(200);
10495 }
10496
10497 static char *ibx_pch_dpll_names[] = {
10498         "PCH DPLL A",
10499         "PCH DPLL B",
10500 };
10501
10502 static void ibx_pch_dpll_init(struct drm_device *dev)
10503 {
10504         struct drm_i915_private *dev_priv = dev->dev_private;
10505         int i;
10506
10507         dev_priv->num_shared_dpll = 2;
10508
10509         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10510                 dev_priv->shared_dplls[i].id = i;
10511                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10512                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10513                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10514                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10515                 dev_priv->shared_dplls[i].get_hw_state =
10516                         ibx_pch_dpll_get_hw_state;
10517         }
10518 }
10519
10520 static void intel_shared_dpll_init(struct drm_device *dev)
10521 {
10522         struct drm_i915_private *dev_priv = dev->dev_private;
10523
10524         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10525                 ibx_pch_dpll_init(dev);
10526         else
10527                 dev_priv->num_shared_dpll = 0;
10528
10529         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10530 }
10531
10532 static void intel_crtc_init(struct drm_device *dev, int pipe)
10533 {
10534         struct drm_i915_private *dev_priv = dev->dev_private;
10535         struct intel_crtc *intel_crtc;
10536         int i;
10537
10538         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10539         if (intel_crtc == NULL)
10540                 return;
10541
10542         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10543
10544         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10545         for (i = 0; i < 256; i++) {
10546                 intel_crtc->lut_r[i] = i;
10547                 intel_crtc->lut_g[i] = i;
10548                 intel_crtc->lut_b[i] = i;
10549         }
10550
10551         /*
10552          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10553          * is hooked to plane B. Hence we want plane A feeding pipe B.
10554          */
10555         intel_crtc->pipe = pipe;
10556         intel_crtc->plane = pipe;
10557         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10558                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10559                 intel_crtc->plane = !pipe;
10560         }
10561
10562         init_waitqueue_head(&intel_crtc->vbl_wait);
10563
10564         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10565                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10566         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10567         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10568
10569         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10570 }
10571
10572 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10573 {
10574         struct drm_encoder *encoder = connector->base.encoder;
10575
10576         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10577
10578         if (!encoder)
10579                 return INVALID_PIPE;
10580
10581         return to_intel_crtc(encoder->crtc)->pipe;
10582 }
10583
10584 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10585                                 struct drm_file *file)
10586 {
10587         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10588         struct drm_mode_object *drmmode_obj;
10589         struct intel_crtc *crtc;
10590
10591         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10592                 return -ENODEV;
10593
10594         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10595                         DRM_MODE_OBJECT_CRTC);
10596
10597         if (!drmmode_obj) {
10598                 DRM_ERROR("no such CRTC id\n");
10599                 return -ENOENT;
10600         }
10601
10602         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10603         pipe_from_crtc_id->pipe = crtc->pipe;
10604
10605         return 0;
10606 }
10607
10608 static int intel_encoder_clones(struct intel_encoder *encoder)
10609 {
10610         struct drm_device *dev = encoder->base.dev;
10611         struct intel_encoder *source_encoder;
10612         int index_mask = 0;
10613         int entry = 0;
10614
10615         list_for_each_entry(source_encoder,
10616                             &dev->mode_config.encoder_list, base.head) {
10617                 if (encoders_cloneable(encoder, source_encoder))
10618                         index_mask |= (1 << entry);
10619
10620                 entry++;
10621         }
10622
10623         return index_mask;
10624 }
10625
10626 static bool has_edp_a(struct drm_device *dev)
10627 {
10628         struct drm_i915_private *dev_priv = dev->dev_private;
10629
10630         if (!IS_MOBILE(dev))
10631                 return false;
10632
10633         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10634                 return false;
10635
10636         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10637                 return false;
10638
10639         return true;
10640 }
10641
10642 const char *intel_output_name(int output)
10643 {
10644         static const char *names[] = {
10645                 [INTEL_OUTPUT_UNUSED] = "Unused",
10646                 [INTEL_OUTPUT_ANALOG] = "Analog",
10647                 [INTEL_OUTPUT_DVO] = "DVO",
10648                 [INTEL_OUTPUT_SDVO] = "SDVO",
10649                 [INTEL_OUTPUT_LVDS] = "LVDS",
10650                 [INTEL_OUTPUT_TVOUT] = "TV",
10651                 [INTEL_OUTPUT_HDMI] = "HDMI",
10652                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10653                 [INTEL_OUTPUT_EDP] = "eDP",
10654                 [INTEL_OUTPUT_DSI] = "DSI",
10655                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10656         };
10657
10658         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10659                 return "Invalid";
10660
10661         return names[output];
10662 }
10663
10664 static void intel_setup_outputs(struct drm_device *dev)
10665 {
10666         struct drm_i915_private *dev_priv = dev->dev_private;
10667         struct intel_encoder *encoder;
10668         bool dpd_is_edp = false;
10669
10670         intel_lvds_init(dev);
10671
10672         if (!IS_ULT(dev))
10673                 intel_crt_init(dev);
10674
10675         if (HAS_DDI(dev)) {
10676                 int found;
10677
10678                 /* Haswell uses DDI functions to detect digital outputs */
10679                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10680                 /* DDI A only supports eDP */
10681                 if (found)
10682                         intel_ddi_init(dev, PORT_A);
10683
10684                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10685                  * register */
10686                 found = I915_READ(SFUSE_STRAP);
10687
10688                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10689                         intel_ddi_init(dev, PORT_B);
10690                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10691                         intel_ddi_init(dev, PORT_C);
10692                 if (found & SFUSE_STRAP_DDID_DETECTED)
10693                         intel_ddi_init(dev, PORT_D);
10694         } else if (HAS_PCH_SPLIT(dev)) {
10695                 int found;
10696                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10697
10698                 if (has_edp_a(dev))
10699                         intel_dp_init(dev, DP_A, PORT_A);
10700
10701                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10702                         /* PCH SDVOB multiplex with HDMIB */
10703                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10704                         if (!found)
10705                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10706                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10707                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10708                 }
10709
10710                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10711                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10712
10713                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10714                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10715
10716                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10717                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10718
10719                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10720                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10721         } else if (IS_VALLEYVIEW(dev)) {
10722                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10723                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10724                                         PORT_B);
10725                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10726                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10727                 }
10728
10729                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10730                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10731                                         PORT_C);
10732                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10733                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10734                 }
10735
10736                 intel_dsi_init(dev);
10737         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10738                 bool found = false;
10739
10740                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10741                         DRM_DEBUG_KMS("probing SDVOB\n");
10742                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10743                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10744                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10745                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10746                         }
10747
10748                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10749                                 intel_dp_init(dev, DP_B, PORT_B);
10750                 }
10751
10752                 /* Before G4X SDVOC doesn't have its own detect register */
10753
10754                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10755                         DRM_DEBUG_KMS("probing SDVOC\n");
10756                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10757                 }
10758
10759                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10760
10761                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10762                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10763                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10764                         }
10765                         if (SUPPORTS_INTEGRATED_DP(dev))
10766                                 intel_dp_init(dev, DP_C, PORT_C);
10767                 }
10768
10769                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10770                     (I915_READ(DP_D) & DP_DETECTED))
10771                         intel_dp_init(dev, DP_D, PORT_D);
10772         } else if (IS_GEN2(dev))
10773                 intel_dvo_init(dev);
10774
10775         if (SUPPORTS_TV(dev))
10776                 intel_tv_init(dev);
10777
10778         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10779                 encoder->base.possible_crtcs = encoder->crtc_mask;
10780                 encoder->base.possible_clones =
10781                         intel_encoder_clones(encoder);
10782         }
10783
10784         intel_init_pch_refclk(dev);
10785
10786         drm_helper_move_panel_connectors_to_head(dev);
10787 }
10788
10789 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10790 {
10791         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10792
10793         drm_framebuffer_cleanup(fb);
10794         WARN_ON(!intel_fb->obj->framebuffer_references--);
10795         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10796         kfree(intel_fb);
10797 }
10798
10799 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10800                                                 struct drm_file *file,
10801                                                 unsigned int *handle)
10802 {
10803         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10804         struct drm_i915_gem_object *obj = intel_fb->obj;
10805
10806         return drm_gem_handle_create(file, &obj->base, handle);
10807 }
10808
10809 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10810         .destroy = intel_user_framebuffer_destroy,
10811         .create_handle = intel_user_framebuffer_create_handle,
10812 };
10813
10814 static int intel_framebuffer_init(struct drm_device *dev,
10815                                   struct intel_framebuffer *intel_fb,
10816                                   struct drm_mode_fb_cmd2 *mode_cmd,
10817                                   struct drm_i915_gem_object *obj)
10818 {
10819         int aligned_height;
10820         int pitch_limit;
10821         int ret;
10822
10823         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10824
10825         if (obj->tiling_mode == I915_TILING_Y) {
10826                 DRM_DEBUG("hardware does not support tiling Y\n");
10827                 return -EINVAL;
10828         }
10829
10830         if (mode_cmd->pitches[0] & 63) {
10831                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10832                           mode_cmd->pitches[0]);
10833                 return -EINVAL;
10834         }
10835
10836         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10837                 pitch_limit = 32*1024;
10838         } else if (INTEL_INFO(dev)->gen >= 4) {
10839                 if (obj->tiling_mode)
10840                         pitch_limit = 16*1024;
10841                 else
10842                         pitch_limit = 32*1024;
10843         } else if (INTEL_INFO(dev)->gen >= 3) {
10844                 if (obj->tiling_mode)
10845                         pitch_limit = 8*1024;
10846                 else
10847                         pitch_limit = 16*1024;
10848         } else
10849                 /* XXX DSPC is limited to 4k tiled */
10850                 pitch_limit = 8*1024;
10851
10852         if (mode_cmd->pitches[0] > pitch_limit) {
10853                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10854                           obj->tiling_mode ? "tiled" : "linear",
10855                           mode_cmd->pitches[0], pitch_limit);
10856                 return -EINVAL;
10857         }
10858
10859         if (obj->tiling_mode != I915_TILING_NONE &&
10860             mode_cmd->pitches[0] != obj->stride) {
10861                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10862                           mode_cmd->pitches[0], obj->stride);
10863                 return -EINVAL;
10864         }
10865
10866         /* Reject formats not supported by any plane early. */
10867         switch (mode_cmd->pixel_format) {
10868         case DRM_FORMAT_C8:
10869         case DRM_FORMAT_RGB565:
10870         case DRM_FORMAT_XRGB8888:
10871         case DRM_FORMAT_ARGB8888:
10872                 break;
10873         case DRM_FORMAT_XRGB1555:
10874         case DRM_FORMAT_ARGB1555:
10875                 if (INTEL_INFO(dev)->gen > 3) {
10876                         DRM_DEBUG("unsupported pixel format: %s\n",
10877                                   drm_get_format_name(mode_cmd->pixel_format));
10878                         return -EINVAL;
10879                 }
10880                 break;
10881         case DRM_FORMAT_XBGR8888:
10882         case DRM_FORMAT_ABGR8888:
10883         case DRM_FORMAT_XRGB2101010:
10884         case DRM_FORMAT_ARGB2101010:
10885         case DRM_FORMAT_XBGR2101010:
10886         case DRM_FORMAT_ABGR2101010:
10887                 if (INTEL_INFO(dev)->gen < 4) {
10888                         DRM_DEBUG("unsupported pixel format: %s\n",
10889                                   drm_get_format_name(mode_cmd->pixel_format));
10890                         return -EINVAL;
10891                 }
10892                 break;
10893         case DRM_FORMAT_YUYV:
10894         case DRM_FORMAT_UYVY:
10895         case DRM_FORMAT_YVYU:
10896         case DRM_FORMAT_VYUY:
10897                 if (INTEL_INFO(dev)->gen < 5) {
10898                         DRM_DEBUG("unsupported pixel format: %s\n",
10899                                   drm_get_format_name(mode_cmd->pixel_format));
10900                         return -EINVAL;
10901                 }
10902                 break;
10903         default:
10904                 DRM_DEBUG("unsupported pixel format: %s\n",
10905                           drm_get_format_name(mode_cmd->pixel_format));
10906                 return -EINVAL;
10907         }
10908
10909         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10910         if (mode_cmd->offsets[0] != 0)
10911                 return -EINVAL;
10912
10913         aligned_height = intel_align_height(dev, mode_cmd->height,
10914                                             obj->tiling_mode);
10915         /* FIXME drm helper for size checks (especially planar formats)? */
10916         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10917                 return -EINVAL;
10918
10919         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10920         intel_fb->obj = obj;
10921         intel_fb->obj->framebuffer_references++;
10922
10923         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10924         if (ret) {
10925                 DRM_ERROR("framebuffer init failed %d\n", ret);
10926                 return ret;
10927         }
10928
10929         return 0;
10930 }
10931
10932 static struct drm_framebuffer *
10933 intel_user_framebuffer_create(struct drm_device *dev,
10934                               struct drm_file *filp,
10935                               struct drm_mode_fb_cmd2 *mode_cmd)
10936 {
10937         struct drm_i915_gem_object *obj;
10938
10939         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10940                                                 mode_cmd->handles[0]));
10941         if (&obj->base == NULL)
10942                 return ERR_PTR(-ENOENT);
10943
10944         return intel_framebuffer_create(dev, mode_cmd, obj);
10945 }
10946
10947 #ifndef CONFIG_DRM_I915_FBDEV
10948 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10949 {
10950 }
10951 #endif
10952
10953 static const struct drm_mode_config_funcs intel_mode_funcs = {
10954         .fb_create = intel_user_framebuffer_create,
10955         .output_poll_changed = intel_fbdev_output_poll_changed,
10956 };
10957
10958 /* Set up chip specific display functions */
10959 static void intel_init_display(struct drm_device *dev)
10960 {
10961         struct drm_i915_private *dev_priv = dev->dev_private;
10962
10963         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10964                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10965         else if (IS_VALLEYVIEW(dev))
10966                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10967         else if (IS_PINEVIEW(dev))
10968                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10969         else
10970                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10971
10972         if (HAS_DDI(dev)) {
10973                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10974                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10975                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10976                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10977                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10978                 dev_priv->display.off = haswell_crtc_off;
10979                 dev_priv->display.update_primary_plane =
10980                         ironlake_update_primary_plane;
10981         } else if (HAS_PCH_SPLIT(dev)) {
10982                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10983                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10984                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10985                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10986                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10987                 dev_priv->display.off = ironlake_crtc_off;
10988                 dev_priv->display.update_primary_plane =
10989                         ironlake_update_primary_plane;
10990         } else if (IS_VALLEYVIEW(dev)) {
10991                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10992                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10993                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10994                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10995                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10996                 dev_priv->display.off = i9xx_crtc_off;
10997                 dev_priv->display.update_primary_plane =
10998                         i9xx_update_primary_plane;
10999         } else {
11000                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11001                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11002                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11003                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11004                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11005                 dev_priv->display.off = i9xx_crtc_off;
11006                 dev_priv->display.update_primary_plane =
11007                         i9xx_update_primary_plane;
11008         }
11009
11010         /* Returns the core display clock speed */
11011         if (IS_VALLEYVIEW(dev))
11012                 dev_priv->display.get_display_clock_speed =
11013                         valleyview_get_display_clock_speed;
11014         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11015                 dev_priv->display.get_display_clock_speed =
11016                         i945_get_display_clock_speed;
11017         else if (IS_I915G(dev))
11018                 dev_priv->display.get_display_clock_speed =
11019                         i915_get_display_clock_speed;
11020         else if (IS_I945GM(dev) || IS_845G(dev))
11021                 dev_priv->display.get_display_clock_speed =
11022                         i9xx_misc_get_display_clock_speed;
11023         else if (IS_PINEVIEW(dev))
11024                 dev_priv->display.get_display_clock_speed =
11025                         pnv_get_display_clock_speed;
11026         else if (IS_I915GM(dev))
11027                 dev_priv->display.get_display_clock_speed =
11028                         i915gm_get_display_clock_speed;
11029         else if (IS_I865G(dev))
11030                 dev_priv->display.get_display_clock_speed =
11031                         i865_get_display_clock_speed;
11032         else if (IS_I85X(dev))
11033                 dev_priv->display.get_display_clock_speed =
11034                         i855_get_display_clock_speed;
11035         else /* 852, 830 */
11036                 dev_priv->display.get_display_clock_speed =
11037                         i830_get_display_clock_speed;
11038
11039         if (HAS_PCH_SPLIT(dev)) {
11040                 if (IS_GEN5(dev)) {
11041                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11042                         dev_priv->display.write_eld = ironlake_write_eld;
11043                 } else if (IS_GEN6(dev)) {
11044                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11045                         dev_priv->display.write_eld = ironlake_write_eld;
11046                         dev_priv->display.modeset_global_resources =
11047                                 snb_modeset_global_resources;
11048                 } else if (IS_IVYBRIDGE(dev)) {
11049                         /* FIXME: detect B0+ stepping and use auto training */
11050                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11051                         dev_priv->display.write_eld = ironlake_write_eld;
11052                         dev_priv->display.modeset_global_resources =
11053                                 ivb_modeset_global_resources;
11054                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11055                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11056                         dev_priv->display.write_eld = haswell_write_eld;
11057                         dev_priv->display.modeset_global_resources =
11058                                 haswell_modeset_global_resources;
11059                 }
11060         } else if (IS_G4X(dev)) {
11061                 dev_priv->display.write_eld = g4x_write_eld;
11062         } else if (IS_VALLEYVIEW(dev)) {
11063                 dev_priv->display.modeset_global_resources =
11064                         valleyview_modeset_global_resources;
11065                 dev_priv->display.write_eld = ironlake_write_eld;
11066         }
11067
11068         /* Default just returns -ENODEV to indicate unsupported */
11069         dev_priv->display.queue_flip = intel_default_queue_flip;
11070
11071         switch (INTEL_INFO(dev)->gen) {
11072         case 2:
11073                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11074                 break;
11075
11076         case 3:
11077                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11078                 break;
11079
11080         case 4:
11081         case 5:
11082                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11083                 break;
11084
11085         case 6:
11086                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11087                 break;
11088         case 7:
11089         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11090                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11091                 break;
11092         }
11093
11094         intel_panel_init_backlight_funcs(dev);
11095 }
11096
11097 /*
11098  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11099  * resume, or other times.  This quirk makes sure that's the case for
11100  * affected systems.
11101  */
11102 static void quirk_pipea_force(struct drm_device *dev)
11103 {
11104         struct drm_i915_private *dev_priv = dev->dev_private;
11105
11106         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11107         DRM_INFO("applying pipe a force quirk\n");
11108 }
11109
11110 /*
11111  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11112  */
11113 static void quirk_ssc_force_disable(struct drm_device *dev)
11114 {
11115         struct drm_i915_private *dev_priv = dev->dev_private;
11116         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11117         DRM_INFO("applying lvds SSC disable quirk\n");
11118 }
11119
11120 /*
11121  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11122  * brightness value
11123  */
11124 static void quirk_invert_brightness(struct drm_device *dev)
11125 {
11126         struct drm_i915_private *dev_priv = dev->dev_private;
11127         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11128         DRM_INFO("applying inverted panel brightness quirk\n");
11129 }
11130
11131 struct intel_quirk {
11132         int device;
11133         int subsystem_vendor;
11134         int subsystem_device;
11135         void (*hook)(struct drm_device *dev);
11136 };
11137
11138 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11139 struct intel_dmi_quirk {
11140         void (*hook)(struct drm_device *dev);
11141         const struct dmi_system_id (*dmi_id_list)[];
11142 };
11143
11144 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11145 {
11146         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11147         return 1;
11148 }
11149
11150 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11151         {
11152                 .dmi_id_list = &(const struct dmi_system_id[]) {
11153                         {
11154                                 .callback = intel_dmi_reverse_brightness,
11155                                 .ident = "NCR Corporation",
11156                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11157                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11158                                 },
11159                         },
11160                         { }  /* terminating entry */
11161                 },
11162                 .hook = quirk_invert_brightness,
11163         },
11164 };
11165
11166 static struct intel_quirk intel_quirks[] = {
11167         /* HP Mini needs pipe A force quirk (LP: #322104) */
11168         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11169
11170         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11171         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11172
11173         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11174         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11175
11176         /* 830 needs to leave pipe A & dpll A up */
11177         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11178
11179         /* Lenovo U160 cannot use SSC on LVDS */
11180         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11181
11182         /* Sony Vaio Y cannot use SSC on LVDS */
11183         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11184
11185         /* Acer Aspire 5734Z must invert backlight brightness */
11186         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11187
11188         /* Acer/eMachines G725 */
11189         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11190
11191         /* Acer/eMachines e725 */
11192         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11193
11194         /* Acer/Packard Bell NCL20 */
11195         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11196
11197         /* Acer Aspire 4736Z */
11198         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11199
11200         /* Acer Aspire 5336 */
11201         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11202 };
11203
11204 static void intel_init_quirks(struct drm_device *dev)
11205 {
11206         struct pci_dev *d = dev->pdev;
11207         int i;
11208
11209         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11210                 struct intel_quirk *q = &intel_quirks[i];
11211
11212                 if (d->device == q->device &&
11213                     (d->subsystem_vendor == q->subsystem_vendor ||
11214                      q->subsystem_vendor == PCI_ANY_ID) &&
11215                     (d->subsystem_device == q->subsystem_device ||
11216                      q->subsystem_device == PCI_ANY_ID))
11217                         q->hook(dev);
11218         }
11219         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11220                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11221                         intel_dmi_quirks[i].hook(dev);
11222         }
11223 }
11224
11225 /* Disable the VGA plane that we never use */
11226 static void i915_disable_vga(struct drm_device *dev)
11227 {
11228         struct drm_i915_private *dev_priv = dev->dev_private;
11229         u8 sr1;
11230         u32 vga_reg = i915_vgacntrl_reg(dev);
11231
11232         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11233         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11234         outb(SR01, VGA_SR_INDEX);
11235         sr1 = inb(VGA_SR_DATA);
11236         outb(sr1 | 1<<5, VGA_SR_DATA);
11237         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11238         udelay(300);
11239
11240         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11241         POSTING_READ(vga_reg);
11242 }
11243
11244 void intel_modeset_init_hw(struct drm_device *dev)
11245 {
11246         intel_prepare_ddi(dev);
11247
11248         intel_init_clock_gating(dev);
11249
11250         intel_reset_dpio(dev);
11251
11252         intel_enable_gt_powersave(dev);
11253 }
11254
11255 void intel_modeset_suspend_hw(struct drm_device *dev)
11256 {
11257         intel_suspend_hw(dev);
11258 }
11259
11260 void intel_modeset_init(struct drm_device *dev)
11261 {
11262         struct drm_i915_private *dev_priv = dev->dev_private;
11263         int sprite, ret;
11264         enum pipe pipe;
11265         struct intel_crtc *crtc;
11266
11267         drm_mode_config_init(dev);
11268
11269         dev->mode_config.min_width = 0;
11270         dev->mode_config.min_height = 0;
11271
11272         dev->mode_config.preferred_depth = 24;
11273         dev->mode_config.prefer_shadow = 1;
11274
11275         dev->mode_config.funcs = &intel_mode_funcs;
11276
11277         intel_init_quirks(dev);
11278
11279         intel_init_pm(dev);
11280
11281         if (INTEL_INFO(dev)->num_pipes == 0)
11282                 return;
11283
11284         intel_init_display(dev);
11285
11286         if (IS_GEN2(dev)) {
11287                 dev->mode_config.max_width = 2048;
11288                 dev->mode_config.max_height = 2048;
11289         } else if (IS_GEN3(dev)) {
11290                 dev->mode_config.max_width = 4096;
11291                 dev->mode_config.max_height = 4096;
11292         } else {
11293                 dev->mode_config.max_width = 8192;
11294                 dev->mode_config.max_height = 8192;
11295         }
11296
11297         if (IS_GEN2(dev)) {
11298                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11299                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11300         } else {
11301                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11302                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11303         }
11304
11305         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11306
11307         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11308                       INTEL_INFO(dev)->num_pipes,
11309                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11310
11311         for_each_pipe(pipe) {
11312                 intel_crtc_init(dev, pipe);
11313                 for_each_sprite(pipe, sprite) {
11314                         ret = intel_plane_init(dev, pipe, sprite);
11315                         if (ret)
11316                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11317                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11318                 }
11319         }
11320
11321         intel_init_dpio(dev);
11322         intel_reset_dpio(dev);
11323
11324         intel_cpu_pll_init(dev);
11325         intel_shared_dpll_init(dev);
11326
11327         /* Just disable it once at startup */
11328         i915_disable_vga(dev);
11329         intel_setup_outputs(dev);
11330
11331         /* Just in case the BIOS is doing something questionable. */
11332         intel_disable_fbc(dev);
11333
11334         mutex_lock(&dev->mode_config.mutex);
11335         intel_modeset_setup_hw_state(dev, false);
11336         mutex_unlock(&dev->mode_config.mutex);
11337
11338         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11339                             base.head) {
11340                 if (!crtc->active)
11341                         continue;
11342
11343                 /*
11344                  * Note that reserving the BIOS fb up front prevents us
11345                  * from stuffing other stolen allocations like the ring
11346                  * on top.  This prevents some ugliness at boot time, and
11347                  * can even allow for smooth boot transitions if the BIOS
11348                  * fb is large enough for the active pipe configuration.
11349                  */
11350                 if (dev_priv->display.get_plane_config) {
11351                         dev_priv->display.get_plane_config(crtc,
11352                                                            &crtc->plane_config);
11353                         /*
11354                          * If the fb is shared between multiple heads, we'll
11355                          * just get the first one.
11356                          */
11357                         intel_find_plane_obj(crtc, &crtc->plane_config);
11358                 }
11359         }
11360 }
11361
11362 static void
11363 intel_connector_break_all_links(struct intel_connector *connector)
11364 {
11365         connector->base.dpms = DRM_MODE_DPMS_OFF;
11366         connector->base.encoder = NULL;
11367         connector->encoder->connectors_active = false;
11368         connector->encoder->base.crtc = NULL;
11369 }
11370
11371 static void intel_enable_pipe_a(struct drm_device *dev)
11372 {
11373         struct intel_connector *connector;
11374         struct drm_connector *crt = NULL;
11375         struct intel_load_detect_pipe load_detect_temp;
11376
11377         /* We can't just switch on the pipe A, we need to set things up with a
11378          * proper mode and output configuration. As a gross hack, enable pipe A
11379          * by enabling the load detect pipe once. */
11380         list_for_each_entry(connector,
11381                             &dev->mode_config.connector_list,
11382                             base.head) {
11383                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11384                         crt = &connector->base;
11385                         break;
11386                 }
11387         }
11388
11389         if (!crt)
11390                 return;
11391
11392         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11393                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11394
11395
11396 }
11397
11398 static bool
11399 intel_check_plane_mapping(struct intel_crtc *crtc)
11400 {
11401         struct drm_device *dev = crtc->base.dev;
11402         struct drm_i915_private *dev_priv = dev->dev_private;
11403         u32 reg, val;
11404
11405         if (INTEL_INFO(dev)->num_pipes == 1)
11406                 return true;
11407
11408         reg = DSPCNTR(!crtc->plane);
11409         val = I915_READ(reg);
11410
11411         if ((val & DISPLAY_PLANE_ENABLE) &&
11412             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11413                 return false;
11414
11415         return true;
11416 }
11417
11418 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11419 {
11420         struct drm_device *dev = crtc->base.dev;
11421         struct drm_i915_private *dev_priv = dev->dev_private;
11422         u32 reg;
11423
11424         /* Clear any frame start delays used for debugging left by the BIOS */
11425         reg = PIPECONF(crtc->config.cpu_transcoder);
11426         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11427
11428         /* We need to sanitize the plane -> pipe mapping first because this will
11429          * disable the crtc (and hence change the state) if it is wrong. Note
11430          * that gen4+ has a fixed plane -> pipe mapping.  */
11431         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11432                 struct intel_connector *connector;
11433                 bool plane;
11434
11435                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11436                               crtc->base.base.id);
11437
11438                 /* Pipe has the wrong plane attached and the plane is active.
11439                  * Temporarily change the plane mapping and disable everything
11440                  * ...  */
11441                 plane = crtc->plane;
11442                 crtc->plane = !plane;
11443                 dev_priv->display.crtc_disable(&crtc->base);
11444                 crtc->plane = plane;
11445
11446                 /* ... and break all links. */
11447                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11448                                     base.head) {
11449                         if (connector->encoder->base.crtc != &crtc->base)
11450                                 continue;
11451
11452                         intel_connector_break_all_links(connector);
11453                 }
11454
11455                 WARN_ON(crtc->active);
11456                 crtc->base.enabled = false;
11457         }
11458
11459         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11460             crtc->pipe == PIPE_A && !crtc->active) {
11461                 /* BIOS forgot to enable pipe A, this mostly happens after
11462                  * resume. Force-enable the pipe to fix this, the update_dpms
11463                  * call below we restore the pipe to the right state, but leave
11464                  * the required bits on. */
11465                 intel_enable_pipe_a(dev);
11466         }
11467
11468         /* Adjust the state of the output pipe according to whether we
11469          * have active connectors/encoders. */
11470         intel_crtc_update_dpms(&crtc->base);
11471
11472         if (crtc->active != crtc->base.enabled) {
11473                 struct intel_encoder *encoder;
11474
11475                 /* This can happen either due to bugs in the get_hw_state
11476                  * functions or because the pipe is force-enabled due to the
11477                  * pipe A quirk. */
11478                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11479                               crtc->base.base.id,
11480                               crtc->base.enabled ? "enabled" : "disabled",
11481                               crtc->active ? "enabled" : "disabled");
11482
11483                 crtc->base.enabled = crtc->active;
11484
11485                 /* Because we only establish the connector -> encoder ->
11486                  * crtc links if something is active, this means the
11487                  * crtc is now deactivated. Break the links. connector
11488                  * -> encoder links are only establish when things are
11489                  *  actually up, hence no need to break them. */
11490                 WARN_ON(crtc->active);
11491
11492                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11493                         WARN_ON(encoder->connectors_active);
11494                         encoder->base.crtc = NULL;
11495                 }
11496         }
11497         if (crtc->active) {
11498                 /*
11499                  * We start out with underrun reporting disabled to avoid races.
11500                  * For correct bookkeeping mark this on active crtcs.
11501                  *
11502                  * No protection against concurrent access is required - at
11503                  * worst a fifo underrun happens which also sets this to false.
11504                  */
11505                 crtc->cpu_fifo_underrun_disabled = true;
11506                 crtc->pch_fifo_underrun_disabled = true;
11507         }
11508 }
11509
11510 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11511 {
11512         struct intel_connector *connector;
11513         struct drm_device *dev = encoder->base.dev;
11514
11515         /* We need to check both for a crtc link (meaning that the
11516          * encoder is active and trying to read from a pipe) and the
11517          * pipe itself being active. */
11518         bool has_active_crtc = encoder->base.crtc &&
11519                 to_intel_crtc(encoder->base.crtc)->active;
11520
11521         if (encoder->connectors_active && !has_active_crtc) {
11522                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11523                               encoder->base.base.id,
11524                               drm_get_encoder_name(&encoder->base));
11525
11526                 /* Connector is active, but has no active pipe. This is
11527                  * fallout from our resume register restoring. Disable
11528                  * the encoder manually again. */
11529                 if (encoder->base.crtc) {
11530                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11531                                       encoder->base.base.id,
11532                                       drm_get_encoder_name(&encoder->base));
11533                         encoder->disable(encoder);
11534                 }
11535
11536                 /* Inconsistent output/port/pipe state happens presumably due to
11537                  * a bug in one of the get_hw_state functions. Or someplace else
11538                  * in our code, like the register restore mess on resume. Clamp
11539                  * things to off as a safer default. */
11540                 list_for_each_entry(connector,
11541                                     &dev->mode_config.connector_list,
11542                                     base.head) {
11543                         if (connector->encoder != encoder)
11544                                 continue;
11545
11546                         intel_connector_break_all_links(connector);
11547                 }
11548         }
11549         /* Enabled encoders without active connectors will be fixed in
11550          * the crtc fixup. */
11551 }
11552
11553 void i915_redisable_vga_power_on(struct drm_device *dev)
11554 {
11555         struct drm_i915_private *dev_priv = dev->dev_private;
11556         u32 vga_reg = i915_vgacntrl_reg(dev);
11557
11558         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11559                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11560                 i915_disable_vga(dev);
11561         }
11562 }
11563
11564 void i915_redisable_vga(struct drm_device *dev)
11565 {
11566         struct drm_i915_private *dev_priv = dev->dev_private;
11567
11568         /* This function can be called both from intel_modeset_setup_hw_state or
11569          * at a very early point in our resume sequence, where the power well
11570          * structures are not yet restored. Since this function is at a very
11571          * paranoid "someone might have enabled VGA while we were not looking"
11572          * level, just check if the power well is enabled instead of trying to
11573          * follow the "don't touch the power well if we don't need it" policy
11574          * the rest of the driver uses. */
11575         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11576                 return;
11577
11578         i915_redisable_vga_power_on(dev);
11579 }
11580
11581 static bool primary_get_hw_state(struct intel_crtc *crtc)
11582 {
11583         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11584
11585         if (!crtc->active)
11586                 return false;
11587
11588         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11589 }
11590
11591 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11592 {
11593         struct drm_i915_private *dev_priv = dev->dev_private;
11594         enum pipe pipe;
11595         struct intel_crtc *crtc;
11596         struct intel_encoder *encoder;
11597         struct intel_connector *connector;
11598         int i;
11599
11600         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11601                             base.head) {
11602                 memset(&crtc->config, 0, sizeof(crtc->config));
11603
11604                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11605
11606                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11607                                                                  &crtc->config);
11608
11609                 crtc->base.enabled = crtc->active;
11610                 crtc->primary_enabled = primary_get_hw_state(crtc);
11611
11612                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11613                               crtc->base.base.id,
11614                               crtc->active ? "enabled" : "disabled");
11615         }
11616
11617         /* FIXME: Smash this into the new shared dpll infrastructure. */
11618         if (HAS_DDI(dev))
11619                 intel_ddi_setup_hw_pll_state(dev);
11620
11621         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11622                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11623
11624                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11625                 pll->active = 0;
11626                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11627                                     base.head) {
11628                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11629                                 pll->active++;
11630                 }
11631                 pll->refcount = pll->active;
11632
11633                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11634                               pll->name, pll->refcount, pll->on);
11635         }
11636
11637         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11638                             base.head) {
11639                 pipe = 0;
11640
11641                 if (encoder->get_hw_state(encoder, &pipe)) {
11642                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11643                         encoder->base.crtc = &crtc->base;
11644                         encoder->get_config(encoder, &crtc->config);
11645                 } else {
11646                         encoder->base.crtc = NULL;
11647                 }
11648
11649                 encoder->connectors_active = false;
11650                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11651                               encoder->base.base.id,
11652                               drm_get_encoder_name(&encoder->base),
11653                               encoder->base.crtc ? "enabled" : "disabled",
11654                               pipe_name(pipe));
11655         }
11656
11657         list_for_each_entry(connector, &dev->mode_config.connector_list,
11658                             base.head) {
11659                 if (connector->get_hw_state(connector)) {
11660                         connector->base.dpms = DRM_MODE_DPMS_ON;
11661                         connector->encoder->connectors_active = true;
11662                         connector->base.encoder = &connector->encoder->base;
11663                 } else {
11664                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11665                         connector->base.encoder = NULL;
11666                 }
11667                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11668                               connector->base.base.id,
11669                               drm_get_connector_name(&connector->base),
11670                               connector->base.encoder ? "enabled" : "disabled");
11671         }
11672 }
11673
11674 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11675  * and i915 state tracking structures. */
11676 void intel_modeset_setup_hw_state(struct drm_device *dev,
11677                                   bool force_restore)
11678 {
11679         struct drm_i915_private *dev_priv = dev->dev_private;
11680         enum pipe pipe;
11681         struct intel_crtc *crtc;
11682         struct intel_encoder *encoder;
11683         int i;
11684
11685         intel_modeset_readout_hw_state(dev);
11686
11687         /*
11688          * Now that we have the config, copy it to each CRTC struct
11689          * Note that this could go away if we move to using crtc_config
11690          * checking everywhere.
11691          */
11692         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11693                             base.head) {
11694                 if (crtc->active && i915.fastboot) {
11695                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11696                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11697                                       crtc->base.base.id);
11698                         drm_mode_debug_printmodeline(&crtc->base.mode);
11699                 }
11700         }
11701
11702         /* HW state is read out, now we need to sanitize this mess. */
11703         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11704                             base.head) {
11705                 intel_sanitize_encoder(encoder);
11706         }
11707
11708         for_each_pipe(pipe) {
11709                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11710                 intel_sanitize_crtc(crtc);
11711                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11712         }
11713
11714         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11715                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11716
11717                 if (!pll->on || pll->active)
11718                         continue;
11719
11720                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11721
11722                 pll->disable(dev_priv, pll);
11723                 pll->on = false;
11724         }
11725
11726         if (HAS_PCH_SPLIT(dev))
11727                 ilk_wm_get_hw_state(dev);
11728
11729         if (force_restore) {
11730                 i915_redisable_vga(dev);
11731
11732                 /*
11733                  * We need to use raw interfaces for restoring state to avoid
11734                  * checking (bogus) intermediate states.
11735                  */
11736                 for_each_pipe(pipe) {
11737                         struct drm_crtc *crtc =
11738                                 dev_priv->pipe_to_crtc_mapping[pipe];
11739
11740                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11741                                          crtc->primary->fb);
11742                 }
11743         } else {
11744                 intel_modeset_update_staged_output_state(dev);
11745         }
11746
11747         intel_modeset_check_state(dev);
11748 }
11749
11750 void intel_modeset_gem_init(struct drm_device *dev)
11751 {
11752         struct drm_crtc *c;
11753         struct intel_framebuffer *fb;
11754
11755         mutex_lock(&dev->struct_mutex);
11756         intel_init_gt_powersave(dev);
11757         mutex_unlock(&dev->struct_mutex);
11758
11759         intel_modeset_init_hw(dev);
11760
11761         intel_setup_overlay(dev);
11762
11763         /*
11764          * Make sure any fbs we allocated at startup are properly
11765          * pinned & fenced.  When we do the allocation it's too early
11766          * for this.
11767          */
11768         mutex_lock(&dev->struct_mutex);
11769         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11770                 if (!c->primary->fb)
11771                         continue;
11772
11773                 fb = to_intel_framebuffer(c->primary->fb);
11774                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11775                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11776                                   to_intel_crtc(c)->pipe);
11777                         drm_framebuffer_unreference(c->primary->fb);
11778                         c->primary->fb = NULL;
11779                 }
11780         }
11781         mutex_unlock(&dev->struct_mutex);
11782 }
11783
11784 void intel_connector_unregister(struct intel_connector *intel_connector)
11785 {
11786         struct drm_connector *connector = &intel_connector->base;
11787
11788         intel_panel_destroy_backlight(connector);
11789         drm_sysfs_connector_remove(connector);
11790 }
11791
11792 void intel_modeset_cleanup(struct drm_device *dev)
11793 {
11794         struct drm_i915_private *dev_priv = dev->dev_private;
11795         struct drm_crtc *crtc;
11796         struct drm_connector *connector;
11797
11798         /*
11799          * Interrupts and polling as the first thing to avoid creating havoc.
11800          * Too much stuff here (turning of rps, connectors, ...) would
11801          * experience fancy races otherwise.
11802          */
11803         drm_irq_uninstall(dev);
11804         cancel_work_sync(&dev_priv->hotplug_work);
11805         /*
11806          * Due to the hpd irq storm handling the hotplug work can re-arm the
11807          * poll handlers. Hence disable polling after hpd handling is shut down.
11808          */
11809         drm_kms_helper_poll_fini(dev);
11810
11811         mutex_lock(&dev->struct_mutex);
11812
11813         intel_unregister_dsm_handler();
11814
11815         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11816                 /* Skip inactive CRTCs */
11817                 if (!crtc->primary->fb)
11818                         continue;
11819
11820                 intel_increase_pllclock(crtc);
11821         }
11822
11823         intel_disable_fbc(dev);
11824
11825         intel_disable_gt_powersave(dev);
11826
11827         ironlake_teardown_rc6(dev);
11828
11829         mutex_unlock(&dev->struct_mutex);
11830
11831         /* flush any delayed tasks or pending work */
11832         flush_scheduled_work();
11833
11834         /* destroy the backlight and sysfs files before encoders/connectors */
11835         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11836                 struct intel_connector *intel_connector;
11837
11838                 intel_connector = to_intel_connector(connector);
11839                 intel_connector->unregister(intel_connector);
11840         }
11841
11842         drm_mode_config_cleanup(dev);
11843
11844         intel_cleanup_overlay(dev);
11845
11846         mutex_lock(&dev->struct_mutex);
11847         intel_cleanup_gt_powersave(dev);
11848         mutex_unlock(&dev->struct_mutex);
11849 }
11850
11851 /*
11852  * Return which encoder is currently attached for connector.
11853  */
11854 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11855 {
11856         return &intel_attached_encoder(connector)->base;
11857 }
11858
11859 void intel_connector_attach_encoder(struct intel_connector *connector,
11860                                     struct intel_encoder *encoder)
11861 {
11862         connector->encoder = encoder;
11863         drm_mode_connector_attach_encoder(&connector->base,
11864                                           &encoder->base);
11865 }
11866
11867 /*
11868  * set vga decode state - true == enable VGA decode
11869  */
11870 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11871 {
11872         struct drm_i915_private *dev_priv = dev->dev_private;
11873         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11874         u16 gmch_ctrl;
11875
11876         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11877                 DRM_ERROR("failed to read control word\n");
11878                 return -EIO;
11879         }
11880
11881         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11882                 return 0;
11883
11884         if (state)
11885                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11886         else
11887                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11888
11889         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11890                 DRM_ERROR("failed to write control word\n");
11891                 return -EIO;
11892         }
11893
11894         return 0;
11895 }
11896
11897 struct intel_display_error_state {
11898
11899         u32 power_well_driver;
11900
11901         int num_transcoders;
11902
11903         struct intel_cursor_error_state {
11904                 u32 control;
11905                 u32 position;
11906                 u32 base;
11907                 u32 size;
11908         } cursor[I915_MAX_PIPES];
11909
11910         struct intel_pipe_error_state {
11911                 bool power_domain_on;
11912                 u32 source;
11913                 u32 stat;
11914         } pipe[I915_MAX_PIPES];
11915
11916         struct intel_plane_error_state {
11917                 u32 control;
11918                 u32 stride;
11919                 u32 size;
11920                 u32 pos;
11921                 u32 addr;
11922                 u32 surface;
11923                 u32 tile_offset;
11924         } plane[I915_MAX_PIPES];
11925
11926         struct intel_transcoder_error_state {
11927                 bool power_domain_on;
11928                 enum transcoder cpu_transcoder;
11929
11930                 u32 conf;
11931
11932                 u32 htotal;
11933                 u32 hblank;
11934                 u32 hsync;
11935                 u32 vtotal;
11936                 u32 vblank;
11937                 u32 vsync;
11938         } transcoder[4];
11939 };
11940
11941 struct intel_display_error_state *
11942 intel_display_capture_error_state(struct drm_device *dev)
11943 {
11944         struct drm_i915_private *dev_priv = dev->dev_private;
11945         struct intel_display_error_state *error;
11946         int transcoders[] = {
11947                 TRANSCODER_A,
11948                 TRANSCODER_B,
11949                 TRANSCODER_C,
11950                 TRANSCODER_EDP,
11951         };
11952         int i;
11953
11954         if (INTEL_INFO(dev)->num_pipes == 0)
11955                 return NULL;
11956
11957         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11958         if (error == NULL)
11959                 return NULL;
11960
11961         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11962                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11963
11964         for_each_pipe(i) {
11965                 error->pipe[i].power_domain_on =
11966                         intel_display_power_enabled_sw(dev_priv,
11967                                                        POWER_DOMAIN_PIPE(i));
11968                 if (!error->pipe[i].power_domain_on)
11969                         continue;
11970
11971                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11972                         error->cursor[i].control = I915_READ(CURCNTR(i));
11973                         error->cursor[i].position = I915_READ(CURPOS(i));
11974                         error->cursor[i].base = I915_READ(CURBASE(i));
11975                 } else {
11976                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11977                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11978                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11979                 }
11980
11981                 error->plane[i].control = I915_READ(DSPCNTR(i));
11982                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11983                 if (INTEL_INFO(dev)->gen <= 3) {
11984                         error->plane[i].size = I915_READ(DSPSIZE(i));
11985                         error->plane[i].pos = I915_READ(DSPPOS(i));
11986                 }
11987                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11988                         error->plane[i].addr = I915_READ(DSPADDR(i));
11989                 if (INTEL_INFO(dev)->gen >= 4) {
11990                         error->plane[i].surface = I915_READ(DSPSURF(i));
11991                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11992                 }
11993
11994                 error->pipe[i].source = I915_READ(PIPESRC(i));
11995
11996                 if (!HAS_PCH_SPLIT(dev))
11997                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
11998         }
11999
12000         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12001         if (HAS_DDI(dev_priv->dev))
12002                 error->num_transcoders++; /* Account for eDP. */
12003
12004         for (i = 0; i < error->num_transcoders; i++) {
12005                 enum transcoder cpu_transcoder = transcoders[i];
12006
12007                 error->transcoder[i].power_domain_on =
12008                         intel_display_power_enabled_sw(dev_priv,
12009                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12010                 if (!error->transcoder[i].power_domain_on)
12011                         continue;
12012
12013                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12014
12015                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12016                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12017                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12018                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12019                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12020                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12021                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12022         }
12023
12024         return error;
12025 }
12026
12027 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12028
12029 void
12030 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12031                                 struct drm_device *dev,
12032                                 struct intel_display_error_state *error)
12033 {
12034         int i;
12035
12036         if (!error)
12037                 return;
12038
12039         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12040         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12041                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12042                            error->power_well_driver);
12043         for_each_pipe(i) {
12044                 err_printf(m, "Pipe [%d]:\n", i);
12045                 err_printf(m, "  Power: %s\n",
12046                            error->pipe[i].power_domain_on ? "on" : "off");
12047                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12048                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12049
12050                 err_printf(m, "Plane [%d]:\n", i);
12051                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12052                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12053                 if (INTEL_INFO(dev)->gen <= 3) {
12054                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12055                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12056                 }
12057                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12058                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12059                 if (INTEL_INFO(dev)->gen >= 4) {
12060                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12061                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12062                 }
12063
12064                 err_printf(m, "Cursor [%d]:\n", i);
12065                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12066                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12067                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12068         }
12069
12070         for (i = 0; i < error->num_transcoders; i++) {
12071                 err_printf(m, "CPU transcoder: %c\n",
12072                            transcoder_name(error->transcoder[i].cpu_transcoder));
12073                 err_printf(m, "  Power: %s\n",
12074                            error->transcoder[i].power_domain_on ? "on" : "off");
12075                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12076                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12077                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12078                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12079                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12080                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12081                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12082         }
12083 }