2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
66 typedef struct intel_limit intel_limit_t;
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
76 intel_pch_rawclk(struct drm_device *dev)
78 struct drm_i915_private *dev_priv = dev->dev_private;
80 WARN_ON(!HAS_PCH_SPLIT(dev));
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
85 static inline u32 /* units of 100MHz */
86 intel_fdi_link_freq(struct drm_device *dev)
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
95 static const intel_limit_t intel_limits_i8xx_dac = {
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
134 static const intel_limit_t intel_limits_i9xx_sdvo = {
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
147 static const intel_limit_t intel_limits_i9xx_lvds = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
161 static const intel_limit_t intel_limits_g4x_sdvo = {
162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
176 static const intel_limit_t intel_limits_g4x_hdmi = {
177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
217 static const intel_limit_t intel_limits_pineview_sdvo = {
218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
220 /* Pineview's Ncounter is a ring counter */
221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
223 /* Pineview only has one combined m divider, which we treat as m2. */
224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
232 static const intel_limit_t intel_limits_pineview_lvds = {
233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
245 /* Ironlake / Sandybridge
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
250 static const intel_limit_t intel_limits_ironlake_dac = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
289 /* LVDS 100mhz refclk limits. */
290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
298 .p1 = { .min = 2, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
311 .p1 = { .min = 2, .max = 6 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
316 static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
324 .p1 = { .min = 1, .max = 3 },
325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
329 static const intel_limit_t intel_limits_vlv_hdmi = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
342 static const intel_limit_t intel_limits_vlv_dp = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 },
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 struct drm_device *dev = crtc->dev;
359 const intel_limit_t *limit;
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
362 if (intel_is_dual_link_lvds(dev)) {
363 if (refclk == 100000)
364 limit = &intel_limits_ironlake_dual_lvds_100m;
366 limit = &intel_limits_ironlake_dual_lvds;
368 if (refclk == 100000)
369 limit = &intel_limits_ironlake_single_lvds_100m;
371 limit = &intel_limits_ironlake_single_lvds;
374 limit = &intel_limits_ironlake_dac;
379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
385 if (intel_is_dual_link_lvds(dev))
386 limit = &intel_limits_g4x_dual_channel_lvds;
388 limit = &intel_limits_g4x_single_channel_lvds;
389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
391 limit = &intel_limits_g4x_hdmi;
392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
393 limit = &intel_limits_g4x_sdvo;
394 } else /* The option is for other outputs */
395 limit = &intel_limits_i9xx_sdvo;
400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
405 if (HAS_PCH_SPLIT(dev))
406 limit = intel_ironlake_limit(crtc, refclk);
407 else if (IS_G4X(dev)) {
408 limit = intel_g4x_limit(crtc);
409 } else if (IS_PINEVIEW(dev)) {
410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
411 limit = &intel_limits_pineview_lvds;
413 limit = &intel_limits_pineview_sdvo;
414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
420 limit = &intel_limits_vlv_dp;
421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
425 limit = &intel_limits_i9xx_sdvo;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_i8xx_lvds;
429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
430 limit = &intel_limits_i8xx_dvo;
432 limit = &intel_limits_i8xx_dac;
437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
438 static void pineview_clock(int refclk, intel_clock_t *clock)
440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
451 static void i9xx_clock(int refclk, intel_clock_t *clock)
453 clock->m = i9xx_dpll_compute_m(clock);
454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
460 * Returns whether any output on the specified pipe is of the specified type
462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
464 struct drm_device *dev = crtc->dev;
465 struct intel_encoder *encoder;
467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
474 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
480 static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
485 INTELPllInvalid("p1 out of range\n");
486 if (clock->p < limit->p.min || limit->p.max < clock->p)
487 INTELPllInvalid("p out of range\n");
488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
489 INTELPllInvalid("m2 out of range\n");
490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
491 INTELPllInvalid("m1 out of range\n");
492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
493 INTELPllInvalid("m1 <= m2\n");
494 if (clock->m < limit->m.min || limit->m.max < clock->m)
495 INTELPllInvalid("m out of range\n");
496 if (clock->n < limit->n.min || limit->n.max < clock->n)
497 INTELPllInvalid("n out of range\n");
498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
499 INTELPllInvalid("vco out of range\n");
500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
504 INTELPllInvalid("dot out of range\n");
510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
514 struct drm_device *dev = crtc->dev;
518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
524 if (intel_is_dual_link_lvds(dev))
525 clock.p2 = limit->p2.p2_fast;
527 clock.p2 = limit->p2.p2_slow;
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
532 clock.p2 = limit->p2.p2_fast;
535 memset(best_clock, 0, sizeof(*best_clock));
537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
541 if (clock.m2 >= clock.m1)
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
554 clock.p != match_clock->p)
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
567 return (err != target);
571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
575 struct drm_device *dev = crtc->dev;
579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
585 if (intel_is_dual_link_lvds(dev))
586 clock.p2 = limit->p2.p2_fast;
588 clock.p2 = limit->p2.p2_slow;
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
593 clock.p2 = limit->p2.p2_fast;
596 memset(best_clock, 0, sizeof(*best_clock));
598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
608 pineview_clock(refclk, &clock);
609 if (!intel_PLL_is_valid(dev, limit,
613 clock.p != match_clock->p)
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
626 return (err != target);
630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
634 struct drm_device *dev = crtc->dev;
638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (intel_is_dual_link_lvds(dev))
644 clock.p2 = limit->p2.p2_fast;
646 clock.p2 = limit->p2.p2_slow;
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
651 clock.p2 = limit->p2.p2_fast;
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
656 /* based on hardware requirement, prefer smaller n to precision */
657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
658 /* based on hardware requirement, prefere larger m1,m2 */
659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
667 i9xx_clock(refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
672 this_err = abs(clock.dot - target);
673 if (this_err < err_most) {
687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
693 u32 updrate, minupdate, p;
694 unsigned long bestppm, ppm, absppm;
698 dotclk = target * 1000;
701 fastclk = dotclk / (2*100);
704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
728 if (absppm < bestppm - 10) {
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
760 return intel_crtc->config.cpu_transcoder;
763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
768 frame = I915_READ(frame_reg);
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
775 * intel_wait_for_vblank - wait for vblank on a given pipe
777 * @pipe: pipe to wait for
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 int pipestat_reg = PIPESTAT(pipe);
787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
808 /* Wait for vblank interrupt bit to set */
809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
812 DRM_DEBUG_KMS("vblank wait timed out\n");
816 * intel_wait_for_pipe_off - wait for pipe to turn off
818 * @pipe: pipe to wait for
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
825 * wait for the pipe register state bit to turn off
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
838 if (INTEL_INFO(dev)->gen >= 4) {
839 int reg = PIPECONF(cpu_transcoder);
841 /* Wait for the Pipe State to go off */
842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
844 WARN(1, "pipe_off wait timed out\n");
846 u32 last_line, line_mask;
847 int reg = PIPEDSL(pipe);
848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
851 line_mask = DSL_LINEMASK_GEN2;
853 line_mask = DSL_LINEMASK_GEN3;
855 /* Wait for the display line to settle */
857 last_line = I915_READ(reg) & line_mask;
859 } while (((I915_READ(reg) & line_mask) != last_line) &&
860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
862 WARN(1, "pipe_off wait timed out\n");
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
871 * Returns true if @port is connected, false otherwise.
873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
878 if (HAS_PCH_IBX(dev_priv->dev)) {
881 bit = SDE_PORTB_HOTPLUG;
884 bit = SDE_PORTC_HOTPLUG;
887 bit = SDE_PORTD_HOTPLUG;
895 bit = SDE_PORTB_HOTPLUG_CPT;
898 bit = SDE_PORTC_HOTPLUG_CPT;
901 bit = SDE_PORTD_HOTPLUG_CPT;
908 return I915_READ(SDEISR) & bit;
911 static const char *state_string(bool enabled)
913 return enabled ? "on" : "off";
916 /* Only for pre-ILK configs */
917 void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
932 struct intel_shared_dpll *
933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
937 if (crtc->config.shared_dpll < 0)
940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
949 struct intel_dpll_hw_state hw_state;
951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 "asserting DPLL %s with no DPLL\n", state_string(state)))
960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
961 WARN(cur_state != state,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
978 val = I915_READ(reg);
979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv->dev))
1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1046 int pp_reg, lvds_reg;
1048 enum pipe panel_pipe = PIPE_A;
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1055 pp_reg = PP_CONTROL;
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe), state_string(state), state_string(cur_state));
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1120 struct drm_device *dev = dev_priv->dev;
1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1135 /* Need to check both planes against the pipe */
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1150 struct drm_device *dev = dev_priv->dev;
1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1164 val = I915_READ(reg);
1165 WARN((val & SPRITE_ENABLE),
1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
1170 val = I915_READ(reg);
1171 WARN((val & DVS_ENABLE),
1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(pipe), pipe_name(pipe));
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1200 reg = PCH_TRANSCONF(pipe);
1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
1211 if ((val & DP_PORT_EN) == 0)
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1229 if ((val & SDVO_ENABLE) == 0)
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1245 if ((val & LVDS_PORT_EN) == 0)
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, int reg, u32 port_sel)
1276 u32 val = I915_READ(reg);
1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279 reg, pipe_name(pipe));
1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
1283 "IBX PCH dp port still using transcoder B\n");
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1289 u32 val = I915_READ(reg);
1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292 reg, pipe_name(pipe));
1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295 && (val & SDVO_PIPE_B_SELECT),
1296 "IBX PCH hdmi port still using transcoder B\n");
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1310 val = I915_READ(reg);
1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
1316 val = I915_READ(reg);
1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
1333 assert_pipe_disabled(dev_priv, crtc->pipe);
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340 assert_panel_unlocked(dev_priv, crtc->pipe);
1342 I915_WRITE(reg, dpll);
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
1352 /* We do this three times for luck */
1353 I915_WRITE(reg, dpll);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg, dpll);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg, dpll);
1361 udelay(150); /* wait for warmup */
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
1371 assert_pipe_disabled(dev_priv, crtc->pipe);
1373 /* No really, not for ILK+ */
1374 BUG_ON(dev_priv->info->gen >= 5);
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
1380 I915_WRITE(reg, dpll);
1382 /* Wait for the clocks to stabilize. */
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1393 * So write it again.
1395 I915_WRITE(reg, dpll);
1398 /* We do this three times for luck */
1399 I915_WRITE(reg, dpll);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg, dpll);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg, dpll);
1407 udelay(150); /* wait for warmup */
1411 * i9xx_disable_pll - disable a PLL
1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1417 * Note! This is for pre-ILK only.
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
1432 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1439 port_mask = DPLL_PORTC_READY_MASK;
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1447 * ironlake_enable_shared_dpll - enable PCH PLL
1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1454 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1459 /* PCH PLLs only available on ILK, SNB and IVB */
1460 BUG_ON(dev_priv->info->gen < 5);
1461 if (WARN_ON(pll == NULL))
1464 if (WARN_ON(pll->refcount == 0))
1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
1469 crtc->base.base.id);
1471 if (pll->active++) {
1473 assert_shared_dpll_enabled(dev_priv, pll);
1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479 pll->enable(dev_priv, pll);
1483 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
1490 if (WARN_ON(pll == NULL))
1493 if (WARN_ON(pll->refcount == 0))
1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
1498 crtc->base.base.id);
1500 if (WARN_ON(pll->active == 0)) {
1501 assert_shared_dpll_disabled(dev_priv, pll);
1505 assert_shared_dpll_enabled(dev_priv, pll);
1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511 pll->disable(dev_priv, pll);
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1518 struct drm_device *dev = dev_priv->dev;
1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521 uint32_t reg, val, pipeconf_val;
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1526 /* Make sure PCH DPLL is enabled */
1527 assert_shared_dpll_enabled(dev_priv,
1528 intel_crtc_to_shared_dpll(intel_crtc));
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
1543 reg = PCH_TRANSCONF(pipe);
1544 val = I915_READ(reg);
1545 pipeconf_val = I915_READ(PIPECONF(pipe));
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1562 val |= TRANS_INTERLACED;
1564 val |= TRANS_PROGRESSIVE;
1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572 enum transcoder cpu_transcoder)
1574 u32 val, pipeconf_val;
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1579 /* FDI must be feeding us bits for PCH ports */
1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
1593 val |= TRANS_INTERLACED;
1595 val |= TRANS_PROGRESSIVE;
1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599 DRM_ERROR("Failed to enable PCH transcoder\n");
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1605 struct drm_device *dev = dev_priv->dev;
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1615 reg = PCH_TRANSCONF(pipe);
1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1636 val = I915_READ(LPT_TRANSCONF);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(LPT_TRANSCONF, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641 DRM_ERROR("Failed to disable PCH transcoder\n");
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1650 * intel_enable_pipe - enable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1658 * @pipe should be %PIPE_A or %PIPE_B.
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1663 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1668 enum pipe pch_transcoder;
1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1675 if (HAS_PCH_LPT(dev_priv->dev))
1676 pch_transcoder = TRANSCODER_A;
1678 pch_transcoder = pipe;
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
1686 assert_pll_enabled(dev_priv, pipe);
1689 /* if driving the PCH, we need FDI enabled */
1690 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1691 assert_fdi_tx_pll_enabled(dev_priv,
1692 (enum pipe) cpu_transcoder);
1694 /* FIXME: assert CPU port conditions for SNB+ */
1697 reg = PIPECONF(cpu_transcoder);
1698 val = I915_READ(reg);
1699 if (val & PIPECONF_ENABLE)
1702 I915_WRITE(reg, val | PIPECONF_ENABLE);
1703 intel_wait_for_vblank(dev_priv->dev, pipe);
1707 * intel_disable_pipe - disable a pipe, asserting requirements
1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe to disable
1711 * Disable @pipe, making sure that various hardware specific requirements
1712 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1714 * @pipe should be %PIPE_A or %PIPE_B.
1716 * Will wait until the pipe has shut down before returning.
1718 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1721 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 * Make sure planes won't keep trying to pump pixels to us,
1728 * or we might hang the display.
1730 assert_planes_disabled(dev_priv, pipe);
1731 assert_sprites_disabled(dev_priv, pipe);
1733 /* Don't disable pipe A or pipe A PLLs if needed */
1734 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1737 reg = PIPECONF(cpu_transcoder);
1738 val = I915_READ(reg);
1739 if ((val & PIPECONF_ENABLE) == 0)
1742 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1747 * Plane regs are double buffered, going from enabled->disabled needs a
1748 * trigger in order to latch. The display address reg provides this.
1750 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1753 if (dev_priv->info->gen >= 4)
1754 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1756 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1760 * intel_enable_plane - enable a display plane on a given pipe
1761 * @dev_priv: i915 private structure
1762 * @plane: plane to enable
1763 * @pipe: pipe being fed
1765 * Enable @plane on @pipe, making sure that @pipe is running first.
1767 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768 enum plane plane, enum pipe pipe)
1773 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774 assert_pipe_enabled(dev_priv, pipe);
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
1778 if (val & DISPLAY_PLANE_ENABLE)
1781 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1787 * intel_disable_plane - disable a display plane
1788 * @dev_priv: i915 private structure
1789 * @plane: plane to disable
1790 * @pipe: pipe consuming the data
1792 * Disable @plane; should be an independent operation.
1794 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795 enum plane plane, enum pipe pipe)
1800 reg = DSPCNTR(plane);
1801 val = I915_READ(reg);
1802 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1805 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806 intel_flush_display_plane(dev_priv, plane);
1807 intel_wait_for_vblank(dev_priv->dev, pipe);
1810 static bool need_vtd_wa(struct drm_device *dev)
1812 #ifdef CONFIG_INTEL_IOMMU
1813 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1820 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821 struct drm_i915_gem_object *obj,
1822 struct intel_ring_buffer *pipelined)
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1828 switch (obj->tiling_mode) {
1829 case I915_TILING_NONE:
1830 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831 alignment = 128 * 1024;
1832 else if (INTEL_INFO(dev)->gen >= 4)
1833 alignment = 4 * 1024;
1835 alignment = 64 * 1024;
1838 /* pin() will align the object as required by fence */
1842 /* Despite that we check this in framebuffer_init userspace can
1843 * screw us over and change the tiling after the fact. Only
1844 * pinned buffers can't change their tiling. */
1845 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1851 /* Note that the w/a also requires 64 PTE of padding following the
1852 * bo. We currently fill all unused PTE with the shadow page and so
1853 * we should always have valid PTE following the scanout preventing
1856 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857 alignment = 256 * 1024;
1859 dev_priv->mm.interruptible = false;
1860 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1862 goto err_interruptible;
1864 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865 * fence, whereas 965+ only requires a fence if using
1866 * framebuffer compression. For simplicity, we always install
1867 * a fence as the cost is not that onerous.
1869 ret = i915_gem_object_get_fence(obj);
1873 i915_gem_object_pin_fence(obj);
1875 dev_priv->mm.interruptible = true;
1879 i915_gem_object_unpin_from_display_plane(obj);
1881 dev_priv->mm.interruptible = true;
1885 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1887 i915_gem_object_unpin_fence(obj);
1888 i915_gem_object_unpin_from_display_plane(obj);
1891 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892 * is assumed to be a power-of-two. */
1893 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894 unsigned int tiling_mode,
1898 if (tiling_mode != I915_TILING_NONE) {
1899 unsigned int tile_rows, tiles;
1904 tiles = *x / (512/cpp);
1907 return tile_rows * pitch * 8 + tiles * 4096;
1909 unsigned int offset;
1911 offset = *y * pitch + *x * cpp;
1913 *x = (offset & 4095) / cpp;
1914 return offset & -4096;
1918 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1921 struct drm_device *dev = crtc->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924 struct intel_framebuffer *intel_fb;
1925 struct drm_i915_gem_object *obj;
1926 int plane = intel_crtc->plane;
1927 unsigned long linear_offset;
1936 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1940 intel_fb = to_intel_framebuffer(fb);
1941 obj = intel_fb->obj;
1943 reg = DSPCNTR(plane);
1944 dspcntr = I915_READ(reg);
1945 /* Mask out pixel format bits in case we change it */
1946 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947 switch (fb->pixel_format) {
1949 dspcntr |= DISPPLANE_8BPP;
1951 case DRM_FORMAT_XRGB1555:
1952 case DRM_FORMAT_ARGB1555:
1953 dspcntr |= DISPPLANE_BGRX555;
1955 case DRM_FORMAT_RGB565:
1956 dspcntr |= DISPPLANE_BGRX565;
1958 case DRM_FORMAT_XRGB8888:
1959 case DRM_FORMAT_ARGB8888:
1960 dspcntr |= DISPPLANE_BGRX888;
1962 case DRM_FORMAT_XBGR8888:
1963 case DRM_FORMAT_ABGR8888:
1964 dspcntr |= DISPPLANE_RGBX888;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 dspcntr |= DISPPLANE_BGRX101010;
1970 case DRM_FORMAT_XBGR2101010:
1971 case DRM_FORMAT_ABGR2101010:
1972 dspcntr |= DISPPLANE_RGBX101010;
1978 if (INTEL_INFO(dev)->gen >= 4) {
1979 if (obj->tiling_mode != I915_TILING_NONE)
1980 dspcntr |= DISPPLANE_TILED;
1982 dspcntr &= ~DISPPLANE_TILED;
1986 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1988 I915_WRITE(reg, dspcntr);
1990 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 intel_crtc->dspaddr_offset =
1994 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995 fb->bits_per_pixel / 8,
1997 linear_offset -= intel_crtc->dspaddr_offset;
1999 intel_crtc->dspaddr_offset = linear_offset;
2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2005 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006 if (INTEL_INFO(dev)->gen >= 4) {
2007 I915_MODIFY_DISPBASE(DSPSURF(plane),
2008 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010 I915_WRITE(DSPLINOFF(plane), linear_offset);
2012 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2018 static int ironlake_update_plane(struct drm_crtc *crtc,
2019 struct drm_framebuffer *fb, int x, int y)
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2037 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->pixel_format) {
2050 dspcntr |= DISPPLANE_8BPP;
2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2078 dspcntr &= ~DISPPLANE_TILED;
2080 if (IS_HASWELL(dev))
2081 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2083 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2085 I915_WRITE(reg, dspcntr);
2087 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2088 intel_crtc->dspaddr_offset =
2089 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2090 fb->bits_per_pixel / 8,
2092 linear_offset -= intel_crtc->dspaddr_offset;
2094 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2095 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2097 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2100 if (IS_HASWELL(dev)) {
2101 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2103 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2104 I915_WRITE(DSPLINOFF(plane), linear_offset);
2111 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2113 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2114 int x, int y, enum mode_set_atomic state)
2116 struct drm_device *dev = crtc->dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2119 if (dev_priv->display.disable_fbc)
2120 dev_priv->display.disable_fbc(dev);
2121 intel_increase_pllclock(crtc);
2123 return dev_priv->display.update_plane(crtc, fb, x, y);
2126 void intel_display_handle_reset(struct drm_device *dev)
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct drm_crtc *crtc;
2132 * Flips in the rings have been nuked by the reset,
2133 * so complete all pending flips so that user space
2134 * will get its events and not get stuck.
2136 * Also update the base address of all primary
2137 * planes to the the last fb to make sure we're
2138 * showing the correct fb after a reset.
2140 * Need to make two loops over the crtcs so that we
2141 * don't try to grab a crtc mutex before the
2142 * pending_flip_queue really got woken up.
2145 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2147 enum plane plane = intel_crtc->plane;
2149 intel_prepare_page_flip(dev, plane);
2150 intel_finish_page_flip_plane(dev, plane);
2153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156 mutex_lock(&crtc->mutex);
2157 if (intel_crtc->active)
2158 dev_priv->display.update_plane(crtc, crtc->fb,
2160 mutex_unlock(&crtc->mutex);
2165 intel_finish_fb(struct drm_framebuffer *old_fb)
2167 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2168 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2169 bool was_interruptible = dev_priv->mm.interruptible;
2172 /* Big Hammer, we also need to ensure that any pending
2173 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2174 * current scanout is retired before unpinning the old
2177 * This should only fail upon a hung GPU, in which case we
2178 * can safely continue.
2180 dev_priv->mm.interruptible = false;
2181 ret = i915_gem_object_finish_gpu(obj);
2182 dev_priv->mm.interruptible = was_interruptible;
2187 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2189 struct drm_device *dev = crtc->dev;
2190 struct drm_i915_master_private *master_priv;
2191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2193 if (!dev->primary->master)
2196 master_priv = dev->primary->master->driver_priv;
2197 if (!master_priv->sarea_priv)
2200 switch (intel_crtc->pipe) {
2202 master_priv->sarea_priv->pipeA_x = x;
2203 master_priv->sarea_priv->pipeA_y = y;
2206 master_priv->sarea_priv->pipeB_x = x;
2207 master_priv->sarea_priv->pipeB_y = y;
2215 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2216 struct drm_framebuffer *fb)
2218 struct drm_device *dev = crtc->dev;
2219 struct drm_i915_private *dev_priv = dev->dev_private;
2220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2221 struct drm_framebuffer *old_fb;
2226 DRM_ERROR("No FB bound\n");
2230 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2231 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2232 plane_name(intel_crtc->plane),
2233 INTEL_INFO(dev)->num_pipes);
2237 mutex_lock(&dev->struct_mutex);
2238 ret = intel_pin_and_fence_fb_obj(dev,
2239 to_intel_framebuffer(fb)->obj,
2242 mutex_unlock(&dev->struct_mutex);
2243 DRM_ERROR("pin & fence failed\n");
2247 /* Update pipe size and adjust fitter if needed */
2248 if (i915_fastboot) {
2249 I915_WRITE(PIPESRC(intel_crtc->pipe),
2250 ((crtc->mode.hdisplay - 1) << 16) |
2251 (crtc->mode.vdisplay - 1));
2252 if (!intel_crtc->config.pch_pfit.enabled &&
2253 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2254 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2255 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2256 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2257 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2261 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2263 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2264 mutex_unlock(&dev->struct_mutex);
2265 DRM_ERROR("failed to update base address\n");
2275 if (intel_crtc->active && old_fb != fb)
2276 intel_wait_for_vblank(dev, intel_crtc->pipe);
2277 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2280 intel_update_fbc(dev);
2281 intel_edp_psr_update(dev);
2282 mutex_unlock(&dev->struct_mutex);
2284 intel_crtc_update_sarea_pos(crtc, x, y);
2289 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294 int pipe = intel_crtc->pipe;
2297 /* enable normal train */
2298 reg = FDI_TX_CTL(pipe);
2299 temp = I915_READ(reg);
2300 if (IS_IVYBRIDGE(dev)) {
2301 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2302 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2304 temp &= ~FDI_LINK_TRAIN_NONE;
2305 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2307 I915_WRITE(reg, temp);
2309 reg = FDI_RX_CTL(pipe);
2310 temp = I915_READ(reg);
2311 if (HAS_PCH_CPT(dev)) {
2312 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2313 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2315 temp &= ~FDI_LINK_TRAIN_NONE;
2316 temp |= FDI_LINK_TRAIN_NONE;
2318 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2320 /* wait one idle pattern time */
2324 /* IVB wants error correction enabled */
2325 if (IS_IVYBRIDGE(dev))
2326 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2327 FDI_FE_ERRC_ENABLE);
2330 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2332 return crtc->base.enabled && crtc->active &&
2333 crtc->config.has_pch_encoder;
2336 static void ivb_modeset_global_resources(struct drm_device *dev)
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct intel_crtc *pipe_B_crtc =
2340 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2341 struct intel_crtc *pipe_C_crtc =
2342 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2346 * When everything is off disable fdi C so that we could enable fdi B
2347 * with all lanes. Note that we don't care about enabled pipes without
2348 * an enabled pch encoder.
2350 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2351 !pipe_has_enabled_pch(pipe_C_crtc)) {
2352 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2353 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2355 temp = I915_READ(SOUTH_CHICKEN1);
2356 temp &= ~FDI_BC_BIFURCATION_SELECT;
2357 DRM_DEBUG_KMS("disabling fdi C rx\n");
2358 I915_WRITE(SOUTH_CHICKEN1, temp);
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2390 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2407 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 reg = FDI_RX_IIR(pipe);
2410 for (tries = 0; tries < 5; tries++) {
2411 temp = I915_READ(reg);
2412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2414 if ((temp & FDI_RX_BIT_LOCK)) {
2415 DRM_DEBUG_KMS("FDI train 1 done.\n");
2416 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2421 DRM_ERROR("FDI train 1 fail!\n");
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
2428 I915_WRITE(reg, temp);
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
2434 I915_WRITE(reg, temp);
2439 reg = FDI_RX_IIR(pipe);
2440 for (tries = 0; tries < 5; tries++) {
2441 temp = I915_READ(reg);
2442 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2444 if (temp & FDI_RX_SYMBOL_LOCK) {
2445 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2446 DRM_DEBUG_KMS("FDI train 2 done.\n");
2451 DRM_ERROR("FDI train 2 fail!\n");
2453 DRM_DEBUG_KMS("FDI train done\n");
2457 static const int snb_b_fdi_train_param[] = {
2458 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2459 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2460 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2461 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 /* The FDI link training functions for SNB/Cougarpoint. */
2465 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2467 struct drm_device *dev = crtc->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470 int pipe = intel_crtc->pipe;
2471 u32 reg, temp, i, retry;
2473 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2475 reg = FDI_RX_IMR(pipe);
2476 temp = I915_READ(reg);
2477 temp &= ~FDI_RX_SYMBOL_LOCK;
2478 temp &= ~FDI_RX_BIT_LOCK;
2479 I915_WRITE(reg, temp);
2484 /* enable CPU FDI TX and PCH FDI RX */
2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2488 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2494 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2496 I915_WRITE(FDI_RX_MISC(pipe),
2497 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2499 reg = FDI_RX_CTL(pipe);
2500 temp = I915_READ(reg);
2501 if (HAS_PCH_CPT(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2505 temp &= ~FDI_LINK_TRAIN_NONE;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1;
2508 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513 for (i = 0; i < 4; i++) {
2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
2516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517 temp |= snb_b_fdi_train_param[i];
2518 I915_WRITE(reg, temp);
2523 for (retry = 0; retry < 5; retry++) {
2524 reg = FDI_RX_IIR(pipe);
2525 temp = I915_READ(reg);
2526 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2527 if (temp & FDI_RX_BIT_LOCK) {
2528 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2529 DRM_DEBUG_KMS("FDI train 1 done.\n");
2538 DRM_ERROR("FDI train 1 fail!\n");
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2550 I915_WRITE(reg, temp);
2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2561 I915_WRITE(reg, temp);
2566 for (i = 0; i < 4; i++) {
2567 reg = FDI_TX_CTL(pipe);
2568 temp = I915_READ(reg);
2569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2570 temp |= snb_b_fdi_train_param[i];
2571 I915_WRITE(reg, temp);
2576 for (retry = 0; retry < 5; retry++) {
2577 reg = FDI_RX_IIR(pipe);
2578 temp = I915_READ(reg);
2579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2580 if (temp & FDI_RX_SYMBOL_LOCK) {
2581 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2582 DRM_DEBUG_KMS("FDI train 2 done.\n");
2591 DRM_ERROR("FDI train 2 fail!\n");
2593 DRM_DEBUG_KMS("FDI train done.\n");
2596 /* Manual link training for Ivy Bridge A0 parts */
2597 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 int pipe = intel_crtc->pipe;
2603 u32 reg, temp, i, j;
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2607 reg = FDI_RX_IMR(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_RX_SYMBOL_LOCK;
2610 temp &= ~FDI_RX_BIT_LOCK;
2611 I915_WRITE(reg, temp);
2616 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2617 I915_READ(FDI_RX_IIR(pipe)));
2619 /* Try each vswing and preemphasis setting twice before moving on */
2620 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2621 /* disable first in case we need to retry */
2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp &= ~FDI_TX_ENABLE;
2626 I915_WRITE(reg, temp);
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_AUTO;
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp &= ~FDI_RX_ENABLE;
2633 I915_WRITE(reg, temp);
2635 /* enable CPU FDI TX and PCH FDI RX */
2636 reg = FDI_TX_CTL(pipe);
2637 temp = I915_READ(reg);
2638 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2639 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2640 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2641 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2642 temp |= snb_b_fdi_train_param[j/2];
2643 temp |= FDI_COMPOSITE_SYNC;
2644 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2646 I915_WRITE(FDI_RX_MISC(pipe),
2647 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2649 reg = FDI_RX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2652 temp |= FDI_COMPOSITE_SYNC;
2653 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2656 udelay(1); /* should be 0.5us */
2658 for (i = 0; i < 4; i++) {
2659 reg = FDI_RX_IIR(pipe);
2660 temp = I915_READ(reg);
2661 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2663 if (temp & FDI_RX_BIT_LOCK ||
2664 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2665 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2666 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2670 udelay(1); /* should be 0.5us */
2673 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682 I915_WRITE(reg, temp);
2684 reg = FDI_RX_CTL(pipe);
2685 temp = I915_READ(reg);
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688 I915_WRITE(reg, temp);
2691 udelay(2); /* should be 1.5us */
2693 for (i = 0; i < 4; i++) {
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698 if (temp & FDI_RX_SYMBOL_LOCK ||
2699 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2700 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2701 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2705 udelay(2); /* should be 1.5us */
2708 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2712 DRM_DEBUG_KMS("FDI train done.\n");
2715 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2717 struct drm_device *dev = intel_crtc->base.dev;
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 int pipe = intel_crtc->pipe;
2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2727 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734 /* Switch from Rawclk to PCDclk */
2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2741 /* Enable CPU FDI TX PLL, always on for Ironlake */
2742 reg = FDI_TX_CTL(pipe);
2743 temp = I915_READ(reg);
2744 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2745 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2752 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2754 struct drm_device *dev = intel_crtc->base.dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 int pipe = intel_crtc->pipe;
2759 /* Switch from PCDclk to Rawclk */
2760 reg = FDI_RX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2764 /* Disable CPU FDI TX PLL */
2765 reg = FDI_TX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2776 /* Wait for the clocks to turn off. */
2781 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 int pipe = intel_crtc->pipe;
2789 /* disable CPU FDI tx and PCH FDI rx */
2790 reg = FDI_TX_CTL(pipe);
2791 temp = I915_READ(reg);
2792 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795 reg = FDI_RX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~(0x7 << 16);
2798 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2799 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2804 /* Ironlake workaround, disable clock pointer after downing FDI */
2805 if (HAS_PCH_IBX(dev)) {
2806 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2809 /* still set train pattern 1 */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~FDI_LINK_TRAIN_NONE;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1;
2814 I915_WRITE(reg, temp);
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 if (HAS_PCH_CPT(dev)) {
2819 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2822 temp &= ~FDI_LINK_TRAIN_NONE;
2823 temp |= FDI_LINK_TRAIN_PATTERN_1;
2825 /* BPC in FDI rx is consistent with that in PIPECONF */
2826 temp &= ~(0x07 << 16);
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp);
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2836 struct drm_device *dev = crtc->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839 unsigned long flags;
2842 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2843 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2846 spin_lock_irqsave(&dev->event_lock, flags);
2847 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2848 spin_unlock_irqrestore(&dev->event_lock, flags);
2853 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 struct drm_device *dev = crtc->dev;
2856 struct drm_i915_private *dev_priv = dev->dev_private;
2858 if (crtc->fb == NULL)
2861 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2863 wait_event(dev_priv->pending_flip_queue,
2864 !intel_crtc_has_pending_flip(crtc));
2866 mutex_lock(&dev->struct_mutex);
2867 intel_finish_fb(crtc->fb);
2868 mutex_unlock(&dev->struct_mutex);
2871 /* Program iCLKIP clock to the desired frequency */
2872 static void lpt_program_iclkip(struct drm_crtc *crtc)
2874 struct drm_device *dev = crtc->dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2879 mutex_lock(&dev_priv->dpio_lock);
2881 /* It is necessary to ungate the pixclk gate prior to programming
2882 * the divisors, and gate it back when it is done.
2884 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2886 /* Disable SSCCTL */
2887 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2888 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2892 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2893 if (crtc->mode.clock == 20000) {
2898 /* The iCLK virtual clock root frequency is in MHz,
2899 * but the crtc->mode.clock in in KHz. To get the divisors,
2900 * it is necessary to divide one by another, so we
2901 * convert the virtual clock precision to KHz here for higher
2904 u32 iclk_virtual_root_freq = 172800 * 1000;
2905 u32 iclk_pi_range = 64;
2906 u32 desired_divisor, msb_divisor_value, pi_value;
2908 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2909 msb_divisor_value = desired_divisor / iclk_pi_range;
2910 pi_value = desired_divisor % iclk_pi_range;
2913 divsel = msb_divisor_value - 2;
2914 phaseinc = pi_value;
2917 /* This should not happen with any sane values */
2918 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2919 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2921 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2923 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2930 /* Program SSCDIVINTPHASE6 */
2931 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2932 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2933 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2934 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2935 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2936 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2937 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2938 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2940 /* Program SSCAUXDIV */
2941 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2942 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2943 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2944 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2946 /* Enable modulator and associated divider */
2947 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2948 temp &= ~SBI_SSCCTL_DISABLE;
2949 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2951 /* Wait for initialization time */
2954 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2956 mutex_unlock(&dev_priv->dpio_lock);
2959 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2960 enum pipe pch_transcoder)
2962 struct drm_device *dev = crtc->base.dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2966 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2967 I915_READ(HTOTAL(cpu_transcoder)));
2968 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2969 I915_READ(HBLANK(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2971 I915_READ(HSYNC(cpu_transcoder)));
2973 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2974 I915_READ(VTOTAL(cpu_transcoder)));
2975 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2976 I915_READ(VBLANK(cpu_transcoder)));
2977 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2978 I915_READ(VSYNC(cpu_transcoder)));
2979 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2980 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2983 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2988 temp = I915_READ(SOUTH_CHICKEN1);
2989 if (temp & FDI_BC_BIFURCATION_SELECT)
2992 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2993 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2995 temp |= FDI_BC_BIFURCATION_SELECT;
2996 DRM_DEBUG_KMS("enabling fdi C rx\n");
2997 I915_WRITE(SOUTH_CHICKEN1, temp);
2998 POSTING_READ(SOUTH_CHICKEN1);
3001 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3003 struct drm_device *dev = intel_crtc->base.dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3006 switch (intel_crtc->pipe) {
3010 if (intel_crtc->config.fdi_lanes > 2)
3011 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3013 cpt_enable_fdi_bc_bifurcation(dev);
3017 cpt_enable_fdi_bc_bifurcation(dev);
3026 * Enable PCH resources required for PCH ports:
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3033 static void ironlake_pch_enable(struct drm_crtc *crtc)
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
3041 assert_pch_transcoder_disabled(dev_priv, pipe);
3043 if (IS_IVYBRIDGE(dev))
3044 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3046 /* Write the TU size bits before fdi link training, so that error
3047 * detection works. */
3048 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3049 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3051 /* For PCH output, training FDI link */
3052 dev_priv->display.fdi_link_train(crtc);
3054 /* We need to program the right clock selection before writing the pixel
3055 * mutliplier into the DPLL. */
3056 if (HAS_PCH_CPT(dev)) {
3059 temp = I915_READ(PCH_DPLL_SEL);
3060 temp |= TRANS_DPLL_ENABLE(pipe);
3061 sel = TRANS_DPLLB_SEL(pipe);
3062 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3066 I915_WRITE(PCH_DPLL_SEL, temp);
3069 /* XXX: pch pll's can be enabled any time before we enable the PCH
3070 * transcoder, and we actually should do this to not upset any PCH
3071 * transcoder that already use the clock when we share it.
3073 * Note that enable_shared_dpll tries to do the right thing, but
3074 * get_shared_dpll unconditionally resets the pll - we need that to have
3075 * the right LVDS enable sequence. */
3076 ironlake_enable_shared_dpll(intel_crtc);
3078 /* set transcoder timing, panel must allow it */
3079 assert_panel_unlocked(dev_priv, pipe);
3080 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3082 intel_fdi_normal_train(crtc);
3084 /* For PCH DP, enable TRANS_DP_CTL */
3085 if (HAS_PCH_CPT(dev) &&
3086 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3087 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3088 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3089 reg = TRANS_DP_CTL(pipe);
3090 temp = I915_READ(reg);
3091 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3092 TRANS_DP_SYNC_MASK |
3094 temp |= (TRANS_DP_OUTPUT_ENABLE |
3095 TRANS_DP_ENH_FRAMING);
3096 temp |= bpc << 9; /* same format but at 11:9 */
3098 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3099 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3100 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3101 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3103 switch (intel_trans_dp_port_sel(crtc)) {
3105 temp |= TRANS_DP_PORT_SEL_B;
3108 temp |= TRANS_DP_PORT_SEL_C;
3111 temp |= TRANS_DP_PORT_SEL_D;
3117 I915_WRITE(reg, temp);
3120 ironlake_enable_pch_transcoder(dev_priv, pipe);
3123 static void lpt_pch_enable(struct drm_crtc *crtc)
3125 struct drm_device *dev = crtc->dev;
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3130 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3132 lpt_program_iclkip(crtc);
3134 /* Set transcoder timing. */
3135 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3137 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3140 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3142 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3147 if (pll->refcount == 0) {
3148 WARN(1, "bad %s refcount\n", pll->name);
3152 if (--pll->refcount == 0) {
3154 WARN_ON(pll->active);
3157 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3160 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3162 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3163 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3164 enum intel_dpll_id i;
3167 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3168 crtc->base.base.id, pll->name);
3169 intel_put_shared_dpll(crtc);
3172 if (HAS_PCH_IBX(dev_priv->dev)) {
3173 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3174 i = (enum intel_dpll_id) crtc->pipe;
3175 pll = &dev_priv->shared_dplls[i];
3177 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3178 crtc->base.base.id, pll->name);
3183 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3184 pll = &dev_priv->shared_dplls[i];
3186 /* Only want to check enabled timings first */
3187 if (pll->refcount == 0)
3190 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3191 sizeof(pll->hw_state)) == 0) {
3192 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3194 pll->name, pll->refcount, pll->active);
3200 /* Ok no matching timings, maybe there's a free one? */
3201 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3202 pll = &dev_priv->shared_dplls[i];
3203 if (pll->refcount == 0) {
3204 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3205 crtc->base.base.id, pll->name);
3213 crtc->config.shared_dpll = i;
3214 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3215 pipe_name(crtc->pipe));
3217 if (pll->active == 0) {
3218 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3219 sizeof(pll->hw_state));
3221 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3223 assert_shared_dpll_disabled(dev_priv, pll);
3225 pll->mode_set(dev_priv, pll);
3232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 int dslreg = PIPEDSL(pipe);
3238 temp = I915_READ(dslreg);
3240 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241 if (wait_for(I915_READ(dslreg) != temp, 5))
3242 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3248 struct drm_device *dev = crtc->base.dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int pipe = crtc->pipe;
3252 if (crtc->config.pch_pfit.enabled) {
3253 /* Force use of hard-coded filter coefficients
3254 * as some pre-programmed values are broken,
3257 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259 PF_PIPE_SEL_IVB(pipe));
3261 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3267 static void intel_enable_planes(struct drm_crtc *crtc)
3269 struct drm_device *dev = crtc->dev;
3270 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3271 struct intel_plane *intel_plane;
3273 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3274 if (intel_plane->pipe == pipe)
3275 intel_plane_restore(&intel_plane->base);
3278 static void intel_disable_planes(struct drm_crtc *crtc)
3280 struct drm_device *dev = crtc->dev;
3281 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3282 struct intel_plane *intel_plane;
3284 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3285 if (intel_plane->pipe == pipe)
3286 intel_plane_disable(&intel_plane->base);
3289 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294 struct intel_encoder *encoder;
3295 int pipe = intel_crtc->pipe;
3296 int plane = intel_crtc->plane;
3298 WARN_ON(!crtc->enabled);
3300 if (intel_crtc->active)
3303 intel_crtc->active = true;
3305 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3306 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3308 intel_update_watermarks(dev);
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 if (encoder->pre_enable)
3312 encoder->pre_enable(encoder);
3314 if (intel_crtc->config.has_pch_encoder) {
3315 /* Note: FDI PLL enabling _must_ be done before we enable the
3316 * cpu pipes, hence this is separate from all the other fdi/pch
3318 ironlake_fdi_pll_enable(intel_crtc);
3320 assert_fdi_tx_disabled(dev_priv, pipe);
3321 assert_fdi_rx_disabled(dev_priv, pipe);
3324 ironlake_pfit_enable(intel_crtc);
3327 * On ILK+ LUT must be loaded before the pipe is running but with
3330 intel_crtc_load_lut(crtc);
3332 intel_enable_pipe(dev_priv, pipe,
3333 intel_crtc->config.has_pch_encoder);
3334 intel_enable_plane(dev_priv, plane, pipe);
3335 intel_enable_planes(crtc);
3336 intel_crtc_update_cursor(crtc, true);
3338 if (intel_crtc->config.has_pch_encoder)
3339 ironlake_pch_enable(crtc);
3341 mutex_lock(&dev->struct_mutex);
3342 intel_update_fbc(dev);
3343 mutex_unlock(&dev->struct_mutex);
3345 for_each_encoder_on_crtc(dev, crtc, encoder)
3346 encoder->enable(encoder);
3348 if (HAS_PCH_CPT(dev))
3349 cpt_verify_modeset(dev, intel_crtc->pipe);
3352 * There seems to be a race in PCH platform hw (at least on some
3353 * outputs) where an enabled pipe still completes any pageflip right
3354 * away (as if the pipe is off) instead of waiting for vblank. As soon
3355 * as the first vblank happend, everything works as expected. Hence just
3356 * wait for one vblank before returning to avoid strange things
3359 intel_wait_for_vblank(dev, intel_crtc->pipe);
3362 /* IPS only exists on ULT machines and is tied to pipe A. */
3363 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3365 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3368 static void hsw_enable_ips(struct intel_crtc *crtc)
3370 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3372 if (!crtc->config.ips_enabled)
3375 /* We can only enable IPS after we enable a plane and wait for a vblank.
3376 * We guarantee that the plane is enabled by calling intel_enable_ips
3377 * only after intel_enable_plane. And intel_enable_plane already waits
3378 * for a vblank, so all we need to do here is to enable the IPS bit. */
3379 assert_plane_enabled(dev_priv, crtc->plane);
3380 I915_WRITE(IPS_CTL, IPS_ENABLE);
3383 static void hsw_disable_ips(struct intel_crtc *crtc)
3385 struct drm_device *dev = crtc->base.dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3388 if (!crtc->config.ips_enabled)
3391 assert_plane_enabled(dev_priv, crtc->plane);
3392 I915_WRITE(IPS_CTL, 0);
3394 /* We need to wait for a vblank before we can disable the plane. */
3395 intel_wait_for_vblank(dev, crtc->pipe);
3398 static void haswell_crtc_enable(struct drm_crtc *crtc)
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403 struct intel_encoder *encoder;
3404 int pipe = intel_crtc->pipe;
3405 int plane = intel_crtc->plane;
3407 WARN_ON(!crtc->enabled);
3409 if (intel_crtc->active)
3412 intel_crtc->active = true;
3414 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3415 if (intel_crtc->config.has_pch_encoder)
3416 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3418 intel_update_watermarks(dev);
3420 if (intel_crtc->config.has_pch_encoder)
3421 dev_priv->display.fdi_link_train(crtc);
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 if (encoder->pre_enable)
3425 encoder->pre_enable(encoder);
3427 intel_ddi_enable_pipe_clock(intel_crtc);
3429 ironlake_pfit_enable(intel_crtc);
3432 * On ILK+ LUT must be loaded before the pipe is running but with
3435 intel_crtc_load_lut(crtc);
3437 intel_ddi_set_pipe_settings(crtc);
3438 intel_ddi_enable_transcoder_func(crtc);
3440 intel_enable_pipe(dev_priv, pipe,
3441 intel_crtc->config.has_pch_encoder);
3442 intel_enable_plane(dev_priv, plane, pipe);
3443 intel_enable_planes(crtc);
3444 intel_crtc_update_cursor(crtc, true);
3446 hsw_enable_ips(intel_crtc);
3448 if (intel_crtc->config.has_pch_encoder)
3449 lpt_pch_enable(crtc);
3451 mutex_lock(&dev->struct_mutex);
3452 intel_update_fbc(dev);
3453 mutex_unlock(&dev->struct_mutex);
3455 for_each_encoder_on_crtc(dev, crtc, encoder)
3456 encoder->enable(encoder);
3459 * There seems to be a race in PCH platform hw (at least on some
3460 * outputs) where an enabled pipe still completes any pageflip right
3461 * away (as if the pipe is off) instead of waiting for vblank. As soon
3462 * as the first vblank happend, everything works as expected. Hence just
3463 * wait for one vblank before returning to avoid strange things
3466 intel_wait_for_vblank(dev, intel_crtc->pipe);
3469 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3471 struct drm_device *dev = crtc->base.dev;
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 int pipe = crtc->pipe;
3475 /* To avoid upsetting the power well on haswell only disable the pfit if
3476 * it's in use. The hw state code will make sure we get this right. */
3477 if (crtc->config.pch_pfit.enabled) {
3478 I915_WRITE(PF_CTL(pipe), 0);
3479 I915_WRITE(PF_WIN_POS(pipe), 0);
3480 I915_WRITE(PF_WIN_SZ(pipe), 0);
3484 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3489 struct intel_encoder *encoder;
3490 int pipe = intel_crtc->pipe;
3491 int plane = intel_crtc->plane;
3495 if (!intel_crtc->active)
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->disable(encoder);
3501 intel_crtc_wait_for_pending_flips(crtc);
3502 drm_vblank_off(dev, pipe);
3504 if (dev_priv->fbc.plane == plane)
3505 intel_disable_fbc(dev);
3507 intel_crtc_update_cursor(crtc, false);
3508 intel_disable_planes(crtc);
3509 intel_disable_plane(dev_priv, plane, pipe);
3511 if (intel_crtc->config.has_pch_encoder)
3512 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3514 intel_disable_pipe(dev_priv, pipe);
3516 ironlake_pfit_disable(intel_crtc);
3518 for_each_encoder_on_crtc(dev, crtc, encoder)
3519 if (encoder->post_disable)
3520 encoder->post_disable(encoder);
3522 if (intel_crtc->config.has_pch_encoder) {
3523 ironlake_fdi_disable(crtc);
3525 ironlake_disable_pch_transcoder(dev_priv, pipe);
3526 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3528 if (HAS_PCH_CPT(dev)) {
3529 /* disable TRANS_DP_CTL */
3530 reg = TRANS_DP_CTL(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3533 TRANS_DP_PORT_SEL_MASK);
3534 temp |= TRANS_DP_PORT_SEL_NONE;
3535 I915_WRITE(reg, temp);
3537 /* disable DPLL_SEL */
3538 temp = I915_READ(PCH_DPLL_SEL);
3539 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3540 I915_WRITE(PCH_DPLL_SEL, temp);
3543 /* disable PCH DPLL */
3544 intel_disable_shared_dpll(intel_crtc);
3546 ironlake_fdi_pll_disable(intel_crtc);
3549 intel_crtc->active = false;
3550 intel_update_watermarks(dev);
3552 mutex_lock(&dev->struct_mutex);
3553 intel_update_fbc(dev);
3554 mutex_unlock(&dev->struct_mutex);
3557 static void haswell_crtc_disable(struct drm_crtc *crtc)
3559 struct drm_device *dev = crtc->dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 struct intel_encoder *encoder;
3563 int pipe = intel_crtc->pipe;
3564 int plane = intel_crtc->plane;
3565 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3567 if (!intel_crtc->active)
3570 for_each_encoder_on_crtc(dev, crtc, encoder)
3571 encoder->disable(encoder);
3573 intel_crtc_wait_for_pending_flips(crtc);
3574 drm_vblank_off(dev, pipe);
3576 /* FBC must be disabled before disabling the plane on HSW. */
3577 if (dev_priv->fbc.plane == plane)
3578 intel_disable_fbc(dev);
3580 hsw_disable_ips(intel_crtc);
3582 intel_crtc_update_cursor(crtc, false);
3583 intel_disable_planes(crtc);
3584 intel_disable_plane(dev_priv, plane, pipe);
3586 if (intel_crtc->config.has_pch_encoder)
3587 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3588 intel_disable_pipe(dev_priv, pipe);
3590 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3592 ironlake_pfit_disable(intel_crtc);
3594 intel_ddi_disable_pipe_clock(intel_crtc);
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 if (encoder->post_disable)
3598 encoder->post_disable(encoder);
3600 if (intel_crtc->config.has_pch_encoder) {
3601 lpt_disable_pch_transcoder(dev_priv);
3602 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3603 intel_ddi_fdi_disable(crtc);
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3614 static void ironlake_crtc_off(struct drm_crtc *crtc)
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_shared_dpll(intel_crtc);
3620 static void haswell_crtc_off(struct drm_crtc *crtc)
3622 intel_ddi_put_crtc_pll(crtc);
3625 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3627 if (!enable && intel_crtc->overlay) {
3628 struct drm_device *dev = intel_crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3631 mutex_lock(&dev->struct_mutex);
3632 dev_priv->mm.interruptible = false;
3633 (void) intel_overlay_switch_off(intel_crtc->overlay);
3634 dev_priv->mm.interruptible = true;
3635 mutex_unlock(&dev->struct_mutex);
3638 /* Let userspace switch the overlay on again. In most cases userspace
3639 * has to recompute where to put it anyway.
3644 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3645 * cursor plane briefly if not already running after enabling the display
3647 * This workaround avoids occasional blank screens when self refresh is
3651 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3653 u32 cntl = I915_READ(CURCNTR(pipe));
3655 if ((cntl & CURSOR_MODE) == 0) {
3656 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3658 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3659 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3660 intel_wait_for_vblank(dev_priv->dev, pipe);
3661 I915_WRITE(CURCNTR(pipe), cntl);
3662 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3663 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3669 struct drm_device *dev = crtc->base.dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 struct intel_crtc_config *pipe_config = &crtc->config;
3673 if (!crtc->config.gmch_pfit.control)
3677 * The panel fitter should only be adjusted whilst the pipe is disabled,
3678 * according to register description and PRM.
3680 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3681 assert_pipe_disabled(dev_priv, crtc->pipe);
3683 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3684 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3686 /* Border color in case we don't scale up to the full screen. Black by
3687 * default, change to something else for debugging. */
3688 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3691 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696 struct intel_encoder *encoder;
3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
3700 WARN_ON(!crtc->enabled);
3702 if (intel_crtc->active)
3705 intel_crtc->active = true;
3706 intel_update_watermarks(dev);
3708 for_each_encoder_on_crtc(dev, crtc, encoder)
3709 if (encoder->pre_pll_enable)
3710 encoder->pre_pll_enable(encoder);
3712 vlv_enable_pll(intel_crtc);
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 if (encoder->pre_enable)
3716 encoder->pre_enable(encoder);
3718 i9xx_pfit_enable(intel_crtc);
3720 intel_crtc_load_lut(crtc);
3722 intel_enable_pipe(dev_priv, pipe, false);
3723 intel_enable_plane(dev_priv, plane, pipe);
3724 intel_enable_planes(crtc);
3725 intel_crtc_update_cursor(crtc, true);
3727 intel_update_fbc(dev);
3729 for_each_encoder_on_crtc(dev, crtc, encoder)
3730 encoder->enable(encoder);
3733 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3738 struct intel_encoder *encoder;
3739 int pipe = intel_crtc->pipe;
3740 int plane = intel_crtc->plane;
3742 WARN_ON(!crtc->enabled);
3744 if (intel_crtc->active)
3747 intel_crtc->active = true;
3748 intel_update_watermarks(dev);
3750 for_each_encoder_on_crtc(dev, crtc, encoder)
3751 if (encoder->pre_enable)
3752 encoder->pre_enable(encoder);
3754 i9xx_enable_pll(intel_crtc);
3756 i9xx_pfit_enable(intel_crtc);
3758 intel_crtc_load_lut(crtc);
3760 intel_enable_pipe(dev_priv, pipe, false);
3761 intel_enable_plane(dev_priv, plane, pipe);
3762 intel_enable_planes(crtc);
3763 /* The fixup needs to happen before cursor is enabled */
3765 g4x_fixup_plane(dev_priv, pipe);
3766 intel_crtc_update_cursor(crtc, true);
3768 /* Give the overlay scaler a chance to enable if it's on this pipe */
3769 intel_crtc_dpms_overlay(intel_crtc, true);
3771 intel_update_fbc(dev);
3773 for_each_encoder_on_crtc(dev, crtc, encoder)
3774 encoder->enable(encoder);
3777 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3779 struct drm_device *dev = crtc->base.dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3782 if (!crtc->config.gmch_pfit.control)
3785 assert_pipe_disabled(dev_priv, crtc->pipe);
3787 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3788 I915_READ(PFIT_CONTROL));
3789 I915_WRITE(PFIT_CONTROL, 0);
3792 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 struct intel_encoder *encoder;
3798 int pipe = intel_crtc->pipe;
3799 int plane = intel_crtc->plane;
3801 if (!intel_crtc->active)
3804 for_each_encoder_on_crtc(dev, crtc, encoder)
3805 encoder->disable(encoder);
3807 /* Give the overlay scaler a chance to disable if it's on this pipe */
3808 intel_crtc_wait_for_pending_flips(crtc);
3809 drm_vblank_off(dev, pipe);
3811 if (dev_priv->fbc.plane == plane)
3812 intel_disable_fbc(dev);
3814 intel_crtc_dpms_overlay(intel_crtc, false);
3815 intel_crtc_update_cursor(crtc, false);
3816 intel_disable_planes(crtc);
3817 intel_disable_plane(dev_priv, plane, pipe);
3819 intel_disable_pipe(dev_priv, pipe);
3821 i9xx_pfit_disable(intel_crtc);
3823 for_each_encoder_on_crtc(dev, crtc, encoder)
3824 if (encoder->post_disable)
3825 encoder->post_disable(encoder);
3827 i9xx_disable_pll(dev_priv, pipe);
3829 intel_crtc->active = false;
3830 intel_update_fbc(dev);
3831 intel_update_watermarks(dev);
3834 static void i9xx_crtc_off(struct drm_crtc *crtc)
3838 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_master_private *master_priv;
3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844 int pipe = intel_crtc->pipe;
3846 if (!dev->primary->master)
3849 master_priv = dev->primary->master->driver_priv;
3850 if (!master_priv->sarea_priv)
3855 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3856 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3859 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3860 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3863 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3869 * Sets the power management mode of the pipe and plane.
3871 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 struct intel_encoder *intel_encoder;
3876 bool enable = false;
3878 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3879 enable |= intel_encoder->connectors_active;
3882 dev_priv->display.crtc_enable(crtc);
3884 dev_priv->display.crtc_disable(crtc);
3886 intel_crtc_update_sarea(crtc, enable);
3889 static void intel_crtc_disable(struct drm_crtc *crtc)
3891 struct drm_device *dev = crtc->dev;
3892 struct drm_connector *connector;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3896 /* crtc should still be enabled when we disable it. */
3897 WARN_ON(!crtc->enabled);
3899 dev_priv->display.crtc_disable(crtc);
3900 intel_crtc->eld_vld = false;
3901 intel_crtc_update_sarea(crtc, false);
3902 dev_priv->display.off(crtc);
3904 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3905 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3908 mutex_lock(&dev->struct_mutex);
3909 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3910 mutex_unlock(&dev->struct_mutex);
3914 /* Update computed state. */
3915 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3916 if (!connector->encoder || !connector->encoder->crtc)
3919 if (connector->encoder->crtc != crtc)
3922 connector->dpms = DRM_MODE_DPMS_OFF;
3923 to_intel_encoder(connector->encoder)->connectors_active = false;
3927 void intel_encoder_destroy(struct drm_encoder *encoder)
3929 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3931 drm_encoder_cleanup(encoder);
3932 kfree(intel_encoder);
3935 /* Simple dpms helper for encoders with just one connector, no cloning and only
3936 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3937 * state of the entire output pipe. */
3938 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3940 if (mode == DRM_MODE_DPMS_ON) {
3941 encoder->connectors_active = true;
3943 intel_crtc_update_dpms(encoder->base.crtc);
3945 encoder->connectors_active = false;
3947 intel_crtc_update_dpms(encoder->base.crtc);
3951 /* Cross check the actual hw state with our own modeset state tracking (and it's
3952 * internal consistency). */
3953 static void intel_connector_check_state(struct intel_connector *connector)
3955 if (connector->get_hw_state(connector)) {
3956 struct intel_encoder *encoder = connector->encoder;
3957 struct drm_crtc *crtc;
3958 bool encoder_enabled;
3961 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3962 connector->base.base.id,
3963 drm_get_connector_name(&connector->base));
3965 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3966 "wrong connector dpms state\n");
3967 WARN(connector->base.encoder != &encoder->base,
3968 "active connector not linked to encoder\n");
3969 WARN(!encoder->connectors_active,
3970 "encoder->connectors_active not set\n");
3972 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3973 WARN(!encoder_enabled, "encoder not enabled\n");
3974 if (WARN_ON(!encoder->base.crtc))
3977 crtc = encoder->base.crtc;
3979 WARN(!crtc->enabled, "crtc not enabled\n");
3980 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3981 WARN(pipe != to_intel_crtc(crtc)->pipe,
3982 "encoder active on the wrong pipe\n");
3986 /* Even simpler default implementation, if there's really no special case to
3988 void intel_connector_dpms(struct drm_connector *connector, int mode)
3990 /* All the simple cases only support two dpms states. */
3991 if (mode != DRM_MODE_DPMS_ON)
3992 mode = DRM_MODE_DPMS_OFF;
3994 if (mode == connector->dpms)
3997 connector->dpms = mode;
3999 /* Only need to change hw state when actually enabled */
4000 if (connector->encoder)
4001 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4003 intel_modeset_check_state(connector->dev);
4006 /* Simple connector->get_hw_state implementation for encoders that support only
4007 * one connector and no cloning and hence the encoder state determines the state
4008 * of the connector. */
4009 bool intel_connector_get_hw_state(struct intel_connector *connector)
4012 struct intel_encoder *encoder = connector->encoder;
4014 return encoder->get_hw_state(encoder, &pipe);
4017 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4018 struct intel_crtc_config *pipe_config)
4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021 struct intel_crtc *pipe_B_crtc =
4022 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4024 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4025 pipe_name(pipe), pipe_config->fdi_lanes);
4026 if (pipe_config->fdi_lanes > 4) {
4027 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4028 pipe_name(pipe), pipe_config->fdi_lanes);
4032 if (IS_HASWELL(dev)) {
4033 if (pipe_config->fdi_lanes > 2) {
4034 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4035 pipe_config->fdi_lanes);
4042 if (INTEL_INFO(dev)->num_pipes == 2)
4045 /* Ivybridge 3 pipe is really complicated */
4050 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4051 pipe_config->fdi_lanes > 2) {
4052 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4053 pipe_name(pipe), pipe_config->fdi_lanes);
4058 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4059 pipe_B_crtc->config.fdi_lanes <= 2) {
4060 if (pipe_config->fdi_lanes > 2) {
4061 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4062 pipe_name(pipe), pipe_config->fdi_lanes);
4066 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4076 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4077 struct intel_crtc_config *pipe_config)
4079 struct drm_device *dev = intel_crtc->base.dev;
4080 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4081 int lane, link_bw, fdi_dotclock;
4082 bool setup_ok, needs_recompute = false;
4085 /* FDI is a binary signal running at ~2.7GHz, encoding
4086 * each output octet as 10 bits. The actual frequency
4087 * is stored as a divider into a 100MHz clock, and the
4088 * mode pixel clock is stored in units of 1KHz.
4089 * Hence the bw of each lane in terms of the mode signal
4092 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4094 fdi_dotclock = adjusted_mode->clock;
4095 fdi_dotclock /= pipe_config->pixel_multiplier;
4097 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4098 pipe_config->pipe_bpp);
4100 pipe_config->fdi_lanes = lane;
4102 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4103 link_bw, &pipe_config->fdi_m_n);
4105 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4106 intel_crtc->pipe, pipe_config);
4107 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4108 pipe_config->pipe_bpp -= 2*3;
4109 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4110 pipe_config->pipe_bpp);
4111 needs_recompute = true;
4112 pipe_config->bw_constrained = true;
4117 if (needs_recompute)
4120 return setup_ok ? 0 : -EINVAL;
4123 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4124 struct intel_crtc_config *pipe_config)
4126 pipe_config->ips_enabled = i915_enable_ips &&
4127 hsw_crtc_supports_ips(crtc) &&
4128 pipe_config->pipe_bpp <= 24;
4131 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4132 struct intel_crtc_config *pipe_config)
4134 struct drm_device *dev = crtc->base.dev;
4135 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4137 if (HAS_PCH_SPLIT(dev)) {
4138 /* FDI link clock is fixed at 2.7G */
4139 if (pipe_config->requested_mode.clock * 3
4140 > IRONLAKE_FDI_FREQ * 4)
4144 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4145 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4147 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4148 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4151 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4152 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4153 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4154 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4156 pipe_config->pipe_bpp = 8*3;
4160 hsw_compute_ips_config(crtc, pipe_config);
4162 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4163 * clock survives for now. */
4164 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4165 pipe_config->shared_dpll = crtc->config.shared_dpll;
4167 if (pipe_config->has_pch_encoder)
4168 return ironlake_fdi_compute_config(crtc, pipe_config);
4173 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4175 return 400000; /* FIXME */
4178 static int i945_get_display_clock_speed(struct drm_device *dev)
4183 static int i915_get_display_clock_speed(struct drm_device *dev)
4188 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4193 static int pnv_get_display_clock_speed(struct drm_device *dev)
4197 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4199 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4200 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4202 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4204 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4206 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4209 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4210 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4212 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4217 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4221 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4223 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4226 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4227 case GC_DISPLAY_CLOCK_333_MHZ:
4230 case GC_DISPLAY_CLOCK_190_200_MHZ:
4236 static int i865_get_display_clock_speed(struct drm_device *dev)
4241 static int i855_get_display_clock_speed(struct drm_device *dev)
4244 /* Assume that the hardware is in the high speed state. This
4245 * should be the default.
4247 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4248 case GC_CLOCK_133_200:
4249 case GC_CLOCK_100_200:
4251 case GC_CLOCK_166_250:
4253 case GC_CLOCK_100_133:
4257 /* Shouldn't happen */
4261 static int i830_get_display_clock_speed(struct drm_device *dev)
4267 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4269 while (*num > DATA_LINK_M_N_MASK ||
4270 *den > DATA_LINK_M_N_MASK) {
4276 static void compute_m_n(unsigned int m, unsigned int n,
4277 uint32_t *ret_m, uint32_t *ret_n)
4279 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4280 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4281 intel_reduce_m_n_ratio(ret_m, ret_n);
4285 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4286 int pixel_clock, int link_clock,
4287 struct intel_link_m_n *m_n)
4291 compute_m_n(bits_per_pixel * pixel_clock,
4292 link_clock * nlanes * 8,
4293 &m_n->gmch_m, &m_n->gmch_n);
4295 compute_m_n(pixel_clock, link_clock,
4296 &m_n->link_m, &m_n->link_n);
4299 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4301 if (i915_panel_use_ssc >= 0)
4302 return i915_panel_use_ssc != 0;
4303 return dev_priv->vbt.lvds_use_ssc
4304 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4307 static int vlv_get_refclk(struct drm_crtc *crtc)
4309 struct drm_device *dev = crtc->dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 int refclk = 27000; /* for DP & HDMI */
4313 return 100000; /* only one validated so far */
4315 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4317 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4318 if (intel_panel_use_ssc(dev_priv))
4322 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4329 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4331 struct drm_device *dev = crtc->dev;
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4335 if (IS_VALLEYVIEW(dev)) {
4336 refclk = vlv_get_refclk(crtc);
4337 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4338 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4339 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4340 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4342 } else if (!IS_GEN2(dev)) {
4351 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4353 return (1 << dpll->n) << 16 | dpll->m2;
4356 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4358 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4361 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4362 intel_clock_t *reduced_clock)
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 int pipe = crtc->pipe;
4369 if (IS_PINEVIEW(dev)) {
4370 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4372 fp2 = pnv_dpll_compute_fp(reduced_clock);
4374 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4376 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4379 I915_WRITE(FP0(pipe), fp);
4380 crtc->config.dpll_hw_state.fp0 = fp;
4382 crtc->lowfreq_avail = false;
4383 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4384 reduced_clock && i915_powersave) {
4385 I915_WRITE(FP1(pipe), fp2);
4386 crtc->config.dpll_hw_state.fp1 = fp2;
4387 crtc->lowfreq_avail = true;
4389 I915_WRITE(FP1(pipe), fp);
4390 crtc->config.dpll_hw_state.fp1 = fp;
4394 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4399 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4400 * and set it to a reasonable value instead.
4402 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4403 reg_val &= 0xffffff00;
4404 reg_val |= 0x00000030;
4405 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4407 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4408 reg_val &= 0x8cffffff;
4409 reg_val = 0x8c000000;
4410 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4412 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4413 reg_val &= 0xffffff00;
4414 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4416 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4417 reg_val &= 0x00ffffff;
4418 reg_val |= 0xb0000000;
4419 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4422 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4423 struct intel_link_m_n *m_n)
4425 struct drm_device *dev = crtc->base.dev;
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 int pipe = crtc->pipe;
4429 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4430 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4431 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4432 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4435 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4436 struct intel_link_m_n *m_n)
4438 struct drm_device *dev = crtc->base.dev;
4439 struct drm_i915_private *dev_priv = dev->dev_private;
4440 int pipe = crtc->pipe;
4441 enum transcoder transcoder = crtc->config.cpu_transcoder;
4443 if (INTEL_INFO(dev)->gen >= 5) {
4444 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4445 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4446 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4447 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4449 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4450 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4451 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4452 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4456 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4458 if (crtc->config.has_pch_encoder)
4459 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4461 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4464 static void vlv_update_pll(struct intel_crtc *crtc)
4466 struct drm_device *dev = crtc->base.dev;
4467 struct drm_i915_private *dev_priv = dev->dev_private;
4468 int pipe = crtc->pipe;
4470 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4471 u32 coreclk, reg_val, dpll_md;
4473 mutex_lock(&dev_priv->dpio_lock);
4475 bestn = crtc->config.dpll.n;
4476 bestm1 = crtc->config.dpll.m1;
4477 bestm2 = crtc->config.dpll.m2;
4478 bestp1 = crtc->config.dpll.p1;
4479 bestp2 = crtc->config.dpll.p2;
4481 /* See eDP HDMI DPIO driver vbios notes doc */
4483 /* PLL B needs special handling */
4485 vlv_pllb_recal_opamp(dev_priv);
4487 /* Set up Tx target for periodic Rcomp update */
4488 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4490 /* Disable target IRef on PLL */
4491 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4492 reg_val &= 0x00ffffff;
4493 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4495 /* Disable fast lock */
4496 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4498 /* Set idtafcrecal before PLL is enabled */
4499 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4500 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4501 mdiv |= ((bestn << DPIO_N_SHIFT));
4502 mdiv |= (1 << DPIO_K_SHIFT);
4505 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4506 * but we don't support that).
4507 * Note: don't use the DAC post divider as it seems unstable.
4509 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4510 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4512 mdiv |= DPIO_ENABLE_CALIBRATION;
4513 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4515 /* Set HBR and RBR LPF coefficients */
4516 if (crtc->config.port_clock == 162000 ||
4517 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4518 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4519 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4522 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4525 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4526 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4527 /* Use SSC source */
4529 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4532 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4534 } else { /* HDMI or VGA */
4535 /* Use bend source */
4537 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4540 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4544 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4545 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4546 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4547 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4548 coreclk |= 0x01000000;
4549 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4551 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4553 /* Enable DPIO clock input */
4554 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4555 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4557 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4559 dpll |= DPLL_VCO_ENABLE;
4560 crtc->config.dpll_hw_state.dpll = dpll;
4562 dpll_md = (crtc->config.pixel_multiplier - 1)
4563 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4564 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4566 if (crtc->config.has_dp_encoder)
4567 intel_dp_set_m_n(crtc);
4569 mutex_unlock(&dev_priv->dpio_lock);
4572 static void i9xx_update_pll(struct intel_crtc *crtc,
4573 intel_clock_t *reduced_clock,
4576 struct drm_device *dev = crtc->base.dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct dpll *clock = &crtc->config.dpll;
4582 i9xx_update_pll_dividers(crtc, reduced_clock);
4584 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4585 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4587 dpll = DPLL_VGA_MODE_DIS;
4589 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4590 dpll |= DPLLB_MODE_LVDS;
4592 dpll |= DPLLB_MODE_DAC_SERIAL;
4594 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4595 dpll |= (crtc->config.pixel_multiplier - 1)
4596 << SDVO_MULTIPLIER_SHIFT_HIRES;
4600 dpll |= DPLL_SDVO_HIGH_SPEED;
4602 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4603 dpll |= DPLL_SDVO_HIGH_SPEED;
4605 /* compute bitmask from p1 value */
4606 if (IS_PINEVIEW(dev))
4607 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4609 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4610 if (IS_G4X(dev) && reduced_clock)
4611 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4613 switch (clock->p2) {
4615 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4618 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4621 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4624 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4627 if (INTEL_INFO(dev)->gen >= 4)
4628 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4630 if (crtc->config.sdvo_tv_clock)
4631 dpll |= PLL_REF_INPUT_TVCLKINBC;
4632 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4633 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4634 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4636 dpll |= PLL_REF_INPUT_DREFCLK;
4638 dpll |= DPLL_VCO_ENABLE;
4639 crtc->config.dpll_hw_state.dpll = dpll;
4641 if (INTEL_INFO(dev)->gen >= 4) {
4642 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4643 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4644 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4647 if (crtc->config.has_dp_encoder)
4648 intel_dp_set_m_n(crtc);
4651 static void i8xx_update_pll(struct intel_crtc *crtc,
4652 intel_clock_t *reduced_clock,
4655 struct drm_device *dev = crtc->base.dev;
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct dpll *clock = &crtc->config.dpll;
4660 i9xx_update_pll_dividers(crtc, reduced_clock);
4662 dpll = DPLL_VGA_MODE_DIS;
4664 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4665 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4668 dpll |= PLL_P1_DIVIDE_BY_TWO;
4670 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4672 dpll |= PLL_P2_DIVIDE_BY_4;
4675 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4676 dpll |= DPLL_DVO_2X_MODE;
4678 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4679 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4680 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4682 dpll |= PLL_REF_INPUT_DREFCLK;
4684 dpll |= DPLL_VCO_ENABLE;
4685 crtc->config.dpll_hw_state.dpll = dpll;
4688 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4690 struct drm_device *dev = intel_crtc->base.dev;
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4692 enum pipe pipe = intel_crtc->pipe;
4693 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4694 struct drm_display_mode *adjusted_mode =
4695 &intel_crtc->config.adjusted_mode;
4696 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4697 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4699 /* We need to be careful not to changed the adjusted mode, for otherwise
4700 * the hw state checker will get angry at the mismatch. */
4701 crtc_vtotal = adjusted_mode->crtc_vtotal;
4702 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4704 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4705 /* the chip adds 2 halflines automatically */
4707 crtc_vblank_end -= 1;
4708 vsyncshift = adjusted_mode->crtc_hsync_start
4709 - adjusted_mode->crtc_htotal / 2;
4714 if (INTEL_INFO(dev)->gen > 3)
4715 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4717 I915_WRITE(HTOTAL(cpu_transcoder),
4718 (adjusted_mode->crtc_hdisplay - 1) |
4719 ((adjusted_mode->crtc_htotal - 1) << 16));
4720 I915_WRITE(HBLANK(cpu_transcoder),
4721 (adjusted_mode->crtc_hblank_start - 1) |
4722 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4723 I915_WRITE(HSYNC(cpu_transcoder),
4724 (adjusted_mode->crtc_hsync_start - 1) |
4725 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4727 I915_WRITE(VTOTAL(cpu_transcoder),
4728 (adjusted_mode->crtc_vdisplay - 1) |
4729 ((crtc_vtotal - 1) << 16));
4730 I915_WRITE(VBLANK(cpu_transcoder),
4731 (adjusted_mode->crtc_vblank_start - 1) |
4732 ((crtc_vblank_end - 1) << 16));
4733 I915_WRITE(VSYNC(cpu_transcoder),
4734 (adjusted_mode->crtc_vsync_start - 1) |
4735 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4737 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4738 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4739 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4741 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4742 (pipe == PIPE_B || pipe == PIPE_C))
4743 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4745 /* pipesrc controls the size that is scaled from, which should
4746 * always be the user's requested size.
4748 I915_WRITE(PIPESRC(pipe),
4749 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4752 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4753 struct intel_crtc_config *pipe_config)
4755 struct drm_device *dev = crtc->base.dev;
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4760 tmp = I915_READ(HTOTAL(cpu_transcoder));
4761 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4763 tmp = I915_READ(HBLANK(cpu_transcoder));
4764 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4765 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4766 tmp = I915_READ(HSYNC(cpu_transcoder));
4767 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4768 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4770 tmp = I915_READ(VTOTAL(cpu_transcoder));
4771 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4772 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4773 tmp = I915_READ(VBLANK(cpu_transcoder));
4774 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4775 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4776 tmp = I915_READ(VSYNC(cpu_transcoder));
4777 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4778 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4780 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4781 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4782 pipe_config->adjusted_mode.crtc_vtotal += 1;
4783 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4786 tmp = I915_READ(PIPESRC(crtc->pipe));
4787 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4788 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4791 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4792 struct intel_crtc_config *pipe_config)
4794 struct drm_crtc *crtc = &intel_crtc->base;
4796 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4797 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4798 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4799 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4801 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4802 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4803 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4804 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4806 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4808 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4809 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4812 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4814 struct drm_device *dev = intel_crtc->base.dev;
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4820 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4821 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4822 pipeconf |= PIPECONF_ENABLE;
4824 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4825 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4828 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4831 if (intel_crtc->config.requested_mode.clock >
4832 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4833 pipeconf |= PIPECONF_DOUBLE_WIDE;
4836 /* only g4x and later have fancy bpc/dither controls */
4837 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4838 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4839 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4840 pipeconf |= PIPECONF_DITHER_EN |
4841 PIPECONF_DITHER_TYPE_SP;
4843 switch (intel_crtc->config.pipe_bpp) {
4845 pipeconf |= PIPECONF_6BPC;
4848 pipeconf |= PIPECONF_8BPC;
4851 pipeconf |= PIPECONF_10BPC;
4854 /* Case prevented by intel_choose_pipe_bpp_dither. */
4859 if (HAS_PIPE_CXSR(dev)) {
4860 if (intel_crtc->lowfreq_avail) {
4861 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4862 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4864 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4868 if (!IS_GEN2(dev) &&
4869 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4870 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4872 pipeconf |= PIPECONF_PROGRESSIVE;
4874 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4875 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4877 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4878 POSTING_READ(PIPECONF(intel_crtc->pipe));
4881 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4883 struct drm_framebuffer *fb)
4885 struct drm_device *dev = crtc->dev;
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4888 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4889 int pipe = intel_crtc->pipe;
4890 int plane = intel_crtc->plane;
4891 int refclk, num_connectors = 0;
4892 intel_clock_t clock, reduced_clock;
4894 bool ok, has_reduced_clock = false;
4895 bool is_lvds = false;
4896 struct intel_encoder *encoder;
4897 const intel_limit_t *limit;
4900 for_each_encoder_on_crtc(dev, crtc, encoder) {
4901 switch (encoder->type) {
4902 case INTEL_OUTPUT_LVDS:
4910 refclk = i9xx_get_refclk(crtc, num_connectors);
4913 * Returns a set of divisors for the desired target clock with the given
4914 * refclk, or FALSE. The returned values represent the clock equation:
4915 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4917 limit = intel_limit(crtc, refclk);
4918 ok = dev_priv->display.find_dpll(limit, crtc,
4919 intel_crtc->config.port_clock,
4920 refclk, NULL, &clock);
4921 if (!ok && !intel_crtc->config.clock_set) {
4922 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4926 if (is_lvds && dev_priv->lvds_downclock_avail) {
4928 * Ensure we match the reduced clock's P to the target clock.
4929 * If the clocks don't match, we can't switch the display clock
4930 * by using the FP0/FP1. In such case we will disable the LVDS
4931 * downclock feature.
4934 dev_priv->display.find_dpll(limit, crtc,
4935 dev_priv->lvds_downclock,
4939 /* Compat-code for transition, will disappear. */
4940 if (!intel_crtc->config.clock_set) {
4941 intel_crtc->config.dpll.n = clock.n;
4942 intel_crtc->config.dpll.m1 = clock.m1;
4943 intel_crtc->config.dpll.m2 = clock.m2;
4944 intel_crtc->config.dpll.p1 = clock.p1;
4945 intel_crtc->config.dpll.p2 = clock.p2;
4949 i8xx_update_pll(intel_crtc,
4950 has_reduced_clock ? &reduced_clock : NULL,
4952 else if (IS_VALLEYVIEW(dev))
4953 vlv_update_pll(intel_crtc);
4955 i9xx_update_pll(intel_crtc,
4956 has_reduced_clock ? &reduced_clock : NULL,
4959 /* Set up the display plane register */
4960 dspcntr = DISPPLANE_GAMMA_ENABLE;
4962 if (!IS_VALLEYVIEW(dev)) {
4964 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4966 dspcntr |= DISPPLANE_SEL_PIPE_B;
4969 intel_set_pipe_timings(intel_crtc);
4971 /* pipesrc and dspsize control the size that is scaled from,
4972 * which should always be the user's requested size.
4974 I915_WRITE(DSPSIZE(plane),
4975 ((mode->vdisplay - 1) << 16) |
4976 (mode->hdisplay - 1));
4977 I915_WRITE(DSPPOS(plane), 0);
4979 i9xx_set_pipeconf(intel_crtc);
4981 I915_WRITE(DSPCNTR(plane), dspcntr);
4982 POSTING_READ(DSPCNTR(plane));
4984 ret = intel_pipe_set_base(crtc, x, y, fb);
4986 intel_update_watermarks(dev);
4991 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4992 struct intel_crtc_config *pipe_config)
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4998 tmp = I915_READ(PFIT_CONTROL);
4999 if (!(tmp & PFIT_ENABLE))
5002 /* Check whether the pfit is attached to our pipe. */
5003 if (INTEL_INFO(dev)->gen < 4) {
5004 if (crtc->pipe != PIPE_B)
5007 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5011 pipe_config->gmch_pfit.control = tmp;
5012 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5013 if (INTEL_INFO(dev)->gen < 5)
5014 pipe_config->gmch_pfit.lvds_border_bits =
5015 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5018 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5019 struct intel_crtc_config *pipe_config)
5021 struct drm_device *dev = crtc->base.dev;
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5025 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5026 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5028 tmp = I915_READ(PIPECONF(crtc->pipe));
5029 if (!(tmp & PIPECONF_ENABLE))
5032 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5033 switch (tmp & PIPECONF_BPC_MASK) {
5035 pipe_config->pipe_bpp = 18;
5038 pipe_config->pipe_bpp = 24;
5040 case PIPECONF_10BPC:
5041 pipe_config->pipe_bpp = 30;
5048 intel_get_pipe_timings(crtc, pipe_config);
5050 i9xx_get_pfit_config(crtc, pipe_config);
5052 if (INTEL_INFO(dev)->gen >= 4) {
5053 tmp = I915_READ(DPLL_MD(crtc->pipe));
5054 pipe_config->pixel_multiplier =
5055 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5056 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5057 pipe_config->dpll_hw_state.dpll_md = tmp;
5058 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5059 tmp = I915_READ(DPLL(crtc->pipe));
5060 pipe_config->pixel_multiplier =
5061 ((tmp & SDVO_MULTIPLIER_MASK)
5062 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5064 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5065 * port and will be fixed up in the encoder->get_config
5067 pipe_config->pixel_multiplier = 1;
5069 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5070 if (!IS_VALLEYVIEW(dev)) {
5071 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5072 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5074 /* Mask out read-only status bits. */
5075 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5076 DPLL_PORTC_READY_MASK |
5077 DPLL_PORTB_READY_MASK);
5083 static void ironlake_init_pch_refclk(struct drm_device *dev)
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 struct drm_mode_config *mode_config = &dev->mode_config;
5087 struct intel_encoder *encoder;
5089 bool has_lvds = false;
5090 bool has_cpu_edp = false;
5091 bool has_panel = false;
5092 bool has_ck505 = false;
5093 bool can_ssc = false;
5095 /* We need to take the global config into account */
5096 list_for_each_entry(encoder, &mode_config->encoder_list,
5098 switch (encoder->type) {
5099 case INTEL_OUTPUT_LVDS:
5103 case INTEL_OUTPUT_EDP:
5105 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5111 if (HAS_PCH_IBX(dev)) {
5112 has_ck505 = dev_priv->vbt.display_clock_mode;
5113 can_ssc = has_ck505;
5119 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5120 has_panel, has_lvds, has_ck505);
5122 /* Ironlake: try to setup display ref clock before DPLL
5123 * enabling. This is only under driver's control after
5124 * PCH B stepping, previous chipset stepping should be
5125 * ignoring this setting.
5127 val = I915_READ(PCH_DREF_CONTROL);
5129 /* As we must carefully and slowly disable/enable each source in turn,
5130 * compute the final state we want first and check if we need to
5131 * make any changes at all.
5134 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5136 final |= DREF_NONSPREAD_CK505_ENABLE;
5138 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5140 final &= ~DREF_SSC_SOURCE_MASK;
5141 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5142 final &= ~DREF_SSC1_ENABLE;
5145 final |= DREF_SSC_SOURCE_ENABLE;
5147 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5148 final |= DREF_SSC1_ENABLE;
5151 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5152 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5154 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5156 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5158 final |= DREF_SSC_SOURCE_DISABLE;
5159 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5165 /* Always enable nonspread source */
5166 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5169 val |= DREF_NONSPREAD_CK505_ENABLE;
5171 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5174 val &= ~DREF_SSC_SOURCE_MASK;
5175 val |= DREF_SSC_SOURCE_ENABLE;
5177 /* SSC must be turned on before enabling the CPU output */
5178 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5179 DRM_DEBUG_KMS("Using SSC on panel\n");
5180 val |= DREF_SSC1_ENABLE;
5182 val &= ~DREF_SSC1_ENABLE;
5184 /* Get SSC going before enabling the outputs */
5185 I915_WRITE(PCH_DREF_CONTROL, val);
5186 POSTING_READ(PCH_DREF_CONTROL);
5189 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5191 /* Enable CPU source on CPU attached eDP */
5193 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5194 DRM_DEBUG_KMS("Using SSC on eDP\n");
5195 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5198 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5200 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5202 I915_WRITE(PCH_DREF_CONTROL, val);
5203 POSTING_READ(PCH_DREF_CONTROL);
5206 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5208 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5210 /* Turn off CPU output */
5211 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5213 I915_WRITE(PCH_DREF_CONTROL, val);
5214 POSTING_READ(PCH_DREF_CONTROL);
5217 /* Turn off the SSC source */
5218 val &= ~DREF_SSC_SOURCE_MASK;
5219 val |= DREF_SSC_SOURCE_DISABLE;
5222 val &= ~DREF_SSC1_ENABLE;
5224 I915_WRITE(PCH_DREF_CONTROL, val);
5225 POSTING_READ(PCH_DREF_CONTROL);
5229 BUG_ON(val != final);
5232 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5236 tmp = I915_READ(SOUTH_CHICKEN2);
5237 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5238 I915_WRITE(SOUTH_CHICKEN2, tmp);
5240 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5241 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5242 DRM_ERROR("FDI mPHY reset assert timeout\n");
5244 tmp = I915_READ(SOUTH_CHICKEN2);
5245 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5246 I915_WRITE(SOUTH_CHICKEN2, tmp);
5248 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5249 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5250 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5253 /* WaMPhyProgramming:hsw */
5254 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5258 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5259 tmp &= ~(0xFF << 24);
5260 tmp |= (0x12 << 24);
5261 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5263 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5265 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5267 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5269 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5271 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5272 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5273 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5275 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5276 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5277 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5279 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5282 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5284 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5287 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5289 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5292 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5294 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5297 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5299 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5300 tmp &= ~(0xFF << 16);
5301 tmp |= (0x1C << 16);
5302 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5304 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5305 tmp &= ~(0xFF << 16);
5306 tmp |= (0x1C << 16);
5307 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5309 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5311 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5313 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5315 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5317 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5318 tmp &= ~(0xF << 28);
5320 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5322 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5323 tmp &= ~(0xF << 28);
5325 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5328 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5329 * Programming" based on the parameters passed:
5330 * - Sequence to enable CLKOUT_DP
5331 * - Sequence to enable CLKOUT_DP without spread
5332 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5334 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5340 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5342 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5343 with_fdi, "LP PCH doesn't have FDI\n"))
5346 mutex_lock(&dev_priv->dpio_lock);
5348 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5349 tmp &= ~SBI_SSCCTL_DISABLE;
5350 tmp |= SBI_SSCCTL_PATHALT;
5351 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5356 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5357 tmp &= ~SBI_SSCCTL_PATHALT;
5358 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5361 lpt_reset_fdi_mphy(dev_priv);
5362 lpt_program_fdi_mphy(dev_priv);
5366 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5367 SBI_GEN0 : SBI_DBUFF0;
5368 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5369 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5370 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5372 mutex_unlock(&dev_priv->dpio_lock);
5375 /* Sequence to disable CLKOUT_DP */
5376 static void lpt_disable_clkout_dp(struct drm_device *dev)
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5381 mutex_lock(&dev_priv->dpio_lock);
5383 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5384 SBI_GEN0 : SBI_DBUFF0;
5385 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5386 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5387 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5389 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5390 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5391 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5392 tmp |= SBI_SSCCTL_PATHALT;
5393 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5396 tmp |= SBI_SSCCTL_DISABLE;
5397 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5400 mutex_unlock(&dev_priv->dpio_lock);
5403 static void lpt_init_pch_refclk(struct drm_device *dev)
5405 struct drm_mode_config *mode_config = &dev->mode_config;
5406 struct intel_encoder *encoder;
5407 bool has_vga = false;
5409 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5410 switch (encoder->type) {
5411 case INTEL_OUTPUT_ANALOG:
5418 lpt_enable_clkout_dp(dev, true, true);
5420 lpt_disable_clkout_dp(dev);
5424 * Initialize reference clocks when the driver loads
5426 void intel_init_pch_refclk(struct drm_device *dev)
5428 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5429 ironlake_init_pch_refclk(dev);
5430 else if (HAS_PCH_LPT(dev))
5431 lpt_init_pch_refclk(dev);
5434 static int ironlake_get_refclk(struct drm_crtc *crtc)
5436 struct drm_device *dev = crtc->dev;
5437 struct drm_i915_private *dev_priv = dev->dev_private;
5438 struct intel_encoder *encoder;
5439 int num_connectors = 0;
5440 bool is_lvds = false;
5442 for_each_encoder_on_crtc(dev, crtc, encoder) {
5443 switch (encoder->type) {
5444 case INTEL_OUTPUT_LVDS:
5451 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5452 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5453 dev_priv->vbt.lvds_ssc_freq);
5454 return dev_priv->vbt.lvds_ssc_freq * 1000;
5460 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5462 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464 int pipe = intel_crtc->pipe;
5469 switch (intel_crtc->config.pipe_bpp) {
5471 val |= PIPECONF_6BPC;
5474 val |= PIPECONF_8BPC;
5477 val |= PIPECONF_10BPC;
5480 val |= PIPECONF_12BPC;
5483 /* Case prevented by intel_choose_pipe_bpp_dither. */
5487 if (intel_crtc->config.dither)
5488 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5490 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5491 val |= PIPECONF_INTERLACED_ILK;
5493 val |= PIPECONF_PROGRESSIVE;
5495 if (intel_crtc->config.limited_color_range)
5496 val |= PIPECONF_COLOR_RANGE_SELECT;
5498 I915_WRITE(PIPECONF(pipe), val);
5499 POSTING_READ(PIPECONF(pipe));
5503 * Set up the pipe CSC unit.
5505 * Currently only full range RGB to limited range RGB conversion
5506 * is supported, but eventually this should handle various
5507 * RGB<->YCbCr scenarios as well.
5509 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5511 struct drm_device *dev = crtc->dev;
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5514 int pipe = intel_crtc->pipe;
5515 uint16_t coeff = 0x7800; /* 1.0 */
5518 * TODO: Check what kind of values actually come out of the pipe
5519 * with these coeff/postoff values and adjust to get the best
5520 * accuracy. Perhaps we even need to take the bpc value into
5524 if (intel_crtc->config.limited_color_range)
5525 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5528 * GY/GU and RY/RU should be the other way around according
5529 * to BSpec, but reality doesn't agree. Just set them up in
5530 * a way that results in the correct picture.
5532 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5533 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5535 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5536 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5538 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5539 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5541 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5542 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5543 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5545 if (INTEL_INFO(dev)->gen > 6) {
5546 uint16_t postoff = 0;
5548 if (intel_crtc->config.limited_color_range)
5549 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5551 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5552 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5553 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5555 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5557 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5559 if (intel_crtc->config.limited_color_range)
5560 mode |= CSC_BLACK_SCREEN_OFFSET;
5562 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5566 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5568 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5570 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5575 if (intel_crtc->config.dither)
5576 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5578 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5579 val |= PIPECONF_INTERLACED_ILK;
5581 val |= PIPECONF_PROGRESSIVE;
5583 I915_WRITE(PIPECONF(cpu_transcoder), val);
5584 POSTING_READ(PIPECONF(cpu_transcoder));
5586 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5587 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5590 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5591 intel_clock_t *clock,
5592 bool *has_reduced_clock,
5593 intel_clock_t *reduced_clock)
5595 struct drm_device *dev = crtc->dev;
5596 struct drm_i915_private *dev_priv = dev->dev_private;
5597 struct intel_encoder *intel_encoder;
5599 const intel_limit_t *limit;
5600 bool ret, is_lvds = false;
5602 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5603 switch (intel_encoder->type) {
5604 case INTEL_OUTPUT_LVDS:
5610 refclk = ironlake_get_refclk(crtc);
5613 * Returns a set of divisors for the desired target clock with the given
5614 * refclk, or FALSE. The returned values represent the clock equation:
5615 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5617 limit = intel_limit(crtc, refclk);
5618 ret = dev_priv->display.find_dpll(limit, crtc,
5619 to_intel_crtc(crtc)->config.port_clock,
5620 refclk, NULL, clock);
5624 if (is_lvds && dev_priv->lvds_downclock_avail) {
5626 * Ensure we match the reduced clock's P to the target clock.
5627 * If the clocks don't match, we can't switch the display clock
5628 * by using the FP0/FP1. In such case we will disable the LVDS
5629 * downclock feature.
5631 *has_reduced_clock =
5632 dev_priv->display.find_dpll(limit, crtc,
5633 dev_priv->lvds_downclock,
5641 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5644 * Account for spread spectrum to avoid
5645 * oversubscribing the link. Max center spread
5646 * is 2.5%; use 5% for safety's sake.
5648 u32 bps = target_clock * bpp * 21 / 20;
5649 return bps / (link_bw * 8) + 1;
5652 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5654 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5657 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5659 intel_clock_t *reduced_clock, u32 *fp2)
5661 struct drm_crtc *crtc = &intel_crtc->base;
5662 struct drm_device *dev = crtc->dev;
5663 struct drm_i915_private *dev_priv = dev->dev_private;
5664 struct intel_encoder *intel_encoder;
5666 int factor, num_connectors = 0;
5667 bool is_lvds = false, is_sdvo = false;
5669 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5670 switch (intel_encoder->type) {
5671 case INTEL_OUTPUT_LVDS:
5674 case INTEL_OUTPUT_SDVO:
5675 case INTEL_OUTPUT_HDMI:
5683 /* Enable autotuning of the PLL clock (if permissible) */
5686 if ((intel_panel_use_ssc(dev_priv) &&
5687 dev_priv->vbt.lvds_ssc_freq == 100) ||
5688 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5690 } else if (intel_crtc->config.sdvo_tv_clock)
5693 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5696 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5702 dpll |= DPLLB_MODE_LVDS;
5704 dpll |= DPLLB_MODE_DAC_SERIAL;
5706 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5707 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5710 dpll |= DPLL_SDVO_HIGH_SPEED;
5711 if (intel_crtc->config.has_dp_encoder)
5712 dpll |= DPLL_SDVO_HIGH_SPEED;
5714 /* compute bitmask from p1 value */
5715 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5717 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5719 switch (intel_crtc->config.dpll.p2) {
5721 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5724 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5727 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5730 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5734 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5735 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5737 dpll |= PLL_REF_INPUT_DREFCLK;
5739 return dpll | DPLL_VCO_ENABLE;
5742 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5744 struct drm_framebuffer *fb)
5746 struct drm_device *dev = crtc->dev;
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5749 int pipe = intel_crtc->pipe;
5750 int plane = intel_crtc->plane;
5751 int num_connectors = 0;
5752 intel_clock_t clock, reduced_clock;
5753 u32 dpll = 0, fp = 0, fp2 = 0;
5754 bool ok, has_reduced_clock = false;
5755 bool is_lvds = false;
5756 struct intel_encoder *encoder;
5757 struct intel_shared_dpll *pll;
5760 for_each_encoder_on_crtc(dev, crtc, encoder) {
5761 switch (encoder->type) {
5762 case INTEL_OUTPUT_LVDS:
5770 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5771 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5773 ok = ironlake_compute_clocks(crtc, &clock,
5774 &has_reduced_clock, &reduced_clock);
5775 if (!ok && !intel_crtc->config.clock_set) {
5776 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5779 /* Compat-code for transition, will disappear. */
5780 if (!intel_crtc->config.clock_set) {
5781 intel_crtc->config.dpll.n = clock.n;
5782 intel_crtc->config.dpll.m1 = clock.m1;
5783 intel_crtc->config.dpll.m2 = clock.m2;
5784 intel_crtc->config.dpll.p1 = clock.p1;
5785 intel_crtc->config.dpll.p2 = clock.p2;
5788 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5789 if (intel_crtc->config.has_pch_encoder) {
5790 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5791 if (has_reduced_clock)
5792 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5794 dpll = ironlake_compute_dpll(intel_crtc,
5795 &fp, &reduced_clock,
5796 has_reduced_clock ? &fp2 : NULL);
5798 intel_crtc->config.dpll_hw_state.dpll = dpll;
5799 intel_crtc->config.dpll_hw_state.fp0 = fp;
5800 if (has_reduced_clock)
5801 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5803 intel_crtc->config.dpll_hw_state.fp1 = fp;
5805 pll = intel_get_shared_dpll(intel_crtc);
5807 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5812 intel_put_shared_dpll(intel_crtc);
5814 if (intel_crtc->config.has_dp_encoder)
5815 intel_dp_set_m_n(intel_crtc);
5817 if (is_lvds && has_reduced_clock && i915_powersave)
5818 intel_crtc->lowfreq_avail = true;
5820 intel_crtc->lowfreq_avail = false;
5822 if (intel_crtc->config.has_pch_encoder) {
5823 pll = intel_crtc_to_shared_dpll(intel_crtc);
5827 intel_set_pipe_timings(intel_crtc);
5829 if (intel_crtc->config.has_pch_encoder) {
5830 intel_cpu_transcoder_set_m_n(intel_crtc,
5831 &intel_crtc->config.fdi_m_n);
5834 ironlake_set_pipeconf(crtc);
5836 /* Set up the display plane register */
5837 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5838 POSTING_READ(DSPCNTR(plane));
5840 ret = intel_pipe_set_base(crtc, x, y, fb);
5842 intel_update_watermarks(dev);
5847 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5848 struct intel_crtc_config *pipe_config)
5850 struct drm_device *dev = crtc->base.dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 enum transcoder transcoder = pipe_config->cpu_transcoder;
5854 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5855 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5856 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5858 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5859 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5860 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5863 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5864 struct intel_crtc_config *pipe_config)
5866 struct drm_device *dev = crtc->base.dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5870 tmp = I915_READ(PF_CTL(crtc->pipe));
5872 if (tmp & PF_ENABLE) {
5873 pipe_config->pch_pfit.enabled = true;
5874 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5875 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5877 /* We currently do not free assignements of panel fitters on
5878 * ivb/hsw (since we don't use the higher upscaling modes which
5879 * differentiates them) so just WARN about this case for now. */
5881 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5882 PF_PIPE_SEL_IVB(crtc->pipe));
5887 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5888 struct intel_crtc_config *pipe_config)
5890 struct drm_device *dev = crtc->base.dev;
5891 struct drm_i915_private *dev_priv = dev->dev_private;
5894 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5895 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5897 tmp = I915_READ(PIPECONF(crtc->pipe));
5898 if (!(tmp & PIPECONF_ENABLE))
5901 switch (tmp & PIPECONF_BPC_MASK) {
5903 pipe_config->pipe_bpp = 18;
5906 pipe_config->pipe_bpp = 24;
5908 case PIPECONF_10BPC:
5909 pipe_config->pipe_bpp = 30;
5911 case PIPECONF_12BPC:
5912 pipe_config->pipe_bpp = 36;
5918 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5919 struct intel_shared_dpll *pll;
5921 pipe_config->has_pch_encoder = true;
5923 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5924 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5925 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5927 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5929 if (HAS_PCH_IBX(dev_priv->dev)) {
5930 pipe_config->shared_dpll =
5931 (enum intel_dpll_id) crtc->pipe;
5933 tmp = I915_READ(PCH_DPLL_SEL);
5934 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5935 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5937 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5940 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5942 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5943 &pipe_config->dpll_hw_state));
5945 tmp = pipe_config->dpll_hw_state.dpll;
5946 pipe_config->pixel_multiplier =
5947 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5948 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5950 pipe_config->pixel_multiplier = 1;
5953 intel_get_pipe_timings(crtc, pipe_config);
5955 ironlake_get_pfit_config(crtc, pipe_config);
5960 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5962 struct drm_device *dev = dev_priv->dev;
5963 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5964 struct intel_crtc *crtc;
5965 unsigned long irqflags;
5968 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5969 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5970 pipe_name(crtc->pipe));
5972 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5973 WARN(plls->spll_refcount, "SPLL enabled\n");
5974 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5975 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5976 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5977 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5978 "CPU PWM1 enabled\n");
5979 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5980 "CPU PWM2 enabled\n");
5981 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5982 "PCH PWM1 enabled\n");
5983 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5984 "Utility pin enabled\n");
5985 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5987 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5988 val = I915_READ(DEIMR);
5989 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5990 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5991 val = I915_READ(SDEIMR);
5992 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5993 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5994 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5998 * This function implements pieces of two sequences from BSpec:
5999 * - Sequence for display software to disable LCPLL
6000 * - Sequence for display software to allow package C8+
6001 * The steps implemented here are just the steps that actually touch the LCPLL
6002 * register. Callers should take care of disabling all the display engine
6003 * functions, doing the mode unset, fixing interrupts, etc.
6005 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6006 bool switch_to_fclk, bool allow_power_down)
6010 assert_can_disable_lcpll(dev_priv);
6012 val = I915_READ(LCPLL_CTL);
6014 if (switch_to_fclk) {
6015 val |= LCPLL_CD_SOURCE_FCLK;
6016 I915_WRITE(LCPLL_CTL, val);
6018 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6019 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6020 DRM_ERROR("Switching to FCLK failed\n");
6022 val = I915_READ(LCPLL_CTL);
6025 val |= LCPLL_PLL_DISABLE;
6026 I915_WRITE(LCPLL_CTL, val);
6027 POSTING_READ(LCPLL_CTL);
6029 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6030 DRM_ERROR("LCPLL still locked\n");
6032 val = I915_READ(D_COMP);
6033 val |= D_COMP_COMP_DISABLE;
6034 I915_WRITE(D_COMP, val);
6035 POSTING_READ(D_COMP);
6038 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6039 DRM_ERROR("D_COMP RCOMP still in progress\n");
6041 if (allow_power_down) {
6042 val = I915_READ(LCPLL_CTL);
6043 val |= LCPLL_POWER_DOWN_ALLOW;
6044 I915_WRITE(LCPLL_CTL, val);
6045 POSTING_READ(LCPLL_CTL);
6050 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6053 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6057 val = I915_READ(LCPLL_CTL);
6059 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6060 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6063 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6064 * we'll hang the machine! */
6065 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6067 if (val & LCPLL_POWER_DOWN_ALLOW) {
6068 val &= ~LCPLL_POWER_DOWN_ALLOW;
6069 I915_WRITE(LCPLL_CTL, val);
6070 POSTING_READ(LCPLL_CTL);
6073 val = I915_READ(D_COMP);
6074 val |= D_COMP_COMP_FORCE;
6075 val &= ~D_COMP_COMP_DISABLE;
6076 I915_WRITE(D_COMP, val);
6077 POSTING_READ(D_COMP);
6079 val = I915_READ(LCPLL_CTL);
6080 val &= ~LCPLL_PLL_DISABLE;
6081 I915_WRITE(LCPLL_CTL, val);
6083 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6084 DRM_ERROR("LCPLL not locked yet\n");
6086 if (val & LCPLL_CD_SOURCE_FCLK) {
6087 val = I915_READ(LCPLL_CTL);
6088 val &= ~LCPLL_CD_SOURCE_FCLK;
6089 I915_WRITE(LCPLL_CTL, val);
6091 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6092 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6093 DRM_ERROR("Switching back to LCPLL failed\n");
6096 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6099 void hsw_enable_pc8_work(struct work_struct *__work)
6101 struct drm_i915_private *dev_priv =
6102 container_of(to_delayed_work(__work), struct drm_i915_private,
6104 struct drm_device *dev = dev_priv->dev;
6107 if (dev_priv->pc8.enabled)
6110 DRM_DEBUG_KMS("Enabling package C8+\n");
6112 dev_priv->pc8.enabled = true;
6114 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6115 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6116 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6117 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6120 lpt_disable_clkout_dp(dev);
6121 hsw_pc8_disable_interrupts(dev);
6122 hsw_disable_lcpll(dev_priv, true, true);
6125 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6127 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6128 WARN(dev_priv->pc8.disable_count < 1,
6129 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6131 dev_priv->pc8.disable_count--;
6132 if (dev_priv->pc8.disable_count != 0)
6135 schedule_delayed_work(&dev_priv->pc8.enable_work,
6136 msecs_to_jiffies(i915_pc8_timeout));
6139 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6141 struct drm_device *dev = dev_priv->dev;
6144 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6145 WARN(dev_priv->pc8.disable_count < 0,
6146 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6148 dev_priv->pc8.disable_count++;
6149 if (dev_priv->pc8.disable_count != 1)
6152 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6153 if (!dev_priv->pc8.enabled)
6156 DRM_DEBUG_KMS("Disabling package C8+\n");
6158 hsw_restore_lcpll(dev_priv);
6159 hsw_pc8_restore_interrupts(dev);
6160 lpt_init_pch_refclk(dev);
6162 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6163 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6164 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6165 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6168 intel_prepare_ddi(dev);
6169 i915_gem_init_swizzling(dev);
6170 mutex_lock(&dev_priv->rps.hw_lock);
6171 gen6_update_ring_freq(dev);
6172 mutex_unlock(&dev_priv->rps.hw_lock);
6173 dev_priv->pc8.enabled = false;
6176 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6178 mutex_lock(&dev_priv->pc8.lock);
6179 __hsw_enable_package_c8(dev_priv);
6180 mutex_unlock(&dev_priv->pc8.lock);
6183 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6185 mutex_lock(&dev_priv->pc8.lock);
6186 __hsw_disable_package_c8(dev_priv);
6187 mutex_unlock(&dev_priv->pc8.lock);
6190 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6192 struct drm_device *dev = dev_priv->dev;
6193 struct intel_crtc *crtc;
6196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6197 if (crtc->base.enabled)
6200 /* This case is still possible since we have the i915.disable_power_well
6201 * parameter and also the KVMr or something else might be requesting the
6203 val = I915_READ(HSW_PWR_WELL_DRIVER);
6205 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6212 /* Since we're called from modeset_global_resources there's no way to
6213 * symmetrically increase and decrease the refcount, so we use
6214 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6217 static void hsw_update_package_c8(struct drm_device *dev)
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6222 if (!i915_enable_pc8)
6225 mutex_lock(&dev_priv->pc8.lock);
6227 allow = hsw_can_enable_package_c8(dev_priv);
6229 if (allow == dev_priv->pc8.requirements_met)
6232 dev_priv->pc8.requirements_met = allow;
6235 __hsw_enable_package_c8(dev_priv);
6237 __hsw_disable_package_c8(dev_priv);
6240 mutex_unlock(&dev_priv->pc8.lock);
6243 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6245 if (!dev_priv->pc8.gpu_idle) {
6246 dev_priv->pc8.gpu_idle = true;
6247 hsw_enable_package_c8(dev_priv);
6251 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6253 if (dev_priv->pc8.gpu_idle) {
6254 dev_priv->pc8.gpu_idle = false;
6255 hsw_disable_package_c8(dev_priv);
6259 static void haswell_modeset_global_resources(struct drm_device *dev)
6261 bool enable = false;
6262 struct intel_crtc *crtc;
6264 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6265 if (!crtc->base.enabled)
6268 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6269 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6273 intel_set_power_well(dev, enable);
6275 hsw_update_package_c8(dev);
6278 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6280 struct drm_framebuffer *fb)
6282 struct drm_device *dev = crtc->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6285 int plane = intel_crtc->plane;
6288 if (!intel_ddi_pll_mode_set(crtc))
6291 if (intel_crtc->config.has_dp_encoder)
6292 intel_dp_set_m_n(intel_crtc);
6294 intel_crtc->lowfreq_avail = false;
6296 intel_set_pipe_timings(intel_crtc);
6298 if (intel_crtc->config.has_pch_encoder) {
6299 intel_cpu_transcoder_set_m_n(intel_crtc,
6300 &intel_crtc->config.fdi_m_n);
6303 haswell_set_pipeconf(crtc);
6305 intel_set_pipe_csc(crtc);
6307 /* Set up the display plane register */
6308 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6309 POSTING_READ(DSPCNTR(plane));
6311 ret = intel_pipe_set_base(crtc, x, y, fb);
6313 intel_update_watermarks(dev);
6318 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6319 struct intel_crtc_config *pipe_config)
6321 struct drm_device *dev = crtc->base.dev;
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 enum intel_display_power_domain pfit_domain;
6326 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6327 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6329 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6330 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6331 enum pipe trans_edp_pipe;
6332 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6334 WARN(1, "unknown pipe linked to edp transcoder\n");
6335 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6336 case TRANS_DDI_EDP_INPUT_A_ON:
6337 trans_edp_pipe = PIPE_A;
6339 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6340 trans_edp_pipe = PIPE_B;
6342 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6343 trans_edp_pipe = PIPE_C;
6347 if (trans_edp_pipe == crtc->pipe)
6348 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6351 if (!intel_display_power_enabled(dev,
6352 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6355 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6356 if (!(tmp & PIPECONF_ENABLE))
6360 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6361 * DDI E. So just check whether this pipe is wired to DDI E and whether
6362 * the PCH transcoder is on.
6364 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6365 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6366 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6367 pipe_config->has_pch_encoder = true;
6369 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6370 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6371 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6373 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6376 intel_get_pipe_timings(crtc, pipe_config);
6378 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6379 if (intel_display_power_enabled(dev, pfit_domain))
6380 ironlake_get_pfit_config(crtc, pipe_config);
6382 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6383 (I915_READ(IPS_CTL) & IPS_ENABLE);
6385 pipe_config->pixel_multiplier = 1;
6390 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6392 struct drm_framebuffer *fb)
6394 struct drm_device *dev = crtc->dev;
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396 struct intel_encoder *encoder;
6397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6399 int pipe = intel_crtc->pipe;
6402 drm_vblank_pre_modeset(dev, pipe);
6404 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6406 drm_vblank_post_modeset(dev, pipe);
6411 for_each_encoder_on_crtc(dev, crtc, encoder) {
6412 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6413 encoder->base.base.id,
6414 drm_get_encoder_name(&encoder->base),
6415 mode->base.id, mode->name);
6416 encoder->mode_set(encoder);
6422 static bool intel_eld_uptodate(struct drm_connector *connector,
6423 int reg_eldv, uint32_t bits_eldv,
6424 int reg_elda, uint32_t bits_elda,
6427 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6428 uint8_t *eld = connector->eld;
6431 i = I915_READ(reg_eldv);
6440 i = I915_READ(reg_elda);
6442 I915_WRITE(reg_elda, i);
6444 for (i = 0; i < eld[2]; i++)
6445 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6451 static void g4x_write_eld(struct drm_connector *connector,
6452 struct drm_crtc *crtc)
6454 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6455 uint8_t *eld = connector->eld;
6460 i = I915_READ(G4X_AUD_VID_DID);
6462 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6463 eldv = G4X_ELDV_DEVCL_DEVBLC;
6465 eldv = G4X_ELDV_DEVCTG;
6467 if (intel_eld_uptodate(connector,
6468 G4X_AUD_CNTL_ST, eldv,
6469 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6470 G4X_HDMIW_HDMIEDID))
6473 i = I915_READ(G4X_AUD_CNTL_ST);
6474 i &= ~(eldv | G4X_ELD_ADDR);
6475 len = (i >> 9) & 0x1f; /* ELD buffer size */
6476 I915_WRITE(G4X_AUD_CNTL_ST, i);
6481 len = min_t(uint8_t, eld[2], len);
6482 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6483 for (i = 0; i < len; i++)
6484 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6486 i = I915_READ(G4X_AUD_CNTL_ST);
6488 I915_WRITE(G4X_AUD_CNTL_ST, i);
6491 static void haswell_write_eld(struct drm_connector *connector,
6492 struct drm_crtc *crtc)
6494 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6495 uint8_t *eld = connector->eld;
6496 struct drm_device *dev = crtc->dev;
6497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6501 int pipe = to_intel_crtc(crtc)->pipe;
6504 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6505 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6506 int aud_config = HSW_AUD_CFG(pipe);
6507 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6510 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6512 /* Audio output enable */
6513 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6514 tmp = I915_READ(aud_cntrl_st2);
6515 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6516 I915_WRITE(aud_cntrl_st2, tmp);
6518 /* Wait for 1 vertical blank */
6519 intel_wait_for_vblank(dev, pipe);
6521 /* Set ELD valid state */
6522 tmp = I915_READ(aud_cntrl_st2);
6523 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6524 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6525 I915_WRITE(aud_cntrl_st2, tmp);
6526 tmp = I915_READ(aud_cntrl_st2);
6527 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6529 /* Enable HDMI mode */
6530 tmp = I915_READ(aud_config);
6531 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6532 /* clear N_programing_enable and N_value_index */
6533 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6534 I915_WRITE(aud_config, tmp);
6536 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6538 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6539 intel_crtc->eld_vld = true;
6541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6542 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6543 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6544 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6546 I915_WRITE(aud_config, 0);
6548 if (intel_eld_uptodate(connector,
6549 aud_cntrl_st2, eldv,
6550 aud_cntl_st, IBX_ELD_ADDRESS,
6554 i = I915_READ(aud_cntrl_st2);
6556 I915_WRITE(aud_cntrl_st2, i);
6561 i = I915_READ(aud_cntl_st);
6562 i &= ~IBX_ELD_ADDRESS;
6563 I915_WRITE(aud_cntl_st, i);
6564 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6565 DRM_DEBUG_DRIVER("port num:%d\n", i);
6567 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6568 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6569 for (i = 0; i < len; i++)
6570 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6572 i = I915_READ(aud_cntrl_st2);
6574 I915_WRITE(aud_cntrl_st2, i);
6578 static void ironlake_write_eld(struct drm_connector *connector,
6579 struct drm_crtc *crtc)
6581 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6582 uint8_t *eld = connector->eld;
6590 int pipe = to_intel_crtc(crtc)->pipe;
6592 if (HAS_PCH_IBX(connector->dev)) {
6593 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6594 aud_config = IBX_AUD_CFG(pipe);
6595 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6596 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6598 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6599 aud_config = CPT_AUD_CFG(pipe);
6600 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6601 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6604 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6606 i = I915_READ(aud_cntl_st);
6607 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6609 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6610 /* operate blindly on all ports */
6611 eldv = IBX_ELD_VALIDB;
6612 eldv |= IBX_ELD_VALIDB << 4;
6613 eldv |= IBX_ELD_VALIDB << 8;
6615 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6616 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6620 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6621 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6622 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6624 I915_WRITE(aud_config, 0);
6626 if (intel_eld_uptodate(connector,
6627 aud_cntrl_st2, eldv,
6628 aud_cntl_st, IBX_ELD_ADDRESS,
6632 i = I915_READ(aud_cntrl_st2);
6634 I915_WRITE(aud_cntrl_st2, i);
6639 i = I915_READ(aud_cntl_st);
6640 i &= ~IBX_ELD_ADDRESS;
6641 I915_WRITE(aud_cntl_st, i);
6643 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6644 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6645 for (i = 0; i < len; i++)
6646 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6648 i = I915_READ(aud_cntrl_st2);
6650 I915_WRITE(aud_cntrl_st2, i);
6653 void intel_write_eld(struct drm_encoder *encoder,
6654 struct drm_display_mode *mode)
6656 struct drm_crtc *crtc = encoder->crtc;
6657 struct drm_connector *connector;
6658 struct drm_device *dev = encoder->dev;
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6661 connector = drm_select_eld(encoder, mode);
6665 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6667 drm_get_connector_name(connector),
6668 connector->encoder->base.id,
6669 drm_get_encoder_name(connector->encoder));
6671 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6673 if (dev_priv->display.write_eld)
6674 dev_priv->display.write_eld(connector, crtc);
6677 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6678 void intel_crtc_load_lut(struct drm_crtc *crtc)
6680 struct drm_device *dev = crtc->dev;
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6683 enum pipe pipe = intel_crtc->pipe;
6684 int palreg = PALETTE(pipe);
6686 bool reenable_ips = false;
6688 /* The clocks have to be on to load the palette. */
6689 if (!crtc->enabled || !intel_crtc->active)
6692 if (!HAS_PCH_SPLIT(dev_priv->dev))
6693 assert_pll_enabled(dev_priv, pipe);
6695 /* use legacy palette for Ironlake */
6696 if (HAS_PCH_SPLIT(dev))
6697 palreg = LGC_PALETTE(pipe);
6699 /* Workaround : Do not read or write the pipe palette/gamma data while
6700 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6702 if (intel_crtc->config.ips_enabled &&
6703 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6704 GAMMA_MODE_MODE_SPLIT)) {
6705 hsw_disable_ips(intel_crtc);
6706 reenable_ips = true;
6709 for (i = 0; i < 256; i++) {
6710 I915_WRITE(palreg + 4 * i,
6711 (intel_crtc->lut_r[i] << 16) |
6712 (intel_crtc->lut_g[i] << 8) |
6713 intel_crtc->lut_b[i]);
6717 hsw_enable_ips(intel_crtc);
6720 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6722 struct drm_device *dev = crtc->dev;
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6725 bool visible = base != 0;
6728 if (intel_crtc->cursor_visible == visible)
6731 cntl = I915_READ(_CURACNTR);
6733 /* On these chipsets we can only modify the base whilst
6734 * the cursor is disabled.
6736 I915_WRITE(_CURABASE, base);
6738 cntl &= ~(CURSOR_FORMAT_MASK);
6739 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6740 cntl |= CURSOR_ENABLE |
6741 CURSOR_GAMMA_ENABLE |
6744 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6745 I915_WRITE(_CURACNTR, cntl);
6747 intel_crtc->cursor_visible = visible;
6750 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6752 struct drm_device *dev = crtc->dev;
6753 struct drm_i915_private *dev_priv = dev->dev_private;
6754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6755 int pipe = intel_crtc->pipe;
6756 bool visible = base != 0;
6758 if (intel_crtc->cursor_visible != visible) {
6759 uint32_t cntl = I915_READ(CURCNTR(pipe));
6761 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6762 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6763 cntl |= pipe << 28; /* Connect to correct pipe */
6765 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6766 cntl |= CURSOR_MODE_DISABLE;
6768 I915_WRITE(CURCNTR(pipe), cntl);
6770 intel_crtc->cursor_visible = visible;
6772 /* and commit changes on next vblank */
6773 I915_WRITE(CURBASE(pipe), base);
6776 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6778 struct drm_device *dev = crtc->dev;
6779 struct drm_i915_private *dev_priv = dev->dev_private;
6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6781 int pipe = intel_crtc->pipe;
6782 bool visible = base != 0;
6784 if (intel_crtc->cursor_visible != visible) {
6785 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6787 cntl &= ~CURSOR_MODE;
6788 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6790 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6791 cntl |= CURSOR_MODE_DISABLE;
6793 if (IS_HASWELL(dev)) {
6794 cntl |= CURSOR_PIPE_CSC_ENABLE;
6795 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6797 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6799 intel_crtc->cursor_visible = visible;
6801 /* and commit changes on next vblank */
6802 I915_WRITE(CURBASE_IVB(pipe), base);
6805 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6806 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6809 struct drm_device *dev = crtc->dev;
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812 int pipe = intel_crtc->pipe;
6813 int x = intel_crtc->cursor_x;
6814 int y = intel_crtc->cursor_y;
6820 if (on && crtc->enabled && crtc->fb) {
6821 base = intel_crtc->cursor_addr;
6822 if (x > (int) crtc->fb->width)
6825 if (y > (int) crtc->fb->height)
6831 if (x + intel_crtc->cursor_width < 0)
6834 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6837 pos |= x << CURSOR_X_SHIFT;
6840 if (y + intel_crtc->cursor_height < 0)
6843 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6846 pos |= y << CURSOR_Y_SHIFT;
6848 visible = base != 0;
6849 if (!visible && !intel_crtc->cursor_visible)
6852 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6853 I915_WRITE(CURPOS_IVB(pipe), pos);
6854 ivb_update_cursor(crtc, base);
6856 I915_WRITE(CURPOS(pipe), pos);
6857 if (IS_845G(dev) || IS_I865G(dev))
6858 i845_update_cursor(crtc, base);
6860 i9xx_update_cursor(crtc, base);
6864 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6865 struct drm_file *file,
6867 uint32_t width, uint32_t height)
6869 struct drm_device *dev = crtc->dev;
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6872 struct drm_i915_gem_object *obj;
6876 /* if we want to turn off the cursor ignore width and height */
6878 DRM_DEBUG_KMS("cursor off\n");
6881 mutex_lock(&dev->struct_mutex);
6885 /* Currently we only support 64x64 cursors */
6886 if (width != 64 || height != 64) {
6887 DRM_ERROR("we currently only support 64x64 cursors\n");
6891 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6892 if (&obj->base == NULL)
6895 if (obj->base.size < width * height * 4) {
6896 DRM_ERROR("buffer is to small\n");
6901 /* we only need to pin inside GTT if cursor is non-phy */
6902 mutex_lock(&dev->struct_mutex);
6903 if (!dev_priv->info->cursor_needs_physical) {
6906 if (obj->tiling_mode) {
6907 DRM_ERROR("cursor cannot be tiled\n");
6912 /* Note that the w/a also requires 2 PTE of padding following
6913 * the bo. We currently fill all unused PTE with the shadow
6914 * page and so we should always have valid PTE following the
6915 * cursor preventing the VT-d warning.
6918 if (need_vtd_wa(dev))
6919 alignment = 64*1024;
6921 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6923 DRM_ERROR("failed to move cursor bo into the GTT\n");
6927 ret = i915_gem_object_put_fence(obj);
6929 DRM_ERROR("failed to release fence for cursor");
6933 addr = i915_gem_obj_ggtt_offset(obj);
6935 int align = IS_I830(dev) ? 16 * 1024 : 256;
6936 ret = i915_gem_attach_phys_object(dev, obj,
6937 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6940 DRM_ERROR("failed to attach phys object\n");
6943 addr = obj->phys_obj->handle->busaddr;
6947 I915_WRITE(CURSIZE, (height << 12) | width);
6950 if (intel_crtc->cursor_bo) {
6951 if (dev_priv->info->cursor_needs_physical) {
6952 if (intel_crtc->cursor_bo != obj)
6953 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6955 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6956 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6959 mutex_unlock(&dev->struct_mutex);
6961 intel_crtc->cursor_addr = addr;
6962 intel_crtc->cursor_bo = obj;
6963 intel_crtc->cursor_width = width;
6964 intel_crtc->cursor_height = height;
6966 if (intel_crtc->active)
6967 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6971 i915_gem_object_unpin_from_display_plane(obj);
6973 mutex_unlock(&dev->struct_mutex);
6975 drm_gem_object_unreference_unlocked(&obj->base);
6979 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6983 intel_crtc->cursor_x = x;
6984 intel_crtc->cursor_y = y;
6986 if (intel_crtc->active)
6987 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6992 /** Sets the color ramps on behalf of RandR */
6993 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6994 u16 blue, int regno)
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6998 intel_crtc->lut_r[regno] = red >> 8;
6999 intel_crtc->lut_g[regno] = green >> 8;
7000 intel_crtc->lut_b[regno] = blue >> 8;
7003 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7004 u16 *blue, int regno)
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7008 *red = intel_crtc->lut_r[regno] << 8;
7009 *green = intel_crtc->lut_g[regno] << 8;
7010 *blue = intel_crtc->lut_b[regno] << 8;
7013 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7014 u16 *blue, uint32_t start, uint32_t size)
7016 int end = (start + size > 256) ? 256 : start + size, i;
7017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 for (i = start; i < end; i++) {
7020 intel_crtc->lut_r[i] = red[i] >> 8;
7021 intel_crtc->lut_g[i] = green[i] >> 8;
7022 intel_crtc->lut_b[i] = blue[i] >> 8;
7025 intel_crtc_load_lut(crtc);
7028 /* VESA 640x480x72Hz mode to set on the pipe */
7029 static struct drm_display_mode load_detect_mode = {
7030 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7031 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7034 static struct drm_framebuffer *
7035 intel_framebuffer_create(struct drm_device *dev,
7036 struct drm_mode_fb_cmd2 *mode_cmd,
7037 struct drm_i915_gem_object *obj)
7039 struct intel_framebuffer *intel_fb;
7042 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7044 drm_gem_object_unreference_unlocked(&obj->base);
7045 return ERR_PTR(-ENOMEM);
7048 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7050 drm_gem_object_unreference_unlocked(&obj->base);
7052 return ERR_PTR(ret);
7055 return &intel_fb->base;
7059 intel_framebuffer_pitch_for_width(int width, int bpp)
7061 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7062 return ALIGN(pitch, 64);
7066 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7068 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7069 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7072 static struct drm_framebuffer *
7073 intel_framebuffer_create_for_mode(struct drm_device *dev,
7074 struct drm_display_mode *mode,
7077 struct drm_i915_gem_object *obj;
7078 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7080 obj = i915_gem_alloc_object(dev,
7081 intel_framebuffer_size_for_mode(mode, bpp));
7083 return ERR_PTR(-ENOMEM);
7085 mode_cmd.width = mode->hdisplay;
7086 mode_cmd.height = mode->vdisplay;
7087 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7089 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7091 return intel_framebuffer_create(dev, &mode_cmd, obj);
7094 static struct drm_framebuffer *
7095 mode_fits_in_fbdev(struct drm_device *dev,
7096 struct drm_display_mode *mode)
7098 struct drm_i915_private *dev_priv = dev->dev_private;
7099 struct drm_i915_gem_object *obj;
7100 struct drm_framebuffer *fb;
7102 if (dev_priv->fbdev == NULL)
7105 obj = dev_priv->fbdev->ifb.obj;
7109 fb = &dev_priv->fbdev->ifb.base;
7110 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7111 fb->bits_per_pixel))
7114 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7120 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7121 struct drm_display_mode *mode,
7122 struct intel_load_detect_pipe *old)
7124 struct intel_crtc *intel_crtc;
7125 struct intel_encoder *intel_encoder =
7126 intel_attached_encoder(connector);
7127 struct drm_crtc *possible_crtc;
7128 struct drm_encoder *encoder = &intel_encoder->base;
7129 struct drm_crtc *crtc = NULL;
7130 struct drm_device *dev = encoder->dev;
7131 struct drm_framebuffer *fb;
7134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7135 connector->base.id, drm_get_connector_name(connector),
7136 encoder->base.id, drm_get_encoder_name(encoder));
7139 * Algorithm gets a little messy:
7141 * - if the connector already has an assigned crtc, use it (but make
7142 * sure it's on first)
7144 * - try to find the first unused crtc that can drive this connector,
7145 * and use that if we find one
7148 /* See if we already have a CRTC for this connector */
7149 if (encoder->crtc) {
7150 crtc = encoder->crtc;
7152 mutex_lock(&crtc->mutex);
7154 old->dpms_mode = connector->dpms;
7155 old->load_detect_temp = false;
7157 /* Make sure the crtc and connector are running */
7158 if (connector->dpms != DRM_MODE_DPMS_ON)
7159 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7164 /* Find an unused one (if possible) */
7165 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7167 if (!(encoder->possible_crtcs & (1 << i)))
7169 if (!possible_crtc->enabled) {
7170 crtc = possible_crtc;
7176 * If we didn't find an unused CRTC, don't use any.
7179 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7183 mutex_lock(&crtc->mutex);
7184 intel_encoder->new_crtc = to_intel_crtc(crtc);
7185 to_intel_connector(connector)->new_encoder = intel_encoder;
7187 intel_crtc = to_intel_crtc(crtc);
7188 old->dpms_mode = connector->dpms;
7189 old->load_detect_temp = true;
7190 old->release_fb = NULL;
7193 mode = &load_detect_mode;
7195 /* We need a framebuffer large enough to accommodate all accesses
7196 * that the plane may generate whilst we perform load detection.
7197 * We can not rely on the fbcon either being present (we get called
7198 * during its initialisation to detect all boot displays, or it may
7199 * not even exist) or that it is large enough to satisfy the
7202 fb = mode_fits_in_fbdev(dev, mode);
7204 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7205 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7206 old->release_fb = fb;
7208 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7210 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7211 mutex_unlock(&crtc->mutex);
7215 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7216 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7217 if (old->release_fb)
7218 old->release_fb->funcs->destroy(old->release_fb);
7219 mutex_unlock(&crtc->mutex);
7223 /* let the connector get through one full cycle before testing */
7224 intel_wait_for_vblank(dev, intel_crtc->pipe);
7228 void intel_release_load_detect_pipe(struct drm_connector *connector,
7229 struct intel_load_detect_pipe *old)
7231 struct intel_encoder *intel_encoder =
7232 intel_attached_encoder(connector);
7233 struct drm_encoder *encoder = &intel_encoder->base;
7234 struct drm_crtc *crtc = encoder->crtc;
7236 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7237 connector->base.id, drm_get_connector_name(connector),
7238 encoder->base.id, drm_get_encoder_name(encoder));
7240 if (old->load_detect_temp) {
7241 to_intel_connector(connector)->new_encoder = NULL;
7242 intel_encoder->new_crtc = NULL;
7243 intel_set_mode(crtc, NULL, 0, 0, NULL);
7245 if (old->release_fb) {
7246 drm_framebuffer_unregister_private(old->release_fb);
7247 drm_framebuffer_unreference(old->release_fb);
7250 mutex_unlock(&crtc->mutex);
7254 /* Switch crtc and encoder back off if necessary */
7255 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7256 connector->funcs->dpms(connector, old->dpms_mode);
7258 mutex_unlock(&crtc->mutex);
7261 /* Returns the clock of the currently programmed mode of the given pipe. */
7262 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7263 struct intel_crtc_config *pipe_config)
7265 struct drm_device *dev = crtc->base.dev;
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 int pipe = pipe_config->cpu_transcoder;
7268 u32 dpll = I915_READ(DPLL(pipe));
7270 intel_clock_t clock;
7272 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7273 fp = I915_READ(FP0(pipe));
7275 fp = I915_READ(FP1(pipe));
7277 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7278 if (IS_PINEVIEW(dev)) {
7279 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7280 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7282 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7283 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7286 if (!IS_GEN2(dev)) {
7287 if (IS_PINEVIEW(dev))
7288 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7289 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7291 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7292 DPLL_FPA01_P1_POST_DIV_SHIFT);
7294 switch (dpll & DPLL_MODE_MASK) {
7295 case DPLLB_MODE_DAC_SERIAL:
7296 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7299 case DPLLB_MODE_LVDS:
7300 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7304 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7305 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7306 pipe_config->adjusted_mode.clock = 0;
7310 if (IS_PINEVIEW(dev))
7311 pineview_clock(96000, &clock);
7313 i9xx_clock(96000, &clock);
7315 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7318 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7319 DPLL_FPA01_P1_POST_DIV_SHIFT);
7322 if ((dpll & PLL_REF_INPUT_MASK) ==
7323 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7324 /* XXX: might not be 66MHz */
7325 i9xx_clock(66000, &clock);
7327 i9xx_clock(48000, &clock);
7329 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7332 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7333 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7335 if (dpll & PLL_P2_DIVIDE_BY_4)
7340 i9xx_clock(48000, &clock);
7344 pipe_config->adjusted_mode.clock = clock.dot;
7347 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7348 struct intel_crtc_config *pipe_config)
7350 struct drm_device *dev = crtc->base.dev;
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7353 int link_freq, repeat;
7357 repeat = pipe_config->pixel_multiplier;
7360 * The calculation for the data clock is:
7361 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7362 * But we want to avoid losing precison if possible, so:
7363 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7365 * and the link clock is simpler:
7366 * link_clock = (m * link_clock * repeat) / n
7370 * We need to get the FDI or DP link clock here to derive
7373 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7374 * For DP, it's either 1.62GHz or 2.7GHz.
7375 * We do our calculations in 10*MHz since we don't need much precison.
7377 if (pipe_config->has_pch_encoder)
7378 link_freq = intel_fdi_link_freq(dev) * 10000;
7380 link_freq = pipe_config->port_clock;
7382 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7383 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7385 if (!link_m || !link_n)
7388 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7389 do_div(clock, link_n);
7391 pipe_config->adjusted_mode.clock = clock;
7394 /** Returns the currently programmed mode of the given pipe. */
7395 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7396 struct drm_crtc *crtc)
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7400 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7401 struct drm_display_mode *mode;
7402 struct intel_crtc_config pipe_config;
7403 int htot = I915_READ(HTOTAL(cpu_transcoder));
7404 int hsync = I915_READ(HSYNC(cpu_transcoder));
7405 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7406 int vsync = I915_READ(VSYNC(cpu_transcoder));
7408 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7413 * Construct a pipe_config sufficient for getting the clock info
7414 * back out of crtc_clock_get.
7416 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7417 * to use a real value here instead.
7419 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7420 pipe_config.pixel_multiplier = 1;
7421 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7423 mode->clock = pipe_config.adjusted_mode.clock;
7424 mode->hdisplay = (htot & 0xffff) + 1;
7425 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7426 mode->hsync_start = (hsync & 0xffff) + 1;
7427 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7428 mode->vdisplay = (vtot & 0xffff) + 1;
7429 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7430 mode->vsync_start = (vsync & 0xffff) + 1;
7431 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7433 drm_mode_set_name(mode);
7438 static void intel_increase_pllclock(struct drm_crtc *crtc)
7440 struct drm_device *dev = crtc->dev;
7441 drm_i915_private_t *dev_priv = dev->dev_private;
7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443 int pipe = intel_crtc->pipe;
7444 int dpll_reg = DPLL(pipe);
7447 if (HAS_PCH_SPLIT(dev))
7450 if (!dev_priv->lvds_downclock_avail)
7453 dpll = I915_READ(dpll_reg);
7454 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7455 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7457 assert_panel_unlocked(dev_priv, pipe);
7459 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7460 I915_WRITE(dpll_reg, dpll);
7461 intel_wait_for_vblank(dev, pipe);
7463 dpll = I915_READ(dpll_reg);
7464 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7465 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7469 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7471 struct drm_device *dev = crtc->dev;
7472 drm_i915_private_t *dev_priv = dev->dev_private;
7473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7475 if (HAS_PCH_SPLIT(dev))
7478 if (!dev_priv->lvds_downclock_avail)
7482 * Since this is called by a timer, we should never get here in
7485 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7486 int pipe = intel_crtc->pipe;
7487 int dpll_reg = DPLL(pipe);
7490 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7492 assert_panel_unlocked(dev_priv, pipe);
7494 dpll = I915_READ(dpll_reg);
7495 dpll |= DISPLAY_RATE_SELECT_FPA1;
7496 I915_WRITE(dpll_reg, dpll);
7497 intel_wait_for_vblank(dev, pipe);
7498 dpll = I915_READ(dpll_reg);
7499 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7500 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7505 void intel_mark_busy(struct drm_device *dev)
7507 struct drm_i915_private *dev_priv = dev->dev_private;
7509 hsw_package_c8_gpu_busy(dev_priv);
7510 i915_update_gfx_val(dev_priv);
7513 void intel_mark_idle(struct drm_device *dev)
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 struct drm_crtc *crtc;
7518 hsw_package_c8_gpu_idle(dev_priv);
7520 if (!i915_powersave)
7523 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7527 intel_decrease_pllclock(crtc);
7531 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7532 struct intel_ring_buffer *ring)
7534 struct drm_device *dev = obj->base.dev;
7535 struct drm_crtc *crtc;
7537 if (!i915_powersave)
7540 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7544 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7547 intel_increase_pllclock(crtc);
7548 if (ring && intel_fbc_enabled(dev))
7549 ring->fbc_dirty = true;
7553 static void intel_crtc_destroy(struct drm_crtc *crtc)
7555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556 struct drm_device *dev = crtc->dev;
7557 struct intel_unpin_work *work;
7558 unsigned long flags;
7560 spin_lock_irqsave(&dev->event_lock, flags);
7561 work = intel_crtc->unpin_work;
7562 intel_crtc->unpin_work = NULL;
7563 spin_unlock_irqrestore(&dev->event_lock, flags);
7566 cancel_work_sync(&work->work);
7570 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7572 drm_crtc_cleanup(crtc);
7577 static void intel_unpin_work_fn(struct work_struct *__work)
7579 struct intel_unpin_work *work =
7580 container_of(__work, struct intel_unpin_work, work);
7581 struct drm_device *dev = work->crtc->dev;
7583 mutex_lock(&dev->struct_mutex);
7584 intel_unpin_fb_obj(work->old_fb_obj);
7585 drm_gem_object_unreference(&work->pending_flip_obj->base);
7586 drm_gem_object_unreference(&work->old_fb_obj->base);
7588 intel_update_fbc(dev);
7589 mutex_unlock(&dev->struct_mutex);
7591 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7592 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7597 static void do_intel_finish_page_flip(struct drm_device *dev,
7598 struct drm_crtc *crtc)
7600 drm_i915_private_t *dev_priv = dev->dev_private;
7601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7602 struct intel_unpin_work *work;
7603 unsigned long flags;
7605 /* Ignore early vblank irqs */
7606 if (intel_crtc == NULL)
7609 spin_lock_irqsave(&dev->event_lock, flags);
7610 work = intel_crtc->unpin_work;
7612 /* Ensure we don't miss a work->pending update ... */
7615 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7616 spin_unlock_irqrestore(&dev->event_lock, flags);
7620 /* and that the unpin work is consistent wrt ->pending. */
7623 intel_crtc->unpin_work = NULL;
7626 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7628 drm_vblank_put(dev, intel_crtc->pipe);
7630 spin_unlock_irqrestore(&dev->event_lock, flags);
7632 wake_up_all(&dev_priv->pending_flip_queue);
7634 queue_work(dev_priv->wq, &work->work);
7636 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7639 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7641 drm_i915_private_t *dev_priv = dev->dev_private;
7642 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7644 do_intel_finish_page_flip(dev, crtc);
7647 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7649 drm_i915_private_t *dev_priv = dev->dev_private;
7650 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7652 do_intel_finish_page_flip(dev, crtc);
7655 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7657 drm_i915_private_t *dev_priv = dev->dev_private;
7658 struct intel_crtc *intel_crtc =
7659 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7660 unsigned long flags;
7662 /* NB: An MMIO update of the plane base pointer will also
7663 * generate a page-flip completion irq, i.e. every modeset
7664 * is also accompanied by a spurious intel_prepare_page_flip().
7666 spin_lock_irqsave(&dev->event_lock, flags);
7667 if (intel_crtc->unpin_work)
7668 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7669 spin_unlock_irqrestore(&dev->event_lock, flags);
7672 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7674 /* Ensure that the work item is consistent when activating it ... */
7676 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7677 /* and that it is marked active as soon as the irq could fire. */
7681 static int intel_gen2_queue_flip(struct drm_device *dev,
7682 struct drm_crtc *crtc,
7683 struct drm_framebuffer *fb,
7684 struct drm_i915_gem_object *obj,
7687 struct drm_i915_private *dev_priv = dev->dev_private;
7688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7690 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7693 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7697 ret = intel_ring_begin(ring, 6);
7701 /* Can't queue multiple flips, so wait for the previous
7702 * one to finish before executing the next.
7704 if (intel_crtc->plane)
7705 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7707 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7708 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7709 intel_ring_emit(ring, MI_NOOP);
7710 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7711 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7712 intel_ring_emit(ring, fb->pitches[0]);
7713 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7714 intel_ring_emit(ring, 0); /* aux display base address, unused */
7716 intel_mark_page_flip_active(intel_crtc);
7717 intel_ring_advance(ring);
7721 intel_unpin_fb_obj(obj);
7726 static int intel_gen3_queue_flip(struct drm_device *dev,
7727 struct drm_crtc *crtc,
7728 struct drm_framebuffer *fb,
7729 struct drm_i915_gem_object *obj,
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7735 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7738 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7742 ret = intel_ring_begin(ring, 6);
7746 if (intel_crtc->plane)
7747 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7749 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7750 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7751 intel_ring_emit(ring, MI_NOOP);
7752 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7753 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7754 intel_ring_emit(ring, fb->pitches[0]);
7755 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7756 intel_ring_emit(ring, MI_NOOP);
7758 intel_mark_page_flip_active(intel_crtc);
7759 intel_ring_advance(ring);
7763 intel_unpin_fb_obj(obj);
7768 static int intel_gen4_queue_flip(struct drm_device *dev,
7769 struct drm_crtc *crtc,
7770 struct drm_framebuffer *fb,
7771 struct drm_i915_gem_object *obj,
7774 struct drm_i915_private *dev_priv = dev->dev_private;
7775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7776 uint32_t pf, pipesrc;
7777 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7780 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7784 ret = intel_ring_begin(ring, 4);
7788 /* i965+ uses the linear or tiled offsets from the
7789 * Display Registers (which do not change across a page-flip)
7790 * so we need only reprogram the base address.
7792 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7793 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7794 intel_ring_emit(ring, fb->pitches[0]);
7795 intel_ring_emit(ring,
7796 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7799 /* XXX Enabling the panel-fitter across page-flip is so far
7800 * untested on non-native modes, so ignore it for now.
7801 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7804 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7805 intel_ring_emit(ring, pf | pipesrc);
7807 intel_mark_page_flip_active(intel_crtc);
7808 intel_ring_advance(ring);
7812 intel_unpin_fb_obj(obj);
7817 static int intel_gen6_queue_flip(struct drm_device *dev,
7818 struct drm_crtc *crtc,
7819 struct drm_framebuffer *fb,
7820 struct drm_i915_gem_object *obj,
7823 struct drm_i915_private *dev_priv = dev->dev_private;
7824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7825 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7826 uint32_t pf, pipesrc;
7829 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7833 ret = intel_ring_begin(ring, 4);
7837 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7838 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7839 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7840 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7842 /* Contrary to the suggestions in the documentation,
7843 * "Enable Panel Fitter" does not seem to be required when page
7844 * flipping with a non-native mode, and worse causes a normal
7846 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7849 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7850 intel_ring_emit(ring, pf | pipesrc);
7852 intel_mark_page_flip_active(intel_crtc);
7853 intel_ring_advance(ring);
7857 intel_unpin_fb_obj(obj);
7862 static int intel_gen7_queue_flip(struct drm_device *dev,
7863 struct drm_crtc *crtc,
7864 struct drm_framebuffer *fb,
7865 struct drm_i915_gem_object *obj,
7868 struct drm_i915_private *dev_priv = dev->dev_private;
7869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7870 struct intel_ring_buffer *ring;
7871 uint32_t plane_bit = 0;
7875 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7876 ring = &dev_priv->ring[BCS];
7878 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7882 switch(intel_crtc->plane) {
7884 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7887 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7890 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7893 WARN_ONCE(1, "unknown plane in flip command\n");
7899 if (ring->id == RCS)
7902 ret = intel_ring_begin(ring, len);
7906 /* Unmask the flip-done completion message. Note that the bspec says that
7907 * we should do this for both the BCS and RCS, and that we must not unmask
7908 * more than one flip event at any time (or ensure that one flip message
7909 * can be sent by waiting for flip-done prior to queueing new flips).
7910 * Experimentation says that BCS works despite DERRMR masking all
7911 * flip-done completion events and that unmasking all planes at once
7912 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7913 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7915 if (ring->id == RCS) {
7916 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7917 intel_ring_emit(ring, DERRMR);
7918 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7919 DERRMR_PIPEB_PRI_FLIP_DONE |
7920 DERRMR_PIPEC_PRI_FLIP_DONE));
7921 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7922 intel_ring_emit(ring, DERRMR);
7923 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7926 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7927 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7928 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7929 intel_ring_emit(ring, (MI_NOOP));
7931 intel_mark_page_flip_active(intel_crtc);
7932 intel_ring_advance(ring);
7936 intel_unpin_fb_obj(obj);
7941 static int intel_default_queue_flip(struct drm_device *dev,
7942 struct drm_crtc *crtc,
7943 struct drm_framebuffer *fb,
7944 struct drm_i915_gem_object *obj,
7950 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7951 struct drm_framebuffer *fb,
7952 struct drm_pending_vblank_event *event,
7953 uint32_t page_flip_flags)
7955 struct drm_device *dev = crtc->dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 struct drm_framebuffer *old_fb = crtc->fb;
7958 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7960 struct intel_unpin_work *work;
7961 unsigned long flags;
7964 /* Can't change pixel format via MI display flips. */
7965 if (fb->pixel_format != crtc->fb->pixel_format)
7969 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7970 * Note that pitch changes could also affect these register.
7972 if (INTEL_INFO(dev)->gen > 3 &&
7973 (fb->offsets[0] != crtc->fb->offsets[0] ||
7974 fb->pitches[0] != crtc->fb->pitches[0]))
7977 work = kzalloc(sizeof *work, GFP_KERNEL);
7981 work->event = event;
7983 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7984 INIT_WORK(&work->work, intel_unpin_work_fn);
7986 ret = drm_vblank_get(dev, intel_crtc->pipe);
7990 /* We borrow the event spin lock for protecting unpin_work */
7991 spin_lock_irqsave(&dev->event_lock, flags);
7992 if (intel_crtc->unpin_work) {
7993 spin_unlock_irqrestore(&dev->event_lock, flags);
7995 drm_vblank_put(dev, intel_crtc->pipe);
7997 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8000 intel_crtc->unpin_work = work;
8001 spin_unlock_irqrestore(&dev->event_lock, flags);
8003 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8004 flush_workqueue(dev_priv->wq);
8006 ret = i915_mutex_lock_interruptible(dev);
8010 /* Reference the objects for the scheduled work. */
8011 drm_gem_object_reference(&work->old_fb_obj->base);
8012 drm_gem_object_reference(&obj->base);
8016 work->pending_flip_obj = obj;
8018 work->enable_stall_check = true;
8020 atomic_inc(&intel_crtc->unpin_work_count);
8021 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8023 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8025 goto cleanup_pending;
8027 intel_disable_fbc(dev);
8028 intel_mark_fb_busy(obj, NULL);
8029 mutex_unlock(&dev->struct_mutex);
8031 trace_i915_flip_request(intel_crtc->plane, obj);
8036 atomic_dec(&intel_crtc->unpin_work_count);
8038 drm_gem_object_unreference(&work->old_fb_obj->base);
8039 drm_gem_object_unreference(&obj->base);
8040 mutex_unlock(&dev->struct_mutex);
8043 spin_lock_irqsave(&dev->event_lock, flags);
8044 intel_crtc->unpin_work = NULL;
8045 spin_unlock_irqrestore(&dev->event_lock, flags);
8047 drm_vblank_put(dev, intel_crtc->pipe);
8054 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8055 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8056 .load_lut = intel_crtc_load_lut,
8059 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8060 struct drm_crtc *crtc)
8062 struct drm_device *dev;
8063 struct drm_crtc *tmp;
8066 WARN(!crtc, "checking null crtc?\n");
8070 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8076 if (encoder->possible_crtcs & crtc_mask)
8082 * intel_modeset_update_staged_output_state
8084 * Updates the staged output configuration state, e.g. after we've read out the
8087 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8089 struct intel_encoder *encoder;
8090 struct intel_connector *connector;
8092 list_for_each_entry(connector, &dev->mode_config.connector_list,
8094 connector->new_encoder =
8095 to_intel_encoder(connector->base.encoder);
8098 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8101 to_intel_crtc(encoder->base.crtc);
8106 * intel_modeset_commit_output_state
8108 * This function copies the stage display pipe configuration to the real one.
8110 static void intel_modeset_commit_output_state(struct drm_device *dev)
8112 struct intel_encoder *encoder;
8113 struct intel_connector *connector;
8115 list_for_each_entry(connector, &dev->mode_config.connector_list,
8117 connector->base.encoder = &connector->new_encoder->base;
8120 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8122 encoder->base.crtc = &encoder->new_crtc->base;
8127 connected_sink_compute_bpp(struct intel_connector * connector,
8128 struct intel_crtc_config *pipe_config)
8130 int bpp = pipe_config->pipe_bpp;
8132 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8133 connector->base.base.id,
8134 drm_get_connector_name(&connector->base));
8136 /* Don't use an invalid EDID bpc value */
8137 if (connector->base.display_info.bpc &&
8138 connector->base.display_info.bpc * 3 < bpp) {
8139 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8140 bpp, connector->base.display_info.bpc*3);
8141 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8144 /* Clamp bpp to 8 on screens without EDID 1.4 */
8145 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8146 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8148 pipe_config->pipe_bpp = 24;
8153 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8154 struct drm_framebuffer *fb,
8155 struct intel_crtc_config *pipe_config)
8157 struct drm_device *dev = crtc->base.dev;
8158 struct intel_connector *connector;
8161 switch (fb->pixel_format) {
8163 bpp = 8*3; /* since we go through a colormap */
8165 case DRM_FORMAT_XRGB1555:
8166 case DRM_FORMAT_ARGB1555:
8167 /* checked in intel_framebuffer_init already */
8168 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8170 case DRM_FORMAT_RGB565:
8171 bpp = 6*3; /* min is 18bpp */
8173 case DRM_FORMAT_XBGR8888:
8174 case DRM_FORMAT_ABGR8888:
8175 /* checked in intel_framebuffer_init already */
8176 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8178 case DRM_FORMAT_XRGB8888:
8179 case DRM_FORMAT_ARGB8888:
8182 case DRM_FORMAT_XRGB2101010:
8183 case DRM_FORMAT_ARGB2101010:
8184 case DRM_FORMAT_XBGR2101010:
8185 case DRM_FORMAT_ABGR2101010:
8186 /* checked in intel_framebuffer_init already */
8187 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8191 /* TODO: gen4+ supports 16 bpc floating point, too. */
8193 DRM_DEBUG_KMS("unsupported depth\n");
8197 pipe_config->pipe_bpp = bpp;
8199 /* Clamp display bpp to EDID value */
8200 list_for_each_entry(connector, &dev->mode_config.connector_list,
8202 if (!connector->new_encoder ||
8203 connector->new_encoder->new_crtc != crtc)
8206 connected_sink_compute_bpp(connector, pipe_config);
8212 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8213 struct intel_crtc_config *pipe_config,
8214 const char *context)
8216 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8217 context, pipe_name(crtc->pipe));
8219 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8220 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8221 pipe_config->pipe_bpp, pipe_config->dither);
8222 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8223 pipe_config->has_pch_encoder,
8224 pipe_config->fdi_lanes,
8225 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8226 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8227 pipe_config->fdi_m_n.tu);
8228 DRM_DEBUG_KMS("requested mode:\n");
8229 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8230 DRM_DEBUG_KMS("adjusted mode:\n");
8231 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8232 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8233 pipe_config->gmch_pfit.control,
8234 pipe_config->gmch_pfit.pgm_ratios,
8235 pipe_config->gmch_pfit.lvds_border_bits);
8236 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8237 pipe_config->pch_pfit.pos,
8238 pipe_config->pch_pfit.size,
8239 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8240 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8243 static bool check_encoder_cloning(struct drm_crtc *crtc)
8245 int num_encoders = 0;
8246 bool uncloneable_encoders = false;
8247 struct intel_encoder *encoder;
8249 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8251 if (&encoder->new_crtc->base != crtc)
8255 if (!encoder->cloneable)
8256 uncloneable_encoders = true;
8259 return !(num_encoders > 1 && uncloneable_encoders);
8262 static struct intel_crtc_config *
8263 intel_modeset_pipe_config(struct drm_crtc *crtc,
8264 struct drm_framebuffer *fb,
8265 struct drm_display_mode *mode)
8267 struct drm_device *dev = crtc->dev;
8268 struct intel_encoder *encoder;
8269 struct intel_crtc_config *pipe_config;
8270 int plane_bpp, ret = -EINVAL;
8273 if (!check_encoder_cloning(crtc)) {
8274 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8275 return ERR_PTR(-EINVAL);
8278 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8280 return ERR_PTR(-ENOMEM);
8282 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8283 drm_mode_copy(&pipe_config->requested_mode, mode);
8284 pipe_config->cpu_transcoder =
8285 (enum transcoder) to_intel_crtc(crtc)->pipe;
8286 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8289 * Sanitize sync polarity flags based on requested ones. If neither
8290 * positive or negative polarity is requested, treat this as meaning
8291 * negative polarity.
8293 if (!(pipe_config->adjusted_mode.flags &
8294 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8295 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8297 if (!(pipe_config->adjusted_mode.flags &
8298 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8299 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8301 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8302 * plane pixel format and any sink constraints into account. Returns the
8303 * source plane bpp so that dithering can be selected on mismatches
8304 * after encoders and crtc also have had their say. */
8305 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8311 /* Ensure the port clock defaults are reset when retrying. */
8312 pipe_config->port_clock = 0;
8313 pipe_config->pixel_multiplier = 1;
8315 /* Fill in default crtc timings, allow encoders to overwrite them. */
8316 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8318 /* Pass our mode to the connectors and the CRTC to give them a chance to
8319 * adjust it according to limitations or connector properties, and also
8320 * a chance to reject the mode entirely.
8322 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8325 if (&encoder->new_crtc->base != crtc)
8328 if (!(encoder->compute_config(encoder, pipe_config))) {
8329 DRM_DEBUG_KMS("Encoder config failure\n");
8334 /* Set default port clock if not overwritten by the encoder. Needs to be
8335 * done afterwards in case the encoder adjusts the mode. */
8336 if (!pipe_config->port_clock)
8337 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8339 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8341 DRM_DEBUG_KMS("CRTC fixup failed\n");
8346 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8351 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8356 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8357 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8358 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8363 return ERR_PTR(ret);
8366 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8367 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8369 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8370 unsigned *prepare_pipes, unsigned *disable_pipes)
8372 struct intel_crtc *intel_crtc;
8373 struct drm_device *dev = crtc->dev;
8374 struct intel_encoder *encoder;
8375 struct intel_connector *connector;
8376 struct drm_crtc *tmp_crtc;
8378 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8380 /* Check which crtcs have changed outputs connected to them, these need
8381 * to be part of the prepare_pipes mask. We don't (yet) support global
8382 * modeset across multiple crtcs, so modeset_pipes will only have one
8383 * bit set at most. */
8384 list_for_each_entry(connector, &dev->mode_config.connector_list,
8386 if (connector->base.encoder == &connector->new_encoder->base)
8389 if (connector->base.encoder) {
8390 tmp_crtc = connector->base.encoder->crtc;
8392 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8395 if (connector->new_encoder)
8397 1 << connector->new_encoder->new_crtc->pipe;
8400 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8402 if (encoder->base.crtc == &encoder->new_crtc->base)
8405 if (encoder->base.crtc) {
8406 tmp_crtc = encoder->base.crtc;
8408 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8411 if (encoder->new_crtc)
8412 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8415 /* Check for any pipes that will be fully disabled ... */
8416 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8420 /* Don't try to disable disabled crtcs. */
8421 if (!intel_crtc->base.enabled)
8424 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8426 if (encoder->new_crtc == intel_crtc)
8431 *disable_pipes |= 1 << intel_crtc->pipe;
8435 /* set_mode is also used to update properties on life display pipes. */
8436 intel_crtc = to_intel_crtc(crtc);
8438 *prepare_pipes |= 1 << intel_crtc->pipe;
8441 * For simplicity do a full modeset on any pipe where the output routing
8442 * changed. We could be more clever, but that would require us to be
8443 * more careful with calling the relevant encoder->mode_set functions.
8446 *modeset_pipes = *prepare_pipes;
8448 /* ... and mask these out. */
8449 *modeset_pipes &= ~(*disable_pipes);
8450 *prepare_pipes &= ~(*disable_pipes);
8453 * HACK: We don't (yet) fully support global modesets. intel_set_config
8454 * obies this rule, but the modeset restore mode of
8455 * intel_modeset_setup_hw_state does not.
8457 *modeset_pipes &= 1 << intel_crtc->pipe;
8458 *prepare_pipes &= 1 << intel_crtc->pipe;
8460 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8461 *modeset_pipes, *prepare_pipes, *disable_pipes);
8464 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8466 struct drm_encoder *encoder;
8467 struct drm_device *dev = crtc->dev;
8469 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8470 if (encoder->crtc == crtc)
8477 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8479 struct intel_encoder *intel_encoder;
8480 struct intel_crtc *intel_crtc;
8481 struct drm_connector *connector;
8483 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8485 if (!intel_encoder->base.crtc)
8488 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8490 if (prepare_pipes & (1 << intel_crtc->pipe))
8491 intel_encoder->connectors_active = false;
8494 intel_modeset_commit_output_state(dev);
8496 /* Update computed state. */
8497 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8499 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8502 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8503 if (!connector->encoder || !connector->encoder->crtc)
8506 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8508 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8509 struct drm_property *dpms_property =
8510 dev->mode_config.dpms_property;
8512 connector->dpms = DRM_MODE_DPMS_ON;
8513 drm_object_property_set_value(&connector->base,
8517 intel_encoder = to_intel_encoder(connector->encoder);
8518 intel_encoder->connectors_active = true;
8524 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8525 struct intel_crtc_config *new)
8527 int clock1, clock2, diff;
8529 clock1 = cur->adjusted_mode.clock;
8530 clock2 = new->adjusted_mode.clock;
8532 if (clock1 == clock2)
8535 if (!clock1 || !clock2)
8538 diff = abs(clock1 - clock2);
8540 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8546 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8547 list_for_each_entry((intel_crtc), \
8548 &(dev)->mode_config.crtc_list, \
8550 if (mask & (1 <<(intel_crtc)->pipe))
8553 intel_pipe_config_compare(struct drm_device *dev,
8554 struct intel_crtc_config *current_config,
8555 struct intel_crtc_config *pipe_config)
8557 #define PIPE_CONF_CHECK_X(name) \
8558 if (current_config->name != pipe_config->name) { \
8559 DRM_ERROR("mismatch in " #name " " \
8560 "(expected 0x%08x, found 0x%08x)\n", \
8561 current_config->name, \
8562 pipe_config->name); \
8566 #define PIPE_CONF_CHECK_I(name) \
8567 if (current_config->name != pipe_config->name) { \
8568 DRM_ERROR("mismatch in " #name " " \
8569 "(expected %i, found %i)\n", \
8570 current_config->name, \
8571 pipe_config->name); \
8575 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8576 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8577 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8578 "(expected %i, found %i)\n", \
8579 current_config->name & (mask), \
8580 pipe_config->name & (mask)); \
8584 #define PIPE_CONF_QUIRK(quirk) \
8585 ((current_config->quirks | pipe_config->quirks) & (quirk))
8587 PIPE_CONF_CHECK_I(cpu_transcoder);
8589 PIPE_CONF_CHECK_I(has_pch_encoder);
8590 PIPE_CONF_CHECK_I(fdi_lanes);
8591 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8592 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8593 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8594 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8595 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8597 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8598 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8602 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8604 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8605 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8606 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8607 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8608 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8609 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8611 PIPE_CONF_CHECK_I(pixel_multiplier);
8613 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8614 DRM_MODE_FLAG_INTERLACE);
8616 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8617 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8618 DRM_MODE_FLAG_PHSYNC);
8619 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8620 DRM_MODE_FLAG_NHSYNC);
8621 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8622 DRM_MODE_FLAG_PVSYNC);
8623 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8624 DRM_MODE_FLAG_NVSYNC);
8627 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8628 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8630 PIPE_CONF_CHECK_I(gmch_pfit.control);
8631 /* pfit ratios are autocomputed by the hw on gen4+ */
8632 if (INTEL_INFO(dev)->gen < 4)
8633 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8634 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8635 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8636 if (current_config->pch_pfit.enabled) {
8637 PIPE_CONF_CHECK_I(pch_pfit.pos);
8638 PIPE_CONF_CHECK_I(pch_pfit.size);
8641 PIPE_CONF_CHECK_I(ips_enabled);
8643 PIPE_CONF_CHECK_I(shared_dpll);
8644 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8645 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8646 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8647 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8649 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8650 PIPE_CONF_CHECK_I(pipe_bpp);
8652 #undef PIPE_CONF_CHECK_X
8653 #undef PIPE_CONF_CHECK_I
8654 #undef PIPE_CONF_CHECK_FLAGS
8655 #undef PIPE_CONF_QUIRK
8657 if (!IS_HASWELL(dev)) {
8658 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8659 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8660 current_config->adjusted_mode.clock,
8661 pipe_config->adjusted_mode.clock);
8670 check_connector_state(struct drm_device *dev)
8672 struct intel_connector *connector;
8674 list_for_each_entry(connector, &dev->mode_config.connector_list,
8676 /* This also checks the encoder/connector hw state with the
8677 * ->get_hw_state callbacks. */
8678 intel_connector_check_state(connector);
8680 WARN(&connector->new_encoder->base != connector->base.encoder,
8681 "connector's staged encoder doesn't match current encoder\n");
8686 check_encoder_state(struct drm_device *dev)
8688 struct intel_encoder *encoder;
8689 struct intel_connector *connector;
8691 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8693 bool enabled = false;
8694 bool active = false;
8695 enum pipe pipe, tracked_pipe;
8697 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8698 encoder->base.base.id,
8699 drm_get_encoder_name(&encoder->base));
8701 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8702 "encoder's stage crtc doesn't match current crtc\n");
8703 WARN(encoder->connectors_active && !encoder->base.crtc,
8704 "encoder's active_connectors set, but no crtc\n");
8706 list_for_each_entry(connector, &dev->mode_config.connector_list,
8708 if (connector->base.encoder != &encoder->base)
8711 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8714 WARN(!!encoder->base.crtc != enabled,
8715 "encoder's enabled state mismatch "
8716 "(expected %i, found %i)\n",
8717 !!encoder->base.crtc, enabled);
8718 WARN(active && !encoder->base.crtc,
8719 "active encoder with no crtc\n");
8721 WARN(encoder->connectors_active != active,
8722 "encoder's computed active state doesn't match tracked active state "
8723 "(expected %i, found %i)\n", active, encoder->connectors_active);
8725 active = encoder->get_hw_state(encoder, &pipe);
8726 WARN(active != encoder->connectors_active,
8727 "encoder's hw state doesn't match sw tracking "
8728 "(expected %i, found %i)\n",
8729 encoder->connectors_active, active);
8731 if (!encoder->base.crtc)
8734 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8735 WARN(active && pipe != tracked_pipe,
8736 "active encoder's pipe doesn't match"
8737 "(expected %i, found %i)\n",
8738 tracked_pipe, pipe);
8744 check_crtc_state(struct drm_device *dev)
8746 drm_i915_private_t *dev_priv = dev->dev_private;
8747 struct intel_crtc *crtc;
8748 struct intel_encoder *encoder;
8749 struct intel_crtc_config pipe_config;
8751 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8753 bool enabled = false;
8754 bool active = false;
8756 memset(&pipe_config, 0, sizeof(pipe_config));
8758 DRM_DEBUG_KMS("[CRTC:%d]\n",
8759 crtc->base.base.id);
8761 WARN(crtc->active && !crtc->base.enabled,
8762 "active crtc, but not enabled in sw tracking\n");
8764 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8766 if (encoder->base.crtc != &crtc->base)
8769 if (encoder->connectors_active)
8773 WARN(active != crtc->active,
8774 "crtc's computed active state doesn't match tracked active state "
8775 "(expected %i, found %i)\n", active, crtc->active);
8776 WARN(enabled != crtc->base.enabled,
8777 "crtc's computed enabled state doesn't match tracked enabled state "
8778 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8780 active = dev_priv->display.get_pipe_config(crtc,
8783 /* hw state is inconsistent with the pipe A quirk */
8784 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8785 active = crtc->active;
8787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8790 if (encoder->base.crtc != &crtc->base)
8792 if (encoder->get_config &&
8793 encoder->get_hw_state(encoder, &pipe))
8794 encoder->get_config(encoder, &pipe_config);
8797 if (dev_priv->display.get_clock)
8798 dev_priv->display.get_clock(crtc, &pipe_config);
8800 WARN(crtc->active != active,
8801 "crtc active state doesn't match with hw state "
8802 "(expected %i, found %i)\n", crtc->active, active);
8805 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8806 WARN(1, "pipe state doesn't match!\n");
8807 intel_dump_pipe_config(crtc, &pipe_config,
8809 intel_dump_pipe_config(crtc, &crtc->config,
8816 check_shared_dpll_state(struct drm_device *dev)
8818 drm_i915_private_t *dev_priv = dev->dev_private;
8819 struct intel_crtc *crtc;
8820 struct intel_dpll_hw_state dpll_hw_state;
8823 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8824 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8825 int enabled_crtcs = 0, active_crtcs = 0;
8828 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8830 DRM_DEBUG_KMS("%s\n", pll->name);
8832 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8834 WARN(pll->active > pll->refcount,
8835 "more active pll users than references: %i vs %i\n",
8836 pll->active, pll->refcount);
8837 WARN(pll->active && !pll->on,
8838 "pll in active use but not on in sw tracking\n");
8839 WARN(pll->on && !pll->active,
8840 "pll in on but not on in use in sw tracking\n");
8841 WARN(pll->on != active,
8842 "pll on state mismatch (expected %i, found %i)\n",
8845 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8847 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8849 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8852 WARN(pll->active != active_crtcs,
8853 "pll active crtcs mismatch (expected %i, found %i)\n",
8854 pll->active, active_crtcs);
8855 WARN(pll->refcount != enabled_crtcs,
8856 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8857 pll->refcount, enabled_crtcs);
8859 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8860 sizeof(dpll_hw_state)),
8861 "pll hw state mismatch\n");
8866 intel_modeset_check_state(struct drm_device *dev)
8868 check_connector_state(dev);
8869 check_encoder_state(dev);
8870 check_crtc_state(dev);
8871 check_shared_dpll_state(dev);
8874 static int __intel_set_mode(struct drm_crtc *crtc,
8875 struct drm_display_mode *mode,
8876 int x, int y, struct drm_framebuffer *fb)
8878 struct drm_device *dev = crtc->dev;
8879 drm_i915_private_t *dev_priv = dev->dev_private;
8880 struct drm_display_mode *saved_mode, *saved_hwmode;
8881 struct intel_crtc_config *pipe_config = NULL;
8882 struct intel_crtc *intel_crtc;
8883 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8886 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8889 saved_hwmode = saved_mode + 1;
8891 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8892 &prepare_pipes, &disable_pipes);
8894 *saved_hwmode = crtc->hwmode;
8895 *saved_mode = crtc->mode;
8897 /* Hack: Because we don't (yet) support global modeset on multiple
8898 * crtcs, we don't keep track of the new mode for more than one crtc.
8899 * Hence simply check whether any bit is set in modeset_pipes in all the
8900 * pieces of code that are not yet converted to deal with mutliple crtcs
8901 * changing their mode at the same time. */
8902 if (modeset_pipes) {
8903 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8904 if (IS_ERR(pipe_config)) {
8905 ret = PTR_ERR(pipe_config);
8910 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8914 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8915 intel_crtc_disable(&intel_crtc->base);
8917 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8918 if (intel_crtc->base.enabled)
8919 dev_priv->display.crtc_disable(&intel_crtc->base);
8922 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8923 * to set it here already despite that we pass it down the callchain.
8925 if (modeset_pipes) {
8927 /* mode_set/enable/disable functions rely on a correct pipe
8929 to_intel_crtc(crtc)->config = *pipe_config;
8932 /* Only after disabling all output pipelines that will be changed can we
8933 * update the the output configuration. */
8934 intel_modeset_update_state(dev, prepare_pipes);
8936 if (dev_priv->display.modeset_global_resources)
8937 dev_priv->display.modeset_global_resources(dev);
8939 /* Set up the DPLL and any encoders state that needs to adjust or depend
8942 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8943 ret = intel_crtc_mode_set(&intel_crtc->base,
8949 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8950 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8951 dev_priv->display.crtc_enable(&intel_crtc->base);
8953 if (modeset_pipes) {
8954 /* Store real post-adjustment hardware mode. */
8955 crtc->hwmode = pipe_config->adjusted_mode;
8957 /* Calculate and store various constants which
8958 * are later needed by vblank and swap-completion
8959 * timestamping. They are derived from true hwmode.
8961 drm_calc_timestamping_constants(crtc);
8964 /* FIXME: add subpixel order */
8966 if (ret && crtc->enabled) {
8967 crtc->hwmode = *saved_hwmode;
8968 crtc->mode = *saved_mode;
8977 static int intel_set_mode(struct drm_crtc *crtc,
8978 struct drm_display_mode *mode,
8979 int x, int y, struct drm_framebuffer *fb)
8983 ret = __intel_set_mode(crtc, mode, x, y, fb);
8986 intel_modeset_check_state(crtc->dev);
8991 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8993 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8996 #undef for_each_intel_crtc_masked
8998 static void intel_set_config_free(struct intel_set_config *config)
9003 kfree(config->save_connector_encoders);
9004 kfree(config->save_encoder_crtcs);
9008 static int intel_set_config_save_state(struct drm_device *dev,
9009 struct intel_set_config *config)
9011 struct drm_encoder *encoder;
9012 struct drm_connector *connector;
9015 config->save_encoder_crtcs =
9016 kcalloc(dev->mode_config.num_encoder,
9017 sizeof(struct drm_crtc *), GFP_KERNEL);
9018 if (!config->save_encoder_crtcs)
9021 config->save_connector_encoders =
9022 kcalloc(dev->mode_config.num_connector,
9023 sizeof(struct drm_encoder *), GFP_KERNEL);
9024 if (!config->save_connector_encoders)
9027 /* Copy data. Note that driver private data is not affected.
9028 * Should anything bad happen only the expected state is
9029 * restored, not the drivers personal bookkeeping.
9032 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9033 config->save_encoder_crtcs[count++] = encoder->crtc;
9037 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9038 config->save_connector_encoders[count++] = connector->encoder;
9044 static void intel_set_config_restore_state(struct drm_device *dev,
9045 struct intel_set_config *config)
9047 struct intel_encoder *encoder;
9048 struct intel_connector *connector;
9052 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9054 to_intel_crtc(config->save_encoder_crtcs[count++]);
9058 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9059 connector->new_encoder =
9060 to_intel_encoder(config->save_connector_encoders[count++]);
9065 is_crtc_connector_off(struct drm_mode_set *set)
9069 if (set->num_connectors == 0)
9072 if (WARN_ON(set->connectors == NULL))
9075 for (i = 0; i < set->num_connectors; i++)
9076 if (set->connectors[i]->encoder &&
9077 set->connectors[i]->encoder->crtc == set->crtc &&
9078 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9085 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9086 struct intel_set_config *config)
9089 /* We should be able to check here if the fb has the same properties
9090 * and then just flip_or_move it */
9091 if (is_crtc_connector_off(set)) {
9092 config->mode_changed = true;
9093 } else if (set->crtc->fb != set->fb) {
9094 /* If we have no fb then treat it as a full mode set */
9095 if (set->crtc->fb == NULL) {
9096 struct intel_crtc *intel_crtc =
9097 to_intel_crtc(set->crtc);
9099 if (intel_crtc->active && i915_fastboot) {
9100 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9101 config->fb_changed = true;
9103 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9104 config->mode_changed = true;
9106 } else if (set->fb == NULL) {
9107 config->mode_changed = true;
9108 } else if (set->fb->pixel_format !=
9109 set->crtc->fb->pixel_format) {
9110 config->mode_changed = true;
9112 config->fb_changed = true;
9116 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9117 config->fb_changed = true;
9119 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9120 DRM_DEBUG_KMS("modes are different, full mode set\n");
9121 drm_mode_debug_printmodeline(&set->crtc->mode);
9122 drm_mode_debug_printmodeline(set->mode);
9123 config->mode_changed = true;
9126 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9127 set->crtc->base.id, config->mode_changed, config->fb_changed);
9131 intel_modeset_stage_output_state(struct drm_device *dev,
9132 struct drm_mode_set *set,
9133 struct intel_set_config *config)
9135 struct drm_crtc *new_crtc;
9136 struct intel_connector *connector;
9137 struct intel_encoder *encoder;
9140 /* The upper layers ensure that we either disable a crtc or have a list
9141 * of connectors. For paranoia, double-check this. */
9142 WARN_ON(!set->fb && (set->num_connectors != 0));
9143 WARN_ON(set->fb && (set->num_connectors == 0));
9145 list_for_each_entry(connector, &dev->mode_config.connector_list,
9147 /* Otherwise traverse passed in connector list and get encoders
9149 for (ro = 0; ro < set->num_connectors; ro++) {
9150 if (set->connectors[ro] == &connector->base) {
9151 connector->new_encoder = connector->encoder;
9156 /* If we disable the crtc, disable all its connectors. Also, if
9157 * the connector is on the changing crtc but not on the new
9158 * connector list, disable it. */
9159 if ((!set->fb || ro == set->num_connectors) &&
9160 connector->base.encoder &&
9161 connector->base.encoder->crtc == set->crtc) {
9162 connector->new_encoder = NULL;
9164 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9165 connector->base.base.id,
9166 drm_get_connector_name(&connector->base));
9170 if (&connector->new_encoder->base != connector->base.encoder) {
9171 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9172 config->mode_changed = true;
9175 /* connector->new_encoder is now updated for all connectors. */
9177 /* Update crtc of enabled connectors. */
9178 list_for_each_entry(connector, &dev->mode_config.connector_list,
9180 if (!connector->new_encoder)
9183 new_crtc = connector->new_encoder->base.crtc;
9185 for (ro = 0; ro < set->num_connectors; ro++) {
9186 if (set->connectors[ro] == &connector->base)
9187 new_crtc = set->crtc;
9190 /* Make sure the new CRTC will work with the encoder */
9191 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9195 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9197 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9198 connector->base.base.id,
9199 drm_get_connector_name(&connector->base),
9203 /* Check for any encoders that needs to be disabled. */
9204 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9206 list_for_each_entry(connector,
9207 &dev->mode_config.connector_list,
9209 if (connector->new_encoder == encoder) {
9210 WARN_ON(!connector->new_encoder->new_crtc);
9215 encoder->new_crtc = NULL;
9217 /* Only now check for crtc changes so we don't miss encoders
9218 * that will be disabled. */
9219 if (&encoder->new_crtc->base != encoder->base.crtc) {
9220 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9221 config->mode_changed = true;
9224 /* Now we've also updated encoder->new_crtc for all encoders. */
9229 static int intel_crtc_set_config(struct drm_mode_set *set)
9231 struct drm_device *dev;
9232 struct drm_mode_set save_set;
9233 struct intel_set_config *config;
9238 BUG_ON(!set->crtc->helper_private);
9240 /* Enforce sane interface api - has been abused by the fb helper. */
9241 BUG_ON(!set->mode && set->fb);
9242 BUG_ON(set->fb && set->num_connectors == 0);
9245 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9246 set->crtc->base.id, set->fb->base.id,
9247 (int)set->num_connectors, set->x, set->y);
9249 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9252 dev = set->crtc->dev;
9255 config = kzalloc(sizeof(*config), GFP_KERNEL);
9259 ret = intel_set_config_save_state(dev, config);
9263 save_set.crtc = set->crtc;
9264 save_set.mode = &set->crtc->mode;
9265 save_set.x = set->crtc->x;
9266 save_set.y = set->crtc->y;
9267 save_set.fb = set->crtc->fb;
9269 /* Compute whether we need a full modeset, only an fb base update or no
9270 * change at all. In the future we might also check whether only the
9271 * mode changed, e.g. for LVDS where we only change the panel fitter in
9273 intel_set_config_compute_mode_changes(set, config);
9275 ret = intel_modeset_stage_output_state(dev, set, config);
9279 if (config->mode_changed) {
9280 ret = intel_set_mode(set->crtc, set->mode,
9281 set->x, set->y, set->fb);
9282 } else if (config->fb_changed) {
9283 intel_crtc_wait_for_pending_flips(set->crtc);
9285 ret = intel_pipe_set_base(set->crtc,
9286 set->x, set->y, set->fb);
9290 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9291 set->crtc->base.id, ret);
9293 intel_set_config_restore_state(dev, config);
9295 /* Try to restore the config */
9296 if (config->mode_changed &&
9297 intel_set_mode(save_set.crtc, save_set.mode,
9298 save_set.x, save_set.y, save_set.fb))
9299 DRM_ERROR("failed to restore config after modeset failure\n");
9303 intel_set_config_free(config);
9307 static const struct drm_crtc_funcs intel_crtc_funcs = {
9308 .cursor_set = intel_crtc_cursor_set,
9309 .cursor_move = intel_crtc_cursor_move,
9310 .gamma_set = intel_crtc_gamma_set,
9311 .set_config = intel_crtc_set_config,
9312 .destroy = intel_crtc_destroy,
9313 .page_flip = intel_crtc_page_flip,
9316 static void intel_cpu_pll_init(struct drm_device *dev)
9319 intel_ddi_pll_init(dev);
9322 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9323 struct intel_shared_dpll *pll,
9324 struct intel_dpll_hw_state *hw_state)
9328 val = I915_READ(PCH_DPLL(pll->id));
9329 hw_state->dpll = val;
9330 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9331 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9333 return val & DPLL_VCO_ENABLE;
9336 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9337 struct intel_shared_dpll *pll)
9339 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9340 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9343 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9344 struct intel_shared_dpll *pll)
9346 /* PCH refclock must be enabled first */
9347 assert_pch_refclk_enabled(dev_priv);
9349 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9351 /* Wait for the clocks to stabilize. */
9352 POSTING_READ(PCH_DPLL(pll->id));
9355 /* The pixel multiplier can only be updated once the
9356 * DPLL is enabled and the clocks are stable.
9358 * So write it again.
9360 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9361 POSTING_READ(PCH_DPLL(pll->id));
9365 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9366 struct intel_shared_dpll *pll)
9368 struct drm_device *dev = dev_priv->dev;
9369 struct intel_crtc *crtc;
9371 /* Make sure no transcoder isn't still depending on us. */
9372 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9373 if (intel_crtc_to_shared_dpll(crtc) == pll)
9374 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9377 I915_WRITE(PCH_DPLL(pll->id), 0);
9378 POSTING_READ(PCH_DPLL(pll->id));
9382 static char *ibx_pch_dpll_names[] = {
9387 static void ibx_pch_dpll_init(struct drm_device *dev)
9389 struct drm_i915_private *dev_priv = dev->dev_private;
9392 dev_priv->num_shared_dpll = 2;
9394 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9395 dev_priv->shared_dplls[i].id = i;
9396 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9397 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9398 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9399 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9400 dev_priv->shared_dplls[i].get_hw_state =
9401 ibx_pch_dpll_get_hw_state;
9405 static void intel_shared_dpll_init(struct drm_device *dev)
9407 struct drm_i915_private *dev_priv = dev->dev_private;
9409 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9410 ibx_pch_dpll_init(dev);
9412 dev_priv->num_shared_dpll = 0;
9414 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9415 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9416 dev_priv->num_shared_dpll);
9419 static void intel_crtc_init(struct drm_device *dev, int pipe)
9421 drm_i915_private_t *dev_priv = dev->dev_private;
9422 struct intel_crtc *intel_crtc;
9425 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9426 if (intel_crtc == NULL)
9429 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9431 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9432 for (i = 0; i < 256; i++) {
9433 intel_crtc->lut_r[i] = i;
9434 intel_crtc->lut_g[i] = i;
9435 intel_crtc->lut_b[i] = i;
9438 /* Swap pipes & planes for FBC on pre-965 */
9439 intel_crtc->pipe = pipe;
9440 intel_crtc->plane = pipe;
9441 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9442 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9443 intel_crtc->plane = !pipe;
9446 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9447 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9448 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9449 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9451 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9454 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9455 struct drm_file *file)
9457 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9458 struct drm_mode_object *drmmode_obj;
9459 struct intel_crtc *crtc;
9461 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9464 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9465 DRM_MODE_OBJECT_CRTC);
9468 DRM_ERROR("no such CRTC id\n");
9472 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9473 pipe_from_crtc_id->pipe = crtc->pipe;
9478 static int intel_encoder_clones(struct intel_encoder *encoder)
9480 struct drm_device *dev = encoder->base.dev;
9481 struct intel_encoder *source_encoder;
9485 list_for_each_entry(source_encoder,
9486 &dev->mode_config.encoder_list, base.head) {
9488 if (encoder == source_encoder)
9489 index_mask |= (1 << entry);
9491 /* Intel hw has only one MUX where enocoders could be cloned. */
9492 if (encoder->cloneable && source_encoder->cloneable)
9493 index_mask |= (1 << entry);
9501 static bool has_edp_a(struct drm_device *dev)
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9505 if (!IS_MOBILE(dev))
9508 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9512 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9518 static void intel_setup_outputs(struct drm_device *dev)
9520 struct drm_i915_private *dev_priv = dev->dev_private;
9521 struct intel_encoder *encoder;
9522 bool dpd_is_edp = false;
9524 intel_lvds_init(dev);
9527 intel_crt_init(dev);
9532 /* Haswell uses DDI functions to detect digital outputs */
9533 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9534 /* DDI A only supports eDP */
9536 intel_ddi_init(dev, PORT_A);
9538 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9540 found = I915_READ(SFUSE_STRAP);
9542 if (found & SFUSE_STRAP_DDIB_DETECTED)
9543 intel_ddi_init(dev, PORT_B);
9544 if (found & SFUSE_STRAP_DDIC_DETECTED)
9545 intel_ddi_init(dev, PORT_C);
9546 if (found & SFUSE_STRAP_DDID_DETECTED)
9547 intel_ddi_init(dev, PORT_D);
9548 } else if (HAS_PCH_SPLIT(dev)) {
9550 dpd_is_edp = intel_dpd_is_edp(dev);
9553 intel_dp_init(dev, DP_A, PORT_A);
9555 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9556 /* PCH SDVOB multiplex with HDMIB */
9557 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9559 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9560 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9561 intel_dp_init(dev, PCH_DP_B, PORT_B);
9564 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9565 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9567 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9568 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9570 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9571 intel_dp_init(dev, PCH_DP_C, PORT_C);
9573 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9574 intel_dp_init(dev, PCH_DP_D, PORT_D);
9575 } else if (IS_VALLEYVIEW(dev)) {
9576 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9577 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9578 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9580 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9581 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9585 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9586 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9588 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9589 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9591 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9594 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9595 DRM_DEBUG_KMS("probing SDVOB\n");
9596 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9597 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9598 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9599 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9602 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9603 intel_dp_init(dev, DP_B, PORT_B);
9606 /* Before G4X SDVOC doesn't have its own detect register */
9608 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9609 DRM_DEBUG_KMS("probing SDVOC\n");
9610 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9613 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9615 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9616 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9617 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9619 if (SUPPORTS_INTEGRATED_DP(dev))
9620 intel_dp_init(dev, DP_C, PORT_C);
9623 if (SUPPORTS_INTEGRATED_DP(dev) &&
9624 (I915_READ(DP_D) & DP_DETECTED))
9625 intel_dp_init(dev, DP_D, PORT_D);
9626 } else if (IS_GEN2(dev))
9627 intel_dvo_init(dev);
9629 if (SUPPORTS_TV(dev))
9632 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9633 encoder->base.possible_crtcs = encoder->crtc_mask;
9634 encoder->base.possible_clones =
9635 intel_encoder_clones(encoder);
9638 intel_init_pch_refclk(dev);
9640 drm_helper_move_panel_connectors_to_head(dev);
9643 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9645 drm_framebuffer_cleanup(&fb->base);
9646 drm_gem_object_unreference_unlocked(&fb->obj->base);
9649 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9651 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9653 intel_framebuffer_fini(intel_fb);
9657 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9658 struct drm_file *file,
9659 unsigned int *handle)
9661 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9662 struct drm_i915_gem_object *obj = intel_fb->obj;
9664 return drm_gem_handle_create(file, &obj->base, handle);
9667 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9668 .destroy = intel_user_framebuffer_destroy,
9669 .create_handle = intel_user_framebuffer_create_handle,
9672 int intel_framebuffer_init(struct drm_device *dev,
9673 struct intel_framebuffer *intel_fb,
9674 struct drm_mode_fb_cmd2 *mode_cmd,
9675 struct drm_i915_gem_object *obj)
9680 if (obj->tiling_mode == I915_TILING_Y) {
9681 DRM_DEBUG("hardware does not support tiling Y\n");
9685 if (mode_cmd->pitches[0] & 63) {
9686 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9687 mode_cmd->pitches[0]);
9691 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9692 pitch_limit = 32*1024;
9693 } else if (INTEL_INFO(dev)->gen >= 4) {
9694 if (obj->tiling_mode)
9695 pitch_limit = 16*1024;
9697 pitch_limit = 32*1024;
9698 } else if (INTEL_INFO(dev)->gen >= 3) {
9699 if (obj->tiling_mode)
9700 pitch_limit = 8*1024;
9702 pitch_limit = 16*1024;
9704 /* XXX DSPC is limited to 4k tiled */
9705 pitch_limit = 8*1024;
9707 if (mode_cmd->pitches[0] > pitch_limit) {
9708 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9709 obj->tiling_mode ? "tiled" : "linear",
9710 mode_cmd->pitches[0], pitch_limit);
9714 if (obj->tiling_mode != I915_TILING_NONE &&
9715 mode_cmd->pitches[0] != obj->stride) {
9716 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9717 mode_cmd->pitches[0], obj->stride);
9721 /* Reject formats not supported by any plane early. */
9722 switch (mode_cmd->pixel_format) {
9724 case DRM_FORMAT_RGB565:
9725 case DRM_FORMAT_XRGB8888:
9726 case DRM_FORMAT_ARGB8888:
9728 case DRM_FORMAT_XRGB1555:
9729 case DRM_FORMAT_ARGB1555:
9730 if (INTEL_INFO(dev)->gen > 3) {
9731 DRM_DEBUG("unsupported pixel format: %s\n",
9732 drm_get_format_name(mode_cmd->pixel_format));
9736 case DRM_FORMAT_XBGR8888:
9737 case DRM_FORMAT_ABGR8888:
9738 case DRM_FORMAT_XRGB2101010:
9739 case DRM_FORMAT_ARGB2101010:
9740 case DRM_FORMAT_XBGR2101010:
9741 case DRM_FORMAT_ABGR2101010:
9742 if (INTEL_INFO(dev)->gen < 4) {
9743 DRM_DEBUG("unsupported pixel format: %s\n",
9744 drm_get_format_name(mode_cmd->pixel_format));
9748 case DRM_FORMAT_YUYV:
9749 case DRM_FORMAT_UYVY:
9750 case DRM_FORMAT_YVYU:
9751 case DRM_FORMAT_VYUY:
9752 if (INTEL_INFO(dev)->gen < 5) {
9753 DRM_DEBUG("unsupported pixel format: %s\n",
9754 drm_get_format_name(mode_cmd->pixel_format));
9759 DRM_DEBUG("unsupported pixel format: %s\n",
9760 drm_get_format_name(mode_cmd->pixel_format));
9764 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9765 if (mode_cmd->offsets[0] != 0)
9768 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9769 intel_fb->obj = obj;
9771 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9773 DRM_ERROR("framebuffer init failed %d\n", ret);
9780 static struct drm_framebuffer *
9781 intel_user_framebuffer_create(struct drm_device *dev,
9782 struct drm_file *filp,
9783 struct drm_mode_fb_cmd2 *mode_cmd)
9785 struct drm_i915_gem_object *obj;
9787 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9788 mode_cmd->handles[0]));
9789 if (&obj->base == NULL)
9790 return ERR_PTR(-ENOENT);
9792 return intel_framebuffer_create(dev, mode_cmd, obj);
9795 static const struct drm_mode_config_funcs intel_mode_funcs = {
9796 .fb_create = intel_user_framebuffer_create,
9797 .output_poll_changed = intel_fb_output_poll_changed,
9800 /* Set up chip specific display functions */
9801 static void intel_init_display(struct drm_device *dev)
9803 struct drm_i915_private *dev_priv = dev->dev_private;
9805 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9806 dev_priv->display.find_dpll = g4x_find_best_dpll;
9807 else if (IS_VALLEYVIEW(dev))
9808 dev_priv->display.find_dpll = vlv_find_best_dpll;
9809 else if (IS_PINEVIEW(dev))
9810 dev_priv->display.find_dpll = pnv_find_best_dpll;
9812 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9815 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9816 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9817 dev_priv->display.crtc_enable = haswell_crtc_enable;
9818 dev_priv->display.crtc_disable = haswell_crtc_disable;
9819 dev_priv->display.off = haswell_crtc_off;
9820 dev_priv->display.update_plane = ironlake_update_plane;
9821 } else if (HAS_PCH_SPLIT(dev)) {
9822 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9823 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9824 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9825 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9826 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9827 dev_priv->display.off = ironlake_crtc_off;
9828 dev_priv->display.update_plane = ironlake_update_plane;
9829 } else if (IS_VALLEYVIEW(dev)) {
9830 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9831 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9832 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9833 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9834 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9835 dev_priv->display.off = i9xx_crtc_off;
9836 dev_priv->display.update_plane = i9xx_update_plane;
9838 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9839 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9840 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9841 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9842 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9843 dev_priv->display.off = i9xx_crtc_off;
9844 dev_priv->display.update_plane = i9xx_update_plane;
9847 /* Returns the core display clock speed */
9848 if (IS_VALLEYVIEW(dev))
9849 dev_priv->display.get_display_clock_speed =
9850 valleyview_get_display_clock_speed;
9851 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9852 dev_priv->display.get_display_clock_speed =
9853 i945_get_display_clock_speed;
9854 else if (IS_I915G(dev))
9855 dev_priv->display.get_display_clock_speed =
9856 i915_get_display_clock_speed;
9857 else if (IS_I945GM(dev) || IS_845G(dev))
9858 dev_priv->display.get_display_clock_speed =
9859 i9xx_misc_get_display_clock_speed;
9860 else if (IS_PINEVIEW(dev))
9861 dev_priv->display.get_display_clock_speed =
9862 pnv_get_display_clock_speed;
9863 else if (IS_I915GM(dev))
9864 dev_priv->display.get_display_clock_speed =
9865 i915gm_get_display_clock_speed;
9866 else if (IS_I865G(dev))
9867 dev_priv->display.get_display_clock_speed =
9868 i865_get_display_clock_speed;
9869 else if (IS_I85X(dev))
9870 dev_priv->display.get_display_clock_speed =
9871 i855_get_display_clock_speed;
9873 dev_priv->display.get_display_clock_speed =
9874 i830_get_display_clock_speed;
9876 if (HAS_PCH_SPLIT(dev)) {
9878 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9879 dev_priv->display.write_eld = ironlake_write_eld;
9880 } else if (IS_GEN6(dev)) {
9881 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9882 dev_priv->display.write_eld = ironlake_write_eld;
9883 } else if (IS_IVYBRIDGE(dev)) {
9884 /* FIXME: detect B0+ stepping and use auto training */
9885 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9886 dev_priv->display.write_eld = ironlake_write_eld;
9887 dev_priv->display.modeset_global_resources =
9888 ivb_modeset_global_resources;
9889 } else if (IS_HASWELL(dev)) {
9890 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9891 dev_priv->display.write_eld = haswell_write_eld;
9892 dev_priv->display.modeset_global_resources =
9893 haswell_modeset_global_resources;
9895 } else if (IS_G4X(dev)) {
9896 dev_priv->display.write_eld = g4x_write_eld;
9899 /* Default just returns -ENODEV to indicate unsupported */
9900 dev_priv->display.queue_flip = intel_default_queue_flip;
9902 switch (INTEL_INFO(dev)->gen) {
9904 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9908 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9913 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9917 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9920 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9926 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9927 * resume, or other times. This quirk makes sure that's the case for
9930 static void quirk_pipea_force(struct drm_device *dev)
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9934 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9935 DRM_INFO("applying pipe a force quirk\n");
9939 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9941 static void quirk_ssc_force_disable(struct drm_device *dev)
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9945 DRM_INFO("applying lvds SSC disable quirk\n");
9949 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9952 static void quirk_invert_brightness(struct drm_device *dev)
9954 struct drm_i915_private *dev_priv = dev->dev_private;
9955 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9956 DRM_INFO("applying inverted panel brightness quirk\n");
9960 * Some machines (Dell XPS13) suffer broken backlight controls if
9961 * BLM_PCH_PWM_ENABLE is set.
9963 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9965 struct drm_i915_private *dev_priv = dev->dev_private;
9966 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9967 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9970 struct intel_quirk {
9972 int subsystem_vendor;
9973 int subsystem_device;
9974 void (*hook)(struct drm_device *dev);
9977 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9978 struct intel_dmi_quirk {
9979 void (*hook)(struct drm_device *dev);
9980 const struct dmi_system_id (*dmi_id_list)[];
9983 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9985 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9989 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9991 .dmi_id_list = &(const struct dmi_system_id[]) {
9993 .callback = intel_dmi_reverse_brightness,
9994 .ident = "NCR Corporation",
9995 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9996 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9999 { } /* terminating entry */
10001 .hook = quirk_invert_brightness,
10005 static struct intel_quirk intel_quirks[] = {
10006 /* HP Mini needs pipe A force quirk (LP: #322104) */
10007 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10009 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10010 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10012 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10013 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10015 /* 830/845 need to leave pipe A & dpll A up */
10016 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10017 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10019 /* Lenovo U160 cannot use SSC on LVDS */
10020 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10022 /* Sony Vaio Y cannot use SSC on LVDS */
10023 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10025 /* Acer Aspire 5734Z must invert backlight brightness */
10026 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10028 /* Acer/eMachines G725 */
10029 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10031 /* Acer/eMachines e725 */
10032 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10034 /* Acer/Packard Bell NCL20 */
10035 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10037 /* Acer Aspire 4736Z */
10038 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10040 /* Dell XPS13 HD Sandy Bridge */
10041 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10042 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10043 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10046 static void intel_init_quirks(struct drm_device *dev)
10048 struct pci_dev *d = dev->pdev;
10051 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10052 struct intel_quirk *q = &intel_quirks[i];
10054 if (d->device == q->device &&
10055 (d->subsystem_vendor == q->subsystem_vendor ||
10056 q->subsystem_vendor == PCI_ANY_ID) &&
10057 (d->subsystem_device == q->subsystem_device ||
10058 q->subsystem_device == PCI_ANY_ID))
10061 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10062 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10063 intel_dmi_quirks[i].hook(dev);
10067 /* Disable the VGA plane that we never use */
10068 static void i915_disable_vga(struct drm_device *dev)
10070 struct drm_i915_private *dev_priv = dev->dev_private;
10072 u32 vga_reg = i915_vgacntrl_reg(dev);
10074 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10075 outb(SR01, VGA_SR_INDEX);
10076 sr1 = inb(VGA_SR_DATA);
10077 outb(sr1 | 1<<5, VGA_SR_DATA);
10078 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10081 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10082 POSTING_READ(vga_reg);
10085 void intel_modeset_init_hw(struct drm_device *dev)
10087 intel_init_power_well(dev);
10089 intel_prepare_ddi(dev);
10091 intel_init_clock_gating(dev);
10093 mutex_lock(&dev->struct_mutex);
10094 intel_enable_gt_powersave(dev);
10095 mutex_unlock(&dev->struct_mutex);
10098 void intel_modeset_suspend_hw(struct drm_device *dev)
10100 intel_suspend_hw(dev);
10103 void intel_modeset_init(struct drm_device *dev)
10105 struct drm_i915_private *dev_priv = dev->dev_private;
10108 drm_mode_config_init(dev);
10110 dev->mode_config.min_width = 0;
10111 dev->mode_config.min_height = 0;
10113 dev->mode_config.preferred_depth = 24;
10114 dev->mode_config.prefer_shadow = 1;
10116 dev->mode_config.funcs = &intel_mode_funcs;
10118 intel_init_quirks(dev);
10120 intel_init_pm(dev);
10122 if (INTEL_INFO(dev)->num_pipes == 0)
10125 intel_init_display(dev);
10127 if (IS_GEN2(dev)) {
10128 dev->mode_config.max_width = 2048;
10129 dev->mode_config.max_height = 2048;
10130 } else if (IS_GEN3(dev)) {
10131 dev->mode_config.max_width = 4096;
10132 dev->mode_config.max_height = 4096;
10134 dev->mode_config.max_width = 8192;
10135 dev->mode_config.max_height = 8192;
10137 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10139 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10140 INTEL_INFO(dev)->num_pipes,
10141 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10144 intel_crtc_init(dev, i);
10145 for (j = 0; j < dev_priv->num_plane; j++) {
10146 ret = intel_plane_init(dev, i, j);
10148 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10149 pipe_name(i), sprite_name(i, j), ret);
10153 intel_cpu_pll_init(dev);
10154 intel_shared_dpll_init(dev);
10156 /* Just disable it once at startup */
10157 i915_disable_vga(dev);
10158 intel_setup_outputs(dev);
10160 /* Just in case the BIOS is doing something questionable. */
10161 intel_disable_fbc(dev);
10165 intel_connector_break_all_links(struct intel_connector *connector)
10167 connector->base.dpms = DRM_MODE_DPMS_OFF;
10168 connector->base.encoder = NULL;
10169 connector->encoder->connectors_active = false;
10170 connector->encoder->base.crtc = NULL;
10173 static void intel_enable_pipe_a(struct drm_device *dev)
10175 struct intel_connector *connector;
10176 struct drm_connector *crt = NULL;
10177 struct intel_load_detect_pipe load_detect_temp;
10179 /* We can't just switch on the pipe A, we need to set things up with a
10180 * proper mode and output configuration. As a gross hack, enable pipe A
10181 * by enabling the load detect pipe once. */
10182 list_for_each_entry(connector,
10183 &dev->mode_config.connector_list,
10185 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10186 crt = &connector->base;
10194 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10195 intel_release_load_detect_pipe(crt, &load_detect_temp);
10201 intel_check_plane_mapping(struct intel_crtc *crtc)
10203 struct drm_device *dev = crtc->base.dev;
10204 struct drm_i915_private *dev_priv = dev->dev_private;
10207 if (INTEL_INFO(dev)->num_pipes == 1)
10210 reg = DSPCNTR(!crtc->plane);
10211 val = I915_READ(reg);
10213 if ((val & DISPLAY_PLANE_ENABLE) &&
10214 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10220 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10222 struct drm_device *dev = crtc->base.dev;
10223 struct drm_i915_private *dev_priv = dev->dev_private;
10226 /* Clear any frame start delays used for debugging left by the BIOS */
10227 reg = PIPECONF(crtc->config.cpu_transcoder);
10228 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10230 /* We need to sanitize the plane -> pipe mapping first because this will
10231 * disable the crtc (and hence change the state) if it is wrong. Note
10232 * that gen4+ has a fixed plane -> pipe mapping. */
10233 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10234 struct intel_connector *connector;
10237 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10238 crtc->base.base.id);
10240 /* Pipe has the wrong plane attached and the plane is active.
10241 * Temporarily change the plane mapping and disable everything
10243 plane = crtc->plane;
10244 crtc->plane = !plane;
10245 dev_priv->display.crtc_disable(&crtc->base);
10246 crtc->plane = plane;
10248 /* ... and break all links. */
10249 list_for_each_entry(connector, &dev->mode_config.connector_list,
10251 if (connector->encoder->base.crtc != &crtc->base)
10254 intel_connector_break_all_links(connector);
10257 WARN_ON(crtc->active);
10258 crtc->base.enabled = false;
10261 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10262 crtc->pipe == PIPE_A && !crtc->active) {
10263 /* BIOS forgot to enable pipe A, this mostly happens after
10264 * resume. Force-enable the pipe to fix this, the update_dpms
10265 * call below we restore the pipe to the right state, but leave
10266 * the required bits on. */
10267 intel_enable_pipe_a(dev);
10270 /* Adjust the state of the output pipe according to whether we
10271 * have active connectors/encoders. */
10272 intel_crtc_update_dpms(&crtc->base);
10274 if (crtc->active != crtc->base.enabled) {
10275 struct intel_encoder *encoder;
10277 /* This can happen either due to bugs in the get_hw_state
10278 * functions or because the pipe is force-enabled due to the
10280 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10281 crtc->base.base.id,
10282 crtc->base.enabled ? "enabled" : "disabled",
10283 crtc->active ? "enabled" : "disabled");
10285 crtc->base.enabled = crtc->active;
10287 /* Because we only establish the connector -> encoder ->
10288 * crtc links if something is active, this means the
10289 * crtc is now deactivated. Break the links. connector
10290 * -> encoder links are only establish when things are
10291 * actually up, hence no need to break them. */
10292 WARN_ON(crtc->active);
10294 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10295 WARN_ON(encoder->connectors_active);
10296 encoder->base.crtc = NULL;
10301 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10303 struct intel_connector *connector;
10304 struct drm_device *dev = encoder->base.dev;
10306 /* We need to check both for a crtc link (meaning that the
10307 * encoder is active and trying to read from a pipe) and the
10308 * pipe itself being active. */
10309 bool has_active_crtc = encoder->base.crtc &&
10310 to_intel_crtc(encoder->base.crtc)->active;
10312 if (encoder->connectors_active && !has_active_crtc) {
10313 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10314 encoder->base.base.id,
10315 drm_get_encoder_name(&encoder->base));
10317 /* Connector is active, but has no active pipe. This is
10318 * fallout from our resume register restoring. Disable
10319 * the encoder manually again. */
10320 if (encoder->base.crtc) {
10321 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10322 encoder->base.base.id,
10323 drm_get_encoder_name(&encoder->base));
10324 encoder->disable(encoder);
10327 /* Inconsistent output/port/pipe state happens presumably due to
10328 * a bug in one of the get_hw_state functions. Or someplace else
10329 * in our code, like the register restore mess on resume. Clamp
10330 * things to off as a safer default. */
10331 list_for_each_entry(connector,
10332 &dev->mode_config.connector_list,
10334 if (connector->encoder != encoder)
10337 intel_connector_break_all_links(connector);
10340 /* Enabled encoders without active connectors will be fixed in
10341 * the crtc fixup. */
10344 void i915_redisable_vga(struct drm_device *dev)
10346 struct drm_i915_private *dev_priv = dev->dev_private;
10347 u32 vga_reg = i915_vgacntrl_reg(dev);
10349 /* This function can be called both from intel_modeset_setup_hw_state or
10350 * at a very early point in our resume sequence, where the power well
10351 * structures are not yet restored. Since this function is at a very
10352 * paranoid "someone might have enabled VGA while we were not looking"
10353 * level, just check if the power well is enabled instead of trying to
10354 * follow the "don't touch the power well if we don't need it" policy
10355 * the rest of the driver uses. */
10356 if (HAS_POWER_WELL(dev) &&
10357 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10360 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10361 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10362 i915_disable_vga(dev);
10366 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10368 struct drm_i915_private *dev_priv = dev->dev_private;
10370 struct intel_crtc *crtc;
10371 struct intel_encoder *encoder;
10372 struct intel_connector *connector;
10375 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10377 memset(&crtc->config, 0, sizeof(crtc->config));
10379 crtc->active = dev_priv->display.get_pipe_config(crtc,
10382 crtc->base.enabled = crtc->active;
10384 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10385 crtc->base.base.id,
10386 crtc->active ? "enabled" : "disabled");
10389 /* FIXME: Smash this into the new shared dpll infrastructure. */
10391 intel_ddi_setup_hw_pll_state(dev);
10393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10394 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10396 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10398 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10400 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10403 pll->refcount = pll->active;
10405 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10406 pll->name, pll->refcount, pll->on);
10409 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10413 if (encoder->get_hw_state(encoder, &pipe)) {
10414 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10415 encoder->base.crtc = &crtc->base;
10416 if (encoder->get_config)
10417 encoder->get_config(encoder, &crtc->config);
10419 encoder->base.crtc = NULL;
10422 encoder->connectors_active = false;
10423 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10424 encoder->base.base.id,
10425 drm_get_encoder_name(&encoder->base),
10426 encoder->base.crtc ? "enabled" : "disabled",
10430 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10434 if (dev_priv->display.get_clock)
10435 dev_priv->display.get_clock(crtc,
10439 list_for_each_entry(connector, &dev->mode_config.connector_list,
10441 if (connector->get_hw_state(connector)) {
10442 connector->base.dpms = DRM_MODE_DPMS_ON;
10443 connector->encoder->connectors_active = true;
10444 connector->base.encoder = &connector->encoder->base;
10446 connector->base.dpms = DRM_MODE_DPMS_OFF;
10447 connector->base.encoder = NULL;
10449 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10450 connector->base.base.id,
10451 drm_get_connector_name(&connector->base),
10452 connector->base.encoder ? "enabled" : "disabled");
10456 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10457 * and i915 state tracking structures. */
10458 void intel_modeset_setup_hw_state(struct drm_device *dev,
10459 bool force_restore)
10461 struct drm_i915_private *dev_priv = dev->dev_private;
10463 struct drm_plane *plane;
10464 struct intel_crtc *crtc;
10465 struct intel_encoder *encoder;
10468 intel_modeset_readout_hw_state(dev);
10471 * Now that we have the config, copy it to each CRTC struct
10472 * Note that this could go away if we move to using crtc_config
10473 * checking everywhere.
10475 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10477 if (crtc->active && i915_fastboot) {
10478 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10480 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10481 crtc->base.base.id);
10482 drm_mode_debug_printmodeline(&crtc->base.mode);
10486 /* HW state is read out, now we need to sanitize this mess. */
10487 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10489 intel_sanitize_encoder(encoder);
10492 for_each_pipe(pipe) {
10493 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10494 intel_sanitize_crtc(crtc);
10495 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10498 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10499 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10501 if (!pll->on || pll->active)
10504 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10506 pll->disable(dev_priv, pll);
10510 if (force_restore) {
10512 * We need to use raw interfaces for restoring state to avoid
10513 * checking (bogus) intermediate states.
10515 for_each_pipe(pipe) {
10516 struct drm_crtc *crtc =
10517 dev_priv->pipe_to_crtc_mapping[pipe];
10519 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10522 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10523 intel_plane_restore(plane);
10525 i915_redisable_vga(dev);
10527 intel_modeset_update_staged_output_state(dev);
10530 intel_modeset_check_state(dev);
10532 drm_mode_config_reset(dev);
10535 void intel_modeset_gem_init(struct drm_device *dev)
10537 intel_modeset_init_hw(dev);
10539 intel_setup_overlay(dev);
10541 intel_modeset_setup_hw_state(dev, false);
10544 void intel_modeset_cleanup(struct drm_device *dev)
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 struct drm_crtc *crtc;
10550 * Interrupts and polling as the first thing to avoid creating havoc.
10551 * Too much stuff here (turning of rps, connectors, ...) would
10552 * experience fancy races otherwise.
10554 drm_irq_uninstall(dev);
10555 cancel_work_sync(&dev_priv->hotplug_work);
10557 * Due to the hpd irq storm handling the hotplug work can re-arm the
10558 * poll handlers. Hence disable polling after hpd handling is shut down.
10560 drm_kms_helper_poll_fini(dev);
10562 mutex_lock(&dev->struct_mutex);
10564 intel_unregister_dsm_handler();
10566 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10567 /* Skip inactive CRTCs */
10571 intel_increase_pllclock(crtc);
10574 intel_disable_fbc(dev);
10576 intel_disable_gt_powersave(dev);
10578 ironlake_teardown_rc6(dev);
10580 mutex_unlock(&dev->struct_mutex);
10582 /* flush any delayed tasks or pending work */
10583 flush_scheduled_work();
10585 /* destroy backlight, if any, before the connectors */
10586 intel_panel_destroy_backlight(dev);
10588 drm_mode_config_cleanup(dev);
10590 intel_cleanup_overlay(dev);
10594 * Return which encoder is currently attached for connector.
10596 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10598 return &intel_attached_encoder(connector)->base;
10601 void intel_connector_attach_encoder(struct intel_connector *connector,
10602 struct intel_encoder *encoder)
10604 connector->encoder = encoder;
10605 drm_mode_connector_attach_encoder(&connector->base,
10610 * set vga decode state - true == enable VGA decode
10612 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10614 struct drm_i915_private *dev_priv = dev->dev_private;
10617 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10619 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10621 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10622 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10626 struct intel_display_error_state {
10628 u32 power_well_driver;
10630 int num_transcoders;
10632 struct intel_cursor_error_state {
10637 } cursor[I915_MAX_PIPES];
10639 struct intel_pipe_error_state {
10641 } pipe[I915_MAX_PIPES];
10643 struct intel_plane_error_state {
10651 } plane[I915_MAX_PIPES];
10653 struct intel_transcoder_error_state {
10654 enum transcoder cpu_transcoder;
10667 struct intel_display_error_state *
10668 intel_display_capture_error_state(struct drm_device *dev)
10670 drm_i915_private_t *dev_priv = dev->dev_private;
10671 struct intel_display_error_state *error;
10672 int transcoders[] = {
10680 if (INTEL_INFO(dev)->num_pipes == 0)
10683 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10687 if (HAS_POWER_WELL(dev))
10688 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10691 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10692 error->cursor[i].control = I915_READ(CURCNTR(i));
10693 error->cursor[i].position = I915_READ(CURPOS(i));
10694 error->cursor[i].base = I915_READ(CURBASE(i));
10696 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10697 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10698 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10701 error->plane[i].control = I915_READ(DSPCNTR(i));
10702 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10703 if (INTEL_INFO(dev)->gen <= 3) {
10704 error->plane[i].size = I915_READ(DSPSIZE(i));
10705 error->plane[i].pos = I915_READ(DSPPOS(i));
10707 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10708 error->plane[i].addr = I915_READ(DSPADDR(i));
10709 if (INTEL_INFO(dev)->gen >= 4) {
10710 error->plane[i].surface = I915_READ(DSPSURF(i));
10711 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10714 error->pipe[i].source = I915_READ(PIPESRC(i));
10717 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10718 if (HAS_DDI(dev_priv->dev))
10719 error->num_transcoders++; /* Account for eDP. */
10721 for (i = 0; i < error->num_transcoders; i++) {
10722 enum transcoder cpu_transcoder = transcoders[i];
10724 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10726 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10727 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10728 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10729 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10730 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10731 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10732 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10735 /* In the code above we read the registers without checking if the power
10736 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10737 * prevent the next I915_WRITE from detecting it and printing an error
10739 intel_uncore_clear_errors(dev);
10744 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10747 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10748 struct drm_device *dev,
10749 struct intel_display_error_state *error)
10756 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10757 if (HAS_POWER_WELL(dev))
10758 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10759 error->power_well_driver);
10761 err_printf(m, "Pipe [%d]:\n", i);
10762 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10764 err_printf(m, "Plane [%d]:\n", i);
10765 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10766 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10767 if (INTEL_INFO(dev)->gen <= 3) {
10768 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10769 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10771 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10772 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10773 if (INTEL_INFO(dev)->gen >= 4) {
10774 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10775 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10778 err_printf(m, "Cursor [%d]:\n", i);
10779 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10780 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10781 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10784 for (i = 0; i < error->num_transcoders; i++) {
10785 err_printf(m, " CPU transcoder: %c\n",
10786 transcoder_name(error->transcoder[i].cpu_transcoder));
10787 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10788 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10789 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10790 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10791 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10792 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10793 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);