drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /*
1371          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1372          * CHV x1 PHY (DP/HDMI D)
1373          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1374          */
1375         if (IS_CHERRYVIEW(dev)) {
1376                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1377                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1378         } else {
1379                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1380         }
1381 }
1382
1383 static void intel_reset_dpio(struct drm_device *dev)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386
1387         if (!IS_VALLEYVIEW(dev))
1388                 return;
1389
1390         /*
1391          * Enable the CRI clock source so we can get at the display and the
1392          * reference clock for VGA hotplug / manual detection.
1393          */
1394         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1395                    DPLL_REFA_CLK_ENABLE_VLV |
1396                    DPLL_INTEGRATED_CRI_CLK_VLV);
1397
1398         if (IS_CHERRYVIEW(dev)) {
1399                 enum dpio_phy phy;
1400                 u32 val;
1401
1402                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1403                         /* Poll for phypwrgood signal */
1404                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1405                                                 PHY_POWERGOOD(phy), 1))
1406                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1407
1408                         /*
1409                          * Deassert common lane reset for PHY.
1410                          *
1411                          * This should only be done on init and resume from S3
1412                          * with both PLLs disabled, or we risk losing DPIO and
1413                          * PLL synchronization.
1414                          */
1415                         val = I915_READ(DISPLAY_PHY_CONTROL);
1416                         I915_WRITE(DISPLAY_PHY_CONTROL,
1417                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1418                 }
1419
1420         } else {
1421                 /*
1422                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1423                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1424                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1425                  *   b. The other bits such as sfr settings / modesel may all
1426                  *      be set to 0.
1427                  *
1428                  * This should only be done on init and resume from S3 with
1429                  * both PLLs disabled, or we risk losing DPIO and PLL
1430                  * synchronization.
1431                  */
1432                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1433         }
1434 }
1435
1436 static void vlv_enable_pll(struct intel_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->base.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int reg = DPLL(crtc->pipe);
1441         u32 dpll = crtc->config.dpll_hw_state.dpll;
1442
1443         assert_pipe_disabled(dev_priv, crtc->pipe);
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450                 assert_panel_unlocked(dev_priv, crtc->pipe);
1451
1452         I915_WRITE(reg, dpll);
1453         POSTING_READ(reg);
1454         udelay(150);
1455
1456         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1457                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1458
1459         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1460         POSTING_READ(DPLL_MD(crtc->pipe));
1461
1462         /* We do this three times for luck */
1463         I915_WRITE(reg, dpll);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466         I915_WRITE(reg, dpll);
1467         POSTING_READ(reg);
1468         udelay(150); /* wait for warmup */
1469         I915_WRITE(reg, dpll);
1470         POSTING_READ(reg);
1471         udelay(150); /* wait for warmup */
1472 }
1473
1474 static void i9xx_enable_pll(struct intel_crtc *crtc)
1475 {
1476         struct drm_device *dev = crtc->base.dev;
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478         int reg = DPLL(crtc->pipe);
1479         u32 dpll = crtc->config.dpll_hw_state.dpll;
1480
1481         assert_pipe_disabled(dev_priv, crtc->pipe);
1482
1483         /* No really, not for ILK+ */
1484         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1485
1486         /* PLL is protected by panel, make sure we can write it */
1487         if (IS_MOBILE(dev) && !IS_I830(dev))
1488                 assert_panel_unlocked(dev_priv, crtc->pipe);
1489
1490         I915_WRITE(reg, dpll);
1491
1492         /* Wait for the clocks to stabilize. */
1493         POSTING_READ(reg);
1494         udelay(150);
1495
1496         if (INTEL_INFO(dev)->gen >= 4) {
1497                 I915_WRITE(DPLL_MD(crtc->pipe),
1498                            crtc->config.dpll_hw_state.dpll_md);
1499         } else {
1500                 /* The pixel multiplier can only be updated once the
1501                  * DPLL is enabled and the clocks are stable.
1502                  *
1503                  * So write it again.
1504                  */
1505                 I915_WRITE(reg, dpll);
1506         }
1507
1508         /* We do this three times for luck */
1509         I915_WRITE(reg, dpll);
1510         POSTING_READ(reg);
1511         udelay(150); /* wait for warmup */
1512         I915_WRITE(reg, dpll);
1513         POSTING_READ(reg);
1514         udelay(150); /* wait for warmup */
1515         I915_WRITE(reg, dpll);
1516         POSTING_READ(reg);
1517         udelay(150); /* wait for warmup */
1518 }
1519
1520 /**
1521  * i9xx_disable_pll - disable a PLL
1522  * @dev_priv: i915 private structure
1523  * @pipe: pipe PLL to disable
1524  *
1525  * Disable the PLL for @pipe, making sure the pipe is off first.
1526  *
1527  * Note!  This is for pre-ILK only.
1528  */
1529 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1530 {
1531         /* Don't disable pipe A or pipe A PLLs if needed */
1532         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1533                 return;
1534
1535         /* Make sure the pipe isn't still relying on us */
1536         assert_pipe_disabled(dev_priv, pipe);
1537
1538         I915_WRITE(DPLL(pipe), 0);
1539         POSTING_READ(DPLL(pipe));
1540 }
1541
1542 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1543 {
1544         u32 val = 0;
1545
1546         /* Make sure the pipe isn't still relying on us */
1547         assert_pipe_disabled(dev_priv, pipe);
1548
1549         /*
1550          * Leave integrated clock source and reference clock enabled for pipe B.
1551          * The latter is needed for VGA hotplug / manual detection.
1552          */
1553         if (pipe == PIPE_B)
1554                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1555         I915_WRITE(DPLL(pipe), val);
1556         POSTING_READ(DPLL(pipe));
1557
1558 }
1559
1560 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1561 {
1562         int dpll = DPLL(pipe);
1563         u32 val;
1564
1565         /* Set PLL en = 0 */
1566         val = I915_READ(dpll);
1567         val &= ~DPLL_VCO_ENABLE;
1568         I915_WRITE(dpll, val);
1569
1570 }
1571
1572 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1573                 struct intel_digital_port *dport)
1574 {
1575         u32 port_mask;
1576         int dpll_reg;
1577
1578         switch (dport->port) {
1579         case PORT_B:
1580                 port_mask = DPLL_PORTB_READY_MASK;
1581                 dpll_reg = DPLL(0);
1582                 break;
1583         case PORT_C:
1584                 port_mask = DPLL_PORTC_READY_MASK;
1585                 dpll_reg = DPLL(0);
1586                 break;
1587         case PORT_D:
1588                 port_mask = DPLL_PORTD_READY_MASK;
1589                 dpll_reg = DPIO_PHY_STATUS;
1590                 break;
1591         default:
1592                 BUG();
1593         }
1594
1595         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1596                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1597                      port_name(dport->port), I915_READ(dpll_reg));
1598 }
1599
1600 /**
1601  * ironlake_enable_shared_dpll - enable PCH PLL
1602  * @dev_priv: i915 private structure
1603  * @pipe: pipe PLL to enable
1604  *
1605  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1606  * drives the transcoder clock.
1607  */
1608 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1609 {
1610         struct drm_device *dev = crtc->base.dev;
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1613
1614         /* PCH PLLs only available on ILK, SNB and IVB */
1615         BUG_ON(INTEL_INFO(dev)->gen < 5);
1616         if (WARN_ON(pll == NULL))
1617                 return;
1618
1619         if (WARN_ON(pll->refcount == 0))
1620                 return;
1621
1622         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1623                       pll->name, pll->active, pll->on,
1624                       crtc->base.base.id);
1625
1626         if (pll->active++) {
1627                 WARN_ON(!pll->on);
1628                 assert_shared_dpll_enabled(dev_priv, pll);
1629                 return;
1630         }
1631         WARN_ON(pll->on);
1632
1633         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1634         pll->enable(dev_priv, pll);
1635         pll->on = true;
1636 }
1637
1638 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1639 {
1640         struct drm_device *dev = crtc->base.dev;
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1643
1644         /* PCH only available on ILK+ */
1645         BUG_ON(INTEL_INFO(dev)->gen < 5);
1646         if (WARN_ON(pll == NULL))
1647                return;
1648
1649         if (WARN_ON(pll->refcount == 0))
1650                 return;
1651
1652         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1653                       pll->name, pll->active, pll->on,
1654                       crtc->base.base.id);
1655
1656         if (WARN_ON(pll->active == 0)) {
1657                 assert_shared_dpll_disabled(dev_priv, pll);
1658                 return;
1659         }
1660
1661         assert_shared_dpll_enabled(dev_priv, pll);
1662         WARN_ON(!pll->on);
1663         if (--pll->active)
1664                 return;
1665
1666         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1667         pll->disable(dev_priv, pll);
1668         pll->on = false;
1669 }
1670
1671 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1672                                            enum pipe pipe)
1673 {
1674         struct drm_device *dev = dev_priv->dev;
1675         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1677         uint32_t reg, val, pipeconf_val;
1678
1679         /* PCH only available on ILK+ */
1680         BUG_ON(INTEL_INFO(dev)->gen < 5);
1681
1682         /* Make sure PCH DPLL is enabled */
1683         assert_shared_dpll_enabled(dev_priv,
1684                                    intel_crtc_to_shared_dpll(intel_crtc));
1685
1686         /* FDI must be feeding us bits for PCH ports */
1687         assert_fdi_tx_enabled(dev_priv, pipe);
1688         assert_fdi_rx_enabled(dev_priv, pipe);
1689
1690         if (HAS_PCH_CPT(dev)) {
1691                 /* Workaround: Set the timing override bit before enabling the
1692                  * pch transcoder. */
1693                 reg = TRANS_CHICKEN2(pipe);
1694                 val = I915_READ(reg);
1695                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1696                 I915_WRITE(reg, val);
1697         }
1698
1699         reg = PCH_TRANSCONF(pipe);
1700         val = I915_READ(reg);
1701         pipeconf_val = I915_READ(PIPECONF(pipe));
1702
1703         if (HAS_PCH_IBX(dev_priv->dev)) {
1704                 /*
1705                  * make the BPC in transcoder be consistent with
1706                  * that in pipeconf reg.
1707                  */
1708                 val &= ~PIPECONF_BPC_MASK;
1709                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1710         }
1711
1712         val &= ~TRANS_INTERLACE_MASK;
1713         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1714                 if (HAS_PCH_IBX(dev_priv->dev) &&
1715                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1716                         val |= TRANS_LEGACY_INTERLACED_ILK;
1717                 else
1718                         val |= TRANS_INTERLACED;
1719         else
1720                 val |= TRANS_PROGRESSIVE;
1721
1722         I915_WRITE(reg, val | TRANS_ENABLE);
1723         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1724                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1725 }
1726
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728                                       enum transcoder cpu_transcoder)
1729 {
1730         u32 val, pipeconf_val;
1731
1732         /* PCH only available on ILK+ */
1733         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1734
1735         /* FDI must be feeding us bits for PCH ports */
1736         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1737         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1738
1739         /* Workaround: set timing override bit. */
1740         val = I915_READ(_TRANSA_CHICKEN2);
1741         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1742         I915_WRITE(_TRANSA_CHICKEN2, val);
1743
1744         val = TRANS_ENABLE;
1745         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1746
1747         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748             PIPECONF_INTERLACED_ILK)
1749                 val |= TRANS_INTERLACED;
1750         else
1751                 val |= TRANS_PROGRESSIVE;
1752
1753         I915_WRITE(LPT_TRANSCONF, val);
1754         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1755                 DRM_ERROR("Failed to enable PCH transcoder\n");
1756 }
1757
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759                                             enum pipe pipe)
1760 {
1761         struct drm_device *dev = dev_priv->dev;
1762         uint32_t reg, val;
1763
1764         /* FDI relies on the transcoder */
1765         assert_fdi_tx_disabled(dev_priv, pipe);
1766         assert_fdi_rx_disabled(dev_priv, pipe);
1767
1768         /* Ports must be off as well */
1769         assert_pch_ports_disabled(dev_priv, pipe);
1770
1771         reg = PCH_TRANSCONF(pipe);
1772         val = I915_READ(reg);
1773         val &= ~TRANS_ENABLE;
1774         I915_WRITE(reg, val);
1775         /* wait for PCH transcoder off, transcoder state */
1776         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1777                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1778
1779         if (!HAS_PCH_IBX(dev)) {
1780                 /* Workaround: Clear the timing override chicken bit again. */
1781                 reg = TRANS_CHICKEN2(pipe);
1782                 val = I915_READ(reg);
1783                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784                 I915_WRITE(reg, val);
1785         }
1786 }
1787
1788 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1789 {
1790         u32 val;
1791
1792         val = I915_READ(LPT_TRANSCONF);
1793         val &= ~TRANS_ENABLE;
1794         I915_WRITE(LPT_TRANSCONF, val);
1795         /* wait for PCH transcoder off, transcoder state */
1796         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1797                 DRM_ERROR("Failed to disable PCH transcoder\n");
1798
1799         /* Workaround: clear timing override bit. */
1800         val = I915_READ(_TRANSA_CHICKEN2);
1801         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1802         I915_WRITE(_TRANSA_CHICKEN2, val);
1803 }
1804
1805 /**
1806  * intel_enable_pipe - enable a pipe, asserting requirements
1807  * @crtc: crtc responsible for the pipe
1808  *
1809  * Enable @crtc's pipe, making sure that various hardware specific requirements
1810  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1811  */
1812 static void intel_enable_pipe(struct intel_crtc *crtc)
1813 {
1814         struct drm_device *dev = crtc->base.dev;
1815         struct drm_i915_private *dev_priv = dev->dev_private;
1816         enum pipe pipe = crtc->pipe;
1817         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818                                                                       pipe);
1819         enum pipe pch_transcoder;
1820         int reg;
1821         u32 val;
1822
1823         assert_planes_disabled(dev_priv, pipe);
1824         assert_cursor_disabled(dev_priv, pipe);
1825         assert_sprites_disabled(dev_priv, pipe);
1826
1827         if (HAS_PCH_LPT(dev_priv->dev))
1828                 pch_transcoder = TRANSCODER_A;
1829         else
1830                 pch_transcoder = pipe;
1831
1832         /*
1833          * A pipe without a PLL won't actually be able to drive bits from
1834          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1835          * need the check.
1836          */
1837         if (!HAS_PCH_SPLIT(dev_priv->dev))
1838                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1839                         assert_dsi_pll_enabled(dev_priv);
1840                 else
1841                         assert_pll_enabled(dev_priv, pipe);
1842         else {
1843                 if (crtc->config.has_pch_encoder) {
1844                         /* if driving the PCH, we need FDI enabled */
1845                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1846                         assert_fdi_tx_pll_enabled(dev_priv,
1847                                                   (enum pipe) cpu_transcoder);
1848                 }
1849                 /* FIXME: assert CPU port conditions for SNB+ */
1850         }
1851
1852         reg = PIPECONF(cpu_transcoder);
1853         val = I915_READ(reg);
1854         if (val & PIPECONF_ENABLE) {
1855                 WARN_ON(!(pipe == PIPE_A &&
1856                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1857                 return;
1858         }
1859
1860         I915_WRITE(reg, val | PIPECONF_ENABLE);
1861         POSTING_READ(reg);
1862 }
1863
1864 /**
1865  * intel_disable_pipe - disable a pipe, asserting requirements
1866  * @dev_priv: i915 private structure
1867  * @pipe: pipe to disable
1868  *
1869  * Disable @pipe, making sure that various hardware specific requirements
1870  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1871  *
1872  * @pipe should be %PIPE_A or %PIPE_B.
1873  *
1874  * Will wait until the pipe has shut down before returning.
1875  */
1876 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1877                                enum pipe pipe)
1878 {
1879         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1880                                                                       pipe);
1881         int reg;
1882         u32 val;
1883
1884         /*
1885          * Make sure planes won't keep trying to pump pixels to us,
1886          * or we might hang the display.
1887          */
1888         assert_planes_disabled(dev_priv, pipe);
1889         assert_cursor_disabled(dev_priv, pipe);
1890         assert_sprites_disabled(dev_priv, pipe);
1891
1892         /* Don't disable pipe A or pipe A PLLs if needed */
1893         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1894                 return;
1895
1896         reg = PIPECONF(cpu_transcoder);
1897         val = I915_READ(reg);
1898         if ((val & PIPECONF_ENABLE) == 0)
1899                 return;
1900
1901         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1902         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1903 }
1904
1905 /*
1906  * Plane regs are double buffered, going from enabled->disabled needs a
1907  * trigger in order to latch.  The display address reg provides this.
1908  */
1909 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1910                                enum plane plane)
1911 {
1912         struct drm_device *dev = dev_priv->dev;
1913         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1914
1915         I915_WRITE(reg, I915_READ(reg));
1916         POSTING_READ(reg);
1917 }
1918
1919 /**
1920  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1921  * @dev_priv: i915 private structure
1922  * @plane: plane to enable
1923  * @pipe: pipe being fed
1924  *
1925  * Enable @plane on @pipe, making sure that @pipe is running first.
1926  */
1927 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1928                                           enum plane plane, enum pipe pipe)
1929 {
1930         struct intel_crtc *intel_crtc =
1931                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1932         int reg;
1933         u32 val;
1934
1935         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1936         assert_pipe_enabled(dev_priv, pipe);
1937
1938         if (intel_crtc->primary_enabled)
1939                 return;
1940
1941         intel_crtc->primary_enabled = true;
1942
1943         reg = DSPCNTR(plane);
1944         val = I915_READ(reg);
1945         WARN_ON(val & DISPLAY_PLANE_ENABLE);
1946
1947         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1948         intel_flush_primary_plane(dev_priv, plane);
1949         intel_wait_for_vblank(dev_priv->dev, pipe);
1950 }
1951
1952 /**
1953  * intel_disable_primary_hw_plane - disable the primary hardware plane
1954  * @dev_priv: i915 private structure
1955  * @plane: plane to disable
1956  * @pipe: pipe consuming the data
1957  *
1958  * Disable @plane; should be an independent operation.
1959  */
1960 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1961                                            enum plane plane, enum pipe pipe)
1962 {
1963         struct intel_crtc *intel_crtc =
1964                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1965         int reg;
1966         u32 val;
1967
1968         if (!intel_crtc->primary_enabled)
1969                 return;
1970
1971         intel_crtc->primary_enabled = false;
1972
1973         reg = DSPCNTR(plane);
1974         val = I915_READ(reg);
1975         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
1976
1977         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1978         intel_flush_primary_plane(dev_priv, plane);
1979         intel_wait_for_vblank(dev_priv->dev, pipe);
1980 }
1981
1982 static bool need_vtd_wa(struct drm_device *dev)
1983 {
1984 #ifdef CONFIG_INTEL_IOMMU
1985         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1986                 return true;
1987 #endif
1988         return false;
1989 }
1990
1991 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1992 {
1993         int tile_height;
1994
1995         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1996         return ALIGN(height, tile_height);
1997 }
1998
1999 int
2000 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2001                            struct drm_i915_gem_object *obj,
2002                            struct intel_ring_buffer *pipelined)
2003 {
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         u32 alignment;
2006         int ret;
2007
2008         switch (obj->tiling_mode) {
2009         case I915_TILING_NONE:
2010                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2011                         alignment = 128 * 1024;
2012                 else if (INTEL_INFO(dev)->gen >= 4)
2013                         alignment = 4 * 1024;
2014                 else
2015                         alignment = 64 * 1024;
2016                 break;
2017         case I915_TILING_X:
2018                 /* pin() will align the object as required by fence */
2019                 alignment = 0;
2020                 break;
2021         case I915_TILING_Y:
2022                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2023                 return -EINVAL;
2024         default:
2025                 BUG();
2026         }
2027
2028         /* Note that the w/a also requires 64 PTE of padding following the
2029          * bo. We currently fill all unused PTE with the shadow page and so
2030          * we should always have valid PTE following the scanout preventing
2031          * the VT-d warning.
2032          */
2033         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2034                 alignment = 256 * 1024;
2035
2036         dev_priv->mm.interruptible = false;
2037         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2038         if (ret)
2039                 goto err_interruptible;
2040
2041         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2042          * fence, whereas 965+ only requires a fence if using
2043          * framebuffer compression.  For simplicity, we always install
2044          * a fence as the cost is not that onerous.
2045          */
2046         ret = i915_gem_object_get_fence(obj);
2047         if (ret)
2048                 goto err_unpin;
2049
2050         i915_gem_object_pin_fence(obj);
2051
2052         dev_priv->mm.interruptible = true;
2053         return 0;
2054
2055 err_unpin:
2056         i915_gem_object_unpin_from_display_plane(obj);
2057 err_interruptible:
2058         dev_priv->mm.interruptible = true;
2059         return ret;
2060 }
2061
2062 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2063 {
2064         i915_gem_object_unpin_fence(obj);
2065         i915_gem_object_unpin_from_display_plane(obj);
2066 }
2067
2068 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2069  * is assumed to be a power-of-two. */
2070 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2071                                              unsigned int tiling_mode,
2072                                              unsigned int cpp,
2073                                              unsigned int pitch)
2074 {
2075         if (tiling_mode != I915_TILING_NONE) {
2076                 unsigned int tile_rows, tiles;
2077
2078                 tile_rows = *y / 8;
2079                 *y %= 8;
2080
2081                 tiles = *x / (512/cpp);
2082                 *x %= 512/cpp;
2083
2084                 return tile_rows * pitch * 8 + tiles * 4096;
2085         } else {
2086                 unsigned int offset;
2087
2088                 offset = *y * pitch + *x * cpp;
2089                 *y = 0;
2090                 *x = (offset & 4095) / cpp;
2091                 return offset & -4096;
2092         }
2093 }
2094
2095 int intel_format_to_fourcc(int format)
2096 {
2097         switch (format) {
2098         case DISPPLANE_8BPP:
2099                 return DRM_FORMAT_C8;
2100         case DISPPLANE_BGRX555:
2101                 return DRM_FORMAT_XRGB1555;
2102         case DISPPLANE_BGRX565:
2103                 return DRM_FORMAT_RGB565;
2104         default:
2105         case DISPPLANE_BGRX888:
2106                 return DRM_FORMAT_XRGB8888;
2107         case DISPPLANE_RGBX888:
2108                 return DRM_FORMAT_XBGR8888;
2109         case DISPPLANE_BGRX101010:
2110                 return DRM_FORMAT_XRGB2101010;
2111         case DISPPLANE_RGBX101010:
2112                 return DRM_FORMAT_XBGR2101010;
2113         }
2114 }
2115
2116 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2117                                   struct intel_plane_config *plane_config)
2118 {
2119         struct drm_device *dev = crtc->base.dev;
2120         struct drm_i915_gem_object *obj = NULL;
2121         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2122         u32 base = plane_config->base;
2123
2124         if (plane_config->size == 0)
2125                 return false;
2126
2127         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2128                                                              plane_config->size);
2129         if (!obj)
2130                 return false;
2131
2132         if (plane_config->tiled) {
2133                 obj->tiling_mode = I915_TILING_X;
2134                 obj->stride = crtc->base.primary->fb->pitches[0];
2135         }
2136
2137         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2138         mode_cmd.width = crtc->base.primary->fb->width;
2139         mode_cmd.height = crtc->base.primary->fb->height;
2140         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2141
2142         mutex_lock(&dev->struct_mutex);
2143
2144         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2145                                    &mode_cmd, obj)) {
2146                 DRM_DEBUG_KMS("intel fb init failed\n");
2147                 goto out_unref_obj;
2148         }
2149
2150         mutex_unlock(&dev->struct_mutex);
2151
2152         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2153         return true;
2154
2155 out_unref_obj:
2156         drm_gem_object_unreference(&obj->base);
2157         mutex_unlock(&dev->struct_mutex);
2158         return false;
2159 }
2160
2161 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2162                                  struct intel_plane_config *plane_config)
2163 {
2164         struct drm_device *dev = intel_crtc->base.dev;
2165         struct drm_crtc *c;
2166         struct intel_crtc *i;
2167         struct intel_framebuffer *fb;
2168
2169         if (!intel_crtc->base.primary->fb)
2170                 return;
2171
2172         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2173                 return;
2174
2175         kfree(intel_crtc->base.primary->fb);
2176         intel_crtc->base.primary->fb = NULL;
2177
2178         /*
2179          * Failed to alloc the obj, check to see if we should share
2180          * an fb with another CRTC instead
2181          */
2182         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2183                 i = to_intel_crtc(c);
2184
2185                 if (c == &intel_crtc->base)
2186                         continue;
2187
2188                 if (!i->active || !c->primary->fb)
2189                         continue;
2190
2191                 fb = to_intel_framebuffer(c->primary->fb);
2192                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2193                         drm_framebuffer_reference(c->primary->fb);
2194                         intel_crtc->base.primary->fb = c->primary->fb;
2195                         break;
2196                 }
2197         }
2198 }
2199
2200 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2201                                      struct drm_framebuffer *fb,
2202                                      int x, int y)
2203 {
2204         struct drm_device *dev = crtc->dev;
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207         struct intel_framebuffer *intel_fb;
2208         struct drm_i915_gem_object *obj;
2209         int plane = intel_crtc->plane;
2210         unsigned long linear_offset;
2211         u32 dspcntr;
2212         u32 reg;
2213
2214         intel_fb = to_intel_framebuffer(fb);
2215         obj = intel_fb->obj;
2216
2217         reg = DSPCNTR(plane);
2218         dspcntr = I915_READ(reg);
2219         /* Mask out pixel format bits in case we change it */
2220         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2221         switch (fb->pixel_format) {
2222         case DRM_FORMAT_C8:
2223                 dspcntr |= DISPPLANE_8BPP;
2224                 break;
2225         case DRM_FORMAT_XRGB1555:
2226         case DRM_FORMAT_ARGB1555:
2227                 dspcntr |= DISPPLANE_BGRX555;
2228                 break;
2229         case DRM_FORMAT_RGB565:
2230                 dspcntr |= DISPPLANE_BGRX565;
2231                 break;
2232         case DRM_FORMAT_XRGB8888:
2233         case DRM_FORMAT_ARGB8888:
2234                 dspcntr |= DISPPLANE_BGRX888;
2235                 break;
2236         case DRM_FORMAT_XBGR8888:
2237         case DRM_FORMAT_ABGR8888:
2238                 dspcntr |= DISPPLANE_RGBX888;
2239                 break;
2240         case DRM_FORMAT_XRGB2101010:
2241         case DRM_FORMAT_ARGB2101010:
2242                 dspcntr |= DISPPLANE_BGRX101010;
2243                 break;
2244         case DRM_FORMAT_XBGR2101010:
2245         case DRM_FORMAT_ABGR2101010:
2246                 dspcntr |= DISPPLANE_RGBX101010;
2247                 break;
2248         default:
2249                 BUG();
2250         }
2251
2252         if (INTEL_INFO(dev)->gen >= 4) {
2253                 if (obj->tiling_mode != I915_TILING_NONE)
2254                         dspcntr |= DISPPLANE_TILED;
2255                 else
2256                         dspcntr &= ~DISPPLANE_TILED;
2257         }
2258
2259         if (IS_G4X(dev))
2260                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2261
2262         I915_WRITE(reg, dspcntr);
2263
2264         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2265
2266         if (INTEL_INFO(dev)->gen >= 4) {
2267                 intel_crtc->dspaddr_offset =
2268                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2269                                                        fb->bits_per_pixel / 8,
2270                                                        fb->pitches[0]);
2271                 linear_offset -= intel_crtc->dspaddr_offset;
2272         } else {
2273                 intel_crtc->dspaddr_offset = linear_offset;
2274         }
2275
2276         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2277                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2278                       fb->pitches[0]);
2279         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2280         if (INTEL_INFO(dev)->gen >= 4) {
2281                 I915_WRITE(DSPSURF(plane),
2282                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2283                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2284                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2285         } else
2286                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2287         POSTING_READ(reg);
2288
2289         return 0;
2290 }
2291
2292 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2293                                          struct drm_framebuffer *fb,
2294                                          int x, int y)
2295 {
2296         struct drm_device *dev = crtc->dev;
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2299         struct intel_framebuffer *intel_fb;
2300         struct drm_i915_gem_object *obj;
2301         int plane = intel_crtc->plane;
2302         unsigned long linear_offset;
2303         u32 dspcntr;
2304         u32 reg;
2305
2306         intel_fb = to_intel_framebuffer(fb);
2307         obj = intel_fb->obj;
2308
2309         reg = DSPCNTR(plane);
2310         dspcntr = I915_READ(reg);
2311         /* Mask out pixel format bits in case we change it */
2312         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2313         switch (fb->pixel_format) {
2314         case DRM_FORMAT_C8:
2315                 dspcntr |= DISPPLANE_8BPP;
2316                 break;
2317         case DRM_FORMAT_RGB565:
2318                 dspcntr |= DISPPLANE_BGRX565;
2319                 break;
2320         case DRM_FORMAT_XRGB8888:
2321         case DRM_FORMAT_ARGB8888:
2322                 dspcntr |= DISPPLANE_BGRX888;
2323                 break;
2324         case DRM_FORMAT_XBGR8888:
2325         case DRM_FORMAT_ABGR8888:
2326                 dspcntr |= DISPPLANE_RGBX888;
2327                 break;
2328         case DRM_FORMAT_XRGB2101010:
2329         case DRM_FORMAT_ARGB2101010:
2330                 dspcntr |= DISPPLANE_BGRX101010;
2331                 break;
2332         case DRM_FORMAT_XBGR2101010:
2333         case DRM_FORMAT_ABGR2101010:
2334                 dspcntr |= DISPPLANE_RGBX101010;
2335                 break;
2336         default:
2337                 BUG();
2338         }
2339
2340         if (obj->tiling_mode != I915_TILING_NONE)
2341                 dspcntr |= DISPPLANE_TILED;
2342         else
2343                 dspcntr &= ~DISPPLANE_TILED;
2344
2345         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2346                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2347         else
2348                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2349
2350         I915_WRITE(reg, dspcntr);
2351
2352         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2353         intel_crtc->dspaddr_offset =
2354                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2355                                                fb->bits_per_pixel / 8,
2356                                                fb->pitches[0]);
2357         linear_offset -= intel_crtc->dspaddr_offset;
2358
2359         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2360                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2361                       fb->pitches[0]);
2362         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2363         I915_WRITE(DSPSURF(plane),
2364                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2365         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2366                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2367         } else {
2368                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2369                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2370         }
2371         POSTING_READ(reg);
2372
2373         return 0;
2374 }
2375
2376 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2377 static int
2378 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2379                            int x, int y, enum mode_set_atomic state)
2380 {
2381         struct drm_device *dev = crtc->dev;
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383
2384         if (dev_priv->display.disable_fbc)
2385                 dev_priv->display.disable_fbc(dev);
2386         intel_increase_pllclock(crtc);
2387
2388         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2389 }
2390
2391 void intel_display_handle_reset(struct drm_device *dev)
2392 {
2393         struct drm_i915_private *dev_priv = dev->dev_private;
2394         struct drm_crtc *crtc;
2395
2396         /*
2397          * Flips in the rings have been nuked by the reset,
2398          * so complete all pending flips so that user space
2399          * will get its events and not get stuck.
2400          *
2401          * Also update the base address of all primary
2402          * planes to the the last fb to make sure we're
2403          * showing the correct fb after a reset.
2404          *
2405          * Need to make two loops over the crtcs so that we
2406          * don't try to grab a crtc mutex before the
2407          * pending_flip_queue really got woken up.
2408          */
2409
2410         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2411                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412                 enum plane plane = intel_crtc->plane;
2413
2414                 intel_prepare_page_flip(dev, plane);
2415                 intel_finish_page_flip_plane(dev, plane);
2416         }
2417
2418         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2419                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420
2421                 mutex_lock(&crtc->mutex);
2422                 /*
2423                  * FIXME: Once we have proper support for primary planes (and
2424                  * disabling them without disabling the entire crtc) allow again
2425                  * a NULL crtc->primary->fb.
2426                  */
2427                 if (intel_crtc->active && crtc->primary->fb)
2428                         dev_priv->display.update_primary_plane(crtc,
2429                                                                crtc->primary->fb,
2430                                                                crtc->x,
2431                                                                crtc->y);
2432                 mutex_unlock(&crtc->mutex);
2433         }
2434 }
2435
2436 static int
2437 intel_finish_fb(struct drm_framebuffer *old_fb)
2438 {
2439         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2440         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2441         bool was_interruptible = dev_priv->mm.interruptible;
2442         int ret;
2443
2444         /* Big Hammer, we also need to ensure that any pending
2445          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2446          * current scanout is retired before unpinning the old
2447          * framebuffer.
2448          *
2449          * This should only fail upon a hung GPU, in which case we
2450          * can safely continue.
2451          */
2452         dev_priv->mm.interruptible = false;
2453         ret = i915_gem_object_finish_gpu(obj);
2454         dev_priv->mm.interruptible = was_interruptible;
2455
2456         return ret;
2457 }
2458
2459 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         unsigned long flags;
2465         bool pending;
2466
2467         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2468             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2469                 return false;
2470
2471         spin_lock_irqsave(&dev->event_lock, flags);
2472         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2473         spin_unlock_irqrestore(&dev->event_lock, flags);
2474
2475         return pending;
2476 }
2477
2478 static int
2479 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2480                     struct drm_framebuffer *fb)
2481 {
2482         struct drm_device *dev = crtc->dev;
2483         struct drm_i915_private *dev_priv = dev->dev_private;
2484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485         struct drm_framebuffer *old_fb;
2486         int ret;
2487
2488         if (intel_crtc_has_pending_flip(crtc)) {
2489                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2490                 return -EBUSY;
2491         }
2492
2493         /* no fb bound */
2494         if (!fb) {
2495                 DRM_ERROR("No FB bound\n");
2496                 return 0;
2497         }
2498
2499         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2500                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2501                           plane_name(intel_crtc->plane),
2502                           INTEL_INFO(dev)->num_pipes);
2503                 return -EINVAL;
2504         }
2505
2506         mutex_lock(&dev->struct_mutex);
2507         ret = intel_pin_and_fence_fb_obj(dev,
2508                                          to_intel_framebuffer(fb)->obj,
2509                                          NULL);
2510         mutex_unlock(&dev->struct_mutex);
2511         if (ret != 0) {
2512                 DRM_ERROR("pin & fence failed\n");
2513                 return ret;
2514         }
2515
2516         /*
2517          * Update pipe size and adjust fitter if needed: the reason for this is
2518          * that in compute_mode_changes we check the native mode (not the pfit
2519          * mode) to see if we can flip rather than do a full mode set. In the
2520          * fastboot case, we'll flip, but if we don't update the pipesrc and
2521          * pfit state, we'll end up with a big fb scanned out into the wrong
2522          * sized surface.
2523          *
2524          * To fix this properly, we need to hoist the checks up into
2525          * compute_mode_changes (or above), check the actual pfit state and
2526          * whether the platform allows pfit disable with pipe active, and only
2527          * then update the pipesrc and pfit state, even on the flip path.
2528          */
2529         if (i915.fastboot) {
2530                 const struct drm_display_mode *adjusted_mode =
2531                         &intel_crtc->config.adjusted_mode;
2532
2533                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2534                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2535                            (adjusted_mode->crtc_vdisplay - 1));
2536                 if (!intel_crtc->config.pch_pfit.enabled &&
2537                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2538                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2539                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2540                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2541                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2542                 }
2543                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2544                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2545         }
2546
2547         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2548         if (ret) {
2549                 mutex_lock(&dev->struct_mutex);
2550                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2551                 mutex_unlock(&dev->struct_mutex);
2552                 DRM_ERROR("failed to update base address\n");
2553                 return ret;
2554         }
2555
2556         old_fb = crtc->primary->fb;
2557         crtc->primary->fb = fb;
2558         crtc->x = x;
2559         crtc->y = y;
2560
2561         if (old_fb) {
2562                 if (intel_crtc->active && old_fb != fb)
2563                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2564                 mutex_lock(&dev->struct_mutex);
2565                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2566                 mutex_unlock(&dev->struct_mutex);
2567         }
2568
2569         mutex_lock(&dev->struct_mutex);
2570         intel_update_fbc(dev);
2571         intel_edp_psr_update(dev);
2572         mutex_unlock(&dev->struct_mutex);
2573
2574         return 0;
2575 }
2576
2577 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2578 {
2579         struct drm_device *dev = crtc->dev;
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2582         int pipe = intel_crtc->pipe;
2583         u32 reg, temp;
2584
2585         /* enable normal train */
2586         reg = FDI_TX_CTL(pipe);
2587         temp = I915_READ(reg);
2588         if (IS_IVYBRIDGE(dev)) {
2589                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2590                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2591         } else {
2592                 temp &= ~FDI_LINK_TRAIN_NONE;
2593                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2594         }
2595         I915_WRITE(reg, temp);
2596
2597         reg = FDI_RX_CTL(pipe);
2598         temp = I915_READ(reg);
2599         if (HAS_PCH_CPT(dev)) {
2600                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2602         } else {
2603                 temp &= ~FDI_LINK_TRAIN_NONE;
2604                 temp |= FDI_LINK_TRAIN_NONE;
2605         }
2606         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2607
2608         /* wait one idle pattern time */
2609         POSTING_READ(reg);
2610         udelay(1000);
2611
2612         /* IVB wants error correction enabled */
2613         if (IS_IVYBRIDGE(dev))
2614                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2615                            FDI_FE_ERRC_ENABLE);
2616 }
2617
2618 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2619 {
2620         return crtc->base.enabled && crtc->active &&
2621                 crtc->config.has_pch_encoder;
2622 }
2623
2624 static void ivb_modeset_global_resources(struct drm_device *dev)
2625 {
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627         struct intel_crtc *pipe_B_crtc =
2628                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2629         struct intel_crtc *pipe_C_crtc =
2630                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2631         uint32_t temp;
2632
2633         /*
2634          * When everything is off disable fdi C so that we could enable fdi B
2635          * with all lanes. Note that we don't care about enabled pipes without
2636          * an enabled pch encoder.
2637          */
2638         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2639             !pipe_has_enabled_pch(pipe_C_crtc)) {
2640                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2641                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2642
2643                 temp = I915_READ(SOUTH_CHICKEN1);
2644                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2645                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2646                 I915_WRITE(SOUTH_CHICKEN1, temp);
2647         }
2648 }
2649
2650 /* The FDI link training functions for ILK/Ibexpeak. */
2651 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2652 {
2653         struct drm_device *dev = crtc->dev;
2654         struct drm_i915_private *dev_priv = dev->dev_private;
2655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2656         int pipe = intel_crtc->pipe;
2657         u32 reg, temp, tries;
2658
2659         /* FDI needs bits from pipe first */
2660         assert_pipe_enabled(dev_priv, pipe);
2661
2662         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2663            for train result */
2664         reg = FDI_RX_IMR(pipe);
2665         temp = I915_READ(reg);
2666         temp &= ~FDI_RX_SYMBOL_LOCK;
2667         temp &= ~FDI_RX_BIT_LOCK;
2668         I915_WRITE(reg, temp);
2669         I915_READ(reg);
2670         udelay(150);
2671
2672         /* enable CPU FDI TX and PCH FDI RX */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2676         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2677         temp &= ~FDI_LINK_TRAIN_NONE;
2678         temp |= FDI_LINK_TRAIN_PATTERN_1;
2679         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2680
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         temp &= ~FDI_LINK_TRAIN_NONE;
2684         temp |= FDI_LINK_TRAIN_PATTERN_1;
2685         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2686
2687         POSTING_READ(reg);
2688         udelay(150);
2689
2690         /* Ironlake workaround, enable clock pointer after FDI enable*/
2691         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2692         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2693                    FDI_RX_PHASE_SYNC_POINTER_EN);
2694
2695         reg = FDI_RX_IIR(pipe);
2696         for (tries = 0; tries < 5; tries++) {
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if ((temp & FDI_RX_BIT_LOCK)) {
2701                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2702                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703                         break;
2704                 }
2705         }
2706         if (tries == 5)
2707                 DRM_ERROR("FDI train 1 fail!\n");
2708
2709         /* Train 2 */
2710         reg = FDI_TX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         temp &= ~FDI_LINK_TRAIN_NONE;
2713         temp |= FDI_LINK_TRAIN_PATTERN_2;
2714         I915_WRITE(reg, temp);
2715
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE;
2719         temp |= FDI_LINK_TRAIN_PATTERN_2;
2720         I915_WRITE(reg, temp);
2721
2722         POSTING_READ(reg);
2723         udelay(150);
2724
2725         reg = FDI_RX_IIR(pipe);
2726         for (tries = 0; tries < 5; tries++) {
2727                 temp = I915_READ(reg);
2728                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2729
2730                 if (temp & FDI_RX_SYMBOL_LOCK) {
2731                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2732                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2733                         break;
2734                 }
2735         }
2736         if (tries == 5)
2737                 DRM_ERROR("FDI train 2 fail!\n");
2738
2739         DRM_DEBUG_KMS("FDI train done\n");
2740
2741 }
2742
2743 static const int snb_b_fdi_train_param[] = {
2744         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2745         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2746         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2747         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2748 };
2749
2750 /* The FDI link training functions for SNB/Cougarpoint. */
2751 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp, i, retry;
2758
2759         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2760            for train result */
2761         reg = FDI_RX_IMR(pipe);
2762         temp = I915_READ(reg);
2763         temp &= ~FDI_RX_SYMBOL_LOCK;
2764         temp &= ~FDI_RX_BIT_LOCK;
2765         I915_WRITE(reg, temp);
2766
2767         POSTING_READ(reg);
2768         udelay(150);
2769
2770         /* enable CPU FDI TX and PCH FDI RX */
2771         reg = FDI_TX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2774         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2775         temp &= ~FDI_LINK_TRAIN_NONE;
2776         temp |= FDI_LINK_TRAIN_PATTERN_1;
2777         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778         /* SNB-B */
2779         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2781
2782         I915_WRITE(FDI_RX_MISC(pipe),
2783                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2784
2785         reg = FDI_RX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         if (HAS_PCH_CPT(dev)) {
2788                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2790         } else {
2791                 temp &= ~FDI_LINK_TRAIN_NONE;
2792                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2793         }
2794         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2795
2796         POSTING_READ(reg);
2797         udelay(150);
2798
2799         for (i = 0; i < 4; i++) {
2800                 reg = FDI_TX_CTL(pipe);
2801                 temp = I915_READ(reg);
2802                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2803                 temp |= snb_b_fdi_train_param[i];
2804                 I915_WRITE(reg, temp);
2805
2806                 POSTING_READ(reg);
2807                 udelay(500);
2808
2809                 for (retry = 0; retry < 5; retry++) {
2810                         reg = FDI_RX_IIR(pipe);
2811                         temp = I915_READ(reg);
2812                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2813                         if (temp & FDI_RX_BIT_LOCK) {
2814                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2815                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2816                                 break;
2817                         }
2818                         udelay(50);
2819                 }
2820                 if (retry < 5)
2821                         break;
2822         }
2823         if (i == 4)
2824                 DRM_ERROR("FDI train 1 fail!\n");
2825
2826         /* Train 2 */
2827         reg = FDI_TX_CTL(pipe);
2828         temp = I915_READ(reg);
2829         temp &= ~FDI_LINK_TRAIN_NONE;
2830         temp |= FDI_LINK_TRAIN_PATTERN_2;
2831         if (IS_GEN6(dev)) {
2832                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2833                 /* SNB-B */
2834                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2835         }
2836         I915_WRITE(reg, temp);
2837
2838         reg = FDI_RX_CTL(pipe);
2839         temp = I915_READ(reg);
2840         if (HAS_PCH_CPT(dev)) {
2841                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2842                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2843         } else {
2844                 temp &= ~FDI_LINK_TRAIN_NONE;
2845                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2846         }
2847         I915_WRITE(reg, temp);
2848
2849         POSTING_READ(reg);
2850         udelay(150);
2851
2852         for (i = 0; i < 4; i++) {
2853                 reg = FDI_TX_CTL(pipe);
2854                 temp = I915_READ(reg);
2855                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2856                 temp |= snb_b_fdi_train_param[i];
2857                 I915_WRITE(reg, temp);
2858
2859                 POSTING_READ(reg);
2860                 udelay(500);
2861
2862                 for (retry = 0; retry < 5; retry++) {
2863                         reg = FDI_RX_IIR(pipe);
2864                         temp = I915_READ(reg);
2865                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2866                         if (temp & FDI_RX_SYMBOL_LOCK) {
2867                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2868                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2869                                 break;
2870                         }
2871                         udelay(50);
2872                 }
2873                 if (retry < 5)
2874                         break;
2875         }
2876         if (i == 4)
2877                 DRM_ERROR("FDI train 2 fail!\n");
2878
2879         DRM_DEBUG_KMS("FDI train done.\n");
2880 }
2881
2882 /* Manual link training for Ivy Bridge A0 parts */
2883 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2884 {
2885         struct drm_device *dev = crtc->dev;
2886         struct drm_i915_private *dev_priv = dev->dev_private;
2887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2888         int pipe = intel_crtc->pipe;
2889         u32 reg, temp, i, j;
2890
2891         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2892            for train result */
2893         reg = FDI_RX_IMR(pipe);
2894         temp = I915_READ(reg);
2895         temp &= ~FDI_RX_SYMBOL_LOCK;
2896         temp &= ~FDI_RX_BIT_LOCK;
2897         I915_WRITE(reg, temp);
2898
2899         POSTING_READ(reg);
2900         udelay(150);
2901
2902         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2903                       I915_READ(FDI_RX_IIR(pipe)));
2904
2905         /* Try each vswing and preemphasis setting twice before moving on */
2906         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2907                 /* disable first in case we need to retry */
2908                 reg = FDI_TX_CTL(pipe);
2909                 temp = I915_READ(reg);
2910                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2911                 temp &= ~FDI_TX_ENABLE;
2912                 I915_WRITE(reg, temp);
2913
2914                 reg = FDI_RX_CTL(pipe);
2915                 temp = I915_READ(reg);
2916                 temp &= ~FDI_LINK_TRAIN_AUTO;
2917                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2918                 temp &= ~FDI_RX_ENABLE;
2919                 I915_WRITE(reg, temp);
2920
2921                 /* enable CPU FDI TX and PCH FDI RX */
2922                 reg = FDI_TX_CTL(pipe);
2923                 temp = I915_READ(reg);
2924                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2925                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2926                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2927                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2928                 temp |= snb_b_fdi_train_param[j/2];
2929                 temp |= FDI_COMPOSITE_SYNC;
2930                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2931
2932                 I915_WRITE(FDI_RX_MISC(pipe),
2933                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2934
2935                 reg = FDI_RX_CTL(pipe);
2936                 temp = I915_READ(reg);
2937                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2938                 temp |= FDI_COMPOSITE_SYNC;
2939                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2940
2941                 POSTING_READ(reg);
2942                 udelay(1); /* should be 0.5us */
2943
2944                 for (i = 0; i < 4; i++) {
2945                         reg = FDI_RX_IIR(pipe);
2946                         temp = I915_READ(reg);
2947                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2948
2949                         if (temp & FDI_RX_BIT_LOCK ||
2950                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2951                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2952                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2953                                               i);
2954                                 break;
2955                         }
2956                         udelay(1); /* should be 0.5us */
2957                 }
2958                 if (i == 4) {
2959                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2960                         continue;
2961                 }
2962
2963                 /* Train 2 */
2964                 reg = FDI_TX_CTL(pipe);
2965                 temp = I915_READ(reg);
2966                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2967                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2968                 I915_WRITE(reg, temp);
2969
2970                 reg = FDI_RX_CTL(pipe);
2971                 temp = I915_READ(reg);
2972                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2973                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2974                 I915_WRITE(reg, temp);
2975
2976                 POSTING_READ(reg);
2977                 udelay(2); /* should be 1.5us */
2978
2979                 for (i = 0; i < 4; i++) {
2980                         reg = FDI_RX_IIR(pipe);
2981                         temp = I915_READ(reg);
2982                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2983
2984                         if (temp & FDI_RX_SYMBOL_LOCK ||
2985                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2986                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2987                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2988                                               i);
2989                                 goto train_done;
2990                         }
2991                         udelay(2); /* should be 1.5us */
2992                 }
2993                 if (i == 4)
2994                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2995         }
2996
2997 train_done:
2998         DRM_DEBUG_KMS("FDI train done.\n");
2999 }
3000
3001 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3002 {
3003         struct drm_device *dev = intel_crtc->base.dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         int pipe = intel_crtc->pipe;
3006         u32 reg, temp;
3007
3008
3009         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3010         reg = FDI_RX_CTL(pipe);
3011         temp = I915_READ(reg);
3012         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3013         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3014         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3015         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3016
3017         POSTING_READ(reg);
3018         udelay(200);
3019
3020         /* Switch from Rawclk to PCDclk */
3021         temp = I915_READ(reg);
3022         I915_WRITE(reg, temp | FDI_PCDCLK);
3023
3024         POSTING_READ(reg);
3025         udelay(200);
3026
3027         /* Enable CPU FDI TX PLL, always on for Ironlake */
3028         reg = FDI_TX_CTL(pipe);
3029         temp = I915_READ(reg);
3030         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3031                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3032
3033                 POSTING_READ(reg);
3034                 udelay(100);
3035         }
3036 }
3037
3038 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3039 {
3040         struct drm_device *dev = intel_crtc->base.dev;
3041         struct drm_i915_private *dev_priv = dev->dev_private;
3042         int pipe = intel_crtc->pipe;
3043         u32 reg, temp;
3044
3045         /* Switch from PCDclk to Rawclk */
3046         reg = FDI_RX_CTL(pipe);
3047         temp = I915_READ(reg);
3048         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3049
3050         /* Disable CPU FDI TX PLL */
3051         reg = FDI_TX_CTL(pipe);
3052         temp = I915_READ(reg);
3053         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3054
3055         POSTING_READ(reg);
3056         udelay(100);
3057
3058         reg = FDI_RX_CTL(pipe);
3059         temp = I915_READ(reg);
3060         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3061
3062         /* Wait for the clocks to turn off. */
3063         POSTING_READ(reg);
3064         udelay(100);
3065 }
3066
3067 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3068 {
3069         struct drm_device *dev = crtc->dev;
3070         struct drm_i915_private *dev_priv = dev->dev_private;
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072         int pipe = intel_crtc->pipe;
3073         u32 reg, temp;
3074
3075         /* disable CPU FDI tx and PCH FDI rx */
3076         reg = FDI_TX_CTL(pipe);
3077         temp = I915_READ(reg);
3078         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3079         POSTING_READ(reg);
3080
3081         reg = FDI_RX_CTL(pipe);
3082         temp = I915_READ(reg);
3083         temp &= ~(0x7 << 16);
3084         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3085         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3086
3087         POSTING_READ(reg);
3088         udelay(100);
3089
3090         /* Ironlake workaround, disable clock pointer after downing FDI */
3091         if (HAS_PCH_IBX(dev)) {
3092                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3093         }
3094
3095         /* still set train pattern 1 */
3096         reg = FDI_TX_CTL(pipe);
3097         temp = I915_READ(reg);
3098         temp &= ~FDI_LINK_TRAIN_NONE;
3099         temp |= FDI_LINK_TRAIN_PATTERN_1;
3100         I915_WRITE(reg, temp);
3101
3102         reg = FDI_RX_CTL(pipe);
3103         temp = I915_READ(reg);
3104         if (HAS_PCH_CPT(dev)) {
3105                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3107         } else {
3108                 temp &= ~FDI_LINK_TRAIN_NONE;
3109                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3110         }
3111         /* BPC in FDI rx is consistent with that in PIPECONF */
3112         temp &= ~(0x07 << 16);
3113         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3114         I915_WRITE(reg, temp);
3115
3116         POSTING_READ(reg);
3117         udelay(100);
3118 }
3119
3120 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3121 {
3122         struct intel_crtc *crtc;
3123
3124         /* Note that we don't need to be called with mode_config.lock here
3125          * as our list of CRTC objects is static for the lifetime of the
3126          * device and so cannot disappear as we iterate. Similarly, we can
3127          * happily treat the predicates as racy, atomic checks as userspace
3128          * cannot claim and pin a new fb without at least acquring the
3129          * struct_mutex and so serialising with us.
3130          */
3131         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3132                 if (atomic_read(&crtc->unpin_work_count) == 0)
3133                         continue;
3134
3135                 if (crtc->unpin_work)
3136                         intel_wait_for_vblank(dev, crtc->pipe);
3137
3138                 return true;
3139         }
3140
3141         return false;
3142 }
3143
3144 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3145 {
3146         struct drm_device *dev = crtc->dev;
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148
3149         if (crtc->primary->fb == NULL)
3150                 return;
3151
3152         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3153
3154         wait_event(dev_priv->pending_flip_queue,
3155                    !intel_crtc_has_pending_flip(crtc));
3156
3157         mutex_lock(&dev->struct_mutex);
3158         intel_finish_fb(crtc->primary->fb);
3159         mutex_unlock(&dev->struct_mutex);
3160 }
3161
3162 /* Program iCLKIP clock to the desired frequency */
3163 static void lpt_program_iclkip(struct drm_crtc *crtc)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3168         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3169         u32 temp;
3170
3171         mutex_lock(&dev_priv->dpio_lock);
3172
3173         /* It is necessary to ungate the pixclk gate prior to programming
3174          * the divisors, and gate it back when it is done.
3175          */
3176         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3177
3178         /* Disable SSCCTL */
3179         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3180                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3181                                 SBI_SSCCTL_DISABLE,
3182                         SBI_ICLK);
3183
3184         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3185         if (clock == 20000) {
3186                 auxdiv = 1;
3187                 divsel = 0x41;
3188                 phaseinc = 0x20;
3189         } else {
3190                 /* The iCLK virtual clock root frequency is in MHz,
3191                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3192                  * divisors, it is necessary to divide one by another, so we
3193                  * convert the virtual clock precision to KHz here for higher
3194                  * precision.
3195                  */
3196                 u32 iclk_virtual_root_freq = 172800 * 1000;
3197                 u32 iclk_pi_range = 64;
3198                 u32 desired_divisor, msb_divisor_value, pi_value;
3199
3200                 desired_divisor = (iclk_virtual_root_freq / clock);
3201                 msb_divisor_value = desired_divisor / iclk_pi_range;
3202                 pi_value = desired_divisor % iclk_pi_range;
3203
3204                 auxdiv = 0;
3205                 divsel = msb_divisor_value - 2;
3206                 phaseinc = pi_value;
3207         }
3208
3209         /* This should not happen with any sane values */
3210         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3211                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3212         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3213                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3214
3215         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3216                         clock,
3217                         auxdiv,
3218                         divsel,
3219                         phasedir,
3220                         phaseinc);
3221
3222         /* Program SSCDIVINTPHASE6 */
3223         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3224         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3225         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3226         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3227         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3228         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3229         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3230         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3231
3232         /* Program SSCAUXDIV */
3233         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3234         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3235         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3236         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3237
3238         /* Enable modulator and associated divider */
3239         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3240         temp &= ~SBI_SSCCTL_DISABLE;
3241         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3242
3243         /* Wait for initialization time */
3244         udelay(24);
3245
3246         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3247
3248         mutex_unlock(&dev_priv->dpio_lock);
3249 }
3250
3251 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3252                                                 enum pipe pch_transcoder)
3253 {
3254         struct drm_device *dev = crtc->base.dev;
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3257
3258         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3259                    I915_READ(HTOTAL(cpu_transcoder)));
3260         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3261                    I915_READ(HBLANK(cpu_transcoder)));
3262         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3263                    I915_READ(HSYNC(cpu_transcoder)));
3264
3265         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3266                    I915_READ(VTOTAL(cpu_transcoder)));
3267         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3268                    I915_READ(VBLANK(cpu_transcoder)));
3269         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3270                    I915_READ(VSYNC(cpu_transcoder)));
3271         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3272                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3273 }
3274
3275 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3276 {
3277         struct drm_i915_private *dev_priv = dev->dev_private;
3278         uint32_t temp;
3279
3280         temp = I915_READ(SOUTH_CHICKEN1);
3281         if (temp & FDI_BC_BIFURCATION_SELECT)
3282                 return;
3283
3284         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3285         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3286
3287         temp |= FDI_BC_BIFURCATION_SELECT;
3288         DRM_DEBUG_KMS("enabling fdi C rx\n");
3289         I915_WRITE(SOUTH_CHICKEN1, temp);
3290         POSTING_READ(SOUTH_CHICKEN1);
3291 }
3292
3293 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3294 {
3295         struct drm_device *dev = intel_crtc->base.dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297
3298         switch (intel_crtc->pipe) {
3299         case PIPE_A:
3300                 break;
3301         case PIPE_B:
3302                 if (intel_crtc->config.fdi_lanes > 2)
3303                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3304                 else
3305                         cpt_enable_fdi_bc_bifurcation(dev);
3306
3307                 break;
3308         case PIPE_C:
3309                 cpt_enable_fdi_bc_bifurcation(dev);
3310
3311                 break;
3312         default:
3313                 BUG();
3314         }
3315 }
3316
3317 /*
3318  * Enable PCH resources required for PCH ports:
3319  *   - PCH PLLs
3320  *   - FDI training & RX/TX
3321  *   - update transcoder timings
3322  *   - DP transcoding bits
3323  *   - transcoder
3324  */
3325 static void ironlake_pch_enable(struct drm_crtc *crtc)
3326 {
3327         struct drm_device *dev = crtc->dev;
3328         struct drm_i915_private *dev_priv = dev->dev_private;
3329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330         int pipe = intel_crtc->pipe;
3331         u32 reg, temp;
3332
3333         assert_pch_transcoder_disabled(dev_priv, pipe);
3334
3335         if (IS_IVYBRIDGE(dev))
3336                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3337
3338         /* Write the TU size bits before fdi link training, so that error
3339          * detection works. */
3340         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3341                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3342
3343         /* For PCH output, training FDI link */
3344         dev_priv->display.fdi_link_train(crtc);
3345
3346         /* We need to program the right clock selection before writing the pixel
3347          * mutliplier into the DPLL. */
3348         if (HAS_PCH_CPT(dev)) {
3349                 u32 sel;
3350
3351                 temp = I915_READ(PCH_DPLL_SEL);
3352                 temp |= TRANS_DPLL_ENABLE(pipe);
3353                 sel = TRANS_DPLLB_SEL(pipe);
3354                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3355                         temp |= sel;
3356                 else
3357                         temp &= ~sel;
3358                 I915_WRITE(PCH_DPLL_SEL, temp);
3359         }
3360
3361         /* XXX: pch pll's can be enabled any time before we enable the PCH
3362          * transcoder, and we actually should do this to not upset any PCH
3363          * transcoder that already use the clock when we share it.
3364          *
3365          * Note that enable_shared_dpll tries to do the right thing, but
3366          * get_shared_dpll unconditionally resets the pll - we need that to have
3367          * the right LVDS enable sequence. */
3368         ironlake_enable_shared_dpll(intel_crtc);
3369
3370         /* set transcoder timing, panel must allow it */
3371         assert_panel_unlocked(dev_priv, pipe);
3372         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3373
3374         intel_fdi_normal_train(crtc);
3375
3376         /* For PCH DP, enable TRANS_DP_CTL */
3377         if (HAS_PCH_CPT(dev) &&
3378             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3379              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3380                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3381                 reg = TRANS_DP_CTL(pipe);
3382                 temp = I915_READ(reg);
3383                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3384                           TRANS_DP_SYNC_MASK |
3385                           TRANS_DP_BPC_MASK);
3386                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3387                          TRANS_DP_ENH_FRAMING);
3388                 temp |= bpc << 9; /* same format but at 11:9 */
3389
3390                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3391                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3392                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3393                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3394
3395                 switch (intel_trans_dp_port_sel(crtc)) {
3396                 case PCH_DP_B:
3397                         temp |= TRANS_DP_PORT_SEL_B;
3398                         break;
3399                 case PCH_DP_C:
3400                         temp |= TRANS_DP_PORT_SEL_C;
3401                         break;
3402                 case PCH_DP_D:
3403                         temp |= TRANS_DP_PORT_SEL_D;
3404                         break;
3405                 default:
3406                         BUG();
3407                 }
3408
3409                 I915_WRITE(reg, temp);
3410         }
3411
3412         ironlake_enable_pch_transcoder(dev_priv, pipe);
3413 }
3414
3415 static void lpt_pch_enable(struct drm_crtc *crtc)
3416 {
3417         struct drm_device *dev = crtc->dev;
3418         struct drm_i915_private *dev_priv = dev->dev_private;
3419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3420         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3421
3422         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3423
3424         lpt_program_iclkip(crtc);
3425
3426         /* Set transcoder timing. */
3427         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3428
3429         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3430 }
3431
3432 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3433 {
3434         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3435
3436         if (pll == NULL)
3437                 return;
3438
3439         if (pll->refcount == 0) {
3440                 WARN(1, "bad %s refcount\n", pll->name);
3441                 return;
3442         }
3443
3444         if (--pll->refcount == 0) {
3445                 WARN_ON(pll->on);
3446                 WARN_ON(pll->active);
3447         }
3448
3449         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3450 }
3451
3452 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3453 {
3454         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3455         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3456         enum intel_dpll_id i;
3457
3458         if (pll) {
3459                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3460                               crtc->base.base.id, pll->name);
3461                 intel_put_shared_dpll(crtc);
3462         }
3463
3464         if (HAS_PCH_IBX(dev_priv->dev)) {
3465                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3466                 i = (enum intel_dpll_id) crtc->pipe;
3467                 pll = &dev_priv->shared_dplls[i];
3468
3469                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3470                               crtc->base.base.id, pll->name);
3471
3472                 goto found;
3473         }
3474
3475         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3476                 pll = &dev_priv->shared_dplls[i];
3477
3478                 /* Only want to check enabled timings first */
3479                 if (pll->refcount == 0)
3480                         continue;
3481
3482                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3483                            sizeof(pll->hw_state)) == 0) {
3484                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3485                                       crtc->base.base.id,
3486                                       pll->name, pll->refcount, pll->active);
3487
3488                         goto found;
3489                 }
3490         }
3491
3492         /* Ok no matching timings, maybe there's a free one? */
3493         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3494                 pll = &dev_priv->shared_dplls[i];
3495                 if (pll->refcount == 0) {
3496                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3497                                       crtc->base.base.id, pll->name);
3498                         goto found;
3499                 }
3500         }
3501
3502         return NULL;
3503
3504 found:
3505         crtc->config.shared_dpll = i;
3506         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3507                          pipe_name(crtc->pipe));
3508
3509         if (pll->active == 0) {
3510                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3511                        sizeof(pll->hw_state));
3512
3513                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3514                 WARN_ON(pll->on);
3515                 assert_shared_dpll_disabled(dev_priv, pll);
3516
3517                 pll->mode_set(dev_priv, pll);
3518         }
3519         pll->refcount++;
3520
3521         return pll;
3522 }
3523
3524 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3525 {
3526         struct drm_i915_private *dev_priv = dev->dev_private;
3527         int dslreg = PIPEDSL(pipe);
3528         u32 temp;
3529
3530         temp = I915_READ(dslreg);
3531         udelay(500);
3532         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3533                 if (wait_for(I915_READ(dslreg) != temp, 5))
3534                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3535         }
3536 }
3537
3538 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->base.dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         int pipe = crtc->pipe;
3543
3544         if (crtc->config.pch_pfit.enabled) {
3545                 /* Force use of hard-coded filter coefficients
3546                  * as some pre-programmed values are broken,
3547                  * e.g. x201.
3548                  */
3549                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3550                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3551                                                  PF_PIPE_SEL_IVB(pipe));
3552                 else
3553                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3554                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3555                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3556         }
3557 }
3558
3559 static void intel_enable_planes(struct drm_crtc *crtc)
3560 {
3561         struct drm_device *dev = crtc->dev;
3562         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3563         struct drm_plane *plane;
3564         struct intel_plane *intel_plane;
3565
3566         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3567                 intel_plane = to_intel_plane(plane);
3568                 if (intel_plane->pipe == pipe)
3569                         intel_plane_restore(&intel_plane->base);
3570         }
3571 }
3572
3573 static void intel_disable_planes(struct drm_crtc *crtc)
3574 {
3575         struct drm_device *dev = crtc->dev;
3576         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3577         struct drm_plane *plane;
3578         struct intel_plane *intel_plane;
3579
3580         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3581                 intel_plane = to_intel_plane(plane);
3582                 if (intel_plane->pipe == pipe)
3583                         intel_plane_disable(&intel_plane->base);
3584         }
3585 }
3586
3587 void hsw_enable_ips(struct intel_crtc *crtc)
3588 {
3589         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3590
3591         if (!crtc->config.ips_enabled)
3592                 return;
3593
3594         /* We can only enable IPS after we enable a plane and wait for a vblank.
3595          * We guarantee that the plane is enabled by calling intel_enable_ips
3596          * only after intel_enable_plane. And intel_enable_plane already waits
3597          * for a vblank, so all we need to do here is to enable the IPS bit. */
3598         assert_plane_enabled(dev_priv, crtc->plane);
3599         if (IS_BROADWELL(crtc->base.dev)) {
3600                 mutex_lock(&dev_priv->rps.hw_lock);
3601                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3602                 mutex_unlock(&dev_priv->rps.hw_lock);
3603                 /* Quoting Art Runyan: "its not safe to expect any particular
3604                  * value in IPS_CTL bit 31 after enabling IPS through the
3605                  * mailbox." Moreover, the mailbox may return a bogus state,
3606                  * so we need to just enable it and continue on.
3607                  */
3608         } else {
3609                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3610                 /* The bit only becomes 1 in the next vblank, so this wait here
3611                  * is essentially intel_wait_for_vblank. If we don't have this
3612                  * and don't wait for vblanks until the end of crtc_enable, then
3613                  * the HW state readout code will complain that the expected
3614                  * IPS_CTL value is not the one we read. */
3615                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3616                         DRM_ERROR("Timed out waiting for IPS enable\n");
3617         }
3618 }
3619
3620 void hsw_disable_ips(struct intel_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->base.dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624
3625         if (!crtc->config.ips_enabled)
3626                 return;
3627
3628         assert_plane_enabled(dev_priv, crtc->plane);
3629         if (IS_BROADWELL(dev)) {
3630                 mutex_lock(&dev_priv->rps.hw_lock);
3631                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3632                 mutex_unlock(&dev_priv->rps.hw_lock);
3633                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3634                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3635                         DRM_ERROR("Timed out waiting for IPS disable\n");
3636         } else {
3637                 I915_WRITE(IPS_CTL, 0);
3638                 POSTING_READ(IPS_CTL);
3639         }
3640
3641         /* We need to wait for a vblank before we can disable the plane. */
3642         intel_wait_for_vblank(dev, crtc->pipe);
3643 }
3644
3645 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3646 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3651         enum pipe pipe = intel_crtc->pipe;
3652         int palreg = PALETTE(pipe);
3653         int i;
3654         bool reenable_ips = false;
3655
3656         /* The clocks have to be on to load the palette. */
3657         if (!crtc->enabled || !intel_crtc->active)
3658                 return;
3659
3660         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3661                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3662                         assert_dsi_pll_enabled(dev_priv);
3663                 else
3664                         assert_pll_enabled(dev_priv, pipe);
3665         }
3666
3667         /* use legacy palette for Ironlake */
3668         if (HAS_PCH_SPLIT(dev))
3669                 palreg = LGC_PALETTE(pipe);
3670
3671         /* Workaround : Do not read or write the pipe palette/gamma data while
3672          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3673          */
3674         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3675             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3676              GAMMA_MODE_MODE_SPLIT)) {
3677                 hsw_disable_ips(intel_crtc);
3678                 reenable_ips = true;
3679         }
3680
3681         for (i = 0; i < 256; i++) {
3682                 I915_WRITE(palreg + 4 * i,
3683                            (intel_crtc->lut_r[i] << 16) |
3684                            (intel_crtc->lut_g[i] << 8) |
3685                            intel_crtc->lut_b[i]);
3686         }
3687
3688         if (reenable_ips)
3689                 hsw_enable_ips(intel_crtc);
3690 }
3691
3692 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3693 {
3694         if (!enable && intel_crtc->overlay) {
3695                 struct drm_device *dev = intel_crtc->base.dev;
3696                 struct drm_i915_private *dev_priv = dev->dev_private;
3697
3698                 mutex_lock(&dev->struct_mutex);
3699                 dev_priv->mm.interruptible = false;
3700                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3701                 dev_priv->mm.interruptible = true;
3702                 mutex_unlock(&dev->struct_mutex);
3703         }
3704
3705         /* Let userspace switch the overlay on again. In most cases userspace
3706          * has to recompute where to put it anyway.
3707          */
3708 }
3709
3710 /**
3711  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3712  * cursor plane briefly if not already running after enabling the display
3713  * plane.
3714  * This workaround avoids occasional blank screens when self refresh is
3715  * enabled.
3716  */
3717 static void
3718 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3719 {
3720         u32 cntl = I915_READ(CURCNTR(pipe));
3721
3722         if ((cntl & CURSOR_MODE) == 0) {
3723                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3724
3725                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3726                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3727                 intel_wait_for_vblank(dev_priv->dev, pipe);
3728                 I915_WRITE(CURCNTR(pipe), cntl);
3729                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3730                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3731         }
3732 }
3733
3734 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->dev;
3737         struct drm_i915_private *dev_priv = dev->dev_private;
3738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3739         int pipe = intel_crtc->pipe;
3740         int plane = intel_crtc->plane;
3741
3742         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3743         intel_enable_planes(crtc);
3744         /* The fixup needs to happen before cursor is enabled */
3745         if (IS_G4X(dev))
3746                 g4x_fixup_plane(dev_priv, pipe);
3747         intel_crtc_update_cursor(crtc, true);
3748         intel_crtc_dpms_overlay(intel_crtc, true);
3749
3750         hsw_enable_ips(intel_crtc);
3751
3752         mutex_lock(&dev->struct_mutex);
3753         intel_update_fbc(dev);
3754         mutex_unlock(&dev->struct_mutex);
3755 }
3756
3757 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3758 {
3759         struct drm_device *dev = crtc->dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762         int pipe = intel_crtc->pipe;
3763         int plane = intel_crtc->plane;
3764
3765         intel_crtc_wait_for_pending_flips(crtc);
3766         drm_vblank_off(dev, pipe);
3767
3768         if (dev_priv->fbc.plane == plane)
3769                 intel_disable_fbc(dev);
3770
3771         hsw_disable_ips(intel_crtc);
3772
3773         intel_crtc_dpms_overlay(intel_crtc, false);
3774         intel_crtc_update_cursor(crtc, false);
3775         intel_disable_planes(crtc);
3776         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3777 }
3778
3779 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         struct intel_encoder *encoder;
3785         int pipe = intel_crtc->pipe;
3786
3787         WARN_ON(!crtc->enabled);
3788
3789         if (intel_crtc->active)
3790                 return;
3791
3792         intel_crtc->active = true;
3793
3794         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3795         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3796
3797         for_each_encoder_on_crtc(dev, crtc, encoder)
3798                 if (encoder->pre_enable)
3799                         encoder->pre_enable(encoder);
3800
3801         if (intel_crtc->config.has_pch_encoder) {
3802                 /* Note: FDI PLL enabling _must_ be done before we enable the
3803                  * cpu pipes, hence this is separate from all the other fdi/pch
3804                  * enabling. */
3805                 ironlake_fdi_pll_enable(intel_crtc);
3806         } else {
3807                 assert_fdi_tx_disabled(dev_priv, pipe);
3808                 assert_fdi_rx_disabled(dev_priv, pipe);
3809         }
3810
3811         ironlake_pfit_enable(intel_crtc);
3812
3813         /*
3814          * On ILK+ LUT must be loaded before the pipe is running but with
3815          * clocks enabled
3816          */
3817         intel_crtc_load_lut(crtc);
3818
3819         intel_update_watermarks(crtc);
3820         intel_enable_pipe(intel_crtc);
3821
3822         if (intel_crtc->config.has_pch_encoder)
3823                 ironlake_pch_enable(crtc);
3824
3825         for_each_encoder_on_crtc(dev, crtc, encoder)
3826                 encoder->enable(encoder);
3827
3828         if (HAS_PCH_CPT(dev))
3829                 cpt_verify_modeset(dev, intel_crtc->pipe);
3830
3831         intel_crtc_enable_planes(crtc);
3832
3833         /*
3834          * There seems to be a race in PCH platform hw (at least on some
3835          * outputs) where an enabled pipe still completes any pageflip right
3836          * away (as if the pipe is off) instead of waiting for vblank. As soon
3837          * as the first vblank happend, everything works as expected. Hence just
3838          * wait for one vblank before returning to avoid strange things
3839          * happening.
3840          */
3841         intel_wait_for_vblank(dev, intel_crtc->pipe);
3842 }
3843
3844 /* IPS only exists on ULT machines and is tied to pipe A. */
3845 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3846 {
3847         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3848 }
3849
3850 /*
3851  * This implements the workaround described in the "notes" section of the mode
3852  * set sequence documentation. When going from no pipes or single pipe to
3853  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3854  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3855  */
3856 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3857 {
3858         struct drm_device *dev = crtc->base.dev;
3859         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3860
3861         /* We want to get the other_active_crtc only if there's only 1 other
3862          * active crtc. */
3863         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3864                 if (!crtc_it->active || crtc_it == crtc)
3865                         continue;
3866
3867                 if (other_active_crtc)
3868                         return;
3869
3870                 other_active_crtc = crtc_it;
3871         }
3872         if (!other_active_crtc)
3873                 return;
3874
3875         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3876         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3877 }
3878
3879 static void haswell_crtc_enable(struct drm_crtc *crtc)
3880 {
3881         struct drm_device *dev = crtc->dev;
3882         struct drm_i915_private *dev_priv = dev->dev_private;
3883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3884         struct intel_encoder *encoder;
3885         int pipe = intel_crtc->pipe;
3886
3887         WARN_ON(!crtc->enabled);
3888
3889         if (intel_crtc->active)
3890                 return;
3891
3892         intel_crtc->active = true;
3893
3894         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3895         if (intel_crtc->config.has_pch_encoder)
3896                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3897
3898         if (intel_crtc->config.has_pch_encoder)
3899                 dev_priv->display.fdi_link_train(crtc);
3900
3901         for_each_encoder_on_crtc(dev, crtc, encoder)
3902                 if (encoder->pre_enable)
3903                         encoder->pre_enable(encoder);
3904
3905         intel_ddi_enable_pipe_clock(intel_crtc);
3906
3907         ironlake_pfit_enable(intel_crtc);
3908
3909         /*
3910          * On ILK+ LUT must be loaded before the pipe is running but with
3911          * clocks enabled
3912          */
3913         intel_crtc_load_lut(crtc);
3914
3915         intel_ddi_set_pipe_settings(crtc);
3916         intel_ddi_enable_transcoder_func(crtc);
3917
3918         intel_update_watermarks(crtc);
3919         intel_enable_pipe(intel_crtc);
3920
3921         if (intel_crtc->config.has_pch_encoder)
3922                 lpt_pch_enable(crtc);
3923
3924         for_each_encoder_on_crtc(dev, crtc, encoder) {
3925                 encoder->enable(encoder);
3926                 intel_opregion_notify_encoder(encoder, true);
3927         }
3928
3929         /* If we change the relative order between pipe/planes enabling, we need
3930          * to change the workaround. */
3931         haswell_mode_set_planes_workaround(intel_crtc);
3932         intel_crtc_enable_planes(crtc);
3933 }
3934
3935 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3936 {
3937         struct drm_device *dev = crtc->base.dev;
3938         struct drm_i915_private *dev_priv = dev->dev_private;
3939         int pipe = crtc->pipe;
3940
3941         /* To avoid upsetting the power well on haswell only disable the pfit if
3942          * it's in use. The hw state code will make sure we get this right. */
3943         if (crtc->config.pch_pfit.enabled) {
3944                 I915_WRITE(PF_CTL(pipe), 0);
3945                 I915_WRITE(PF_WIN_POS(pipe), 0);
3946                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3947         }
3948 }
3949
3950 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3951 {
3952         struct drm_device *dev = crtc->dev;
3953         struct drm_i915_private *dev_priv = dev->dev_private;
3954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955         struct intel_encoder *encoder;
3956         int pipe = intel_crtc->pipe;
3957         u32 reg, temp;
3958
3959         if (!intel_crtc->active)
3960                 return;
3961
3962         intel_crtc_disable_planes(crtc);
3963
3964         for_each_encoder_on_crtc(dev, crtc, encoder)
3965                 encoder->disable(encoder);
3966
3967         if (intel_crtc->config.has_pch_encoder)
3968                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3969
3970         intel_disable_pipe(dev_priv, pipe);
3971
3972         ironlake_pfit_disable(intel_crtc);
3973
3974         for_each_encoder_on_crtc(dev, crtc, encoder)
3975                 if (encoder->post_disable)
3976                         encoder->post_disable(encoder);
3977
3978         if (intel_crtc->config.has_pch_encoder) {
3979                 ironlake_fdi_disable(crtc);
3980
3981                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3982                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3983
3984                 if (HAS_PCH_CPT(dev)) {
3985                         /* disable TRANS_DP_CTL */
3986                         reg = TRANS_DP_CTL(pipe);
3987                         temp = I915_READ(reg);
3988                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3989                                   TRANS_DP_PORT_SEL_MASK);
3990                         temp |= TRANS_DP_PORT_SEL_NONE;
3991                         I915_WRITE(reg, temp);
3992
3993                         /* disable DPLL_SEL */
3994                         temp = I915_READ(PCH_DPLL_SEL);
3995                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3996                         I915_WRITE(PCH_DPLL_SEL, temp);
3997                 }
3998
3999                 /* disable PCH DPLL */
4000                 intel_disable_shared_dpll(intel_crtc);
4001
4002                 ironlake_fdi_pll_disable(intel_crtc);
4003         }
4004
4005         intel_crtc->active = false;
4006         intel_update_watermarks(crtc);
4007
4008         mutex_lock(&dev->struct_mutex);
4009         intel_update_fbc(dev);
4010         mutex_unlock(&dev->struct_mutex);
4011 }
4012
4013 static void haswell_crtc_disable(struct drm_crtc *crtc)
4014 {
4015         struct drm_device *dev = crtc->dev;
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4018         struct intel_encoder *encoder;
4019         int pipe = intel_crtc->pipe;
4020         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4021
4022         if (!intel_crtc->active)
4023                 return;
4024
4025         intel_crtc_disable_planes(crtc);
4026
4027         for_each_encoder_on_crtc(dev, crtc, encoder) {
4028                 intel_opregion_notify_encoder(encoder, false);
4029                 encoder->disable(encoder);
4030         }
4031
4032         if (intel_crtc->config.has_pch_encoder)
4033                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4034         intel_disable_pipe(dev_priv, pipe);
4035
4036         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4037
4038         ironlake_pfit_disable(intel_crtc);
4039
4040         intel_ddi_disable_pipe_clock(intel_crtc);
4041
4042         for_each_encoder_on_crtc(dev, crtc, encoder)
4043                 if (encoder->post_disable)
4044                         encoder->post_disable(encoder);
4045
4046         if (intel_crtc->config.has_pch_encoder) {
4047                 lpt_disable_pch_transcoder(dev_priv);
4048                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4049                 intel_ddi_fdi_disable(crtc);
4050         }
4051
4052         intel_crtc->active = false;
4053         intel_update_watermarks(crtc);
4054
4055         mutex_lock(&dev->struct_mutex);
4056         intel_update_fbc(dev);
4057         mutex_unlock(&dev->struct_mutex);
4058 }
4059
4060 static void ironlake_crtc_off(struct drm_crtc *crtc)
4061 {
4062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063         intel_put_shared_dpll(intel_crtc);
4064 }
4065
4066 static void haswell_crtc_off(struct drm_crtc *crtc)
4067 {
4068         intel_ddi_put_crtc_pll(crtc);
4069 }
4070
4071 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->base.dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         struct intel_crtc_config *pipe_config = &crtc->config;
4076
4077         if (!crtc->config.gmch_pfit.control)
4078                 return;
4079
4080         /*
4081          * The panel fitter should only be adjusted whilst the pipe is disabled,
4082          * according to register description and PRM.
4083          */
4084         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4085         assert_pipe_disabled(dev_priv, crtc->pipe);
4086
4087         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4088         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4089
4090         /* Border color in case we don't scale up to the full screen. Black by
4091          * default, change to something else for debugging. */
4092         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4093 }
4094
4095 #define for_each_power_domain(domain, mask)                             \
4096         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4097                 if ((1 << (domain)) & (mask))
4098
4099 enum intel_display_power_domain
4100 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4101 {
4102         struct drm_device *dev = intel_encoder->base.dev;
4103         struct intel_digital_port *intel_dig_port;
4104
4105         switch (intel_encoder->type) {
4106         case INTEL_OUTPUT_UNKNOWN:
4107                 /* Only DDI platforms should ever use this output type */
4108                 WARN_ON_ONCE(!HAS_DDI(dev));
4109         case INTEL_OUTPUT_DISPLAYPORT:
4110         case INTEL_OUTPUT_HDMI:
4111         case INTEL_OUTPUT_EDP:
4112                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4113                 switch (intel_dig_port->port) {
4114                 case PORT_A:
4115                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4116                 case PORT_B:
4117                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4118                 case PORT_C:
4119                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4120                 case PORT_D:
4121                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4122                 default:
4123                         WARN_ON_ONCE(1);
4124                         return POWER_DOMAIN_PORT_OTHER;
4125                 }
4126         case INTEL_OUTPUT_ANALOG:
4127                 return POWER_DOMAIN_PORT_CRT;
4128         case INTEL_OUTPUT_DSI:
4129                 return POWER_DOMAIN_PORT_DSI;
4130         default:
4131                 return POWER_DOMAIN_PORT_OTHER;
4132         }
4133 }
4134
4135 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4136 {
4137         struct drm_device *dev = crtc->dev;
4138         struct intel_encoder *intel_encoder;
4139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4140         enum pipe pipe = intel_crtc->pipe;
4141         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4142         unsigned long mask;
4143         enum transcoder transcoder;
4144
4145         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4146
4147         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4148         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4149         if (pfit_enabled)
4150                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4151
4152         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4153                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4154
4155         return mask;
4156 }
4157
4158 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4159                                   bool enable)
4160 {
4161         if (dev_priv->power_domains.init_power_on == enable)
4162                 return;
4163
4164         if (enable)
4165                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4166         else
4167                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4168
4169         dev_priv->power_domains.init_power_on = enable;
4170 }
4171
4172 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4173 {
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4176         struct intel_crtc *crtc;
4177
4178         /*
4179          * First get all needed power domains, then put all unneeded, to avoid
4180          * any unnecessary toggling of the power wells.
4181          */
4182         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4183                 enum intel_display_power_domain domain;
4184
4185                 if (!crtc->base.enabled)
4186                         continue;
4187
4188                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4189
4190                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4191                         intel_display_power_get(dev_priv, domain);
4192         }
4193
4194         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4195                 enum intel_display_power_domain domain;
4196
4197                 for_each_power_domain(domain, crtc->enabled_power_domains)
4198                         intel_display_power_put(dev_priv, domain);
4199
4200                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4201         }
4202
4203         intel_display_set_init_power(dev_priv, false);
4204 }
4205
4206 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4207 {
4208         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4209
4210         /* Obtain SKU information */
4211         mutex_lock(&dev_priv->dpio_lock);
4212         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4213                 CCK_FUSE_HPLL_FREQ_MASK;
4214         mutex_unlock(&dev_priv->dpio_lock);
4215
4216         return vco_freq[hpll_freq];
4217 }
4218
4219 /* Adjust CDclk dividers to allow high res or save power if possible */
4220 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4221 {
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         u32 val, cmd;
4224
4225         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4226         dev_priv->vlv_cdclk_freq = cdclk;
4227
4228         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4229                 cmd = 2;
4230         else if (cdclk == 266)
4231                 cmd = 1;
4232         else
4233                 cmd = 0;
4234
4235         mutex_lock(&dev_priv->rps.hw_lock);
4236         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4237         val &= ~DSPFREQGUAR_MASK;
4238         val |= (cmd << DSPFREQGUAR_SHIFT);
4239         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4240         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4241                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4242                      50)) {
4243                 DRM_ERROR("timed out waiting for CDclk change\n");
4244         }
4245         mutex_unlock(&dev_priv->rps.hw_lock);
4246
4247         if (cdclk == 400) {
4248                 u32 divider, vco;
4249
4250                 vco = valleyview_get_vco(dev_priv);
4251                 divider = ((vco << 1) / cdclk) - 1;
4252
4253                 mutex_lock(&dev_priv->dpio_lock);
4254                 /* adjust cdclk divider */
4255                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4256                 val &= ~0xf;
4257                 val |= divider;
4258                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4259                 mutex_unlock(&dev_priv->dpio_lock);
4260         }
4261
4262         mutex_lock(&dev_priv->dpio_lock);
4263         /* adjust self-refresh exit latency value */
4264         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4265         val &= ~0x7f;
4266
4267         /*
4268          * For high bandwidth configs, we set a higher latency in the bunit
4269          * so that the core display fetch happens in time to avoid underruns.
4270          */
4271         if (cdclk == 400)
4272                 val |= 4500 / 250; /* 4.5 usec */
4273         else
4274                 val |= 3000 / 250; /* 3.0 usec */
4275         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4276         mutex_unlock(&dev_priv->dpio_lock);
4277
4278         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4279         intel_i2c_reset(dev);
4280 }
4281
4282 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4283 {
4284         int cur_cdclk, vco;
4285         int divider;
4286
4287         vco = valleyview_get_vco(dev_priv);
4288
4289         mutex_lock(&dev_priv->dpio_lock);
4290         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4291         mutex_unlock(&dev_priv->dpio_lock);
4292
4293         divider &= 0xf;
4294
4295         cur_cdclk = (vco << 1) / (divider + 1);
4296
4297         return cur_cdclk;
4298 }
4299
4300 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4301                                  int max_pixclk)
4302 {
4303         /*
4304          * Really only a few cases to deal with, as only 4 CDclks are supported:
4305          *   200MHz
4306          *   267MHz
4307          *   320MHz
4308          *   400MHz
4309          * So we check to see whether we're above 90% of the lower bin and
4310          * adjust if needed.
4311          */
4312         if (max_pixclk > 288000) {
4313                 return 400;
4314         } else if (max_pixclk > 240000) {
4315                 return 320;
4316         } else
4317                 return 266;
4318         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4319 }
4320
4321 /* compute the max pixel clock for new configuration */
4322 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4323 {
4324         struct drm_device *dev = dev_priv->dev;
4325         struct intel_crtc *intel_crtc;
4326         int max_pixclk = 0;
4327
4328         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4329                             base.head) {
4330                 if (intel_crtc->new_enabled)
4331                         max_pixclk = max(max_pixclk,
4332                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4333         }
4334
4335         return max_pixclk;
4336 }
4337
4338 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4339                                             unsigned *prepare_pipes)
4340 {
4341         struct drm_i915_private *dev_priv = dev->dev_private;
4342         struct intel_crtc *intel_crtc;
4343         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4344
4345         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4346             dev_priv->vlv_cdclk_freq)
4347                 return;
4348
4349         /* disable/enable all currently active pipes while we change cdclk */
4350         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4351                             base.head)
4352                 if (intel_crtc->base.enabled)
4353                         *prepare_pipes |= (1 << intel_crtc->pipe);
4354 }
4355
4356 static void valleyview_modeset_global_resources(struct drm_device *dev)
4357 {
4358         struct drm_i915_private *dev_priv = dev->dev_private;
4359         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4360         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4361
4362         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4363                 valleyview_set_cdclk(dev, req_cdclk);
4364         modeset_update_crtc_power_domains(dev);
4365 }
4366
4367 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4368 {
4369         struct drm_device *dev = crtc->dev;
4370         struct drm_i915_private *dev_priv = dev->dev_private;
4371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372         struct intel_encoder *encoder;
4373         int pipe = intel_crtc->pipe;
4374         bool is_dsi;
4375
4376         WARN_ON(!crtc->enabled);
4377
4378         if (intel_crtc->active)
4379                 return;
4380
4381         intel_crtc->active = true;
4382
4383         for_each_encoder_on_crtc(dev, crtc, encoder)
4384                 if (encoder->pre_pll_enable)
4385                         encoder->pre_pll_enable(encoder);
4386
4387         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4388
4389         if (!is_dsi)
4390                 vlv_enable_pll(intel_crtc);
4391
4392         for_each_encoder_on_crtc(dev, crtc, encoder)
4393                 if (encoder->pre_enable)
4394                         encoder->pre_enable(encoder);
4395
4396         i9xx_pfit_enable(intel_crtc);
4397
4398         intel_crtc_load_lut(crtc);
4399
4400         intel_update_watermarks(crtc);
4401         intel_enable_pipe(intel_crtc);
4402         intel_wait_for_vblank(dev_priv->dev, pipe);
4403         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4404
4405         intel_crtc_enable_planes(crtc);
4406
4407         for_each_encoder_on_crtc(dev, crtc, encoder)
4408                 encoder->enable(encoder);
4409 }
4410
4411 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4412 {
4413         struct drm_device *dev = crtc->dev;
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4416         struct intel_encoder *encoder;
4417         int pipe = intel_crtc->pipe;
4418
4419         WARN_ON(!crtc->enabled);
4420
4421         if (intel_crtc->active)
4422                 return;
4423
4424         intel_crtc->active = true;
4425
4426         for_each_encoder_on_crtc(dev, crtc, encoder)
4427                 if (encoder->pre_enable)
4428                         encoder->pre_enable(encoder);
4429
4430         i9xx_enable_pll(intel_crtc);
4431
4432         i9xx_pfit_enable(intel_crtc);
4433
4434         intel_crtc_load_lut(crtc);
4435
4436         intel_update_watermarks(crtc);
4437         intel_enable_pipe(intel_crtc);
4438         intel_wait_for_vblank(dev_priv->dev, pipe);
4439         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4440
4441         intel_crtc_enable_planes(crtc);
4442
4443         for_each_encoder_on_crtc(dev, crtc, encoder)
4444                 encoder->enable(encoder);
4445 }
4446
4447 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4448 {
4449         struct drm_device *dev = crtc->base.dev;
4450         struct drm_i915_private *dev_priv = dev->dev_private;
4451
4452         if (!crtc->config.gmch_pfit.control)
4453                 return;
4454
4455         assert_pipe_disabled(dev_priv, crtc->pipe);
4456
4457         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4458                          I915_READ(PFIT_CONTROL));
4459         I915_WRITE(PFIT_CONTROL, 0);
4460 }
4461
4462 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4463 {
4464         struct drm_device *dev = crtc->dev;
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467         struct intel_encoder *encoder;
4468         int pipe = intel_crtc->pipe;
4469
4470         if (!intel_crtc->active)
4471                 return;
4472
4473         for_each_encoder_on_crtc(dev, crtc, encoder)
4474                 encoder->disable(encoder);
4475
4476         intel_crtc_disable_planes(crtc);
4477
4478         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4479         intel_disable_pipe(dev_priv, pipe);
4480
4481         i9xx_pfit_disable(intel_crtc);
4482
4483         for_each_encoder_on_crtc(dev, crtc, encoder)
4484                 if (encoder->post_disable)
4485                         encoder->post_disable(encoder);
4486
4487         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4488                 if (IS_CHERRYVIEW(dev))
4489                         chv_disable_pll(dev_priv, pipe);
4490                 else if (IS_VALLEYVIEW(dev))
4491                         vlv_disable_pll(dev_priv, pipe);
4492                 else
4493                         i9xx_disable_pll(dev_priv, pipe);
4494         }
4495
4496         intel_crtc->active = false;
4497         intel_update_watermarks(crtc);
4498
4499         intel_update_fbc(dev);
4500 }
4501
4502 static void i9xx_crtc_off(struct drm_crtc *crtc)
4503 {
4504 }
4505
4506 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4507                                     bool enabled)
4508 {
4509         struct drm_device *dev = crtc->dev;
4510         struct drm_i915_master_private *master_priv;
4511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512         int pipe = intel_crtc->pipe;
4513
4514         if (!dev->primary->master)
4515                 return;
4516
4517         master_priv = dev->primary->master->driver_priv;
4518         if (!master_priv->sarea_priv)
4519                 return;
4520
4521         switch (pipe) {
4522         case 0:
4523                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4524                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4525                 break;
4526         case 1:
4527                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4528                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4529                 break;
4530         default:
4531                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4532                 break;
4533         }
4534 }
4535
4536 /**
4537  * Sets the power management mode of the pipe and plane.
4538  */
4539 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4540 {
4541         struct drm_device *dev = crtc->dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         struct intel_encoder *intel_encoder;
4544         bool enable = false;
4545
4546         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4547                 enable |= intel_encoder->connectors_active;
4548
4549         if (enable)
4550                 dev_priv->display.crtc_enable(crtc);
4551         else
4552                 dev_priv->display.crtc_disable(crtc);
4553
4554         intel_crtc_update_sarea(crtc, enable);
4555 }
4556
4557 static void intel_crtc_disable(struct drm_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_connector *connector;
4561         struct drm_i915_private *dev_priv = dev->dev_private;
4562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4563
4564         /* crtc should still be enabled when we disable it. */
4565         WARN_ON(!crtc->enabled);
4566
4567         dev_priv->display.crtc_disable(crtc);
4568         intel_crtc->eld_vld = false;
4569         intel_crtc_update_sarea(crtc, false);
4570         dev_priv->display.off(crtc);
4571
4572         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4573         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4574         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4575
4576         if (crtc->primary->fb) {
4577                 mutex_lock(&dev->struct_mutex);
4578                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4579                 mutex_unlock(&dev->struct_mutex);
4580                 crtc->primary->fb = NULL;
4581         }
4582
4583         /* Update computed state. */
4584         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4585                 if (!connector->encoder || !connector->encoder->crtc)
4586                         continue;
4587
4588                 if (connector->encoder->crtc != crtc)
4589                         continue;
4590
4591                 connector->dpms = DRM_MODE_DPMS_OFF;
4592                 to_intel_encoder(connector->encoder)->connectors_active = false;
4593         }
4594 }
4595
4596 void intel_encoder_destroy(struct drm_encoder *encoder)
4597 {
4598         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4599
4600         drm_encoder_cleanup(encoder);
4601         kfree(intel_encoder);
4602 }
4603
4604 /* Simple dpms helper for encoders with just one connector, no cloning and only
4605  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4606  * state of the entire output pipe. */
4607 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4608 {
4609         if (mode == DRM_MODE_DPMS_ON) {
4610                 encoder->connectors_active = true;
4611
4612                 intel_crtc_update_dpms(encoder->base.crtc);
4613         } else {
4614                 encoder->connectors_active = false;
4615
4616                 intel_crtc_update_dpms(encoder->base.crtc);
4617         }
4618 }
4619
4620 /* Cross check the actual hw state with our own modeset state tracking (and it's
4621  * internal consistency). */
4622 static void intel_connector_check_state(struct intel_connector *connector)
4623 {
4624         if (connector->get_hw_state(connector)) {
4625                 struct intel_encoder *encoder = connector->encoder;
4626                 struct drm_crtc *crtc;
4627                 bool encoder_enabled;
4628                 enum pipe pipe;
4629
4630                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4631                               connector->base.base.id,
4632                               drm_get_connector_name(&connector->base));
4633
4634                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4635                      "wrong connector dpms state\n");
4636                 WARN(connector->base.encoder != &encoder->base,
4637                      "active connector not linked to encoder\n");
4638                 WARN(!encoder->connectors_active,
4639                      "encoder->connectors_active not set\n");
4640
4641                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4642                 WARN(!encoder_enabled, "encoder not enabled\n");
4643                 if (WARN_ON(!encoder->base.crtc))
4644                         return;
4645
4646                 crtc = encoder->base.crtc;
4647
4648                 WARN(!crtc->enabled, "crtc not enabled\n");
4649                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4650                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4651                      "encoder active on the wrong pipe\n");
4652         }
4653 }
4654
4655 /* Even simpler default implementation, if there's really no special case to
4656  * consider. */
4657 void intel_connector_dpms(struct drm_connector *connector, int mode)
4658 {
4659         /* All the simple cases only support two dpms states. */
4660         if (mode != DRM_MODE_DPMS_ON)
4661                 mode = DRM_MODE_DPMS_OFF;
4662
4663         if (mode == connector->dpms)
4664                 return;
4665
4666         connector->dpms = mode;
4667
4668         /* Only need to change hw state when actually enabled */
4669         if (connector->encoder)
4670                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4671
4672         intel_modeset_check_state(connector->dev);
4673 }
4674
4675 /* Simple connector->get_hw_state implementation for encoders that support only
4676  * one connector and no cloning and hence the encoder state determines the state
4677  * of the connector. */
4678 bool intel_connector_get_hw_state(struct intel_connector *connector)
4679 {
4680         enum pipe pipe = 0;
4681         struct intel_encoder *encoder = connector->encoder;
4682
4683         return encoder->get_hw_state(encoder, &pipe);
4684 }
4685
4686 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4687                                      struct intel_crtc_config *pipe_config)
4688 {
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690         struct intel_crtc *pipe_B_crtc =
4691                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4692
4693         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4694                       pipe_name(pipe), pipe_config->fdi_lanes);
4695         if (pipe_config->fdi_lanes > 4) {
4696                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4697                               pipe_name(pipe), pipe_config->fdi_lanes);
4698                 return false;
4699         }
4700
4701         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4702                 if (pipe_config->fdi_lanes > 2) {
4703                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4704                                       pipe_config->fdi_lanes);
4705                         return false;
4706                 } else {
4707                         return true;
4708                 }
4709         }
4710
4711         if (INTEL_INFO(dev)->num_pipes == 2)
4712                 return true;
4713
4714         /* Ivybridge 3 pipe is really complicated */
4715         switch (pipe) {
4716         case PIPE_A:
4717                 return true;
4718         case PIPE_B:
4719                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4720                     pipe_config->fdi_lanes > 2) {
4721                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4722                                       pipe_name(pipe), pipe_config->fdi_lanes);
4723                         return false;
4724                 }
4725                 return true;
4726         case PIPE_C:
4727                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4728                     pipe_B_crtc->config.fdi_lanes <= 2) {
4729                         if (pipe_config->fdi_lanes > 2) {
4730                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4731                                               pipe_name(pipe), pipe_config->fdi_lanes);
4732                                 return false;
4733                         }
4734                 } else {
4735                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4736                         return false;
4737                 }
4738                 return true;
4739         default:
4740                 BUG();
4741         }
4742 }
4743
4744 #define RETRY 1
4745 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4746                                        struct intel_crtc_config *pipe_config)
4747 {
4748         struct drm_device *dev = intel_crtc->base.dev;
4749         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4750         int lane, link_bw, fdi_dotclock;
4751         bool setup_ok, needs_recompute = false;
4752
4753 retry:
4754         /* FDI is a binary signal running at ~2.7GHz, encoding
4755          * each output octet as 10 bits. The actual frequency
4756          * is stored as a divider into a 100MHz clock, and the
4757          * mode pixel clock is stored in units of 1KHz.
4758          * Hence the bw of each lane in terms of the mode signal
4759          * is:
4760          */
4761         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4762
4763         fdi_dotclock = adjusted_mode->crtc_clock;
4764
4765         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4766                                            pipe_config->pipe_bpp);
4767
4768         pipe_config->fdi_lanes = lane;
4769
4770         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4771                                link_bw, &pipe_config->fdi_m_n);
4772
4773         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4774                                             intel_crtc->pipe, pipe_config);
4775         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4776                 pipe_config->pipe_bpp -= 2*3;
4777                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4778                               pipe_config->pipe_bpp);
4779                 needs_recompute = true;
4780                 pipe_config->bw_constrained = true;
4781
4782                 goto retry;
4783         }
4784
4785         if (needs_recompute)
4786                 return RETRY;
4787
4788         return setup_ok ? 0 : -EINVAL;
4789 }
4790
4791 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4792                                    struct intel_crtc_config *pipe_config)
4793 {
4794         pipe_config->ips_enabled = i915.enable_ips &&
4795                                    hsw_crtc_supports_ips(crtc) &&
4796                                    pipe_config->pipe_bpp <= 24;
4797 }
4798
4799 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4800                                      struct intel_crtc_config *pipe_config)
4801 {
4802         struct drm_device *dev = crtc->base.dev;
4803         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4804
4805         /* FIXME should check pixel clock limits on all platforms */
4806         if (INTEL_INFO(dev)->gen < 4) {
4807                 struct drm_i915_private *dev_priv = dev->dev_private;
4808                 int clock_limit =
4809                         dev_priv->display.get_display_clock_speed(dev);
4810
4811                 /*
4812                  * Enable pixel doubling when the dot clock
4813                  * is > 90% of the (display) core speed.
4814                  *
4815                  * GDG double wide on either pipe,
4816                  * otherwise pipe A only.
4817                  */
4818                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4819                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4820                         clock_limit *= 2;
4821                         pipe_config->double_wide = true;
4822                 }
4823
4824                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4825                         return -EINVAL;
4826         }
4827
4828         /*
4829          * Pipe horizontal size must be even in:
4830          * - DVO ganged mode
4831          * - LVDS dual channel mode
4832          * - Double wide pipe
4833          */
4834         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4835              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4836                 pipe_config->pipe_src_w &= ~1;
4837
4838         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4839          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4840          */
4841         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4842                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4843                 return -EINVAL;
4844
4845         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4846                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4847         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4848                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4849                  * for lvds. */
4850                 pipe_config->pipe_bpp = 8*3;
4851         }
4852
4853         if (HAS_IPS(dev))
4854                 hsw_compute_ips_config(crtc, pipe_config);
4855
4856         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4857          * clock survives for now. */
4858         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4859                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4860
4861         if (pipe_config->has_pch_encoder)
4862                 return ironlake_fdi_compute_config(crtc, pipe_config);
4863
4864         return 0;
4865 }
4866
4867 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4868 {
4869         return 400000; /* FIXME */
4870 }
4871
4872 static int i945_get_display_clock_speed(struct drm_device *dev)
4873 {
4874         return 400000;
4875 }
4876
4877 static int i915_get_display_clock_speed(struct drm_device *dev)
4878 {
4879         return 333000;
4880 }
4881
4882 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4883 {
4884         return 200000;
4885 }
4886
4887 static int pnv_get_display_clock_speed(struct drm_device *dev)
4888 {
4889         u16 gcfgc = 0;
4890
4891         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4892
4893         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4894         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4895                 return 267000;
4896         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4897                 return 333000;
4898         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4899                 return 444000;
4900         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4901                 return 200000;
4902         default:
4903                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4904         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4905                 return 133000;
4906         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4907                 return 167000;
4908         }
4909 }
4910
4911 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4912 {
4913         u16 gcfgc = 0;
4914
4915         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4916
4917         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4918                 return 133000;
4919         else {
4920                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4921                 case GC_DISPLAY_CLOCK_333_MHZ:
4922                         return 333000;
4923                 default:
4924                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4925                         return 190000;
4926                 }
4927         }
4928 }
4929
4930 static int i865_get_display_clock_speed(struct drm_device *dev)
4931 {
4932         return 266000;
4933 }
4934
4935 static int i855_get_display_clock_speed(struct drm_device *dev)
4936 {
4937         u16 hpllcc = 0;
4938         /* Assume that the hardware is in the high speed state.  This
4939          * should be the default.
4940          */
4941         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4942         case GC_CLOCK_133_200:
4943         case GC_CLOCK_100_200:
4944                 return 200000;
4945         case GC_CLOCK_166_250:
4946                 return 250000;
4947         case GC_CLOCK_100_133:
4948                 return 133000;
4949         }
4950
4951         /* Shouldn't happen */
4952         return 0;
4953 }
4954
4955 static int i830_get_display_clock_speed(struct drm_device *dev)
4956 {
4957         return 133000;
4958 }
4959
4960 static void
4961 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4962 {
4963         while (*num > DATA_LINK_M_N_MASK ||
4964                *den > DATA_LINK_M_N_MASK) {
4965                 *num >>= 1;
4966                 *den >>= 1;
4967         }
4968 }
4969
4970 static void compute_m_n(unsigned int m, unsigned int n,
4971                         uint32_t *ret_m, uint32_t *ret_n)
4972 {
4973         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4974         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4975         intel_reduce_m_n_ratio(ret_m, ret_n);
4976 }
4977
4978 void
4979 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4980                        int pixel_clock, int link_clock,
4981                        struct intel_link_m_n *m_n)
4982 {
4983         m_n->tu = 64;
4984
4985         compute_m_n(bits_per_pixel * pixel_clock,
4986                     link_clock * nlanes * 8,
4987                     &m_n->gmch_m, &m_n->gmch_n);
4988
4989         compute_m_n(pixel_clock, link_clock,
4990                     &m_n->link_m, &m_n->link_n);
4991 }
4992
4993 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4994 {
4995         if (i915.panel_use_ssc >= 0)
4996                 return i915.panel_use_ssc != 0;
4997         return dev_priv->vbt.lvds_use_ssc
4998                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4999 }
5000
5001 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5002 {
5003         struct drm_device *dev = crtc->dev;
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         int refclk;
5006
5007         if (IS_VALLEYVIEW(dev)) {
5008                 refclk = 100000;
5009         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5010             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5011                 refclk = dev_priv->vbt.lvds_ssc_freq;
5012                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5013         } else if (!IS_GEN2(dev)) {
5014                 refclk = 96000;
5015         } else {
5016                 refclk = 48000;
5017         }
5018
5019         return refclk;
5020 }
5021
5022 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5023 {
5024         return (1 << dpll->n) << 16 | dpll->m2;
5025 }
5026
5027 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5028 {
5029         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5030 }
5031
5032 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5033                                      intel_clock_t *reduced_clock)
5034 {
5035         struct drm_device *dev = crtc->base.dev;
5036         struct drm_i915_private *dev_priv = dev->dev_private;
5037         int pipe = crtc->pipe;
5038         u32 fp, fp2 = 0;
5039
5040         if (IS_PINEVIEW(dev)) {
5041                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5042                 if (reduced_clock)
5043                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5044         } else {
5045                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5046                 if (reduced_clock)
5047                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5048         }
5049
5050         I915_WRITE(FP0(pipe), fp);
5051         crtc->config.dpll_hw_state.fp0 = fp;
5052
5053         crtc->lowfreq_avail = false;
5054         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5055             reduced_clock && i915.powersave) {
5056                 I915_WRITE(FP1(pipe), fp2);
5057                 crtc->config.dpll_hw_state.fp1 = fp2;
5058                 crtc->lowfreq_avail = true;
5059         } else {
5060                 I915_WRITE(FP1(pipe), fp);
5061                 crtc->config.dpll_hw_state.fp1 = fp;
5062         }
5063 }
5064
5065 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5066                 pipe)
5067 {
5068         u32 reg_val;
5069
5070         /*
5071          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5072          * and set it to a reasonable value instead.
5073          */
5074         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5075         reg_val &= 0xffffff00;
5076         reg_val |= 0x00000030;
5077         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5078
5079         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5080         reg_val &= 0x8cffffff;
5081         reg_val = 0x8c000000;
5082         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5083
5084         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5085         reg_val &= 0xffffff00;
5086         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5087
5088         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5089         reg_val &= 0x00ffffff;
5090         reg_val |= 0xb0000000;
5091         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5092 }
5093
5094 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5095                                          struct intel_link_m_n *m_n)
5096 {
5097         struct drm_device *dev = crtc->base.dev;
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099         int pipe = crtc->pipe;
5100
5101         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5102         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5103         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5104         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5105 }
5106
5107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5108                                          struct intel_link_m_n *m_n)
5109 {
5110         struct drm_device *dev = crtc->base.dev;
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         int pipe = crtc->pipe;
5113         enum transcoder transcoder = crtc->config.cpu_transcoder;
5114
5115         if (INTEL_INFO(dev)->gen >= 5) {
5116                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5117                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5118                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5119                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5120         } else {
5121                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5122                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5123                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5124                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5125         }
5126 }
5127
5128 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5129 {
5130         if (crtc->config.has_pch_encoder)
5131                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5132         else
5133                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5134 }
5135
5136 static void vlv_update_pll(struct intel_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->base.dev;
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140         int pipe = crtc->pipe;
5141         u32 dpll, mdiv;
5142         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5143         u32 coreclk, reg_val, dpll_md;
5144
5145         mutex_lock(&dev_priv->dpio_lock);
5146
5147         bestn = crtc->config.dpll.n;
5148         bestm1 = crtc->config.dpll.m1;
5149         bestm2 = crtc->config.dpll.m2;
5150         bestp1 = crtc->config.dpll.p1;
5151         bestp2 = crtc->config.dpll.p2;
5152
5153         /* See eDP HDMI DPIO driver vbios notes doc */
5154
5155         /* PLL B needs special handling */
5156         if (pipe)
5157                 vlv_pllb_recal_opamp(dev_priv, pipe);
5158
5159         /* Set up Tx target for periodic Rcomp update */
5160         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5161
5162         /* Disable target IRef on PLL */
5163         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5164         reg_val &= 0x00ffffff;
5165         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5166
5167         /* Disable fast lock */
5168         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5169
5170         /* Set idtafcrecal before PLL is enabled */
5171         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5172         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5173         mdiv |= ((bestn << DPIO_N_SHIFT));
5174         mdiv |= (1 << DPIO_K_SHIFT);
5175
5176         /*
5177          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5178          * but we don't support that).
5179          * Note: don't use the DAC post divider as it seems unstable.
5180          */
5181         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5182         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5183
5184         mdiv |= DPIO_ENABLE_CALIBRATION;
5185         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5186
5187         /* Set HBR and RBR LPF coefficients */
5188         if (crtc->config.port_clock == 162000 ||
5189             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5190             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5191                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5192                                  0x009f0003);
5193         else
5194                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5195                                  0x00d0000f);
5196
5197         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5198             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5199                 /* Use SSC source */
5200                 if (!pipe)
5201                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5202                                          0x0df40000);
5203                 else
5204                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5205                                          0x0df70000);
5206         } else { /* HDMI or VGA */
5207                 /* Use bend source */
5208                 if (!pipe)
5209                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5210                                          0x0df70000);
5211                 else
5212                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5213                                          0x0df40000);
5214         }
5215
5216         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5217         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5218         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5219             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5220                 coreclk |= 0x01000000;
5221         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5222
5223         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5224
5225         /*
5226          * Enable DPIO clock input. We should never disable the reference
5227          * clock for pipe B, since VGA hotplug / manual detection depends
5228          * on it.
5229          */
5230         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5231                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5232         /* We should never disable this, set it here for state tracking */
5233         if (pipe == PIPE_B)
5234                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5235         dpll |= DPLL_VCO_ENABLE;
5236         crtc->config.dpll_hw_state.dpll = dpll;
5237
5238         dpll_md = (crtc->config.pixel_multiplier - 1)
5239                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5240         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5241
5242         mutex_unlock(&dev_priv->dpio_lock);
5243 }
5244
5245 static void i9xx_update_pll(struct intel_crtc *crtc,
5246                             intel_clock_t *reduced_clock,
5247                             int num_connectors)
5248 {
5249         struct drm_device *dev = crtc->base.dev;
5250         struct drm_i915_private *dev_priv = dev->dev_private;
5251         u32 dpll;
5252         bool is_sdvo;
5253         struct dpll *clock = &crtc->config.dpll;
5254
5255         i9xx_update_pll_dividers(crtc, reduced_clock);
5256
5257         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5258                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5259
5260         dpll = DPLL_VGA_MODE_DIS;
5261
5262         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5263                 dpll |= DPLLB_MODE_LVDS;
5264         else
5265                 dpll |= DPLLB_MODE_DAC_SERIAL;
5266
5267         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5268                 dpll |= (crtc->config.pixel_multiplier - 1)
5269                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5270         }
5271
5272         if (is_sdvo)
5273                 dpll |= DPLL_SDVO_HIGH_SPEED;
5274
5275         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5276                 dpll |= DPLL_SDVO_HIGH_SPEED;
5277
5278         /* compute bitmask from p1 value */
5279         if (IS_PINEVIEW(dev))
5280                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5281         else {
5282                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5283                 if (IS_G4X(dev) && reduced_clock)
5284                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5285         }
5286         switch (clock->p2) {
5287         case 5:
5288                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5289                 break;
5290         case 7:
5291                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5292                 break;
5293         case 10:
5294                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5295                 break;
5296         case 14:
5297                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5298                 break;
5299         }
5300         if (INTEL_INFO(dev)->gen >= 4)
5301                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5302
5303         if (crtc->config.sdvo_tv_clock)
5304                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5305         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5306                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5307                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5308         else
5309                 dpll |= PLL_REF_INPUT_DREFCLK;
5310
5311         dpll |= DPLL_VCO_ENABLE;
5312         crtc->config.dpll_hw_state.dpll = dpll;
5313
5314         if (INTEL_INFO(dev)->gen >= 4) {
5315                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5316                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5317                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5318         }
5319 }
5320
5321 static void i8xx_update_pll(struct intel_crtc *crtc,
5322                             intel_clock_t *reduced_clock,
5323                             int num_connectors)
5324 {
5325         struct drm_device *dev = crtc->base.dev;
5326         struct drm_i915_private *dev_priv = dev->dev_private;
5327         u32 dpll;
5328         struct dpll *clock = &crtc->config.dpll;
5329
5330         i9xx_update_pll_dividers(crtc, reduced_clock);
5331
5332         dpll = DPLL_VGA_MODE_DIS;
5333
5334         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5335                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5336         } else {
5337                 if (clock->p1 == 2)
5338                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5339                 else
5340                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5341                 if (clock->p2 == 4)
5342                         dpll |= PLL_P2_DIVIDE_BY_4;
5343         }
5344
5345         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5346                 dpll |= DPLL_DVO_2X_MODE;
5347
5348         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5349                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5350                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5351         else
5352                 dpll |= PLL_REF_INPUT_DREFCLK;
5353
5354         dpll |= DPLL_VCO_ENABLE;
5355         crtc->config.dpll_hw_state.dpll = dpll;
5356 }
5357
5358 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5359 {
5360         struct drm_device *dev = intel_crtc->base.dev;
5361         struct drm_i915_private *dev_priv = dev->dev_private;
5362         enum pipe pipe = intel_crtc->pipe;
5363         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5364         struct drm_display_mode *adjusted_mode =
5365                 &intel_crtc->config.adjusted_mode;
5366         uint32_t crtc_vtotal, crtc_vblank_end;
5367         int vsyncshift = 0;
5368
5369         /* We need to be careful not to changed the adjusted mode, for otherwise
5370          * the hw state checker will get angry at the mismatch. */
5371         crtc_vtotal = adjusted_mode->crtc_vtotal;
5372         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5373
5374         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5375                 /* the chip adds 2 halflines automatically */
5376                 crtc_vtotal -= 1;
5377                 crtc_vblank_end -= 1;
5378
5379                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5380                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5381                 else
5382                         vsyncshift = adjusted_mode->crtc_hsync_start -
5383                                 adjusted_mode->crtc_htotal / 2;
5384                 if (vsyncshift < 0)
5385                         vsyncshift += adjusted_mode->crtc_htotal;
5386         }
5387
5388         if (INTEL_INFO(dev)->gen > 3)
5389                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5390
5391         I915_WRITE(HTOTAL(cpu_transcoder),
5392                    (adjusted_mode->crtc_hdisplay - 1) |
5393                    ((adjusted_mode->crtc_htotal - 1) << 16));
5394         I915_WRITE(HBLANK(cpu_transcoder),
5395                    (adjusted_mode->crtc_hblank_start - 1) |
5396                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5397         I915_WRITE(HSYNC(cpu_transcoder),
5398                    (adjusted_mode->crtc_hsync_start - 1) |
5399                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5400
5401         I915_WRITE(VTOTAL(cpu_transcoder),
5402                    (adjusted_mode->crtc_vdisplay - 1) |
5403                    ((crtc_vtotal - 1) << 16));
5404         I915_WRITE(VBLANK(cpu_transcoder),
5405                    (adjusted_mode->crtc_vblank_start - 1) |
5406                    ((crtc_vblank_end - 1) << 16));
5407         I915_WRITE(VSYNC(cpu_transcoder),
5408                    (adjusted_mode->crtc_vsync_start - 1) |
5409                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5410
5411         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5412          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5413          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5414          * bits. */
5415         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5416             (pipe == PIPE_B || pipe == PIPE_C))
5417                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5418
5419         /* pipesrc controls the size that is scaled from, which should
5420          * always be the user's requested size.
5421          */
5422         I915_WRITE(PIPESRC(pipe),
5423                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5424                    (intel_crtc->config.pipe_src_h - 1));
5425 }
5426
5427 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5428                                    struct intel_crtc_config *pipe_config)
5429 {
5430         struct drm_device *dev = crtc->base.dev;
5431         struct drm_i915_private *dev_priv = dev->dev_private;
5432         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5433         uint32_t tmp;
5434
5435         tmp = I915_READ(HTOTAL(cpu_transcoder));
5436         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5437         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5438         tmp = I915_READ(HBLANK(cpu_transcoder));
5439         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5440         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5441         tmp = I915_READ(HSYNC(cpu_transcoder));
5442         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5443         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5444
5445         tmp = I915_READ(VTOTAL(cpu_transcoder));
5446         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5447         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5448         tmp = I915_READ(VBLANK(cpu_transcoder));
5449         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5450         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5451         tmp = I915_READ(VSYNC(cpu_transcoder));
5452         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5453         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5454
5455         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5456                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5457                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5458                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5459         }
5460
5461         tmp = I915_READ(PIPESRC(crtc->pipe));
5462         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5463         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5464
5465         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5466         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5467 }
5468
5469 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5470                                  struct intel_crtc_config *pipe_config)
5471 {
5472         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5473         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5474         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5475         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5476
5477         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5478         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5479         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5480         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5481
5482         mode->flags = pipe_config->adjusted_mode.flags;
5483
5484         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5485         mode->flags |= pipe_config->adjusted_mode.flags;
5486 }
5487
5488 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5489 {
5490         struct drm_device *dev = intel_crtc->base.dev;
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         uint32_t pipeconf;
5493
5494         pipeconf = 0;
5495
5496         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5497             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5498                 pipeconf |= PIPECONF_ENABLE;
5499
5500         if (intel_crtc->config.double_wide)
5501                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5502
5503         /* only g4x and later have fancy bpc/dither controls */
5504         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5505                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5506                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5507                         pipeconf |= PIPECONF_DITHER_EN |
5508                                     PIPECONF_DITHER_TYPE_SP;
5509
5510                 switch (intel_crtc->config.pipe_bpp) {
5511                 case 18:
5512                         pipeconf |= PIPECONF_6BPC;
5513                         break;
5514                 case 24:
5515                         pipeconf |= PIPECONF_8BPC;
5516                         break;
5517                 case 30:
5518                         pipeconf |= PIPECONF_10BPC;
5519                         break;
5520                 default:
5521                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5522                         BUG();
5523                 }
5524         }
5525
5526         if (HAS_PIPE_CXSR(dev)) {
5527                 if (intel_crtc->lowfreq_avail) {
5528                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5529                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5530                 } else {
5531                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5532                 }
5533         }
5534
5535         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5536                 if (INTEL_INFO(dev)->gen < 4 ||
5537                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5538                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5539                 else
5540                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5541         } else
5542                 pipeconf |= PIPECONF_PROGRESSIVE;
5543
5544         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5545                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5546
5547         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5548         POSTING_READ(PIPECONF(intel_crtc->pipe));
5549 }
5550
5551 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5552                               int x, int y,
5553                               struct drm_framebuffer *fb)
5554 {
5555         struct drm_device *dev = crtc->dev;
5556         struct drm_i915_private *dev_priv = dev->dev_private;
5557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558         int pipe = intel_crtc->pipe;
5559         int plane = intel_crtc->plane;
5560         int refclk, num_connectors = 0;
5561         intel_clock_t clock, reduced_clock;
5562         u32 dspcntr;
5563         bool ok, has_reduced_clock = false;
5564         bool is_lvds = false, is_dsi = false;
5565         struct intel_encoder *encoder;
5566         const intel_limit_t *limit;
5567         int ret;
5568
5569         for_each_encoder_on_crtc(dev, crtc, encoder) {
5570                 switch (encoder->type) {
5571                 case INTEL_OUTPUT_LVDS:
5572                         is_lvds = true;
5573                         break;
5574                 case INTEL_OUTPUT_DSI:
5575                         is_dsi = true;
5576                         break;
5577                 }
5578
5579                 num_connectors++;
5580         }
5581
5582         if (is_dsi)
5583                 goto skip_dpll;
5584
5585         if (!intel_crtc->config.clock_set) {
5586                 refclk = i9xx_get_refclk(crtc, num_connectors);
5587
5588                 /*
5589                  * Returns a set of divisors for the desired target clock with
5590                  * the given refclk, or FALSE.  The returned values represent
5591                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5592                  * 2) / p1 / p2.
5593                  */
5594                 limit = intel_limit(crtc, refclk);
5595                 ok = dev_priv->display.find_dpll(limit, crtc,
5596                                                  intel_crtc->config.port_clock,
5597                                                  refclk, NULL, &clock);
5598                 if (!ok) {
5599                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5600                         return -EINVAL;
5601                 }
5602
5603                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5604                         /*
5605                          * Ensure we match the reduced clock's P to the target
5606                          * clock.  If the clocks don't match, we can't switch
5607                          * the display clock by using the FP0/FP1. In such case
5608                          * we will disable the LVDS downclock feature.
5609                          */
5610                         has_reduced_clock =
5611                                 dev_priv->display.find_dpll(limit, crtc,
5612                                                             dev_priv->lvds_downclock,
5613                                                             refclk, &clock,
5614                                                             &reduced_clock);
5615                 }
5616                 /* Compat-code for transition, will disappear. */
5617                 intel_crtc->config.dpll.n = clock.n;
5618                 intel_crtc->config.dpll.m1 = clock.m1;
5619                 intel_crtc->config.dpll.m2 = clock.m2;
5620                 intel_crtc->config.dpll.p1 = clock.p1;
5621                 intel_crtc->config.dpll.p2 = clock.p2;
5622         }
5623
5624         if (IS_GEN2(dev)) {
5625                 i8xx_update_pll(intel_crtc,
5626                                 has_reduced_clock ? &reduced_clock : NULL,
5627                                 num_connectors);
5628         } else if (IS_VALLEYVIEW(dev)) {
5629                 vlv_update_pll(intel_crtc);
5630         } else {
5631                 i9xx_update_pll(intel_crtc,
5632                                 has_reduced_clock ? &reduced_clock : NULL,
5633                                 num_connectors);
5634         }
5635
5636 skip_dpll:
5637         /* Set up the display plane register */
5638         dspcntr = DISPPLANE_GAMMA_ENABLE;
5639
5640         if (!IS_VALLEYVIEW(dev)) {
5641                 if (pipe == 0)
5642                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5643                 else
5644                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5645         }
5646
5647         if (intel_crtc->config.has_dp_encoder)
5648                 intel_dp_set_m_n(intel_crtc);
5649
5650         intel_set_pipe_timings(intel_crtc);
5651
5652         /* pipesrc and dspsize control the size that is scaled from,
5653          * which should always be the user's requested size.
5654          */
5655         I915_WRITE(DSPSIZE(plane),
5656                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5657                    (intel_crtc->config.pipe_src_w - 1));
5658         I915_WRITE(DSPPOS(plane), 0);
5659
5660         i9xx_set_pipeconf(intel_crtc);
5661
5662         I915_WRITE(DSPCNTR(plane), dspcntr);
5663         POSTING_READ(DSPCNTR(plane));
5664
5665         ret = intel_pipe_set_base(crtc, x, y, fb);
5666
5667         return ret;
5668 }
5669
5670 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5671                                  struct intel_crtc_config *pipe_config)
5672 {
5673         struct drm_device *dev = crtc->base.dev;
5674         struct drm_i915_private *dev_priv = dev->dev_private;
5675         uint32_t tmp;
5676
5677         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5678                 return;
5679
5680         tmp = I915_READ(PFIT_CONTROL);
5681         if (!(tmp & PFIT_ENABLE))
5682                 return;
5683
5684         /* Check whether the pfit is attached to our pipe. */
5685         if (INTEL_INFO(dev)->gen < 4) {
5686                 if (crtc->pipe != PIPE_B)
5687                         return;
5688         } else {
5689                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5690                         return;
5691         }
5692
5693         pipe_config->gmch_pfit.control = tmp;
5694         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5695         if (INTEL_INFO(dev)->gen < 5)
5696                 pipe_config->gmch_pfit.lvds_border_bits =
5697                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5698 }
5699
5700 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5701                                struct intel_crtc_config *pipe_config)
5702 {
5703         struct drm_device *dev = crtc->base.dev;
5704         struct drm_i915_private *dev_priv = dev->dev_private;
5705         int pipe = pipe_config->cpu_transcoder;
5706         intel_clock_t clock;
5707         u32 mdiv;
5708         int refclk = 100000;
5709
5710         mutex_lock(&dev_priv->dpio_lock);
5711         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5712         mutex_unlock(&dev_priv->dpio_lock);
5713
5714         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5715         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5716         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5717         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5718         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5719
5720         vlv_clock(refclk, &clock);
5721
5722         /* clock.dot is the fast clock */
5723         pipe_config->port_clock = clock.dot / 5;
5724 }
5725
5726 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5727                                   struct intel_plane_config *plane_config)
5728 {
5729         struct drm_device *dev = crtc->base.dev;
5730         struct drm_i915_private *dev_priv = dev->dev_private;
5731         u32 val, base, offset;
5732         int pipe = crtc->pipe, plane = crtc->plane;
5733         int fourcc, pixel_format;
5734         int aligned_height;
5735
5736         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5737         if (!crtc->base.primary->fb) {
5738                 DRM_DEBUG_KMS("failed to alloc fb\n");
5739                 return;
5740         }
5741
5742         val = I915_READ(DSPCNTR(plane));
5743
5744         if (INTEL_INFO(dev)->gen >= 4)
5745                 if (val & DISPPLANE_TILED)
5746                         plane_config->tiled = true;
5747
5748         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5749         fourcc = intel_format_to_fourcc(pixel_format);
5750         crtc->base.primary->fb->pixel_format = fourcc;
5751         crtc->base.primary->fb->bits_per_pixel =
5752                 drm_format_plane_cpp(fourcc, 0) * 8;
5753
5754         if (INTEL_INFO(dev)->gen >= 4) {
5755                 if (plane_config->tiled)
5756                         offset = I915_READ(DSPTILEOFF(plane));
5757                 else
5758                         offset = I915_READ(DSPLINOFF(plane));
5759                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5760         } else {
5761                 base = I915_READ(DSPADDR(plane));
5762         }
5763         plane_config->base = base;
5764
5765         val = I915_READ(PIPESRC(pipe));
5766         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5767         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5768
5769         val = I915_READ(DSPSTRIDE(pipe));
5770         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5771
5772         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5773                                             plane_config->tiled);
5774
5775         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5776                                    aligned_height, PAGE_SIZE);
5777
5778         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5779                       pipe, plane, crtc->base.primary->fb->width,
5780                       crtc->base.primary->fb->height,
5781                       crtc->base.primary->fb->bits_per_pixel, base,
5782                       crtc->base.primary->fb->pitches[0],
5783                       plane_config->size);
5784
5785 }
5786
5787 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5788                                  struct intel_crtc_config *pipe_config)
5789 {
5790         struct drm_device *dev = crtc->base.dev;
5791         struct drm_i915_private *dev_priv = dev->dev_private;
5792         uint32_t tmp;
5793
5794         if (!intel_display_power_enabled(dev_priv,
5795                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5796                 return false;
5797
5798         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5799         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5800
5801         tmp = I915_READ(PIPECONF(crtc->pipe));
5802         if (!(tmp & PIPECONF_ENABLE))
5803                 return false;
5804
5805         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5806                 switch (tmp & PIPECONF_BPC_MASK) {
5807                 case PIPECONF_6BPC:
5808                         pipe_config->pipe_bpp = 18;
5809                         break;
5810                 case PIPECONF_8BPC:
5811                         pipe_config->pipe_bpp = 24;
5812                         break;
5813                 case PIPECONF_10BPC:
5814                         pipe_config->pipe_bpp = 30;
5815                         break;
5816                 default:
5817                         break;
5818                 }
5819         }
5820
5821         if (INTEL_INFO(dev)->gen < 4)
5822                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5823
5824         intel_get_pipe_timings(crtc, pipe_config);
5825
5826         i9xx_get_pfit_config(crtc, pipe_config);
5827
5828         if (INTEL_INFO(dev)->gen >= 4) {
5829                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5830                 pipe_config->pixel_multiplier =
5831                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5832                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5833                 pipe_config->dpll_hw_state.dpll_md = tmp;
5834         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5835                 tmp = I915_READ(DPLL(crtc->pipe));
5836                 pipe_config->pixel_multiplier =
5837                         ((tmp & SDVO_MULTIPLIER_MASK)
5838                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5839         } else {
5840                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5841                  * port and will be fixed up in the encoder->get_config
5842                  * function. */
5843                 pipe_config->pixel_multiplier = 1;
5844         }
5845         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5846         if (!IS_VALLEYVIEW(dev)) {
5847                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5848                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5849         } else {
5850                 /* Mask out read-only status bits. */
5851                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5852                                                      DPLL_PORTC_READY_MASK |
5853                                                      DPLL_PORTB_READY_MASK);
5854         }
5855
5856         if (IS_VALLEYVIEW(dev))
5857                 vlv_crtc_clock_get(crtc, pipe_config);
5858         else
5859                 i9xx_crtc_clock_get(crtc, pipe_config);
5860
5861         return true;
5862 }
5863
5864 static void ironlake_init_pch_refclk(struct drm_device *dev)
5865 {
5866         struct drm_i915_private *dev_priv = dev->dev_private;
5867         struct drm_mode_config *mode_config = &dev->mode_config;
5868         struct intel_encoder *encoder;
5869         u32 val, final;
5870         bool has_lvds = false;
5871         bool has_cpu_edp = false;
5872         bool has_panel = false;
5873         bool has_ck505 = false;
5874         bool can_ssc = false;
5875
5876         /* We need to take the global config into account */
5877         list_for_each_entry(encoder, &mode_config->encoder_list,
5878                             base.head) {
5879                 switch (encoder->type) {
5880                 case INTEL_OUTPUT_LVDS:
5881                         has_panel = true;
5882                         has_lvds = true;
5883                         break;
5884                 case INTEL_OUTPUT_EDP:
5885                         has_panel = true;
5886                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5887                                 has_cpu_edp = true;
5888                         break;
5889                 }
5890         }
5891
5892         if (HAS_PCH_IBX(dev)) {
5893                 has_ck505 = dev_priv->vbt.display_clock_mode;
5894                 can_ssc = has_ck505;
5895         } else {
5896                 has_ck505 = false;
5897                 can_ssc = true;
5898         }
5899
5900         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5901                       has_panel, has_lvds, has_ck505);
5902
5903         /* Ironlake: try to setup display ref clock before DPLL
5904          * enabling. This is only under driver's control after
5905          * PCH B stepping, previous chipset stepping should be
5906          * ignoring this setting.
5907          */
5908         val = I915_READ(PCH_DREF_CONTROL);
5909
5910         /* As we must carefully and slowly disable/enable each source in turn,
5911          * compute the final state we want first and check if we need to
5912          * make any changes at all.
5913          */
5914         final = val;
5915         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5916         if (has_ck505)
5917                 final |= DREF_NONSPREAD_CK505_ENABLE;
5918         else
5919                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5920
5921         final &= ~DREF_SSC_SOURCE_MASK;
5922         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5923         final &= ~DREF_SSC1_ENABLE;
5924
5925         if (has_panel) {
5926                 final |= DREF_SSC_SOURCE_ENABLE;
5927
5928                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5929                         final |= DREF_SSC1_ENABLE;
5930
5931                 if (has_cpu_edp) {
5932                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5933                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5934                         else
5935                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5936                 } else
5937                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5938         } else {
5939                 final |= DREF_SSC_SOURCE_DISABLE;
5940                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5941         }
5942
5943         if (final == val)
5944                 return;
5945
5946         /* Always enable nonspread source */
5947         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5948
5949         if (has_ck505)
5950                 val |= DREF_NONSPREAD_CK505_ENABLE;
5951         else
5952                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5953
5954         if (has_panel) {
5955                 val &= ~DREF_SSC_SOURCE_MASK;
5956                 val |= DREF_SSC_SOURCE_ENABLE;
5957
5958                 /* SSC must be turned on before enabling the CPU output  */
5959                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5960                         DRM_DEBUG_KMS("Using SSC on panel\n");
5961                         val |= DREF_SSC1_ENABLE;
5962                 } else
5963                         val &= ~DREF_SSC1_ENABLE;
5964
5965                 /* Get SSC going before enabling the outputs */
5966                 I915_WRITE(PCH_DREF_CONTROL, val);
5967                 POSTING_READ(PCH_DREF_CONTROL);
5968                 udelay(200);
5969
5970                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5971
5972                 /* Enable CPU source on CPU attached eDP */
5973                 if (has_cpu_edp) {
5974                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5975                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5976                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5977                         }
5978                         else
5979                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5980                 } else
5981                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5982
5983                 I915_WRITE(PCH_DREF_CONTROL, val);
5984                 POSTING_READ(PCH_DREF_CONTROL);
5985                 udelay(200);
5986         } else {
5987                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5988
5989                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5990
5991                 /* Turn off CPU output */
5992                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5993
5994                 I915_WRITE(PCH_DREF_CONTROL, val);
5995                 POSTING_READ(PCH_DREF_CONTROL);
5996                 udelay(200);
5997
5998                 /* Turn off the SSC source */
5999                 val &= ~DREF_SSC_SOURCE_MASK;
6000                 val |= DREF_SSC_SOURCE_DISABLE;
6001
6002                 /* Turn off SSC1 */
6003                 val &= ~DREF_SSC1_ENABLE;
6004
6005                 I915_WRITE(PCH_DREF_CONTROL, val);
6006                 POSTING_READ(PCH_DREF_CONTROL);
6007                 udelay(200);
6008         }
6009
6010         BUG_ON(val != final);
6011 }
6012
6013 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6014 {
6015         uint32_t tmp;
6016
6017         tmp = I915_READ(SOUTH_CHICKEN2);
6018         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6019         I915_WRITE(SOUTH_CHICKEN2, tmp);
6020
6021         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6022                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6023                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6024
6025         tmp = I915_READ(SOUTH_CHICKEN2);
6026         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6027         I915_WRITE(SOUTH_CHICKEN2, tmp);
6028
6029         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6030                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6031                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6032 }
6033
6034 /* WaMPhyProgramming:hsw */
6035 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6036 {
6037         uint32_t tmp;
6038
6039         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6040         tmp &= ~(0xFF << 24);
6041         tmp |= (0x12 << 24);
6042         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6043
6044         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6045         tmp |= (1 << 11);
6046         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6047
6048         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6049         tmp |= (1 << 11);
6050         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6051
6052         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6053         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6054         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6055
6056         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6057         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6058         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6059
6060         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6061         tmp &= ~(7 << 13);
6062         tmp |= (5 << 13);
6063         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6064
6065         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6066         tmp &= ~(7 << 13);
6067         tmp |= (5 << 13);
6068         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6069
6070         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6071         tmp &= ~0xFF;
6072         tmp |= 0x1C;
6073         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6074
6075         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6076         tmp &= ~0xFF;
6077         tmp |= 0x1C;
6078         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6079
6080         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6081         tmp &= ~(0xFF << 16);
6082         tmp |= (0x1C << 16);
6083         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6084
6085         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6086         tmp &= ~(0xFF << 16);
6087         tmp |= (0x1C << 16);
6088         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6089
6090         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6091         tmp |= (1 << 27);
6092         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6093
6094         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6095         tmp |= (1 << 27);
6096         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6097
6098         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6099         tmp &= ~(0xF << 28);
6100         tmp |= (4 << 28);
6101         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6102
6103         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6104         tmp &= ~(0xF << 28);
6105         tmp |= (4 << 28);
6106         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6107 }
6108
6109 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6110  * Programming" based on the parameters passed:
6111  * - Sequence to enable CLKOUT_DP
6112  * - Sequence to enable CLKOUT_DP without spread
6113  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6114  */
6115 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6116                                  bool with_fdi)
6117 {
6118         struct drm_i915_private *dev_priv = dev->dev_private;
6119         uint32_t reg, tmp;
6120
6121         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6122                 with_spread = true;
6123         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6124                  with_fdi, "LP PCH doesn't have FDI\n"))
6125                 with_fdi = false;
6126
6127         mutex_lock(&dev_priv->dpio_lock);
6128
6129         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6130         tmp &= ~SBI_SSCCTL_DISABLE;
6131         tmp |= SBI_SSCCTL_PATHALT;
6132         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6133
6134         udelay(24);
6135
6136         if (with_spread) {
6137                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6138                 tmp &= ~SBI_SSCCTL_PATHALT;
6139                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6140
6141                 if (with_fdi) {
6142                         lpt_reset_fdi_mphy(dev_priv);
6143                         lpt_program_fdi_mphy(dev_priv);
6144                 }
6145         }
6146
6147         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6148                SBI_GEN0 : SBI_DBUFF0;
6149         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6150         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6151         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6152
6153         mutex_unlock(&dev_priv->dpio_lock);
6154 }
6155
6156 /* Sequence to disable CLKOUT_DP */
6157 static void lpt_disable_clkout_dp(struct drm_device *dev)
6158 {
6159         struct drm_i915_private *dev_priv = dev->dev_private;
6160         uint32_t reg, tmp;
6161
6162         mutex_lock(&dev_priv->dpio_lock);
6163
6164         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6165                SBI_GEN0 : SBI_DBUFF0;
6166         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6167         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6168         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6169
6170         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6171         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6172                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6173                         tmp |= SBI_SSCCTL_PATHALT;
6174                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6175                         udelay(32);
6176                 }
6177                 tmp |= SBI_SSCCTL_DISABLE;
6178                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6179         }
6180
6181         mutex_unlock(&dev_priv->dpio_lock);
6182 }
6183
6184 static void lpt_init_pch_refclk(struct drm_device *dev)
6185 {
6186         struct drm_mode_config *mode_config = &dev->mode_config;
6187         struct intel_encoder *encoder;
6188         bool has_vga = false;
6189
6190         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6191                 switch (encoder->type) {
6192                 case INTEL_OUTPUT_ANALOG:
6193                         has_vga = true;
6194                         break;
6195                 }
6196         }
6197
6198         if (has_vga)
6199                 lpt_enable_clkout_dp(dev, true, true);
6200         else
6201                 lpt_disable_clkout_dp(dev);
6202 }
6203
6204 /*
6205  * Initialize reference clocks when the driver loads
6206  */
6207 void intel_init_pch_refclk(struct drm_device *dev)
6208 {
6209         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6210                 ironlake_init_pch_refclk(dev);
6211         else if (HAS_PCH_LPT(dev))
6212                 lpt_init_pch_refclk(dev);
6213 }
6214
6215 static int ironlake_get_refclk(struct drm_crtc *crtc)
6216 {
6217         struct drm_device *dev = crtc->dev;
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219         struct intel_encoder *encoder;
6220         int num_connectors = 0;
6221         bool is_lvds = false;
6222
6223         for_each_encoder_on_crtc(dev, crtc, encoder) {
6224                 switch (encoder->type) {
6225                 case INTEL_OUTPUT_LVDS:
6226                         is_lvds = true;
6227                         break;
6228                 }
6229                 num_connectors++;
6230         }
6231
6232         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6233                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6234                               dev_priv->vbt.lvds_ssc_freq);
6235                 return dev_priv->vbt.lvds_ssc_freq;
6236         }
6237
6238         return 120000;
6239 }
6240
6241 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6242 {
6243         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245         int pipe = intel_crtc->pipe;
6246         uint32_t val;
6247
6248         val = 0;
6249
6250         switch (intel_crtc->config.pipe_bpp) {
6251         case 18:
6252                 val |= PIPECONF_6BPC;
6253                 break;
6254         case 24:
6255                 val |= PIPECONF_8BPC;
6256                 break;
6257         case 30:
6258                 val |= PIPECONF_10BPC;
6259                 break;
6260         case 36:
6261                 val |= PIPECONF_12BPC;
6262                 break;
6263         default:
6264                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6265                 BUG();
6266         }
6267
6268         if (intel_crtc->config.dither)
6269                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6270
6271         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6272                 val |= PIPECONF_INTERLACED_ILK;
6273         else
6274                 val |= PIPECONF_PROGRESSIVE;
6275
6276         if (intel_crtc->config.limited_color_range)
6277                 val |= PIPECONF_COLOR_RANGE_SELECT;
6278
6279         I915_WRITE(PIPECONF(pipe), val);
6280         POSTING_READ(PIPECONF(pipe));
6281 }
6282
6283 /*
6284  * Set up the pipe CSC unit.
6285  *
6286  * Currently only full range RGB to limited range RGB conversion
6287  * is supported, but eventually this should handle various
6288  * RGB<->YCbCr scenarios as well.
6289  */
6290 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6291 {
6292         struct drm_device *dev = crtc->dev;
6293         struct drm_i915_private *dev_priv = dev->dev_private;
6294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295         int pipe = intel_crtc->pipe;
6296         uint16_t coeff = 0x7800; /* 1.0 */
6297
6298         /*
6299          * TODO: Check what kind of values actually come out of the pipe
6300          * with these coeff/postoff values and adjust to get the best
6301          * accuracy. Perhaps we even need to take the bpc value into
6302          * consideration.
6303          */
6304
6305         if (intel_crtc->config.limited_color_range)
6306                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6307
6308         /*
6309          * GY/GU and RY/RU should be the other way around according
6310          * to BSpec, but reality doesn't agree. Just set them up in
6311          * a way that results in the correct picture.
6312          */
6313         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6314         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6315
6316         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6317         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6318
6319         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6320         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6321
6322         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6323         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6324         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6325
6326         if (INTEL_INFO(dev)->gen > 6) {
6327                 uint16_t postoff = 0;
6328
6329                 if (intel_crtc->config.limited_color_range)
6330                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6331
6332                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6333                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6334                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6335
6336                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6337         } else {
6338                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6339
6340                 if (intel_crtc->config.limited_color_range)
6341                         mode |= CSC_BLACK_SCREEN_OFFSET;
6342
6343                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6344         }
6345 }
6346
6347 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6348 {
6349         struct drm_device *dev = crtc->dev;
6350         struct drm_i915_private *dev_priv = dev->dev_private;
6351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352         enum pipe pipe = intel_crtc->pipe;
6353         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6354         uint32_t val;
6355
6356         val = 0;
6357
6358         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6359                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6360
6361         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6362                 val |= PIPECONF_INTERLACED_ILK;
6363         else
6364                 val |= PIPECONF_PROGRESSIVE;
6365
6366         I915_WRITE(PIPECONF(cpu_transcoder), val);
6367         POSTING_READ(PIPECONF(cpu_transcoder));
6368
6369         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6370         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6371
6372         if (IS_BROADWELL(dev)) {
6373                 val = 0;
6374
6375                 switch (intel_crtc->config.pipe_bpp) {
6376                 case 18:
6377                         val |= PIPEMISC_DITHER_6_BPC;
6378                         break;
6379                 case 24:
6380                         val |= PIPEMISC_DITHER_8_BPC;
6381                         break;
6382                 case 30:
6383                         val |= PIPEMISC_DITHER_10_BPC;
6384                         break;
6385                 case 36:
6386                         val |= PIPEMISC_DITHER_12_BPC;
6387                         break;
6388                 default:
6389                         /* Case prevented by pipe_config_set_bpp. */
6390                         BUG();
6391                 }
6392
6393                 if (intel_crtc->config.dither)
6394                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6395
6396                 I915_WRITE(PIPEMISC(pipe), val);
6397         }
6398 }
6399
6400 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6401                                     intel_clock_t *clock,
6402                                     bool *has_reduced_clock,
6403                                     intel_clock_t *reduced_clock)
6404 {
6405         struct drm_device *dev = crtc->dev;
6406         struct drm_i915_private *dev_priv = dev->dev_private;
6407         struct intel_encoder *intel_encoder;
6408         int refclk;
6409         const intel_limit_t *limit;
6410         bool ret, is_lvds = false;
6411
6412         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6413                 switch (intel_encoder->type) {
6414                 case INTEL_OUTPUT_LVDS:
6415                         is_lvds = true;
6416                         break;
6417                 }
6418         }
6419
6420         refclk = ironlake_get_refclk(crtc);
6421
6422         /*
6423          * Returns a set of divisors for the desired target clock with the given
6424          * refclk, or FALSE.  The returned values represent the clock equation:
6425          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6426          */
6427         limit = intel_limit(crtc, refclk);
6428         ret = dev_priv->display.find_dpll(limit, crtc,
6429                                           to_intel_crtc(crtc)->config.port_clock,
6430                                           refclk, NULL, clock);
6431         if (!ret)
6432                 return false;
6433
6434         if (is_lvds && dev_priv->lvds_downclock_avail) {
6435                 /*
6436                  * Ensure we match the reduced clock's P to the target clock.
6437                  * If the clocks don't match, we can't switch the display clock
6438                  * by using the FP0/FP1. In such case we will disable the LVDS
6439                  * downclock feature.
6440                 */
6441                 *has_reduced_clock =
6442                         dev_priv->display.find_dpll(limit, crtc,
6443                                                     dev_priv->lvds_downclock,
6444                                                     refclk, clock,
6445                                                     reduced_clock);
6446         }
6447
6448         return true;
6449 }
6450
6451 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6452 {
6453         /*
6454          * Account for spread spectrum to avoid
6455          * oversubscribing the link. Max center spread
6456          * is 2.5%; use 5% for safety's sake.
6457          */
6458         u32 bps = target_clock * bpp * 21 / 20;
6459         return DIV_ROUND_UP(bps, link_bw * 8);
6460 }
6461
6462 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6463 {
6464         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6465 }
6466
6467 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6468                                       u32 *fp,
6469                                       intel_clock_t *reduced_clock, u32 *fp2)
6470 {
6471         struct drm_crtc *crtc = &intel_crtc->base;
6472         struct drm_device *dev = crtc->dev;
6473         struct drm_i915_private *dev_priv = dev->dev_private;
6474         struct intel_encoder *intel_encoder;
6475         uint32_t dpll;
6476         int factor, num_connectors = 0;
6477         bool is_lvds = false, is_sdvo = false;
6478
6479         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6480                 switch (intel_encoder->type) {
6481                 case INTEL_OUTPUT_LVDS:
6482                         is_lvds = true;
6483                         break;
6484                 case INTEL_OUTPUT_SDVO:
6485                 case INTEL_OUTPUT_HDMI:
6486                         is_sdvo = true;
6487                         break;
6488                 }
6489
6490                 num_connectors++;
6491         }
6492
6493         /* Enable autotuning of the PLL clock (if permissible) */
6494         factor = 21;
6495         if (is_lvds) {
6496                 if ((intel_panel_use_ssc(dev_priv) &&
6497                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6498                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6499                         factor = 25;
6500         } else if (intel_crtc->config.sdvo_tv_clock)
6501                 factor = 20;
6502
6503         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6504                 *fp |= FP_CB_TUNE;
6505
6506         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6507                 *fp2 |= FP_CB_TUNE;
6508
6509         dpll = 0;
6510
6511         if (is_lvds)
6512                 dpll |= DPLLB_MODE_LVDS;
6513         else
6514                 dpll |= DPLLB_MODE_DAC_SERIAL;
6515
6516         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6517                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6518
6519         if (is_sdvo)
6520                 dpll |= DPLL_SDVO_HIGH_SPEED;
6521         if (intel_crtc->config.has_dp_encoder)
6522                 dpll |= DPLL_SDVO_HIGH_SPEED;
6523
6524         /* compute bitmask from p1 value */
6525         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6526         /* also FPA1 */
6527         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6528
6529         switch (intel_crtc->config.dpll.p2) {
6530         case 5:
6531                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6532                 break;
6533         case 7:
6534                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6535                 break;
6536         case 10:
6537                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6538                 break;
6539         case 14:
6540                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6541                 break;
6542         }
6543
6544         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6545                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6546         else
6547                 dpll |= PLL_REF_INPUT_DREFCLK;
6548
6549         return dpll | DPLL_VCO_ENABLE;
6550 }
6551
6552 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6553                                   int x, int y,
6554                                   struct drm_framebuffer *fb)
6555 {
6556         struct drm_device *dev = crtc->dev;
6557         struct drm_i915_private *dev_priv = dev->dev_private;
6558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559         int pipe = intel_crtc->pipe;
6560         int plane = intel_crtc->plane;
6561         int num_connectors = 0;
6562         intel_clock_t clock, reduced_clock;
6563         u32 dpll = 0, fp = 0, fp2 = 0;
6564         bool ok, has_reduced_clock = false;
6565         bool is_lvds = false;
6566         struct intel_encoder *encoder;
6567         struct intel_shared_dpll *pll;
6568         int ret;
6569
6570         for_each_encoder_on_crtc(dev, crtc, encoder) {
6571                 switch (encoder->type) {
6572                 case INTEL_OUTPUT_LVDS:
6573                         is_lvds = true;
6574                         break;
6575                 }
6576
6577                 num_connectors++;
6578         }
6579
6580         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6581              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6582
6583         ok = ironlake_compute_clocks(crtc, &clock,
6584                                      &has_reduced_clock, &reduced_clock);
6585         if (!ok && !intel_crtc->config.clock_set) {
6586                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6587                 return -EINVAL;
6588         }
6589         /* Compat-code for transition, will disappear. */
6590         if (!intel_crtc->config.clock_set) {
6591                 intel_crtc->config.dpll.n = clock.n;
6592                 intel_crtc->config.dpll.m1 = clock.m1;
6593                 intel_crtc->config.dpll.m2 = clock.m2;
6594                 intel_crtc->config.dpll.p1 = clock.p1;
6595                 intel_crtc->config.dpll.p2 = clock.p2;
6596         }
6597
6598         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6599         if (intel_crtc->config.has_pch_encoder) {
6600                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6601                 if (has_reduced_clock)
6602                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6603
6604                 dpll = ironlake_compute_dpll(intel_crtc,
6605                                              &fp, &reduced_clock,
6606                                              has_reduced_clock ? &fp2 : NULL);
6607
6608                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6609                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6610                 if (has_reduced_clock)
6611                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6612                 else
6613                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6614
6615                 pll = intel_get_shared_dpll(intel_crtc);
6616                 if (pll == NULL) {
6617                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6618                                          pipe_name(pipe));
6619                         return -EINVAL;
6620                 }
6621         } else
6622                 intel_put_shared_dpll(intel_crtc);
6623
6624         if (intel_crtc->config.has_dp_encoder)
6625                 intel_dp_set_m_n(intel_crtc);
6626
6627         if (is_lvds && has_reduced_clock && i915.powersave)
6628                 intel_crtc->lowfreq_avail = true;
6629         else
6630                 intel_crtc->lowfreq_avail = false;
6631
6632         intel_set_pipe_timings(intel_crtc);
6633
6634         if (intel_crtc->config.has_pch_encoder) {
6635                 intel_cpu_transcoder_set_m_n(intel_crtc,
6636                                              &intel_crtc->config.fdi_m_n);
6637         }
6638
6639         ironlake_set_pipeconf(crtc);
6640
6641         /* Set up the display plane register */
6642         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6643         POSTING_READ(DSPCNTR(plane));
6644
6645         ret = intel_pipe_set_base(crtc, x, y, fb);
6646
6647         return ret;
6648 }
6649
6650 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6651                                          struct intel_link_m_n *m_n)
6652 {
6653         struct drm_device *dev = crtc->base.dev;
6654         struct drm_i915_private *dev_priv = dev->dev_private;
6655         enum pipe pipe = crtc->pipe;
6656
6657         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6658         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6659         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6660                 & ~TU_SIZE_MASK;
6661         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6662         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6663                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6664 }
6665
6666 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6667                                          enum transcoder transcoder,
6668                                          struct intel_link_m_n *m_n)
6669 {
6670         struct drm_device *dev = crtc->base.dev;
6671         struct drm_i915_private *dev_priv = dev->dev_private;
6672         enum pipe pipe = crtc->pipe;
6673
6674         if (INTEL_INFO(dev)->gen >= 5) {
6675                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6676                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6677                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6678                         & ~TU_SIZE_MASK;
6679                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6680                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6681                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6682         } else {
6683                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6684                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6685                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6686                         & ~TU_SIZE_MASK;
6687                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6688                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6689                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6690         }
6691 }
6692
6693 void intel_dp_get_m_n(struct intel_crtc *crtc,
6694                       struct intel_crtc_config *pipe_config)
6695 {
6696         if (crtc->config.has_pch_encoder)
6697                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6698         else
6699                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6700                                              &pipe_config->dp_m_n);
6701 }
6702
6703 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6704                                         struct intel_crtc_config *pipe_config)
6705 {
6706         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6707                                      &pipe_config->fdi_m_n);
6708 }
6709
6710 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6711                                      struct intel_crtc_config *pipe_config)
6712 {
6713         struct drm_device *dev = crtc->base.dev;
6714         struct drm_i915_private *dev_priv = dev->dev_private;
6715         uint32_t tmp;
6716
6717         tmp = I915_READ(PF_CTL(crtc->pipe));
6718
6719         if (tmp & PF_ENABLE) {
6720                 pipe_config->pch_pfit.enabled = true;
6721                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6722                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6723
6724                 /* We currently do not free assignements of panel fitters on
6725                  * ivb/hsw (since we don't use the higher upscaling modes which
6726                  * differentiates them) so just WARN about this case for now. */
6727                 if (IS_GEN7(dev)) {
6728                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6729                                 PF_PIPE_SEL_IVB(crtc->pipe));
6730                 }
6731         }
6732 }
6733
6734 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6735                                       struct intel_plane_config *plane_config)
6736 {
6737         struct drm_device *dev = crtc->base.dev;
6738         struct drm_i915_private *dev_priv = dev->dev_private;
6739         u32 val, base, offset;
6740         int pipe = crtc->pipe, plane = crtc->plane;
6741         int fourcc, pixel_format;
6742         int aligned_height;
6743
6744         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6745         if (!crtc->base.primary->fb) {
6746                 DRM_DEBUG_KMS("failed to alloc fb\n");
6747                 return;
6748         }
6749
6750         val = I915_READ(DSPCNTR(plane));
6751
6752         if (INTEL_INFO(dev)->gen >= 4)
6753                 if (val & DISPPLANE_TILED)
6754                         plane_config->tiled = true;
6755
6756         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6757         fourcc = intel_format_to_fourcc(pixel_format);
6758         crtc->base.primary->fb->pixel_format = fourcc;
6759         crtc->base.primary->fb->bits_per_pixel =
6760                 drm_format_plane_cpp(fourcc, 0) * 8;
6761
6762         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6763         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6764                 offset = I915_READ(DSPOFFSET(plane));
6765         } else {
6766                 if (plane_config->tiled)
6767                         offset = I915_READ(DSPTILEOFF(plane));
6768                 else
6769                         offset = I915_READ(DSPLINOFF(plane));
6770         }
6771         plane_config->base = base;
6772
6773         val = I915_READ(PIPESRC(pipe));
6774         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6775         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6776
6777         val = I915_READ(DSPSTRIDE(pipe));
6778         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6779
6780         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6781                                             plane_config->tiled);
6782
6783         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6784                                    aligned_height, PAGE_SIZE);
6785
6786         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6787                       pipe, plane, crtc->base.primary->fb->width,
6788                       crtc->base.primary->fb->height,
6789                       crtc->base.primary->fb->bits_per_pixel, base,
6790                       crtc->base.primary->fb->pitches[0],
6791                       plane_config->size);
6792 }
6793
6794 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6795                                      struct intel_crtc_config *pipe_config)
6796 {
6797         struct drm_device *dev = crtc->base.dev;
6798         struct drm_i915_private *dev_priv = dev->dev_private;
6799         uint32_t tmp;
6800
6801         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6802         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6803
6804         tmp = I915_READ(PIPECONF(crtc->pipe));
6805         if (!(tmp & PIPECONF_ENABLE))
6806                 return false;
6807
6808         switch (tmp & PIPECONF_BPC_MASK) {
6809         case PIPECONF_6BPC:
6810                 pipe_config->pipe_bpp = 18;
6811                 break;
6812         case PIPECONF_8BPC:
6813                 pipe_config->pipe_bpp = 24;
6814                 break;
6815         case PIPECONF_10BPC:
6816                 pipe_config->pipe_bpp = 30;
6817                 break;
6818         case PIPECONF_12BPC:
6819                 pipe_config->pipe_bpp = 36;
6820                 break;
6821         default:
6822                 break;
6823         }
6824
6825         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6826                 struct intel_shared_dpll *pll;
6827
6828                 pipe_config->has_pch_encoder = true;
6829
6830                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6831                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6832                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6833
6834                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6835
6836                 if (HAS_PCH_IBX(dev_priv->dev)) {
6837                         pipe_config->shared_dpll =
6838                                 (enum intel_dpll_id) crtc->pipe;
6839                 } else {
6840                         tmp = I915_READ(PCH_DPLL_SEL);
6841                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6842                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6843                         else
6844                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6845                 }
6846
6847                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6848
6849                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6850                                            &pipe_config->dpll_hw_state));
6851
6852                 tmp = pipe_config->dpll_hw_state.dpll;
6853                 pipe_config->pixel_multiplier =
6854                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6855                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6856
6857                 ironlake_pch_clock_get(crtc, pipe_config);
6858         } else {
6859                 pipe_config->pixel_multiplier = 1;
6860         }
6861
6862         intel_get_pipe_timings(crtc, pipe_config);
6863
6864         ironlake_get_pfit_config(crtc, pipe_config);
6865
6866         return true;
6867 }
6868
6869 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6870 {
6871         struct drm_device *dev = dev_priv->dev;
6872         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6873         struct intel_crtc *crtc;
6874
6875         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6876                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6877                      pipe_name(crtc->pipe));
6878
6879         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6880         WARN(plls->spll_refcount, "SPLL enabled\n");
6881         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6882         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6883         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6884         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6885              "CPU PWM1 enabled\n");
6886         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6887              "CPU PWM2 enabled\n");
6888         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6889              "PCH PWM1 enabled\n");
6890         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6891              "Utility pin enabled\n");
6892         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6893
6894         /*
6895          * In theory we can still leave IRQs enabled, as long as only the HPD
6896          * interrupts remain enabled. We used to check for that, but since it's
6897          * gen-specific and since we only disable LCPLL after we fully disable
6898          * the interrupts, the check below should be enough.
6899          */
6900         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6901 }
6902
6903 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6904 {
6905         struct drm_device *dev = dev_priv->dev;
6906
6907         if (IS_HASWELL(dev)) {
6908                 mutex_lock(&dev_priv->rps.hw_lock);
6909                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6910                                             val))
6911                         DRM_ERROR("Failed to disable D_COMP\n");
6912                 mutex_unlock(&dev_priv->rps.hw_lock);
6913         } else {
6914                 I915_WRITE(D_COMP, val);
6915         }
6916         POSTING_READ(D_COMP);
6917 }
6918
6919 /*
6920  * This function implements pieces of two sequences from BSpec:
6921  * - Sequence for display software to disable LCPLL
6922  * - Sequence for display software to allow package C8+
6923  * The steps implemented here are just the steps that actually touch the LCPLL
6924  * register. Callers should take care of disabling all the display engine
6925  * functions, doing the mode unset, fixing interrupts, etc.
6926  */
6927 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6928                               bool switch_to_fclk, bool allow_power_down)
6929 {
6930         uint32_t val;
6931
6932         assert_can_disable_lcpll(dev_priv);
6933
6934         val = I915_READ(LCPLL_CTL);
6935
6936         if (switch_to_fclk) {
6937                 val |= LCPLL_CD_SOURCE_FCLK;
6938                 I915_WRITE(LCPLL_CTL, val);
6939
6940                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6941                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6942                         DRM_ERROR("Switching to FCLK failed\n");
6943
6944                 val = I915_READ(LCPLL_CTL);
6945         }
6946
6947         val |= LCPLL_PLL_DISABLE;
6948         I915_WRITE(LCPLL_CTL, val);
6949         POSTING_READ(LCPLL_CTL);
6950
6951         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6952                 DRM_ERROR("LCPLL still locked\n");
6953
6954         val = I915_READ(D_COMP);
6955         val |= D_COMP_COMP_DISABLE;
6956         hsw_write_dcomp(dev_priv, val);
6957         ndelay(100);
6958
6959         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6960                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6961
6962         if (allow_power_down) {
6963                 val = I915_READ(LCPLL_CTL);
6964                 val |= LCPLL_POWER_DOWN_ALLOW;
6965                 I915_WRITE(LCPLL_CTL, val);
6966                 POSTING_READ(LCPLL_CTL);
6967         }
6968 }
6969
6970 /*
6971  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6972  * source.
6973  */
6974 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6975 {
6976         uint32_t val;
6977         unsigned long irqflags;
6978
6979         val = I915_READ(LCPLL_CTL);
6980
6981         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6982                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6983                 return;
6984
6985         /*
6986          * Make sure we're not on PC8 state before disabling PC8, otherwise
6987          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6988          *
6989          * The other problem is that hsw_restore_lcpll() is called as part of
6990          * the runtime PM resume sequence, so we can't just call
6991          * gen6_gt_force_wake_get() because that function calls
6992          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6993          * while we are on the resume sequence. So to solve this problem we have
6994          * to call special forcewake code that doesn't touch runtime PM and
6995          * doesn't enable the forcewake delayed work.
6996          */
6997         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6998         if (dev_priv->uncore.forcewake_count++ == 0)
6999                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7000         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7001
7002         if (val & LCPLL_POWER_DOWN_ALLOW) {
7003                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7004                 I915_WRITE(LCPLL_CTL, val);
7005                 POSTING_READ(LCPLL_CTL);
7006         }
7007
7008         val = I915_READ(D_COMP);
7009         val |= D_COMP_COMP_FORCE;
7010         val &= ~D_COMP_COMP_DISABLE;
7011         hsw_write_dcomp(dev_priv, val);
7012
7013         val = I915_READ(LCPLL_CTL);
7014         val &= ~LCPLL_PLL_DISABLE;
7015         I915_WRITE(LCPLL_CTL, val);
7016
7017         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7018                 DRM_ERROR("LCPLL not locked yet\n");
7019
7020         if (val & LCPLL_CD_SOURCE_FCLK) {
7021                 val = I915_READ(LCPLL_CTL);
7022                 val &= ~LCPLL_CD_SOURCE_FCLK;
7023                 I915_WRITE(LCPLL_CTL, val);
7024
7025                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7026                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7027                         DRM_ERROR("Switching back to LCPLL failed\n");
7028         }
7029
7030         /* See the big comment above. */
7031         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7032         if (--dev_priv->uncore.forcewake_count == 0)
7033                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7034         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7035 }
7036
7037 /*
7038  * Package states C8 and deeper are really deep PC states that can only be
7039  * reached when all the devices on the system allow it, so even if the graphics
7040  * device allows PC8+, it doesn't mean the system will actually get to these
7041  * states. Our driver only allows PC8+ when going into runtime PM.
7042  *
7043  * The requirements for PC8+ are that all the outputs are disabled, the power
7044  * well is disabled and most interrupts are disabled, and these are also
7045  * requirements for runtime PM. When these conditions are met, we manually do
7046  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7047  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7048  * hang the machine.
7049  *
7050  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7051  * the state of some registers, so when we come back from PC8+ we need to
7052  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7053  * need to take care of the registers kept by RC6. Notice that this happens even
7054  * if we don't put the device in PCI D3 state (which is what currently happens
7055  * because of the runtime PM support).
7056  *
7057  * For more, read "Display Sequences for Package C8" on the hardware
7058  * documentation.
7059  */
7060 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7061 {
7062         struct drm_device *dev = dev_priv->dev;
7063         uint32_t val;
7064
7065         DRM_DEBUG_KMS("Enabling package C8+\n");
7066
7067         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7068                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7069                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7070                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7071         }
7072
7073         lpt_disable_clkout_dp(dev);
7074         hsw_disable_lcpll(dev_priv, true, true);
7075 }
7076
7077 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7078 {
7079         struct drm_device *dev = dev_priv->dev;
7080         uint32_t val;
7081
7082         DRM_DEBUG_KMS("Disabling package C8+\n");
7083
7084         hsw_restore_lcpll(dev_priv);
7085         lpt_init_pch_refclk(dev);
7086
7087         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7088                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7089                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7090                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7091         }
7092
7093         intel_prepare_ddi(dev);
7094 }
7095
7096 static void snb_modeset_global_resources(struct drm_device *dev)
7097 {
7098         modeset_update_crtc_power_domains(dev);
7099 }
7100
7101 static void haswell_modeset_global_resources(struct drm_device *dev)
7102 {
7103         modeset_update_crtc_power_domains(dev);
7104 }
7105
7106 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7107                                  int x, int y,
7108                                  struct drm_framebuffer *fb)
7109 {
7110         struct drm_device *dev = crtc->dev;
7111         struct drm_i915_private *dev_priv = dev->dev_private;
7112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7113         int plane = intel_crtc->plane;
7114         int ret;
7115
7116         if (!intel_ddi_pll_select(intel_crtc))
7117                 return -EINVAL;
7118         intel_ddi_pll_enable(intel_crtc);
7119
7120         if (intel_crtc->config.has_dp_encoder)
7121                 intel_dp_set_m_n(intel_crtc);
7122
7123         intel_crtc->lowfreq_avail = false;
7124
7125         intel_set_pipe_timings(intel_crtc);
7126
7127         if (intel_crtc->config.has_pch_encoder) {
7128                 intel_cpu_transcoder_set_m_n(intel_crtc,
7129                                              &intel_crtc->config.fdi_m_n);
7130         }
7131
7132         haswell_set_pipeconf(crtc);
7133
7134         intel_set_pipe_csc(crtc);
7135
7136         /* Set up the display plane register */
7137         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7138         POSTING_READ(DSPCNTR(plane));
7139
7140         ret = intel_pipe_set_base(crtc, x, y, fb);
7141
7142         return ret;
7143 }
7144
7145 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7146                                     struct intel_crtc_config *pipe_config)
7147 {
7148         struct drm_device *dev = crtc->base.dev;
7149         struct drm_i915_private *dev_priv = dev->dev_private;
7150         enum intel_display_power_domain pfit_domain;
7151         uint32_t tmp;
7152
7153         if (!intel_display_power_enabled(dev_priv,
7154                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7155                 return false;
7156
7157         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7158         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7159
7160         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7161         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7162                 enum pipe trans_edp_pipe;
7163                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7164                 default:
7165                         WARN(1, "unknown pipe linked to edp transcoder\n");
7166                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7167                 case TRANS_DDI_EDP_INPUT_A_ON:
7168                         trans_edp_pipe = PIPE_A;
7169                         break;
7170                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7171                         trans_edp_pipe = PIPE_B;
7172                         break;
7173                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7174                         trans_edp_pipe = PIPE_C;
7175                         break;
7176                 }
7177
7178                 if (trans_edp_pipe == crtc->pipe)
7179                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7180         }
7181
7182         if (!intel_display_power_enabled(dev_priv,
7183                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7184                 return false;
7185
7186         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7187         if (!(tmp & PIPECONF_ENABLE))
7188                 return false;
7189
7190         /*
7191          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7192          * DDI E. So just check whether this pipe is wired to DDI E and whether
7193          * the PCH transcoder is on.
7194          */
7195         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7196         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7197             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7198                 pipe_config->has_pch_encoder = true;
7199
7200                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7201                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7202                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7203
7204                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7205         }
7206
7207         intel_get_pipe_timings(crtc, pipe_config);
7208
7209         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7210         if (intel_display_power_enabled(dev_priv, pfit_domain))
7211                 ironlake_get_pfit_config(crtc, pipe_config);
7212
7213         if (IS_HASWELL(dev))
7214                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7215                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7216
7217         pipe_config->pixel_multiplier = 1;
7218
7219         return true;
7220 }
7221
7222 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7223                                int x, int y,
7224                                struct drm_framebuffer *fb)
7225 {
7226         struct drm_device *dev = crtc->dev;
7227         struct drm_i915_private *dev_priv = dev->dev_private;
7228         struct intel_encoder *encoder;
7229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7230         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7231         int pipe = intel_crtc->pipe;
7232         int ret;
7233
7234         drm_vblank_pre_modeset(dev, pipe);
7235
7236         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7237
7238         drm_vblank_post_modeset(dev, pipe);
7239
7240         if (ret != 0)
7241                 return ret;
7242
7243         for_each_encoder_on_crtc(dev, crtc, encoder) {
7244                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7245                         encoder->base.base.id,
7246                         drm_get_encoder_name(&encoder->base),
7247                         mode->base.id, mode->name);
7248
7249                 if (encoder->mode_set)
7250                         encoder->mode_set(encoder);
7251         }
7252
7253         return 0;
7254 }
7255
7256 static struct {
7257         int clock;
7258         u32 config;
7259 } hdmi_audio_clock[] = {
7260         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7261         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7262         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7263         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7264         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7265         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7266         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7267         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7268         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7269         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7270 };
7271
7272 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7273 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7274 {
7275         int i;
7276
7277         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7278                 if (mode->clock == hdmi_audio_clock[i].clock)
7279                         break;
7280         }
7281
7282         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7283                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7284                 i = 1;
7285         }
7286
7287         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7288                       hdmi_audio_clock[i].clock,
7289                       hdmi_audio_clock[i].config);
7290
7291         return hdmi_audio_clock[i].config;
7292 }
7293
7294 static bool intel_eld_uptodate(struct drm_connector *connector,
7295                                int reg_eldv, uint32_t bits_eldv,
7296                                int reg_elda, uint32_t bits_elda,
7297                                int reg_edid)
7298 {
7299         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7300         uint8_t *eld = connector->eld;
7301         uint32_t i;
7302
7303         i = I915_READ(reg_eldv);
7304         i &= bits_eldv;
7305
7306         if (!eld[0])
7307                 return !i;
7308
7309         if (!i)
7310                 return false;
7311
7312         i = I915_READ(reg_elda);
7313         i &= ~bits_elda;
7314         I915_WRITE(reg_elda, i);
7315
7316         for (i = 0; i < eld[2]; i++)
7317                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7318                         return false;
7319
7320         return true;
7321 }
7322
7323 static void g4x_write_eld(struct drm_connector *connector,
7324                           struct drm_crtc *crtc,
7325                           struct drm_display_mode *mode)
7326 {
7327         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7328         uint8_t *eld = connector->eld;
7329         uint32_t eldv;
7330         uint32_t len;
7331         uint32_t i;
7332
7333         i = I915_READ(G4X_AUD_VID_DID);
7334
7335         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7336                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7337         else
7338                 eldv = G4X_ELDV_DEVCTG;
7339
7340         if (intel_eld_uptodate(connector,
7341                                G4X_AUD_CNTL_ST, eldv,
7342                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7343                                G4X_HDMIW_HDMIEDID))
7344                 return;
7345
7346         i = I915_READ(G4X_AUD_CNTL_ST);
7347         i &= ~(eldv | G4X_ELD_ADDR);
7348         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7349         I915_WRITE(G4X_AUD_CNTL_ST, i);
7350
7351         if (!eld[0])
7352                 return;
7353
7354         len = min_t(uint8_t, eld[2], len);
7355         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7356         for (i = 0; i < len; i++)
7357                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7358
7359         i = I915_READ(G4X_AUD_CNTL_ST);
7360         i |= eldv;
7361         I915_WRITE(G4X_AUD_CNTL_ST, i);
7362 }
7363
7364 static void haswell_write_eld(struct drm_connector *connector,
7365                               struct drm_crtc *crtc,
7366                               struct drm_display_mode *mode)
7367 {
7368         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7369         uint8_t *eld = connector->eld;
7370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371         uint32_t eldv;
7372         uint32_t i;
7373         int len;
7374         int pipe = to_intel_crtc(crtc)->pipe;
7375         int tmp;
7376
7377         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7378         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7379         int aud_config = HSW_AUD_CFG(pipe);
7380         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7381
7382         /* Audio output enable */
7383         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7384         tmp = I915_READ(aud_cntrl_st2);
7385         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7386         I915_WRITE(aud_cntrl_st2, tmp);
7387         POSTING_READ(aud_cntrl_st2);
7388
7389         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7390
7391         /* Set ELD valid state */
7392         tmp = I915_READ(aud_cntrl_st2);
7393         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7394         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7395         I915_WRITE(aud_cntrl_st2, tmp);
7396         tmp = I915_READ(aud_cntrl_st2);
7397         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7398
7399         /* Enable HDMI mode */
7400         tmp = I915_READ(aud_config);
7401         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7402         /* clear N_programing_enable and N_value_index */
7403         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7404         I915_WRITE(aud_config, tmp);
7405
7406         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7407
7408         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7409         intel_crtc->eld_vld = true;
7410
7411         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7412                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7413                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7414                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7415         } else {
7416                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7417         }
7418
7419         if (intel_eld_uptodate(connector,
7420                                aud_cntrl_st2, eldv,
7421                                aud_cntl_st, IBX_ELD_ADDRESS,
7422                                hdmiw_hdmiedid))
7423                 return;
7424
7425         i = I915_READ(aud_cntrl_st2);
7426         i &= ~eldv;
7427         I915_WRITE(aud_cntrl_st2, i);
7428
7429         if (!eld[0])
7430                 return;
7431
7432         i = I915_READ(aud_cntl_st);
7433         i &= ~IBX_ELD_ADDRESS;
7434         I915_WRITE(aud_cntl_st, i);
7435         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7436         DRM_DEBUG_DRIVER("port num:%d\n", i);
7437
7438         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7439         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7440         for (i = 0; i < len; i++)
7441                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7442
7443         i = I915_READ(aud_cntrl_st2);
7444         i |= eldv;
7445         I915_WRITE(aud_cntrl_st2, i);
7446
7447 }
7448
7449 static void ironlake_write_eld(struct drm_connector *connector,
7450                                struct drm_crtc *crtc,
7451                                struct drm_display_mode *mode)
7452 {
7453         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7454         uint8_t *eld = connector->eld;
7455         uint32_t eldv;
7456         uint32_t i;
7457         int len;
7458         int hdmiw_hdmiedid;
7459         int aud_config;
7460         int aud_cntl_st;
7461         int aud_cntrl_st2;
7462         int pipe = to_intel_crtc(crtc)->pipe;
7463
7464         if (HAS_PCH_IBX(connector->dev)) {
7465                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7466                 aud_config = IBX_AUD_CFG(pipe);
7467                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7468                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7469         } else if (IS_VALLEYVIEW(connector->dev)) {
7470                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7471                 aud_config = VLV_AUD_CFG(pipe);
7472                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7473                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7474         } else {
7475                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7476                 aud_config = CPT_AUD_CFG(pipe);
7477                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7478                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7479         }
7480
7481         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7482
7483         if (IS_VALLEYVIEW(connector->dev))  {
7484                 struct intel_encoder *intel_encoder;
7485                 struct intel_digital_port *intel_dig_port;
7486
7487                 intel_encoder = intel_attached_encoder(connector);
7488                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7489                 i = intel_dig_port->port;
7490         } else {
7491                 i = I915_READ(aud_cntl_st);
7492                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7493                 /* DIP_Port_Select, 0x1 = PortB */
7494         }
7495
7496         if (!i) {
7497                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7498                 /* operate blindly on all ports */
7499                 eldv = IBX_ELD_VALIDB;
7500                 eldv |= IBX_ELD_VALIDB << 4;
7501                 eldv |= IBX_ELD_VALIDB << 8;
7502         } else {
7503                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7504                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7505         }
7506
7507         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7508                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7509                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7510                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7511         } else {
7512                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7513         }
7514
7515         if (intel_eld_uptodate(connector,
7516                                aud_cntrl_st2, eldv,
7517                                aud_cntl_st, IBX_ELD_ADDRESS,
7518                                hdmiw_hdmiedid))
7519                 return;
7520
7521         i = I915_READ(aud_cntrl_st2);
7522         i &= ~eldv;
7523         I915_WRITE(aud_cntrl_st2, i);
7524
7525         if (!eld[0])
7526                 return;
7527
7528         i = I915_READ(aud_cntl_st);
7529         i &= ~IBX_ELD_ADDRESS;
7530         I915_WRITE(aud_cntl_st, i);
7531
7532         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7533         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7534         for (i = 0; i < len; i++)
7535                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7536
7537         i = I915_READ(aud_cntrl_st2);
7538         i |= eldv;
7539         I915_WRITE(aud_cntrl_st2, i);
7540 }
7541
7542 void intel_write_eld(struct drm_encoder *encoder,
7543                      struct drm_display_mode *mode)
7544 {
7545         struct drm_crtc *crtc = encoder->crtc;
7546         struct drm_connector *connector;
7547         struct drm_device *dev = encoder->dev;
7548         struct drm_i915_private *dev_priv = dev->dev_private;
7549
7550         connector = drm_select_eld(encoder, mode);
7551         if (!connector)
7552                 return;
7553
7554         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7555                          connector->base.id,
7556                          drm_get_connector_name(connector),
7557                          connector->encoder->base.id,
7558                          drm_get_encoder_name(connector->encoder));
7559
7560         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7561
7562         if (dev_priv->display.write_eld)
7563                 dev_priv->display.write_eld(connector, crtc, mode);
7564 }
7565
7566 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7567 {
7568         struct drm_device *dev = crtc->dev;
7569         struct drm_i915_private *dev_priv = dev->dev_private;
7570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7571         bool visible = base != 0;
7572         u32 cntl;
7573
7574         if (intel_crtc->cursor_visible == visible)
7575                 return;
7576
7577         cntl = I915_READ(_CURACNTR);
7578         if (visible) {
7579                 /* On these chipsets we can only modify the base whilst
7580                  * the cursor is disabled.
7581                  */
7582                 I915_WRITE(_CURABASE, base);
7583
7584                 cntl &= ~(CURSOR_FORMAT_MASK);
7585                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7586                 cntl |= CURSOR_ENABLE |
7587                         CURSOR_GAMMA_ENABLE |
7588                         CURSOR_FORMAT_ARGB;
7589         } else
7590                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7591         I915_WRITE(_CURACNTR, cntl);
7592
7593         intel_crtc->cursor_visible = visible;
7594 }
7595
7596 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7597 {
7598         struct drm_device *dev = crtc->dev;
7599         struct drm_i915_private *dev_priv = dev->dev_private;
7600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7601         int pipe = intel_crtc->pipe;
7602         bool visible = base != 0;
7603
7604         if (intel_crtc->cursor_visible != visible) {
7605                 int16_t width = intel_crtc->cursor_width;
7606                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7607                 if (base) {
7608                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7609                         cntl |= MCURSOR_GAMMA_ENABLE;
7610
7611                         switch (width) {
7612                         case 64:
7613                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7614                                 break;
7615                         case 128:
7616                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7617                                 break;
7618                         case 256:
7619                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7620                                 break;
7621                         default:
7622                                 WARN_ON(1);
7623                                 return;
7624                         }
7625                         cntl |= pipe << 28; /* Connect to correct pipe */
7626                 } else {
7627                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7628                         cntl |= CURSOR_MODE_DISABLE;
7629                 }
7630                 I915_WRITE(CURCNTR(pipe), cntl);
7631
7632                 intel_crtc->cursor_visible = visible;
7633         }
7634         /* and commit changes on next vblank */
7635         POSTING_READ(CURCNTR(pipe));
7636         I915_WRITE(CURBASE(pipe), base);
7637         POSTING_READ(CURBASE(pipe));
7638 }
7639
7640 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7641 {
7642         struct drm_device *dev = crtc->dev;
7643         struct drm_i915_private *dev_priv = dev->dev_private;
7644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7645         int pipe = intel_crtc->pipe;
7646         bool visible = base != 0;
7647
7648         if (intel_crtc->cursor_visible != visible) {
7649                 int16_t width = intel_crtc->cursor_width;
7650                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7651                 if (base) {
7652                         cntl &= ~CURSOR_MODE;
7653                         cntl |= MCURSOR_GAMMA_ENABLE;
7654                         switch (width) {
7655                         case 64:
7656                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7657                                 break;
7658                         case 128:
7659                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7660                                 break;
7661                         case 256:
7662                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7663                                 break;
7664                         default:
7665                                 WARN_ON(1);
7666                                 return;
7667                         }
7668                 } else {
7669                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7670                         cntl |= CURSOR_MODE_DISABLE;
7671                 }
7672                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7673                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7674                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7675                 }
7676                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7677
7678                 intel_crtc->cursor_visible = visible;
7679         }
7680         /* and commit changes on next vblank */
7681         POSTING_READ(CURCNTR_IVB(pipe));
7682         I915_WRITE(CURBASE_IVB(pipe), base);
7683         POSTING_READ(CURBASE_IVB(pipe));
7684 }
7685
7686 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7687 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7688                                      bool on)
7689 {
7690         struct drm_device *dev = crtc->dev;
7691         struct drm_i915_private *dev_priv = dev->dev_private;
7692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7693         int pipe = intel_crtc->pipe;
7694         int x = intel_crtc->cursor_x;
7695         int y = intel_crtc->cursor_y;
7696         u32 base = 0, pos = 0;
7697         bool visible;
7698
7699         if (on)
7700                 base = intel_crtc->cursor_addr;
7701
7702         if (x >= intel_crtc->config.pipe_src_w)
7703                 base = 0;
7704
7705         if (y >= intel_crtc->config.pipe_src_h)
7706                 base = 0;
7707
7708         if (x < 0) {
7709                 if (x + intel_crtc->cursor_width <= 0)
7710                         base = 0;
7711
7712                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7713                 x = -x;
7714         }
7715         pos |= x << CURSOR_X_SHIFT;
7716
7717         if (y < 0) {
7718                 if (y + intel_crtc->cursor_height <= 0)
7719                         base = 0;
7720
7721                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7722                 y = -y;
7723         }
7724         pos |= y << CURSOR_Y_SHIFT;
7725
7726         visible = base != 0;
7727         if (!visible && !intel_crtc->cursor_visible)
7728                 return;
7729
7730         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7731                 I915_WRITE(CURPOS_IVB(pipe), pos);
7732                 ivb_update_cursor(crtc, base);
7733         } else {
7734                 I915_WRITE(CURPOS(pipe), pos);
7735                 if (IS_845G(dev) || IS_I865G(dev))
7736                         i845_update_cursor(crtc, base);
7737                 else
7738                         i9xx_update_cursor(crtc, base);
7739         }
7740 }
7741
7742 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7743                                  struct drm_file *file,
7744                                  uint32_t handle,
7745                                  uint32_t width, uint32_t height)
7746 {
7747         struct drm_device *dev = crtc->dev;
7748         struct drm_i915_private *dev_priv = dev->dev_private;
7749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7750         struct drm_i915_gem_object *obj;
7751         unsigned old_width;
7752         uint32_t addr;
7753         int ret;
7754
7755         /* if we want to turn off the cursor ignore width and height */
7756         if (!handle) {
7757                 DRM_DEBUG_KMS("cursor off\n");
7758                 addr = 0;
7759                 obj = NULL;
7760                 mutex_lock(&dev->struct_mutex);
7761                 goto finish;
7762         }
7763
7764         /* Check for which cursor types we support */
7765         if (!((width == 64 && height == 64) ||
7766                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7767                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7768                 DRM_DEBUG("Cursor dimension not supported\n");
7769                 return -EINVAL;
7770         }
7771
7772         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7773         if (&obj->base == NULL)
7774                 return -ENOENT;
7775
7776         if (obj->base.size < width * height * 4) {
7777                 DRM_DEBUG_KMS("buffer is to small\n");
7778                 ret = -ENOMEM;
7779                 goto fail;
7780         }
7781
7782         /* we only need to pin inside GTT if cursor is non-phy */
7783         mutex_lock(&dev->struct_mutex);
7784         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7785                 unsigned alignment;
7786
7787                 if (obj->tiling_mode) {
7788                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7789                         ret = -EINVAL;
7790                         goto fail_locked;
7791                 }
7792
7793                 /* Note that the w/a also requires 2 PTE of padding following
7794                  * the bo. We currently fill all unused PTE with the shadow
7795                  * page and so we should always have valid PTE following the
7796                  * cursor preventing the VT-d warning.
7797                  */
7798                 alignment = 0;
7799                 if (need_vtd_wa(dev))
7800                         alignment = 64*1024;
7801
7802                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7803                 if (ret) {
7804                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7805                         goto fail_locked;
7806                 }
7807
7808                 ret = i915_gem_object_put_fence(obj);
7809                 if (ret) {
7810                         DRM_DEBUG_KMS("failed to release fence for cursor");
7811                         goto fail_unpin;
7812                 }
7813
7814                 addr = i915_gem_obj_ggtt_offset(obj);
7815         } else {
7816                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7817                 ret = i915_gem_attach_phys_object(dev, obj,
7818                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7819                                                   align);
7820                 if (ret) {
7821                         DRM_DEBUG_KMS("failed to attach phys object\n");
7822                         goto fail_locked;
7823                 }
7824                 addr = obj->phys_obj->handle->busaddr;
7825         }
7826
7827         if (IS_GEN2(dev))
7828                 I915_WRITE(CURSIZE, (height << 12) | width);
7829
7830  finish:
7831         if (intel_crtc->cursor_bo) {
7832                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7833                         if (intel_crtc->cursor_bo != obj)
7834                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7835                 } else
7836                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7837                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7838         }
7839
7840         mutex_unlock(&dev->struct_mutex);
7841
7842         old_width = intel_crtc->cursor_width;
7843
7844         intel_crtc->cursor_addr = addr;
7845         intel_crtc->cursor_bo = obj;
7846         intel_crtc->cursor_width = width;
7847         intel_crtc->cursor_height = height;
7848
7849         if (intel_crtc->active) {
7850                 if (old_width != width)
7851                         intel_update_watermarks(crtc);
7852                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7853         }
7854
7855         return 0;
7856 fail_unpin:
7857         i915_gem_object_unpin_from_display_plane(obj);
7858 fail_locked:
7859         mutex_unlock(&dev->struct_mutex);
7860 fail:
7861         drm_gem_object_unreference_unlocked(&obj->base);
7862         return ret;
7863 }
7864
7865 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7866 {
7867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7868
7869         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7870         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7871
7872         if (intel_crtc->active)
7873                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7874
7875         return 0;
7876 }
7877
7878 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7879                                  u16 *blue, uint32_t start, uint32_t size)
7880 {
7881         int end = (start + size > 256) ? 256 : start + size, i;
7882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7883
7884         for (i = start; i < end; i++) {
7885                 intel_crtc->lut_r[i] = red[i] >> 8;
7886                 intel_crtc->lut_g[i] = green[i] >> 8;
7887                 intel_crtc->lut_b[i] = blue[i] >> 8;
7888         }
7889
7890         intel_crtc_load_lut(crtc);
7891 }
7892
7893 /* VESA 640x480x72Hz mode to set on the pipe */
7894 static struct drm_display_mode load_detect_mode = {
7895         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7896                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7897 };
7898
7899 struct drm_framebuffer *
7900 __intel_framebuffer_create(struct drm_device *dev,
7901                            struct drm_mode_fb_cmd2 *mode_cmd,
7902                            struct drm_i915_gem_object *obj)
7903 {
7904         struct intel_framebuffer *intel_fb;
7905         int ret;
7906
7907         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7908         if (!intel_fb) {
7909                 drm_gem_object_unreference_unlocked(&obj->base);
7910                 return ERR_PTR(-ENOMEM);
7911         }
7912
7913         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7914         if (ret)
7915                 goto err;
7916
7917         return &intel_fb->base;
7918 err:
7919         drm_gem_object_unreference_unlocked(&obj->base);
7920         kfree(intel_fb);
7921
7922         return ERR_PTR(ret);
7923 }
7924
7925 static struct drm_framebuffer *
7926 intel_framebuffer_create(struct drm_device *dev,
7927                          struct drm_mode_fb_cmd2 *mode_cmd,
7928                          struct drm_i915_gem_object *obj)
7929 {
7930         struct drm_framebuffer *fb;
7931         int ret;
7932
7933         ret = i915_mutex_lock_interruptible(dev);
7934         if (ret)
7935                 return ERR_PTR(ret);
7936         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7937         mutex_unlock(&dev->struct_mutex);
7938
7939         return fb;
7940 }
7941
7942 static u32
7943 intel_framebuffer_pitch_for_width(int width, int bpp)
7944 {
7945         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7946         return ALIGN(pitch, 64);
7947 }
7948
7949 static u32
7950 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7951 {
7952         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7953         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7954 }
7955
7956 static struct drm_framebuffer *
7957 intel_framebuffer_create_for_mode(struct drm_device *dev,
7958                                   struct drm_display_mode *mode,
7959                                   int depth, int bpp)
7960 {
7961         struct drm_i915_gem_object *obj;
7962         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7963
7964         obj = i915_gem_alloc_object(dev,
7965                                     intel_framebuffer_size_for_mode(mode, bpp));
7966         if (obj == NULL)
7967                 return ERR_PTR(-ENOMEM);
7968
7969         mode_cmd.width = mode->hdisplay;
7970         mode_cmd.height = mode->vdisplay;
7971         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7972                                                                 bpp);
7973         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7974
7975         return intel_framebuffer_create(dev, &mode_cmd, obj);
7976 }
7977
7978 static struct drm_framebuffer *
7979 mode_fits_in_fbdev(struct drm_device *dev,
7980                    struct drm_display_mode *mode)
7981 {
7982 #ifdef CONFIG_DRM_I915_FBDEV
7983         struct drm_i915_private *dev_priv = dev->dev_private;
7984         struct drm_i915_gem_object *obj;
7985         struct drm_framebuffer *fb;
7986
7987         if (!dev_priv->fbdev)
7988                 return NULL;
7989
7990         if (!dev_priv->fbdev->fb)
7991                 return NULL;
7992
7993         obj = dev_priv->fbdev->fb->obj;
7994         BUG_ON(!obj);
7995
7996         fb = &dev_priv->fbdev->fb->base;
7997         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7998                                                                fb->bits_per_pixel))
7999                 return NULL;
8000
8001         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8002                 return NULL;
8003
8004         return fb;
8005 #else
8006         return NULL;
8007 #endif
8008 }
8009
8010 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8011                                 struct drm_display_mode *mode,
8012                                 struct intel_load_detect_pipe *old)
8013 {
8014         struct intel_crtc *intel_crtc;
8015         struct intel_encoder *intel_encoder =
8016                 intel_attached_encoder(connector);
8017         struct drm_crtc *possible_crtc;
8018         struct drm_encoder *encoder = &intel_encoder->base;
8019         struct drm_crtc *crtc = NULL;
8020         struct drm_device *dev = encoder->dev;
8021         struct drm_framebuffer *fb;
8022         int i = -1;
8023
8024         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8025                       connector->base.id, drm_get_connector_name(connector),
8026                       encoder->base.id, drm_get_encoder_name(encoder));
8027
8028         /*
8029          * Algorithm gets a little messy:
8030          *
8031          *   - if the connector already has an assigned crtc, use it (but make
8032          *     sure it's on first)
8033          *
8034          *   - try to find the first unused crtc that can drive this connector,
8035          *     and use that if we find one
8036          */
8037
8038         /* See if we already have a CRTC for this connector */
8039         if (encoder->crtc) {
8040                 crtc = encoder->crtc;
8041
8042                 mutex_lock(&crtc->mutex);
8043
8044                 old->dpms_mode = connector->dpms;
8045                 old->load_detect_temp = false;
8046
8047                 /* Make sure the crtc and connector are running */
8048                 if (connector->dpms != DRM_MODE_DPMS_ON)
8049                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8050
8051                 return true;
8052         }
8053
8054         /* Find an unused one (if possible) */
8055         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8056                 i++;
8057                 if (!(encoder->possible_crtcs & (1 << i)))
8058                         continue;
8059                 if (!possible_crtc->enabled) {
8060                         crtc = possible_crtc;
8061                         break;
8062                 }
8063         }
8064
8065         /*
8066          * If we didn't find an unused CRTC, don't use any.
8067          */
8068         if (!crtc) {
8069                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8070                 return false;
8071         }
8072
8073         mutex_lock(&crtc->mutex);
8074         intel_encoder->new_crtc = to_intel_crtc(crtc);
8075         to_intel_connector(connector)->new_encoder = intel_encoder;
8076
8077         intel_crtc = to_intel_crtc(crtc);
8078         intel_crtc->new_enabled = true;
8079         intel_crtc->new_config = &intel_crtc->config;
8080         old->dpms_mode = connector->dpms;
8081         old->load_detect_temp = true;
8082         old->release_fb = NULL;
8083
8084         if (!mode)
8085                 mode = &load_detect_mode;
8086
8087         /* We need a framebuffer large enough to accommodate all accesses
8088          * that the plane may generate whilst we perform load detection.
8089          * We can not rely on the fbcon either being present (we get called
8090          * during its initialisation to detect all boot displays, or it may
8091          * not even exist) or that it is large enough to satisfy the
8092          * requested mode.
8093          */
8094         fb = mode_fits_in_fbdev(dev, mode);
8095         if (fb == NULL) {
8096                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8097                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8098                 old->release_fb = fb;
8099         } else
8100                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8101         if (IS_ERR(fb)) {
8102                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8103                 goto fail;
8104         }
8105
8106         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8107                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8108                 if (old->release_fb)
8109                         old->release_fb->funcs->destroy(old->release_fb);
8110                 goto fail;
8111         }
8112
8113         /* let the connector get through one full cycle before testing */
8114         intel_wait_for_vblank(dev, intel_crtc->pipe);
8115         return true;
8116
8117  fail:
8118         intel_crtc->new_enabled = crtc->enabled;
8119         if (intel_crtc->new_enabled)
8120                 intel_crtc->new_config = &intel_crtc->config;
8121         else
8122                 intel_crtc->new_config = NULL;
8123         mutex_unlock(&crtc->mutex);
8124         return false;
8125 }
8126
8127 void intel_release_load_detect_pipe(struct drm_connector *connector,
8128                                     struct intel_load_detect_pipe *old)
8129 {
8130         struct intel_encoder *intel_encoder =
8131                 intel_attached_encoder(connector);
8132         struct drm_encoder *encoder = &intel_encoder->base;
8133         struct drm_crtc *crtc = encoder->crtc;
8134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8135
8136         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8137                       connector->base.id, drm_get_connector_name(connector),
8138                       encoder->base.id, drm_get_encoder_name(encoder));
8139
8140         if (old->load_detect_temp) {
8141                 to_intel_connector(connector)->new_encoder = NULL;
8142                 intel_encoder->new_crtc = NULL;
8143                 intel_crtc->new_enabled = false;
8144                 intel_crtc->new_config = NULL;
8145                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8146
8147                 if (old->release_fb) {
8148                         drm_framebuffer_unregister_private(old->release_fb);
8149                         drm_framebuffer_unreference(old->release_fb);
8150                 }
8151
8152                 mutex_unlock(&crtc->mutex);
8153                 return;
8154         }
8155
8156         /* Switch crtc and encoder back off if necessary */
8157         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8158                 connector->funcs->dpms(connector, old->dpms_mode);
8159
8160         mutex_unlock(&crtc->mutex);
8161 }
8162
8163 static int i9xx_pll_refclk(struct drm_device *dev,
8164                            const struct intel_crtc_config *pipe_config)
8165 {
8166         struct drm_i915_private *dev_priv = dev->dev_private;
8167         u32 dpll = pipe_config->dpll_hw_state.dpll;
8168
8169         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8170                 return dev_priv->vbt.lvds_ssc_freq;
8171         else if (HAS_PCH_SPLIT(dev))
8172                 return 120000;
8173         else if (!IS_GEN2(dev))
8174                 return 96000;
8175         else
8176                 return 48000;
8177 }
8178
8179 /* Returns the clock of the currently programmed mode of the given pipe. */
8180 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8181                                 struct intel_crtc_config *pipe_config)
8182 {
8183         struct drm_device *dev = crtc->base.dev;
8184         struct drm_i915_private *dev_priv = dev->dev_private;
8185         int pipe = pipe_config->cpu_transcoder;
8186         u32 dpll = pipe_config->dpll_hw_state.dpll;
8187         u32 fp;
8188         intel_clock_t clock;
8189         int refclk = i9xx_pll_refclk(dev, pipe_config);
8190
8191         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8192                 fp = pipe_config->dpll_hw_state.fp0;
8193         else
8194                 fp = pipe_config->dpll_hw_state.fp1;
8195
8196         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8197         if (IS_PINEVIEW(dev)) {
8198                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8199                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8200         } else {
8201                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8202                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8203         }
8204
8205         if (!IS_GEN2(dev)) {
8206                 if (IS_PINEVIEW(dev))
8207                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8208                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8209                 else
8210                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8211                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8212
8213                 switch (dpll & DPLL_MODE_MASK) {
8214                 case DPLLB_MODE_DAC_SERIAL:
8215                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8216                                 5 : 10;
8217                         break;
8218                 case DPLLB_MODE_LVDS:
8219                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8220                                 7 : 14;
8221                         break;
8222                 default:
8223                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8224                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8225                         return;
8226                 }
8227
8228                 if (IS_PINEVIEW(dev))
8229                         pineview_clock(refclk, &clock);
8230                 else
8231                         i9xx_clock(refclk, &clock);
8232         } else {
8233                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8234                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8235
8236                 if (is_lvds) {
8237                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8238                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8239
8240                         if (lvds & LVDS_CLKB_POWER_UP)
8241                                 clock.p2 = 7;
8242                         else
8243                                 clock.p2 = 14;
8244                 } else {
8245                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8246                                 clock.p1 = 2;
8247                         else {
8248                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8249                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8250                         }
8251                         if (dpll & PLL_P2_DIVIDE_BY_4)
8252                                 clock.p2 = 4;
8253                         else
8254                                 clock.p2 = 2;
8255                 }
8256
8257                 i9xx_clock(refclk, &clock);
8258         }
8259
8260         /*
8261          * This value includes pixel_multiplier. We will use
8262          * port_clock to compute adjusted_mode.crtc_clock in the
8263          * encoder's get_config() function.
8264          */
8265         pipe_config->port_clock = clock.dot;
8266 }
8267
8268 int intel_dotclock_calculate(int link_freq,
8269                              const struct intel_link_m_n *m_n)
8270 {
8271         /*
8272          * The calculation for the data clock is:
8273          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8274          * But we want to avoid losing precison if possible, so:
8275          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8276          *
8277          * and the link clock is simpler:
8278          * link_clock = (m * link_clock) / n
8279          */
8280
8281         if (!m_n->link_n)
8282                 return 0;
8283
8284         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8285 }
8286
8287 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8288                                    struct intel_crtc_config *pipe_config)
8289 {
8290         struct drm_device *dev = crtc->base.dev;
8291
8292         /* read out port_clock from the DPLL */
8293         i9xx_crtc_clock_get(crtc, pipe_config);
8294
8295         /*
8296          * This value does not include pixel_multiplier.
8297          * We will check that port_clock and adjusted_mode.crtc_clock
8298          * agree once we know their relationship in the encoder's
8299          * get_config() function.
8300          */
8301         pipe_config->adjusted_mode.crtc_clock =
8302                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8303                                          &pipe_config->fdi_m_n);
8304 }
8305
8306 /** Returns the currently programmed mode of the given pipe. */
8307 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8308                                              struct drm_crtc *crtc)
8309 {
8310         struct drm_i915_private *dev_priv = dev->dev_private;
8311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8312         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8313         struct drm_display_mode *mode;
8314         struct intel_crtc_config pipe_config;
8315         int htot = I915_READ(HTOTAL(cpu_transcoder));
8316         int hsync = I915_READ(HSYNC(cpu_transcoder));
8317         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8318         int vsync = I915_READ(VSYNC(cpu_transcoder));
8319         enum pipe pipe = intel_crtc->pipe;
8320
8321         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8322         if (!mode)
8323                 return NULL;
8324
8325         /*
8326          * Construct a pipe_config sufficient for getting the clock info
8327          * back out of crtc_clock_get.
8328          *
8329          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8330          * to use a real value here instead.
8331          */
8332         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8333         pipe_config.pixel_multiplier = 1;
8334         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8335         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8336         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8337         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8338
8339         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8340         mode->hdisplay = (htot & 0xffff) + 1;
8341         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8342         mode->hsync_start = (hsync & 0xffff) + 1;
8343         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8344         mode->vdisplay = (vtot & 0xffff) + 1;
8345         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8346         mode->vsync_start = (vsync & 0xffff) + 1;
8347         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8348
8349         drm_mode_set_name(mode);
8350
8351         return mode;
8352 }
8353
8354 static void intel_increase_pllclock(struct drm_crtc *crtc)
8355 {
8356         struct drm_device *dev = crtc->dev;
8357         struct drm_i915_private *dev_priv = dev->dev_private;
8358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359         int pipe = intel_crtc->pipe;
8360         int dpll_reg = DPLL(pipe);
8361         int dpll;
8362
8363         if (HAS_PCH_SPLIT(dev))
8364                 return;
8365
8366         if (!dev_priv->lvds_downclock_avail)
8367                 return;
8368
8369         dpll = I915_READ(dpll_reg);
8370         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8371                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8372
8373                 assert_panel_unlocked(dev_priv, pipe);
8374
8375                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8376                 I915_WRITE(dpll_reg, dpll);
8377                 intel_wait_for_vblank(dev, pipe);
8378
8379                 dpll = I915_READ(dpll_reg);
8380                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8381                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8382         }
8383 }
8384
8385 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8386 {
8387         struct drm_device *dev = crtc->dev;
8388         struct drm_i915_private *dev_priv = dev->dev_private;
8389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8390
8391         if (HAS_PCH_SPLIT(dev))
8392                 return;
8393
8394         if (!dev_priv->lvds_downclock_avail)
8395                 return;
8396
8397         /*
8398          * Since this is called by a timer, we should never get here in
8399          * the manual case.
8400          */
8401         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8402                 int pipe = intel_crtc->pipe;
8403                 int dpll_reg = DPLL(pipe);
8404                 int dpll;
8405
8406                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8407
8408                 assert_panel_unlocked(dev_priv, pipe);
8409
8410                 dpll = I915_READ(dpll_reg);
8411                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8412                 I915_WRITE(dpll_reg, dpll);
8413                 intel_wait_for_vblank(dev, pipe);
8414                 dpll = I915_READ(dpll_reg);
8415                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8416                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8417         }
8418
8419 }
8420
8421 void intel_mark_busy(struct drm_device *dev)
8422 {
8423         struct drm_i915_private *dev_priv = dev->dev_private;
8424
8425         if (dev_priv->mm.busy)
8426                 return;
8427
8428         intel_runtime_pm_get(dev_priv);
8429         i915_update_gfx_val(dev_priv);
8430         dev_priv->mm.busy = true;
8431 }
8432
8433 void intel_mark_idle(struct drm_device *dev)
8434 {
8435         struct drm_i915_private *dev_priv = dev->dev_private;
8436         struct drm_crtc *crtc;
8437
8438         if (!dev_priv->mm.busy)
8439                 return;
8440
8441         dev_priv->mm.busy = false;
8442
8443         if (!i915.powersave)
8444                 goto out;
8445
8446         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8447                 if (!crtc->primary->fb)
8448                         continue;
8449
8450                 intel_decrease_pllclock(crtc);
8451         }
8452
8453         if (INTEL_INFO(dev)->gen >= 6)
8454                 gen6_rps_idle(dev->dev_private);
8455
8456 out:
8457         intel_runtime_pm_put(dev_priv);
8458 }
8459
8460 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8461                         struct intel_ring_buffer *ring)
8462 {
8463         struct drm_device *dev = obj->base.dev;
8464         struct drm_crtc *crtc;
8465
8466         if (!i915.powersave)
8467                 return;
8468
8469         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8470                 if (!crtc->primary->fb)
8471                         continue;
8472
8473                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8474                         continue;
8475
8476                 intel_increase_pllclock(crtc);
8477                 if (ring && intel_fbc_enabled(dev))
8478                         ring->fbc_dirty = true;
8479         }
8480 }
8481
8482 static void intel_crtc_destroy(struct drm_crtc *crtc)
8483 {
8484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8485         struct drm_device *dev = crtc->dev;
8486         struct intel_unpin_work *work;
8487         unsigned long flags;
8488
8489         spin_lock_irqsave(&dev->event_lock, flags);
8490         work = intel_crtc->unpin_work;
8491         intel_crtc->unpin_work = NULL;
8492         spin_unlock_irqrestore(&dev->event_lock, flags);
8493
8494         if (work) {
8495                 cancel_work_sync(&work->work);
8496                 kfree(work);
8497         }
8498
8499         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8500
8501         drm_crtc_cleanup(crtc);
8502
8503         kfree(intel_crtc);
8504 }
8505
8506 static void intel_unpin_work_fn(struct work_struct *__work)
8507 {
8508         struct intel_unpin_work *work =
8509                 container_of(__work, struct intel_unpin_work, work);
8510         struct drm_device *dev = work->crtc->dev;
8511
8512         mutex_lock(&dev->struct_mutex);
8513         intel_unpin_fb_obj(work->old_fb_obj);
8514         drm_gem_object_unreference(&work->pending_flip_obj->base);
8515         drm_gem_object_unreference(&work->old_fb_obj->base);
8516
8517         intel_update_fbc(dev);
8518         mutex_unlock(&dev->struct_mutex);
8519
8520         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8521         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8522
8523         kfree(work);
8524 }
8525
8526 static void do_intel_finish_page_flip(struct drm_device *dev,
8527                                       struct drm_crtc *crtc)
8528 {
8529         struct drm_i915_private *dev_priv = dev->dev_private;
8530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8531         struct intel_unpin_work *work;
8532         unsigned long flags;
8533
8534         /* Ignore early vblank irqs */
8535         if (intel_crtc == NULL)
8536                 return;
8537
8538         spin_lock_irqsave(&dev->event_lock, flags);
8539         work = intel_crtc->unpin_work;
8540
8541         /* Ensure we don't miss a work->pending update ... */
8542         smp_rmb();
8543
8544         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8545                 spin_unlock_irqrestore(&dev->event_lock, flags);
8546                 return;
8547         }
8548
8549         /* and that the unpin work is consistent wrt ->pending. */
8550         smp_rmb();
8551
8552         intel_crtc->unpin_work = NULL;
8553
8554         if (work->event)
8555                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8556
8557         drm_vblank_put(dev, intel_crtc->pipe);
8558
8559         spin_unlock_irqrestore(&dev->event_lock, flags);
8560
8561         wake_up_all(&dev_priv->pending_flip_queue);
8562
8563         queue_work(dev_priv->wq, &work->work);
8564
8565         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8566 }
8567
8568 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8569 {
8570         struct drm_i915_private *dev_priv = dev->dev_private;
8571         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8572
8573         do_intel_finish_page_flip(dev, crtc);
8574 }
8575
8576 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8577 {
8578         struct drm_i915_private *dev_priv = dev->dev_private;
8579         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8580
8581         do_intel_finish_page_flip(dev, crtc);
8582 }
8583
8584 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8585 {
8586         struct drm_i915_private *dev_priv = dev->dev_private;
8587         struct intel_crtc *intel_crtc =
8588                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8589         unsigned long flags;
8590
8591         /* NB: An MMIO update of the plane base pointer will also
8592          * generate a page-flip completion irq, i.e. every modeset
8593          * is also accompanied by a spurious intel_prepare_page_flip().
8594          */
8595         spin_lock_irqsave(&dev->event_lock, flags);
8596         if (intel_crtc->unpin_work)
8597                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8598         spin_unlock_irqrestore(&dev->event_lock, flags);
8599 }
8600
8601 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8602 {
8603         /* Ensure that the work item is consistent when activating it ... */
8604         smp_wmb();
8605         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8606         /* and that it is marked active as soon as the irq could fire. */
8607         smp_wmb();
8608 }
8609
8610 static int intel_gen2_queue_flip(struct drm_device *dev,
8611                                  struct drm_crtc *crtc,
8612                                  struct drm_framebuffer *fb,
8613                                  struct drm_i915_gem_object *obj,
8614                                  uint32_t flags)
8615 {
8616         struct drm_i915_private *dev_priv = dev->dev_private;
8617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8618         u32 flip_mask;
8619         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8620         int ret;
8621
8622         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8623         if (ret)
8624                 goto err;
8625
8626         ret = intel_ring_begin(ring, 6);
8627         if (ret)
8628                 goto err_unpin;
8629
8630         /* Can't queue multiple flips, so wait for the previous
8631          * one to finish before executing the next.
8632          */
8633         if (intel_crtc->plane)
8634                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8635         else
8636                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8637         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8638         intel_ring_emit(ring, MI_NOOP);
8639         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8640                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8641         intel_ring_emit(ring, fb->pitches[0]);
8642         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8643         intel_ring_emit(ring, 0); /* aux display base address, unused */
8644
8645         intel_mark_page_flip_active(intel_crtc);
8646         __intel_ring_advance(ring);
8647         return 0;
8648
8649 err_unpin:
8650         intel_unpin_fb_obj(obj);
8651 err:
8652         return ret;
8653 }
8654
8655 static int intel_gen3_queue_flip(struct drm_device *dev,
8656                                  struct drm_crtc *crtc,
8657                                  struct drm_framebuffer *fb,
8658                                  struct drm_i915_gem_object *obj,
8659                                  uint32_t flags)
8660 {
8661         struct drm_i915_private *dev_priv = dev->dev_private;
8662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8663         u32 flip_mask;
8664         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8665         int ret;
8666
8667         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8668         if (ret)
8669                 goto err;
8670
8671         ret = intel_ring_begin(ring, 6);
8672         if (ret)
8673                 goto err_unpin;
8674
8675         if (intel_crtc->plane)
8676                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8677         else
8678                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8679         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8680         intel_ring_emit(ring, MI_NOOP);
8681         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8682                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8683         intel_ring_emit(ring, fb->pitches[0]);
8684         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8685         intel_ring_emit(ring, MI_NOOP);
8686
8687         intel_mark_page_flip_active(intel_crtc);
8688         __intel_ring_advance(ring);
8689         return 0;
8690
8691 err_unpin:
8692         intel_unpin_fb_obj(obj);
8693 err:
8694         return ret;
8695 }
8696
8697 static int intel_gen4_queue_flip(struct drm_device *dev,
8698                                  struct drm_crtc *crtc,
8699                                  struct drm_framebuffer *fb,
8700                                  struct drm_i915_gem_object *obj,
8701                                  uint32_t flags)
8702 {
8703         struct drm_i915_private *dev_priv = dev->dev_private;
8704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8705         uint32_t pf, pipesrc;
8706         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8707         int ret;
8708
8709         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8710         if (ret)
8711                 goto err;
8712
8713         ret = intel_ring_begin(ring, 4);
8714         if (ret)
8715                 goto err_unpin;
8716
8717         /* i965+ uses the linear or tiled offsets from the
8718          * Display Registers (which do not change across a page-flip)
8719          * so we need only reprogram the base address.
8720          */
8721         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8722                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8723         intel_ring_emit(ring, fb->pitches[0]);
8724         intel_ring_emit(ring,
8725                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8726                         obj->tiling_mode);
8727
8728         /* XXX Enabling the panel-fitter across page-flip is so far
8729          * untested on non-native modes, so ignore it for now.
8730          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8731          */
8732         pf = 0;
8733         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8734         intel_ring_emit(ring, pf | pipesrc);
8735
8736         intel_mark_page_flip_active(intel_crtc);
8737         __intel_ring_advance(ring);
8738         return 0;
8739
8740 err_unpin:
8741         intel_unpin_fb_obj(obj);
8742 err:
8743         return ret;
8744 }
8745
8746 static int intel_gen6_queue_flip(struct drm_device *dev,
8747                                  struct drm_crtc *crtc,
8748                                  struct drm_framebuffer *fb,
8749                                  struct drm_i915_gem_object *obj,
8750                                  uint32_t flags)
8751 {
8752         struct drm_i915_private *dev_priv = dev->dev_private;
8753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8754         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8755         uint32_t pf, pipesrc;
8756         int ret;
8757
8758         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8759         if (ret)
8760                 goto err;
8761
8762         ret = intel_ring_begin(ring, 4);
8763         if (ret)
8764                 goto err_unpin;
8765
8766         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8767                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8768         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8769         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8770
8771         /* Contrary to the suggestions in the documentation,
8772          * "Enable Panel Fitter" does not seem to be required when page
8773          * flipping with a non-native mode, and worse causes a normal
8774          * modeset to fail.
8775          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8776          */
8777         pf = 0;
8778         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8779         intel_ring_emit(ring, pf | pipesrc);
8780
8781         intel_mark_page_flip_active(intel_crtc);
8782         __intel_ring_advance(ring);
8783         return 0;
8784
8785 err_unpin:
8786         intel_unpin_fb_obj(obj);
8787 err:
8788         return ret;
8789 }
8790
8791 static int intel_gen7_queue_flip(struct drm_device *dev,
8792                                  struct drm_crtc *crtc,
8793                                  struct drm_framebuffer *fb,
8794                                  struct drm_i915_gem_object *obj,
8795                                  uint32_t flags)
8796 {
8797         struct drm_i915_private *dev_priv = dev->dev_private;
8798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799         struct intel_ring_buffer *ring;
8800         uint32_t plane_bit = 0;
8801         int len, ret;
8802
8803         ring = obj->ring;
8804         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8805                 ring = &dev_priv->ring[BCS];
8806
8807         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8808         if (ret)
8809                 goto err;
8810
8811         switch(intel_crtc->plane) {
8812         case PLANE_A:
8813                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8814                 break;
8815         case PLANE_B:
8816                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8817                 break;
8818         case PLANE_C:
8819                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8820                 break;
8821         default:
8822                 WARN_ONCE(1, "unknown plane in flip command\n");
8823                 ret = -ENODEV;
8824                 goto err_unpin;
8825         }
8826
8827         len = 4;
8828         if (ring->id == RCS) {
8829                 len += 6;
8830                 /*
8831                  * On Gen 8, SRM is now taking an extra dword to accommodate
8832                  * 48bits addresses, and we need a NOOP for the batch size to
8833                  * stay even.
8834                  */
8835                 if (IS_GEN8(dev))
8836                         len += 2;
8837         }
8838
8839         /*
8840          * BSpec MI_DISPLAY_FLIP for IVB:
8841          * "The full packet must be contained within the same cache line."
8842          *
8843          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8844          * cacheline, if we ever start emitting more commands before
8845          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8846          * then do the cacheline alignment, and finally emit the
8847          * MI_DISPLAY_FLIP.
8848          */
8849         ret = intel_ring_cacheline_align(ring);
8850         if (ret)
8851                 goto err_unpin;
8852
8853         ret = intel_ring_begin(ring, len);
8854         if (ret)
8855                 goto err_unpin;
8856
8857         /* Unmask the flip-done completion message. Note that the bspec says that
8858          * we should do this for both the BCS and RCS, and that we must not unmask
8859          * more than one flip event at any time (or ensure that one flip message
8860          * can be sent by waiting for flip-done prior to queueing new flips).
8861          * Experimentation says that BCS works despite DERRMR masking all
8862          * flip-done completion events and that unmasking all planes at once
8863          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8864          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8865          */
8866         if (ring->id == RCS) {
8867                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8868                 intel_ring_emit(ring, DERRMR);
8869                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8870                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8871                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8872                 if (IS_GEN8(dev))
8873                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8874                                               MI_SRM_LRM_GLOBAL_GTT);
8875                 else
8876                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8877                                               MI_SRM_LRM_GLOBAL_GTT);
8878                 intel_ring_emit(ring, DERRMR);
8879                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8880                 if (IS_GEN8(dev)) {
8881                         intel_ring_emit(ring, 0);
8882                         intel_ring_emit(ring, MI_NOOP);
8883                 }
8884         }
8885
8886         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8887         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8888         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8889         intel_ring_emit(ring, (MI_NOOP));
8890
8891         intel_mark_page_flip_active(intel_crtc);
8892         __intel_ring_advance(ring);
8893         return 0;
8894
8895 err_unpin:
8896         intel_unpin_fb_obj(obj);
8897 err:
8898         return ret;
8899 }
8900
8901 static int intel_default_queue_flip(struct drm_device *dev,
8902                                     struct drm_crtc *crtc,
8903                                     struct drm_framebuffer *fb,
8904                                     struct drm_i915_gem_object *obj,
8905                                     uint32_t flags)
8906 {
8907         return -ENODEV;
8908 }
8909
8910 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8911                                 struct drm_framebuffer *fb,
8912                                 struct drm_pending_vblank_event *event,
8913                                 uint32_t page_flip_flags)
8914 {
8915         struct drm_device *dev = crtc->dev;
8916         struct drm_i915_private *dev_priv = dev->dev_private;
8917         struct drm_framebuffer *old_fb = crtc->primary->fb;
8918         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8920         struct intel_unpin_work *work;
8921         unsigned long flags;
8922         int ret;
8923
8924         /* Can't change pixel format via MI display flips. */
8925         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8926                 return -EINVAL;
8927
8928         /*
8929          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8930          * Note that pitch changes could also affect these register.
8931          */
8932         if (INTEL_INFO(dev)->gen > 3 &&
8933             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8934              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8935                 return -EINVAL;
8936
8937         if (i915_terminally_wedged(&dev_priv->gpu_error))
8938                 goto out_hang;
8939
8940         work = kzalloc(sizeof(*work), GFP_KERNEL);
8941         if (work == NULL)
8942                 return -ENOMEM;
8943
8944         work->event = event;
8945         work->crtc = crtc;
8946         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8947         INIT_WORK(&work->work, intel_unpin_work_fn);
8948
8949         ret = drm_vblank_get(dev, intel_crtc->pipe);
8950         if (ret)
8951                 goto free_work;
8952
8953         /* We borrow the event spin lock for protecting unpin_work */
8954         spin_lock_irqsave(&dev->event_lock, flags);
8955         if (intel_crtc->unpin_work) {
8956                 spin_unlock_irqrestore(&dev->event_lock, flags);
8957                 kfree(work);
8958                 drm_vblank_put(dev, intel_crtc->pipe);
8959
8960                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8961                 return -EBUSY;
8962         }
8963         intel_crtc->unpin_work = work;
8964         spin_unlock_irqrestore(&dev->event_lock, flags);
8965
8966         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8967                 flush_workqueue(dev_priv->wq);
8968
8969         ret = i915_mutex_lock_interruptible(dev);
8970         if (ret)
8971                 goto cleanup;
8972
8973         /* Reference the objects for the scheduled work. */
8974         drm_gem_object_reference(&work->old_fb_obj->base);
8975         drm_gem_object_reference(&obj->base);
8976
8977         crtc->primary->fb = fb;
8978
8979         work->pending_flip_obj = obj;
8980
8981         work->enable_stall_check = true;
8982
8983         atomic_inc(&intel_crtc->unpin_work_count);
8984         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8985
8986         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8987         if (ret)
8988                 goto cleanup_pending;
8989
8990         intel_disable_fbc(dev);
8991         intel_mark_fb_busy(obj, NULL);
8992         mutex_unlock(&dev->struct_mutex);
8993
8994         trace_i915_flip_request(intel_crtc->plane, obj);
8995
8996         return 0;
8997
8998 cleanup_pending:
8999         atomic_dec(&intel_crtc->unpin_work_count);
9000         crtc->primary->fb = old_fb;
9001         drm_gem_object_unreference(&work->old_fb_obj->base);
9002         drm_gem_object_unreference(&obj->base);
9003         mutex_unlock(&dev->struct_mutex);
9004
9005 cleanup:
9006         spin_lock_irqsave(&dev->event_lock, flags);
9007         intel_crtc->unpin_work = NULL;
9008         spin_unlock_irqrestore(&dev->event_lock, flags);
9009
9010         drm_vblank_put(dev, intel_crtc->pipe);
9011 free_work:
9012         kfree(work);
9013
9014         if (ret == -EIO) {
9015 out_hang:
9016                 intel_crtc_wait_for_pending_flips(crtc);
9017                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9018                 if (ret == 0 && event)
9019                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9020         }
9021         return ret;
9022 }
9023
9024 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9025         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9026         .load_lut = intel_crtc_load_lut,
9027 };
9028
9029 /**
9030  * intel_modeset_update_staged_output_state
9031  *
9032  * Updates the staged output configuration state, e.g. after we've read out the
9033  * current hw state.
9034  */
9035 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9036 {
9037         struct intel_crtc *crtc;
9038         struct intel_encoder *encoder;
9039         struct intel_connector *connector;
9040
9041         list_for_each_entry(connector, &dev->mode_config.connector_list,
9042                             base.head) {
9043                 connector->new_encoder =
9044                         to_intel_encoder(connector->base.encoder);
9045         }
9046
9047         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9048                             base.head) {
9049                 encoder->new_crtc =
9050                         to_intel_crtc(encoder->base.crtc);
9051         }
9052
9053         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9054                             base.head) {
9055                 crtc->new_enabled = crtc->base.enabled;
9056
9057                 if (crtc->new_enabled)
9058                         crtc->new_config = &crtc->config;
9059                 else
9060                         crtc->new_config = NULL;
9061         }
9062 }
9063
9064 /**
9065  * intel_modeset_commit_output_state
9066  *
9067  * This function copies the stage display pipe configuration to the real one.
9068  */
9069 static void intel_modeset_commit_output_state(struct drm_device *dev)
9070 {
9071         struct intel_crtc *crtc;
9072         struct intel_encoder *encoder;
9073         struct intel_connector *connector;
9074
9075         list_for_each_entry(connector, &dev->mode_config.connector_list,
9076                             base.head) {
9077                 connector->base.encoder = &connector->new_encoder->base;
9078         }
9079
9080         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9081                             base.head) {
9082                 encoder->base.crtc = &encoder->new_crtc->base;
9083         }
9084
9085         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9086                             base.head) {
9087                 crtc->base.enabled = crtc->new_enabled;
9088         }
9089 }
9090
9091 static void
9092 connected_sink_compute_bpp(struct intel_connector * connector,
9093                            struct intel_crtc_config *pipe_config)
9094 {
9095         int bpp = pipe_config->pipe_bpp;
9096
9097         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9098                 connector->base.base.id,
9099                 drm_get_connector_name(&connector->base));
9100
9101         /* Don't use an invalid EDID bpc value */
9102         if (connector->base.display_info.bpc &&
9103             connector->base.display_info.bpc * 3 < bpp) {
9104                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9105                               bpp, connector->base.display_info.bpc*3);
9106                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9107         }
9108
9109         /* Clamp bpp to 8 on screens without EDID 1.4 */
9110         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9111                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9112                               bpp);
9113                 pipe_config->pipe_bpp = 24;
9114         }
9115 }
9116
9117 static int
9118 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9119                           struct drm_framebuffer *fb,
9120                           struct intel_crtc_config *pipe_config)
9121 {
9122         struct drm_device *dev = crtc->base.dev;
9123         struct intel_connector *connector;
9124         int bpp;
9125
9126         switch (fb->pixel_format) {
9127         case DRM_FORMAT_C8:
9128                 bpp = 8*3; /* since we go through a colormap */
9129                 break;
9130         case DRM_FORMAT_XRGB1555:
9131         case DRM_FORMAT_ARGB1555:
9132                 /* checked in intel_framebuffer_init already */
9133                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9134                         return -EINVAL;
9135         case DRM_FORMAT_RGB565:
9136                 bpp = 6*3; /* min is 18bpp */
9137                 break;
9138         case DRM_FORMAT_XBGR8888:
9139         case DRM_FORMAT_ABGR8888:
9140                 /* checked in intel_framebuffer_init already */
9141                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9142                         return -EINVAL;
9143         case DRM_FORMAT_XRGB8888:
9144         case DRM_FORMAT_ARGB8888:
9145                 bpp = 8*3;
9146                 break;
9147         case DRM_FORMAT_XRGB2101010:
9148         case DRM_FORMAT_ARGB2101010:
9149         case DRM_FORMAT_XBGR2101010:
9150         case DRM_FORMAT_ABGR2101010:
9151                 /* checked in intel_framebuffer_init already */
9152                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9153                         return -EINVAL;
9154                 bpp = 10*3;
9155                 break;
9156         /* TODO: gen4+ supports 16 bpc floating point, too. */
9157         default:
9158                 DRM_DEBUG_KMS("unsupported depth\n");
9159                 return -EINVAL;
9160         }
9161
9162         pipe_config->pipe_bpp = bpp;
9163
9164         /* Clamp display bpp to EDID value */
9165         list_for_each_entry(connector, &dev->mode_config.connector_list,
9166                             base.head) {
9167                 if (!connector->new_encoder ||
9168                     connector->new_encoder->new_crtc != crtc)
9169                         continue;
9170
9171                 connected_sink_compute_bpp(connector, pipe_config);
9172         }
9173
9174         return bpp;
9175 }
9176
9177 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9178 {
9179         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9180                         "type: 0x%x flags: 0x%x\n",
9181                 mode->crtc_clock,
9182                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9183                 mode->crtc_hsync_end, mode->crtc_htotal,
9184                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9185                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9186 }
9187
9188 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9189                                    struct intel_crtc_config *pipe_config,
9190                                    const char *context)
9191 {
9192         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9193                       context, pipe_name(crtc->pipe));
9194
9195         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9196         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9197                       pipe_config->pipe_bpp, pipe_config->dither);
9198         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9199                       pipe_config->has_pch_encoder,
9200                       pipe_config->fdi_lanes,
9201                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9202                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9203                       pipe_config->fdi_m_n.tu);
9204         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9205                       pipe_config->has_dp_encoder,
9206                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9207                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9208                       pipe_config->dp_m_n.tu);
9209         DRM_DEBUG_KMS("requested mode:\n");
9210         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9211         DRM_DEBUG_KMS("adjusted mode:\n");
9212         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9213         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9214         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9215         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9216                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9217         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9218                       pipe_config->gmch_pfit.control,
9219                       pipe_config->gmch_pfit.pgm_ratios,
9220                       pipe_config->gmch_pfit.lvds_border_bits);
9221         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9222                       pipe_config->pch_pfit.pos,
9223                       pipe_config->pch_pfit.size,
9224                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9225         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9226         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9227 }
9228
9229 static bool encoders_cloneable(const struct intel_encoder *a,
9230                                const struct intel_encoder *b)
9231 {
9232         /* masks could be asymmetric, so check both ways */
9233         return a == b || (a->cloneable & (1 << b->type) &&
9234                           b->cloneable & (1 << a->type));
9235 }
9236
9237 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9238                                          struct intel_encoder *encoder)
9239 {
9240         struct drm_device *dev = crtc->base.dev;
9241         struct intel_encoder *source_encoder;
9242
9243         list_for_each_entry(source_encoder,
9244                             &dev->mode_config.encoder_list, base.head) {
9245                 if (source_encoder->new_crtc != crtc)
9246                         continue;
9247
9248                 if (!encoders_cloneable(encoder, source_encoder))
9249                         return false;
9250         }
9251
9252         return true;
9253 }
9254
9255 static bool check_encoder_cloning(struct intel_crtc *crtc)
9256 {
9257         struct drm_device *dev = crtc->base.dev;
9258         struct intel_encoder *encoder;
9259
9260         list_for_each_entry(encoder,
9261                             &dev->mode_config.encoder_list, base.head) {
9262                 if (encoder->new_crtc != crtc)
9263                         continue;
9264
9265                 if (!check_single_encoder_cloning(crtc, encoder))
9266                         return false;
9267         }
9268
9269         return true;
9270 }
9271
9272 static struct intel_crtc_config *
9273 intel_modeset_pipe_config(struct drm_crtc *crtc,
9274                           struct drm_framebuffer *fb,
9275                           struct drm_display_mode *mode)
9276 {
9277         struct drm_device *dev = crtc->dev;
9278         struct intel_encoder *encoder;
9279         struct intel_crtc_config *pipe_config;
9280         int plane_bpp, ret = -EINVAL;
9281         bool retry = true;
9282
9283         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9284                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9285                 return ERR_PTR(-EINVAL);
9286         }
9287
9288         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9289         if (!pipe_config)
9290                 return ERR_PTR(-ENOMEM);
9291
9292         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9293         drm_mode_copy(&pipe_config->requested_mode, mode);
9294
9295         pipe_config->cpu_transcoder =
9296                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9297         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9298
9299         /*
9300          * Sanitize sync polarity flags based on requested ones. If neither
9301          * positive or negative polarity is requested, treat this as meaning
9302          * negative polarity.
9303          */
9304         if (!(pipe_config->adjusted_mode.flags &
9305               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9306                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9307
9308         if (!(pipe_config->adjusted_mode.flags &
9309               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9310                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9311
9312         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9313          * plane pixel format and any sink constraints into account. Returns the
9314          * source plane bpp so that dithering can be selected on mismatches
9315          * after encoders and crtc also have had their say. */
9316         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9317                                               fb, pipe_config);
9318         if (plane_bpp < 0)
9319                 goto fail;
9320
9321         /*
9322          * Determine the real pipe dimensions. Note that stereo modes can
9323          * increase the actual pipe size due to the frame doubling and
9324          * insertion of additional space for blanks between the frame. This
9325          * is stored in the crtc timings. We use the requested mode to do this
9326          * computation to clearly distinguish it from the adjusted mode, which
9327          * can be changed by the connectors in the below retry loop.
9328          */
9329         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9330         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9331         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9332
9333 encoder_retry:
9334         /* Ensure the port clock defaults are reset when retrying. */
9335         pipe_config->port_clock = 0;
9336         pipe_config->pixel_multiplier = 1;
9337
9338         /* Fill in default crtc timings, allow encoders to overwrite them. */
9339         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9340
9341         /* Pass our mode to the connectors and the CRTC to give them a chance to
9342          * adjust it according to limitations or connector properties, and also
9343          * a chance to reject the mode entirely.
9344          */
9345         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9346                             base.head) {
9347
9348                 if (&encoder->new_crtc->base != crtc)
9349                         continue;
9350
9351                 if (!(encoder->compute_config(encoder, pipe_config))) {
9352                         DRM_DEBUG_KMS("Encoder config failure\n");
9353                         goto fail;
9354                 }
9355         }
9356
9357         /* Set default port clock if not overwritten by the encoder. Needs to be
9358          * done afterwards in case the encoder adjusts the mode. */
9359         if (!pipe_config->port_clock)
9360                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9361                         * pipe_config->pixel_multiplier;
9362
9363         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9364         if (ret < 0) {
9365                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9366                 goto fail;
9367         }
9368
9369         if (ret == RETRY) {
9370                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9371                         ret = -EINVAL;
9372                         goto fail;
9373                 }
9374
9375                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9376                 retry = false;
9377                 goto encoder_retry;
9378         }
9379
9380         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9381         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9382                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9383
9384         return pipe_config;
9385 fail:
9386         kfree(pipe_config);
9387         return ERR_PTR(ret);
9388 }
9389
9390 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9391  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9392 static void
9393 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9394                              unsigned *prepare_pipes, unsigned *disable_pipes)
9395 {
9396         struct intel_crtc *intel_crtc;
9397         struct drm_device *dev = crtc->dev;
9398         struct intel_encoder *encoder;
9399         struct intel_connector *connector;
9400         struct drm_crtc *tmp_crtc;
9401
9402         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9403
9404         /* Check which crtcs have changed outputs connected to them, these need
9405          * to be part of the prepare_pipes mask. We don't (yet) support global
9406          * modeset across multiple crtcs, so modeset_pipes will only have one
9407          * bit set at most. */
9408         list_for_each_entry(connector, &dev->mode_config.connector_list,
9409                             base.head) {
9410                 if (connector->base.encoder == &connector->new_encoder->base)
9411                         continue;
9412
9413                 if (connector->base.encoder) {
9414                         tmp_crtc = connector->base.encoder->crtc;
9415
9416                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9417                 }
9418
9419                 if (connector->new_encoder)
9420                         *prepare_pipes |=
9421                                 1 << connector->new_encoder->new_crtc->pipe;
9422         }
9423
9424         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9425                             base.head) {
9426                 if (encoder->base.crtc == &encoder->new_crtc->base)
9427                         continue;
9428
9429                 if (encoder->base.crtc) {
9430                         tmp_crtc = encoder->base.crtc;
9431
9432                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9433                 }
9434
9435                 if (encoder->new_crtc)
9436                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9437         }
9438
9439         /* Check for pipes that will be enabled/disabled ... */
9440         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9441                             base.head) {
9442                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9443                         continue;
9444
9445                 if (!intel_crtc->new_enabled)
9446                         *disable_pipes |= 1 << intel_crtc->pipe;
9447                 else
9448                         *prepare_pipes |= 1 << intel_crtc->pipe;
9449         }
9450
9451
9452         /* set_mode is also used to update properties on life display pipes. */
9453         intel_crtc = to_intel_crtc(crtc);
9454         if (intel_crtc->new_enabled)
9455                 *prepare_pipes |= 1 << intel_crtc->pipe;
9456
9457         /*
9458          * For simplicity do a full modeset on any pipe where the output routing
9459          * changed. We could be more clever, but that would require us to be
9460          * more careful with calling the relevant encoder->mode_set functions.
9461          */
9462         if (*prepare_pipes)
9463                 *modeset_pipes = *prepare_pipes;
9464
9465         /* ... and mask these out. */
9466         *modeset_pipes &= ~(*disable_pipes);
9467         *prepare_pipes &= ~(*disable_pipes);
9468
9469         /*
9470          * HACK: We don't (yet) fully support global modesets. intel_set_config
9471          * obies this rule, but the modeset restore mode of
9472          * intel_modeset_setup_hw_state does not.
9473          */
9474         *modeset_pipes &= 1 << intel_crtc->pipe;
9475         *prepare_pipes &= 1 << intel_crtc->pipe;
9476
9477         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9478                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9479 }
9480
9481 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9482 {
9483         struct drm_encoder *encoder;
9484         struct drm_device *dev = crtc->dev;
9485
9486         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9487                 if (encoder->crtc == crtc)
9488                         return true;
9489
9490         return false;
9491 }
9492
9493 static void
9494 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9495 {
9496         struct intel_encoder *intel_encoder;
9497         struct intel_crtc *intel_crtc;
9498         struct drm_connector *connector;
9499
9500         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9501                             base.head) {
9502                 if (!intel_encoder->base.crtc)
9503                         continue;
9504
9505                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9506
9507                 if (prepare_pipes & (1 << intel_crtc->pipe))
9508                         intel_encoder->connectors_active = false;
9509         }
9510
9511         intel_modeset_commit_output_state(dev);
9512
9513         /* Double check state. */
9514         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9515                             base.head) {
9516                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9517                 WARN_ON(intel_crtc->new_config &&
9518                         intel_crtc->new_config != &intel_crtc->config);
9519                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9520         }
9521
9522         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9523                 if (!connector->encoder || !connector->encoder->crtc)
9524                         continue;
9525
9526                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9527
9528                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9529                         struct drm_property *dpms_property =
9530                                 dev->mode_config.dpms_property;
9531
9532                         connector->dpms = DRM_MODE_DPMS_ON;
9533                         drm_object_property_set_value(&connector->base,
9534                                                          dpms_property,
9535                                                          DRM_MODE_DPMS_ON);
9536
9537                         intel_encoder = to_intel_encoder(connector->encoder);
9538                         intel_encoder->connectors_active = true;
9539                 }
9540         }
9541
9542 }
9543
9544 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9545 {
9546         int diff;
9547
9548         if (clock1 == clock2)
9549                 return true;
9550
9551         if (!clock1 || !clock2)
9552                 return false;
9553
9554         diff = abs(clock1 - clock2);
9555
9556         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9557                 return true;
9558
9559         return false;
9560 }
9561
9562 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9563         list_for_each_entry((intel_crtc), \
9564                             &(dev)->mode_config.crtc_list, \
9565                             base.head) \
9566                 if (mask & (1 <<(intel_crtc)->pipe))
9567
9568 static bool
9569 intel_pipe_config_compare(struct drm_device *dev,
9570                           struct intel_crtc_config *current_config,
9571                           struct intel_crtc_config *pipe_config)
9572 {
9573 #define PIPE_CONF_CHECK_X(name) \
9574         if (current_config->name != pipe_config->name) { \
9575                 DRM_ERROR("mismatch in " #name " " \
9576                           "(expected 0x%08x, found 0x%08x)\n", \
9577                           current_config->name, \
9578                           pipe_config->name); \
9579                 return false; \
9580         }
9581
9582 #define PIPE_CONF_CHECK_I(name) \
9583         if (current_config->name != pipe_config->name) { \
9584                 DRM_ERROR("mismatch in " #name " " \
9585                           "(expected %i, found %i)\n", \
9586                           current_config->name, \
9587                           pipe_config->name); \
9588                 return false; \
9589         }
9590
9591 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9592         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9593                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9594                           "(expected %i, found %i)\n", \
9595                           current_config->name & (mask), \
9596                           pipe_config->name & (mask)); \
9597                 return false; \
9598         }
9599
9600 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9601         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9602                 DRM_ERROR("mismatch in " #name " " \
9603                           "(expected %i, found %i)\n", \
9604                           current_config->name, \
9605                           pipe_config->name); \
9606                 return false; \
9607         }
9608
9609 #define PIPE_CONF_QUIRK(quirk)  \
9610         ((current_config->quirks | pipe_config->quirks) & (quirk))
9611
9612         PIPE_CONF_CHECK_I(cpu_transcoder);
9613
9614         PIPE_CONF_CHECK_I(has_pch_encoder);
9615         PIPE_CONF_CHECK_I(fdi_lanes);
9616         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9617         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9618         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9619         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9620         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9621
9622         PIPE_CONF_CHECK_I(has_dp_encoder);
9623         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9624         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9625         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9626         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9627         PIPE_CONF_CHECK_I(dp_m_n.tu);
9628
9629         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9630         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9631         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9632         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9633         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9634         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9635
9636         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9637         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9638         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9639         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9640         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9641         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9642
9643         PIPE_CONF_CHECK_I(pixel_multiplier);
9644
9645         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9646                               DRM_MODE_FLAG_INTERLACE);
9647
9648         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9649                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9650                                       DRM_MODE_FLAG_PHSYNC);
9651                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9652                                       DRM_MODE_FLAG_NHSYNC);
9653                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9654                                       DRM_MODE_FLAG_PVSYNC);
9655                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9656                                       DRM_MODE_FLAG_NVSYNC);
9657         }
9658
9659         PIPE_CONF_CHECK_I(pipe_src_w);
9660         PIPE_CONF_CHECK_I(pipe_src_h);
9661
9662         /*
9663          * FIXME: BIOS likes to set up a cloned config with lvds+external
9664          * screen. Since we don't yet re-compute the pipe config when moving
9665          * just the lvds port away to another pipe the sw tracking won't match.
9666          *
9667          * Proper atomic modesets with recomputed global state will fix this.
9668          * Until then just don't check gmch state for inherited modes.
9669          */
9670         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9671                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9672                 /* pfit ratios are autocomputed by the hw on gen4+ */
9673                 if (INTEL_INFO(dev)->gen < 4)
9674                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9675                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9676         }
9677
9678         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9679         if (current_config->pch_pfit.enabled) {
9680                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9681                 PIPE_CONF_CHECK_I(pch_pfit.size);
9682         }
9683
9684         /* BDW+ don't expose a synchronous way to read the state */
9685         if (IS_HASWELL(dev))
9686                 PIPE_CONF_CHECK_I(ips_enabled);
9687
9688         PIPE_CONF_CHECK_I(double_wide);
9689
9690         PIPE_CONF_CHECK_I(shared_dpll);
9691         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9692         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9693         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9694         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9695
9696         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9697                 PIPE_CONF_CHECK_I(pipe_bpp);
9698
9699         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9700         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9701
9702 #undef PIPE_CONF_CHECK_X
9703 #undef PIPE_CONF_CHECK_I
9704 #undef PIPE_CONF_CHECK_FLAGS
9705 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9706 #undef PIPE_CONF_QUIRK
9707
9708         return true;
9709 }
9710
9711 static void
9712 check_connector_state(struct drm_device *dev)
9713 {
9714         struct intel_connector *connector;
9715
9716         list_for_each_entry(connector, &dev->mode_config.connector_list,
9717                             base.head) {
9718                 /* This also checks the encoder/connector hw state with the
9719                  * ->get_hw_state callbacks. */
9720                 intel_connector_check_state(connector);
9721
9722                 WARN(&connector->new_encoder->base != connector->base.encoder,
9723                      "connector's staged encoder doesn't match current encoder\n");
9724         }
9725 }
9726
9727 static void
9728 check_encoder_state(struct drm_device *dev)
9729 {
9730         struct intel_encoder *encoder;
9731         struct intel_connector *connector;
9732
9733         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9734                             base.head) {
9735                 bool enabled = false;
9736                 bool active = false;
9737                 enum pipe pipe, tracked_pipe;
9738
9739                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9740                               encoder->base.base.id,
9741                               drm_get_encoder_name(&encoder->base));
9742
9743                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9744                      "encoder's stage crtc doesn't match current crtc\n");
9745                 WARN(encoder->connectors_active && !encoder->base.crtc,
9746                      "encoder's active_connectors set, but no crtc\n");
9747
9748                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9749                                     base.head) {
9750                         if (connector->base.encoder != &encoder->base)
9751                                 continue;
9752                         enabled = true;
9753                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9754                                 active = true;
9755                 }
9756                 WARN(!!encoder->base.crtc != enabled,
9757                      "encoder's enabled state mismatch "
9758                      "(expected %i, found %i)\n",
9759                      !!encoder->base.crtc, enabled);
9760                 WARN(active && !encoder->base.crtc,
9761                      "active encoder with no crtc\n");
9762
9763                 WARN(encoder->connectors_active != active,
9764                      "encoder's computed active state doesn't match tracked active state "
9765                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9766
9767                 active = encoder->get_hw_state(encoder, &pipe);
9768                 WARN(active != encoder->connectors_active,
9769                      "encoder's hw state doesn't match sw tracking "
9770                      "(expected %i, found %i)\n",
9771                      encoder->connectors_active, active);
9772
9773                 if (!encoder->base.crtc)
9774                         continue;
9775
9776                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9777                 WARN(active && pipe != tracked_pipe,
9778                      "active encoder's pipe doesn't match"
9779                      "(expected %i, found %i)\n",
9780                      tracked_pipe, pipe);
9781
9782         }
9783 }
9784
9785 static void
9786 check_crtc_state(struct drm_device *dev)
9787 {
9788         struct drm_i915_private *dev_priv = dev->dev_private;
9789         struct intel_crtc *crtc;
9790         struct intel_encoder *encoder;
9791         struct intel_crtc_config pipe_config;
9792
9793         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9794                             base.head) {
9795                 bool enabled = false;
9796                 bool active = false;
9797
9798                 memset(&pipe_config, 0, sizeof(pipe_config));
9799
9800                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9801                               crtc->base.base.id);
9802
9803                 WARN(crtc->active && !crtc->base.enabled,
9804                      "active crtc, but not enabled in sw tracking\n");
9805
9806                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9807                                     base.head) {
9808                         if (encoder->base.crtc != &crtc->base)
9809                                 continue;
9810                         enabled = true;
9811                         if (encoder->connectors_active)
9812                                 active = true;
9813                 }
9814
9815                 WARN(active != crtc->active,
9816                      "crtc's computed active state doesn't match tracked active state "
9817                      "(expected %i, found %i)\n", active, crtc->active);
9818                 WARN(enabled != crtc->base.enabled,
9819                      "crtc's computed enabled state doesn't match tracked enabled state "
9820                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9821
9822                 active = dev_priv->display.get_pipe_config(crtc,
9823                                                            &pipe_config);
9824
9825                 /* hw state is inconsistent with the pipe A quirk */
9826                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9827                         active = crtc->active;
9828
9829                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9830                                     base.head) {
9831                         enum pipe pipe;
9832                         if (encoder->base.crtc != &crtc->base)
9833                                 continue;
9834                         if (encoder->get_hw_state(encoder, &pipe))
9835                                 encoder->get_config(encoder, &pipe_config);
9836                 }
9837
9838                 WARN(crtc->active != active,
9839                      "crtc active state doesn't match with hw state "
9840                      "(expected %i, found %i)\n", crtc->active, active);
9841
9842                 if (active &&
9843                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9844                         WARN(1, "pipe state doesn't match!\n");
9845                         intel_dump_pipe_config(crtc, &pipe_config,
9846                                                "[hw state]");
9847                         intel_dump_pipe_config(crtc, &crtc->config,
9848                                                "[sw state]");
9849                 }
9850         }
9851 }
9852
9853 static void
9854 check_shared_dpll_state(struct drm_device *dev)
9855 {
9856         struct drm_i915_private *dev_priv = dev->dev_private;
9857         struct intel_crtc *crtc;
9858         struct intel_dpll_hw_state dpll_hw_state;
9859         int i;
9860
9861         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9862                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9863                 int enabled_crtcs = 0, active_crtcs = 0;
9864                 bool active;
9865
9866                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9867
9868                 DRM_DEBUG_KMS("%s\n", pll->name);
9869
9870                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9871
9872                 WARN(pll->active > pll->refcount,
9873                      "more active pll users than references: %i vs %i\n",
9874                      pll->active, pll->refcount);
9875                 WARN(pll->active && !pll->on,
9876                      "pll in active use but not on in sw tracking\n");
9877                 WARN(pll->on && !pll->active,
9878                      "pll in on but not on in use in sw tracking\n");
9879                 WARN(pll->on != active,
9880                      "pll on state mismatch (expected %i, found %i)\n",
9881                      pll->on, active);
9882
9883                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9884                                     base.head) {
9885                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9886                                 enabled_crtcs++;
9887                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9888                                 active_crtcs++;
9889                 }
9890                 WARN(pll->active != active_crtcs,
9891                      "pll active crtcs mismatch (expected %i, found %i)\n",
9892                      pll->active, active_crtcs);
9893                 WARN(pll->refcount != enabled_crtcs,
9894                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9895                      pll->refcount, enabled_crtcs);
9896
9897                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9898                                        sizeof(dpll_hw_state)),
9899                      "pll hw state mismatch\n");
9900         }
9901 }
9902
9903 void
9904 intel_modeset_check_state(struct drm_device *dev)
9905 {
9906         check_connector_state(dev);
9907         check_encoder_state(dev);
9908         check_crtc_state(dev);
9909         check_shared_dpll_state(dev);
9910 }
9911
9912 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9913                                      int dotclock)
9914 {
9915         /*
9916          * FDI already provided one idea for the dotclock.
9917          * Yell if the encoder disagrees.
9918          */
9919         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9920              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9921              pipe_config->adjusted_mode.crtc_clock, dotclock);
9922 }
9923
9924 static int __intel_set_mode(struct drm_crtc *crtc,
9925                             struct drm_display_mode *mode,
9926                             int x, int y, struct drm_framebuffer *fb)
9927 {
9928         struct drm_device *dev = crtc->dev;
9929         struct drm_i915_private *dev_priv = dev->dev_private;
9930         struct drm_display_mode *saved_mode;
9931         struct intel_crtc_config *pipe_config = NULL;
9932         struct intel_crtc *intel_crtc;
9933         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9934         int ret = 0;
9935
9936         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9937         if (!saved_mode)
9938                 return -ENOMEM;
9939
9940         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9941                                      &prepare_pipes, &disable_pipes);
9942
9943         *saved_mode = crtc->mode;
9944
9945         /* Hack: Because we don't (yet) support global modeset on multiple
9946          * crtcs, we don't keep track of the new mode for more than one crtc.
9947          * Hence simply check whether any bit is set in modeset_pipes in all the
9948          * pieces of code that are not yet converted to deal with mutliple crtcs
9949          * changing their mode at the same time. */
9950         if (modeset_pipes) {
9951                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9952                 if (IS_ERR(pipe_config)) {
9953                         ret = PTR_ERR(pipe_config);
9954                         pipe_config = NULL;
9955
9956                         goto out;
9957                 }
9958                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9959                                        "[modeset]");
9960                 to_intel_crtc(crtc)->new_config = pipe_config;
9961         }
9962
9963         /*
9964          * See if the config requires any additional preparation, e.g.
9965          * to adjust global state with pipes off.  We need to do this
9966          * here so we can get the modeset_pipe updated config for the new
9967          * mode set on this crtc.  For other crtcs we need to use the
9968          * adjusted_mode bits in the crtc directly.
9969          */
9970         if (IS_VALLEYVIEW(dev)) {
9971                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9972
9973                 /* may have added more to prepare_pipes than we should */
9974                 prepare_pipes &= ~disable_pipes;
9975         }
9976
9977         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9978                 intel_crtc_disable(&intel_crtc->base);
9979
9980         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9981                 if (intel_crtc->base.enabled)
9982                         dev_priv->display.crtc_disable(&intel_crtc->base);
9983         }
9984
9985         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9986          * to set it here already despite that we pass it down the callchain.
9987          */
9988         if (modeset_pipes) {
9989                 crtc->mode = *mode;
9990                 /* mode_set/enable/disable functions rely on a correct pipe
9991                  * config. */
9992                 to_intel_crtc(crtc)->config = *pipe_config;
9993                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9994
9995                 /*
9996                  * Calculate and store various constants which
9997                  * are later needed by vblank and swap-completion
9998                  * timestamping. They are derived from true hwmode.
9999                  */
10000                 drm_calc_timestamping_constants(crtc,
10001                                                 &pipe_config->adjusted_mode);
10002         }
10003
10004         /* Only after disabling all output pipelines that will be changed can we
10005          * update the the output configuration. */
10006         intel_modeset_update_state(dev, prepare_pipes);
10007
10008         if (dev_priv->display.modeset_global_resources)
10009                 dev_priv->display.modeset_global_resources(dev);
10010
10011         /* Set up the DPLL and any encoders state that needs to adjust or depend
10012          * on the DPLL.
10013          */
10014         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10015                 ret = intel_crtc_mode_set(&intel_crtc->base,
10016                                           x, y, fb);
10017                 if (ret)
10018                         goto done;
10019         }
10020
10021         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10022         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10023                 dev_priv->display.crtc_enable(&intel_crtc->base);
10024
10025         /* FIXME: add subpixel order */
10026 done:
10027         if (ret && crtc->enabled)
10028                 crtc->mode = *saved_mode;
10029
10030 out:
10031         kfree(pipe_config);
10032         kfree(saved_mode);
10033         return ret;
10034 }
10035
10036 static int intel_set_mode(struct drm_crtc *crtc,
10037                           struct drm_display_mode *mode,
10038                           int x, int y, struct drm_framebuffer *fb)
10039 {
10040         int ret;
10041
10042         ret = __intel_set_mode(crtc, mode, x, y, fb);
10043
10044         if (ret == 0)
10045                 intel_modeset_check_state(crtc->dev);
10046
10047         return ret;
10048 }
10049
10050 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10051 {
10052         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10053 }
10054
10055 #undef for_each_intel_crtc_masked
10056
10057 static void intel_set_config_free(struct intel_set_config *config)
10058 {
10059         if (!config)
10060                 return;
10061
10062         kfree(config->save_connector_encoders);
10063         kfree(config->save_encoder_crtcs);
10064         kfree(config->save_crtc_enabled);
10065         kfree(config);
10066 }
10067
10068 static int intel_set_config_save_state(struct drm_device *dev,
10069                                        struct intel_set_config *config)
10070 {
10071         struct drm_crtc *crtc;
10072         struct drm_encoder *encoder;
10073         struct drm_connector *connector;
10074         int count;
10075
10076         config->save_crtc_enabled =
10077                 kcalloc(dev->mode_config.num_crtc,
10078                         sizeof(bool), GFP_KERNEL);
10079         if (!config->save_crtc_enabled)
10080                 return -ENOMEM;
10081
10082         config->save_encoder_crtcs =
10083                 kcalloc(dev->mode_config.num_encoder,
10084                         sizeof(struct drm_crtc *), GFP_KERNEL);
10085         if (!config->save_encoder_crtcs)
10086                 return -ENOMEM;
10087
10088         config->save_connector_encoders =
10089                 kcalloc(dev->mode_config.num_connector,
10090                         sizeof(struct drm_encoder *), GFP_KERNEL);
10091         if (!config->save_connector_encoders)
10092                 return -ENOMEM;
10093
10094         /* Copy data. Note that driver private data is not affected.
10095          * Should anything bad happen only the expected state is
10096          * restored, not the drivers personal bookkeeping.
10097          */
10098         count = 0;
10099         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10100                 config->save_crtc_enabled[count++] = crtc->enabled;
10101         }
10102
10103         count = 0;
10104         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10105                 config->save_encoder_crtcs[count++] = encoder->crtc;
10106         }
10107
10108         count = 0;
10109         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10110                 config->save_connector_encoders[count++] = connector->encoder;
10111         }
10112
10113         return 0;
10114 }
10115
10116 static void intel_set_config_restore_state(struct drm_device *dev,
10117                                            struct intel_set_config *config)
10118 {
10119         struct intel_crtc *crtc;
10120         struct intel_encoder *encoder;
10121         struct intel_connector *connector;
10122         int count;
10123
10124         count = 0;
10125         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10126                 crtc->new_enabled = config->save_crtc_enabled[count++];
10127
10128                 if (crtc->new_enabled)
10129                         crtc->new_config = &crtc->config;
10130                 else
10131                         crtc->new_config = NULL;
10132         }
10133
10134         count = 0;
10135         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10136                 encoder->new_crtc =
10137                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10138         }
10139
10140         count = 0;
10141         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10142                 connector->new_encoder =
10143                         to_intel_encoder(config->save_connector_encoders[count++]);
10144         }
10145 }
10146
10147 static bool
10148 is_crtc_connector_off(struct drm_mode_set *set)
10149 {
10150         int i;
10151
10152         if (set->num_connectors == 0)
10153                 return false;
10154
10155         if (WARN_ON(set->connectors == NULL))
10156                 return false;
10157
10158         for (i = 0; i < set->num_connectors; i++)
10159                 if (set->connectors[i]->encoder &&
10160                     set->connectors[i]->encoder->crtc == set->crtc &&
10161                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10162                         return true;
10163
10164         return false;
10165 }
10166
10167 static void
10168 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10169                                       struct intel_set_config *config)
10170 {
10171
10172         /* We should be able to check here if the fb has the same properties
10173          * and then just flip_or_move it */
10174         if (is_crtc_connector_off(set)) {
10175                 config->mode_changed = true;
10176         } else if (set->crtc->primary->fb != set->fb) {
10177                 /* If we have no fb then treat it as a full mode set */
10178                 if (set->crtc->primary->fb == NULL) {
10179                         struct intel_crtc *intel_crtc =
10180                                 to_intel_crtc(set->crtc);
10181
10182                         if (intel_crtc->active && i915.fastboot) {
10183                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10184                                 config->fb_changed = true;
10185                         } else {
10186                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10187                                 config->mode_changed = true;
10188                         }
10189                 } else if (set->fb == NULL) {
10190                         config->mode_changed = true;
10191                 } else if (set->fb->pixel_format !=
10192                            set->crtc->primary->fb->pixel_format) {
10193                         config->mode_changed = true;
10194                 } else {
10195                         config->fb_changed = true;
10196                 }
10197         }
10198
10199         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10200                 config->fb_changed = true;
10201
10202         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10203                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10204                 drm_mode_debug_printmodeline(&set->crtc->mode);
10205                 drm_mode_debug_printmodeline(set->mode);
10206                 config->mode_changed = true;
10207         }
10208
10209         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10210                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10211 }
10212
10213 static int
10214 intel_modeset_stage_output_state(struct drm_device *dev,
10215                                  struct drm_mode_set *set,
10216                                  struct intel_set_config *config)
10217 {
10218         struct intel_connector *connector;
10219         struct intel_encoder *encoder;
10220         struct intel_crtc *crtc;
10221         int ro;
10222
10223         /* The upper layers ensure that we either disable a crtc or have a list
10224          * of connectors. For paranoia, double-check this. */
10225         WARN_ON(!set->fb && (set->num_connectors != 0));
10226         WARN_ON(set->fb && (set->num_connectors == 0));
10227
10228         list_for_each_entry(connector, &dev->mode_config.connector_list,
10229                             base.head) {
10230                 /* Otherwise traverse passed in connector list and get encoders
10231                  * for them. */
10232                 for (ro = 0; ro < set->num_connectors; ro++) {
10233                         if (set->connectors[ro] == &connector->base) {
10234                                 connector->new_encoder = connector->encoder;
10235                                 break;
10236                         }
10237                 }
10238
10239                 /* If we disable the crtc, disable all its connectors. Also, if
10240                  * the connector is on the changing crtc but not on the new
10241                  * connector list, disable it. */
10242                 if ((!set->fb || ro == set->num_connectors) &&
10243                     connector->base.encoder &&
10244                     connector->base.encoder->crtc == set->crtc) {
10245                         connector->new_encoder = NULL;
10246
10247                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10248                                 connector->base.base.id,
10249                                 drm_get_connector_name(&connector->base));
10250                 }
10251
10252
10253                 if (&connector->new_encoder->base != connector->base.encoder) {
10254                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10255                         config->mode_changed = true;
10256                 }
10257         }
10258         /* connector->new_encoder is now updated for all connectors. */
10259
10260         /* Update crtc of enabled connectors. */
10261         list_for_each_entry(connector, &dev->mode_config.connector_list,
10262                             base.head) {
10263                 struct drm_crtc *new_crtc;
10264
10265                 if (!connector->new_encoder)
10266                         continue;
10267
10268                 new_crtc = connector->new_encoder->base.crtc;
10269
10270                 for (ro = 0; ro < set->num_connectors; ro++) {
10271                         if (set->connectors[ro] == &connector->base)
10272                                 new_crtc = set->crtc;
10273                 }
10274
10275                 /* Make sure the new CRTC will work with the encoder */
10276                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10277                                          new_crtc)) {
10278                         return -EINVAL;
10279                 }
10280                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10281
10282                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10283                         connector->base.base.id,
10284                         drm_get_connector_name(&connector->base),
10285                         new_crtc->base.id);
10286         }
10287
10288         /* Check for any encoders that needs to be disabled. */
10289         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10290                             base.head) {
10291                 int num_connectors = 0;
10292                 list_for_each_entry(connector,
10293                                     &dev->mode_config.connector_list,
10294                                     base.head) {
10295                         if (connector->new_encoder == encoder) {
10296                                 WARN_ON(!connector->new_encoder->new_crtc);
10297                                 num_connectors++;
10298                         }
10299                 }
10300
10301                 if (num_connectors == 0)
10302                         encoder->new_crtc = NULL;
10303                 else if (num_connectors > 1)
10304                         return -EINVAL;
10305
10306                 /* Only now check for crtc changes so we don't miss encoders
10307                  * that will be disabled. */
10308                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10309                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10310                         config->mode_changed = true;
10311                 }
10312         }
10313         /* Now we've also updated encoder->new_crtc for all encoders. */
10314
10315         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10316                             base.head) {
10317                 crtc->new_enabled = false;
10318
10319                 list_for_each_entry(encoder,
10320                                     &dev->mode_config.encoder_list,
10321                                     base.head) {
10322                         if (encoder->new_crtc == crtc) {
10323                                 crtc->new_enabled = true;
10324                                 break;
10325                         }
10326                 }
10327
10328                 if (crtc->new_enabled != crtc->base.enabled) {
10329                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10330                                       crtc->new_enabled ? "en" : "dis");
10331                         config->mode_changed = true;
10332                 }
10333
10334                 if (crtc->new_enabled)
10335                         crtc->new_config = &crtc->config;
10336                 else
10337                         crtc->new_config = NULL;
10338         }
10339
10340         return 0;
10341 }
10342
10343 static void disable_crtc_nofb(struct intel_crtc *crtc)
10344 {
10345         struct drm_device *dev = crtc->base.dev;
10346         struct intel_encoder *encoder;
10347         struct intel_connector *connector;
10348
10349         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10350                       pipe_name(crtc->pipe));
10351
10352         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10353                 if (connector->new_encoder &&
10354                     connector->new_encoder->new_crtc == crtc)
10355                         connector->new_encoder = NULL;
10356         }
10357
10358         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10359                 if (encoder->new_crtc == crtc)
10360                         encoder->new_crtc = NULL;
10361         }
10362
10363         crtc->new_enabled = false;
10364         crtc->new_config = NULL;
10365 }
10366
10367 static int intel_crtc_set_config(struct drm_mode_set *set)
10368 {
10369         struct drm_device *dev;
10370         struct drm_mode_set save_set;
10371         struct intel_set_config *config;
10372         int ret;
10373
10374         BUG_ON(!set);
10375         BUG_ON(!set->crtc);
10376         BUG_ON(!set->crtc->helper_private);
10377
10378         /* Enforce sane interface api - has been abused by the fb helper. */
10379         BUG_ON(!set->mode && set->fb);
10380         BUG_ON(set->fb && set->num_connectors == 0);
10381
10382         if (set->fb) {
10383                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10384                                 set->crtc->base.id, set->fb->base.id,
10385                                 (int)set->num_connectors, set->x, set->y);
10386         } else {
10387                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10388         }
10389
10390         dev = set->crtc->dev;
10391
10392         ret = -ENOMEM;
10393         config = kzalloc(sizeof(*config), GFP_KERNEL);
10394         if (!config)
10395                 goto out_config;
10396
10397         ret = intel_set_config_save_state(dev, config);
10398         if (ret)
10399                 goto out_config;
10400
10401         save_set.crtc = set->crtc;
10402         save_set.mode = &set->crtc->mode;
10403         save_set.x = set->crtc->x;
10404         save_set.y = set->crtc->y;
10405         save_set.fb = set->crtc->primary->fb;
10406
10407         /* Compute whether we need a full modeset, only an fb base update or no
10408          * change at all. In the future we might also check whether only the
10409          * mode changed, e.g. for LVDS where we only change the panel fitter in
10410          * such cases. */
10411         intel_set_config_compute_mode_changes(set, config);
10412
10413         ret = intel_modeset_stage_output_state(dev, set, config);
10414         if (ret)
10415                 goto fail;
10416
10417         if (config->mode_changed) {
10418                 ret = intel_set_mode(set->crtc, set->mode,
10419                                      set->x, set->y, set->fb);
10420         } else if (config->fb_changed) {
10421                 intel_crtc_wait_for_pending_flips(set->crtc);
10422
10423                 ret = intel_pipe_set_base(set->crtc,
10424                                           set->x, set->y, set->fb);
10425                 /*
10426                  * In the fastboot case this may be our only check of the
10427                  * state after boot.  It would be better to only do it on
10428                  * the first update, but we don't have a nice way of doing that
10429                  * (and really, set_config isn't used much for high freq page
10430                  * flipping, so increasing its cost here shouldn't be a big
10431                  * deal).
10432                  */
10433                 if (i915.fastboot && ret == 0)
10434                         intel_modeset_check_state(set->crtc->dev);
10435         }
10436
10437         if (ret) {
10438                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10439                               set->crtc->base.id, ret);
10440 fail:
10441                 intel_set_config_restore_state(dev, config);
10442
10443                 /*
10444                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10445                  * force the pipe off to avoid oopsing in the modeset code
10446                  * due to fb==NULL. This should only happen during boot since
10447                  * we don't yet reconstruct the FB from the hardware state.
10448                  */
10449                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10450                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10451
10452                 /* Try to restore the config */
10453                 if (config->mode_changed &&
10454                     intel_set_mode(save_set.crtc, save_set.mode,
10455                                    save_set.x, save_set.y, save_set.fb))
10456                         DRM_ERROR("failed to restore config after modeset failure\n");
10457         }
10458
10459 out_config:
10460         intel_set_config_free(config);
10461         return ret;
10462 }
10463
10464 static const struct drm_crtc_funcs intel_crtc_funcs = {
10465         .cursor_set = intel_crtc_cursor_set,
10466         .cursor_move = intel_crtc_cursor_move,
10467         .gamma_set = intel_crtc_gamma_set,
10468         .set_config = intel_crtc_set_config,
10469         .destroy = intel_crtc_destroy,
10470         .page_flip = intel_crtc_page_flip,
10471 };
10472
10473 static void intel_cpu_pll_init(struct drm_device *dev)
10474 {
10475         if (HAS_DDI(dev))
10476                 intel_ddi_pll_init(dev);
10477 }
10478
10479 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10480                                       struct intel_shared_dpll *pll,
10481                                       struct intel_dpll_hw_state *hw_state)
10482 {
10483         uint32_t val;
10484
10485         val = I915_READ(PCH_DPLL(pll->id));
10486         hw_state->dpll = val;
10487         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10488         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10489
10490         return val & DPLL_VCO_ENABLE;
10491 }
10492
10493 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10494                                   struct intel_shared_dpll *pll)
10495 {
10496         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10497         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10498 }
10499
10500 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10501                                 struct intel_shared_dpll *pll)
10502 {
10503         /* PCH refclock must be enabled first */
10504         ibx_assert_pch_refclk_enabled(dev_priv);
10505
10506         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10507
10508         /* Wait for the clocks to stabilize. */
10509         POSTING_READ(PCH_DPLL(pll->id));
10510         udelay(150);
10511
10512         /* The pixel multiplier can only be updated once the
10513          * DPLL is enabled and the clocks are stable.
10514          *
10515          * So write it again.
10516          */
10517         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10518         POSTING_READ(PCH_DPLL(pll->id));
10519         udelay(200);
10520 }
10521
10522 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10523                                  struct intel_shared_dpll *pll)
10524 {
10525         struct drm_device *dev = dev_priv->dev;
10526         struct intel_crtc *crtc;
10527
10528         /* Make sure no transcoder isn't still depending on us. */
10529         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10530                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10531                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10532         }
10533
10534         I915_WRITE(PCH_DPLL(pll->id), 0);
10535         POSTING_READ(PCH_DPLL(pll->id));
10536         udelay(200);
10537 }
10538
10539 static char *ibx_pch_dpll_names[] = {
10540         "PCH DPLL A",
10541         "PCH DPLL B",
10542 };
10543
10544 static void ibx_pch_dpll_init(struct drm_device *dev)
10545 {
10546         struct drm_i915_private *dev_priv = dev->dev_private;
10547         int i;
10548
10549         dev_priv->num_shared_dpll = 2;
10550
10551         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10552                 dev_priv->shared_dplls[i].id = i;
10553                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10554                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10555                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10556                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10557                 dev_priv->shared_dplls[i].get_hw_state =
10558                         ibx_pch_dpll_get_hw_state;
10559         }
10560 }
10561
10562 static void intel_shared_dpll_init(struct drm_device *dev)
10563 {
10564         struct drm_i915_private *dev_priv = dev->dev_private;
10565
10566         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10567                 ibx_pch_dpll_init(dev);
10568         else
10569                 dev_priv->num_shared_dpll = 0;
10570
10571         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10572 }
10573
10574 static void intel_crtc_init(struct drm_device *dev, int pipe)
10575 {
10576         struct drm_i915_private *dev_priv = dev->dev_private;
10577         struct intel_crtc *intel_crtc;
10578         int i;
10579
10580         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10581         if (intel_crtc == NULL)
10582                 return;
10583
10584         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10585
10586         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10587         for (i = 0; i < 256; i++) {
10588                 intel_crtc->lut_r[i] = i;
10589                 intel_crtc->lut_g[i] = i;
10590                 intel_crtc->lut_b[i] = i;
10591         }
10592
10593         /*
10594          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10595          * is hooked to plane B. Hence we want plane A feeding pipe B.
10596          */
10597         intel_crtc->pipe = pipe;
10598         intel_crtc->plane = pipe;
10599         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10600                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10601                 intel_crtc->plane = !pipe;
10602         }
10603
10604         init_waitqueue_head(&intel_crtc->vbl_wait);
10605
10606         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10607                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10608         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10609         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10610
10611         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10612 }
10613
10614 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10615 {
10616         struct drm_encoder *encoder = connector->base.encoder;
10617
10618         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10619
10620         if (!encoder)
10621                 return INVALID_PIPE;
10622
10623         return to_intel_crtc(encoder->crtc)->pipe;
10624 }
10625
10626 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10627                                 struct drm_file *file)
10628 {
10629         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10630         struct drm_mode_object *drmmode_obj;
10631         struct intel_crtc *crtc;
10632
10633         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10634                 return -ENODEV;
10635
10636         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10637                         DRM_MODE_OBJECT_CRTC);
10638
10639         if (!drmmode_obj) {
10640                 DRM_ERROR("no such CRTC id\n");
10641                 return -ENOENT;
10642         }
10643
10644         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10645         pipe_from_crtc_id->pipe = crtc->pipe;
10646
10647         return 0;
10648 }
10649
10650 static int intel_encoder_clones(struct intel_encoder *encoder)
10651 {
10652         struct drm_device *dev = encoder->base.dev;
10653         struct intel_encoder *source_encoder;
10654         int index_mask = 0;
10655         int entry = 0;
10656
10657         list_for_each_entry(source_encoder,
10658                             &dev->mode_config.encoder_list, base.head) {
10659                 if (encoders_cloneable(encoder, source_encoder))
10660                         index_mask |= (1 << entry);
10661
10662                 entry++;
10663         }
10664
10665         return index_mask;
10666 }
10667
10668 static bool has_edp_a(struct drm_device *dev)
10669 {
10670         struct drm_i915_private *dev_priv = dev->dev_private;
10671
10672         if (!IS_MOBILE(dev))
10673                 return false;
10674
10675         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10676                 return false;
10677
10678         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10679                 return false;
10680
10681         return true;
10682 }
10683
10684 const char *intel_output_name(int output)
10685 {
10686         static const char *names[] = {
10687                 [INTEL_OUTPUT_UNUSED] = "Unused",
10688                 [INTEL_OUTPUT_ANALOG] = "Analog",
10689                 [INTEL_OUTPUT_DVO] = "DVO",
10690                 [INTEL_OUTPUT_SDVO] = "SDVO",
10691                 [INTEL_OUTPUT_LVDS] = "LVDS",
10692                 [INTEL_OUTPUT_TVOUT] = "TV",
10693                 [INTEL_OUTPUT_HDMI] = "HDMI",
10694                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10695                 [INTEL_OUTPUT_EDP] = "eDP",
10696                 [INTEL_OUTPUT_DSI] = "DSI",
10697                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10698         };
10699
10700         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10701                 return "Invalid";
10702
10703         return names[output];
10704 }
10705
10706 static void intel_setup_outputs(struct drm_device *dev)
10707 {
10708         struct drm_i915_private *dev_priv = dev->dev_private;
10709         struct intel_encoder *encoder;
10710         bool dpd_is_edp = false;
10711
10712         intel_lvds_init(dev);
10713
10714         if (!IS_ULT(dev))
10715                 intel_crt_init(dev);
10716
10717         if (HAS_DDI(dev)) {
10718                 int found;
10719
10720                 /* Haswell uses DDI functions to detect digital outputs */
10721                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10722                 /* DDI A only supports eDP */
10723                 if (found)
10724                         intel_ddi_init(dev, PORT_A);
10725
10726                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10727                  * register */
10728                 found = I915_READ(SFUSE_STRAP);
10729
10730                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10731                         intel_ddi_init(dev, PORT_B);
10732                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10733                         intel_ddi_init(dev, PORT_C);
10734                 if (found & SFUSE_STRAP_DDID_DETECTED)
10735                         intel_ddi_init(dev, PORT_D);
10736         } else if (HAS_PCH_SPLIT(dev)) {
10737                 int found;
10738                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10739
10740                 if (has_edp_a(dev))
10741                         intel_dp_init(dev, DP_A, PORT_A);
10742
10743                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10744                         /* PCH SDVOB multiplex with HDMIB */
10745                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10746                         if (!found)
10747                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10748                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10749                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10750                 }
10751
10752                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10753                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10754
10755                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10756                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10757
10758                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10759                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10760
10761                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10762                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10763         } else if (IS_VALLEYVIEW(dev)) {
10764                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10765                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10766                                         PORT_B);
10767                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10768                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10769                 }
10770
10771                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10772                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10773                                         PORT_C);
10774                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10775                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10776                 }
10777
10778                 intel_dsi_init(dev);
10779         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10780                 bool found = false;
10781
10782                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10783                         DRM_DEBUG_KMS("probing SDVOB\n");
10784                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10785                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10786                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10787                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10788                         }
10789
10790                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10791                                 intel_dp_init(dev, DP_B, PORT_B);
10792                 }
10793
10794                 /* Before G4X SDVOC doesn't have its own detect register */
10795
10796                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10797                         DRM_DEBUG_KMS("probing SDVOC\n");
10798                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10799                 }
10800
10801                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10802
10803                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10804                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10805                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10806                         }
10807                         if (SUPPORTS_INTEGRATED_DP(dev))
10808                                 intel_dp_init(dev, DP_C, PORT_C);
10809                 }
10810
10811                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10812                     (I915_READ(DP_D) & DP_DETECTED))
10813                         intel_dp_init(dev, DP_D, PORT_D);
10814         } else if (IS_GEN2(dev))
10815                 intel_dvo_init(dev);
10816
10817         if (SUPPORTS_TV(dev))
10818                 intel_tv_init(dev);
10819
10820         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10821                 encoder->base.possible_crtcs = encoder->crtc_mask;
10822                 encoder->base.possible_clones =
10823                         intel_encoder_clones(encoder);
10824         }
10825
10826         intel_init_pch_refclk(dev);
10827
10828         drm_helper_move_panel_connectors_to_head(dev);
10829 }
10830
10831 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10832 {
10833         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10834
10835         drm_framebuffer_cleanup(fb);
10836         WARN_ON(!intel_fb->obj->framebuffer_references--);
10837         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10838         kfree(intel_fb);
10839 }
10840
10841 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10842                                                 struct drm_file *file,
10843                                                 unsigned int *handle)
10844 {
10845         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10846         struct drm_i915_gem_object *obj = intel_fb->obj;
10847
10848         return drm_gem_handle_create(file, &obj->base, handle);
10849 }
10850
10851 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10852         .destroy = intel_user_framebuffer_destroy,
10853         .create_handle = intel_user_framebuffer_create_handle,
10854 };
10855
10856 static int intel_framebuffer_init(struct drm_device *dev,
10857                                   struct intel_framebuffer *intel_fb,
10858                                   struct drm_mode_fb_cmd2 *mode_cmd,
10859                                   struct drm_i915_gem_object *obj)
10860 {
10861         int aligned_height;
10862         int pitch_limit;
10863         int ret;
10864
10865         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10866
10867         if (obj->tiling_mode == I915_TILING_Y) {
10868                 DRM_DEBUG("hardware does not support tiling Y\n");
10869                 return -EINVAL;
10870         }
10871
10872         if (mode_cmd->pitches[0] & 63) {
10873                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10874                           mode_cmd->pitches[0]);
10875                 return -EINVAL;
10876         }
10877
10878         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10879                 pitch_limit = 32*1024;
10880         } else if (INTEL_INFO(dev)->gen >= 4) {
10881                 if (obj->tiling_mode)
10882                         pitch_limit = 16*1024;
10883                 else
10884                         pitch_limit = 32*1024;
10885         } else if (INTEL_INFO(dev)->gen >= 3) {
10886                 if (obj->tiling_mode)
10887                         pitch_limit = 8*1024;
10888                 else
10889                         pitch_limit = 16*1024;
10890         } else
10891                 /* XXX DSPC is limited to 4k tiled */
10892                 pitch_limit = 8*1024;
10893
10894         if (mode_cmd->pitches[0] > pitch_limit) {
10895                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10896                           obj->tiling_mode ? "tiled" : "linear",
10897                           mode_cmd->pitches[0], pitch_limit);
10898                 return -EINVAL;
10899         }
10900
10901         if (obj->tiling_mode != I915_TILING_NONE &&
10902             mode_cmd->pitches[0] != obj->stride) {
10903                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10904                           mode_cmd->pitches[0], obj->stride);
10905                 return -EINVAL;
10906         }
10907
10908         /* Reject formats not supported by any plane early. */
10909         switch (mode_cmd->pixel_format) {
10910         case DRM_FORMAT_C8:
10911         case DRM_FORMAT_RGB565:
10912         case DRM_FORMAT_XRGB8888:
10913         case DRM_FORMAT_ARGB8888:
10914                 break;
10915         case DRM_FORMAT_XRGB1555:
10916         case DRM_FORMAT_ARGB1555:
10917                 if (INTEL_INFO(dev)->gen > 3) {
10918                         DRM_DEBUG("unsupported pixel format: %s\n",
10919                                   drm_get_format_name(mode_cmd->pixel_format));
10920                         return -EINVAL;
10921                 }
10922                 break;
10923         case DRM_FORMAT_XBGR8888:
10924         case DRM_FORMAT_ABGR8888:
10925         case DRM_FORMAT_XRGB2101010:
10926         case DRM_FORMAT_ARGB2101010:
10927         case DRM_FORMAT_XBGR2101010:
10928         case DRM_FORMAT_ABGR2101010:
10929                 if (INTEL_INFO(dev)->gen < 4) {
10930                         DRM_DEBUG("unsupported pixel format: %s\n",
10931                                   drm_get_format_name(mode_cmd->pixel_format));
10932                         return -EINVAL;
10933                 }
10934                 break;
10935         case DRM_FORMAT_YUYV:
10936         case DRM_FORMAT_UYVY:
10937         case DRM_FORMAT_YVYU:
10938         case DRM_FORMAT_VYUY:
10939                 if (INTEL_INFO(dev)->gen < 5) {
10940                         DRM_DEBUG("unsupported pixel format: %s\n",
10941                                   drm_get_format_name(mode_cmd->pixel_format));
10942                         return -EINVAL;
10943                 }
10944                 break;
10945         default:
10946                 DRM_DEBUG("unsupported pixel format: %s\n",
10947                           drm_get_format_name(mode_cmd->pixel_format));
10948                 return -EINVAL;
10949         }
10950
10951         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10952         if (mode_cmd->offsets[0] != 0)
10953                 return -EINVAL;
10954
10955         aligned_height = intel_align_height(dev, mode_cmd->height,
10956                                             obj->tiling_mode);
10957         /* FIXME drm helper for size checks (especially planar formats)? */
10958         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10959                 return -EINVAL;
10960
10961         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10962         intel_fb->obj = obj;
10963         intel_fb->obj->framebuffer_references++;
10964
10965         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10966         if (ret) {
10967                 DRM_ERROR("framebuffer init failed %d\n", ret);
10968                 return ret;
10969         }
10970
10971         return 0;
10972 }
10973
10974 static struct drm_framebuffer *
10975 intel_user_framebuffer_create(struct drm_device *dev,
10976                               struct drm_file *filp,
10977                               struct drm_mode_fb_cmd2 *mode_cmd)
10978 {
10979         struct drm_i915_gem_object *obj;
10980
10981         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10982                                                 mode_cmd->handles[0]));
10983         if (&obj->base == NULL)
10984                 return ERR_PTR(-ENOENT);
10985
10986         return intel_framebuffer_create(dev, mode_cmd, obj);
10987 }
10988
10989 #ifndef CONFIG_DRM_I915_FBDEV
10990 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10991 {
10992 }
10993 #endif
10994
10995 static const struct drm_mode_config_funcs intel_mode_funcs = {
10996         .fb_create = intel_user_framebuffer_create,
10997         .output_poll_changed = intel_fbdev_output_poll_changed,
10998 };
10999
11000 /* Set up chip specific display functions */
11001 static void intel_init_display(struct drm_device *dev)
11002 {
11003         struct drm_i915_private *dev_priv = dev->dev_private;
11004
11005         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11006                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11007         else if (IS_VALLEYVIEW(dev))
11008                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11009         else if (IS_PINEVIEW(dev))
11010                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11011         else
11012                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11013
11014         if (HAS_DDI(dev)) {
11015                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11016                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11017                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11018                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11019                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11020                 dev_priv->display.off = haswell_crtc_off;
11021                 dev_priv->display.update_primary_plane =
11022                         ironlake_update_primary_plane;
11023         } else if (HAS_PCH_SPLIT(dev)) {
11024                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11025                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11026                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11027                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11028                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11029                 dev_priv->display.off = ironlake_crtc_off;
11030                 dev_priv->display.update_primary_plane =
11031                         ironlake_update_primary_plane;
11032         } else if (IS_VALLEYVIEW(dev)) {
11033                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11034                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11035                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11036                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11037                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11038                 dev_priv->display.off = i9xx_crtc_off;
11039                 dev_priv->display.update_primary_plane =
11040                         i9xx_update_primary_plane;
11041         } else {
11042                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11043                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11044                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11045                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11046                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11047                 dev_priv->display.off = i9xx_crtc_off;
11048                 dev_priv->display.update_primary_plane =
11049                         i9xx_update_primary_plane;
11050         }
11051
11052         /* Returns the core display clock speed */
11053         if (IS_VALLEYVIEW(dev))
11054                 dev_priv->display.get_display_clock_speed =
11055                         valleyview_get_display_clock_speed;
11056         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11057                 dev_priv->display.get_display_clock_speed =
11058                         i945_get_display_clock_speed;
11059         else if (IS_I915G(dev))
11060                 dev_priv->display.get_display_clock_speed =
11061                         i915_get_display_clock_speed;
11062         else if (IS_I945GM(dev) || IS_845G(dev))
11063                 dev_priv->display.get_display_clock_speed =
11064                         i9xx_misc_get_display_clock_speed;
11065         else if (IS_PINEVIEW(dev))
11066                 dev_priv->display.get_display_clock_speed =
11067                         pnv_get_display_clock_speed;
11068         else if (IS_I915GM(dev))
11069                 dev_priv->display.get_display_clock_speed =
11070                         i915gm_get_display_clock_speed;
11071         else if (IS_I865G(dev))
11072                 dev_priv->display.get_display_clock_speed =
11073                         i865_get_display_clock_speed;
11074         else if (IS_I85X(dev))
11075                 dev_priv->display.get_display_clock_speed =
11076                         i855_get_display_clock_speed;
11077         else /* 852, 830 */
11078                 dev_priv->display.get_display_clock_speed =
11079                         i830_get_display_clock_speed;
11080
11081         if (HAS_PCH_SPLIT(dev)) {
11082                 if (IS_GEN5(dev)) {
11083                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11084                         dev_priv->display.write_eld = ironlake_write_eld;
11085                 } else if (IS_GEN6(dev)) {
11086                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11087                         dev_priv->display.write_eld = ironlake_write_eld;
11088                         dev_priv->display.modeset_global_resources =
11089                                 snb_modeset_global_resources;
11090                 } else if (IS_IVYBRIDGE(dev)) {
11091                         /* FIXME: detect B0+ stepping and use auto training */
11092                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11093                         dev_priv->display.write_eld = ironlake_write_eld;
11094                         dev_priv->display.modeset_global_resources =
11095                                 ivb_modeset_global_resources;
11096                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11097                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11098                         dev_priv->display.write_eld = haswell_write_eld;
11099                         dev_priv->display.modeset_global_resources =
11100                                 haswell_modeset_global_resources;
11101                 }
11102         } else if (IS_G4X(dev)) {
11103                 dev_priv->display.write_eld = g4x_write_eld;
11104         } else if (IS_VALLEYVIEW(dev)) {
11105                 dev_priv->display.modeset_global_resources =
11106                         valleyview_modeset_global_resources;
11107                 dev_priv->display.write_eld = ironlake_write_eld;
11108         }
11109
11110         /* Default just returns -ENODEV to indicate unsupported */
11111         dev_priv->display.queue_flip = intel_default_queue_flip;
11112
11113         switch (INTEL_INFO(dev)->gen) {
11114         case 2:
11115                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11116                 break;
11117
11118         case 3:
11119                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11120                 break;
11121
11122         case 4:
11123         case 5:
11124                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11125                 break;
11126
11127         case 6:
11128                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11129                 break;
11130         case 7:
11131         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11132                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11133                 break;
11134         }
11135
11136         intel_panel_init_backlight_funcs(dev);
11137 }
11138
11139 /*
11140  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11141  * resume, or other times.  This quirk makes sure that's the case for
11142  * affected systems.
11143  */
11144 static void quirk_pipea_force(struct drm_device *dev)
11145 {
11146         struct drm_i915_private *dev_priv = dev->dev_private;
11147
11148         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11149         DRM_INFO("applying pipe a force quirk\n");
11150 }
11151
11152 /*
11153  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11154  */
11155 static void quirk_ssc_force_disable(struct drm_device *dev)
11156 {
11157         struct drm_i915_private *dev_priv = dev->dev_private;
11158         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11159         DRM_INFO("applying lvds SSC disable quirk\n");
11160 }
11161
11162 /*
11163  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11164  * brightness value
11165  */
11166 static void quirk_invert_brightness(struct drm_device *dev)
11167 {
11168         struct drm_i915_private *dev_priv = dev->dev_private;
11169         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11170         DRM_INFO("applying inverted panel brightness quirk\n");
11171 }
11172
11173 struct intel_quirk {
11174         int device;
11175         int subsystem_vendor;
11176         int subsystem_device;
11177         void (*hook)(struct drm_device *dev);
11178 };
11179
11180 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11181 struct intel_dmi_quirk {
11182         void (*hook)(struct drm_device *dev);
11183         const struct dmi_system_id (*dmi_id_list)[];
11184 };
11185
11186 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11187 {
11188         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11189         return 1;
11190 }
11191
11192 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11193         {
11194                 .dmi_id_list = &(const struct dmi_system_id[]) {
11195                         {
11196                                 .callback = intel_dmi_reverse_brightness,
11197                                 .ident = "NCR Corporation",
11198                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11199                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11200                                 },
11201                         },
11202                         { }  /* terminating entry */
11203                 },
11204                 .hook = quirk_invert_brightness,
11205         },
11206 };
11207
11208 static struct intel_quirk intel_quirks[] = {
11209         /* HP Mini needs pipe A force quirk (LP: #322104) */
11210         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11211
11212         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11213         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11214
11215         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11216         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11217
11218         /* 830 needs to leave pipe A & dpll A up */
11219         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11220
11221         /* Lenovo U160 cannot use SSC on LVDS */
11222         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11223
11224         /* Sony Vaio Y cannot use SSC on LVDS */
11225         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11226
11227         /* Acer Aspire 5734Z must invert backlight brightness */
11228         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11229
11230         /* Acer/eMachines G725 */
11231         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11232
11233         /* Acer/eMachines e725 */
11234         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11235
11236         /* Acer/Packard Bell NCL20 */
11237         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11238
11239         /* Acer Aspire 4736Z */
11240         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11241
11242         /* Acer Aspire 5336 */
11243         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11244 };
11245
11246 static void intel_init_quirks(struct drm_device *dev)
11247 {
11248         struct pci_dev *d = dev->pdev;
11249         int i;
11250
11251         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11252                 struct intel_quirk *q = &intel_quirks[i];
11253
11254                 if (d->device == q->device &&
11255                     (d->subsystem_vendor == q->subsystem_vendor ||
11256                      q->subsystem_vendor == PCI_ANY_ID) &&
11257                     (d->subsystem_device == q->subsystem_device ||
11258                      q->subsystem_device == PCI_ANY_ID))
11259                         q->hook(dev);
11260         }
11261         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11262                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11263                         intel_dmi_quirks[i].hook(dev);
11264         }
11265 }
11266
11267 /* Disable the VGA plane that we never use */
11268 static void i915_disable_vga(struct drm_device *dev)
11269 {
11270         struct drm_i915_private *dev_priv = dev->dev_private;
11271         u8 sr1;
11272         u32 vga_reg = i915_vgacntrl_reg(dev);
11273
11274         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11275         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11276         outb(SR01, VGA_SR_INDEX);
11277         sr1 = inb(VGA_SR_DATA);
11278         outb(sr1 | 1<<5, VGA_SR_DATA);
11279         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11280         udelay(300);
11281
11282         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11283         POSTING_READ(vga_reg);
11284 }
11285
11286 void intel_modeset_init_hw(struct drm_device *dev)
11287 {
11288         intel_prepare_ddi(dev);
11289
11290         intel_init_clock_gating(dev);
11291
11292         intel_reset_dpio(dev);
11293
11294         intel_enable_gt_powersave(dev);
11295 }
11296
11297 void intel_modeset_suspend_hw(struct drm_device *dev)
11298 {
11299         intel_suspend_hw(dev);
11300 }
11301
11302 void intel_modeset_init(struct drm_device *dev)
11303 {
11304         struct drm_i915_private *dev_priv = dev->dev_private;
11305         int sprite, ret;
11306         enum pipe pipe;
11307         struct intel_crtc *crtc;
11308
11309         drm_mode_config_init(dev);
11310
11311         dev->mode_config.min_width = 0;
11312         dev->mode_config.min_height = 0;
11313
11314         dev->mode_config.preferred_depth = 24;
11315         dev->mode_config.prefer_shadow = 1;
11316
11317         dev->mode_config.funcs = &intel_mode_funcs;
11318
11319         intel_init_quirks(dev);
11320
11321         intel_init_pm(dev);
11322
11323         if (INTEL_INFO(dev)->num_pipes == 0)
11324                 return;
11325
11326         intel_init_display(dev);
11327
11328         if (IS_GEN2(dev)) {
11329                 dev->mode_config.max_width = 2048;
11330                 dev->mode_config.max_height = 2048;
11331         } else if (IS_GEN3(dev)) {
11332                 dev->mode_config.max_width = 4096;
11333                 dev->mode_config.max_height = 4096;
11334         } else {
11335                 dev->mode_config.max_width = 8192;
11336                 dev->mode_config.max_height = 8192;
11337         }
11338
11339         if (IS_GEN2(dev)) {
11340                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11341                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11342         } else {
11343                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11344                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11345         }
11346
11347         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11348
11349         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11350                       INTEL_INFO(dev)->num_pipes,
11351                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11352
11353         for_each_pipe(pipe) {
11354                 intel_crtc_init(dev, pipe);
11355                 for_each_sprite(pipe, sprite) {
11356                         ret = intel_plane_init(dev, pipe, sprite);
11357                         if (ret)
11358                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11359                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11360                 }
11361         }
11362
11363         intel_init_dpio(dev);
11364         intel_reset_dpio(dev);
11365
11366         intel_cpu_pll_init(dev);
11367         intel_shared_dpll_init(dev);
11368
11369         /* Just disable it once at startup */
11370         i915_disable_vga(dev);
11371         intel_setup_outputs(dev);
11372
11373         /* Just in case the BIOS is doing something questionable. */
11374         intel_disable_fbc(dev);
11375
11376         mutex_lock(&dev->mode_config.mutex);
11377         intel_modeset_setup_hw_state(dev, false);
11378         mutex_unlock(&dev->mode_config.mutex);
11379
11380         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11381                             base.head) {
11382                 if (!crtc->active)
11383                         continue;
11384
11385                 /*
11386                  * Note that reserving the BIOS fb up front prevents us
11387                  * from stuffing other stolen allocations like the ring
11388                  * on top.  This prevents some ugliness at boot time, and
11389                  * can even allow for smooth boot transitions if the BIOS
11390                  * fb is large enough for the active pipe configuration.
11391                  */
11392                 if (dev_priv->display.get_plane_config) {
11393                         dev_priv->display.get_plane_config(crtc,
11394                                                            &crtc->plane_config);
11395                         /*
11396                          * If the fb is shared between multiple heads, we'll
11397                          * just get the first one.
11398                          */
11399                         intel_find_plane_obj(crtc, &crtc->plane_config);
11400                 }
11401         }
11402 }
11403
11404 static void
11405 intel_connector_break_all_links(struct intel_connector *connector)
11406 {
11407         connector->base.dpms = DRM_MODE_DPMS_OFF;
11408         connector->base.encoder = NULL;
11409         connector->encoder->connectors_active = false;
11410         connector->encoder->base.crtc = NULL;
11411 }
11412
11413 static void intel_enable_pipe_a(struct drm_device *dev)
11414 {
11415         struct intel_connector *connector;
11416         struct drm_connector *crt = NULL;
11417         struct intel_load_detect_pipe load_detect_temp;
11418
11419         /* We can't just switch on the pipe A, we need to set things up with a
11420          * proper mode and output configuration. As a gross hack, enable pipe A
11421          * by enabling the load detect pipe once. */
11422         list_for_each_entry(connector,
11423                             &dev->mode_config.connector_list,
11424                             base.head) {
11425                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11426                         crt = &connector->base;
11427                         break;
11428                 }
11429         }
11430
11431         if (!crt)
11432                 return;
11433
11434         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11435                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11436
11437
11438 }
11439
11440 static bool
11441 intel_check_plane_mapping(struct intel_crtc *crtc)
11442 {
11443         struct drm_device *dev = crtc->base.dev;
11444         struct drm_i915_private *dev_priv = dev->dev_private;
11445         u32 reg, val;
11446
11447         if (INTEL_INFO(dev)->num_pipes == 1)
11448                 return true;
11449
11450         reg = DSPCNTR(!crtc->plane);
11451         val = I915_READ(reg);
11452
11453         if ((val & DISPLAY_PLANE_ENABLE) &&
11454             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11455                 return false;
11456
11457         return true;
11458 }
11459
11460 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11461 {
11462         struct drm_device *dev = crtc->base.dev;
11463         struct drm_i915_private *dev_priv = dev->dev_private;
11464         u32 reg;
11465
11466         /* Clear any frame start delays used for debugging left by the BIOS */
11467         reg = PIPECONF(crtc->config.cpu_transcoder);
11468         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11469
11470         /* We need to sanitize the plane -> pipe mapping first because this will
11471          * disable the crtc (and hence change the state) if it is wrong. Note
11472          * that gen4+ has a fixed plane -> pipe mapping.  */
11473         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11474                 struct intel_connector *connector;
11475                 bool plane;
11476
11477                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11478                               crtc->base.base.id);
11479
11480                 /* Pipe has the wrong plane attached and the plane is active.
11481                  * Temporarily change the plane mapping and disable everything
11482                  * ...  */
11483                 plane = crtc->plane;
11484                 crtc->plane = !plane;
11485                 dev_priv->display.crtc_disable(&crtc->base);
11486                 crtc->plane = plane;
11487
11488                 /* ... and break all links. */
11489                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11490                                     base.head) {
11491                         if (connector->encoder->base.crtc != &crtc->base)
11492                                 continue;
11493
11494                         intel_connector_break_all_links(connector);
11495                 }
11496
11497                 WARN_ON(crtc->active);
11498                 crtc->base.enabled = false;
11499         }
11500
11501         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11502             crtc->pipe == PIPE_A && !crtc->active) {
11503                 /* BIOS forgot to enable pipe A, this mostly happens after
11504                  * resume. Force-enable the pipe to fix this, the update_dpms
11505                  * call below we restore the pipe to the right state, but leave
11506                  * the required bits on. */
11507                 intel_enable_pipe_a(dev);
11508         }
11509
11510         /* Adjust the state of the output pipe according to whether we
11511          * have active connectors/encoders. */
11512         intel_crtc_update_dpms(&crtc->base);
11513
11514         if (crtc->active != crtc->base.enabled) {
11515                 struct intel_encoder *encoder;
11516
11517                 /* This can happen either due to bugs in the get_hw_state
11518                  * functions or because the pipe is force-enabled due to the
11519                  * pipe A quirk. */
11520                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11521                               crtc->base.base.id,
11522                               crtc->base.enabled ? "enabled" : "disabled",
11523                               crtc->active ? "enabled" : "disabled");
11524
11525                 crtc->base.enabled = crtc->active;
11526
11527                 /* Because we only establish the connector -> encoder ->
11528                  * crtc links if something is active, this means the
11529                  * crtc is now deactivated. Break the links. connector
11530                  * -> encoder links are only establish when things are
11531                  *  actually up, hence no need to break them. */
11532                 WARN_ON(crtc->active);
11533
11534                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11535                         WARN_ON(encoder->connectors_active);
11536                         encoder->base.crtc = NULL;
11537                 }
11538         }
11539         if (crtc->active) {
11540                 /*
11541                  * We start out with underrun reporting disabled to avoid races.
11542                  * For correct bookkeeping mark this on active crtcs.
11543                  *
11544                  * No protection against concurrent access is required - at
11545                  * worst a fifo underrun happens which also sets this to false.
11546                  */
11547                 crtc->cpu_fifo_underrun_disabled = true;
11548                 crtc->pch_fifo_underrun_disabled = true;
11549         }
11550 }
11551
11552 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11553 {
11554         struct intel_connector *connector;
11555         struct drm_device *dev = encoder->base.dev;
11556
11557         /* We need to check both for a crtc link (meaning that the
11558          * encoder is active and trying to read from a pipe) and the
11559          * pipe itself being active. */
11560         bool has_active_crtc = encoder->base.crtc &&
11561                 to_intel_crtc(encoder->base.crtc)->active;
11562
11563         if (encoder->connectors_active && !has_active_crtc) {
11564                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11565                               encoder->base.base.id,
11566                               drm_get_encoder_name(&encoder->base));
11567
11568                 /* Connector is active, but has no active pipe. This is
11569                  * fallout from our resume register restoring. Disable
11570                  * the encoder manually again. */
11571                 if (encoder->base.crtc) {
11572                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11573                                       encoder->base.base.id,
11574                                       drm_get_encoder_name(&encoder->base));
11575                         encoder->disable(encoder);
11576                 }
11577
11578                 /* Inconsistent output/port/pipe state happens presumably due to
11579                  * a bug in one of the get_hw_state functions. Or someplace else
11580                  * in our code, like the register restore mess on resume. Clamp
11581                  * things to off as a safer default. */
11582                 list_for_each_entry(connector,
11583                                     &dev->mode_config.connector_list,
11584                                     base.head) {
11585                         if (connector->encoder != encoder)
11586                                 continue;
11587
11588                         intel_connector_break_all_links(connector);
11589                 }
11590         }
11591         /* Enabled encoders without active connectors will be fixed in
11592          * the crtc fixup. */
11593 }
11594
11595 void i915_redisable_vga_power_on(struct drm_device *dev)
11596 {
11597         struct drm_i915_private *dev_priv = dev->dev_private;
11598         u32 vga_reg = i915_vgacntrl_reg(dev);
11599
11600         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11601                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11602                 i915_disable_vga(dev);
11603         }
11604 }
11605
11606 void i915_redisable_vga(struct drm_device *dev)
11607 {
11608         struct drm_i915_private *dev_priv = dev->dev_private;
11609
11610         /* This function can be called both from intel_modeset_setup_hw_state or
11611          * at a very early point in our resume sequence, where the power well
11612          * structures are not yet restored. Since this function is at a very
11613          * paranoid "someone might have enabled VGA while we were not looking"
11614          * level, just check if the power well is enabled instead of trying to
11615          * follow the "don't touch the power well if we don't need it" policy
11616          * the rest of the driver uses. */
11617         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11618                 return;
11619
11620         i915_redisable_vga_power_on(dev);
11621 }
11622
11623 static bool primary_get_hw_state(struct intel_crtc *crtc)
11624 {
11625         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11626
11627         if (!crtc->active)
11628                 return false;
11629
11630         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11631 }
11632
11633 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11634 {
11635         struct drm_i915_private *dev_priv = dev->dev_private;
11636         enum pipe pipe;
11637         struct intel_crtc *crtc;
11638         struct intel_encoder *encoder;
11639         struct intel_connector *connector;
11640         int i;
11641
11642         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11643                             base.head) {
11644                 memset(&crtc->config, 0, sizeof(crtc->config));
11645
11646                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11647
11648                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11649                                                                  &crtc->config);
11650
11651                 crtc->base.enabled = crtc->active;
11652                 crtc->primary_enabled = primary_get_hw_state(crtc);
11653
11654                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11655                               crtc->base.base.id,
11656                               crtc->active ? "enabled" : "disabled");
11657         }
11658
11659         /* FIXME: Smash this into the new shared dpll infrastructure. */
11660         if (HAS_DDI(dev))
11661                 intel_ddi_setup_hw_pll_state(dev);
11662
11663         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11664                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11665
11666                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11667                 pll->active = 0;
11668                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11669                                     base.head) {
11670                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11671                                 pll->active++;
11672                 }
11673                 pll->refcount = pll->active;
11674
11675                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11676                               pll->name, pll->refcount, pll->on);
11677         }
11678
11679         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11680                             base.head) {
11681                 pipe = 0;
11682
11683                 if (encoder->get_hw_state(encoder, &pipe)) {
11684                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11685                         encoder->base.crtc = &crtc->base;
11686                         encoder->get_config(encoder, &crtc->config);
11687                 } else {
11688                         encoder->base.crtc = NULL;
11689                 }
11690
11691                 encoder->connectors_active = false;
11692                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11693                               encoder->base.base.id,
11694                               drm_get_encoder_name(&encoder->base),
11695                               encoder->base.crtc ? "enabled" : "disabled",
11696                               pipe_name(pipe));
11697         }
11698
11699         list_for_each_entry(connector, &dev->mode_config.connector_list,
11700                             base.head) {
11701                 if (connector->get_hw_state(connector)) {
11702                         connector->base.dpms = DRM_MODE_DPMS_ON;
11703                         connector->encoder->connectors_active = true;
11704                         connector->base.encoder = &connector->encoder->base;
11705                 } else {
11706                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11707                         connector->base.encoder = NULL;
11708                 }
11709                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11710                               connector->base.base.id,
11711                               drm_get_connector_name(&connector->base),
11712                               connector->base.encoder ? "enabled" : "disabled");
11713         }
11714 }
11715
11716 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11717  * and i915 state tracking structures. */
11718 void intel_modeset_setup_hw_state(struct drm_device *dev,
11719                                   bool force_restore)
11720 {
11721         struct drm_i915_private *dev_priv = dev->dev_private;
11722         enum pipe pipe;
11723         struct intel_crtc *crtc;
11724         struct intel_encoder *encoder;
11725         int i;
11726
11727         intel_modeset_readout_hw_state(dev);
11728
11729         /*
11730          * Now that we have the config, copy it to each CRTC struct
11731          * Note that this could go away if we move to using crtc_config
11732          * checking everywhere.
11733          */
11734         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11735                             base.head) {
11736                 if (crtc->active && i915.fastboot) {
11737                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11738                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11739                                       crtc->base.base.id);
11740                         drm_mode_debug_printmodeline(&crtc->base.mode);
11741                 }
11742         }
11743
11744         /* HW state is read out, now we need to sanitize this mess. */
11745         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11746                             base.head) {
11747                 intel_sanitize_encoder(encoder);
11748         }
11749
11750         for_each_pipe(pipe) {
11751                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11752                 intel_sanitize_crtc(crtc);
11753                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11754         }
11755
11756         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11757                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11758
11759                 if (!pll->on || pll->active)
11760                         continue;
11761
11762                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11763
11764                 pll->disable(dev_priv, pll);
11765                 pll->on = false;
11766         }
11767
11768         if (HAS_PCH_SPLIT(dev))
11769                 ilk_wm_get_hw_state(dev);
11770
11771         if (force_restore) {
11772                 i915_redisable_vga(dev);
11773
11774                 /*
11775                  * We need to use raw interfaces for restoring state to avoid
11776                  * checking (bogus) intermediate states.
11777                  */
11778                 for_each_pipe(pipe) {
11779                         struct drm_crtc *crtc =
11780                                 dev_priv->pipe_to_crtc_mapping[pipe];
11781
11782                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11783                                          crtc->primary->fb);
11784                 }
11785         } else {
11786                 intel_modeset_update_staged_output_state(dev);
11787         }
11788
11789         intel_modeset_check_state(dev);
11790 }
11791
11792 void intel_modeset_gem_init(struct drm_device *dev)
11793 {
11794         struct drm_crtc *c;
11795         struct intel_framebuffer *fb;
11796
11797         mutex_lock(&dev->struct_mutex);
11798         intel_init_gt_powersave(dev);
11799         mutex_unlock(&dev->struct_mutex);
11800
11801         intel_modeset_init_hw(dev);
11802
11803         intel_setup_overlay(dev);
11804
11805         /*
11806          * Make sure any fbs we allocated at startup are properly
11807          * pinned & fenced.  When we do the allocation it's too early
11808          * for this.
11809          */
11810         mutex_lock(&dev->struct_mutex);
11811         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11812                 if (!c->primary->fb)
11813                         continue;
11814
11815                 fb = to_intel_framebuffer(c->primary->fb);
11816                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11817                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11818                                   to_intel_crtc(c)->pipe);
11819                         drm_framebuffer_unreference(c->primary->fb);
11820                         c->primary->fb = NULL;
11821                 }
11822         }
11823         mutex_unlock(&dev->struct_mutex);
11824 }
11825
11826 void intel_connector_unregister(struct intel_connector *intel_connector)
11827 {
11828         struct drm_connector *connector = &intel_connector->base;
11829
11830         intel_panel_destroy_backlight(connector);
11831         drm_sysfs_connector_remove(connector);
11832 }
11833
11834 void intel_modeset_cleanup(struct drm_device *dev)
11835 {
11836         struct drm_i915_private *dev_priv = dev->dev_private;
11837         struct drm_crtc *crtc;
11838         struct drm_connector *connector;
11839
11840         /*
11841          * Interrupts and polling as the first thing to avoid creating havoc.
11842          * Too much stuff here (turning of rps, connectors, ...) would
11843          * experience fancy races otherwise.
11844          */
11845         drm_irq_uninstall(dev);
11846         cancel_work_sync(&dev_priv->hotplug_work);
11847         /*
11848          * Due to the hpd irq storm handling the hotplug work can re-arm the
11849          * poll handlers. Hence disable polling after hpd handling is shut down.
11850          */
11851         drm_kms_helper_poll_fini(dev);
11852
11853         mutex_lock(&dev->struct_mutex);
11854
11855         intel_unregister_dsm_handler();
11856
11857         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11858                 /* Skip inactive CRTCs */
11859                 if (!crtc->primary->fb)
11860                         continue;
11861
11862                 intel_increase_pllclock(crtc);
11863         }
11864
11865         intel_disable_fbc(dev);
11866
11867         intel_disable_gt_powersave(dev);
11868
11869         ironlake_teardown_rc6(dev);
11870
11871         mutex_unlock(&dev->struct_mutex);
11872
11873         /* flush any delayed tasks or pending work */
11874         flush_scheduled_work();
11875
11876         /* destroy the backlight and sysfs files before encoders/connectors */
11877         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11878                 struct intel_connector *intel_connector;
11879
11880                 intel_connector = to_intel_connector(connector);
11881                 intel_connector->unregister(intel_connector);
11882         }
11883
11884         drm_mode_config_cleanup(dev);
11885
11886         intel_cleanup_overlay(dev);
11887
11888         mutex_lock(&dev->struct_mutex);
11889         intel_cleanup_gt_powersave(dev);
11890         mutex_unlock(&dev->struct_mutex);
11891 }
11892
11893 /*
11894  * Return which encoder is currently attached for connector.
11895  */
11896 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11897 {
11898         return &intel_attached_encoder(connector)->base;
11899 }
11900
11901 void intel_connector_attach_encoder(struct intel_connector *connector,
11902                                     struct intel_encoder *encoder)
11903 {
11904         connector->encoder = encoder;
11905         drm_mode_connector_attach_encoder(&connector->base,
11906                                           &encoder->base);
11907 }
11908
11909 /*
11910  * set vga decode state - true == enable VGA decode
11911  */
11912 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11913 {
11914         struct drm_i915_private *dev_priv = dev->dev_private;
11915         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11916         u16 gmch_ctrl;
11917
11918         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11919                 DRM_ERROR("failed to read control word\n");
11920                 return -EIO;
11921         }
11922
11923         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11924                 return 0;
11925
11926         if (state)
11927                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11928         else
11929                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11930
11931         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11932                 DRM_ERROR("failed to write control word\n");
11933                 return -EIO;
11934         }
11935
11936         return 0;
11937 }
11938
11939 struct intel_display_error_state {
11940
11941         u32 power_well_driver;
11942
11943         int num_transcoders;
11944
11945         struct intel_cursor_error_state {
11946                 u32 control;
11947                 u32 position;
11948                 u32 base;
11949                 u32 size;
11950         } cursor[I915_MAX_PIPES];
11951
11952         struct intel_pipe_error_state {
11953                 bool power_domain_on;
11954                 u32 source;
11955                 u32 stat;
11956         } pipe[I915_MAX_PIPES];
11957
11958         struct intel_plane_error_state {
11959                 u32 control;
11960                 u32 stride;
11961                 u32 size;
11962                 u32 pos;
11963                 u32 addr;
11964                 u32 surface;
11965                 u32 tile_offset;
11966         } plane[I915_MAX_PIPES];
11967
11968         struct intel_transcoder_error_state {
11969                 bool power_domain_on;
11970                 enum transcoder cpu_transcoder;
11971
11972                 u32 conf;
11973
11974                 u32 htotal;
11975                 u32 hblank;
11976                 u32 hsync;
11977                 u32 vtotal;
11978                 u32 vblank;
11979                 u32 vsync;
11980         } transcoder[4];
11981 };
11982
11983 struct intel_display_error_state *
11984 intel_display_capture_error_state(struct drm_device *dev)
11985 {
11986         struct drm_i915_private *dev_priv = dev->dev_private;
11987         struct intel_display_error_state *error;
11988         int transcoders[] = {
11989                 TRANSCODER_A,
11990                 TRANSCODER_B,
11991                 TRANSCODER_C,
11992                 TRANSCODER_EDP,
11993         };
11994         int i;
11995
11996         if (INTEL_INFO(dev)->num_pipes == 0)
11997                 return NULL;
11998
11999         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12000         if (error == NULL)
12001                 return NULL;
12002
12003         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12004                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12005
12006         for_each_pipe(i) {
12007                 error->pipe[i].power_domain_on =
12008                         intel_display_power_enabled_sw(dev_priv,
12009                                                        POWER_DOMAIN_PIPE(i));
12010                 if (!error->pipe[i].power_domain_on)
12011                         continue;
12012
12013                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12014                         error->cursor[i].control = I915_READ(CURCNTR(i));
12015                         error->cursor[i].position = I915_READ(CURPOS(i));
12016                         error->cursor[i].base = I915_READ(CURBASE(i));
12017                 } else {
12018                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12019                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12020                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12021                 }
12022
12023                 error->plane[i].control = I915_READ(DSPCNTR(i));
12024                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12025                 if (INTEL_INFO(dev)->gen <= 3) {
12026                         error->plane[i].size = I915_READ(DSPSIZE(i));
12027                         error->plane[i].pos = I915_READ(DSPPOS(i));
12028                 }
12029                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12030                         error->plane[i].addr = I915_READ(DSPADDR(i));
12031                 if (INTEL_INFO(dev)->gen >= 4) {
12032                         error->plane[i].surface = I915_READ(DSPSURF(i));
12033                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12034                 }
12035
12036                 error->pipe[i].source = I915_READ(PIPESRC(i));
12037
12038                 if (!HAS_PCH_SPLIT(dev))
12039                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12040         }
12041
12042         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12043         if (HAS_DDI(dev_priv->dev))
12044                 error->num_transcoders++; /* Account for eDP. */
12045
12046         for (i = 0; i < error->num_transcoders; i++) {
12047                 enum transcoder cpu_transcoder = transcoders[i];
12048
12049                 error->transcoder[i].power_domain_on =
12050                         intel_display_power_enabled_sw(dev_priv,
12051                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12052                 if (!error->transcoder[i].power_domain_on)
12053                         continue;
12054
12055                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12056
12057                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12058                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12059                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12060                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12061                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12062                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12063                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12064         }
12065
12066         return error;
12067 }
12068
12069 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12070
12071 void
12072 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12073                                 struct drm_device *dev,
12074                                 struct intel_display_error_state *error)
12075 {
12076         int i;
12077
12078         if (!error)
12079                 return;
12080
12081         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12082         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12083                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12084                            error->power_well_driver);
12085         for_each_pipe(i) {
12086                 err_printf(m, "Pipe [%d]:\n", i);
12087                 err_printf(m, "  Power: %s\n",
12088                            error->pipe[i].power_domain_on ? "on" : "off");
12089                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12090                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12091
12092                 err_printf(m, "Plane [%d]:\n", i);
12093                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12094                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12095                 if (INTEL_INFO(dev)->gen <= 3) {
12096                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12097                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12098                 }
12099                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12100                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12101                 if (INTEL_INFO(dev)->gen >= 4) {
12102                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12103                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12104                 }
12105
12106                 err_printf(m, "Cursor [%d]:\n", i);
12107                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12108                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12109                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12110         }
12111
12112         for (i = 0; i < error->num_transcoders; i++) {
12113                 err_printf(m, "CPU transcoder: %c\n",
12114                            transcoder_name(error->transcoder[i].cpu_transcoder));
12115                 err_printf(m, "  Power: %s\n",
12116                            error->transcoder[i].power_domain_on ? "on" : "off");
12117                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12118                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12119                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12120                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12121                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12122                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12123                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12124         }
12125 }