drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->refcount);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->refcount == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->refcount == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198                            struct drm_i915_gem_object *obj,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         u32 alignment;
2203         int ret;
2204
2205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207         switch (obj->tiling_mode) {
2208         case I915_TILING_NONE:
2209                 if (INTEL_INFO(dev)->gen >= 9)
2210                         alignment = 256 * 1024;
2211                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212                         alignment = 128 * 1024;
2213                 else if (INTEL_INFO(dev)->gen >= 4)
2214                         alignment = 4 * 1024;
2215                 else
2216                         alignment = 64 * 1024;
2217                 break;
2218         case I915_TILING_X:
2219                 if (INTEL_INFO(dev)->gen >= 9)
2220                         alignment = 256 * 1024;
2221                 else {
2222                         /* pin() will align the object as required by fence */
2223                         alignment = 0;
2224                 }
2225                 break;
2226         case I915_TILING_Y:
2227                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228                 return -EINVAL;
2229         default:
2230                 BUG();
2231         }
2232
2233         /* Note that the w/a also requires 64 PTE of padding following the
2234          * bo. We currently fill all unused PTE with the shadow page and so
2235          * we should always have valid PTE following the scanout preventing
2236          * the VT-d warning.
2237          */
2238         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239                 alignment = 256 * 1024;
2240
2241         /*
2242          * Global gtt pte registers are special registers which actually forward
2243          * writes to a chunk of system memory. Which means that there is no risk
2244          * that the register values disappear as soon as we call
2245          * intel_runtime_pm_put(), so it is correct to wrap only the
2246          * pin/unpin/fence and not more.
2247          */
2248         intel_runtime_pm_get(dev_priv);
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         intel_runtime_pm_put(dev_priv);
2268         return 0;
2269
2270 err_unpin:
2271         i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282         i915_gem_object_unpin_fence(obj);
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287  * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289                                              unsigned int tiling_mode,
2290                                              unsigned int cpp,
2291                                              unsigned int pitch)
2292 {
2293         if (tiling_mode != I915_TILING_NONE) {
2294                 unsigned int tile_rows, tiles;
2295
2296                 tile_rows = *y / 8;
2297                 *y %= 8;
2298
2299                 tiles = *x / (512/cpp);
2300                 *x %= 512/cpp;
2301
2302                 return tile_rows * pitch * 8 + tiles * 4096;
2303         } else {
2304                 unsigned int offset;
2305
2306                 offset = *y * pitch + *x * cpp;
2307                 *y = 0;
2308                 *x = (offset & 4095) / cpp;
2309                 return offset & -4096;
2310         }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315         switch (format) {
2316         case DISPPLANE_8BPP:
2317                 return DRM_FORMAT_C8;
2318         case DISPPLANE_BGRX555:
2319                 return DRM_FORMAT_XRGB1555;
2320         case DISPPLANE_BGRX565:
2321                 return DRM_FORMAT_RGB565;
2322         default:
2323         case DISPPLANE_BGRX888:
2324                 return DRM_FORMAT_XRGB8888;
2325         case DISPPLANE_RGBX888:
2326                 return DRM_FORMAT_XBGR8888;
2327         case DISPPLANE_BGRX101010:
2328                 return DRM_FORMAT_XRGB2101010;
2329         case DISPPLANE_RGBX101010:
2330                 return DRM_FORMAT_XBGR2101010;
2331         }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335                                   struct intel_plane_config *plane_config)
2336 {
2337         struct drm_device *dev = crtc->base.dev;
2338         struct drm_i915_gem_object *obj = NULL;
2339         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340         u32 base = plane_config->base;
2341
2342         if (plane_config->size == 0)
2343                 return false;
2344
2345         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346                                                              plane_config->size);
2347         if (!obj)
2348                 return false;
2349
2350         if (plane_config->tiled) {
2351                 obj->tiling_mode = I915_TILING_X;
2352                 obj->stride = crtc->base.primary->fb->pitches[0];
2353         }
2354
2355         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356         mode_cmd.width = crtc->base.primary->fb->width;
2357         mode_cmd.height = crtc->base.primary->fb->height;
2358         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360         mutex_lock(&dev->struct_mutex);
2361
2362         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363                                    &mode_cmd, obj)) {
2364                 DRM_DEBUG_KMS("intel fb init failed\n");
2365                 goto out_unref_obj;
2366         }
2367
2368         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369         mutex_unlock(&dev->struct_mutex);
2370
2371         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372         return true;
2373
2374 out_unref_obj:
2375         drm_gem_object_unreference(&obj->base);
2376         mutex_unlock(&dev->struct_mutex);
2377         return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381                                  struct intel_plane_config *plane_config)
2382 {
2383         struct drm_device *dev = intel_crtc->base.dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_crtc *c;
2386         struct intel_crtc *i;
2387         struct drm_i915_gem_object *obj;
2388
2389         if (!intel_crtc->base.primary->fb)
2390                 return;
2391
2392         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393                 return;
2394
2395         kfree(intel_crtc->base.primary->fb);
2396         intel_crtc->base.primary->fb = NULL;
2397
2398         /*
2399          * Failed to alloc the obj, check to see if we should share
2400          * an fb with another CRTC instead
2401          */
2402         for_each_crtc(dev, c) {
2403                 i = to_intel_crtc(c);
2404
2405                 if (c == &intel_crtc->base)
2406                         continue;
2407
2408                 if (!i->active)
2409                         continue;
2410
2411                 obj = intel_fb_obj(c->primary->fb);
2412                 if (obj == NULL)
2413                         continue;
2414
2415                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416                         if (obj->tiling_mode != I915_TILING_NONE)
2417                                 dev_priv->preserve_bios_swizzle = true;
2418
2419                         drm_framebuffer_reference(c->primary->fb);
2420                         intel_crtc->base.primary->fb = c->primary->fb;
2421                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2422                         break;
2423                 }
2424         }
2425 }
2426
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428                                       struct drm_framebuffer *fb,
2429                                       int x, int y)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg = DSPCNTR(plane);
2439         int pixel_size;
2440
2441         if (!intel_crtc->primary_enabled) {
2442                 I915_WRITE(reg, 0);
2443                 if (INTEL_INFO(dev)->gen >= 4)
2444                         I915_WRITE(DSPSURF(plane), 0);
2445                 else
2446                         I915_WRITE(DSPADDR(plane), 0);
2447                 POSTING_READ(reg);
2448                 return;
2449         }
2450
2451         obj = intel_fb_obj(fb);
2452         if (WARN_ON(obj == NULL))
2453                 return;
2454
2455         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
2457         dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
2459         dspcntr |= DISPLAY_PLANE_ENABLE;
2460
2461         if (INTEL_INFO(dev)->gen < 4) {
2462                 if (intel_crtc->pipe == PIPE_B)
2463                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465                 /* pipesrc and dspsize control the size that is scaled from,
2466                  * which should always be the user's requested size.
2467                  */
2468                 I915_WRITE(DSPSIZE(plane),
2469                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470                            (intel_crtc->config.pipe_src_w - 1));
2471                 I915_WRITE(DSPPOS(plane), 0);
2472         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473                 I915_WRITE(PRIMSIZE(plane),
2474                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475                            (intel_crtc->config.pipe_src_w - 1));
2476                 I915_WRITE(PRIMPOS(plane), 0);
2477                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2478         }
2479
2480         switch (fb->pixel_format) {
2481         case DRM_FORMAT_C8:
2482                 dspcntr |= DISPPLANE_8BPP;
2483                 break;
2484         case DRM_FORMAT_XRGB1555:
2485         case DRM_FORMAT_ARGB1555:
2486                 dspcntr |= DISPPLANE_BGRX555;
2487                 break;
2488         case DRM_FORMAT_RGB565:
2489                 dspcntr |= DISPPLANE_BGRX565;
2490                 break;
2491         case DRM_FORMAT_XRGB8888:
2492         case DRM_FORMAT_ARGB8888:
2493                 dspcntr |= DISPPLANE_BGRX888;
2494                 break;
2495         case DRM_FORMAT_XBGR8888:
2496         case DRM_FORMAT_ABGR8888:
2497                 dspcntr |= DISPPLANE_RGBX888;
2498                 break;
2499         case DRM_FORMAT_XRGB2101010:
2500         case DRM_FORMAT_ARGB2101010:
2501                 dspcntr |= DISPPLANE_BGRX101010;
2502                 break;
2503         case DRM_FORMAT_XBGR2101010:
2504         case DRM_FORMAT_ABGR2101010:
2505                 dspcntr |= DISPPLANE_RGBX101010;
2506                 break;
2507         default:
2508                 BUG();
2509         }
2510
2511         if (INTEL_INFO(dev)->gen >= 4 &&
2512             obj->tiling_mode != I915_TILING_NONE)
2513                 dspcntr |= DISPPLANE_TILED;
2514
2515         if (IS_G4X(dev))
2516                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
2518         linear_offset = y * fb->pitches[0] + x * pixel_size;
2519
2520         if (INTEL_INFO(dev)->gen >= 4) {
2521                 intel_crtc->dspaddr_offset =
2522                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2523                                                        pixel_size,
2524                                                        fb->pitches[0]);
2525                 linear_offset -= intel_crtc->dspaddr_offset;
2526         } else {
2527                 intel_crtc->dspaddr_offset = linear_offset;
2528         }
2529
2530         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531                 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533                 x += (intel_crtc->config.pipe_src_w - 1);
2534                 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536                 /* Finding the last pixel of the last line of the display
2537                 data and adding to linear_offset*/
2538                 linear_offset +=
2539                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541         }
2542
2543         I915_WRITE(reg, dspcntr);
2544
2545         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547                       fb->pitches[0]);
2548         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549         if (INTEL_INFO(dev)->gen >= 4) {
2550                 I915_WRITE(DSPSURF(plane),
2551                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2554         } else
2555                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2556         POSTING_READ(reg);
2557 }
2558
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560                                           struct drm_framebuffer *fb,
2561                                           int x, int y)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         struct drm_i915_gem_object *obj;
2567         int plane = intel_crtc->plane;
2568         unsigned long linear_offset;
2569         u32 dspcntr;
2570         u32 reg = DSPCNTR(plane);
2571         int pixel_size;
2572
2573         if (!intel_crtc->primary_enabled) {
2574                 I915_WRITE(reg, 0);
2575                 I915_WRITE(DSPSURF(plane), 0);
2576                 POSTING_READ(reg);
2577                 return;
2578         }
2579
2580         obj = intel_fb_obj(fb);
2581         if (WARN_ON(obj == NULL))
2582                 return;
2583
2584         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
2586         dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
2588         dspcntr |= DISPLAY_PLANE_ENABLE;
2589
2590         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
2593         switch (fb->pixel_format) {
2594         case DRM_FORMAT_C8:
2595                 dspcntr |= DISPPLANE_8BPP;
2596                 break;
2597         case DRM_FORMAT_RGB565:
2598                 dspcntr |= DISPPLANE_BGRX565;
2599                 break;
2600         case DRM_FORMAT_XRGB8888:
2601         case DRM_FORMAT_ARGB8888:
2602                 dspcntr |= DISPPLANE_BGRX888;
2603                 break;
2604         case DRM_FORMAT_XBGR8888:
2605         case DRM_FORMAT_ABGR8888:
2606                 dspcntr |= DISPPLANE_RGBX888;
2607                 break;
2608         case DRM_FORMAT_XRGB2101010:
2609         case DRM_FORMAT_ARGB2101010:
2610                 dspcntr |= DISPPLANE_BGRX101010;
2611                 break;
2612         case DRM_FORMAT_XBGR2101010:
2613         case DRM_FORMAT_ABGR2101010:
2614                 dspcntr |= DISPPLANE_RGBX101010;
2615                 break;
2616         default:
2617                 BUG();
2618         }
2619
2620         if (obj->tiling_mode != I915_TILING_NONE)
2621                 dspcntr |= DISPPLANE_TILED;
2622
2623         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2625
2626         linear_offset = y * fb->pitches[0] + x * pixel_size;
2627         intel_crtc->dspaddr_offset =
2628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629                                                pixel_size,
2630                                                fb->pitches[0]);
2631         linear_offset -= intel_crtc->dspaddr_offset;
2632         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633                 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636                         x += (intel_crtc->config.pipe_src_w - 1);
2637                         y += (intel_crtc->config.pipe_src_h - 1);
2638
2639                         /* Finding the last pixel of the last line of the display
2640                         data and adding to linear_offset*/
2641                         linear_offset +=
2642                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644                 }
2645         }
2646
2647         I915_WRITE(reg, dspcntr);
2648
2649         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651                       fb->pitches[0]);
2652         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653         I915_WRITE(DSPSURF(plane),
2654                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657         } else {
2658                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660         }
2661         POSTING_READ(reg);
2662 }
2663
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665                                          struct drm_framebuffer *fb,
2666                                          int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct intel_framebuffer *intel_fb;
2672         struct drm_i915_gem_object *obj;
2673         int pipe = intel_crtc->pipe;
2674         u32 plane_ctl, stride;
2675
2676         if (!intel_crtc->primary_enabled) {
2677                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679                 POSTING_READ(PLANE_CTL(pipe, 0));
2680                 return;
2681         }
2682
2683         plane_ctl = PLANE_CTL_ENABLE |
2684                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2685                     PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687         switch (fb->pixel_format) {
2688         case DRM_FORMAT_RGB565:
2689                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690                 break;
2691         case DRM_FORMAT_XRGB8888:
2692                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693                 break;
2694         case DRM_FORMAT_XBGR8888:
2695                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697                 break;
2698         case DRM_FORMAT_XRGB2101010:
2699                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700                 break;
2701         case DRM_FORMAT_XBGR2101010:
2702                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704                 break;
2705         default:
2706                 BUG();
2707         }
2708
2709         intel_fb = to_intel_framebuffer(fb);
2710         obj = intel_fb->obj;
2711
2712         /*
2713          * The stride is either expressed as a multiple of 64 bytes chunks for
2714          * linear buffers or in number of tiles for tiled buffers.
2715          */
2716         switch (obj->tiling_mode) {
2717         case I915_TILING_NONE:
2718                 stride = fb->pitches[0] >> 6;
2719                 break;
2720         case I915_TILING_X:
2721                 plane_ctl |= PLANE_CTL_TILED_X;
2722                 stride = fb->pitches[0] >> 9;
2723                 break;
2724         default:
2725                 BUG();
2726         }
2727
2728         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730                 plane_ctl |= PLANE_CTL_ROTATE_180;
2731
2732         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735                       i915_gem_obj_ggtt_offset(obj),
2736                       x, y, fb->width, fb->height,
2737                       fb->pitches[0]);
2738
2739         I915_WRITE(PLANE_POS(pipe, 0), 0);
2740         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741         I915_WRITE(PLANE_SIZE(pipe, 0),
2742                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2743                    (intel_crtc->config.pipe_src_w - 1));
2744         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747         POSTING_READ(PLANE_SURF(pipe, 0));
2748 }
2749
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2751 static int
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753                            int x, int y, enum mode_set_atomic state)
2754 {
2755         struct drm_device *dev = crtc->dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757
2758         if (dev_priv->display.disable_fbc)
2759                 dev_priv->display.disable_fbc(dev);
2760
2761         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763         return 0;
2764 }
2765
2766 void intel_display_handle_reset(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct drm_crtc *crtc;
2770
2771         /*
2772          * Flips in the rings have been nuked by the reset,
2773          * so complete all pending flips so that user space
2774          * will get its events and not get stuck.
2775          *
2776          * Also update the base address of all primary
2777          * planes to the the last fb to make sure we're
2778          * showing the correct fb after a reset.
2779          *
2780          * Need to make two loops over the crtcs so that we
2781          * don't try to grab a crtc mutex before the
2782          * pending_flip_queue really got woken up.
2783          */
2784
2785         for_each_crtc(dev, crtc) {
2786                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787                 enum plane plane = intel_crtc->plane;
2788
2789                 intel_prepare_page_flip(dev, plane);
2790                 intel_finish_page_flip_plane(dev, plane);
2791         }
2792
2793         for_each_crtc(dev, crtc) {
2794                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
2796                 drm_modeset_lock(&crtc->mutex, NULL);
2797                 /*
2798                  * FIXME: Once we have proper support for primary planes (and
2799                  * disabling them without disabling the entire crtc) allow again
2800                  * a NULL crtc->primary->fb.
2801                  */
2802                 if (intel_crtc->active && crtc->primary->fb)
2803                         dev_priv->display.update_primary_plane(crtc,
2804                                                                crtc->primary->fb,
2805                                                                crtc->x,
2806                                                                crtc->y);
2807                 drm_modeset_unlock(&crtc->mutex);
2808         }
2809 }
2810
2811 static int
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2813 {
2814         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816         bool was_interruptible = dev_priv->mm.interruptible;
2817         int ret;
2818
2819         /* Big Hammer, we also need to ensure that any pending
2820          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821          * current scanout is retired before unpinning the old
2822          * framebuffer.
2823          *
2824          * This should only fail upon a hung GPU, in which case we
2825          * can safely continue.
2826          */
2827         dev_priv->mm.interruptible = false;
2828         ret = i915_gem_object_finish_gpu(obj);
2829         dev_priv->mm.interruptible = was_interruptible;
2830
2831         return ret;
2832 }
2833
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irq(&dev->event_lock);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irq(&dev->event_lock);
2848
2849         return pending;
2850 }
2851
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->base.dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         const struct drm_display_mode *adjusted_mode;
2857
2858         if (!i915.fastboot)
2859                 return;
2860
2861         /*
2862          * Update pipe size and adjust fitter if needed: the reason for this is
2863          * that in compute_mode_changes we check the native mode (not the pfit
2864          * mode) to see if we can flip rather than do a full mode set. In the
2865          * fastboot case, we'll flip, but if we don't update the pipesrc and
2866          * pfit state, we'll end up with a big fb scanned out into the wrong
2867          * sized surface.
2868          *
2869          * To fix this properly, we need to hoist the checks up into
2870          * compute_mode_changes (or above), check the actual pfit state and
2871          * whether the platform allows pfit disable with pipe active, and only
2872          * then update the pipesrc and pfit state, even on the flip path.
2873          */
2874
2875         adjusted_mode = &crtc->config.adjusted_mode;
2876
2877         I915_WRITE(PIPESRC(crtc->pipe),
2878                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879                    (adjusted_mode->crtc_vdisplay - 1));
2880         if (!crtc->config.pch_pfit.enabled &&
2881             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886         }
2887         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889 }
2890
2891 static int
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893                     struct drm_framebuffer *fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         enum pipe pipe = intel_crtc->pipe;
2899         struct drm_framebuffer *old_fb = crtc->primary->fb;
2900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2902         int ret;
2903
2904         if (intel_crtc_has_pending_flip(crtc)) {
2905                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906                 return -EBUSY;
2907         }
2908
2909         /* no fb bound */
2910         if (!fb) {
2911                 DRM_ERROR("No FB bound\n");
2912                 return 0;
2913         }
2914
2915         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917                           plane_name(intel_crtc->plane),
2918                           INTEL_INFO(dev)->num_pipes);
2919                 return -EINVAL;
2920         }
2921
2922         mutex_lock(&dev->struct_mutex);
2923         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924         if (ret == 0)
2925                 i915_gem_track_fb(old_obj, obj,
2926                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2927         mutex_unlock(&dev->struct_mutex);
2928         if (ret != 0) {
2929                 DRM_ERROR("pin & fence failed\n");
2930                 return ret;
2931         }
2932
2933         intel_update_pipe_size(intel_crtc);
2934
2935         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2936
2937         if (intel_crtc->active)
2938                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
2940         crtc->primary->fb = fb;
2941         crtc->x = x;
2942         crtc->y = y;
2943
2944         if (old_fb) {
2945                 if (intel_crtc->active && old_fb != fb)
2946                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2947                 mutex_lock(&dev->struct_mutex);
2948                 intel_unpin_fb_obj(old_obj);
2949                 mutex_unlock(&dev->struct_mutex);
2950         }
2951
2952         mutex_lock(&dev->struct_mutex);
2953         intel_update_fbc(dev);
2954         mutex_unlock(&dev->struct_mutex);
2955
2956         return 0;
2957 }
2958
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         int pipe = intel_crtc->pipe;
2965         u32 reg, temp;
2966
2967         /* enable normal train */
2968         reg = FDI_TX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (IS_IVYBRIDGE(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2976         }
2977         I915_WRITE(reg, temp);
2978
2979         reg = FDI_RX_CTL(pipe);
2980         temp = I915_READ(reg);
2981         if (HAS_PCH_CPT(dev)) {
2982                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984         } else {
2985                 temp &= ~FDI_LINK_TRAIN_NONE;
2986                 temp |= FDI_LINK_TRAIN_NONE;
2987         }
2988         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990         /* wait one idle pattern time */
2991         POSTING_READ(reg);
2992         udelay(1000);
2993
2994         /* IVB wants error correction enabled */
2995         if (IS_IVYBRIDGE(dev))
2996                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997                            FDI_FE_ERRC_ENABLE);
2998 }
2999
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3001 {
3002         return crtc->base.enabled && crtc->active &&
3003                 crtc->config.has_pch_encoder;
3004 }
3005
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *pipe_B_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011         struct intel_crtc *pipe_C_crtc =
3012                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013         uint32_t temp;
3014
3015         /*
3016          * When everything is off disable fdi C so that we could enable fdi B
3017          * with all lanes. Note that we don't care about enabled pipes without
3018          * an enabled pch encoder.
3019          */
3020         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021             !pipe_has_enabled_pch(pipe_C_crtc)) {
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025                 temp = I915_READ(SOUTH_CHICKEN1);
3026                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028                 I915_WRITE(SOUTH_CHICKEN1, temp);
3029         }
3030 }
3031
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp, tries;
3040
3041         /* FDI needs bits from pipe first */
3042         assert_pipe_enabled(dev_priv, pipe);
3043
3044         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045            for train result */
3046         reg = FDI_RX_IMR(pipe);
3047         temp = I915_READ(reg);
3048         temp &= ~FDI_RX_SYMBOL_LOCK;
3049         temp &= ~FDI_RX_BIT_LOCK;
3050         I915_WRITE(reg, temp);
3051         I915_READ(reg);
3052         udelay(150);
3053
3054         /* enable CPU FDI TX and PCH FDI RX */
3055         reg = FDI_TX_CTL(pipe);
3056         temp = I915_READ(reg);
3057         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059         temp &= ~FDI_LINK_TRAIN_NONE;
3060         temp |= FDI_LINK_TRAIN_PATTERN_1;
3061         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3062
3063         reg = FDI_RX_CTL(pipe);
3064         temp = I915_READ(reg);
3065         temp &= ~FDI_LINK_TRAIN_NONE;
3066         temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069         POSTING_READ(reg);
3070         udelay(150);
3071
3072         /* Ironlake workaround, enable clock pointer after FDI enable*/
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075                    FDI_RX_PHASE_SYNC_POINTER_EN);
3076
3077         reg = FDI_RX_IIR(pipe);
3078         for (tries = 0; tries < 5; tries++) {
3079                 temp = I915_READ(reg);
3080                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                 if ((temp & FDI_RX_BIT_LOCK)) {
3083                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3084                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                         break;
3086                 }
3087         }
3088         if (tries == 5)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         I915_WRITE(reg, temp);
3097
3098         reg = FDI_RX_CTL(pipe);
3099         temp = I915_READ(reg);
3100         temp &= ~FDI_LINK_TRAIN_NONE;
3101         temp |= FDI_LINK_TRAIN_PATTERN_2;
3102         I915_WRITE(reg, temp);
3103
3104         POSTING_READ(reg);
3105         udelay(150);
3106
3107         reg = FDI_RX_IIR(pipe);
3108         for (tries = 0; tries < 5; tries++) {
3109                 temp = I915_READ(reg);
3110                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112                 if (temp & FDI_RX_SYMBOL_LOCK) {
3113                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3115                         break;
3116                 }
3117         }
3118         if (tries == 5)
3119                 DRM_ERROR("FDI train 2 fail!\n");
3120
3121         DRM_DEBUG_KMS("FDI train done\n");
3122
3123 }
3124
3125 static const int snb_b_fdi_train_param[] = {
3126         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130 };
3131
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134 {
3135         struct drm_device *dev = crtc->dev;
3136         struct drm_i915_private *dev_priv = dev->dev_private;
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp, i, retry;
3140
3141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142            for train result */
3143         reg = FDI_RX_IMR(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_RX_SYMBOL_LOCK;
3146         temp &= ~FDI_RX_BIT_LOCK;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         /* enable CPU FDI TX and PCH FDI RX */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_1;
3159         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160         /* SNB-B */
3161         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3163
3164         I915_WRITE(FDI_RX_MISC(pipe),
3165                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
3167         reg = FDI_RX_CTL(pipe);
3168         temp = I915_READ(reg);
3169         if (HAS_PCH_CPT(dev)) {
3170                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172         } else {
3173                 temp &= ~FDI_LINK_TRAIN_NONE;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175         }
3176         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178         POSTING_READ(reg);
3179         udelay(150);
3180
3181         for (i = 0; i < 4; i++) {
3182                 reg = FDI_TX_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185                 temp |= snb_b_fdi_train_param[i];
3186                 I915_WRITE(reg, temp);
3187
3188                 POSTING_READ(reg);
3189                 udelay(500);
3190
3191                 for (retry = 0; retry < 5; retry++) {
3192                         reg = FDI_RX_IIR(pipe);
3193                         temp = I915_READ(reg);
3194                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195                         if (temp & FDI_RX_BIT_LOCK) {
3196                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198                                 break;
3199                         }
3200                         udelay(50);
3201                 }
3202                 if (retry < 5)
3203                         break;
3204         }
3205         if (i == 4)
3206                 DRM_ERROR("FDI train 1 fail!\n");
3207
3208         /* Train 2 */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_LINK_TRAIN_NONE;
3212         temp |= FDI_LINK_TRAIN_PATTERN_2;
3213         if (IS_GEN6(dev)) {
3214                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215                 /* SNB-B */
3216                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217         }
3218         I915_WRITE(reg, temp);
3219
3220         reg = FDI_RX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (HAS_PCH_CPT(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         POSTING_READ(reg);
3232         udelay(150);
3233
3234         for (i = 0; i < 4; i++) {
3235                 reg = FDI_TX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238                 temp |= snb_b_fdi_train_param[i];
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(500);
3243
3244                 for (retry = 0; retry < 5; retry++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248                         if (temp & FDI_RX_SYMBOL_LOCK) {
3249                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251                                 break;
3252                         }
3253                         udelay(50);
3254                 }
3255                 if (retry < 5)
3256                         break;
3257         }
3258         if (i == 4)
3259                 DRM_ERROR("FDI train 2 fail!\n");
3260
3261         DRM_DEBUG_KMS("FDI train done.\n");
3262 }
3263
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp, i, j;
3272
3273         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274            for train result */
3275         reg = FDI_RX_IMR(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_RX_SYMBOL_LOCK;
3278         temp &= ~FDI_RX_BIT_LOCK;
3279         I915_WRITE(reg, temp);
3280
3281         POSTING_READ(reg);
3282         udelay(150);
3283
3284         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285                       I915_READ(FDI_RX_IIR(pipe)));
3286
3287         /* Try each vswing and preemphasis setting twice before moving on */
3288         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289                 /* disable first in case we need to retry */
3290                 reg = FDI_TX_CTL(pipe);
3291                 temp = I915_READ(reg);
3292                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293                 temp &= ~FDI_TX_ENABLE;
3294                 I915_WRITE(reg, temp);
3295
3296                 reg = FDI_RX_CTL(pipe);
3297                 temp = I915_READ(reg);
3298                 temp &= ~FDI_LINK_TRAIN_AUTO;
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp &= ~FDI_RX_ENABLE;
3301                 I915_WRITE(reg, temp);
3302
3303                 /* enable CPU FDI TX and PCH FDI RX */
3304                 reg = FDI_TX_CTL(pipe);
3305                 temp = I915_READ(reg);
3306                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310                 temp |= snb_b_fdi_train_param[j/2];
3311                 temp |= FDI_COMPOSITE_SYNC;
3312                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314                 I915_WRITE(FDI_RX_MISC(pipe),
3315                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317                 reg = FDI_RX_CTL(pipe);
3318                 temp = I915_READ(reg);
3319                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320                 temp |= FDI_COMPOSITE_SYNC;
3321                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323                 POSTING_READ(reg);
3324                 udelay(1); /* should be 0.5us */
3325
3326                 for (i = 0; i < 4; i++) {
3327                         reg = FDI_RX_IIR(pipe);
3328                         temp = I915_READ(reg);
3329                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331                         if (temp & FDI_RX_BIT_LOCK ||
3332                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335                                               i);
3336                                 break;
3337                         }
3338                         udelay(1); /* should be 0.5us */
3339                 }
3340                 if (i == 4) {
3341                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342                         continue;
3343                 }
3344
3345                 /* Train 2 */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356                 I915_WRITE(reg, temp);
3357
3358                 POSTING_READ(reg);
3359                 udelay(2); /* should be 1.5us */
3360
3361                 for (i = 0; i < 4; i++) {
3362                         reg = FDI_RX_IIR(pipe);
3363                         temp = I915_READ(reg);
3364                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3365
3366                         if (temp & FDI_RX_SYMBOL_LOCK ||
3367                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370                                               i);
3371                                 goto train_done;
3372                         }
3373                         udelay(2); /* should be 1.5us */
3374                 }
3375                 if (i == 4)
3376                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3377         }
3378
3379 train_done:
3380         DRM_DEBUG_KMS("FDI train done.\n");
3381 }
3382
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3384 {
3385         struct drm_device *dev = intel_crtc->base.dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         int pipe = intel_crtc->pipe;
3388         u32 reg, temp;
3389
3390
3391         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392         reg = FDI_RX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399         POSTING_READ(reg);
3400         udelay(200);
3401
3402         /* Switch from Rawclk to PCDclk */
3403         temp = I915_READ(reg);
3404         I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406         POSTING_READ(reg);
3407         udelay(200);
3408
3409         /* Enable CPU FDI TX PLL, always on for Ironlake */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3414
3415                 POSTING_READ(reg);
3416                 udelay(100);
3417         }
3418 }
3419
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp;
3426
3427         /* Switch from PCDclk to Rawclk */
3428         reg = FDI_RX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432         /* Disable CPU FDI TX PLL */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444         /* Wait for the clocks to turn off. */
3445         POSTING_READ(reg);
3446         udelay(100);
3447 }
3448
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         /* disable CPU FDI tx and PCH FDI rx */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461         POSTING_READ(reg);
3462
3463         reg = FDI_RX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~(0x7 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471
3472         /* Ironlake workaround, disable clock pointer after downing FDI */
3473         if (HAS_PCH_IBX(dev))
3474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3475
3476         /* still set train pattern 1 */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_LINK_TRAIN_NONE;
3480         temp |= FDI_LINK_TRAIN_PATTERN_1;
3481         I915_WRITE(reg, temp);
3482
3483         reg = FDI_RX_CTL(pipe);
3484         temp = I915_READ(reg);
3485         if (HAS_PCH_CPT(dev)) {
3486                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488         } else {
3489                 temp &= ~FDI_LINK_TRAIN_NONE;
3490                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491         }
3492         /* BPC in FDI rx is consistent with that in PIPECONF */
3493         temp &= ~(0x07 << 16);
3494         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495         I915_WRITE(reg, temp);
3496
3497         POSTING_READ(reg);
3498         udelay(100);
3499 }
3500
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502 {
3503         struct intel_crtc *crtc;
3504
3505         /* Note that we don't need to be called with mode_config.lock here
3506          * as our list of CRTC objects is static for the lifetime of the
3507          * device and so cannot disappear as we iterate. Similarly, we can
3508          * happily treat the predicates as racy, atomic checks as userspace
3509          * cannot claim and pin a new fb without at least acquring the
3510          * struct_mutex and so serialising with us.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (atomic_read(&crtc->unpin_work_count) == 0)
3514                         continue;
3515
3516                 if (crtc->unpin_work)
3517                         intel_wait_for_vblank(dev, crtc->pipe);
3518
3519                 return true;
3520         }
3521
3522         return false;
3523 }
3524
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3526 {
3527         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528         struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530         /* ensure that the unpin work is consistent wrt ->pending. */
3531         smp_rmb();
3532         intel_crtc->unpin_work = NULL;
3533
3534         if (work->event)
3535                 drm_send_vblank_event(intel_crtc->base.dev,
3536                                       intel_crtc->pipe,
3537                                       work->event);
3538
3539         drm_crtc_vblank_put(&intel_crtc->base);
3540
3541         wake_up_all(&dev_priv->pending_flip_queue);
3542         queue_work(dev_priv->wq, &work->work);
3543
3544         trace_i915_flip_complete(intel_crtc->plane,
3545                                  work->pending_flip_obj);
3546 }
3547
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555                                        !intel_crtc_has_pending_flip(crtc),
3556                                        60*HZ) == 0)) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558
3559                 spin_lock_irq(&dev->event_lock);
3560                 if (intel_crtc->unpin_work) {
3561                         WARN_ONCE(1, "Removing stuck page flip\n");
3562                         page_flip_completed(intel_crtc);
3563                 }
3564                 spin_unlock_irq(&dev->event_lock);
3565         }
3566
3567         if (crtc->primary->fb) {
3568                 mutex_lock(&dev->struct_mutex);
3569                 intel_finish_fb(crtc->primary->fb);
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572 }
3573
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581         u32 temp;
3582
3583         mutex_lock(&dev_priv->dpio_lock);
3584
3585         /* It is necessary to ungate the pixclk gate prior to programming
3586          * the divisors, and gate it back when it is done.
3587          */
3588         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590         /* Disable SSCCTL */
3591         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593                                 SBI_SSCCTL_DISABLE,
3594                         SBI_ICLK);
3595
3596         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597         if (clock == 20000) {
3598                 auxdiv = 1;
3599                 divsel = 0x41;
3600                 phaseinc = 0x20;
3601         } else {
3602                 /* The iCLK virtual clock root frequency is in MHz,
3603                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3604                  * divisors, it is necessary to divide one by another, so we
3605                  * convert the virtual clock precision to KHz here for higher
3606                  * precision.
3607                  */
3608                 u32 iclk_virtual_root_freq = 172800 * 1000;
3609                 u32 iclk_pi_range = 64;
3610                 u32 desired_divisor, msb_divisor_value, pi_value;
3611
3612                 desired_divisor = (iclk_virtual_root_freq / clock);
3613                 msb_divisor_value = desired_divisor / iclk_pi_range;
3614                 pi_value = desired_divisor % iclk_pi_range;
3615
3616                 auxdiv = 0;
3617                 divsel = msb_divisor_value - 2;
3618                 phaseinc = pi_value;
3619         }
3620
3621         /* This should not happen with any sane values */
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3628                         clock,
3629                         auxdiv,
3630                         divsel,
3631                         phasedir,
3632                         phaseinc);
3633
3634         /* Program SSCDIVINTPHASE6 */
3635         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3643
3644         /* Program SSCAUXDIV */
3645         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3649
3650         /* Enable modulator and associated divider */
3651         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652         temp &= ~SBI_SSCCTL_DISABLE;
3653         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3654
3655         /* Wait for initialization time */
3656         udelay(24);
3657
3658         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3659
3660         mutex_unlock(&dev_priv->dpio_lock);
3661 }
3662
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664                                                 enum pipe pch_transcoder)
3665 {
3666         struct drm_device *dev = crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671                    I915_READ(HTOTAL(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673                    I915_READ(HBLANK(cpu_transcoder)));
3674         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675                    I915_READ(HSYNC(cpu_transcoder)));
3676
3677         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678                    I915_READ(VTOTAL(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680                    I915_READ(VBLANK(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682                    I915_READ(VSYNC(cpu_transcoder)));
3683         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685 }
3686
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         uint32_t temp;
3691
3692         temp = I915_READ(SOUTH_CHICKEN1);
3693         if (temp & FDI_BC_BIFURCATION_SELECT)
3694                 return;
3695
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699         temp |= FDI_BC_BIFURCATION_SELECT;
3700         DRM_DEBUG_KMS("enabling fdi C rx\n");
3701         I915_WRITE(SOUTH_CHICKEN1, temp);
3702         POSTING_READ(SOUTH_CHICKEN1);
3703 }
3704
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706 {
3707         struct drm_device *dev = intel_crtc->base.dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         switch (intel_crtc->pipe) {
3711         case PIPE_A:
3712                 break;
3713         case PIPE_B:
3714                 if (intel_crtc->config.fdi_lanes > 2)
3715                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716                 else
3717                         cpt_enable_fdi_bc_bifurcation(dev);
3718
3719                 break;
3720         case PIPE_C:
3721                 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723                 break;
3724         default:
3725                 BUG();
3726         }
3727 }
3728
3729 /*
3730  * Enable PCH resources required for PCH ports:
3731  *   - PCH PLLs
3732  *   - FDI training & RX/TX
3733  *   - update transcoder timings
3734  *   - DP transcoding bits
3735  *   - transcoder
3736  */
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745         assert_pch_transcoder_disabled(dev_priv, pipe);
3746
3747         if (IS_IVYBRIDGE(dev))
3748                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
3750         /* Write the TU size bits before fdi link training, so that error
3751          * detection works. */
3752         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
3755         /* For PCH output, training FDI link */
3756         dev_priv->display.fdi_link_train(crtc);
3757
3758         /* We need to program the right clock selection before writing the pixel
3759          * mutliplier into the DPLL. */
3760         if (HAS_PCH_CPT(dev)) {
3761                 u32 sel;
3762
3763                 temp = I915_READ(PCH_DPLL_SEL);
3764                 temp |= TRANS_DPLL_ENABLE(pipe);
3765                 sel = TRANS_DPLLB_SEL(pipe);
3766                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3767                         temp |= sel;
3768                 else
3769                         temp &= ~sel;
3770                 I915_WRITE(PCH_DPLL_SEL, temp);
3771         }
3772
3773         /* XXX: pch pll's can be enabled any time before we enable the PCH
3774          * transcoder, and we actually should do this to not upset any PCH
3775          * transcoder that already use the clock when we share it.
3776          *
3777          * Note that enable_shared_dpll tries to do the right thing, but
3778          * get_shared_dpll unconditionally resets the pll - we need that to have
3779          * the right LVDS enable sequence. */
3780         intel_enable_shared_dpll(intel_crtc);
3781
3782         /* set transcoder timing, panel must allow it */
3783         assert_panel_unlocked(dev_priv, pipe);
3784         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3785
3786         intel_fdi_normal_train(crtc);
3787
3788         /* For PCH DP, enable TRANS_DP_CTL */
3789         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791                 reg = TRANS_DP_CTL(pipe);
3792                 temp = I915_READ(reg);
3793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794                           TRANS_DP_SYNC_MASK |
3795                           TRANS_DP_BPC_MASK);
3796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797                          TRANS_DP_ENH_FRAMING);
3798                 temp |= bpc << 9; /* same format but at 11:9 */
3799
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3804
3805                 switch (intel_trans_dp_port_sel(crtc)) {
3806                 case PCH_DP_B:
3807                         temp |= TRANS_DP_PORT_SEL_B;
3808                         break;
3809                 case PCH_DP_C:
3810                         temp |= TRANS_DP_PORT_SEL_C;
3811                         break;
3812                 case PCH_DP_D:
3813                         temp |= TRANS_DP_PORT_SEL_D;
3814                         break;
3815                 default:
3816                         BUG();
3817                 }
3818
3819                 I915_WRITE(reg, temp);
3820         }
3821
3822         ironlake_enable_pch_transcoder(dev_priv, pipe);
3823 }
3824
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3833
3834         lpt_program_iclkip(crtc);
3835
3836         /* Set transcoder timing. */
3837         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3838
3839         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3840 }
3841
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3843 {
3844         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3845
3846         if (pll == NULL)
3847                 return;
3848
3849         if (pll->refcount == 0) {
3850                 WARN(1, "bad %s refcount\n", pll->name);
3851                 return;
3852         }
3853
3854         if (--pll->refcount == 0) {
3855                 WARN_ON(pll->on);
3856                 WARN_ON(pll->active);
3857         }
3858
3859         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3860 }
3861
3862 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3863 {
3864         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3865         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3866         enum intel_dpll_id i;
3867
3868         if (pll) {
3869                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3870                               crtc->base.base.id, pll->name);
3871                 intel_put_shared_dpll(crtc);
3872         }
3873
3874         if (HAS_PCH_IBX(dev_priv->dev)) {
3875                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3876                 i = (enum intel_dpll_id) crtc->pipe;
3877                 pll = &dev_priv->shared_dplls[i];
3878
3879                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3880                               crtc->base.base.id, pll->name);
3881
3882                 WARN_ON(pll->refcount);
3883
3884                 goto found;
3885         }
3886
3887         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3888                 pll = &dev_priv->shared_dplls[i];
3889
3890                 /* Only want to check enabled timings first */
3891                 if (pll->refcount == 0)
3892                         continue;
3893
3894                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3895                            sizeof(pll->hw_state)) == 0) {
3896                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3897                                       crtc->base.base.id,
3898                                       pll->name, pll->refcount, pll->active);
3899
3900                         goto found;
3901                 }
3902         }
3903
3904         /* Ok no matching timings, maybe there's a free one? */
3905         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3906                 pll = &dev_priv->shared_dplls[i];
3907                 if (pll->refcount == 0) {
3908                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3909                                       crtc->base.base.id, pll->name);
3910                         goto found;
3911                 }
3912         }
3913
3914         return NULL;
3915
3916 found:
3917         if (pll->refcount == 0)
3918                 pll->hw_state = crtc->config.dpll_hw_state;
3919
3920         crtc->config.shared_dpll = i;
3921         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3922                          pipe_name(crtc->pipe));
3923
3924         pll->refcount++;
3925
3926         return pll;
3927 }
3928
3929 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3930 {
3931         struct drm_i915_private *dev_priv = dev->dev_private;
3932         int dslreg = PIPEDSL(pipe);
3933         u32 temp;
3934
3935         temp = I915_READ(dslreg);
3936         udelay(500);
3937         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3938                 if (wait_for(I915_READ(dslreg) != temp, 5))
3939                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3940         }
3941 }
3942
3943 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3944 {
3945         struct drm_device *dev = crtc->base.dev;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         int pipe = crtc->pipe;
3948
3949         if (crtc->config.pch_pfit.enabled) {
3950                 /* Force use of hard-coded filter coefficients
3951                  * as some pre-programmed values are broken,
3952                  * e.g. x201.
3953                  */
3954                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3955                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3956                                                  PF_PIPE_SEL_IVB(pipe));
3957                 else
3958                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3959                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3960                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3961         }
3962 }
3963
3964 static void intel_enable_planes(struct drm_crtc *crtc)
3965 {
3966         struct drm_device *dev = crtc->dev;
3967         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3968         struct drm_plane *plane;
3969         struct intel_plane *intel_plane;
3970
3971         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3972                 intel_plane = to_intel_plane(plane);
3973                 if (intel_plane->pipe == pipe)
3974                         intel_plane_restore(&intel_plane->base);
3975         }
3976 }
3977
3978 static void intel_disable_planes(struct drm_crtc *crtc)
3979 {
3980         struct drm_device *dev = crtc->dev;
3981         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3982         struct drm_plane *plane;
3983         struct intel_plane *intel_plane;
3984
3985         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3986                 intel_plane = to_intel_plane(plane);
3987                 if (intel_plane->pipe == pipe)
3988                         intel_plane_disable(&intel_plane->base);
3989         }
3990 }
3991
3992 void hsw_enable_ips(struct intel_crtc *crtc)
3993 {
3994         struct drm_device *dev = crtc->base.dev;
3995         struct drm_i915_private *dev_priv = dev->dev_private;
3996
3997         if (!crtc->config.ips_enabled)
3998                 return;
3999
4000         /* We can only enable IPS after we enable a plane and wait for a vblank */
4001         intel_wait_for_vblank(dev, crtc->pipe);
4002
4003         assert_plane_enabled(dev_priv, crtc->plane);
4004         if (IS_BROADWELL(dev)) {
4005                 mutex_lock(&dev_priv->rps.hw_lock);
4006                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4007                 mutex_unlock(&dev_priv->rps.hw_lock);
4008                 /* Quoting Art Runyan: "its not safe to expect any particular
4009                  * value in IPS_CTL bit 31 after enabling IPS through the
4010                  * mailbox." Moreover, the mailbox may return a bogus state,
4011                  * so we need to just enable it and continue on.
4012                  */
4013         } else {
4014                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4015                 /* The bit only becomes 1 in the next vblank, so this wait here
4016                  * is essentially intel_wait_for_vblank. If we don't have this
4017                  * and don't wait for vblanks until the end of crtc_enable, then
4018                  * the HW state readout code will complain that the expected
4019                  * IPS_CTL value is not the one we read. */
4020                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4021                         DRM_ERROR("Timed out waiting for IPS enable\n");
4022         }
4023 }
4024
4025 void hsw_disable_ips(struct intel_crtc *crtc)
4026 {
4027         struct drm_device *dev = crtc->base.dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029
4030         if (!crtc->config.ips_enabled)
4031                 return;
4032
4033         assert_plane_enabled(dev_priv, crtc->plane);
4034         if (IS_BROADWELL(dev)) {
4035                 mutex_lock(&dev_priv->rps.hw_lock);
4036                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4037                 mutex_unlock(&dev_priv->rps.hw_lock);
4038                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4039                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4040                         DRM_ERROR("Timed out waiting for IPS disable\n");
4041         } else {
4042                 I915_WRITE(IPS_CTL, 0);
4043                 POSTING_READ(IPS_CTL);
4044         }
4045
4046         /* We need to wait for a vblank before we can disable the plane. */
4047         intel_wait_for_vblank(dev, crtc->pipe);
4048 }
4049
4050 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4051 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4052 {
4053         struct drm_device *dev = crtc->dev;
4054         struct drm_i915_private *dev_priv = dev->dev_private;
4055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4056         enum pipe pipe = intel_crtc->pipe;
4057         int palreg = PALETTE(pipe);
4058         int i;
4059         bool reenable_ips = false;
4060
4061         /* The clocks have to be on to load the palette. */
4062         if (!crtc->enabled || !intel_crtc->active)
4063                 return;
4064
4065         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4066                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4067                         assert_dsi_pll_enabled(dev_priv);
4068                 else
4069                         assert_pll_enabled(dev_priv, pipe);
4070         }
4071
4072         /* use legacy palette for Ironlake */
4073         if (!HAS_GMCH_DISPLAY(dev))
4074                 palreg = LGC_PALETTE(pipe);
4075
4076         /* Workaround : Do not read or write the pipe palette/gamma data while
4077          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4078          */
4079         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4080             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4081              GAMMA_MODE_MODE_SPLIT)) {
4082                 hsw_disable_ips(intel_crtc);
4083                 reenable_ips = true;
4084         }
4085
4086         for (i = 0; i < 256; i++) {
4087                 I915_WRITE(palreg + 4 * i,
4088                            (intel_crtc->lut_r[i] << 16) |
4089                            (intel_crtc->lut_g[i] << 8) |
4090                            intel_crtc->lut_b[i]);
4091         }
4092
4093         if (reenable_ips)
4094                 hsw_enable_ips(intel_crtc);
4095 }
4096
4097 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4098 {
4099         if (!enable && intel_crtc->overlay) {
4100                 struct drm_device *dev = intel_crtc->base.dev;
4101                 struct drm_i915_private *dev_priv = dev->dev_private;
4102
4103                 mutex_lock(&dev->struct_mutex);
4104                 dev_priv->mm.interruptible = false;
4105                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4106                 dev_priv->mm.interruptible = true;
4107                 mutex_unlock(&dev->struct_mutex);
4108         }
4109
4110         /* Let userspace switch the overlay on again. In most cases userspace
4111          * has to recompute where to put it anyway.
4112          */
4113 }
4114
4115 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4116 {
4117         struct drm_device *dev = crtc->dev;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120
4121         intel_enable_primary_hw_plane(crtc->primary, crtc);
4122         intel_enable_planes(crtc);
4123         intel_crtc_update_cursor(crtc, true);
4124         intel_crtc_dpms_overlay(intel_crtc, true);
4125
4126         hsw_enable_ips(intel_crtc);
4127
4128         mutex_lock(&dev->struct_mutex);
4129         intel_update_fbc(dev);
4130         mutex_unlock(&dev->struct_mutex);
4131
4132         /*
4133          * FIXME: Once we grow proper nuclear flip support out of this we need
4134          * to compute the mask of flip planes precisely. For the time being
4135          * consider this a flip from a NULL plane.
4136          */
4137         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4138 }
4139
4140 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         int pipe = intel_crtc->pipe;
4146         int plane = intel_crtc->plane;
4147
4148         intel_crtc_wait_for_pending_flips(crtc);
4149
4150         if (dev_priv->fbc.plane == plane)
4151                 intel_disable_fbc(dev);
4152
4153         hsw_disable_ips(intel_crtc);
4154
4155         intel_crtc_dpms_overlay(intel_crtc, false);
4156         intel_crtc_update_cursor(crtc, false);
4157         intel_disable_planes(crtc);
4158         intel_disable_primary_hw_plane(crtc->primary, crtc);
4159
4160         /*
4161          * FIXME: Once we grow proper nuclear flip support out of this we need
4162          * to compute the mask of flip planes precisely. For the time being
4163          * consider this a flip to a NULL plane.
4164          */
4165         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4166 }
4167
4168 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4169 {
4170         struct drm_device *dev = crtc->dev;
4171         struct drm_i915_private *dev_priv = dev->dev_private;
4172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4173         struct intel_encoder *encoder;
4174         int pipe = intel_crtc->pipe;
4175
4176         WARN_ON(!crtc->enabled);
4177
4178         if (intel_crtc->active)
4179                 return;
4180
4181         if (intel_crtc->config.has_pch_encoder)
4182                 intel_prepare_shared_dpll(intel_crtc);
4183
4184         if (intel_crtc->config.has_dp_encoder)
4185                 intel_dp_set_m_n(intel_crtc);
4186
4187         intel_set_pipe_timings(intel_crtc);
4188
4189         if (intel_crtc->config.has_pch_encoder) {
4190                 intel_cpu_transcoder_set_m_n(intel_crtc,
4191                                      &intel_crtc->config.fdi_m_n, NULL);
4192         }
4193
4194         ironlake_set_pipeconf(crtc);
4195
4196         intel_crtc->active = true;
4197
4198         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4199         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4200
4201         for_each_encoder_on_crtc(dev, crtc, encoder)
4202                 if (encoder->pre_enable)
4203                         encoder->pre_enable(encoder);
4204
4205         if (intel_crtc->config.has_pch_encoder) {
4206                 /* Note: FDI PLL enabling _must_ be done before we enable the
4207                  * cpu pipes, hence this is separate from all the other fdi/pch
4208                  * enabling. */
4209                 ironlake_fdi_pll_enable(intel_crtc);
4210         } else {
4211                 assert_fdi_tx_disabled(dev_priv, pipe);
4212                 assert_fdi_rx_disabled(dev_priv, pipe);
4213         }
4214
4215         ironlake_pfit_enable(intel_crtc);
4216
4217         /*
4218          * On ILK+ LUT must be loaded before the pipe is running but with
4219          * clocks enabled
4220          */
4221         intel_crtc_load_lut(crtc);
4222
4223         intel_update_watermarks(crtc);
4224         intel_enable_pipe(intel_crtc);
4225
4226         if (intel_crtc->config.has_pch_encoder)
4227                 ironlake_pch_enable(crtc);
4228
4229         for_each_encoder_on_crtc(dev, crtc, encoder)
4230                 encoder->enable(encoder);
4231
4232         if (HAS_PCH_CPT(dev))
4233                 cpt_verify_modeset(dev, intel_crtc->pipe);
4234
4235         assert_vblank_disabled(crtc);
4236         drm_crtc_vblank_on(crtc);
4237
4238         intel_crtc_enable_planes(crtc);
4239 }
4240
4241 /* IPS only exists on ULT machines and is tied to pipe A. */
4242 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4243 {
4244         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4245 }
4246
4247 /*
4248  * This implements the workaround described in the "notes" section of the mode
4249  * set sequence documentation. When going from no pipes or single pipe to
4250  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4251  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4252  */
4253 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4254 {
4255         struct drm_device *dev = crtc->base.dev;
4256         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4257
4258         /* We want to get the other_active_crtc only if there's only 1 other
4259          * active crtc. */
4260         for_each_intel_crtc(dev, crtc_it) {
4261                 if (!crtc_it->active || crtc_it == crtc)
4262                         continue;
4263
4264                 if (other_active_crtc)
4265                         return;
4266
4267                 other_active_crtc = crtc_it;
4268         }
4269         if (!other_active_crtc)
4270                 return;
4271
4272         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4273         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4274 }
4275
4276 static void haswell_crtc_enable(struct drm_crtc *crtc)
4277 {
4278         struct drm_device *dev = crtc->dev;
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281         struct intel_encoder *encoder;
4282         int pipe = intel_crtc->pipe;
4283
4284         WARN_ON(!crtc->enabled);
4285
4286         if (intel_crtc->active)
4287                 return;
4288
4289         if (intel_crtc_to_shared_dpll(intel_crtc))
4290                 intel_enable_shared_dpll(intel_crtc);
4291
4292         if (intel_crtc->config.has_dp_encoder)
4293                 intel_dp_set_m_n(intel_crtc);
4294
4295         intel_set_pipe_timings(intel_crtc);
4296
4297         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4298                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4299                            intel_crtc->config.pixel_multiplier - 1);
4300         }
4301
4302         if (intel_crtc->config.has_pch_encoder) {
4303                 intel_cpu_transcoder_set_m_n(intel_crtc,
4304                                      &intel_crtc->config.fdi_m_n, NULL);
4305         }
4306
4307         haswell_set_pipeconf(crtc);
4308
4309         intel_set_pipe_csc(crtc);
4310
4311         intel_crtc->active = true;
4312
4313         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4314         for_each_encoder_on_crtc(dev, crtc, encoder)
4315                 if (encoder->pre_enable)
4316                         encoder->pre_enable(encoder);
4317
4318         if (intel_crtc->config.has_pch_encoder) {
4319                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4320                                                       true);
4321                 dev_priv->display.fdi_link_train(crtc);
4322         }
4323
4324         intel_ddi_enable_pipe_clock(intel_crtc);
4325
4326         ironlake_pfit_enable(intel_crtc);
4327
4328         /*
4329          * On ILK+ LUT must be loaded before the pipe is running but with
4330          * clocks enabled
4331          */
4332         intel_crtc_load_lut(crtc);
4333
4334         intel_ddi_set_pipe_settings(crtc);
4335         intel_ddi_enable_transcoder_func(crtc);
4336
4337         intel_update_watermarks(crtc);
4338         intel_enable_pipe(intel_crtc);
4339
4340         if (intel_crtc->config.has_pch_encoder)
4341                 lpt_pch_enable(crtc);
4342
4343         if (intel_crtc->config.dp_encoder_is_mst)
4344                 intel_ddi_set_vc_payload_alloc(crtc, true);
4345
4346         for_each_encoder_on_crtc(dev, crtc, encoder) {
4347                 encoder->enable(encoder);
4348                 intel_opregion_notify_encoder(encoder, true);
4349         }
4350
4351         assert_vblank_disabled(crtc);
4352         drm_crtc_vblank_on(crtc);
4353
4354         /* If we change the relative order between pipe/planes enabling, we need
4355          * to change the workaround. */
4356         haswell_mode_set_planes_workaround(intel_crtc);
4357         intel_crtc_enable_planes(crtc);
4358 }
4359
4360 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4361 {
4362         struct drm_device *dev = crtc->base.dev;
4363         struct drm_i915_private *dev_priv = dev->dev_private;
4364         int pipe = crtc->pipe;
4365
4366         /* To avoid upsetting the power well on haswell only disable the pfit if
4367          * it's in use. The hw state code will make sure we get this right. */
4368         if (crtc->config.pch_pfit.enabled) {
4369                 I915_WRITE(PF_CTL(pipe), 0);
4370                 I915_WRITE(PF_WIN_POS(pipe), 0);
4371                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4372         }
4373 }
4374
4375 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4376 {
4377         struct drm_device *dev = crtc->dev;
4378         struct drm_i915_private *dev_priv = dev->dev_private;
4379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380         struct intel_encoder *encoder;
4381         int pipe = intel_crtc->pipe;
4382         u32 reg, temp;
4383
4384         if (!intel_crtc->active)
4385                 return;
4386
4387         intel_crtc_disable_planes(crtc);
4388
4389         drm_crtc_vblank_off(crtc);
4390         assert_vblank_disabled(crtc);
4391
4392         for_each_encoder_on_crtc(dev, crtc, encoder)
4393                 encoder->disable(encoder);
4394
4395         if (intel_crtc->config.has_pch_encoder)
4396                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4397
4398         intel_disable_pipe(intel_crtc);
4399
4400         ironlake_pfit_disable(intel_crtc);
4401
4402         for_each_encoder_on_crtc(dev, crtc, encoder)
4403                 if (encoder->post_disable)
4404                         encoder->post_disable(encoder);
4405
4406         if (intel_crtc->config.has_pch_encoder) {
4407                 ironlake_fdi_disable(crtc);
4408
4409                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4410                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4411
4412                 if (HAS_PCH_CPT(dev)) {
4413                         /* disable TRANS_DP_CTL */
4414                         reg = TRANS_DP_CTL(pipe);
4415                         temp = I915_READ(reg);
4416                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4417                                   TRANS_DP_PORT_SEL_MASK);
4418                         temp |= TRANS_DP_PORT_SEL_NONE;
4419                         I915_WRITE(reg, temp);
4420
4421                         /* disable DPLL_SEL */
4422                         temp = I915_READ(PCH_DPLL_SEL);
4423                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4424                         I915_WRITE(PCH_DPLL_SEL, temp);
4425                 }
4426
4427                 /* disable PCH DPLL */
4428                 intel_disable_shared_dpll(intel_crtc);
4429
4430                 ironlake_fdi_pll_disable(intel_crtc);
4431         }
4432
4433         intel_crtc->active = false;
4434         intel_update_watermarks(crtc);
4435
4436         mutex_lock(&dev->struct_mutex);
4437         intel_update_fbc(dev);
4438         mutex_unlock(&dev->struct_mutex);
4439 }
4440
4441 static void haswell_crtc_disable(struct drm_crtc *crtc)
4442 {
4443         struct drm_device *dev = crtc->dev;
4444         struct drm_i915_private *dev_priv = dev->dev_private;
4445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4446         struct intel_encoder *encoder;
4447         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4448
4449         if (!intel_crtc->active)
4450                 return;
4451
4452         intel_crtc_disable_planes(crtc);
4453
4454         drm_crtc_vblank_off(crtc);
4455         assert_vblank_disabled(crtc);
4456
4457         for_each_encoder_on_crtc(dev, crtc, encoder) {
4458                 intel_opregion_notify_encoder(encoder, false);
4459                 encoder->disable(encoder);
4460         }
4461
4462         if (intel_crtc->config.has_pch_encoder)
4463                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4464                                                       false);
4465         intel_disable_pipe(intel_crtc);
4466
4467         if (intel_crtc->config.dp_encoder_is_mst)
4468                 intel_ddi_set_vc_payload_alloc(crtc, false);
4469
4470         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4471
4472         ironlake_pfit_disable(intel_crtc);
4473
4474         intel_ddi_disable_pipe_clock(intel_crtc);
4475
4476         if (intel_crtc->config.has_pch_encoder) {
4477                 lpt_disable_pch_transcoder(dev_priv);
4478                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4479                                                       true);
4480                 intel_ddi_fdi_disable(crtc);
4481         }
4482
4483         for_each_encoder_on_crtc(dev, crtc, encoder)
4484                 if (encoder->post_disable)
4485                         encoder->post_disable(encoder);
4486
4487         intel_crtc->active = false;
4488         intel_update_watermarks(crtc);
4489
4490         mutex_lock(&dev->struct_mutex);
4491         intel_update_fbc(dev);
4492         mutex_unlock(&dev->struct_mutex);
4493
4494         if (intel_crtc_to_shared_dpll(intel_crtc))
4495                 intel_disable_shared_dpll(intel_crtc);
4496 }
4497
4498 static void ironlake_crtc_off(struct drm_crtc *crtc)
4499 {
4500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4501         intel_put_shared_dpll(intel_crtc);
4502 }
4503
4504
4505 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4506 {
4507         struct drm_device *dev = crtc->base.dev;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         struct intel_crtc_config *pipe_config = &crtc->config;
4510
4511         if (!crtc->config.gmch_pfit.control)
4512                 return;
4513
4514         /*
4515          * The panel fitter should only be adjusted whilst the pipe is disabled,
4516          * according to register description and PRM.
4517          */
4518         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4519         assert_pipe_disabled(dev_priv, crtc->pipe);
4520
4521         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4522         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4523
4524         /* Border color in case we don't scale up to the full screen. Black by
4525          * default, change to something else for debugging. */
4526         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4527 }
4528
4529 static enum intel_display_power_domain port_to_power_domain(enum port port)
4530 {
4531         switch (port) {
4532         case PORT_A:
4533                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4534         case PORT_B:
4535                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4536         case PORT_C:
4537                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4538         case PORT_D:
4539                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4540         default:
4541                 WARN_ON_ONCE(1);
4542                 return POWER_DOMAIN_PORT_OTHER;
4543         }
4544 }
4545
4546 #define for_each_power_domain(domain, mask)                             \
4547         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4548                 if ((1 << (domain)) & (mask))
4549
4550 enum intel_display_power_domain
4551 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4552 {
4553         struct drm_device *dev = intel_encoder->base.dev;
4554         struct intel_digital_port *intel_dig_port;
4555
4556         switch (intel_encoder->type) {
4557         case INTEL_OUTPUT_UNKNOWN:
4558                 /* Only DDI platforms should ever use this output type */
4559                 WARN_ON_ONCE(!HAS_DDI(dev));
4560         case INTEL_OUTPUT_DISPLAYPORT:
4561         case INTEL_OUTPUT_HDMI:
4562         case INTEL_OUTPUT_EDP:
4563                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4564                 return port_to_power_domain(intel_dig_port->port);
4565         case INTEL_OUTPUT_DP_MST:
4566                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4567                 return port_to_power_domain(intel_dig_port->port);
4568         case INTEL_OUTPUT_ANALOG:
4569                 return POWER_DOMAIN_PORT_CRT;
4570         case INTEL_OUTPUT_DSI:
4571                 return POWER_DOMAIN_PORT_DSI;
4572         default:
4573                 return POWER_DOMAIN_PORT_OTHER;
4574         }
4575 }
4576
4577 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4578 {
4579         struct drm_device *dev = crtc->dev;
4580         struct intel_encoder *intel_encoder;
4581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582         enum pipe pipe = intel_crtc->pipe;
4583         unsigned long mask;
4584         enum transcoder transcoder;
4585
4586         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4587
4588         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4589         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4590         if (intel_crtc->config.pch_pfit.enabled ||
4591             intel_crtc->config.pch_pfit.force_thru)
4592                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4593
4594         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4595                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4596
4597         return mask;
4598 }
4599
4600 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4601 {
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4604         struct intel_crtc *crtc;
4605
4606         /*
4607          * First get all needed power domains, then put all unneeded, to avoid
4608          * any unnecessary toggling of the power wells.
4609          */
4610         for_each_intel_crtc(dev, crtc) {
4611                 enum intel_display_power_domain domain;
4612
4613                 if (!crtc->base.enabled)
4614                         continue;
4615
4616                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4617
4618                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4619                         intel_display_power_get(dev_priv, domain);
4620         }
4621
4622         for_each_intel_crtc(dev, crtc) {
4623                 enum intel_display_power_domain domain;
4624
4625                 for_each_power_domain(domain, crtc->enabled_power_domains)
4626                         intel_display_power_put(dev_priv, domain);
4627
4628                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4629         }
4630
4631         intel_display_set_init_power(dev_priv, false);
4632 }
4633
4634 /* returns HPLL frequency in kHz */
4635 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4636 {
4637         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4638
4639         /* Obtain SKU information */
4640         mutex_lock(&dev_priv->dpio_lock);
4641         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4642                 CCK_FUSE_HPLL_FREQ_MASK;
4643         mutex_unlock(&dev_priv->dpio_lock);
4644
4645         return vco_freq[hpll_freq] * 1000;
4646 }
4647
4648 static void vlv_update_cdclk(struct drm_device *dev)
4649 {
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651
4652         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4653         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4654                          dev_priv->vlv_cdclk_freq);
4655
4656         /*
4657          * Program the gmbus_freq based on the cdclk frequency.
4658          * BSpec erroneously claims we should aim for 4MHz, but
4659          * in fact 1MHz is the correct frequency.
4660          */
4661         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4662 }
4663
4664 /* Adjust CDclk dividers to allow high res or save power if possible */
4665 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4666 {
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668         u32 val, cmd;
4669
4670         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4671
4672         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4673                 cmd = 2;
4674         else if (cdclk == 266667)
4675                 cmd = 1;
4676         else
4677                 cmd = 0;
4678
4679         mutex_lock(&dev_priv->rps.hw_lock);
4680         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4681         val &= ~DSPFREQGUAR_MASK;
4682         val |= (cmd << DSPFREQGUAR_SHIFT);
4683         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4684         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4685                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4686                      50)) {
4687                 DRM_ERROR("timed out waiting for CDclk change\n");
4688         }
4689         mutex_unlock(&dev_priv->rps.hw_lock);
4690
4691         if (cdclk == 400000) {
4692                 u32 divider, vco;
4693
4694                 vco = valleyview_get_vco(dev_priv);
4695                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4696
4697                 mutex_lock(&dev_priv->dpio_lock);
4698                 /* adjust cdclk divider */
4699                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4700                 val &= ~DISPLAY_FREQUENCY_VALUES;
4701                 val |= divider;
4702                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4703
4704                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4705                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4706                              50))
4707                         DRM_ERROR("timed out waiting for CDclk change\n");
4708                 mutex_unlock(&dev_priv->dpio_lock);
4709         }
4710
4711         mutex_lock(&dev_priv->dpio_lock);
4712         /* adjust self-refresh exit latency value */
4713         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4714         val &= ~0x7f;
4715
4716         /*
4717          * For high bandwidth configs, we set a higher latency in the bunit
4718          * so that the core display fetch happens in time to avoid underruns.
4719          */
4720         if (cdclk == 400000)
4721                 val |= 4500 / 250; /* 4.5 usec */
4722         else
4723                 val |= 3000 / 250; /* 3.0 usec */
4724         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4725         mutex_unlock(&dev_priv->dpio_lock);
4726
4727         vlv_update_cdclk(dev);
4728 }
4729
4730 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4731 {
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         u32 val, cmd;
4734
4735         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4736
4737         switch (cdclk) {
4738         case 400000:
4739                 cmd = 3;
4740                 break;
4741         case 333333:
4742         case 320000:
4743                 cmd = 2;
4744                 break;
4745         case 266667:
4746                 cmd = 1;
4747                 break;
4748         case 200000:
4749                 cmd = 0;
4750                 break;
4751         default:
4752                 WARN_ON(1);
4753                 return;
4754         }
4755
4756         mutex_lock(&dev_priv->rps.hw_lock);
4757         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4758         val &= ~DSPFREQGUAR_MASK_CHV;
4759         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4760         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4761         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4762                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4763                      50)) {
4764                 DRM_ERROR("timed out waiting for CDclk change\n");
4765         }
4766         mutex_unlock(&dev_priv->rps.hw_lock);
4767
4768         vlv_update_cdclk(dev);
4769 }
4770
4771 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4772                                  int max_pixclk)
4773 {
4774         int vco = valleyview_get_vco(dev_priv);
4775         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4776
4777         /* FIXME: Punit isn't quite ready yet */
4778         if (IS_CHERRYVIEW(dev_priv->dev))
4779                 return 400000;
4780
4781         /*
4782          * Really only a few cases to deal with, as only 4 CDclks are supported:
4783          *   200MHz
4784          *   267MHz
4785          *   320/333MHz (depends on HPLL freq)
4786          *   400MHz
4787          * So we check to see whether we're above 90% of the lower bin and
4788          * adjust if needed.
4789          *
4790          * We seem to get an unstable or solid color picture at 200MHz.
4791          * Not sure what's wrong. For now use 200MHz only when all pipes
4792          * are off.
4793          */
4794         if (max_pixclk > freq_320*9/10)
4795                 return 400000;
4796         else if (max_pixclk > 266667*9/10)
4797                 return freq_320;
4798         else if (max_pixclk > 0)
4799                 return 266667;
4800         else
4801                 return 200000;
4802 }
4803
4804 /* compute the max pixel clock for new configuration */
4805 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4806 {
4807         struct drm_device *dev = dev_priv->dev;
4808         struct intel_crtc *intel_crtc;
4809         int max_pixclk = 0;
4810
4811         for_each_intel_crtc(dev, intel_crtc) {
4812                 if (intel_crtc->new_enabled)
4813                         max_pixclk = max(max_pixclk,
4814                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4815         }
4816
4817         return max_pixclk;
4818 }
4819
4820 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4821                                             unsigned *prepare_pipes)
4822 {
4823         struct drm_i915_private *dev_priv = dev->dev_private;
4824         struct intel_crtc *intel_crtc;
4825         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4826
4827         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4828             dev_priv->vlv_cdclk_freq)
4829                 return;
4830
4831         /* disable/enable all currently active pipes while we change cdclk */
4832         for_each_intel_crtc(dev, intel_crtc)
4833                 if (intel_crtc->base.enabled)
4834                         *prepare_pipes |= (1 << intel_crtc->pipe);
4835 }
4836
4837 static void valleyview_modeset_global_resources(struct drm_device *dev)
4838 {
4839         struct drm_i915_private *dev_priv = dev->dev_private;
4840         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4841         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4842
4843         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4844                 if (IS_CHERRYVIEW(dev))
4845                         cherryview_set_cdclk(dev, req_cdclk);
4846                 else
4847                         valleyview_set_cdclk(dev, req_cdclk);
4848         }
4849
4850         modeset_update_crtc_power_domains(dev);
4851 }
4852
4853 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4854 {
4855         struct drm_device *dev = crtc->dev;
4856         struct drm_i915_private *dev_priv = to_i915(dev);
4857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4858         struct intel_encoder *encoder;
4859         int pipe = intel_crtc->pipe;
4860         bool is_dsi;
4861
4862         WARN_ON(!crtc->enabled);
4863
4864         if (intel_crtc->active)
4865                 return;
4866
4867         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4868
4869         if (!is_dsi) {
4870                 if (IS_CHERRYVIEW(dev))
4871                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4872                 else
4873                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4874         }
4875
4876         if (intel_crtc->config.has_dp_encoder)
4877                 intel_dp_set_m_n(intel_crtc);
4878
4879         intel_set_pipe_timings(intel_crtc);
4880
4881         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4882                 struct drm_i915_private *dev_priv = dev->dev_private;
4883
4884                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4885                 I915_WRITE(CHV_CANVAS(pipe), 0);
4886         }
4887
4888         i9xx_set_pipeconf(intel_crtc);
4889
4890         intel_crtc->active = true;
4891
4892         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4893
4894         for_each_encoder_on_crtc(dev, crtc, encoder)
4895                 if (encoder->pre_pll_enable)
4896                         encoder->pre_pll_enable(encoder);
4897
4898         if (!is_dsi) {
4899                 if (IS_CHERRYVIEW(dev))
4900                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4901                 else
4902                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4903         }
4904
4905         for_each_encoder_on_crtc(dev, crtc, encoder)
4906                 if (encoder->pre_enable)
4907                         encoder->pre_enable(encoder);
4908
4909         i9xx_pfit_enable(intel_crtc);
4910
4911         intel_crtc_load_lut(crtc);
4912
4913         intel_update_watermarks(crtc);
4914         intel_enable_pipe(intel_crtc);
4915
4916         for_each_encoder_on_crtc(dev, crtc, encoder)
4917                 encoder->enable(encoder);
4918
4919         assert_vblank_disabled(crtc);
4920         drm_crtc_vblank_on(crtc);
4921
4922         intel_crtc_enable_planes(crtc);
4923
4924         /* Underruns don't raise interrupts, so check manually. */
4925         i9xx_check_fifo_underruns(dev_priv);
4926 }
4927
4928 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4929 {
4930         struct drm_device *dev = crtc->base.dev;
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932
4933         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4934         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4935 }
4936
4937 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct drm_i915_private *dev_priv = to_i915(dev);
4941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942         struct intel_encoder *encoder;
4943         int pipe = intel_crtc->pipe;
4944
4945         WARN_ON(!crtc->enabled);
4946
4947         if (intel_crtc->active)
4948                 return;
4949
4950         i9xx_set_pll_dividers(intel_crtc);
4951
4952         if (intel_crtc->config.has_dp_encoder)
4953                 intel_dp_set_m_n(intel_crtc);
4954
4955         intel_set_pipe_timings(intel_crtc);
4956
4957         i9xx_set_pipeconf(intel_crtc);
4958
4959         intel_crtc->active = true;
4960
4961         if (!IS_GEN2(dev))
4962                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4963
4964         for_each_encoder_on_crtc(dev, crtc, encoder)
4965                 if (encoder->pre_enable)
4966                         encoder->pre_enable(encoder);
4967
4968         i9xx_enable_pll(intel_crtc);
4969
4970         i9xx_pfit_enable(intel_crtc);
4971
4972         intel_crtc_load_lut(crtc);
4973
4974         intel_update_watermarks(crtc);
4975         intel_enable_pipe(intel_crtc);
4976
4977         for_each_encoder_on_crtc(dev, crtc, encoder)
4978                 encoder->enable(encoder);
4979
4980         assert_vblank_disabled(crtc);
4981         drm_crtc_vblank_on(crtc);
4982
4983         intel_crtc_enable_planes(crtc);
4984
4985         /*
4986          * Gen2 reports pipe underruns whenever all planes are disabled.
4987          * So don't enable underrun reporting before at least some planes
4988          * are enabled.
4989          * FIXME: Need to fix the logic to work when we turn off all planes
4990          * but leave the pipe running.
4991          */
4992         if (IS_GEN2(dev))
4993                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4994
4995         /* Underruns don't raise interrupts, so check manually. */
4996         i9xx_check_fifo_underruns(dev_priv);
4997 }
4998
4999 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5000 {
5001         struct drm_device *dev = crtc->base.dev;
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003
5004         if (!crtc->config.gmch_pfit.control)
5005                 return;
5006
5007         assert_pipe_disabled(dev_priv, crtc->pipe);
5008
5009         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5010                          I915_READ(PFIT_CONTROL));
5011         I915_WRITE(PFIT_CONTROL, 0);
5012 }
5013
5014 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5015 {
5016         struct drm_device *dev = crtc->dev;
5017         struct drm_i915_private *dev_priv = dev->dev_private;
5018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5019         struct intel_encoder *encoder;
5020         int pipe = intel_crtc->pipe;
5021
5022         if (!intel_crtc->active)
5023                 return;
5024
5025         /*
5026          * Gen2 reports pipe underruns whenever all planes are disabled.
5027          * So diasble underrun reporting before all the planes get disabled.
5028          * FIXME: Need to fix the logic to work when we turn off all planes
5029          * but leave the pipe running.
5030          */
5031         if (IS_GEN2(dev))
5032                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5033
5034         /*
5035          * Vblank time updates from the shadow to live plane control register
5036          * are blocked if the memory self-refresh mode is active at that
5037          * moment. So to make sure the plane gets truly disabled, disable
5038          * first the self-refresh mode. The self-refresh enable bit in turn
5039          * will be checked/applied by the HW only at the next frame start
5040          * event which is after the vblank start event, so we need to have a
5041          * wait-for-vblank between disabling the plane and the pipe.
5042          */
5043         intel_set_memory_cxsr(dev_priv, false);
5044         intel_crtc_disable_planes(crtc);
5045
5046         /*
5047          * On gen2 planes are double buffered but the pipe isn't, so we must
5048          * wait for planes to fully turn off before disabling the pipe.
5049          * We also need to wait on all gmch platforms because of the
5050          * self-refresh mode constraint explained above.
5051          */
5052         intel_wait_for_vblank(dev, pipe);
5053
5054         drm_crtc_vblank_off(crtc);
5055         assert_vblank_disabled(crtc);
5056
5057         for_each_encoder_on_crtc(dev, crtc, encoder)
5058                 encoder->disable(encoder);
5059
5060         intel_disable_pipe(intel_crtc);
5061
5062         i9xx_pfit_disable(intel_crtc);
5063
5064         for_each_encoder_on_crtc(dev, crtc, encoder)
5065                 if (encoder->post_disable)
5066                         encoder->post_disable(encoder);
5067
5068         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5069                 if (IS_CHERRYVIEW(dev))
5070                         chv_disable_pll(dev_priv, pipe);
5071                 else if (IS_VALLEYVIEW(dev))
5072                         vlv_disable_pll(dev_priv, pipe);
5073                 else
5074                         i9xx_disable_pll(intel_crtc);
5075         }
5076
5077         if (!IS_GEN2(dev))
5078                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5079
5080         intel_crtc->active = false;
5081         intel_update_watermarks(crtc);
5082
5083         mutex_lock(&dev->struct_mutex);
5084         intel_update_fbc(dev);
5085         mutex_unlock(&dev->struct_mutex);
5086 }
5087
5088 static void i9xx_crtc_off(struct drm_crtc *crtc)
5089 {
5090 }
5091
5092 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5093                                     bool enabled)
5094 {
5095         struct drm_device *dev = crtc->dev;
5096         struct drm_i915_master_private *master_priv;
5097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098         int pipe = intel_crtc->pipe;
5099
5100         if (!dev->primary->master)
5101                 return;
5102
5103         master_priv = dev->primary->master->driver_priv;
5104         if (!master_priv->sarea_priv)
5105                 return;
5106
5107         switch (pipe) {
5108         case 0:
5109                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5110                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5111                 break;
5112         case 1:
5113                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5114                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5115                 break;
5116         default:
5117                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5118                 break;
5119         }
5120 }
5121
5122 /* Master function to enable/disable CRTC and corresponding power wells */
5123 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5124 {
5125         struct drm_device *dev = crtc->dev;
5126         struct drm_i915_private *dev_priv = dev->dev_private;
5127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128         enum intel_display_power_domain domain;
5129         unsigned long domains;
5130
5131         if (enable) {
5132                 if (!intel_crtc->active) {
5133                         domains = get_crtc_power_domains(crtc);
5134                         for_each_power_domain(domain, domains)
5135                                 intel_display_power_get(dev_priv, domain);
5136                         intel_crtc->enabled_power_domains = domains;
5137
5138                         dev_priv->display.crtc_enable(crtc);
5139                 }
5140         } else {
5141                 if (intel_crtc->active) {
5142                         dev_priv->display.crtc_disable(crtc);
5143
5144                         domains = intel_crtc->enabled_power_domains;
5145                         for_each_power_domain(domain, domains)
5146                                 intel_display_power_put(dev_priv, domain);
5147                         intel_crtc->enabled_power_domains = 0;
5148                 }
5149         }
5150 }
5151
5152 /**
5153  * Sets the power management mode of the pipe and plane.
5154  */
5155 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5156 {
5157         struct drm_device *dev = crtc->dev;
5158         struct intel_encoder *intel_encoder;
5159         bool enable = false;
5160
5161         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5162                 enable |= intel_encoder->connectors_active;
5163
5164         intel_crtc_control(crtc, enable);
5165
5166         intel_crtc_update_sarea(crtc, enable);
5167 }
5168
5169 static void intel_crtc_disable(struct drm_crtc *crtc)
5170 {
5171         struct drm_device *dev = crtc->dev;
5172         struct drm_connector *connector;
5173         struct drm_i915_private *dev_priv = dev->dev_private;
5174         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5175         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5176
5177         /* crtc should still be enabled when we disable it. */
5178         WARN_ON(!crtc->enabled);
5179
5180         dev_priv->display.crtc_disable(crtc);
5181         intel_crtc_update_sarea(crtc, false);
5182         dev_priv->display.off(crtc);
5183
5184         if (crtc->primary->fb) {
5185                 mutex_lock(&dev->struct_mutex);
5186                 intel_unpin_fb_obj(old_obj);
5187                 i915_gem_track_fb(old_obj, NULL,
5188                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5189                 mutex_unlock(&dev->struct_mutex);
5190                 crtc->primary->fb = NULL;
5191         }
5192
5193         /* Update computed state. */
5194         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5195                 if (!connector->encoder || !connector->encoder->crtc)
5196                         continue;
5197
5198                 if (connector->encoder->crtc != crtc)
5199                         continue;
5200
5201                 connector->dpms = DRM_MODE_DPMS_OFF;
5202                 to_intel_encoder(connector->encoder)->connectors_active = false;
5203         }
5204 }
5205
5206 void intel_encoder_destroy(struct drm_encoder *encoder)
5207 {
5208         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5209
5210         drm_encoder_cleanup(encoder);
5211         kfree(intel_encoder);
5212 }
5213
5214 /* Simple dpms helper for encoders with just one connector, no cloning and only
5215  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5216  * state of the entire output pipe. */
5217 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5218 {
5219         if (mode == DRM_MODE_DPMS_ON) {
5220                 encoder->connectors_active = true;
5221
5222                 intel_crtc_update_dpms(encoder->base.crtc);
5223         } else {
5224                 encoder->connectors_active = false;
5225
5226                 intel_crtc_update_dpms(encoder->base.crtc);
5227         }
5228 }
5229
5230 /* Cross check the actual hw state with our own modeset state tracking (and it's
5231  * internal consistency). */
5232 static void intel_connector_check_state(struct intel_connector *connector)
5233 {
5234         if (connector->get_hw_state(connector)) {
5235                 struct intel_encoder *encoder = connector->encoder;
5236                 struct drm_crtc *crtc;
5237                 bool encoder_enabled;
5238                 enum pipe pipe;
5239
5240                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5241                               connector->base.base.id,
5242                               connector->base.name);
5243
5244                 /* there is no real hw state for MST connectors */
5245                 if (connector->mst_port)
5246                         return;
5247
5248                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5249                      "wrong connector dpms state\n");
5250                 WARN(connector->base.encoder != &encoder->base,
5251                      "active connector not linked to encoder\n");
5252
5253                 if (encoder) {
5254                         WARN(!encoder->connectors_active,
5255                              "encoder->connectors_active not set\n");
5256
5257                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5258                         WARN(!encoder_enabled, "encoder not enabled\n");
5259                         if (WARN_ON(!encoder->base.crtc))
5260                                 return;
5261
5262                         crtc = encoder->base.crtc;
5263
5264                         WARN(!crtc->enabled, "crtc not enabled\n");
5265                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5266                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5267                              "encoder active on the wrong pipe\n");
5268                 }
5269         }
5270 }
5271
5272 /* Even simpler default implementation, if there's really no special case to
5273  * consider. */
5274 void intel_connector_dpms(struct drm_connector *connector, int mode)
5275 {
5276         /* All the simple cases only support two dpms states. */
5277         if (mode != DRM_MODE_DPMS_ON)
5278                 mode = DRM_MODE_DPMS_OFF;
5279
5280         if (mode == connector->dpms)
5281                 return;
5282
5283         connector->dpms = mode;
5284
5285         /* Only need to change hw state when actually enabled */
5286         if (connector->encoder)
5287                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5288
5289         intel_modeset_check_state(connector->dev);
5290 }
5291
5292 /* Simple connector->get_hw_state implementation for encoders that support only
5293  * one connector and no cloning and hence the encoder state determines the state
5294  * of the connector. */
5295 bool intel_connector_get_hw_state(struct intel_connector *connector)
5296 {
5297         enum pipe pipe = 0;
5298         struct intel_encoder *encoder = connector->encoder;
5299
5300         return encoder->get_hw_state(encoder, &pipe);
5301 }
5302
5303 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5304                                      struct intel_crtc_config *pipe_config)
5305 {
5306         struct drm_i915_private *dev_priv = dev->dev_private;
5307         struct intel_crtc *pipe_B_crtc =
5308                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5309
5310         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5311                       pipe_name(pipe), pipe_config->fdi_lanes);
5312         if (pipe_config->fdi_lanes > 4) {
5313                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5314                               pipe_name(pipe), pipe_config->fdi_lanes);
5315                 return false;
5316         }
5317
5318         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5319                 if (pipe_config->fdi_lanes > 2) {
5320                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5321                                       pipe_config->fdi_lanes);
5322                         return false;
5323                 } else {
5324                         return true;
5325                 }
5326         }
5327
5328         if (INTEL_INFO(dev)->num_pipes == 2)
5329                 return true;
5330
5331         /* Ivybridge 3 pipe is really complicated */
5332         switch (pipe) {
5333         case PIPE_A:
5334                 return true;
5335         case PIPE_B:
5336                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5337                     pipe_config->fdi_lanes > 2) {
5338                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5339                                       pipe_name(pipe), pipe_config->fdi_lanes);
5340                         return false;
5341                 }
5342                 return true;
5343         case PIPE_C:
5344                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5345                     pipe_B_crtc->config.fdi_lanes <= 2) {
5346                         if (pipe_config->fdi_lanes > 2) {
5347                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5348                                               pipe_name(pipe), pipe_config->fdi_lanes);
5349                                 return false;
5350                         }
5351                 } else {
5352                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5353                         return false;
5354                 }
5355                 return true;
5356         default:
5357                 BUG();
5358         }
5359 }
5360
5361 #define RETRY 1
5362 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5363                                        struct intel_crtc_config *pipe_config)
5364 {
5365         struct drm_device *dev = intel_crtc->base.dev;
5366         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5367         int lane, link_bw, fdi_dotclock;
5368         bool setup_ok, needs_recompute = false;
5369
5370 retry:
5371         /* FDI is a binary signal running at ~2.7GHz, encoding
5372          * each output octet as 10 bits. The actual frequency
5373          * is stored as a divider into a 100MHz clock, and the
5374          * mode pixel clock is stored in units of 1KHz.
5375          * Hence the bw of each lane in terms of the mode signal
5376          * is:
5377          */
5378         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5379
5380         fdi_dotclock = adjusted_mode->crtc_clock;
5381
5382         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5383                                            pipe_config->pipe_bpp);
5384
5385         pipe_config->fdi_lanes = lane;
5386
5387         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5388                                link_bw, &pipe_config->fdi_m_n);
5389
5390         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5391                                             intel_crtc->pipe, pipe_config);
5392         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5393                 pipe_config->pipe_bpp -= 2*3;
5394                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5395                               pipe_config->pipe_bpp);
5396                 needs_recompute = true;
5397                 pipe_config->bw_constrained = true;
5398
5399                 goto retry;
5400         }
5401
5402         if (needs_recompute)
5403                 return RETRY;
5404
5405         return setup_ok ? 0 : -EINVAL;
5406 }
5407
5408 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5409                                    struct intel_crtc_config *pipe_config)
5410 {
5411         pipe_config->ips_enabled = i915.enable_ips &&
5412                                    hsw_crtc_supports_ips(crtc) &&
5413                                    pipe_config->pipe_bpp <= 24;
5414 }
5415
5416 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5417                                      struct intel_crtc_config *pipe_config)
5418 {
5419         struct drm_device *dev = crtc->base.dev;
5420         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5421
5422         /* FIXME should check pixel clock limits on all platforms */
5423         if (INTEL_INFO(dev)->gen < 4) {
5424                 struct drm_i915_private *dev_priv = dev->dev_private;
5425                 int clock_limit =
5426                         dev_priv->display.get_display_clock_speed(dev);
5427
5428                 /*
5429                  * Enable pixel doubling when the dot clock
5430                  * is > 90% of the (display) core speed.
5431                  *
5432                  * GDG double wide on either pipe,
5433                  * otherwise pipe A only.
5434                  */
5435                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5436                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5437                         clock_limit *= 2;
5438                         pipe_config->double_wide = true;
5439                 }
5440
5441                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5442                         return -EINVAL;
5443         }
5444
5445         /*
5446          * Pipe horizontal size must be even in:
5447          * - DVO ganged mode
5448          * - LVDS dual channel mode
5449          * - Double wide pipe
5450          */
5451         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5452              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5453                 pipe_config->pipe_src_w &= ~1;
5454
5455         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5456          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5457          */
5458         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5459                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5460                 return -EINVAL;
5461
5462         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5463                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5464         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5465                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5466                  * for lvds. */
5467                 pipe_config->pipe_bpp = 8*3;
5468         }
5469
5470         if (HAS_IPS(dev))
5471                 hsw_compute_ips_config(crtc, pipe_config);
5472
5473         /*
5474          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5475          * old clock survives for now.
5476          */
5477         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5478                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5479
5480         if (pipe_config->has_pch_encoder)
5481                 return ironlake_fdi_compute_config(crtc, pipe_config);
5482
5483         return 0;
5484 }
5485
5486 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5487 {
5488         struct drm_i915_private *dev_priv = dev->dev_private;
5489         int vco = valleyview_get_vco(dev_priv);
5490         u32 val;
5491         int divider;
5492
5493         /* FIXME: Punit isn't quite ready yet */
5494         if (IS_CHERRYVIEW(dev))
5495                 return 400000;
5496
5497         mutex_lock(&dev_priv->dpio_lock);
5498         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5499         mutex_unlock(&dev_priv->dpio_lock);
5500
5501         divider = val & DISPLAY_FREQUENCY_VALUES;
5502
5503         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5504              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5505              "cdclk change in progress\n");
5506
5507         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5508 }
5509
5510 static int i945_get_display_clock_speed(struct drm_device *dev)
5511 {
5512         return 400000;
5513 }
5514
5515 static int i915_get_display_clock_speed(struct drm_device *dev)
5516 {
5517         return 333000;
5518 }
5519
5520 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5521 {
5522         return 200000;
5523 }
5524
5525 static int pnv_get_display_clock_speed(struct drm_device *dev)
5526 {
5527         u16 gcfgc = 0;
5528
5529         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5530
5531         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5532         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5533                 return 267000;
5534         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5535                 return 333000;
5536         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5537                 return 444000;
5538         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5539                 return 200000;
5540         default:
5541                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5542         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5543                 return 133000;
5544         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5545                 return 167000;
5546         }
5547 }
5548
5549 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5550 {
5551         u16 gcfgc = 0;
5552
5553         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5554
5555         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5556                 return 133000;
5557         else {
5558                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5559                 case GC_DISPLAY_CLOCK_333_MHZ:
5560                         return 333000;
5561                 default:
5562                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5563                         return 190000;
5564                 }
5565         }
5566 }
5567
5568 static int i865_get_display_clock_speed(struct drm_device *dev)
5569 {
5570         return 266000;
5571 }
5572
5573 static int i855_get_display_clock_speed(struct drm_device *dev)
5574 {
5575         u16 hpllcc = 0;
5576         /* Assume that the hardware is in the high speed state.  This
5577          * should be the default.
5578          */
5579         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5580         case GC_CLOCK_133_200:
5581         case GC_CLOCK_100_200:
5582                 return 200000;
5583         case GC_CLOCK_166_250:
5584                 return 250000;
5585         case GC_CLOCK_100_133:
5586                 return 133000;
5587         }
5588
5589         /* Shouldn't happen */
5590         return 0;
5591 }
5592
5593 static int i830_get_display_clock_speed(struct drm_device *dev)
5594 {
5595         return 133000;
5596 }
5597
5598 static void
5599 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5600 {
5601         while (*num > DATA_LINK_M_N_MASK ||
5602                *den > DATA_LINK_M_N_MASK) {
5603                 *num >>= 1;
5604                 *den >>= 1;
5605         }
5606 }
5607
5608 static void compute_m_n(unsigned int m, unsigned int n,
5609                         uint32_t *ret_m, uint32_t *ret_n)
5610 {
5611         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5612         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5613         intel_reduce_m_n_ratio(ret_m, ret_n);
5614 }
5615
5616 void
5617 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5618                        int pixel_clock, int link_clock,
5619                        struct intel_link_m_n *m_n)
5620 {
5621         m_n->tu = 64;
5622
5623         compute_m_n(bits_per_pixel * pixel_clock,
5624                     link_clock * nlanes * 8,
5625                     &m_n->gmch_m, &m_n->gmch_n);
5626
5627         compute_m_n(pixel_clock, link_clock,
5628                     &m_n->link_m, &m_n->link_n);
5629 }
5630
5631 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5632 {
5633         if (i915.panel_use_ssc >= 0)
5634                 return i915.panel_use_ssc != 0;
5635         return dev_priv->vbt.lvds_use_ssc
5636                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5637 }
5638
5639 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5640 {
5641         struct drm_device *dev = crtc->base.dev;
5642         struct drm_i915_private *dev_priv = dev->dev_private;
5643         int refclk;
5644
5645         if (IS_VALLEYVIEW(dev)) {
5646                 refclk = 100000;
5647         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5648             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5649                 refclk = dev_priv->vbt.lvds_ssc_freq;
5650                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5651         } else if (!IS_GEN2(dev)) {
5652                 refclk = 96000;
5653         } else {
5654                 refclk = 48000;
5655         }
5656
5657         return refclk;
5658 }
5659
5660 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5661 {
5662         return (1 << dpll->n) << 16 | dpll->m2;
5663 }
5664
5665 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5666 {
5667         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5668 }
5669
5670 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5671                                      intel_clock_t *reduced_clock)
5672 {
5673         struct drm_device *dev = crtc->base.dev;
5674         u32 fp, fp2 = 0;
5675
5676         if (IS_PINEVIEW(dev)) {
5677                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5678                 if (reduced_clock)
5679                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5680         } else {
5681                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5682                 if (reduced_clock)
5683                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5684         }
5685
5686         crtc->config.dpll_hw_state.fp0 = fp;
5687
5688         crtc->lowfreq_avail = false;
5689         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5690             reduced_clock && i915.powersave) {
5691                 crtc->config.dpll_hw_state.fp1 = fp2;
5692                 crtc->lowfreq_avail = true;
5693         } else {
5694                 crtc->config.dpll_hw_state.fp1 = fp;
5695         }
5696 }
5697
5698 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5699                 pipe)
5700 {
5701         u32 reg_val;
5702
5703         /*
5704          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5705          * and set it to a reasonable value instead.
5706          */
5707         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5708         reg_val &= 0xffffff00;
5709         reg_val |= 0x00000030;
5710         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5711
5712         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5713         reg_val &= 0x8cffffff;
5714         reg_val = 0x8c000000;
5715         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5716
5717         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5718         reg_val &= 0xffffff00;
5719         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5720
5721         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5722         reg_val &= 0x00ffffff;
5723         reg_val |= 0xb0000000;
5724         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5725 }
5726
5727 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5728                                          struct intel_link_m_n *m_n)
5729 {
5730         struct drm_device *dev = crtc->base.dev;
5731         struct drm_i915_private *dev_priv = dev->dev_private;
5732         int pipe = crtc->pipe;
5733
5734         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5736         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5737         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5738 }
5739
5740 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5741                                          struct intel_link_m_n *m_n,
5742                                          struct intel_link_m_n *m2_n2)
5743 {
5744         struct drm_device *dev = crtc->base.dev;
5745         struct drm_i915_private *dev_priv = dev->dev_private;
5746         int pipe = crtc->pipe;
5747         enum transcoder transcoder = crtc->config.cpu_transcoder;
5748
5749         if (INTEL_INFO(dev)->gen >= 5) {
5750                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5751                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5752                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5753                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5754                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5755                  * for gen < 8) and if DRRS is supported (to make sure the
5756                  * registers are not unnecessarily accessed).
5757                  */
5758                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5759                         crtc->config.has_drrs) {
5760                         I915_WRITE(PIPE_DATA_M2(transcoder),
5761                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5762                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5763                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5764                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5765                 }
5766         } else {
5767                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5768                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5769                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5770                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5771         }
5772 }
5773
5774 void intel_dp_set_m_n(struct intel_crtc *crtc)
5775 {
5776         if (crtc->config.has_pch_encoder)
5777                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5778         else
5779                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5780                                                    &crtc->config.dp_m2_n2);
5781 }
5782
5783 static void vlv_update_pll(struct intel_crtc *crtc,
5784                            struct intel_crtc_config *pipe_config)
5785 {
5786         u32 dpll, dpll_md;
5787
5788         /*
5789          * Enable DPIO clock input. We should never disable the reference
5790          * clock for pipe B, since VGA hotplug / manual detection depends
5791          * on it.
5792          */
5793         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5794                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5795         /* We should never disable this, set it here for state tracking */
5796         if (crtc->pipe == PIPE_B)
5797                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5798         dpll |= DPLL_VCO_ENABLE;
5799         pipe_config->dpll_hw_state.dpll = dpll;
5800
5801         dpll_md = (pipe_config->pixel_multiplier - 1)
5802                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5803         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5804 }
5805
5806 static void vlv_prepare_pll(struct intel_crtc *crtc,
5807                             const struct intel_crtc_config *pipe_config)
5808 {
5809         struct drm_device *dev = crtc->base.dev;
5810         struct drm_i915_private *dev_priv = dev->dev_private;
5811         int pipe = crtc->pipe;
5812         u32 mdiv;
5813         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5814         u32 coreclk, reg_val;
5815
5816         mutex_lock(&dev_priv->dpio_lock);
5817
5818         bestn = pipe_config->dpll.n;
5819         bestm1 = pipe_config->dpll.m1;
5820         bestm2 = pipe_config->dpll.m2;
5821         bestp1 = pipe_config->dpll.p1;
5822         bestp2 = pipe_config->dpll.p2;
5823
5824         /* See eDP HDMI DPIO driver vbios notes doc */
5825
5826         /* PLL B needs special handling */
5827         if (pipe == PIPE_B)
5828                 vlv_pllb_recal_opamp(dev_priv, pipe);
5829
5830         /* Set up Tx target for periodic Rcomp update */
5831         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5832
5833         /* Disable target IRef on PLL */
5834         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5835         reg_val &= 0x00ffffff;
5836         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5837
5838         /* Disable fast lock */
5839         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5840
5841         /* Set idtafcrecal before PLL is enabled */
5842         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5843         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5844         mdiv |= ((bestn << DPIO_N_SHIFT));
5845         mdiv |= (1 << DPIO_K_SHIFT);
5846
5847         /*
5848          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5849          * but we don't support that).
5850          * Note: don't use the DAC post divider as it seems unstable.
5851          */
5852         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5853         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5854
5855         mdiv |= DPIO_ENABLE_CALIBRATION;
5856         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5857
5858         /* Set HBR and RBR LPF coefficients */
5859         if (pipe_config->port_clock == 162000 ||
5860             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5861             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5862                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5863                                  0x009f0003);
5864         else
5865                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5866                                  0x00d0000f);
5867
5868         if (crtc->config.has_dp_encoder) {
5869                 /* Use SSC source */
5870                 if (pipe == PIPE_A)
5871                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5872                                          0x0df40000);
5873                 else
5874                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5875                                          0x0df70000);
5876         } else { /* HDMI or VGA */
5877                 /* Use bend source */
5878                 if (pipe == PIPE_A)
5879                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5880                                          0x0df70000);
5881                 else
5882                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5883                                          0x0df40000);
5884         }
5885
5886         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5887         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5888         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5889             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5890                 coreclk |= 0x01000000;
5891         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5892
5893         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5894         mutex_unlock(&dev_priv->dpio_lock);
5895 }
5896
5897 static void chv_update_pll(struct intel_crtc *crtc,
5898                            struct intel_crtc_config *pipe_config)
5899 {
5900         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5901                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5902                 DPLL_VCO_ENABLE;
5903         if (crtc->pipe != PIPE_A)
5904                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5905
5906         pipe_config->dpll_hw_state.dpll_md =
5907                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5908 }
5909
5910 static void chv_prepare_pll(struct intel_crtc *crtc,
5911                             const struct intel_crtc_config *pipe_config)
5912 {
5913         struct drm_device *dev = crtc->base.dev;
5914         struct drm_i915_private *dev_priv = dev->dev_private;
5915         int pipe = crtc->pipe;
5916         int dpll_reg = DPLL(crtc->pipe);
5917         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5918         u32 loopfilter, intcoeff;
5919         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5920         int refclk;
5921
5922         bestn = pipe_config->dpll.n;
5923         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5924         bestm1 = pipe_config->dpll.m1;
5925         bestm2 = pipe_config->dpll.m2 >> 22;
5926         bestp1 = pipe_config->dpll.p1;
5927         bestp2 = pipe_config->dpll.p2;
5928
5929         /*
5930          * Enable Refclk and SSC
5931          */
5932         I915_WRITE(dpll_reg,
5933                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5934
5935         mutex_lock(&dev_priv->dpio_lock);
5936
5937         /* p1 and p2 divider */
5938         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5939                         5 << DPIO_CHV_S1_DIV_SHIFT |
5940                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5941                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5942                         1 << DPIO_CHV_K_DIV_SHIFT);
5943
5944         /* Feedback post-divider - m2 */
5945         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5946
5947         /* Feedback refclk divider - n and m1 */
5948         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5949                         DPIO_CHV_M1_DIV_BY_2 |
5950                         1 << DPIO_CHV_N_DIV_SHIFT);
5951
5952         /* M2 fraction division */
5953         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5954
5955         /* M2 fraction division enable */
5956         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5957                        DPIO_CHV_FRAC_DIV_EN |
5958                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5959
5960         /* Loop filter */
5961         refclk = i9xx_get_refclk(crtc, 0);
5962         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5963                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5964         if (refclk == 100000)
5965                 intcoeff = 11;
5966         else if (refclk == 38400)
5967                 intcoeff = 10;
5968         else
5969                 intcoeff = 9;
5970         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5971         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5972
5973         /* AFC Recal */
5974         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5975                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5976                         DPIO_AFC_RECAL);
5977
5978         mutex_unlock(&dev_priv->dpio_lock);
5979 }
5980
5981 /**
5982  * vlv_force_pll_on - forcibly enable just the PLL
5983  * @dev_priv: i915 private structure
5984  * @pipe: pipe PLL to enable
5985  * @dpll: PLL configuration
5986  *
5987  * Enable the PLL for @pipe using the supplied @dpll config. To be used
5988  * in cases where we need the PLL enabled even when @pipe is not going to
5989  * be enabled.
5990  */
5991 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
5992                       const struct dpll *dpll)
5993 {
5994         struct intel_crtc *crtc =
5995                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5996         struct intel_crtc_config pipe_config = {
5997                 .pixel_multiplier = 1,
5998                 .dpll = *dpll,
5999         };
6000
6001         if (IS_CHERRYVIEW(dev)) {
6002                 chv_update_pll(crtc, &pipe_config);
6003                 chv_prepare_pll(crtc, &pipe_config);
6004                 chv_enable_pll(crtc, &pipe_config);
6005         } else {
6006                 vlv_update_pll(crtc, &pipe_config);
6007                 vlv_prepare_pll(crtc, &pipe_config);
6008                 vlv_enable_pll(crtc, &pipe_config);
6009         }
6010 }
6011
6012 /**
6013  * vlv_force_pll_off - forcibly disable just the PLL
6014  * @dev_priv: i915 private structure
6015  * @pipe: pipe PLL to disable
6016  *
6017  * Disable the PLL for @pipe. To be used in cases where we need
6018  * the PLL enabled even when @pipe is not going to be enabled.
6019  */
6020 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6021 {
6022         if (IS_CHERRYVIEW(dev))
6023                 chv_disable_pll(to_i915(dev), pipe);
6024         else
6025                 vlv_disable_pll(to_i915(dev), pipe);
6026 }
6027
6028 static void i9xx_update_pll(struct intel_crtc *crtc,
6029                             intel_clock_t *reduced_clock,
6030                             int num_connectors)
6031 {
6032         struct drm_device *dev = crtc->base.dev;
6033         struct drm_i915_private *dev_priv = dev->dev_private;
6034         u32 dpll;
6035         bool is_sdvo;
6036         struct dpll *clock = &crtc->new_config->dpll;
6037
6038         i9xx_update_pll_dividers(crtc, reduced_clock);
6039
6040         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6041                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6042
6043         dpll = DPLL_VGA_MODE_DIS;
6044
6045         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6046                 dpll |= DPLLB_MODE_LVDS;
6047         else
6048                 dpll |= DPLLB_MODE_DAC_SERIAL;
6049
6050         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6051                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6052                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6053         }
6054
6055         if (is_sdvo)
6056                 dpll |= DPLL_SDVO_HIGH_SPEED;
6057
6058         if (crtc->new_config->has_dp_encoder)
6059                 dpll |= DPLL_SDVO_HIGH_SPEED;
6060
6061         /* compute bitmask from p1 value */
6062         if (IS_PINEVIEW(dev))
6063                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6064         else {
6065                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6066                 if (IS_G4X(dev) && reduced_clock)
6067                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6068         }
6069         switch (clock->p2) {
6070         case 5:
6071                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6072                 break;
6073         case 7:
6074                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6075                 break;
6076         case 10:
6077                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6078                 break;
6079         case 14:
6080                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6081                 break;
6082         }
6083         if (INTEL_INFO(dev)->gen >= 4)
6084                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6085
6086         if (crtc->new_config->sdvo_tv_clock)
6087                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6088         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6089                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6090                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6091         else
6092                 dpll |= PLL_REF_INPUT_DREFCLK;
6093
6094         dpll |= DPLL_VCO_ENABLE;
6095         crtc->new_config->dpll_hw_state.dpll = dpll;
6096
6097         if (INTEL_INFO(dev)->gen >= 4) {
6098                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6099                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6100                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6101         }
6102 }
6103
6104 static void i8xx_update_pll(struct intel_crtc *crtc,
6105                             intel_clock_t *reduced_clock,
6106                             int num_connectors)
6107 {
6108         struct drm_device *dev = crtc->base.dev;
6109         struct drm_i915_private *dev_priv = dev->dev_private;
6110         u32 dpll;
6111         struct dpll *clock = &crtc->new_config->dpll;
6112
6113         i9xx_update_pll_dividers(crtc, reduced_clock);
6114
6115         dpll = DPLL_VGA_MODE_DIS;
6116
6117         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6118                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6119         } else {
6120                 if (clock->p1 == 2)
6121                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6122                 else
6123                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6124                 if (clock->p2 == 4)
6125                         dpll |= PLL_P2_DIVIDE_BY_4;
6126         }
6127
6128         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6129                 dpll |= DPLL_DVO_2X_MODE;
6130
6131         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6132                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6133                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6134         else
6135                 dpll |= PLL_REF_INPUT_DREFCLK;
6136
6137         dpll |= DPLL_VCO_ENABLE;
6138         crtc->new_config->dpll_hw_state.dpll = dpll;
6139 }
6140
6141 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6142 {
6143         struct drm_device *dev = intel_crtc->base.dev;
6144         struct drm_i915_private *dev_priv = dev->dev_private;
6145         enum pipe pipe = intel_crtc->pipe;
6146         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6147         struct drm_display_mode *adjusted_mode =
6148                 &intel_crtc->config.adjusted_mode;
6149         uint32_t crtc_vtotal, crtc_vblank_end;
6150         int vsyncshift = 0;
6151
6152         /* We need to be careful not to changed the adjusted mode, for otherwise
6153          * the hw state checker will get angry at the mismatch. */
6154         crtc_vtotal = adjusted_mode->crtc_vtotal;
6155         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6156
6157         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6158                 /* the chip adds 2 halflines automatically */
6159                 crtc_vtotal -= 1;
6160                 crtc_vblank_end -= 1;
6161
6162                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6163                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6164                 else
6165                         vsyncshift = adjusted_mode->crtc_hsync_start -
6166                                 adjusted_mode->crtc_htotal / 2;
6167                 if (vsyncshift < 0)
6168                         vsyncshift += adjusted_mode->crtc_htotal;
6169         }
6170
6171         if (INTEL_INFO(dev)->gen > 3)
6172                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6173
6174         I915_WRITE(HTOTAL(cpu_transcoder),
6175                    (adjusted_mode->crtc_hdisplay - 1) |
6176                    ((adjusted_mode->crtc_htotal - 1) << 16));
6177         I915_WRITE(HBLANK(cpu_transcoder),
6178                    (adjusted_mode->crtc_hblank_start - 1) |
6179                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6180         I915_WRITE(HSYNC(cpu_transcoder),
6181                    (adjusted_mode->crtc_hsync_start - 1) |
6182                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6183
6184         I915_WRITE(VTOTAL(cpu_transcoder),
6185                    (adjusted_mode->crtc_vdisplay - 1) |
6186                    ((crtc_vtotal - 1) << 16));
6187         I915_WRITE(VBLANK(cpu_transcoder),
6188                    (adjusted_mode->crtc_vblank_start - 1) |
6189                    ((crtc_vblank_end - 1) << 16));
6190         I915_WRITE(VSYNC(cpu_transcoder),
6191                    (adjusted_mode->crtc_vsync_start - 1) |
6192                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6193
6194         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6195          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6196          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6197          * bits. */
6198         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6199             (pipe == PIPE_B || pipe == PIPE_C))
6200                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6201
6202         /* pipesrc controls the size that is scaled from, which should
6203          * always be the user's requested size.
6204          */
6205         I915_WRITE(PIPESRC(pipe),
6206                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6207                    (intel_crtc->config.pipe_src_h - 1));
6208 }
6209
6210 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6211                                    struct intel_crtc_config *pipe_config)
6212 {
6213         struct drm_device *dev = crtc->base.dev;
6214         struct drm_i915_private *dev_priv = dev->dev_private;
6215         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6216         uint32_t tmp;
6217
6218         tmp = I915_READ(HTOTAL(cpu_transcoder));
6219         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6220         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6221         tmp = I915_READ(HBLANK(cpu_transcoder));
6222         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6223         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6224         tmp = I915_READ(HSYNC(cpu_transcoder));
6225         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6226         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6227
6228         tmp = I915_READ(VTOTAL(cpu_transcoder));
6229         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6230         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6231         tmp = I915_READ(VBLANK(cpu_transcoder));
6232         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6233         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6234         tmp = I915_READ(VSYNC(cpu_transcoder));
6235         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6236         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6237
6238         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6239                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6240                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6241                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6242         }
6243
6244         tmp = I915_READ(PIPESRC(crtc->pipe));
6245         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6246         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6247
6248         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6249         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6250 }
6251
6252 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6253                                  struct intel_crtc_config *pipe_config)
6254 {
6255         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6256         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6257         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6258         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6259
6260         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6261         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6262         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6263         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6264
6265         mode->flags = pipe_config->adjusted_mode.flags;
6266
6267         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6268         mode->flags |= pipe_config->adjusted_mode.flags;
6269 }
6270
6271 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6272 {
6273         struct drm_device *dev = intel_crtc->base.dev;
6274         struct drm_i915_private *dev_priv = dev->dev_private;
6275         uint32_t pipeconf;
6276
6277         pipeconf = 0;
6278
6279         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6280             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6281                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6282
6283         if (intel_crtc->config.double_wide)
6284                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6285
6286         /* only g4x and later have fancy bpc/dither controls */
6287         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6288                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6289                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6290                         pipeconf |= PIPECONF_DITHER_EN |
6291                                     PIPECONF_DITHER_TYPE_SP;
6292
6293                 switch (intel_crtc->config.pipe_bpp) {
6294                 case 18:
6295                         pipeconf |= PIPECONF_6BPC;
6296                         break;
6297                 case 24:
6298                         pipeconf |= PIPECONF_8BPC;
6299                         break;
6300                 case 30:
6301                         pipeconf |= PIPECONF_10BPC;
6302                         break;
6303                 default:
6304                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6305                         BUG();
6306                 }
6307         }
6308
6309         if (HAS_PIPE_CXSR(dev)) {
6310                 if (intel_crtc->lowfreq_avail) {
6311                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6312                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6313                 } else {
6314                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6315                 }
6316         }
6317
6318         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6319                 if (INTEL_INFO(dev)->gen < 4 ||
6320                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6321                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6322                 else
6323                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6324         } else
6325                 pipeconf |= PIPECONF_PROGRESSIVE;
6326
6327         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6328                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6329
6330         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6331         POSTING_READ(PIPECONF(intel_crtc->pipe));
6332 }
6333
6334 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6335                               int x, int y,
6336                               struct drm_framebuffer *fb)
6337 {
6338         struct drm_device *dev = crtc->base.dev;
6339         struct drm_i915_private *dev_priv = dev->dev_private;
6340         int refclk, num_connectors = 0;
6341         intel_clock_t clock, reduced_clock;
6342         bool ok, has_reduced_clock = false;
6343         bool is_lvds = false, is_dsi = false;
6344         struct intel_encoder *encoder;
6345         const intel_limit_t *limit;
6346
6347         for_each_intel_encoder(dev, encoder) {
6348                 if (encoder->new_crtc != crtc)
6349                         continue;
6350
6351                 switch (encoder->type) {
6352                 case INTEL_OUTPUT_LVDS:
6353                         is_lvds = true;
6354                         break;
6355                 case INTEL_OUTPUT_DSI:
6356                         is_dsi = true;
6357                         break;
6358                 default:
6359                         break;
6360                 }
6361
6362                 num_connectors++;
6363         }
6364
6365         if (is_dsi)
6366                 return 0;
6367
6368         if (!crtc->new_config->clock_set) {
6369                 refclk = i9xx_get_refclk(crtc, num_connectors);
6370
6371                 /*
6372                  * Returns a set of divisors for the desired target clock with
6373                  * the given refclk, or FALSE.  The returned values represent
6374                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6375                  * 2) / p1 / p2.
6376                  */
6377                 limit = intel_limit(crtc, refclk);
6378                 ok = dev_priv->display.find_dpll(limit, crtc,
6379                                                  crtc->new_config->port_clock,
6380                                                  refclk, NULL, &clock);
6381                 if (!ok) {
6382                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6383                         return -EINVAL;
6384                 }
6385
6386                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6387                         /*
6388                          * Ensure we match the reduced clock's P to the target
6389                          * clock.  If the clocks don't match, we can't switch
6390                          * the display clock by using the FP0/FP1. In such case
6391                          * we will disable the LVDS downclock feature.
6392                          */
6393                         has_reduced_clock =
6394                                 dev_priv->display.find_dpll(limit, crtc,
6395                                                             dev_priv->lvds_downclock,
6396                                                             refclk, &clock,
6397                                                             &reduced_clock);
6398                 }
6399                 /* Compat-code for transition, will disappear. */
6400                 crtc->new_config->dpll.n = clock.n;
6401                 crtc->new_config->dpll.m1 = clock.m1;
6402                 crtc->new_config->dpll.m2 = clock.m2;
6403                 crtc->new_config->dpll.p1 = clock.p1;
6404                 crtc->new_config->dpll.p2 = clock.p2;
6405         }
6406
6407         if (IS_GEN2(dev)) {
6408                 i8xx_update_pll(crtc,
6409                                 has_reduced_clock ? &reduced_clock : NULL,
6410                                 num_connectors);
6411         } else if (IS_CHERRYVIEW(dev)) {
6412                 chv_update_pll(crtc, crtc->new_config);
6413         } else if (IS_VALLEYVIEW(dev)) {
6414                 vlv_update_pll(crtc, crtc->new_config);
6415         } else {
6416                 i9xx_update_pll(crtc,
6417                                 has_reduced_clock ? &reduced_clock : NULL,
6418                                 num_connectors);
6419         }
6420
6421         return 0;
6422 }
6423
6424 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6425                                  struct intel_crtc_config *pipe_config)
6426 {
6427         struct drm_device *dev = crtc->base.dev;
6428         struct drm_i915_private *dev_priv = dev->dev_private;
6429         uint32_t tmp;
6430
6431         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6432                 return;
6433
6434         tmp = I915_READ(PFIT_CONTROL);
6435         if (!(tmp & PFIT_ENABLE))
6436                 return;
6437
6438         /* Check whether the pfit is attached to our pipe. */
6439         if (INTEL_INFO(dev)->gen < 4) {
6440                 if (crtc->pipe != PIPE_B)
6441                         return;
6442         } else {
6443                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6444                         return;
6445         }
6446
6447         pipe_config->gmch_pfit.control = tmp;
6448         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6449         if (INTEL_INFO(dev)->gen < 5)
6450                 pipe_config->gmch_pfit.lvds_border_bits =
6451                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6452 }
6453
6454 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6455                                struct intel_crtc_config *pipe_config)
6456 {
6457         struct drm_device *dev = crtc->base.dev;
6458         struct drm_i915_private *dev_priv = dev->dev_private;
6459         int pipe = pipe_config->cpu_transcoder;
6460         intel_clock_t clock;
6461         u32 mdiv;
6462         int refclk = 100000;
6463
6464         /* In case of MIPI DPLL will not even be used */
6465         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6466                 return;
6467
6468         mutex_lock(&dev_priv->dpio_lock);
6469         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6470         mutex_unlock(&dev_priv->dpio_lock);
6471
6472         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6473         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6474         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6475         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6476         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6477
6478         vlv_clock(refclk, &clock);
6479
6480         /* clock.dot is the fast clock */
6481         pipe_config->port_clock = clock.dot / 5;
6482 }
6483
6484 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6485                                   struct intel_plane_config *plane_config)
6486 {
6487         struct drm_device *dev = crtc->base.dev;
6488         struct drm_i915_private *dev_priv = dev->dev_private;
6489         u32 val, base, offset;
6490         int pipe = crtc->pipe, plane = crtc->plane;
6491         int fourcc, pixel_format;
6492         int aligned_height;
6493
6494         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6495         if (!crtc->base.primary->fb) {
6496                 DRM_DEBUG_KMS("failed to alloc fb\n");
6497                 return;
6498         }
6499
6500         val = I915_READ(DSPCNTR(plane));
6501
6502         if (INTEL_INFO(dev)->gen >= 4)
6503                 if (val & DISPPLANE_TILED)
6504                         plane_config->tiled = true;
6505
6506         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6507         fourcc = intel_format_to_fourcc(pixel_format);
6508         crtc->base.primary->fb->pixel_format = fourcc;
6509         crtc->base.primary->fb->bits_per_pixel =
6510                 drm_format_plane_cpp(fourcc, 0) * 8;
6511
6512         if (INTEL_INFO(dev)->gen >= 4) {
6513                 if (plane_config->tiled)
6514                         offset = I915_READ(DSPTILEOFF(plane));
6515                 else
6516                         offset = I915_READ(DSPLINOFF(plane));
6517                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6518         } else {
6519                 base = I915_READ(DSPADDR(plane));
6520         }
6521         plane_config->base = base;
6522
6523         val = I915_READ(PIPESRC(pipe));
6524         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6525         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6526
6527         val = I915_READ(DSPSTRIDE(pipe));
6528         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6529
6530         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6531                                             plane_config->tiled);
6532
6533         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6534                                         aligned_height);
6535
6536         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6537                       pipe, plane, crtc->base.primary->fb->width,
6538                       crtc->base.primary->fb->height,
6539                       crtc->base.primary->fb->bits_per_pixel, base,
6540                       crtc->base.primary->fb->pitches[0],
6541                       plane_config->size);
6542
6543 }
6544
6545 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6546                                struct intel_crtc_config *pipe_config)
6547 {
6548         struct drm_device *dev = crtc->base.dev;
6549         struct drm_i915_private *dev_priv = dev->dev_private;
6550         int pipe = pipe_config->cpu_transcoder;
6551         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6552         intel_clock_t clock;
6553         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6554         int refclk = 100000;
6555
6556         mutex_lock(&dev_priv->dpio_lock);
6557         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6558         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6559         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6560         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6561         mutex_unlock(&dev_priv->dpio_lock);
6562
6563         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6564         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6565         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6566         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6567         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6568
6569         chv_clock(refclk, &clock);
6570
6571         /* clock.dot is the fast clock */
6572         pipe_config->port_clock = clock.dot / 5;
6573 }
6574
6575 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6576                                  struct intel_crtc_config *pipe_config)
6577 {
6578         struct drm_device *dev = crtc->base.dev;
6579         struct drm_i915_private *dev_priv = dev->dev_private;
6580         uint32_t tmp;
6581
6582         if (!intel_display_power_is_enabled(dev_priv,
6583                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6584                 return false;
6585
6586         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6587         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6588
6589         tmp = I915_READ(PIPECONF(crtc->pipe));
6590         if (!(tmp & PIPECONF_ENABLE))
6591                 return false;
6592
6593         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6594                 switch (tmp & PIPECONF_BPC_MASK) {
6595                 case PIPECONF_6BPC:
6596                         pipe_config->pipe_bpp = 18;
6597                         break;
6598                 case PIPECONF_8BPC:
6599                         pipe_config->pipe_bpp = 24;
6600                         break;
6601                 case PIPECONF_10BPC:
6602                         pipe_config->pipe_bpp = 30;
6603                         break;
6604                 default:
6605                         break;
6606                 }
6607         }
6608
6609         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6610                 pipe_config->limited_color_range = true;
6611
6612         if (INTEL_INFO(dev)->gen < 4)
6613                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6614
6615         intel_get_pipe_timings(crtc, pipe_config);
6616
6617         i9xx_get_pfit_config(crtc, pipe_config);
6618
6619         if (INTEL_INFO(dev)->gen >= 4) {
6620                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6621                 pipe_config->pixel_multiplier =
6622                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6623                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6624                 pipe_config->dpll_hw_state.dpll_md = tmp;
6625         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6626                 tmp = I915_READ(DPLL(crtc->pipe));
6627                 pipe_config->pixel_multiplier =
6628                         ((tmp & SDVO_MULTIPLIER_MASK)
6629                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6630         } else {
6631                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6632                  * port and will be fixed up in the encoder->get_config
6633                  * function. */
6634                 pipe_config->pixel_multiplier = 1;
6635         }
6636         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6637         if (!IS_VALLEYVIEW(dev)) {
6638                 /*
6639                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6640                  * on 830. Filter it out here so that we don't
6641                  * report errors due to that.
6642                  */
6643                 if (IS_I830(dev))
6644                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6645
6646                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6647                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6648         } else {
6649                 /* Mask out read-only status bits. */
6650                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6651                                                      DPLL_PORTC_READY_MASK |
6652                                                      DPLL_PORTB_READY_MASK);
6653         }
6654
6655         if (IS_CHERRYVIEW(dev))
6656                 chv_crtc_clock_get(crtc, pipe_config);
6657         else if (IS_VALLEYVIEW(dev))
6658                 vlv_crtc_clock_get(crtc, pipe_config);
6659         else
6660                 i9xx_crtc_clock_get(crtc, pipe_config);
6661
6662         return true;
6663 }
6664
6665 static void ironlake_init_pch_refclk(struct drm_device *dev)
6666 {
6667         struct drm_i915_private *dev_priv = dev->dev_private;
6668         struct intel_encoder *encoder;
6669         u32 val, final;
6670         bool has_lvds = false;
6671         bool has_cpu_edp = false;
6672         bool has_panel = false;
6673         bool has_ck505 = false;
6674         bool can_ssc = false;
6675
6676         /* We need to take the global config into account */
6677         for_each_intel_encoder(dev, encoder) {
6678                 switch (encoder->type) {
6679                 case INTEL_OUTPUT_LVDS:
6680                         has_panel = true;
6681                         has_lvds = true;
6682                         break;
6683                 case INTEL_OUTPUT_EDP:
6684                         has_panel = true;
6685                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6686                                 has_cpu_edp = true;
6687                         break;
6688                 default:
6689                         break;
6690                 }
6691         }
6692
6693         if (HAS_PCH_IBX(dev)) {
6694                 has_ck505 = dev_priv->vbt.display_clock_mode;
6695                 can_ssc = has_ck505;
6696         } else {
6697                 has_ck505 = false;
6698                 can_ssc = true;
6699         }
6700
6701         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6702                       has_panel, has_lvds, has_ck505);
6703
6704         /* Ironlake: try to setup display ref clock before DPLL
6705          * enabling. This is only under driver's control after
6706          * PCH B stepping, previous chipset stepping should be
6707          * ignoring this setting.
6708          */
6709         val = I915_READ(PCH_DREF_CONTROL);
6710
6711         /* As we must carefully and slowly disable/enable each source in turn,
6712          * compute the final state we want first and check if we need to
6713          * make any changes at all.
6714          */
6715         final = val;
6716         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6717         if (has_ck505)
6718                 final |= DREF_NONSPREAD_CK505_ENABLE;
6719         else
6720                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6721
6722         final &= ~DREF_SSC_SOURCE_MASK;
6723         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6724         final &= ~DREF_SSC1_ENABLE;
6725
6726         if (has_panel) {
6727                 final |= DREF_SSC_SOURCE_ENABLE;
6728
6729                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6730                         final |= DREF_SSC1_ENABLE;
6731
6732                 if (has_cpu_edp) {
6733                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6734                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6735                         else
6736                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6737                 } else
6738                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6739         } else {
6740                 final |= DREF_SSC_SOURCE_DISABLE;
6741                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6742         }
6743
6744         if (final == val)
6745                 return;
6746
6747         /* Always enable nonspread source */
6748         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6749
6750         if (has_ck505)
6751                 val |= DREF_NONSPREAD_CK505_ENABLE;
6752         else
6753                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6754
6755         if (has_panel) {
6756                 val &= ~DREF_SSC_SOURCE_MASK;
6757                 val |= DREF_SSC_SOURCE_ENABLE;
6758
6759                 /* SSC must be turned on before enabling the CPU output  */
6760                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6761                         DRM_DEBUG_KMS("Using SSC on panel\n");
6762                         val |= DREF_SSC1_ENABLE;
6763                 } else
6764                         val &= ~DREF_SSC1_ENABLE;
6765
6766                 /* Get SSC going before enabling the outputs */
6767                 I915_WRITE(PCH_DREF_CONTROL, val);
6768                 POSTING_READ(PCH_DREF_CONTROL);
6769                 udelay(200);
6770
6771                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6772
6773                 /* Enable CPU source on CPU attached eDP */
6774                 if (has_cpu_edp) {
6775                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6776                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6777                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6778                         } else
6779                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6780                 } else
6781                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6782
6783                 I915_WRITE(PCH_DREF_CONTROL, val);
6784                 POSTING_READ(PCH_DREF_CONTROL);
6785                 udelay(200);
6786         } else {
6787                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6788
6789                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6790
6791                 /* Turn off CPU output */
6792                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6793
6794                 I915_WRITE(PCH_DREF_CONTROL, val);
6795                 POSTING_READ(PCH_DREF_CONTROL);
6796                 udelay(200);
6797
6798                 /* Turn off the SSC source */
6799                 val &= ~DREF_SSC_SOURCE_MASK;
6800                 val |= DREF_SSC_SOURCE_DISABLE;
6801
6802                 /* Turn off SSC1 */
6803                 val &= ~DREF_SSC1_ENABLE;
6804
6805                 I915_WRITE(PCH_DREF_CONTROL, val);
6806                 POSTING_READ(PCH_DREF_CONTROL);
6807                 udelay(200);
6808         }
6809
6810         BUG_ON(val != final);
6811 }
6812
6813 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6814 {
6815         uint32_t tmp;
6816
6817         tmp = I915_READ(SOUTH_CHICKEN2);
6818         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6819         I915_WRITE(SOUTH_CHICKEN2, tmp);
6820
6821         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6822                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6823                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6824
6825         tmp = I915_READ(SOUTH_CHICKEN2);
6826         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6827         I915_WRITE(SOUTH_CHICKEN2, tmp);
6828
6829         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6830                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6831                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6832 }
6833
6834 /* WaMPhyProgramming:hsw */
6835 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6836 {
6837         uint32_t tmp;
6838
6839         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6840         tmp &= ~(0xFF << 24);
6841         tmp |= (0x12 << 24);
6842         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6843
6844         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6845         tmp |= (1 << 11);
6846         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6847
6848         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6849         tmp |= (1 << 11);
6850         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6851
6852         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6853         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6854         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6855
6856         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6857         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6858         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6859
6860         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6861         tmp &= ~(7 << 13);
6862         tmp |= (5 << 13);
6863         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6864
6865         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6866         tmp &= ~(7 << 13);
6867         tmp |= (5 << 13);
6868         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6869
6870         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6871         tmp &= ~0xFF;
6872         tmp |= 0x1C;
6873         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6874
6875         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6876         tmp &= ~0xFF;
6877         tmp |= 0x1C;
6878         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6879
6880         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6881         tmp &= ~(0xFF << 16);
6882         tmp |= (0x1C << 16);
6883         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6884
6885         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6886         tmp &= ~(0xFF << 16);
6887         tmp |= (0x1C << 16);
6888         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6889
6890         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6891         tmp |= (1 << 27);
6892         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6893
6894         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6895         tmp |= (1 << 27);
6896         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6897
6898         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6899         tmp &= ~(0xF << 28);
6900         tmp |= (4 << 28);
6901         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6902
6903         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6904         tmp &= ~(0xF << 28);
6905         tmp |= (4 << 28);
6906         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6907 }
6908
6909 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6910  * Programming" based on the parameters passed:
6911  * - Sequence to enable CLKOUT_DP
6912  * - Sequence to enable CLKOUT_DP without spread
6913  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6914  */
6915 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6916                                  bool with_fdi)
6917 {
6918         struct drm_i915_private *dev_priv = dev->dev_private;
6919         uint32_t reg, tmp;
6920
6921         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6922                 with_spread = true;
6923         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6924                  with_fdi, "LP PCH doesn't have FDI\n"))
6925                 with_fdi = false;
6926
6927         mutex_lock(&dev_priv->dpio_lock);
6928
6929         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6930         tmp &= ~SBI_SSCCTL_DISABLE;
6931         tmp |= SBI_SSCCTL_PATHALT;
6932         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6933
6934         udelay(24);
6935
6936         if (with_spread) {
6937                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6938                 tmp &= ~SBI_SSCCTL_PATHALT;
6939                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6940
6941                 if (with_fdi) {
6942                         lpt_reset_fdi_mphy(dev_priv);
6943                         lpt_program_fdi_mphy(dev_priv);
6944                 }
6945         }
6946
6947         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6948                SBI_GEN0 : SBI_DBUFF0;
6949         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6950         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6951         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6952
6953         mutex_unlock(&dev_priv->dpio_lock);
6954 }
6955
6956 /* Sequence to disable CLKOUT_DP */
6957 static void lpt_disable_clkout_dp(struct drm_device *dev)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960         uint32_t reg, tmp;
6961
6962         mutex_lock(&dev_priv->dpio_lock);
6963
6964         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6965                SBI_GEN0 : SBI_DBUFF0;
6966         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6967         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6968         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6969
6970         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6971         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6972                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6973                         tmp |= SBI_SSCCTL_PATHALT;
6974                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6975                         udelay(32);
6976                 }
6977                 tmp |= SBI_SSCCTL_DISABLE;
6978                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6979         }
6980
6981         mutex_unlock(&dev_priv->dpio_lock);
6982 }
6983
6984 static void lpt_init_pch_refclk(struct drm_device *dev)
6985 {
6986         struct intel_encoder *encoder;
6987         bool has_vga = false;
6988
6989         for_each_intel_encoder(dev, encoder) {
6990                 switch (encoder->type) {
6991                 case INTEL_OUTPUT_ANALOG:
6992                         has_vga = true;
6993                         break;
6994                 default:
6995                         break;
6996                 }
6997         }
6998
6999         if (has_vga)
7000                 lpt_enable_clkout_dp(dev, true, true);
7001         else
7002                 lpt_disable_clkout_dp(dev);
7003 }
7004
7005 /*
7006  * Initialize reference clocks when the driver loads
7007  */
7008 void intel_init_pch_refclk(struct drm_device *dev)
7009 {
7010         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7011                 ironlake_init_pch_refclk(dev);
7012         else if (HAS_PCH_LPT(dev))
7013                 lpt_init_pch_refclk(dev);
7014 }
7015
7016 static int ironlake_get_refclk(struct drm_crtc *crtc)
7017 {
7018         struct drm_device *dev = crtc->dev;
7019         struct drm_i915_private *dev_priv = dev->dev_private;
7020         struct intel_encoder *encoder;
7021         int num_connectors = 0;
7022         bool is_lvds = false;
7023
7024         for_each_intel_encoder(dev, encoder) {
7025                 if (encoder->new_crtc != to_intel_crtc(crtc))
7026                         continue;
7027
7028                 switch (encoder->type) {
7029                 case INTEL_OUTPUT_LVDS:
7030                         is_lvds = true;
7031                         break;
7032                 default:
7033                         break;
7034                 }
7035                 num_connectors++;
7036         }
7037
7038         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7039                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7040                               dev_priv->vbt.lvds_ssc_freq);
7041                 return dev_priv->vbt.lvds_ssc_freq;
7042         }
7043
7044         return 120000;
7045 }
7046
7047 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7048 {
7049         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7051         int pipe = intel_crtc->pipe;
7052         uint32_t val;
7053
7054         val = 0;
7055
7056         switch (intel_crtc->config.pipe_bpp) {
7057         case 18:
7058                 val |= PIPECONF_6BPC;
7059                 break;
7060         case 24:
7061                 val |= PIPECONF_8BPC;
7062                 break;
7063         case 30:
7064                 val |= PIPECONF_10BPC;
7065                 break;
7066         case 36:
7067                 val |= PIPECONF_12BPC;
7068                 break;
7069         default:
7070                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7071                 BUG();
7072         }
7073
7074         if (intel_crtc->config.dither)
7075                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7076
7077         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7078                 val |= PIPECONF_INTERLACED_ILK;
7079         else
7080                 val |= PIPECONF_PROGRESSIVE;
7081
7082         if (intel_crtc->config.limited_color_range)
7083                 val |= PIPECONF_COLOR_RANGE_SELECT;
7084
7085         I915_WRITE(PIPECONF(pipe), val);
7086         POSTING_READ(PIPECONF(pipe));
7087 }
7088
7089 /*
7090  * Set up the pipe CSC unit.
7091  *
7092  * Currently only full range RGB to limited range RGB conversion
7093  * is supported, but eventually this should handle various
7094  * RGB<->YCbCr scenarios as well.
7095  */
7096 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7097 {
7098         struct drm_device *dev = crtc->dev;
7099         struct drm_i915_private *dev_priv = dev->dev_private;
7100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101         int pipe = intel_crtc->pipe;
7102         uint16_t coeff = 0x7800; /* 1.0 */
7103
7104         /*
7105          * TODO: Check what kind of values actually come out of the pipe
7106          * with these coeff/postoff values and adjust to get the best
7107          * accuracy. Perhaps we even need to take the bpc value into
7108          * consideration.
7109          */
7110
7111         if (intel_crtc->config.limited_color_range)
7112                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7113
7114         /*
7115          * GY/GU and RY/RU should be the other way around according
7116          * to BSpec, but reality doesn't agree. Just set them up in
7117          * a way that results in the correct picture.
7118          */
7119         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7120         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7121
7122         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7123         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7124
7125         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7126         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7127
7128         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7129         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7130         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7131
7132         if (INTEL_INFO(dev)->gen > 6) {
7133                 uint16_t postoff = 0;
7134
7135                 if (intel_crtc->config.limited_color_range)
7136                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7137
7138                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7139                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7140                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7141
7142                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7143         } else {
7144                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7145
7146                 if (intel_crtc->config.limited_color_range)
7147                         mode |= CSC_BLACK_SCREEN_OFFSET;
7148
7149                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7150         }
7151 }
7152
7153 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7154 {
7155         struct drm_device *dev = crtc->dev;
7156         struct drm_i915_private *dev_priv = dev->dev_private;
7157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158         enum pipe pipe = intel_crtc->pipe;
7159         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7160         uint32_t val;
7161
7162         val = 0;
7163
7164         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7165                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7166
7167         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7168                 val |= PIPECONF_INTERLACED_ILK;
7169         else
7170                 val |= PIPECONF_PROGRESSIVE;
7171
7172         I915_WRITE(PIPECONF(cpu_transcoder), val);
7173         POSTING_READ(PIPECONF(cpu_transcoder));
7174
7175         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7176         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7177
7178         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7179                 val = 0;
7180
7181                 switch (intel_crtc->config.pipe_bpp) {
7182                 case 18:
7183                         val |= PIPEMISC_DITHER_6_BPC;
7184                         break;
7185                 case 24:
7186                         val |= PIPEMISC_DITHER_8_BPC;
7187                         break;
7188                 case 30:
7189                         val |= PIPEMISC_DITHER_10_BPC;
7190                         break;
7191                 case 36:
7192                         val |= PIPEMISC_DITHER_12_BPC;
7193                         break;
7194                 default:
7195                         /* Case prevented by pipe_config_set_bpp. */
7196                         BUG();
7197                 }
7198
7199                 if (intel_crtc->config.dither)
7200                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7201
7202                 I915_WRITE(PIPEMISC(pipe), val);
7203         }
7204 }
7205
7206 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7207                                     intel_clock_t *clock,
7208                                     bool *has_reduced_clock,
7209                                     intel_clock_t *reduced_clock)
7210 {
7211         struct drm_device *dev = crtc->dev;
7212         struct drm_i915_private *dev_priv = dev->dev_private;
7213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7214         int refclk;
7215         const intel_limit_t *limit;
7216         bool ret, is_lvds = false;
7217
7218         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7219
7220         refclk = ironlake_get_refclk(crtc);
7221
7222         /*
7223          * Returns a set of divisors for the desired target clock with the given
7224          * refclk, or FALSE.  The returned values represent the clock equation:
7225          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7226          */
7227         limit = intel_limit(intel_crtc, refclk);
7228         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7229                                           intel_crtc->new_config->port_clock,
7230                                           refclk, NULL, clock);
7231         if (!ret)
7232                 return false;
7233
7234         if (is_lvds && dev_priv->lvds_downclock_avail) {
7235                 /*
7236                  * Ensure we match the reduced clock's P to the target clock.
7237                  * If the clocks don't match, we can't switch the display clock
7238                  * by using the FP0/FP1. In such case we will disable the LVDS
7239                  * downclock feature.
7240                 */
7241                 *has_reduced_clock =
7242                         dev_priv->display.find_dpll(limit, intel_crtc,
7243                                                     dev_priv->lvds_downclock,
7244                                                     refclk, clock,
7245                                                     reduced_clock);
7246         }
7247
7248         return true;
7249 }
7250
7251 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7252 {
7253         /*
7254          * Account for spread spectrum to avoid
7255          * oversubscribing the link. Max center spread
7256          * is 2.5%; use 5% for safety's sake.
7257          */
7258         u32 bps = target_clock * bpp * 21 / 20;
7259         return DIV_ROUND_UP(bps, link_bw * 8);
7260 }
7261
7262 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7263 {
7264         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7265 }
7266
7267 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7268                                       u32 *fp,
7269                                       intel_clock_t *reduced_clock, u32 *fp2)
7270 {
7271         struct drm_crtc *crtc = &intel_crtc->base;
7272         struct drm_device *dev = crtc->dev;
7273         struct drm_i915_private *dev_priv = dev->dev_private;
7274         struct intel_encoder *intel_encoder;
7275         uint32_t dpll;
7276         int factor, num_connectors = 0;
7277         bool is_lvds = false, is_sdvo = false;
7278
7279         for_each_intel_encoder(dev, intel_encoder) {
7280                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7281                         continue;
7282
7283                 switch (intel_encoder->type) {
7284                 case INTEL_OUTPUT_LVDS:
7285                         is_lvds = true;
7286                         break;
7287                 case INTEL_OUTPUT_SDVO:
7288                 case INTEL_OUTPUT_HDMI:
7289                         is_sdvo = true;
7290                         break;
7291                 default:
7292                         break;
7293                 }
7294
7295                 num_connectors++;
7296         }
7297
7298         /* Enable autotuning of the PLL clock (if permissible) */
7299         factor = 21;
7300         if (is_lvds) {
7301                 if ((intel_panel_use_ssc(dev_priv) &&
7302                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7303                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7304                         factor = 25;
7305         } else if (intel_crtc->new_config->sdvo_tv_clock)
7306                 factor = 20;
7307
7308         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7309                 *fp |= FP_CB_TUNE;
7310
7311         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7312                 *fp2 |= FP_CB_TUNE;
7313
7314         dpll = 0;
7315
7316         if (is_lvds)
7317                 dpll |= DPLLB_MODE_LVDS;
7318         else
7319                 dpll |= DPLLB_MODE_DAC_SERIAL;
7320
7321         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7322                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7323
7324         if (is_sdvo)
7325                 dpll |= DPLL_SDVO_HIGH_SPEED;
7326         if (intel_crtc->new_config->has_dp_encoder)
7327                 dpll |= DPLL_SDVO_HIGH_SPEED;
7328
7329         /* compute bitmask from p1 value */
7330         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7331         /* also FPA1 */
7332         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7333
7334         switch (intel_crtc->new_config->dpll.p2) {
7335         case 5:
7336                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7337                 break;
7338         case 7:
7339                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7340                 break;
7341         case 10:
7342                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7343                 break;
7344         case 14:
7345                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7346                 break;
7347         }
7348
7349         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7350                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7351         else
7352                 dpll |= PLL_REF_INPUT_DREFCLK;
7353
7354         return dpll | DPLL_VCO_ENABLE;
7355 }
7356
7357 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7358                                   int x, int y,
7359                                   struct drm_framebuffer *fb)
7360 {
7361         struct drm_device *dev = crtc->base.dev;
7362         intel_clock_t clock, reduced_clock;
7363         u32 dpll = 0, fp = 0, fp2 = 0;
7364         bool ok, has_reduced_clock = false;
7365         bool is_lvds = false;
7366         struct intel_shared_dpll *pll;
7367
7368         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7369
7370         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7371              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7372
7373         ok = ironlake_compute_clocks(&crtc->base, &clock,
7374                                      &has_reduced_clock, &reduced_clock);
7375         if (!ok && !crtc->new_config->clock_set) {
7376                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7377                 return -EINVAL;
7378         }
7379         /* Compat-code for transition, will disappear. */
7380         if (!crtc->new_config->clock_set) {
7381                 crtc->new_config->dpll.n = clock.n;
7382                 crtc->new_config->dpll.m1 = clock.m1;
7383                 crtc->new_config->dpll.m2 = clock.m2;
7384                 crtc->new_config->dpll.p1 = clock.p1;
7385                 crtc->new_config->dpll.p2 = clock.p2;
7386         }
7387
7388         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7389         if (crtc->new_config->has_pch_encoder) {
7390                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7391                 if (has_reduced_clock)
7392                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7393
7394                 dpll = ironlake_compute_dpll(crtc,
7395                                              &fp, &reduced_clock,
7396                                              has_reduced_clock ? &fp2 : NULL);
7397
7398                 crtc->new_config->dpll_hw_state.dpll = dpll;
7399                 crtc->new_config->dpll_hw_state.fp0 = fp;
7400                 if (has_reduced_clock)
7401                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7402                 else
7403                         crtc->new_config->dpll_hw_state.fp1 = fp;
7404
7405                 pll = intel_get_shared_dpll(crtc);
7406                 if (pll == NULL) {
7407                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7408                                          pipe_name(crtc->pipe));
7409                         return -EINVAL;
7410                 }
7411         } else
7412                 intel_put_shared_dpll(crtc);
7413
7414         if (is_lvds && has_reduced_clock && i915.powersave)
7415                 crtc->lowfreq_avail = true;
7416         else
7417                 crtc->lowfreq_avail = false;
7418
7419         return 0;
7420 }
7421
7422 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7423                                          struct intel_link_m_n *m_n)
7424 {
7425         struct drm_device *dev = crtc->base.dev;
7426         struct drm_i915_private *dev_priv = dev->dev_private;
7427         enum pipe pipe = crtc->pipe;
7428
7429         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7430         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7431         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7432                 & ~TU_SIZE_MASK;
7433         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7434         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7435                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7436 }
7437
7438 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7439                                          enum transcoder transcoder,
7440                                          struct intel_link_m_n *m_n,
7441                                          struct intel_link_m_n *m2_n2)
7442 {
7443         struct drm_device *dev = crtc->base.dev;
7444         struct drm_i915_private *dev_priv = dev->dev_private;
7445         enum pipe pipe = crtc->pipe;
7446
7447         if (INTEL_INFO(dev)->gen >= 5) {
7448                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7449                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7450                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7451                         & ~TU_SIZE_MASK;
7452                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7453                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7454                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7455                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7456                  * gen < 8) and if DRRS is supported (to make sure the
7457                  * registers are not unnecessarily read).
7458                  */
7459                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7460                         crtc->config.has_drrs) {
7461                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7462                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7463                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7464                                         & ~TU_SIZE_MASK;
7465                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7466                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7467                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7468                 }
7469         } else {
7470                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7471                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7472                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7473                         & ~TU_SIZE_MASK;
7474                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7475                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7476                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7477         }
7478 }
7479
7480 void intel_dp_get_m_n(struct intel_crtc *crtc,
7481                       struct intel_crtc_config *pipe_config)
7482 {
7483         if (crtc->config.has_pch_encoder)
7484                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7485         else
7486                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7487                                              &pipe_config->dp_m_n,
7488                                              &pipe_config->dp_m2_n2);
7489 }
7490
7491 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7492                                         struct intel_crtc_config *pipe_config)
7493 {
7494         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7495                                      &pipe_config->fdi_m_n, NULL);
7496 }
7497
7498 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7499                                      struct intel_crtc_config *pipe_config)
7500 {
7501         struct drm_device *dev = crtc->base.dev;
7502         struct drm_i915_private *dev_priv = dev->dev_private;
7503         uint32_t tmp;
7504
7505         tmp = I915_READ(PF_CTL(crtc->pipe));
7506
7507         if (tmp & PF_ENABLE) {
7508                 pipe_config->pch_pfit.enabled = true;
7509                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7510                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7511
7512                 /* We currently do not free assignements of panel fitters on
7513                  * ivb/hsw (since we don't use the higher upscaling modes which
7514                  * differentiates them) so just WARN about this case for now. */
7515                 if (IS_GEN7(dev)) {
7516                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7517                                 PF_PIPE_SEL_IVB(crtc->pipe));
7518                 }
7519         }
7520 }
7521
7522 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7523                                       struct intel_plane_config *plane_config)
7524 {
7525         struct drm_device *dev = crtc->base.dev;
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         u32 val, base, offset;
7528         int pipe = crtc->pipe, plane = crtc->plane;
7529         int fourcc, pixel_format;
7530         int aligned_height;
7531
7532         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7533         if (!crtc->base.primary->fb) {
7534                 DRM_DEBUG_KMS("failed to alloc fb\n");
7535                 return;
7536         }
7537
7538         val = I915_READ(DSPCNTR(plane));
7539
7540         if (INTEL_INFO(dev)->gen >= 4)
7541                 if (val & DISPPLANE_TILED)
7542                         plane_config->tiled = true;
7543
7544         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7545         fourcc = intel_format_to_fourcc(pixel_format);
7546         crtc->base.primary->fb->pixel_format = fourcc;
7547         crtc->base.primary->fb->bits_per_pixel =
7548                 drm_format_plane_cpp(fourcc, 0) * 8;
7549
7550         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7551         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7552                 offset = I915_READ(DSPOFFSET(plane));
7553         } else {
7554                 if (plane_config->tiled)
7555                         offset = I915_READ(DSPTILEOFF(plane));
7556                 else
7557                         offset = I915_READ(DSPLINOFF(plane));
7558         }
7559         plane_config->base = base;
7560
7561         val = I915_READ(PIPESRC(pipe));
7562         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7563         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7564
7565         val = I915_READ(DSPSTRIDE(pipe));
7566         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7567
7568         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7569                                             plane_config->tiled);
7570
7571         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7572                                         aligned_height);
7573
7574         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7575                       pipe, plane, crtc->base.primary->fb->width,
7576                       crtc->base.primary->fb->height,
7577                       crtc->base.primary->fb->bits_per_pixel, base,
7578                       crtc->base.primary->fb->pitches[0],
7579                       plane_config->size);
7580 }
7581
7582 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7583                                      struct intel_crtc_config *pipe_config)
7584 {
7585         struct drm_device *dev = crtc->base.dev;
7586         struct drm_i915_private *dev_priv = dev->dev_private;
7587         uint32_t tmp;
7588
7589         if (!intel_display_power_is_enabled(dev_priv,
7590                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7591                 return false;
7592
7593         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7594         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7595
7596         tmp = I915_READ(PIPECONF(crtc->pipe));
7597         if (!(tmp & PIPECONF_ENABLE))
7598                 return false;
7599
7600         switch (tmp & PIPECONF_BPC_MASK) {
7601         case PIPECONF_6BPC:
7602                 pipe_config->pipe_bpp = 18;
7603                 break;
7604         case PIPECONF_8BPC:
7605                 pipe_config->pipe_bpp = 24;
7606                 break;
7607         case PIPECONF_10BPC:
7608                 pipe_config->pipe_bpp = 30;
7609                 break;
7610         case PIPECONF_12BPC:
7611                 pipe_config->pipe_bpp = 36;
7612                 break;
7613         default:
7614                 break;
7615         }
7616
7617         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7618                 pipe_config->limited_color_range = true;
7619
7620         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7621                 struct intel_shared_dpll *pll;
7622
7623                 pipe_config->has_pch_encoder = true;
7624
7625                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7626                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7627                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7628
7629                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7630
7631                 if (HAS_PCH_IBX(dev_priv->dev)) {
7632                         pipe_config->shared_dpll =
7633                                 (enum intel_dpll_id) crtc->pipe;
7634                 } else {
7635                         tmp = I915_READ(PCH_DPLL_SEL);
7636                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7637                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7638                         else
7639                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7640                 }
7641
7642                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7643
7644                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7645                                            &pipe_config->dpll_hw_state));
7646
7647                 tmp = pipe_config->dpll_hw_state.dpll;
7648                 pipe_config->pixel_multiplier =
7649                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7650                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7651
7652                 ironlake_pch_clock_get(crtc, pipe_config);
7653         } else {
7654                 pipe_config->pixel_multiplier = 1;
7655         }
7656
7657         intel_get_pipe_timings(crtc, pipe_config);
7658
7659         ironlake_get_pfit_config(crtc, pipe_config);
7660
7661         return true;
7662 }
7663
7664 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7665 {
7666         struct drm_device *dev = dev_priv->dev;
7667         struct intel_crtc *crtc;
7668
7669         for_each_intel_crtc(dev, crtc)
7670                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7671                      pipe_name(crtc->pipe));
7672
7673         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7674         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7675         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7676         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7677         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7678         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7679              "CPU PWM1 enabled\n");
7680         if (IS_HASWELL(dev))
7681                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7682                      "CPU PWM2 enabled\n");
7683         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7684              "PCH PWM1 enabled\n");
7685         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7686              "Utility pin enabled\n");
7687         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7688
7689         /*
7690          * In theory we can still leave IRQs enabled, as long as only the HPD
7691          * interrupts remain enabled. We used to check for that, but since it's
7692          * gen-specific and since we only disable LCPLL after we fully disable
7693          * the interrupts, the check below should be enough.
7694          */
7695         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7696 }
7697
7698 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7699 {
7700         struct drm_device *dev = dev_priv->dev;
7701
7702         if (IS_HASWELL(dev))
7703                 return I915_READ(D_COMP_HSW);
7704         else
7705                 return I915_READ(D_COMP_BDW);
7706 }
7707
7708 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7709 {
7710         struct drm_device *dev = dev_priv->dev;
7711
7712         if (IS_HASWELL(dev)) {
7713                 mutex_lock(&dev_priv->rps.hw_lock);
7714                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7715                                             val))
7716                         DRM_ERROR("Failed to write to D_COMP\n");
7717                 mutex_unlock(&dev_priv->rps.hw_lock);
7718         } else {
7719                 I915_WRITE(D_COMP_BDW, val);
7720                 POSTING_READ(D_COMP_BDW);
7721         }
7722 }
7723
7724 /*
7725  * This function implements pieces of two sequences from BSpec:
7726  * - Sequence for display software to disable LCPLL
7727  * - Sequence for display software to allow package C8+
7728  * The steps implemented here are just the steps that actually touch the LCPLL
7729  * register. Callers should take care of disabling all the display engine
7730  * functions, doing the mode unset, fixing interrupts, etc.
7731  */
7732 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7733                               bool switch_to_fclk, bool allow_power_down)
7734 {
7735         uint32_t val;
7736
7737         assert_can_disable_lcpll(dev_priv);
7738
7739         val = I915_READ(LCPLL_CTL);
7740
7741         if (switch_to_fclk) {
7742                 val |= LCPLL_CD_SOURCE_FCLK;
7743                 I915_WRITE(LCPLL_CTL, val);
7744
7745                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7746                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7747                         DRM_ERROR("Switching to FCLK failed\n");
7748
7749                 val = I915_READ(LCPLL_CTL);
7750         }
7751
7752         val |= LCPLL_PLL_DISABLE;
7753         I915_WRITE(LCPLL_CTL, val);
7754         POSTING_READ(LCPLL_CTL);
7755
7756         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7757                 DRM_ERROR("LCPLL still locked\n");
7758
7759         val = hsw_read_dcomp(dev_priv);
7760         val |= D_COMP_COMP_DISABLE;
7761         hsw_write_dcomp(dev_priv, val);
7762         ndelay(100);
7763
7764         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7765                      1))
7766                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7767
7768         if (allow_power_down) {
7769                 val = I915_READ(LCPLL_CTL);
7770                 val |= LCPLL_POWER_DOWN_ALLOW;
7771                 I915_WRITE(LCPLL_CTL, val);
7772                 POSTING_READ(LCPLL_CTL);
7773         }
7774 }
7775
7776 /*
7777  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7778  * source.
7779  */
7780 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7781 {
7782         uint32_t val;
7783
7784         val = I915_READ(LCPLL_CTL);
7785
7786         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7787                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7788                 return;
7789
7790         /*
7791          * Make sure we're not on PC8 state before disabling PC8, otherwise
7792          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7793          *
7794          * The other problem is that hsw_restore_lcpll() is called as part of
7795          * the runtime PM resume sequence, so we can't just call
7796          * gen6_gt_force_wake_get() because that function calls
7797          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7798          * while we are on the resume sequence. So to solve this problem we have
7799          * to call special forcewake code that doesn't touch runtime PM and
7800          * doesn't enable the forcewake delayed work.
7801          */
7802         spin_lock_irq(&dev_priv->uncore.lock);
7803         if (dev_priv->uncore.forcewake_count++ == 0)
7804                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7805         spin_unlock_irq(&dev_priv->uncore.lock);
7806
7807         if (val & LCPLL_POWER_DOWN_ALLOW) {
7808                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7809                 I915_WRITE(LCPLL_CTL, val);
7810                 POSTING_READ(LCPLL_CTL);
7811         }
7812
7813         val = hsw_read_dcomp(dev_priv);
7814         val |= D_COMP_COMP_FORCE;
7815         val &= ~D_COMP_COMP_DISABLE;
7816         hsw_write_dcomp(dev_priv, val);
7817
7818         val = I915_READ(LCPLL_CTL);
7819         val &= ~LCPLL_PLL_DISABLE;
7820         I915_WRITE(LCPLL_CTL, val);
7821
7822         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7823                 DRM_ERROR("LCPLL not locked yet\n");
7824
7825         if (val & LCPLL_CD_SOURCE_FCLK) {
7826                 val = I915_READ(LCPLL_CTL);
7827                 val &= ~LCPLL_CD_SOURCE_FCLK;
7828                 I915_WRITE(LCPLL_CTL, val);
7829
7830                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7831                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7832                         DRM_ERROR("Switching back to LCPLL failed\n");
7833         }
7834
7835         /* See the big comment above. */
7836         spin_lock_irq(&dev_priv->uncore.lock);
7837         if (--dev_priv->uncore.forcewake_count == 0)
7838                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7839         spin_unlock_irq(&dev_priv->uncore.lock);
7840 }
7841
7842 /*
7843  * Package states C8 and deeper are really deep PC states that can only be
7844  * reached when all the devices on the system allow it, so even if the graphics
7845  * device allows PC8+, it doesn't mean the system will actually get to these
7846  * states. Our driver only allows PC8+ when going into runtime PM.
7847  *
7848  * The requirements for PC8+ are that all the outputs are disabled, the power
7849  * well is disabled and most interrupts are disabled, and these are also
7850  * requirements for runtime PM. When these conditions are met, we manually do
7851  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7852  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7853  * hang the machine.
7854  *
7855  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7856  * the state of some registers, so when we come back from PC8+ we need to
7857  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7858  * need to take care of the registers kept by RC6. Notice that this happens even
7859  * if we don't put the device in PCI D3 state (which is what currently happens
7860  * because of the runtime PM support).
7861  *
7862  * For more, read "Display Sequences for Package C8" on the hardware
7863  * documentation.
7864  */
7865 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7866 {
7867         struct drm_device *dev = dev_priv->dev;
7868         uint32_t val;
7869
7870         DRM_DEBUG_KMS("Enabling package C8+\n");
7871
7872         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7873                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7874                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7875                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7876         }
7877
7878         lpt_disable_clkout_dp(dev);
7879         hsw_disable_lcpll(dev_priv, true, true);
7880 }
7881
7882 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7883 {
7884         struct drm_device *dev = dev_priv->dev;
7885         uint32_t val;
7886
7887         DRM_DEBUG_KMS("Disabling package C8+\n");
7888
7889         hsw_restore_lcpll(dev_priv);
7890         lpt_init_pch_refclk(dev);
7891
7892         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7893                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7894                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7895                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7896         }
7897
7898         intel_prepare_ddi(dev);
7899 }
7900
7901 static void snb_modeset_global_resources(struct drm_device *dev)
7902 {
7903         modeset_update_crtc_power_domains(dev);
7904 }
7905
7906 static void haswell_modeset_global_resources(struct drm_device *dev)
7907 {
7908         modeset_update_crtc_power_domains(dev);
7909 }
7910
7911 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7912                                  int x, int y,
7913                                  struct drm_framebuffer *fb)
7914 {
7915         if (!intel_ddi_pll_select(crtc))
7916                 return -EINVAL;
7917
7918         crtc->lowfreq_avail = false;
7919
7920         return 0;
7921 }
7922
7923 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7924                                 enum port port,
7925                                 struct intel_crtc_config *pipe_config)
7926 {
7927         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7928
7929         switch (pipe_config->ddi_pll_sel) {
7930         case PORT_CLK_SEL_WRPLL1:
7931                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7932                 break;
7933         case PORT_CLK_SEL_WRPLL2:
7934                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7935                 break;
7936         }
7937 }
7938
7939 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7940                                        struct intel_crtc_config *pipe_config)
7941 {
7942         struct drm_device *dev = crtc->base.dev;
7943         struct drm_i915_private *dev_priv = dev->dev_private;
7944         struct intel_shared_dpll *pll;
7945         enum port port;
7946         uint32_t tmp;
7947
7948         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7949
7950         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7951
7952         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7953
7954         if (pipe_config->shared_dpll >= 0) {
7955                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7956
7957                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7958                                            &pipe_config->dpll_hw_state));
7959         }
7960
7961         /*
7962          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7963          * DDI E. So just check whether this pipe is wired to DDI E and whether
7964          * the PCH transcoder is on.
7965          */
7966         if (INTEL_INFO(dev)->gen < 9 &&
7967             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7968                 pipe_config->has_pch_encoder = true;
7969
7970                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7971                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7972                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7973
7974                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7975         }
7976 }
7977
7978 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7979                                     struct intel_crtc_config *pipe_config)
7980 {
7981         struct drm_device *dev = crtc->base.dev;
7982         struct drm_i915_private *dev_priv = dev->dev_private;
7983         enum intel_display_power_domain pfit_domain;
7984         uint32_t tmp;
7985
7986         if (!intel_display_power_is_enabled(dev_priv,
7987                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7988                 return false;
7989
7990         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7991         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7992
7993         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7994         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7995                 enum pipe trans_edp_pipe;
7996                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7997                 default:
7998                         WARN(1, "unknown pipe linked to edp transcoder\n");
7999                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8000                 case TRANS_DDI_EDP_INPUT_A_ON:
8001                         trans_edp_pipe = PIPE_A;
8002                         break;
8003                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8004                         trans_edp_pipe = PIPE_B;
8005                         break;
8006                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8007                         trans_edp_pipe = PIPE_C;
8008                         break;
8009                 }
8010
8011                 if (trans_edp_pipe == crtc->pipe)
8012                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8013         }
8014
8015         if (!intel_display_power_is_enabled(dev_priv,
8016                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8017                 return false;
8018
8019         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8020         if (!(tmp & PIPECONF_ENABLE))
8021                 return false;
8022
8023         haswell_get_ddi_port_state(crtc, pipe_config);
8024
8025         intel_get_pipe_timings(crtc, pipe_config);
8026
8027         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8028         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8029                 ironlake_get_pfit_config(crtc, pipe_config);
8030
8031         if (IS_HASWELL(dev))
8032                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8033                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8034
8035         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8036                 pipe_config->pixel_multiplier =
8037                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8038         } else {
8039                 pipe_config->pixel_multiplier = 1;
8040         }
8041
8042         return true;
8043 }
8044
8045 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8046 {
8047         struct drm_device *dev = crtc->dev;
8048         struct drm_i915_private *dev_priv = dev->dev_private;
8049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8050         uint32_t cntl = 0, size = 0;
8051
8052         if (base) {
8053                 unsigned int width = intel_crtc->cursor_width;
8054                 unsigned int height = intel_crtc->cursor_height;
8055                 unsigned int stride = roundup_pow_of_two(width) * 4;
8056
8057                 switch (stride) {
8058                 default:
8059                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8060                                   width, stride);
8061                         stride = 256;
8062                         /* fallthrough */
8063                 case 256:
8064                 case 512:
8065                 case 1024:
8066                 case 2048:
8067                         break;
8068                 }
8069
8070                 cntl |= CURSOR_ENABLE |
8071                         CURSOR_GAMMA_ENABLE |
8072                         CURSOR_FORMAT_ARGB |
8073                         CURSOR_STRIDE(stride);
8074
8075                 size = (height << 12) | width;
8076         }
8077
8078         if (intel_crtc->cursor_cntl != 0 &&
8079             (intel_crtc->cursor_base != base ||
8080              intel_crtc->cursor_size != size ||
8081              intel_crtc->cursor_cntl != cntl)) {
8082                 /* On these chipsets we can only modify the base/size/stride
8083                  * whilst the cursor is disabled.
8084                  */
8085                 I915_WRITE(_CURACNTR, 0);
8086                 POSTING_READ(_CURACNTR);
8087                 intel_crtc->cursor_cntl = 0;
8088         }
8089
8090         if (intel_crtc->cursor_base != base) {
8091                 I915_WRITE(_CURABASE, base);
8092                 intel_crtc->cursor_base = base;
8093         }
8094
8095         if (intel_crtc->cursor_size != size) {
8096                 I915_WRITE(CURSIZE, size);
8097                 intel_crtc->cursor_size = size;
8098         }
8099
8100         if (intel_crtc->cursor_cntl != cntl) {
8101                 I915_WRITE(_CURACNTR, cntl);
8102                 POSTING_READ(_CURACNTR);
8103                 intel_crtc->cursor_cntl = cntl;
8104         }
8105 }
8106
8107 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8108 {
8109         struct drm_device *dev = crtc->dev;
8110         struct drm_i915_private *dev_priv = dev->dev_private;
8111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8112         int pipe = intel_crtc->pipe;
8113         uint32_t cntl;
8114
8115         cntl = 0;
8116         if (base) {
8117                 cntl = MCURSOR_GAMMA_ENABLE;
8118                 switch (intel_crtc->cursor_width) {
8119                         case 64:
8120                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8121                                 break;
8122                         case 128:
8123                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8124                                 break;
8125                         case 256:
8126                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8127                                 break;
8128                         default:
8129                                 WARN_ON(1);
8130                                 return;
8131                 }
8132                 cntl |= pipe << 28; /* Connect to correct pipe */
8133
8134                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8135                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8136         }
8137
8138         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8139                 cntl |= CURSOR_ROTATE_180;
8140
8141         if (intel_crtc->cursor_cntl != cntl) {
8142                 I915_WRITE(CURCNTR(pipe), cntl);
8143                 POSTING_READ(CURCNTR(pipe));
8144                 intel_crtc->cursor_cntl = cntl;
8145         }
8146
8147         /* and commit changes on next vblank */
8148         I915_WRITE(CURBASE(pipe), base);
8149         POSTING_READ(CURBASE(pipe));
8150
8151         intel_crtc->cursor_base = base;
8152 }
8153
8154 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8155 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8156                                      bool on)
8157 {
8158         struct drm_device *dev = crtc->dev;
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8161         int pipe = intel_crtc->pipe;
8162         int x = crtc->cursor_x;
8163         int y = crtc->cursor_y;
8164         u32 base = 0, pos = 0;
8165
8166         if (on)
8167                 base = intel_crtc->cursor_addr;
8168
8169         if (x >= intel_crtc->config.pipe_src_w)
8170                 base = 0;
8171
8172         if (y >= intel_crtc->config.pipe_src_h)
8173                 base = 0;
8174
8175         if (x < 0) {
8176                 if (x + intel_crtc->cursor_width <= 0)
8177                         base = 0;
8178
8179                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8180                 x = -x;
8181         }
8182         pos |= x << CURSOR_X_SHIFT;
8183
8184         if (y < 0) {
8185                 if (y + intel_crtc->cursor_height <= 0)
8186                         base = 0;
8187
8188                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8189                 y = -y;
8190         }
8191         pos |= y << CURSOR_Y_SHIFT;
8192
8193         if (base == 0 && intel_crtc->cursor_base == 0)
8194                 return;
8195
8196         I915_WRITE(CURPOS(pipe), pos);
8197
8198         /* ILK+ do this automagically */
8199         if (HAS_GMCH_DISPLAY(dev) &&
8200                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8201                 base += (intel_crtc->cursor_height *
8202                         intel_crtc->cursor_width - 1) * 4;
8203         }
8204
8205         if (IS_845G(dev) || IS_I865G(dev))
8206                 i845_update_cursor(crtc, base);
8207         else
8208                 i9xx_update_cursor(crtc, base);
8209 }
8210
8211 static bool cursor_size_ok(struct drm_device *dev,
8212                            uint32_t width, uint32_t height)
8213 {
8214         if (width == 0 || height == 0)
8215                 return false;
8216
8217         /*
8218          * 845g/865g are special in that they are only limited by
8219          * the width of their cursors, the height is arbitrary up to
8220          * the precision of the register. Everything else requires
8221          * square cursors, limited to a few power-of-two sizes.
8222          */
8223         if (IS_845G(dev) || IS_I865G(dev)) {
8224                 if ((width & 63) != 0)
8225                         return false;
8226
8227                 if (width > (IS_845G(dev) ? 64 : 512))
8228                         return false;
8229
8230                 if (height > 1023)
8231                         return false;
8232         } else {
8233                 switch (width | height) {
8234                 case 256:
8235                 case 128:
8236                         if (IS_GEN2(dev))
8237                                 return false;
8238                 case 64:
8239                         break;
8240                 default:
8241                         return false;
8242                 }
8243         }
8244
8245         return true;
8246 }
8247
8248 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8249                                      struct drm_i915_gem_object *obj,
8250                                      uint32_t width, uint32_t height)
8251 {
8252         struct drm_device *dev = crtc->dev;
8253         struct drm_i915_private *dev_priv = dev->dev_private;
8254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8255         enum pipe pipe = intel_crtc->pipe;
8256         unsigned old_width;
8257         uint32_t addr;
8258         int ret;
8259
8260         /* if we want to turn off the cursor ignore width and height */
8261         if (!obj) {
8262                 DRM_DEBUG_KMS("cursor off\n");
8263                 addr = 0;
8264                 mutex_lock(&dev->struct_mutex);
8265                 goto finish;
8266         }
8267
8268         /* we only need to pin inside GTT if cursor is non-phy */
8269         mutex_lock(&dev->struct_mutex);
8270         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8271                 unsigned alignment;
8272
8273                 /*
8274                  * Global gtt pte registers are special registers which actually
8275                  * forward writes to a chunk of system memory. Which means that
8276                  * there is no risk that the register values disappear as soon
8277                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8278                  * only the pin/unpin/fence and not more.
8279                  */
8280                 intel_runtime_pm_get(dev_priv);
8281
8282                 /* Note that the w/a also requires 2 PTE of padding following
8283                  * the bo. We currently fill all unused PTE with the shadow
8284                  * page and so we should always have valid PTE following the
8285                  * cursor preventing the VT-d warning.
8286                  */
8287                 alignment = 0;
8288                 if (need_vtd_wa(dev))
8289                         alignment = 64*1024;
8290
8291                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8292                 if (ret) {
8293                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8294                         intel_runtime_pm_put(dev_priv);
8295                         goto fail_locked;
8296                 }
8297
8298                 ret = i915_gem_object_put_fence(obj);
8299                 if (ret) {
8300                         DRM_DEBUG_KMS("failed to release fence for cursor");
8301                         intel_runtime_pm_put(dev_priv);
8302                         goto fail_unpin;
8303                 }
8304
8305                 addr = i915_gem_obj_ggtt_offset(obj);
8306
8307                 intel_runtime_pm_put(dev_priv);
8308         } else {
8309                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8310                 ret = i915_gem_object_attach_phys(obj, align);
8311                 if (ret) {
8312                         DRM_DEBUG_KMS("failed to attach phys object\n");
8313                         goto fail_locked;
8314                 }
8315                 addr = obj->phys_handle->busaddr;
8316         }
8317
8318  finish:
8319         if (intel_crtc->cursor_bo) {
8320                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8321                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8322         }
8323
8324         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8325                           INTEL_FRONTBUFFER_CURSOR(pipe));
8326         mutex_unlock(&dev->struct_mutex);
8327
8328         old_width = intel_crtc->cursor_width;
8329
8330         intel_crtc->cursor_addr = addr;
8331         intel_crtc->cursor_bo = obj;
8332         intel_crtc->cursor_width = width;
8333         intel_crtc->cursor_height = height;
8334
8335         if (intel_crtc->active) {
8336                 if (old_width != width)
8337                         intel_update_watermarks(crtc);
8338                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8339
8340                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8341         }
8342
8343         return 0;
8344 fail_unpin:
8345         i915_gem_object_unpin_from_display_plane(obj);
8346 fail_locked:
8347         mutex_unlock(&dev->struct_mutex);
8348         return ret;
8349 }
8350
8351 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8352                                  u16 *blue, uint32_t start, uint32_t size)
8353 {
8354         int end = (start + size > 256) ? 256 : start + size, i;
8355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8356
8357         for (i = start; i < end; i++) {
8358                 intel_crtc->lut_r[i] = red[i] >> 8;
8359                 intel_crtc->lut_g[i] = green[i] >> 8;
8360                 intel_crtc->lut_b[i] = blue[i] >> 8;
8361         }
8362
8363         intel_crtc_load_lut(crtc);
8364 }
8365
8366 /* VESA 640x480x72Hz mode to set on the pipe */
8367 static struct drm_display_mode load_detect_mode = {
8368         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8369                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8370 };
8371
8372 struct drm_framebuffer *
8373 __intel_framebuffer_create(struct drm_device *dev,
8374                            struct drm_mode_fb_cmd2 *mode_cmd,
8375                            struct drm_i915_gem_object *obj)
8376 {
8377         struct intel_framebuffer *intel_fb;
8378         int ret;
8379
8380         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8381         if (!intel_fb) {
8382                 drm_gem_object_unreference_unlocked(&obj->base);
8383                 return ERR_PTR(-ENOMEM);
8384         }
8385
8386         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8387         if (ret)
8388                 goto err;
8389
8390         return &intel_fb->base;
8391 err:
8392         drm_gem_object_unreference_unlocked(&obj->base);
8393         kfree(intel_fb);
8394
8395         return ERR_PTR(ret);
8396 }
8397
8398 static struct drm_framebuffer *
8399 intel_framebuffer_create(struct drm_device *dev,
8400                          struct drm_mode_fb_cmd2 *mode_cmd,
8401                          struct drm_i915_gem_object *obj)
8402 {
8403         struct drm_framebuffer *fb;
8404         int ret;
8405
8406         ret = i915_mutex_lock_interruptible(dev);
8407         if (ret)
8408                 return ERR_PTR(ret);
8409         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8410         mutex_unlock(&dev->struct_mutex);
8411
8412         return fb;
8413 }
8414
8415 static u32
8416 intel_framebuffer_pitch_for_width(int width, int bpp)
8417 {
8418         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8419         return ALIGN(pitch, 64);
8420 }
8421
8422 static u32
8423 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8424 {
8425         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8426         return PAGE_ALIGN(pitch * mode->vdisplay);
8427 }
8428
8429 static struct drm_framebuffer *
8430 intel_framebuffer_create_for_mode(struct drm_device *dev,
8431                                   struct drm_display_mode *mode,
8432                                   int depth, int bpp)
8433 {
8434         struct drm_i915_gem_object *obj;
8435         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8436
8437         obj = i915_gem_alloc_object(dev,
8438                                     intel_framebuffer_size_for_mode(mode, bpp));
8439         if (obj == NULL)
8440                 return ERR_PTR(-ENOMEM);
8441
8442         mode_cmd.width = mode->hdisplay;
8443         mode_cmd.height = mode->vdisplay;
8444         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8445                                                                 bpp);
8446         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8447
8448         return intel_framebuffer_create(dev, &mode_cmd, obj);
8449 }
8450
8451 static struct drm_framebuffer *
8452 mode_fits_in_fbdev(struct drm_device *dev,
8453                    struct drm_display_mode *mode)
8454 {
8455 #ifdef CONFIG_DRM_I915_FBDEV
8456         struct drm_i915_private *dev_priv = dev->dev_private;
8457         struct drm_i915_gem_object *obj;
8458         struct drm_framebuffer *fb;
8459
8460         if (!dev_priv->fbdev)
8461                 return NULL;
8462
8463         if (!dev_priv->fbdev->fb)
8464                 return NULL;
8465
8466         obj = dev_priv->fbdev->fb->obj;
8467         BUG_ON(!obj);
8468
8469         fb = &dev_priv->fbdev->fb->base;
8470         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8471                                                                fb->bits_per_pixel))
8472                 return NULL;
8473
8474         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8475                 return NULL;
8476
8477         return fb;
8478 #else
8479         return NULL;
8480 #endif
8481 }
8482
8483 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8484                                 struct drm_display_mode *mode,
8485                                 struct intel_load_detect_pipe *old,
8486                                 struct drm_modeset_acquire_ctx *ctx)
8487 {
8488         struct intel_crtc *intel_crtc;
8489         struct intel_encoder *intel_encoder =
8490                 intel_attached_encoder(connector);
8491         struct drm_crtc *possible_crtc;
8492         struct drm_encoder *encoder = &intel_encoder->base;
8493         struct drm_crtc *crtc = NULL;
8494         struct drm_device *dev = encoder->dev;
8495         struct drm_framebuffer *fb;
8496         struct drm_mode_config *config = &dev->mode_config;
8497         int ret, i = -1;
8498
8499         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8500                       connector->base.id, connector->name,
8501                       encoder->base.id, encoder->name);
8502
8503 retry:
8504         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8505         if (ret)
8506                 goto fail_unlock;
8507
8508         /*
8509          * Algorithm gets a little messy:
8510          *
8511          *   - if the connector already has an assigned crtc, use it (but make
8512          *     sure it's on first)
8513          *
8514          *   - try to find the first unused crtc that can drive this connector,
8515          *     and use that if we find one
8516          */
8517
8518         /* See if we already have a CRTC for this connector */
8519         if (encoder->crtc) {
8520                 crtc = encoder->crtc;
8521
8522                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8523                 if (ret)
8524                         goto fail_unlock;
8525
8526                 old->dpms_mode = connector->dpms;
8527                 old->load_detect_temp = false;
8528
8529                 /* Make sure the crtc and connector are running */
8530                 if (connector->dpms != DRM_MODE_DPMS_ON)
8531                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8532
8533                 return true;
8534         }
8535
8536         /* Find an unused one (if possible) */
8537         for_each_crtc(dev, possible_crtc) {
8538                 i++;
8539                 if (!(encoder->possible_crtcs & (1 << i)))
8540                         continue;
8541                 if (possible_crtc->enabled)
8542                         continue;
8543                 /* This can occur when applying the pipe A quirk on resume. */
8544                 if (to_intel_crtc(possible_crtc)->new_enabled)
8545                         continue;
8546
8547                 crtc = possible_crtc;
8548                 break;
8549         }
8550
8551         /*
8552          * If we didn't find an unused CRTC, don't use any.
8553          */
8554         if (!crtc) {
8555                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8556                 goto fail_unlock;
8557         }
8558
8559         ret = drm_modeset_lock(&crtc->mutex, ctx);
8560         if (ret)
8561                 goto fail_unlock;
8562         intel_encoder->new_crtc = to_intel_crtc(crtc);
8563         to_intel_connector(connector)->new_encoder = intel_encoder;
8564
8565         intel_crtc = to_intel_crtc(crtc);
8566         intel_crtc->new_enabled = true;
8567         intel_crtc->new_config = &intel_crtc->config;
8568         old->dpms_mode = connector->dpms;
8569         old->load_detect_temp = true;
8570         old->release_fb = NULL;
8571
8572         if (!mode)
8573                 mode = &load_detect_mode;
8574
8575         /* We need a framebuffer large enough to accommodate all accesses
8576          * that the plane may generate whilst we perform load detection.
8577          * We can not rely on the fbcon either being present (we get called
8578          * during its initialisation to detect all boot displays, or it may
8579          * not even exist) or that it is large enough to satisfy the
8580          * requested mode.
8581          */
8582         fb = mode_fits_in_fbdev(dev, mode);
8583         if (fb == NULL) {
8584                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8585                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8586                 old->release_fb = fb;
8587         } else
8588                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8589         if (IS_ERR(fb)) {
8590                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8591                 goto fail;
8592         }
8593
8594         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8595                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8596                 if (old->release_fb)
8597                         old->release_fb->funcs->destroy(old->release_fb);
8598                 goto fail;
8599         }
8600
8601         /* let the connector get through one full cycle before testing */
8602         intel_wait_for_vblank(dev, intel_crtc->pipe);
8603         return true;
8604
8605  fail:
8606         intel_crtc->new_enabled = crtc->enabled;
8607         if (intel_crtc->new_enabled)
8608                 intel_crtc->new_config = &intel_crtc->config;
8609         else
8610                 intel_crtc->new_config = NULL;
8611 fail_unlock:
8612         if (ret == -EDEADLK) {
8613                 drm_modeset_backoff(ctx);
8614                 goto retry;
8615         }
8616
8617         return false;
8618 }
8619
8620 void intel_release_load_detect_pipe(struct drm_connector *connector,
8621                                     struct intel_load_detect_pipe *old)
8622 {
8623         struct intel_encoder *intel_encoder =
8624                 intel_attached_encoder(connector);
8625         struct drm_encoder *encoder = &intel_encoder->base;
8626         struct drm_crtc *crtc = encoder->crtc;
8627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8628
8629         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8630                       connector->base.id, connector->name,
8631                       encoder->base.id, encoder->name);
8632
8633         if (old->load_detect_temp) {
8634                 to_intel_connector(connector)->new_encoder = NULL;
8635                 intel_encoder->new_crtc = NULL;
8636                 intel_crtc->new_enabled = false;
8637                 intel_crtc->new_config = NULL;
8638                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8639
8640                 if (old->release_fb) {
8641                         drm_framebuffer_unregister_private(old->release_fb);
8642                         drm_framebuffer_unreference(old->release_fb);
8643                 }
8644
8645                 return;
8646         }
8647
8648         /* Switch crtc and encoder back off if necessary */
8649         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8650                 connector->funcs->dpms(connector, old->dpms_mode);
8651 }
8652
8653 static int i9xx_pll_refclk(struct drm_device *dev,
8654                            const struct intel_crtc_config *pipe_config)
8655 {
8656         struct drm_i915_private *dev_priv = dev->dev_private;
8657         u32 dpll = pipe_config->dpll_hw_state.dpll;
8658
8659         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8660                 return dev_priv->vbt.lvds_ssc_freq;
8661         else if (HAS_PCH_SPLIT(dev))
8662                 return 120000;
8663         else if (!IS_GEN2(dev))
8664                 return 96000;
8665         else
8666                 return 48000;
8667 }
8668
8669 /* Returns the clock of the currently programmed mode of the given pipe. */
8670 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8671                                 struct intel_crtc_config *pipe_config)
8672 {
8673         struct drm_device *dev = crtc->base.dev;
8674         struct drm_i915_private *dev_priv = dev->dev_private;
8675         int pipe = pipe_config->cpu_transcoder;
8676         u32 dpll = pipe_config->dpll_hw_state.dpll;
8677         u32 fp;
8678         intel_clock_t clock;
8679         int refclk = i9xx_pll_refclk(dev, pipe_config);
8680
8681         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8682                 fp = pipe_config->dpll_hw_state.fp0;
8683         else
8684                 fp = pipe_config->dpll_hw_state.fp1;
8685
8686         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8687         if (IS_PINEVIEW(dev)) {
8688                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8689                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8690         } else {
8691                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8692                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8693         }
8694
8695         if (!IS_GEN2(dev)) {
8696                 if (IS_PINEVIEW(dev))
8697                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8698                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8699                 else
8700                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8701                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8702
8703                 switch (dpll & DPLL_MODE_MASK) {
8704                 case DPLLB_MODE_DAC_SERIAL:
8705                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8706                                 5 : 10;
8707                         break;
8708                 case DPLLB_MODE_LVDS:
8709                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8710                                 7 : 14;
8711                         break;
8712                 default:
8713                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8714                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8715                         return;
8716                 }
8717
8718                 if (IS_PINEVIEW(dev))
8719                         pineview_clock(refclk, &clock);
8720                 else
8721                         i9xx_clock(refclk, &clock);
8722         } else {
8723                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8724                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8725
8726                 if (is_lvds) {
8727                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8728                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8729
8730                         if (lvds & LVDS_CLKB_POWER_UP)
8731                                 clock.p2 = 7;
8732                         else
8733                                 clock.p2 = 14;
8734                 } else {
8735                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8736                                 clock.p1 = 2;
8737                         else {
8738                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8739                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8740                         }
8741                         if (dpll & PLL_P2_DIVIDE_BY_4)
8742                                 clock.p2 = 4;
8743                         else
8744                                 clock.p2 = 2;
8745                 }
8746
8747                 i9xx_clock(refclk, &clock);
8748         }
8749
8750         /*
8751          * This value includes pixel_multiplier. We will use
8752          * port_clock to compute adjusted_mode.crtc_clock in the
8753          * encoder's get_config() function.
8754          */
8755         pipe_config->port_clock = clock.dot;
8756 }
8757
8758 int intel_dotclock_calculate(int link_freq,
8759                              const struct intel_link_m_n *m_n)
8760 {
8761         /*
8762          * The calculation for the data clock is:
8763          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8764          * But we want to avoid losing precison if possible, so:
8765          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8766          *
8767          * and the link clock is simpler:
8768          * link_clock = (m * link_clock) / n
8769          */
8770
8771         if (!m_n->link_n)
8772                 return 0;
8773
8774         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8775 }
8776
8777 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8778                                    struct intel_crtc_config *pipe_config)
8779 {
8780         struct drm_device *dev = crtc->base.dev;
8781
8782         /* read out port_clock from the DPLL */
8783         i9xx_crtc_clock_get(crtc, pipe_config);
8784
8785         /*
8786          * This value does not include pixel_multiplier.
8787          * We will check that port_clock and adjusted_mode.crtc_clock
8788          * agree once we know their relationship in the encoder's
8789          * get_config() function.
8790          */
8791         pipe_config->adjusted_mode.crtc_clock =
8792                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8793                                          &pipe_config->fdi_m_n);
8794 }
8795
8796 /** Returns the currently programmed mode of the given pipe. */
8797 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8798                                              struct drm_crtc *crtc)
8799 {
8800         struct drm_i915_private *dev_priv = dev->dev_private;
8801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8802         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8803         struct drm_display_mode *mode;
8804         struct intel_crtc_config pipe_config;
8805         int htot = I915_READ(HTOTAL(cpu_transcoder));
8806         int hsync = I915_READ(HSYNC(cpu_transcoder));
8807         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8808         int vsync = I915_READ(VSYNC(cpu_transcoder));
8809         enum pipe pipe = intel_crtc->pipe;
8810
8811         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8812         if (!mode)
8813                 return NULL;
8814
8815         /*
8816          * Construct a pipe_config sufficient for getting the clock info
8817          * back out of crtc_clock_get.
8818          *
8819          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8820          * to use a real value here instead.
8821          */
8822         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8823         pipe_config.pixel_multiplier = 1;
8824         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8825         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8826         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8827         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8828
8829         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8830         mode->hdisplay = (htot & 0xffff) + 1;
8831         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8832         mode->hsync_start = (hsync & 0xffff) + 1;
8833         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8834         mode->vdisplay = (vtot & 0xffff) + 1;
8835         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8836         mode->vsync_start = (vsync & 0xffff) + 1;
8837         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8838
8839         drm_mode_set_name(mode);
8840
8841         return mode;
8842 }
8843
8844 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8845 {
8846         struct drm_device *dev = crtc->dev;
8847         struct drm_i915_private *dev_priv = dev->dev_private;
8848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8849
8850         if (!HAS_GMCH_DISPLAY(dev))
8851                 return;
8852
8853         if (!dev_priv->lvds_downclock_avail)
8854                 return;
8855
8856         /*
8857          * Since this is called by a timer, we should never get here in
8858          * the manual case.
8859          */
8860         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8861                 int pipe = intel_crtc->pipe;
8862                 int dpll_reg = DPLL(pipe);
8863                 int dpll;
8864
8865                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8866
8867                 assert_panel_unlocked(dev_priv, pipe);
8868
8869                 dpll = I915_READ(dpll_reg);
8870                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8871                 I915_WRITE(dpll_reg, dpll);
8872                 intel_wait_for_vblank(dev, pipe);
8873                 dpll = I915_READ(dpll_reg);
8874                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8875                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8876         }
8877
8878 }
8879
8880 void intel_mark_busy(struct drm_device *dev)
8881 {
8882         struct drm_i915_private *dev_priv = dev->dev_private;
8883
8884         if (dev_priv->mm.busy)
8885                 return;
8886
8887         intel_runtime_pm_get(dev_priv);
8888         i915_update_gfx_val(dev_priv);
8889         dev_priv->mm.busy = true;
8890 }
8891
8892 void intel_mark_idle(struct drm_device *dev)
8893 {
8894         struct drm_i915_private *dev_priv = dev->dev_private;
8895         struct drm_crtc *crtc;
8896
8897         if (!dev_priv->mm.busy)
8898                 return;
8899
8900         dev_priv->mm.busy = false;
8901
8902         if (!i915.powersave)
8903                 goto out;
8904
8905         for_each_crtc(dev, crtc) {
8906                 if (!crtc->primary->fb)
8907                         continue;
8908
8909                 intel_decrease_pllclock(crtc);
8910         }
8911
8912         if (INTEL_INFO(dev)->gen >= 6)
8913                 gen6_rps_idle(dev->dev_private);
8914
8915 out:
8916         intel_runtime_pm_put(dev_priv);
8917 }
8918
8919 static void intel_crtc_destroy(struct drm_crtc *crtc)
8920 {
8921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8922         struct drm_device *dev = crtc->dev;
8923         struct intel_unpin_work *work;
8924
8925         spin_lock_irq(&dev->event_lock);
8926         work = intel_crtc->unpin_work;
8927         intel_crtc->unpin_work = NULL;
8928         spin_unlock_irq(&dev->event_lock);
8929
8930         if (work) {
8931                 cancel_work_sync(&work->work);
8932                 kfree(work);
8933         }
8934
8935         drm_crtc_cleanup(crtc);
8936
8937         kfree(intel_crtc);
8938 }
8939
8940 static void intel_unpin_work_fn(struct work_struct *__work)
8941 {
8942         struct intel_unpin_work *work =
8943                 container_of(__work, struct intel_unpin_work, work);
8944         struct drm_device *dev = work->crtc->dev;
8945         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8946
8947         mutex_lock(&dev->struct_mutex);
8948         intel_unpin_fb_obj(work->old_fb_obj);
8949         drm_gem_object_unreference(&work->pending_flip_obj->base);
8950         drm_gem_object_unreference(&work->old_fb_obj->base);
8951
8952         intel_update_fbc(dev);
8953         mutex_unlock(&dev->struct_mutex);
8954
8955         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8956
8957         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8958         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8959
8960         kfree(work);
8961 }
8962
8963 static void do_intel_finish_page_flip(struct drm_device *dev,
8964                                       struct drm_crtc *crtc)
8965 {
8966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8967         struct intel_unpin_work *work;
8968         unsigned long flags;
8969
8970         /* Ignore early vblank irqs */
8971         if (intel_crtc == NULL)
8972                 return;
8973
8974         /*
8975          * This is called both by irq handlers and the reset code (to complete
8976          * lost pageflips) so needs the full irqsave spinlocks.
8977          */
8978         spin_lock_irqsave(&dev->event_lock, flags);
8979         work = intel_crtc->unpin_work;
8980
8981         /* Ensure we don't miss a work->pending update ... */
8982         smp_rmb();
8983
8984         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8985                 spin_unlock_irqrestore(&dev->event_lock, flags);
8986                 return;
8987         }
8988
8989         page_flip_completed(intel_crtc);
8990
8991         spin_unlock_irqrestore(&dev->event_lock, flags);
8992 }
8993
8994 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8995 {
8996         struct drm_i915_private *dev_priv = dev->dev_private;
8997         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8998
8999         do_intel_finish_page_flip(dev, crtc);
9000 }
9001
9002 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9003 {
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9006
9007         do_intel_finish_page_flip(dev, crtc);
9008 }
9009
9010 /* Is 'a' after or equal to 'b'? */
9011 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9012 {
9013         return !((a - b) & 0x80000000);
9014 }
9015
9016 static bool page_flip_finished(struct intel_crtc *crtc)
9017 {
9018         struct drm_device *dev = crtc->base.dev;
9019         struct drm_i915_private *dev_priv = dev->dev_private;
9020
9021         /*
9022          * The relevant registers doen't exist on pre-ctg.
9023          * As the flip done interrupt doesn't trigger for mmio
9024          * flips on gmch platforms, a flip count check isn't
9025          * really needed there. But since ctg has the registers,
9026          * include it in the check anyway.
9027          */
9028         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9029                 return true;
9030
9031         /*
9032          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9033          * used the same base address. In that case the mmio flip might
9034          * have completed, but the CS hasn't even executed the flip yet.
9035          *
9036          * A flip count check isn't enough as the CS might have updated
9037          * the base address just after start of vblank, but before we
9038          * managed to process the interrupt. This means we'd complete the
9039          * CS flip too soon.
9040          *
9041          * Combining both checks should get us a good enough result. It may
9042          * still happen that the CS flip has been executed, but has not
9043          * yet actually completed. But in case the base address is the same
9044          * anyway, we don't really care.
9045          */
9046         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9047                 crtc->unpin_work->gtt_offset &&
9048                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9049                                     crtc->unpin_work->flip_count);
9050 }
9051
9052 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9053 {
9054         struct drm_i915_private *dev_priv = dev->dev_private;
9055         struct intel_crtc *intel_crtc =
9056                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9057         unsigned long flags;
9058
9059
9060         /*
9061          * This is called both by irq handlers and the reset code (to complete
9062          * lost pageflips) so needs the full irqsave spinlocks.
9063          *
9064          * NB: An MMIO update of the plane base pointer will also
9065          * generate a page-flip completion irq, i.e. every modeset
9066          * is also accompanied by a spurious intel_prepare_page_flip().
9067          */
9068         spin_lock_irqsave(&dev->event_lock, flags);
9069         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9070                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9071         spin_unlock_irqrestore(&dev->event_lock, flags);
9072 }
9073
9074 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9075 {
9076         /* Ensure that the work item is consistent when activating it ... */
9077         smp_wmb();
9078         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9079         /* and that it is marked active as soon as the irq could fire. */
9080         smp_wmb();
9081 }
9082
9083 static int intel_gen2_queue_flip(struct drm_device *dev,
9084                                  struct drm_crtc *crtc,
9085                                  struct drm_framebuffer *fb,
9086                                  struct drm_i915_gem_object *obj,
9087                                  struct intel_engine_cs *ring,
9088                                  uint32_t flags)
9089 {
9090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9091         u32 flip_mask;
9092         int ret;
9093
9094         ret = intel_ring_begin(ring, 6);
9095         if (ret)
9096                 return ret;
9097
9098         /* Can't queue multiple flips, so wait for the previous
9099          * one to finish before executing the next.
9100          */
9101         if (intel_crtc->plane)
9102                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9103         else
9104                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9105         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9106         intel_ring_emit(ring, MI_NOOP);
9107         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9108                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9109         intel_ring_emit(ring, fb->pitches[0]);
9110         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9111         intel_ring_emit(ring, 0); /* aux display base address, unused */
9112
9113         intel_mark_page_flip_active(intel_crtc);
9114         __intel_ring_advance(ring);
9115         return 0;
9116 }
9117
9118 static int intel_gen3_queue_flip(struct drm_device *dev,
9119                                  struct drm_crtc *crtc,
9120                                  struct drm_framebuffer *fb,
9121                                  struct drm_i915_gem_object *obj,
9122                                  struct intel_engine_cs *ring,
9123                                  uint32_t flags)
9124 {
9125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9126         u32 flip_mask;
9127         int ret;
9128
9129         ret = intel_ring_begin(ring, 6);
9130         if (ret)
9131                 return ret;
9132
9133         if (intel_crtc->plane)
9134                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9135         else
9136                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9137         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9138         intel_ring_emit(ring, MI_NOOP);
9139         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9140                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9141         intel_ring_emit(ring, fb->pitches[0]);
9142         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9143         intel_ring_emit(ring, MI_NOOP);
9144
9145         intel_mark_page_flip_active(intel_crtc);
9146         __intel_ring_advance(ring);
9147         return 0;
9148 }
9149
9150 static int intel_gen4_queue_flip(struct drm_device *dev,
9151                                  struct drm_crtc *crtc,
9152                                  struct drm_framebuffer *fb,
9153                                  struct drm_i915_gem_object *obj,
9154                                  struct intel_engine_cs *ring,
9155                                  uint32_t flags)
9156 {
9157         struct drm_i915_private *dev_priv = dev->dev_private;
9158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9159         uint32_t pf, pipesrc;
9160         int ret;
9161
9162         ret = intel_ring_begin(ring, 4);
9163         if (ret)
9164                 return ret;
9165
9166         /* i965+ uses the linear or tiled offsets from the
9167          * Display Registers (which do not change across a page-flip)
9168          * so we need only reprogram the base address.
9169          */
9170         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9171                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9172         intel_ring_emit(ring, fb->pitches[0]);
9173         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9174                         obj->tiling_mode);
9175
9176         /* XXX Enabling the panel-fitter across page-flip is so far
9177          * untested on non-native modes, so ignore it for now.
9178          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9179          */
9180         pf = 0;
9181         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9182         intel_ring_emit(ring, pf | pipesrc);
9183
9184         intel_mark_page_flip_active(intel_crtc);
9185         __intel_ring_advance(ring);
9186         return 0;
9187 }
9188
9189 static int intel_gen6_queue_flip(struct drm_device *dev,
9190                                  struct drm_crtc *crtc,
9191                                  struct drm_framebuffer *fb,
9192                                  struct drm_i915_gem_object *obj,
9193                                  struct intel_engine_cs *ring,
9194                                  uint32_t flags)
9195 {
9196         struct drm_i915_private *dev_priv = dev->dev_private;
9197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9198         uint32_t pf, pipesrc;
9199         int ret;
9200
9201         ret = intel_ring_begin(ring, 4);
9202         if (ret)
9203                 return ret;
9204
9205         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9206                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9207         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9208         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9209
9210         /* Contrary to the suggestions in the documentation,
9211          * "Enable Panel Fitter" does not seem to be required when page
9212          * flipping with a non-native mode, and worse causes a normal
9213          * modeset to fail.
9214          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9215          */
9216         pf = 0;
9217         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9218         intel_ring_emit(ring, pf | pipesrc);
9219
9220         intel_mark_page_flip_active(intel_crtc);
9221         __intel_ring_advance(ring);
9222         return 0;
9223 }
9224
9225 static int intel_gen7_queue_flip(struct drm_device *dev,
9226                                  struct drm_crtc *crtc,
9227                                  struct drm_framebuffer *fb,
9228                                  struct drm_i915_gem_object *obj,
9229                                  struct intel_engine_cs *ring,
9230                                  uint32_t flags)
9231 {
9232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9233         uint32_t plane_bit = 0;
9234         int len, ret;
9235
9236         switch (intel_crtc->plane) {
9237         case PLANE_A:
9238                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9239                 break;
9240         case PLANE_B:
9241                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9242                 break;
9243         case PLANE_C:
9244                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9245                 break;
9246         default:
9247                 WARN_ONCE(1, "unknown plane in flip command\n");
9248                 return -ENODEV;
9249         }
9250
9251         len = 4;
9252         if (ring->id == RCS) {
9253                 len += 6;
9254                 /*
9255                  * On Gen 8, SRM is now taking an extra dword to accommodate
9256                  * 48bits addresses, and we need a NOOP for the batch size to
9257                  * stay even.
9258                  */
9259                 if (IS_GEN8(dev))
9260                         len += 2;
9261         }
9262
9263         /*
9264          * BSpec MI_DISPLAY_FLIP for IVB:
9265          * "The full packet must be contained within the same cache line."
9266          *
9267          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9268          * cacheline, if we ever start emitting more commands before
9269          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9270          * then do the cacheline alignment, and finally emit the
9271          * MI_DISPLAY_FLIP.
9272          */
9273         ret = intel_ring_cacheline_align(ring);
9274         if (ret)
9275                 return ret;
9276
9277         ret = intel_ring_begin(ring, len);
9278         if (ret)
9279                 return ret;
9280
9281         /* Unmask the flip-done completion message. Note that the bspec says that
9282          * we should do this for both the BCS and RCS, and that we must not unmask
9283          * more than one flip event at any time (or ensure that one flip message
9284          * can be sent by waiting for flip-done prior to queueing new flips).
9285          * Experimentation says that BCS works despite DERRMR masking all
9286          * flip-done completion events and that unmasking all planes at once
9287          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9288          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9289          */
9290         if (ring->id == RCS) {
9291                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9292                 intel_ring_emit(ring, DERRMR);
9293                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9294                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9295                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9296                 if (IS_GEN8(dev))
9297                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9298                                               MI_SRM_LRM_GLOBAL_GTT);
9299                 else
9300                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9301                                               MI_SRM_LRM_GLOBAL_GTT);
9302                 intel_ring_emit(ring, DERRMR);
9303                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9304                 if (IS_GEN8(dev)) {
9305                         intel_ring_emit(ring, 0);
9306                         intel_ring_emit(ring, MI_NOOP);
9307                 }
9308         }
9309
9310         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9311         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9312         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9313         intel_ring_emit(ring, (MI_NOOP));
9314
9315         intel_mark_page_flip_active(intel_crtc);
9316         __intel_ring_advance(ring);
9317         return 0;
9318 }
9319
9320 static bool use_mmio_flip(struct intel_engine_cs *ring,
9321                           struct drm_i915_gem_object *obj)
9322 {
9323         /*
9324          * This is not being used for older platforms, because
9325          * non-availability of flip done interrupt forces us to use
9326          * CS flips. Older platforms derive flip done using some clever
9327          * tricks involving the flip_pending status bits and vblank irqs.
9328          * So using MMIO flips there would disrupt this mechanism.
9329          */
9330
9331         if (ring == NULL)
9332                 return true;
9333
9334         if (INTEL_INFO(ring->dev)->gen < 5)
9335                 return false;
9336
9337         if (i915.use_mmio_flip < 0)
9338                 return false;
9339         else if (i915.use_mmio_flip > 0)
9340                 return true;
9341         else if (i915.enable_execlists)
9342                 return true;
9343         else
9344                 return ring != obj->ring;
9345 }
9346
9347 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9348 {
9349         struct drm_device *dev = intel_crtc->base.dev;
9350         struct drm_i915_private *dev_priv = dev->dev_private;
9351         struct intel_framebuffer *intel_fb =
9352                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9353         struct drm_i915_gem_object *obj = intel_fb->obj;
9354         u32 dspcntr;
9355         u32 reg;
9356
9357         intel_mark_page_flip_active(intel_crtc);
9358
9359         reg = DSPCNTR(intel_crtc->plane);
9360         dspcntr = I915_READ(reg);
9361
9362         if (obj->tiling_mode != I915_TILING_NONE)
9363                 dspcntr |= DISPPLANE_TILED;
9364         else
9365                 dspcntr &= ~DISPPLANE_TILED;
9366
9367         I915_WRITE(reg, dspcntr);
9368
9369         I915_WRITE(DSPSURF(intel_crtc->plane),
9370                    intel_crtc->unpin_work->gtt_offset);
9371         POSTING_READ(DSPSURF(intel_crtc->plane));
9372 }
9373
9374 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9375 {
9376         struct intel_engine_cs *ring;
9377         int ret;
9378
9379         lockdep_assert_held(&obj->base.dev->struct_mutex);
9380
9381         if (!obj->last_write_seqno)
9382                 return 0;
9383
9384         ring = obj->ring;
9385
9386         if (i915_seqno_passed(ring->get_seqno(ring, true),
9387                               obj->last_write_seqno))
9388                 return 0;
9389
9390         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9391         if (ret)
9392                 return ret;
9393
9394         if (WARN_ON(!ring->irq_get(ring)))
9395                 return 0;
9396
9397         return 1;
9398 }
9399
9400 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9401 {
9402         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9403         struct intel_crtc *intel_crtc;
9404         unsigned long irq_flags;
9405         u32 seqno;
9406
9407         seqno = ring->get_seqno(ring, false);
9408
9409         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9410         for_each_intel_crtc(ring->dev, intel_crtc) {
9411                 struct intel_mmio_flip *mmio_flip;
9412
9413                 mmio_flip = &intel_crtc->mmio_flip;
9414                 if (mmio_flip->seqno == 0)
9415                         continue;
9416
9417                 if (ring->id != mmio_flip->ring_id)
9418                         continue;
9419
9420                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9421                         intel_do_mmio_flip(intel_crtc);
9422                         mmio_flip->seqno = 0;
9423                         ring->irq_put(ring);
9424                 }
9425         }
9426         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9427 }
9428
9429 static int intel_queue_mmio_flip(struct drm_device *dev,
9430                                  struct drm_crtc *crtc,
9431                                  struct drm_framebuffer *fb,
9432                                  struct drm_i915_gem_object *obj,
9433                                  struct intel_engine_cs *ring,
9434                                  uint32_t flags)
9435 {
9436         struct drm_i915_private *dev_priv = dev->dev_private;
9437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9438         int ret;
9439
9440         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9441                 return -EBUSY;
9442
9443         ret = intel_postpone_flip(obj);
9444         if (ret < 0)
9445                 return ret;
9446         if (ret == 0) {
9447                 intel_do_mmio_flip(intel_crtc);
9448                 return 0;
9449         }
9450
9451         spin_lock_irq(&dev_priv->mmio_flip_lock);
9452         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9453         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9454         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9455
9456         /*
9457          * Double check to catch cases where irq fired before
9458          * mmio flip data was ready
9459          */
9460         intel_notify_mmio_flip(obj->ring);
9461         return 0;
9462 }
9463
9464 static int intel_default_queue_flip(struct drm_device *dev,
9465                                     struct drm_crtc *crtc,
9466                                     struct drm_framebuffer *fb,
9467                                     struct drm_i915_gem_object *obj,
9468                                     struct intel_engine_cs *ring,
9469                                     uint32_t flags)
9470 {
9471         return -ENODEV;
9472 }
9473
9474 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9475                                          struct drm_crtc *crtc)
9476 {
9477         struct drm_i915_private *dev_priv = dev->dev_private;
9478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9479         struct intel_unpin_work *work = intel_crtc->unpin_work;
9480         u32 addr;
9481
9482         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9483                 return true;
9484
9485         if (!work->enable_stall_check)
9486                 return false;
9487
9488         if (work->flip_ready_vblank == 0) {
9489                 if (work->flip_queued_ring &&
9490                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9491                                        work->flip_queued_seqno))
9492                         return false;
9493
9494                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9495         }
9496
9497         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9498                 return false;
9499
9500         /* Potential stall - if we see that the flip has happened,
9501          * assume a missed interrupt. */
9502         if (INTEL_INFO(dev)->gen >= 4)
9503                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9504         else
9505                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9506
9507         /* There is a potential issue here with a false positive after a flip
9508          * to the same address. We could address this by checking for a
9509          * non-incrementing frame counter.
9510          */
9511         return addr == work->gtt_offset;
9512 }
9513
9514 void intel_check_page_flip(struct drm_device *dev, int pipe)
9515 {
9516         struct drm_i915_private *dev_priv = dev->dev_private;
9517         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9519
9520         WARN_ON(!in_irq());
9521
9522         if (crtc == NULL)
9523                 return;
9524
9525         spin_lock(&dev->event_lock);
9526         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9527                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9528                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9529                 page_flip_completed(intel_crtc);
9530         }
9531         spin_unlock(&dev->event_lock);
9532 }
9533
9534 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9535                                 struct drm_framebuffer *fb,
9536                                 struct drm_pending_vblank_event *event,
9537                                 uint32_t page_flip_flags)
9538 {
9539         struct drm_device *dev = crtc->dev;
9540         struct drm_i915_private *dev_priv = dev->dev_private;
9541         struct drm_framebuffer *old_fb = crtc->primary->fb;
9542         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9544         enum pipe pipe = intel_crtc->pipe;
9545         struct intel_unpin_work *work;
9546         struct intel_engine_cs *ring;
9547         int ret;
9548
9549         /*
9550          * drm_mode_page_flip_ioctl() should already catch this, but double
9551          * check to be safe.  In the future we may enable pageflipping from
9552          * a disabled primary plane.
9553          */
9554         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9555                 return -EBUSY;
9556
9557         /* Can't change pixel format via MI display flips. */
9558         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9559                 return -EINVAL;
9560
9561         /*
9562          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9563          * Note that pitch changes could also affect these register.
9564          */
9565         if (INTEL_INFO(dev)->gen > 3 &&
9566             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9567              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9568                 return -EINVAL;
9569
9570         if (i915_terminally_wedged(&dev_priv->gpu_error))
9571                 goto out_hang;
9572
9573         work = kzalloc(sizeof(*work), GFP_KERNEL);
9574         if (work == NULL)
9575                 return -ENOMEM;
9576
9577         work->event = event;
9578         work->crtc = crtc;
9579         work->old_fb_obj = intel_fb_obj(old_fb);
9580         INIT_WORK(&work->work, intel_unpin_work_fn);
9581
9582         ret = drm_crtc_vblank_get(crtc);
9583         if (ret)
9584                 goto free_work;
9585
9586         /* We borrow the event spin lock for protecting unpin_work */
9587         spin_lock_irq(&dev->event_lock);
9588         if (intel_crtc->unpin_work) {
9589                 /* Before declaring the flip queue wedged, check if
9590                  * the hardware completed the operation behind our backs.
9591                  */
9592                 if (__intel_pageflip_stall_check(dev, crtc)) {
9593                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9594                         page_flip_completed(intel_crtc);
9595                 } else {
9596                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9597                         spin_unlock_irq(&dev->event_lock);
9598
9599                         drm_crtc_vblank_put(crtc);
9600                         kfree(work);
9601                         return -EBUSY;
9602                 }
9603         }
9604         intel_crtc->unpin_work = work;
9605         spin_unlock_irq(&dev->event_lock);
9606
9607         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9608                 flush_workqueue(dev_priv->wq);
9609
9610         ret = i915_mutex_lock_interruptible(dev);
9611         if (ret)
9612                 goto cleanup;
9613
9614         /* Reference the objects for the scheduled work. */
9615         drm_gem_object_reference(&work->old_fb_obj->base);
9616         drm_gem_object_reference(&obj->base);
9617
9618         crtc->primary->fb = fb;
9619
9620         work->pending_flip_obj = obj;
9621
9622         atomic_inc(&intel_crtc->unpin_work_count);
9623         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9624
9625         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9626                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9627
9628         if (IS_VALLEYVIEW(dev)) {
9629                 ring = &dev_priv->ring[BCS];
9630                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9631                         /* vlv: DISPLAY_FLIP fails to change tiling */
9632                         ring = NULL;
9633         } else if (IS_IVYBRIDGE(dev)) {
9634                 ring = &dev_priv->ring[BCS];
9635         } else if (INTEL_INFO(dev)->gen >= 7) {
9636                 ring = obj->ring;
9637                 if (ring == NULL || ring->id != RCS)
9638                         ring = &dev_priv->ring[BCS];
9639         } else {
9640                 ring = &dev_priv->ring[RCS];
9641         }
9642
9643         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9644         if (ret)
9645                 goto cleanup_pending;
9646
9647         work->gtt_offset =
9648                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9649
9650         if (use_mmio_flip(ring, obj)) {
9651                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9652                                             page_flip_flags);
9653                 if (ret)
9654                         goto cleanup_unpin;
9655
9656                 work->flip_queued_seqno = obj->last_write_seqno;
9657                 work->flip_queued_ring = obj->ring;
9658         } else {
9659                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9660                                                    page_flip_flags);
9661                 if (ret)
9662                         goto cleanup_unpin;
9663
9664                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9665                 work->flip_queued_ring = ring;
9666         }
9667
9668         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9669         work->enable_stall_check = true;
9670
9671         i915_gem_track_fb(work->old_fb_obj, obj,
9672                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9673
9674         intel_disable_fbc(dev);
9675         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9676         mutex_unlock(&dev->struct_mutex);
9677
9678         trace_i915_flip_request(intel_crtc->plane, obj);
9679
9680         return 0;
9681
9682 cleanup_unpin:
9683         intel_unpin_fb_obj(obj);
9684 cleanup_pending:
9685         atomic_dec(&intel_crtc->unpin_work_count);
9686         crtc->primary->fb = old_fb;
9687         drm_gem_object_unreference(&work->old_fb_obj->base);
9688         drm_gem_object_unreference(&obj->base);
9689         mutex_unlock(&dev->struct_mutex);
9690
9691 cleanup:
9692         spin_lock_irq(&dev->event_lock);
9693         intel_crtc->unpin_work = NULL;
9694         spin_unlock_irq(&dev->event_lock);
9695
9696         drm_crtc_vblank_put(crtc);
9697 free_work:
9698         kfree(work);
9699
9700         if (ret == -EIO) {
9701 out_hang:
9702                 intel_crtc_wait_for_pending_flips(crtc);
9703                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9704                 if (ret == 0 && event) {
9705                         spin_lock_irq(&dev->event_lock);
9706                         drm_send_vblank_event(dev, pipe, event);
9707                         spin_unlock_irq(&dev->event_lock);
9708                 }
9709         }
9710         return ret;
9711 }
9712
9713 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9714         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9715         .load_lut = intel_crtc_load_lut,
9716 };
9717
9718 /**
9719  * intel_modeset_update_staged_output_state
9720  *
9721  * Updates the staged output configuration state, e.g. after we've read out the
9722  * current hw state.
9723  */
9724 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9725 {
9726         struct intel_crtc *crtc;
9727         struct intel_encoder *encoder;
9728         struct intel_connector *connector;
9729
9730         list_for_each_entry(connector, &dev->mode_config.connector_list,
9731                             base.head) {
9732                 connector->new_encoder =
9733                         to_intel_encoder(connector->base.encoder);
9734         }
9735
9736         for_each_intel_encoder(dev, encoder) {
9737                 encoder->new_crtc =
9738                         to_intel_crtc(encoder->base.crtc);
9739         }
9740
9741         for_each_intel_crtc(dev, crtc) {
9742                 crtc->new_enabled = crtc->base.enabled;
9743
9744                 if (crtc->new_enabled)
9745                         crtc->new_config = &crtc->config;
9746                 else
9747                         crtc->new_config = NULL;
9748         }
9749 }
9750
9751 /**
9752  * intel_modeset_commit_output_state
9753  *
9754  * This function copies the stage display pipe configuration to the real one.
9755  */
9756 static void intel_modeset_commit_output_state(struct drm_device *dev)
9757 {
9758         struct intel_crtc *crtc;
9759         struct intel_encoder *encoder;
9760         struct intel_connector *connector;
9761
9762         list_for_each_entry(connector, &dev->mode_config.connector_list,
9763                             base.head) {
9764                 connector->base.encoder = &connector->new_encoder->base;
9765         }
9766
9767         for_each_intel_encoder(dev, encoder) {
9768                 encoder->base.crtc = &encoder->new_crtc->base;
9769         }
9770
9771         for_each_intel_crtc(dev, crtc) {
9772                 crtc->base.enabled = crtc->new_enabled;
9773         }
9774 }
9775
9776 static void
9777 connected_sink_compute_bpp(struct intel_connector *connector,
9778                            struct intel_crtc_config *pipe_config)
9779 {
9780         int bpp = pipe_config->pipe_bpp;
9781
9782         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9783                 connector->base.base.id,
9784                 connector->base.name);
9785
9786         /* Don't use an invalid EDID bpc value */
9787         if (connector->base.display_info.bpc &&
9788             connector->base.display_info.bpc * 3 < bpp) {
9789                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9790                               bpp, connector->base.display_info.bpc*3);
9791                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9792         }
9793
9794         /* Clamp bpp to 8 on screens without EDID 1.4 */
9795         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9796                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9797                               bpp);
9798                 pipe_config->pipe_bpp = 24;
9799         }
9800 }
9801
9802 static int
9803 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9804                           struct drm_framebuffer *fb,
9805                           struct intel_crtc_config *pipe_config)
9806 {
9807         struct drm_device *dev = crtc->base.dev;
9808         struct intel_connector *connector;
9809         int bpp;
9810
9811         switch (fb->pixel_format) {
9812         case DRM_FORMAT_C8:
9813                 bpp = 8*3; /* since we go through a colormap */
9814                 break;
9815         case DRM_FORMAT_XRGB1555:
9816         case DRM_FORMAT_ARGB1555:
9817                 /* checked in intel_framebuffer_init already */
9818                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9819                         return -EINVAL;
9820         case DRM_FORMAT_RGB565:
9821                 bpp = 6*3; /* min is 18bpp */
9822                 break;
9823         case DRM_FORMAT_XBGR8888:
9824         case DRM_FORMAT_ABGR8888:
9825                 /* checked in intel_framebuffer_init already */
9826                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9827                         return -EINVAL;
9828         case DRM_FORMAT_XRGB8888:
9829         case DRM_FORMAT_ARGB8888:
9830                 bpp = 8*3;
9831                 break;
9832         case DRM_FORMAT_XRGB2101010:
9833         case DRM_FORMAT_ARGB2101010:
9834         case DRM_FORMAT_XBGR2101010:
9835         case DRM_FORMAT_ABGR2101010:
9836                 /* checked in intel_framebuffer_init already */
9837                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9838                         return -EINVAL;
9839                 bpp = 10*3;
9840                 break;
9841         /* TODO: gen4+ supports 16 bpc floating point, too. */
9842         default:
9843                 DRM_DEBUG_KMS("unsupported depth\n");
9844                 return -EINVAL;
9845         }
9846
9847         pipe_config->pipe_bpp = bpp;
9848
9849         /* Clamp display bpp to EDID value */
9850         list_for_each_entry(connector, &dev->mode_config.connector_list,
9851                             base.head) {
9852                 if (!connector->new_encoder ||
9853                     connector->new_encoder->new_crtc != crtc)
9854                         continue;
9855
9856                 connected_sink_compute_bpp(connector, pipe_config);
9857         }
9858
9859         return bpp;
9860 }
9861
9862 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9863 {
9864         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9865                         "type: 0x%x flags: 0x%x\n",
9866                 mode->crtc_clock,
9867                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9868                 mode->crtc_hsync_end, mode->crtc_htotal,
9869                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9870                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9871 }
9872
9873 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9874                                    struct intel_crtc_config *pipe_config,
9875                                    const char *context)
9876 {
9877         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9878                       context, pipe_name(crtc->pipe));
9879
9880         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9881         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9882                       pipe_config->pipe_bpp, pipe_config->dither);
9883         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9884                       pipe_config->has_pch_encoder,
9885                       pipe_config->fdi_lanes,
9886                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9887                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9888                       pipe_config->fdi_m_n.tu);
9889         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9890                       pipe_config->has_dp_encoder,
9891                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9892                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9893                       pipe_config->dp_m_n.tu);
9894
9895         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9896                       pipe_config->has_dp_encoder,
9897                       pipe_config->dp_m2_n2.gmch_m,
9898                       pipe_config->dp_m2_n2.gmch_n,
9899                       pipe_config->dp_m2_n2.link_m,
9900                       pipe_config->dp_m2_n2.link_n,
9901                       pipe_config->dp_m2_n2.tu);
9902
9903         DRM_DEBUG_KMS("requested mode:\n");
9904         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9905         DRM_DEBUG_KMS("adjusted mode:\n");
9906         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9907         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9908         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9909         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9910                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9911         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9912                       pipe_config->gmch_pfit.control,
9913                       pipe_config->gmch_pfit.pgm_ratios,
9914                       pipe_config->gmch_pfit.lvds_border_bits);
9915         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9916                       pipe_config->pch_pfit.pos,
9917                       pipe_config->pch_pfit.size,
9918                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9919         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9920         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9921 }
9922
9923 static bool encoders_cloneable(const struct intel_encoder *a,
9924                                const struct intel_encoder *b)
9925 {
9926         /* masks could be asymmetric, so check both ways */
9927         return a == b || (a->cloneable & (1 << b->type) &&
9928                           b->cloneable & (1 << a->type));
9929 }
9930
9931 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9932                                          struct intel_encoder *encoder)
9933 {
9934         struct drm_device *dev = crtc->base.dev;
9935         struct intel_encoder *source_encoder;
9936
9937         for_each_intel_encoder(dev, source_encoder) {
9938                 if (source_encoder->new_crtc != crtc)
9939                         continue;
9940
9941                 if (!encoders_cloneable(encoder, source_encoder))
9942                         return false;
9943         }
9944
9945         return true;
9946 }
9947
9948 static bool check_encoder_cloning(struct intel_crtc *crtc)
9949 {
9950         struct drm_device *dev = crtc->base.dev;
9951         struct intel_encoder *encoder;
9952
9953         for_each_intel_encoder(dev, encoder) {
9954                 if (encoder->new_crtc != crtc)
9955                         continue;
9956
9957                 if (!check_single_encoder_cloning(crtc, encoder))
9958                         return false;
9959         }
9960
9961         return true;
9962 }
9963
9964 static struct intel_crtc_config *
9965 intel_modeset_pipe_config(struct drm_crtc *crtc,
9966                           struct drm_framebuffer *fb,
9967                           struct drm_display_mode *mode)
9968 {
9969         struct drm_device *dev = crtc->dev;
9970         struct intel_encoder *encoder;
9971         struct intel_crtc_config *pipe_config;
9972         int plane_bpp, ret = -EINVAL;
9973         bool retry = true;
9974
9975         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9976                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9977                 return ERR_PTR(-EINVAL);
9978         }
9979
9980         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9981         if (!pipe_config)
9982                 return ERR_PTR(-ENOMEM);
9983
9984         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9985         drm_mode_copy(&pipe_config->requested_mode, mode);
9986
9987         pipe_config->cpu_transcoder =
9988                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9989         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9990
9991         /*
9992          * Sanitize sync polarity flags based on requested ones. If neither
9993          * positive or negative polarity is requested, treat this as meaning
9994          * negative polarity.
9995          */
9996         if (!(pipe_config->adjusted_mode.flags &
9997               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9998                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9999
10000         if (!(pipe_config->adjusted_mode.flags &
10001               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10002                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10003
10004         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10005          * plane pixel format and any sink constraints into account. Returns the
10006          * source plane bpp so that dithering can be selected on mismatches
10007          * after encoders and crtc also have had their say. */
10008         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10009                                               fb, pipe_config);
10010         if (plane_bpp < 0)
10011                 goto fail;
10012
10013         /*
10014          * Determine the real pipe dimensions. Note that stereo modes can
10015          * increase the actual pipe size due to the frame doubling and
10016          * insertion of additional space for blanks between the frame. This
10017          * is stored in the crtc timings. We use the requested mode to do this
10018          * computation to clearly distinguish it from the adjusted mode, which
10019          * can be changed by the connectors in the below retry loop.
10020          */
10021         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10022         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10023         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10024
10025 encoder_retry:
10026         /* Ensure the port clock defaults are reset when retrying. */
10027         pipe_config->port_clock = 0;
10028         pipe_config->pixel_multiplier = 1;
10029
10030         /* Fill in default crtc timings, allow encoders to overwrite them. */
10031         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10032
10033         /* Pass our mode to the connectors and the CRTC to give them a chance to
10034          * adjust it according to limitations or connector properties, and also
10035          * a chance to reject the mode entirely.
10036          */
10037         for_each_intel_encoder(dev, encoder) {
10038
10039                 if (&encoder->new_crtc->base != crtc)
10040                         continue;
10041
10042                 if (!(encoder->compute_config(encoder, pipe_config))) {
10043                         DRM_DEBUG_KMS("Encoder config failure\n");
10044                         goto fail;
10045                 }
10046         }
10047
10048         /* Set default port clock if not overwritten by the encoder. Needs to be
10049          * done afterwards in case the encoder adjusts the mode. */
10050         if (!pipe_config->port_clock)
10051                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10052                         * pipe_config->pixel_multiplier;
10053
10054         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10055         if (ret < 0) {
10056                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10057                 goto fail;
10058         }
10059
10060         if (ret == RETRY) {
10061                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10062                         ret = -EINVAL;
10063                         goto fail;
10064                 }
10065
10066                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10067                 retry = false;
10068                 goto encoder_retry;
10069         }
10070
10071         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10072         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10073                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10074
10075         return pipe_config;
10076 fail:
10077         kfree(pipe_config);
10078         return ERR_PTR(ret);
10079 }
10080
10081 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10082  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10083 static void
10084 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10085                              unsigned *prepare_pipes, unsigned *disable_pipes)
10086 {
10087         struct intel_crtc *intel_crtc;
10088         struct drm_device *dev = crtc->dev;
10089         struct intel_encoder *encoder;
10090         struct intel_connector *connector;
10091         struct drm_crtc *tmp_crtc;
10092
10093         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10094
10095         /* Check which crtcs have changed outputs connected to them, these need
10096          * to be part of the prepare_pipes mask. We don't (yet) support global
10097          * modeset across multiple crtcs, so modeset_pipes will only have one
10098          * bit set at most. */
10099         list_for_each_entry(connector, &dev->mode_config.connector_list,
10100                             base.head) {
10101                 if (connector->base.encoder == &connector->new_encoder->base)
10102                         continue;
10103
10104                 if (connector->base.encoder) {
10105                         tmp_crtc = connector->base.encoder->crtc;
10106
10107                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10108                 }
10109
10110                 if (connector->new_encoder)
10111                         *prepare_pipes |=
10112                                 1 << connector->new_encoder->new_crtc->pipe;
10113         }
10114
10115         for_each_intel_encoder(dev, encoder) {
10116                 if (encoder->base.crtc == &encoder->new_crtc->base)
10117                         continue;
10118
10119                 if (encoder->base.crtc) {
10120                         tmp_crtc = encoder->base.crtc;
10121
10122                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10123                 }
10124
10125                 if (encoder->new_crtc)
10126                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10127         }
10128
10129         /* Check for pipes that will be enabled/disabled ... */
10130         for_each_intel_crtc(dev, intel_crtc) {
10131                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10132                         continue;
10133
10134                 if (!intel_crtc->new_enabled)
10135                         *disable_pipes |= 1 << intel_crtc->pipe;
10136                 else
10137                         *prepare_pipes |= 1 << intel_crtc->pipe;
10138         }
10139
10140
10141         /* set_mode is also used to update properties on life display pipes. */
10142         intel_crtc = to_intel_crtc(crtc);
10143         if (intel_crtc->new_enabled)
10144                 *prepare_pipes |= 1 << intel_crtc->pipe;
10145
10146         /*
10147          * For simplicity do a full modeset on any pipe where the output routing
10148          * changed. We could be more clever, but that would require us to be
10149          * more careful with calling the relevant encoder->mode_set functions.
10150          */
10151         if (*prepare_pipes)
10152                 *modeset_pipes = *prepare_pipes;
10153
10154         /* ... and mask these out. */
10155         *modeset_pipes &= ~(*disable_pipes);
10156         *prepare_pipes &= ~(*disable_pipes);
10157
10158         /*
10159          * HACK: We don't (yet) fully support global modesets. intel_set_config
10160          * obies this rule, but the modeset restore mode of
10161          * intel_modeset_setup_hw_state does not.
10162          */
10163         *modeset_pipes &= 1 << intel_crtc->pipe;
10164         *prepare_pipes &= 1 << intel_crtc->pipe;
10165
10166         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10167                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10168 }
10169
10170 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10171 {
10172         struct drm_encoder *encoder;
10173         struct drm_device *dev = crtc->dev;
10174
10175         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10176                 if (encoder->crtc == crtc)
10177                         return true;
10178
10179         return false;
10180 }
10181
10182 static void
10183 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10184 {
10185         struct intel_encoder *intel_encoder;
10186         struct intel_crtc *intel_crtc;
10187         struct drm_connector *connector;
10188
10189         for_each_intel_encoder(dev, intel_encoder) {
10190                 if (!intel_encoder->base.crtc)
10191                         continue;
10192
10193                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10194
10195                 if (prepare_pipes & (1 << intel_crtc->pipe))
10196                         intel_encoder->connectors_active = false;
10197         }
10198
10199         intel_modeset_commit_output_state(dev);
10200
10201         /* Double check state. */
10202         for_each_intel_crtc(dev, intel_crtc) {
10203                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10204                 WARN_ON(intel_crtc->new_config &&
10205                         intel_crtc->new_config != &intel_crtc->config);
10206                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10207         }
10208
10209         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10210                 if (!connector->encoder || !connector->encoder->crtc)
10211                         continue;
10212
10213                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10214
10215                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10216                         struct drm_property *dpms_property =
10217                                 dev->mode_config.dpms_property;
10218
10219                         connector->dpms = DRM_MODE_DPMS_ON;
10220                         drm_object_property_set_value(&connector->base,
10221                                                          dpms_property,
10222                                                          DRM_MODE_DPMS_ON);
10223
10224                         intel_encoder = to_intel_encoder(connector->encoder);
10225                         intel_encoder->connectors_active = true;
10226                 }
10227         }
10228
10229 }
10230
10231 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10232 {
10233         int diff;
10234
10235         if (clock1 == clock2)
10236                 return true;
10237
10238         if (!clock1 || !clock2)
10239                 return false;
10240
10241         diff = abs(clock1 - clock2);
10242
10243         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10244                 return true;
10245
10246         return false;
10247 }
10248
10249 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10250         list_for_each_entry((intel_crtc), \
10251                             &(dev)->mode_config.crtc_list, \
10252                             base.head) \
10253                 if (mask & (1 <<(intel_crtc)->pipe))
10254
10255 static bool
10256 intel_pipe_config_compare(struct drm_device *dev,
10257                           struct intel_crtc_config *current_config,
10258                           struct intel_crtc_config *pipe_config)
10259 {
10260 #define PIPE_CONF_CHECK_X(name) \
10261         if (current_config->name != pipe_config->name) { \
10262                 DRM_ERROR("mismatch in " #name " " \
10263                           "(expected 0x%08x, found 0x%08x)\n", \
10264                           current_config->name, \
10265                           pipe_config->name); \
10266                 return false; \
10267         }
10268
10269 #define PIPE_CONF_CHECK_I(name) \
10270         if (current_config->name != pipe_config->name) { \
10271                 DRM_ERROR("mismatch in " #name " " \
10272                           "(expected %i, found %i)\n", \
10273                           current_config->name, \
10274                           pipe_config->name); \
10275                 return false; \
10276         }
10277
10278 /* This is required for BDW+ where there is only one set of registers for
10279  * switching between high and low RR.
10280  * This macro can be used whenever a comparison has to be made between one
10281  * hw state and multiple sw state variables.
10282  */
10283 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10284         if ((current_config->name != pipe_config->name) && \
10285                 (current_config->alt_name != pipe_config->name)) { \
10286                         DRM_ERROR("mismatch in " #name " " \
10287                                   "(expected %i or %i, found %i)\n", \
10288                                   current_config->name, \
10289                                   current_config->alt_name, \
10290                                   pipe_config->name); \
10291                         return false; \
10292         }
10293
10294 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10295         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10296                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10297                           "(expected %i, found %i)\n", \
10298                           current_config->name & (mask), \
10299                           pipe_config->name & (mask)); \
10300                 return false; \
10301         }
10302
10303 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10304         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10305                 DRM_ERROR("mismatch in " #name " " \
10306                           "(expected %i, found %i)\n", \
10307                           current_config->name, \
10308                           pipe_config->name); \
10309                 return false; \
10310         }
10311
10312 #define PIPE_CONF_QUIRK(quirk)  \
10313         ((current_config->quirks | pipe_config->quirks) & (quirk))
10314
10315         PIPE_CONF_CHECK_I(cpu_transcoder);
10316
10317         PIPE_CONF_CHECK_I(has_pch_encoder);
10318         PIPE_CONF_CHECK_I(fdi_lanes);
10319         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10320         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10321         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10322         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10323         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10324
10325         PIPE_CONF_CHECK_I(has_dp_encoder);
10326
10327         if (INTEL_INFO(dev)->gen < 8) {
10328                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10329                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10330                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10331                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10332                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10333
10334                 if (current_config->has_drrs) {
10335                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10336                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10337                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10338                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10339                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10340                 }
10341         } else {
10342                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10343                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10344                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10345                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10346                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10347         }
10348
10349         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10350         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10351         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10352         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10354         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10355
10356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10357         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10358         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10359         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10360         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10361         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10362
10363         PIPE_CONF_CHECK_I(pixel_multiplier);
10364         PIPE_CONF_CHECK_I(has_hdmi_sink);
10365         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10366             IS_VALLEYVIEW(dev))
10367                 PIPE_CONF_CHECK_I(limited_color_range);
10368
10369         PIPE_CONF_CHECK_I(has_audio);
10370
10371         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10372                               DRM_MODE_FLAG_INTERLACE);
10373
10374         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10375                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10376                                       DRM_MODE_FLAG_PHSYNC);
10377                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10378                                       DRM_MODE_FLAG_NHSYNC);
10379                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10380                                       DRM_MODE_FLAG_PVSYNC);
10381                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10382                                       DRM_MODE_FLAG_NVSYNC);
10383         }
10384
10385         PIPE_CONF_CHECK_I(pipe_src_w);
10386         PIPE_CONF_CHECK_I(pipe_src_h);
10387
10388         /*
10389          * FIXME: BIOS likes to set up a cloned config with lvds+external
10390          * screen. Since we don't yet re-compute the pipe config when moving
10391          * just the lvds port away to another pipe the sw tracking won't match.
10392          *
10393          * Proper atomic modesets with recomputed global state will fix this.
10394          * Until then just don't check gmch state for inherited modes.
10395          */
10396         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10397                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10398                 /* pfit ratios are autocomputed by the hw on gen4+ */
10399                 if (INTEL_INFO(dev)->gen < 4)
10400                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10401                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10402         }
10403
10404         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10405         if (current_config->pch_pfit.enabled) {
10406                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10407                 PIPE_CONF_CHECK_I(pch_pfit.size);
10408         }
10409
10410         /* BDW+ don't expose a synchronous way to read the state */
10411         if (IS_HASWELL(dev))
10412                 PIPE_CONF_CHECK_I(ips_enabled);
10413
10414         PIPE_CONF_CHECK_I(double_wide);
10415
10416         PIPE_CONF_CHECK_X(ddi_pll_sel);
10417
10418         PIPE_CONF_CHECK_I(shared_dpll);
10419         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10420         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10421         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10422         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10423         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10424
10425         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10426                 PIPE_CONF_CHECK_I(pipe_bpp);
10427
10428         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10429         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10430
10431 #undef PIPE_CONF_CHECK_X
10432 #undef PIPE_CONF_CHECK_I
10433 #undef PIPE_CONF_CHECK_I_ALT
10434 #undef PIPE_CONF_CHECK_FLAGS
10435 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10436 #undef PIPE_CONF_QUIRK
10437
10438         return true;
10439 }
10440
10441 static void
10442 check_connector_state(struct drm_device *dev)
10443 {
10444         struct intel_connector *connector;
10445
10446         list_for_each_entry(connector, &dev->mode_config.connector_list,
10447                             base.head) {
10448                 /* This also checks the encoder/connector hw state with the
10449                  * ->get_hw_state callbacks. */
10450                 intel_connector_check_state(connector);
10451
10452                 WARN(&connector->new_encoder->base != connector->base.encoder,
10453                      "connector's staged encoder doesn't match current encoder\n");
10454         }
10455 }
10456
10457 static void
10458 check_encoder_state(struct drm_device *dev)
10459 {
10460         struct intel_encoder *encoder;
10461         struct intel_connector *connector;
10462
10463         for_each_intel_encoder(dev, encoder) {
10464                 bool enabled = false;
10465                 bool active = false;
10466                 enum pipe pipe, tracked_pipe;
10467
10468                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10469                               encoder->base.base.id,
10470                               encoder->base.name);
10471
10472                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10473                      "encoder's stage crtc doesn't match current crtc\n");
10474                 WARN(encoder->connectors_active && !encoder->base.crtc,
10475                      "encoder's active_connectors set, but no crtc\n");
10476
10477                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10478                                     base.head) {
10479                         if (connector->base.encoder != &encoder->base)
10480                                 continue;
10481                         enabled = true;
10482                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10483                                 active = true;
10484                 }
10485                 /*
10486                  * for MST connectors if we unplug the connector is gone
10487                  * away but the encoder is still connected to a crtc
10488                  * until a modeset happens in response to the hotplug.
10489                  */
10490                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10491                         continue;
10492
10493                 WARN(!!encoder->base.crtc != enabled,
10494                      "encoder's enabled state mismatch "
10495                      "(expected %i, found %i)\n",
10496                      !!encoder->base.crtc, enabled);
10497                 WARN(active && !encoder->base.crtc,
10498                      "active encoder with no crtc\n");
10499
10500                 WARN(encoder->connectors_active != active,
10501                      "encoder's computed active state doesn't match tracked active state "
10502                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10503
10504                 active = encoder->get_hw_state(encoder, &pipe);
10505                 WARN(active != encoder->connectors_active,
10506                      "encoder's hw state doesn't match sw tracking "
10507                      "(expected %i, found %i)\n",
10508                      encoder->connectors_active, active);
10509
10510                 if (!encoder->base.crtc)
10511                         continue;
10512
10513                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10514                 WARN(active && pipe != tracked_pipe,
10515                      "active encoder's pipe doesn't match"
10516                      "(expected %i, found %i)\n",
10517                      tracked_pipe, pipe);
10518
10519         }
10520 }
10521
10522 static void
10523 check_crtc_state(struct drm_device *dev)
10524 {
10525         struct drm_i915_private *dev_priv = dev->dev_private;
10526         struct intel_crtc *crtc;
10527         struct intel_encoder *encoder;
10528         struct intel_crtc_config pipe_config;
10529
10530         for_each_intel_crtc(dev, crtc) {
10531                 bool enabled = false;
10532                 bool active = false;
10533
10534                 memset(&pipe_config, 0, sizeof(pipe_config));
10535
10536                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10537                               crtc->base.base.id);
10538
10539                 WARN(crtc->active && !crtc->base.enabled,
10540                      "active crtc, but not enabled in sw tracking\n");
10541
10542                 for_each_intel_encoder(dev, encoder) {
10543                         if (encoder->base.crtc != &crtc->base)
10544                                 continue;
10545                         enabled = true;
10546                         if (encoder->connectors_active)
10547                                 active = true;
10548                 }
10549
10550                 WARN(active != crtc->active,
10551                      "crtc's computed active state doesn't match tracked active state "
10552                      "(expected %i, found %i)\n", active, crtc->active);
10553                 WARN(enabled != crtc->base.enabled,
10554                      "crtc's computed enabled state doesn't match tracked enabled state "
10555                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10556
10557                 active = dev_priv->display.get_pipe_config(crtc,
10558                                                            &pipe_config);
10559
10560                 /* hw state is inconsistent with the pipe quirk */
10561                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10562                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10563                         active = crtc->active;
10564
10565                 for_each_intel_encoder(dev, encoder) {
10566                         enum pipe pipe;
10567                         if (encoder->base.crtc != &crtc->base)
10568                                 continue;
10569                         if (encoder->get_hw_state(encoder, &pipe))
10570                                 encoder->get_config(encoder, &pipe_config);
10571                 }
10572
10573                 WARN(crtc->active != active,
10574                      "crtc active state doesn't match with hw state "
10575                      "(expected %i, found %i)\n", crtc->active, active);
10576
10577                 if (active &&
10578                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10579                         WARN(1, "pipe state doesn't match!\n");
10580                         intel_dump_pipe_config(crtc, &pipe_config,
10581                                                "[hw state]");
10582                         intel_dump_pipe_config(crtc, &crtc->config,
10583                                                "[sw state]");
10584                 }
10585         }
10586 }
10587
10588 static void
10589 check_shared_dpll_state(struct drm_device *dev)
10590 {
10591         struct drm_i915_private *dev_priv = dev->dev_private;
10592         struct intel_crtc *crtc;
10593         struct intel_dpll_hw_state dpll_hw_state;
10594         int i;
10595
10596         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10597                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10598                 int enabled_crtcs = 0, active_crtcs = 0;
10599                 bool active;
10600
10601                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10602
10603                 DRM_DEBUG_KMS("%s\n", pll->name);
10604
10605                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10606
10607                 WARN(pll->active > pll->refcount,
10608                      "more active pll users than references: %i vs %i\n",
10609                      pll->active, pll->refcount);
10610                 WARN(pll->active && !pll->on,
10611                      "pll in active use but not on in sw tracking\n");
10612                 WARN(pll->on && !pll->active,
10613                      "pll in on but not on in use in sw tracking\n");
10614                 WARN(pll->on != active,
10615                      "pll on state mismatch (expected %i, found %i)\n",
10616                      pll->on, active);
10617
10618                 for_each_intel_crtc(dev, crtc) {
10619                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10620                                 enabled_crtcs++;
10621                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10622                                 active_crtcs++;
10623                 }
10624                 WARN(pll->active != active_crtcs,
10625                      "pll active crtcs mismatch (expected %i, found %i)\n",
10626                      pll->active, active_crtcs);
10627                 WARN(pll->refcount != enabled_crtcs,
10628                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10629                      pll->refcount, enabled_crtcs);
10630
10631                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10632                                        sizeof(dpll_hw_state)),
10633                      "pll hw state mismatch\n");
10634         }
10635 }
10636
10637 void
10638 intel_modeset_check_state(struct drm_device *dev)
10639 {
10640         check_connector_state(dev);
10641         check_encoder_state(dev);
10642         check_crtc_state(dev);
10643         check_shared_dpll_state(dev);
10644 }
10645
10646 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10647                                      int dotclock)
10648 {
10649         /*
10650          * FDI already provided one idea for the dotclock.
10651          * Yell if the encoder disagrees.
10652          */
10653         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10654              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10655              pipe_config->adjusted_mode.crtc_clock, dotclock);
10656 }
10657
10658 static void update_scanline_offset(struct intel_crtc *crtc)
10659 {
10660         struct drm_device *dev = crtc->base.dev;
10661
10662         /*
10663          * The scanline counter increments at the leading edge of hsync.
10664          *
10665          * On most platforms it starts counting from vtotal-1 on the
10666          * first active line. That means the scanline counter value is
10667          * always one less than what we would expect. Ie. just after
10668          * start of vblank, which also occurs at start of hsync (on the
10669          * last active line), the scanline counter will read vblank_start-1.
10670          *
10671          * On gen2 the scanline counter starts counting from 1 instead
10672          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10673          * to keep the value positive), instead of adding one.
10674          *
10675          * On HSW+ the behaviour of the scanline counter depends on the output
10676          * type. For DP ports it behaves like most other platforms, but on HDMI
10677          * there's an extra 1 line difference. So we need to add two instead of
10678          * one to the value.
10679          */
10680         if (IS_GEN2(dev)) {
10681                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10682                 int vtotal;
10683
10684                 vtotal = mode->crtc_vtotal;
10685                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10686                         vtotal /= 2;
10687
10688                 crtc->scanline_offset = vtotal - 1;
10689         } else if (HAS_DDI(dev) &&
10690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10691                 crtc->scanline_offset = 2;
10692         } else
10693                 crtc->scanline_offset = 1;
10694 }
10695
10696 static int __intel_set_mode(struct drm_crtc *crtc,
10697                             struct drm_display_mode *mode,
10698                             int x, int y, struct drm_framebuffer *fb)
10699 {
10700         struct drm_device *dev = crtc->dev;
10701         struct drm_i915_private *dev_priv = dev->dev_private;
10702         struct drm_display_mode *saved_mode;
10703         struct intel_crtc_config *pipe_config = NULL;
10704         struct intel_crtc *intel_crtc;
10705         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10706         int ret = 0;
10707
10708         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10709         if (!saved_mode)
10710                 return -ENOMEM;
10711
10712         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10713                                      &prepare_pipes, &disable_pipes);
10714
10715         *saved_mode = crtc->mode;
10716
10717         /* Hack: Because we don't (yet) support global modeset on multiple
10718          * crtcs, we don't keep track of the new mode for more than one crtc.
10719          * Hence simply check whether any bit is set in modeset_pipes in all the
10720          * pieces of code that are not yet converted to deal with mutliple crtcs
10721          * changing their mode at the same time. */
10722         if (modeset_pipes) {
10723                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10724                 if (IS_ERR(pipe_config)) {
10725                         ret = PTR_ERR(pipe_config);
10726                         pipe_config = NULL;
10727
10728                         goto out;
10729                 }
10730                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10731                                        "[modeset]");
10732                 to_intel_crtc(crtc)->new_config = pipe_config;
10733         }
10734
10735         /*
10736          * See if the config requires any additional preparation, e.g.
10737          * to adjust global state with pipes off.  We need to do this
10738          * here so we can get the modeset_pipe updated config for the new
10739          * mode set on this crtc.  For other crtcs we need to use the
10740          * adjusted_mode bits in the crtc directly.
10741          */
10742         if (IS_VALLEYVIEW(dev)) {
10743                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10744
10745                 /* may have added more to prepare_pipes than we should */
10746                 prepare_pipes &= ~disable_pipes;
10747         }
10748
10749         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10750                 intel_crtc_disable(&intel_crtc->base);
10751
10752         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10753                 if (intel_crtc->base.enabled)
10754                         dev_priv->display.crtc_disable(&intel_crtc->base);
10755         }
10756
10757         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10758          * to set it here already despite that we pass it down the callchain.
10759          */
10760         if (modeset_pipes) {
10761                 crtc->mode = *mode;
10762                 /* mode_set/enable/disable functions rely on a correct pipe
10763                  * config. */
10764                 to_intel_crtc(crtc)->config = *pipe_config;
10765                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10766
10767                 /*
10768                  * Calculate and store various constants which
10769                  * are later needed by vblank and swap-completion
10770                  * timestamping. They are derived from true hwmode.
10771                  */
10772                 drm_calc_timestamping_constants(crtc,
10773                                                 &pipe_config->adjusted_mode);
10774         }
10775
10776         /* Only after disabling all output pipelines that will be changed can we
10777          * update the the output configuration. */
10778         intel_modeset_update_state(dev, prepare_pipes);
10779
10780         if (dev_priv->display.modeset_global_resources)
10781                 dev_priv->display.modeset_global_resources(dev);
10782
10783         /* Set up the DPLL and any encoders state that needs to adjust or depend
10784          * on the DPLL.
10785          */
10786         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10787                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10788                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10789                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10790
10791                 mutex_lock(&dev->struct_mutex);
10792                 ret = intel_pin_and_fence_fb_obj(dev,
10793                                                  obj,
10794                                                  NULL);
10795                 if (ret != 0) {
10796                         DRM_ERROR("pin & fence failed\n");
10797                         mutex_unlock(&dev->struct_mutex);
10798                         goto done;
10799                 }
10800                 if (old_fb)
10801                         intel_unpin_fb_obj(old_obj);
10802                 i915_gem_track_fb(old_obj, obj,
10803                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10804                 mutex_unlock(&dev->struct_mutex);
10805
10806                 crtc->primary->fb = fb;
10807                 crtc->x = x;
10808                 crtc->y = y;
10809
10810                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10811                 if (ret)
10812                         goto done;
10813         }
10814
10815         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10816         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10817                 update_scanline_offset(intel_crtc);
10818
10819                 dev_priv->display.crtc_enable(&intel_crtc->base);
10820         }
10821
10822         /* FIXME: add subpixel order */
10823 done:
10824         if (ret && crtc->enabled)
10825                 crtc->mode = *saved_mode;
10826
10827 out:
10828         kfree(pipe_config);
10829         kfree(saved_mode);
10830         return ret;
10831 }
10832
10833 static int intel_set_mode(struct drm_crtc *crtc,
10834                           struct drm_display_mode *mode,
10835                           int x, int y, struct drm_framebuffer *fb)
10836 {
10837         int ret;
10838
10839         ret = __intel_set_mode(crtc, mode, x, y, fb);
10840
10841         if (ret == 0)
10842                 intel_modeset_check_state(crtc->dev);
10843
10844         return ret;
10845 }
10846
10847 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10848 {
10849         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10850 }
10851
10852 #undef for_each_intel_crtc_masked
10853
10854 static void intel_set_config_free(struct intel_set_config *config)
10855 {
10856         if (!config)
10857                 return;
10858
10859         kfree(config->save_connector_encoders);
10860         kfree(config->save_encoder_crtcs);
10861         kfree(config->save_crtc_enabled);
10862         kfree(config);
10863 }
10864
10865 static int intel_set_config_save_state(struct drm_device *dev,
10866                                        struct intel_set_config *config)
10867 {
10868         struct drm_crtc *crtc;
10869         struct drm_encoder *encoder;
10870         struct drm_connector *connector;
10871         int count;
10872
10873         config->save_crtc_enabled =
10874                 kcalloc(dev->mode_config.num_crtc,
10875                         sizeof(bool), GFP_KERNEL);
10876         if (!config->save_crtc_enabled)
10877                 return -ENOMEM;
10878
10879         config->save_encoder_crtcs =
10880                 kcalloc(dev->mode_config.num_encoder,
10881                         sizeof(struct drm_crtc *), GFP_KERNEL);
10882         if (!config->save_encoder_crtcs)
10883                 return -ENOMEM;
10884
10885         config->save_connector_encoders =
10886                 kcalloc(dev->mode_config.num_connector,
10887                         sizeof(struct drm_encoder *), GFP_KERNEL);
10888         if (!config->save_connector_encoders)
10889                 return -ENOMEM;
10890
10891         /* Copy data. Note that driver private data is not affected.
10892          * Should anything bad happen only the expected state is
10893          * restored, not the drivers personal bookkeeping.
10894          */
10895         count = 0;
10896         for_each_crtc(dev, crtc) {
10897                 config->save_crtc_enabled[count++] = crtc->enabled;
10898         }
10899
10900         count = 0;
10901         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10902                 config->save_encoder_crtcs[count++] = encoder->crtc;
10903         }
10904
10905         count = 0;
10906         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10907                 config->save_connector_encoders[count++] = connector->encoder;
10908         }
10909
10910         return 0;
10911 }
10912
10913 static void intel_set_config_restore_state(struct drm_device *dev,
10914                                            struct intel_set_config *config)
10915 {
10916         struct intel_crtc *crtc;
10917         struct intel_encoder *encoder;
10918         struct intel_connector *connector;
10919         int count;
10920
10921         count = 0;
10922         for_each_intel_crtc(dev, crtc) {
10923                 crtc->new_enabled = config->save_crtc_enabled[count++];
10924
10925                 if (crtc->new_enabled)
10926                         crtc->new_config = &crtc->config;
10927                 else
10928                         crtc->new_config = NULL;
10929         }
10930
10931         count = 0;
10932         for_each_intel_encoder(dev, encoder) {
10933                 encoder->new_crtc =
10934                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10935         }
10936
10937         count = 0;
10938         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10939                 connector->new_encoder =
10940                         to_intel_encoder(config->save_connector_encoders[count++]);
10941         }
10942 }
10943
10944 static bool
10945 is_crtc_connector_off(struct drm_mode_set *set)
10946 {
10947         int i;
10948
10949         if (set->num_connectors == 0)
10950                 return false;
10951
10952         if (WARN_ON(set->connectors == NULL))
10953                 return false;
10954
10955         for (i = 0; i < set->num_connectors; i++)
10956                 if (set->connectors[i]->encoder &&
10957                     set->connectors[i]->encoder->crtc == set->crtc &&
10958                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10959                         return true;
10960
10961         return false;
10962 }
10963
10964 static void
10965 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10966                                       struct intel_set_config *config)
10967 {
10968
10969         /* We should be able to check here if the fb has the same properties
10970          * and then just flip_or_move it */
10971         if (is_crtc_connector_off(set)) {
10972                 config->mode_changed = true;
10973         } else if (set->crtc->primary->fb != set->fb) {
10974                 /*
10975                  * If we have no fb, we can only flip as long as the crtc is
10976                  * active, otherwise we need a full mode set.  The crtc may
10977                  * be active if we've only disabled the primary plane, or
10978                  * in fastboot situations.
10979                  */
10980                 if (set->crtc->primary->fb == NULL) {
10981                         struct intel_crtc *intel_crtc =
10982                                 to_intel_crtc(set->crtc);
10983
10984                         if (intel_crtc->active) {
10985                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10986                                 config->fb_changed = true;
10987                         } else {
10988                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10989                                 config->mode_changed = true;
10990                         }
10991                 } else if (set->fb == NULL) {
10992                         config->mode_changed = true;
10993                 } else if (set->fb->pixel_format !=
10994                            set->crtc->primary->fb->pixel_format) {
10995                         config->mode_changed = true;
10996                 } else {
10997                         config->fb_changed = true;
10998                 }
10999         }
11000
11001         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11002                 config->fb_changed = true;
11003
11004         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11005                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11006                 drm_mode_debug_printmodeline(&set->crtc->mode);
11007                 drm_mode_debug_printmodeline(set->mode);
11008                 config->mode_changed = true;
11009         }
11010
11011         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11012                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11013 }
11014
11015 static int
11016 intel_modeset_stage_output_state(struct drm_device *dev,
11017                                  struct drm_mode_set *set,
11018                                  struct intel_set_config *config)
11019 {
11020         struct intel_connector *connector;
11021         struct intel_encoder *encoder;
11022         struct intel_crtc *crtc;
11023         int ro;
11024
11025         /* The upper layers ensure that we either disable a crtc or have a list
11026          * of connectors. For paranoia, double-check this. */
11027         WARN_ON(!set->fb && (set->num_connectors != 0));
11028         WARN_ON(set->fb && (set->num_connectors == 0));
11029
11030         list_for_each_entry(connector, &dev->mode_config.connector_list,
11031                             base.head) {
11032                 /* Otherwise traverse passed in connector list and get encoders
11033                  * for them. */
11034                 for (ro = 0; ro < set->num_connectors; ro++) {
11035                         if (set->connectors[ro] == &connector->base) {
11036                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11037                                 break;
11038                         }
11039                 }
11040
11041                 /* If we disable the crtc, disable all its connectors. Also, if
11042                  * the connector is on the changing crtc but not on the new
11043                  * connector list, disable it. */
11044                 if ((!set->fb || ro == set->num_connectors) &&
11045                     connector->base.encoder &&
11046                     connector->base.encoder->crtc == set->crtc) {
11047                         connector->new_encoder = NULL;
11048
11049                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11050                                 connector->base.base.id,
11051                                 connector->base.name);
11052                 }
11053
11054
11055                 if (&connector->new_encoder->base != connector->base.encoder) {
11056                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11057                         config->mode_changed = true;
11058                 }
11059         }
11060         /* connector->new_encoder is now updated for all connectors. */
11061
11062         /* Update crtc of enabled connectors. */
11063         list_for_each_entry(connector, &dev->mode_config.connector_list,
11064                             base.head) {
11065                 struct drm_crtc *new_crtc;
11066
11067                 if (!connector->new_encoder)
11068                         continue;
11069
11070                 new_crtc = connector->new_encoder->base.crtc;
11071
11072                 for (ro = 0; ro < set->num_connectors; ro++) {
11073                         if (set->connectors[ro] == &connector->base)
11074                                 new_crtc = set->crtc;
11075                 }
11076
11077                 /* Make sure the new CRTC will work with the encoder */
11078                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11079                                          new_crtc)) {
11080                         return -EINVAL;
11081                 }
11082                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11083
11084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11085                         connector->base.base.id,
11086                         connector->base.name,
11087                         new_crtc->base.id);
11088         }
11089
11090         /* Check for any encoders that needs to be disabled. */
11091         for_each_intel_encoder(dev, encoder) {
11092                 int num_connectors = 0;
11093                 list_for_each_entry(connector,
11094                                     &dev->mode_config.connector_list,
11095                                     base.head) {
11096                         if (connector->new_encoder == encoder) {
11097                                 WARN_ON(!connector->new_encoder->new_crtc);
11098                                 num_connectors++;
11099                         }
11100                 }
11101
11102                 if (num_connectors == 0)
11103                         encoder->new_crtc = NULL;
11104                 else if (num_connectors > 1)
11105                         return -EINVAL;
11106
11107                 /* Only now check for crtc changes so we don't miss encoders
11108                  * that will be disabled. */
11109                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11110                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11111                         config->mode_changed = true;
11112                 }
11113         }
11114         /* Now we've also updated encoder->new_crtc for all encoders. */
11115         list_for_each_entry(connector, &dev->mode_config.connector_list,
11116                             base.head) {
11117                 if (connector->new_encoder)
11118                         if (connector->new_encoder != connector->encoder)
11119                                 connector->encoder = connector->new_encoder;
11120         }
11121         for_each_intel_crtc(dev, crtc) {
11122                 crtc->new_enabled = false;
11123
11124                 for_each_intel_encoder(dev, encoder) {
11125                         if (encoder->new_crtc == crtc) {
11126                                 crtc->new_enabled = true;
11127                                 break;
11128                         }
11129                 }
11130
11131                 if (crtc->new_enabled != crtc->base.enabled) {
11132                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11133                                       crtc->new_enabled ? "en" : "dis");
11134                         config->mode_changed = true;
11135                 }
11136
11137                 if (crtc->new_enabled)
11138                         crtc->new_config = &crtc->config;
11139                 else
11140                         crtc->new_config = NULL;
11141         }
11142
11143         return 0;
11144 }
11145
11146 static void disable_crtc_nofb(struct intel_crtc *crtc)
11147 {
11148         struct drm_device *dev = crtc->base.dev;
11149         struct intel_encoder *encoder;
11150         struct intel_connector *connector;
11151
11152         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11153                       pipe_name(crtc->pipe));
11154
11155         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11156                 if (connector->new_encoder &&
11157                     connector->new_encoder->new_crtc == crtc)
11158                         connector->new_encoder = NULL;
11159         }
11160
11161         for_each_intel_encoder(dev, encoder) {
11162                 if (encoder->new_crtc == crtc)
11163                         encoder->new_crtc = NULL;
11164         }
11165
11166         crtc->new_enabled = false;
11167         crtc->new_config = NULL;
11168 }
11169
11170 static int intel_crtc_set_config(struct drm_mode_set *set)
11171 {
11172         struct drm_device *dev;
11173         struct drm_mode_set save_set;
11174         struct intel_set_config *config;
11175         int ret;
11176
11177         BUG_ON(!set);
11178         BUG_ON(!set->crtc);
11179         BUG_ON(!set->crtc->helper_private);
11180
11181         /* Enforce sane interface api - has been abused by the fb helper. */
11182         BUG_ON(!set->mode && set->fb);
11183         BUG_ON(set->fb && set->num_connectors == 0);
11184
11185         if (set->fb) {
11186                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11187                                 set->crtc->base.id, set->fb->base.id,
11188                                 (int)set->num_connectors, set->x, set->y);
11189         } else {
11190                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11191         }
11192
11193         dev = set->crtc->dev;
11194
11195         ret = -ENOMEM;
11196         config = kzalloc(sizeof(*config), GFP_KERNEL);
11197         if (!config)
11198                 goto out_config;
11199
11200         ret = intel_set_config_save_state(dev, config);
11201         if (ret)
11202                 goto out_config;
11203
11204         save_set.crtc = set->crtc;
11205         save_set.mode = &set->crtc->mode;
11206         save_set.x = set->crtc->x;
11207         save_set.y = set->crtc->y;
11208         save_set.fb = set->crtc->primary->fb;
11209
11210         /* Compute whether we need a full modeset, only an fb base update or no
11211          * change at all. In the future we might also check whether only the
11212          * mode changed, e.g. for LVDS where we only change the panel fitter in
11213          * such cases. */
11214         intel_set_config_compute_mode_changes(set, config);
11215
11216         ret = intel_modeset_stage_output_state(dev, set, config);
11217         if (ret)
11218                 goto fail;
11219
11220         if (config->mode_changed) {
11221                 ret = intel_set_mode(set->crtc, set->mode,
11222                                      set->x, set->y, set->fb);
11223         } else if (config->fb_changed) {
11224                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11225
11226                 intel_crtc_wait_for_pending_flips(set->crtc);
11227
11228                 ret = intel_pipe_set_base(set->crtc,
11229                                           set->x, set->y, set->fb);
11230
11231                 /*
11232                  * We need to make sure the primary plane is re-enabled if it
11233                  * has previously been turned off.
11234                  */
11235                 if (!intel_crtc->primary_enabled && ret == 0) {
11236                         WARN_ON(!intel_crtc->active);
11237                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11238                 }
11239
11240                 /*
11241                  * In the fastboot case this may be our only check of the
11242                  * state after boot.  It would be better to only do it on
11243                  * the first update, but we don't have a nice way of doing that
11244                  * (and really, set_config isn't used much for high freq page
11245                  * flipping, so increasing its cost here shouldn't be a big
11246                  * deal).
11247                  */
11248                 if (i915.fastboot && ret == 0)
11249                         intel_modeset_check_state(set->crtc->dev);
11250         }
11251
11252         if (ret) {
11253                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11254                               set->crtc->base.id, ret);
11255 fail:
11256                 intel_set_config_restore_state(dev, config);
11257
11258                 /*
11259                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11260                  * force the pipe off to avoid oopsing in the modeset code
11261                  * due to fb==NULL. This should only happen during boot since
11262                  * we don't yet reconstruct the FB from the hardware state.
11263                  */
11264                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11265                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11266
11267                 /* Try to restore the config */
11268                 if (config->mode_changed &&
11269                     intel_set_mode(save_set.crtc, save_set.mode,
11270                                    save_set.x, save_set.y, save_set.fb))
11271                         DRM_ERROR("failed to restore config after modeset failure\n");
11272         }
11273
11274 out_config:
11275         intel_set_config_free(config);
11276         return ret;
11277 }
11278
11279 static const struct drm_crtc_funcs intel_crtc_funcs = {
11280         .gamma_set = intel_crtc_gamma_set,
11281         .set_config = intel_crtc_set_config,
11282         .destroy = intel_crtc_destroy,
11283         .page_flip = intel_crtc_page_flip,
11284 };
11285
11286 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11287                                       struct intel_shared_dpll *pll,
11288                                       struct intel_dpll_hw_state *hw_state)
11289 {
11290         uint32_t val;
11291
11292         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11293                 return false;
11294
11295         val = I915_READ(PCH_DPLL(pll->id));
11296         hw_state->dpll = val;
11297         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11298         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11299
11300         return val & DPLL_VCO_ENABLE;
11301 }
11302
11303 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11304                                   struct intel_shared_dpll *pll)
11305 {
11306         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11307         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11308 }
11309
11310 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11311                                 struct intel_shared_dpll *pll)
11312 {
11313         /* PCH refclock must be enabled first */
11314         ibx_assert_pch_refclk_enabled(dev_priv);
11315
11316         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11317
11318         /* Wait for the clocks to stabilize. */
11319         POSTING_READ(PCH_DPLL(pll->id));
11320         udelay(150);
11321
11322         /* The pixel multiplier can only be updated once the
11323          * DPLL is enabled and the clocks are stable.
11324          *
11325          * So write it again.
11326          */
11327         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11328         POSTING_READ(PCH_DPLL(pll->id));
11329         udelay(200);
11330 }
11331
11332 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11333                                  struct intel_shared_dpll *pll)
11334 {
11335         struct drm_device *dev = dev_priv->dev;
11336         struct intel_crtc *crtc;
11337
11338         /* Make sure no transcoder isn't still depending on us. */
11339         for_each_intel_crtc(dev, crtc) {
11340                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11341                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11342         }
11343
11344         I915_WRITE(PCH_DPLL(pll->id), 0);
11345         POSTING_READ(PCH_DPLL(pll->id));
11346         udelay(200);
11347 }
11348
11349 static char *ibx_pch_dpll_names[] = {
11350         "PCH DPLL A",
11351         "PCH DPLL B",
11352 };
11353
11354 static void ibx_pch_dpll_init(struct drm_device *dev)
11355 {
11356         struct drm_i915_private *dev_priv = dev->dev_private;
11357         int i;
11358
11359         dev_priv->num_shared_dpll = 2;
11360
11361         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11362                 dev_priv->shared_dplls[i].id = i;
11363                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11364                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11365                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11366                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11367                 dev_priv->shared_dplls[i].get_hw_state =
11368                         ibx_pch_dpll_get_hw_state;
11369         }
11370 }
11371
11372 static void intel_shared_dpll_init(struct drm_device *dev)
11373 {
11374         struct drm_i915_private *dev_priv = dev->dev_private;
11375
11376         if (HAS_DDI(dev))
11377                 intel_ddi_pll_init(dev);
11378         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11379                 ibx_pch_dpll_init(dev);
11380         else
11381                 dev_priv->num_shared_dpll = 0;
11382
11383         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11384 }
11385
11386 static int
11387 intel_primary_plane_disable(struct drm_plane *plane)
11388 {
11389         struct drm_device *dev = plane->dev;
11390         struct intel_crtc *intel_crtc;
11391
11392         if (!plane->fb)
11393                 return 0;
11394
11395         BUG_ON(!plane->crtc);
11396
11397         intel_crtc = to_intel_crtc(plane->crtc);
11398
11399         /*
11400          * Even though we checked plane->fb above, it's still possible that
11401          * the primary plane has been implicitly disabled because the crtc
11402          * coordinates given weren't visible, or because we detected
11403          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11404          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11405          * In either case, we need to unpin the FB and let the fb pointer get
11406          * updated, but otherwise we don't need to touch the hardware.
11407          */
11408         if (!intel_crtc->primary_enabled)
11409                 goto disable_unpin;
11410
11411         intel_crtc_wait_for_pending_flips(plane->crtc);
11412         intel_disable_primary_hw_plane(plane, plane->crtc);
11413
11414 disable_unpin:
11415         mutex_lock(&dev->struct_mutex);
11416         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11417                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11418         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11419         mutex_unlock(&dev->struct_mutex);
11420         plane->fb = NULL;
11421
11422         return 0;
11423 }
11424
11425 static int
11426 intel_check_primary_plane(struct drm_plane *plane,
11427                           struct intel_plane_state *state)
11428 {
11429         struct drm_crtc *crtc = state->crtc;
11430         struct drm_framebuffer *fb = state->fb;
11431         struct drm_rect *dest = &state->dst;
11432         struct drm_rect *src = &state->src;
11433         const struct drm_rect *clip = &state->clip;
11434
11435         return drm_plane_helper_check_update(plane, crtc, fb,
11436                                              src, dest, clip,
11437                                              DRM_PLANE_HELPER_NO_SCALING,
11438                                              DRM_PLANE_HELPER_NO_SCALING,
11439                                              false, true, &state->visible);
11440 }
11441
11442 static int
11443 intel_prepare_primary_plane(struct drm_plane *plane,
11444                             struct intel_plane_state *state)
11445 {
11446         struct drm_crtc *crtc = state->crtc;
11447         struct drm_framebuffer *fb = state->fb;
11448         struct drm_device *dev = crtc->dev;
11449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11450         enum pipe pipe = intel_crtc->pipe;
11451         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11452         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11453         int ret;
11454
11455         intel_crtc_wait_for_pending_flips(crtc);
11456
11457         if (intel_crtc_has_pending_flip(crtc)) {
11458                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11459                 return -EBUSY;
11460         }
11461
11462         if (old_obj != obj) {
11463                 mutex_lock(&dev->struct_mutex);
11464                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11465                 if (ret == 0)
11466                         i915_gem_track_fb(old_obj, obj,
11467                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11468                 mutex_unlock(&dev->struct_mutex);
11469                 if (ret != 0) {
11470                         DRM_DEBUG_KMS("pin & fence failed\n");
11471                         return ret;
11472                 }
11473         }
11474
11475         return 0;
11476 }
11477
11478 static void
11479 intel_commit_primary_plane(struct drm_plane *plane,
11480                            struct intel_plane_state *state)
11481 {
11482         struct drm_crtc *crtc = state->crtc;
11483         struct drm_framebuffer *fb = state->fb;
11484         struct drm_device *dev = crtc->dev;
11485         struct drm_i915_private *dev_priv = dev->dev_private;
11486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11487         enum pipe pipe = intel_crtc->pipe;
11488         struct drm_framebuffer *old_fb = plane->fb;
11489         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11490         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11491         struct intel_plane *intel_plane = to_intel_plane(plane);
11492         struct drm_rect *src = &state->src;
11493
11494         crtc->primary->fb = fb;
11495         crtc->x = src->x1;
11496         crtc->y = src->y1;
11497
11498         intel_plane->crtc_x = state->orig_dst.x1;
11499         intel_plane->crtc_y = state->orig_dst.y1;
11500         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11501         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11502         intel_plane->src_x = state->orig_src.x1;
11503         intel_plane->src_y = state->orig_src.y1;
11504         intel_plane->src_w = drm_rect_width(&state->orig_src);
11505         intel_plane->src_h = drm_rect_height(&state->orig_src);
11506         intel_plane->obj = obj;
11507
11508         if (intel_crtc->active) {
11509                 /*
11510                  * FBC does not work on some platforms for rotated
11511                  * planes, so disable it when rotation is not 0 and
11512                  * update it when rotation is set back to 0.
11513                  *
11514                  * FIXME: This is redundant with the fbc update done in
11515                  * the primary plane enable function except that that
11516                  * one is done too late. We eventually need to unify
11517                  * this.
11518                  */
11519                 if (intel_crtc->primary_enabled &&
11520                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11521                     dev_priv->fbc.plane == intel_crtc->plane &&
11522                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11523                         intel_disable_fbc(dev);
11524                 }
11525
11526                 if (state->visible) {
11527                         bool was_enabled = intel_crtc->primary_enabled;
11528
11529                         /* FIXME: kill this fastboot hack */
11530                         intel_update_pipe_size(intel_crtc);
11531
11532                         intel_crtc->primary_enabled = true;
11533
11534                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11535                                         crtc->x, crtc->y);
11536
11537                         /*
11538                          * BDW signals flip done immediately if the plane
11539                          * is disabled, even if the plane enable is already
11540                          * armed to occur at the next vblank :(
11541                          */
11542                         if (IS_BROADWELL(dev) && !was_enabled)
11543                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11544                 } else {
11545                         /*
11546                          * If clipping results in a non-visible primary plane,
11547                          * we'll disable the primary plane.  Note that this is
11548                          * a bit different than what happens if userspace
11549                          * explicitly disables the plane by passing fb=0
11550                          * because plane->fb still gets set and pinned.
11551                          */
11552                         intel_disable_primary_hw_plane(plane, crtc);
11553                 }
11554
11555                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11556
11557                 mutex_lock(&dev->struct_mutex);
11558                 intel_update_fbc(dev);
11559                 mutex_unlock(&dev->struct_mutex);
11560         }
11561
11562         if (old_fb && old_fb != fb) {
11563                 if (intel_crtc->active)
11564                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11565
11566                 mutex_lock(&dev->struct_mutex);
11567                 intel_unpin_fb_obj(old_obj);
11568                 mutex_unlock(&dev->struct_mutex);
11569         }
11570 }
11571
11572 static int
11573 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11574                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11575                              unsigned int crtc_w, unsigned int crtc_h,
11576                              uint32_t src_x, uint32_t src_y,
11577                              uint32_t src_w, uint32_t src_h)
11578 {
11579         struct intel_plane_state state;
11580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11581         int ret;
11582
11583         state.crtc = crtc;
11584         state.fb = fb;
11585
11586         /* sample coordinates in 16.16 fixed point */
11587         state.src.x1 = src_x;
11588         state.src.x2 = src_x + src_w;
11589         state.src.y1 = src_y;
11590         state.src.y2 = src_y + src_h;
11591
11592         /* integer pixels */
11593         state.dst.x1 = crtc_x;
11594         state.dst.x2 = crtc_x + crtc_w;
11595         state.dst.y1 = crtc_y;
11596         state.dst.y2 = crtc_y + crtc_h;
11597
11598         state.clip.x1 = 0;
11599         state.clip.y1 = 0;
11600         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11601         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11602
11603         state.orig_src = state.src;
11604         state.orig_dst = state.dst;
11605
11606         ret = intel_check_primary_plane(plane, &state);
11607         if (ret)
11608                 return ret;
11609
11610         ret = intel_prepare_primary_plane(plane, &state);
11611         if (ret)
11612                 return ret;
11613
11614         intel_commit_primary_plane(plane, &state);
11615
11616         return 0;
11617 }
11618
11619 /* Common destruction function for both primary and cursor planes */
11620 static void intel_plane_destroy(struct drm_plane *plane)
11621 {
11622         struct intel_plane *intel_plane = to_intel_plane(plane);
11623         drm_plane_cleanup(plane);
11624         kfree(intel_plane);
11625 }
11626
11627 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11628         .update_plane = intel_primary_plane_setplane,
11629         .disable_plane = intel_primary_plane_disable,
11630         .destroy = intel_plane_destroy,
11631         .set_property = intel_plane_set_property
11632 };
11633
11634 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11635                                                     int pipe)
11636 {
11637         struct intel_plane *primary;
11638         const uint32_t *intel_primary_formats;
11639         int num_formats;
11640
11641         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11642         if (primary == NULL)
11643                 return NULL;
11644
11645         primary->can_scale = false;
11646         primary->max_downscale = 1;
11647         primary->pipe = pipe;
11648         primary->plane = pipe;
11649         primary->rotation = BIT(DRM_ROTATE_0);
11650         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11651                 primary->plane = !pipe;
11652
11653         if (INTEL_INFO(dev)->gen <= 3) {
11654                 intel_primary_formats = intel_primary_formats_gen2;
11655                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11656         } else {
11657                 intel_primary_formats = intel_primary_formats_gen4;
11658                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11659         }
11660
11661         drm_universal_plane_init(dev, &primary->base, 0,
11662                                  &intel_primary_plane_funcs,
11663                                  intel_primary_formats, num_formats,
11664                                  DRM_PLANE_TYPE_PRIMARY);
11665
11666         if (INTEL_INFO(dev)->gen >= 4) {
11667                 if (!dev->mode_config.rotation_property)
11668                         dev->mode_config.rotation_property =
11669                                 drm_mode_create_rotation_property(dev,
11670                                                         BIT(DRM_ROTATE_0) |
11671                                                         BIT(DRM_ROTATE_180));
11672                 if (dev->mode_config.rotation_property)
11673                         drm_object_attach_property(&primary->base.base,
11674                                 dev->mode_config.rotation_property,
11675                                 primary->rotation);
11676         }
11677
11678         return &primary->base;
11679 }
11680
11681 static int
11682 intel_cursor_plane_disable(struct drm_plane *plane)
11683 {
11684         if (!plane->fb)
11685                 return 0;
11686
11687         BUG_ON(!plane->crtc);
11688
11689         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11690 }
11691
11692 static int
11693 intel_check_cursor_plane(struct drm_plane *plane,
11694                          struct intel_plane_state *state)
11695 {
11696         struct drm_crtc *crtc = state->crtc;
11697         struct drm_device *dev = crtc->dev;
11698         struct drm_framebuffer *fb = state->fb;
11699         struct drm_rect *dest = &state->dst;
11700         struct drm_rect *src = &state->src;
11701         const struct drm_rect *clip = &state->clip;
11702         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11703         int crtc_w, crtc_h;
11704         unsigned stride;
11705         int ret;
11706
11707         ret = drm_plane_helper_check_update(plane, crtc, fb,
11708                                             src, dest, clip,
11709                                             DRM_PLANE_HELPER_NO_SCALING,
11710                                             DRM_PLANE_HELPER_NO_SCALING,
11711                                             true, true, &state->visible);
11712         if (ret)
11713                 return ret;
11714
11715
11716         /* if we want to turn off the cursor ignore width and height */
11717         if (!obj)
11718                 return 0;
11719
11720         /* Check for which cursor types we support */
11721         crtc_w = drm_rect_width(&state->orig_dst);
11722         crtc_h = drm_rect_height(&state->orig_dst);
11723         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11724                 DRM_DEBUG("Cursor dimension not supported\n");
11725                 return -EINVAL;
11726         }
11727
11728         stride = roundup_pow_of_two(crtc_w) * 4;
11729         if (obj->base.size < stride * crtc_h) {
11730                 DRM_DEBUG_KMS("buffer is too small\n");
11731                 return -ENOMEM;
11732         }
11733
11734         if (fb == crtc->cursor->fb)
11735                 return 0;
11736
11737         /* we only need to pin inside GTT if cursor is non-phy */
11738         mutex_lock(&dev->struct_mutex);
11739         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11740                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11741                 ret = -EINVAL;
11742         }
11743         mutex_unlock(&dev->struct_mutex);
11744
11745         return ret;
11746 }
11747
11748 static int
11749 intel_commit_cursor_plane(struct drm_plane *plane,
11750                           struct intel_plane_state *state)
11751 {
11752         struct drm_crtc *crtc = state->crtc;
11753         struct drm_framebuffer *fb = state->fb;
11754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11755         struct intel_plane *intel_plane = to_intel_plane(plane);
11756         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11757         struct drm_i915_gem_object *obj = intel_fb->obj;
11758         int crtc_w, crtc_h;
11759
11760         crtc->cursor_x = state->orig_dst.x1;
11761         crtc->cursor_y = state->orig_dst.y1;
11762
11763         intel_plane->crtc_x = state->orig_dst.x1;
11764         intel_plane->crtc_y = state->orig_dst.y1;
11765         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11766         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11767         intel_plane->src_x = state->orig_src.x1;
11768         intel_plane->src_y = state->orig_src.y1;
11769         intel_plane->src_w = drm_rect_width(&state->orig_src);
11770         intel_plane->src_h = drm_rect_height(&state->orig_src);
11771         intel_plane->obj = obj;
11772
11773         if (fb != crtc->cursor->fb) {
11774                 crtc_w = drm_rect_width(&state->orig_dst);
11775                 crtc_h = drm_rect_height(&state->orig_dst);
11776                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11777         } else {
11778                 intel_crtc_update_cursor(crtc, state->visible);
11779
11780                 intel_frontbuffer_flip(crtc->dev,
11781                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11782
11783                 return 0;
11784         }
11785 }
11786
11787 static int
11788 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11789                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11790                           unsigned int crtc_w, unsigned int crtc_h,
11791                           uint32_t src_x, uint32_t src_y,
11792                           uint32_t src_w, uint32_t src_h)
11793 {
11794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11795         struct intel_plane_state state;
11796         int ret;
11797
11798         state.crtc = crtc;
11799         state.fb = fb;
11800
11801         /* sample coordinates in 16.16 fixed point */
11802         state.src.x1 = src_x;
11803         state.src.x2 = src_x + src_w;
11804         state.src.y1 = src_y;
11805         state.src.y2 = src_y + src_h;
11806
11807         /* integer pixels */
11808         state.dst.x1 = crtc_x;
11809         state.dst.x2 = crtc_x + crtc_w;
11810         state.dst.y1 = crtc_y;
11811         state.dst.y2 = crtc_y + crtc_h;
11812
11813         state.clip.x1 = 0;
11814         state.clip.y1 = 0;
11815         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11816         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11817
11818         state.orig_src = state.src;
11819         state.orig_dst = state.dst;
11820
11821         ret = intel_check_cursor_plane(plane, &state);
11822         if (ret)
11823                 return ret;
11824
11825         return intel_commit_cursor_plane(plane, &state);
11826 }
11827
11828 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11829         .update_plane = intel_cursor_plane_update,
11830         .disable_plane = intel_cursor_plane_disable,
11831         .destroy = intel_plane_destroy,
11832         .set_property = intel_plane_set_property,
11833 };
11834
11835 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11836                                                    int pipe)
11837 {
11838         struct intel_plane *cursor;
11839
11840         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11841         if (cursor == NULL)
11842                 return NULL;
11843
11844         cursor->can_scale = false;
11845         cursor->max_downscale = 1;
11846         cursor->pipe = pipe;
11847         cursor->plane = pipe;
11848         cursor->rotation = BIT(DRM_ROTATE_0);
11849
11850         drm_universal_plane_init(dev, &cursor->base, 0,
11851                                  &intel_cursor_plane_funcs,
11852                                  intel_cursor_formats,
11853                                  ARRAY_SIZE(intel_cursor_formats),
11854                                  DRM_PLANE_TYPE_CURSOR);
11855
11856         if (INTEL_INFO(dev)->gen >= 4) {
11857                 if (!dev->mode_config.rotation_property)
11858                         dev->mode_config.rotation_property =
11859                                 drm_mode_create_rotation_property(dev,
11860                                                         BIT(DRM_ROTATE_0) |
11861                                                         BIT(DRM_ROTATE_180));
11862                 if (dev->mode_config.rotation_property)
11863                         drm_object_attach_property(&cursor->base.base,
11864                                 dev->mode_config.rotation_property,
11865                                 cursor->rotation);
11866         }
11867
11868         return &cursor->base;
11869 }
11870
11871 static void intel_crtc_init(struct drm_device *dev, int pipe)
11872 {
11873         struct drm_i915_private *dev_priv = dev->dev_private;
11874         struct intel_crtc *intel_crtc;
11875         struct drm_plane *primary = NULL;
11876         struct drm_plane *cursor = NULL;
11877         int i, ret;
11878
11879         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11880         if (intel_crtc == NULL)
11881                 return;
11882
11883         primary = intel_primary_plane_create(dev, pipe);
11884         if (!primary)
11885                 goto fail;
11886
11887         cursor = intel_cursor_plane_create(dev, pipe);
11888         if (!cursor)
11889                 goto fail;
11890
11891         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11892                                         cursor, &intel_crtc_funcs);
11893         if (ret)
11894                 goto fail;
11895
11896         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11897         for (i = 0; i < 256; i++) {
11898                 intel_crtc->lut_r[i] = i;
11899                 intel_crtc->lut_g[i] = i;
11900                 intel_crtc->lut_b[i] = i;
11901         }
11902
11903         /*
11904          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11905          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11906          */
11907         intel_crtc->pipe = pipe;
11908         intel_crtc->plane = pipe;
11909         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11910                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11911                 intel_crtc->plane = !pipe;
11912         }
11913
11914         intel_crtc->cursor_base = ~0;
11915         intel_crtc->cursor_cntl = ~0;
11916         intel_crtc->cursor_size = ~0;
11917
11918         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11919                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11920         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11921         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11922
11923         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11924
11925         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11926         return;
11927
11928 fail:
11929         if (primary)
11930                 drm_plane_cleanup(primary);
11931         if (cursor)
11932                 drm_plane_cleanup(cursor);
11933         kfree(intel_crtc);
11934 }
11935
11936 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11937 {
11938         struct drm_encoder *encoder = connector->base.encoder;
11939         struct drm_device *dev = connector->base.dev;
11940
11941         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11942
11943         if (!encoder)
11944                 return INVALID_PIPE;
11945
11946         return to_intel_crtc(encoder->crtc)->pipe;
11947 }
11948
11949 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11950                                 struct drm_file *file)
11951 {
11952         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11953         struct drm_crtc *drmmode_crtc;
11954         struct intel_crtc *crtc;
11955
11956         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11957                 return -ENODEV;
11958
11959         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11960
11961         if (!drmmode_crtc) {
11962                 DRM_ERROR("no such CRTC id\n");
11963                 return -ENOENT;
11964         }
11965
11966         crtc = to_intel_crtc(drmmode_crtc);
11967         pipe_from_crtc_id->pipe = crtc->pipe;
11968
11969         return 0;
11970 }
11971
11972 static int intel_encoder_clones(struct intel_encoder *encoder)
11973 {
11974         struct drm_device *dev = encoder->base.dev;
11975         struct intel_encoder *source_encoder;
11976         int index_mask = 0;
11977         int entry = 0;
11978
11979         for_each_intel_encoder(dev, source_encoder) {
11980                 if (encoders_cloneable(encoder, source_encoder))
11981                         index_mask |= (1 << entry);
11982
11983                 entry++;
11984         }
11985
11986         return index_mask;
11987 }
11988
11989 static bool has_edp_a(struct drm_device *dev)
11990 {
11991         struct drm_i915_private *dev_priv = dev->dev_private;
11992
11993         if (!IS_MOBILE(dev))
11994                 return false;
11995
11996         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11997                 return false;
11998
11999         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12000                 return false;
12001
12002         return true;
12003 }
12004
12005 const char *intel_output_name(int output)
12006 {
12007         static const char *names[] = {
12008                 [INTEL_OUTPUT_UNUSED] = "Unused",
12009                 [INTEL_OUTPUT_ANALOG] = "Analog",
12010                 [INTEL_OUTPUT_DVO] = "DVO",
12011                 [INTEL_OUTPUT_SDVO] = "SDVO",
12012                 [INTEL_OUTPUT_LVDS] = "LVDS",
12013                 [INTEL_OUTPUT_TVOUT] = "TV",
12014                 [INTEL_OUTPUT_HDMI] = "HDMI",
12015                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12016                 [INTEL_OUTPUT_EDP] = "eDP",
12017                 [INTEL_OUTPUT_DSI] = "DSI",
12018                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12019         };
12020
12021         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12022                 return "Invalid";
12023
12024         return names[output];
12025 }
12026
12027 static bool intel_crt_present(struct drm_device *dev)
12028 {
12029         struct drm_i915_private *dev_priv = dev->dev_private;
12030
12031         if (INTEL_INFO(dev)->gen >= 9)
12032                 return false;
12033
12034         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12035                 return false;
12036
12037         if (IS_CHERRYVIEW(dev))
12038                 return false;
12039
12040         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12041                 return false;
12042
12043         return true;
12044 }
12045
12046 static void intel_setup_outputs(struct drm_device *dev)
12047 {
12048         struct drm_i915_private *dev_priv = dev->dev_private;
12049         struct intel_encoder *encoder;
12050         bool dpd_is_edp = false;
12051
12052         intel_lvds_init(dev);
12053
12054         if (intel_crt_present(dev))
12055                 intel_crt_init(dev);
12056
12057         if (HAS_DDI(dev)) {
12058                 int found;
12059
12060                 /* Haswell uses DDI functions to detect digital outputs */
12061                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12062                 /* DDI A only supports eDP */
12063                 if (found)
12064                         intel_ddi_init(dev, PORT_A);
12065
12066                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12067                  * register */
12068                 found = I915_READ(SFUSE_STRAP);
12069
12070                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12071                         intel_ddi_init(dev, PORT_B);
12072                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12073                         intel_ddi_init(dev, PORT_C);
12074                 if (found & SFUSE_STRAP_DDID_DETECTED)
12075                         intel_ddi_init(dev, PORT_D);
12076         } else if (HAS_PCH_SPLIT(dev)) {
12077                 int found;
12078                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12079
12080                 if (has_edp_a(dev))
12081                         intel_dp_init(dev, DP_A, PORT_A);
12082
12083                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12084                         /* PCH SDVOB multiplex with HDMIB */
12085                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12086                         if (!found)
12087                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12088                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12089                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12090                 }
12091
12092                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12093                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12094
12095                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12096                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12097
12098                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12099                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12100
12101                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12102                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12103         } else if (IS_VALLEYVIEW(dev)) {
12104                 /*
12105                  * The DP_DETECTED bit is the latched state of the DDC
12106                  * SDA pin at boot. However since eDP doesn't require DDC
12107                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12108                  * eDP ports may have been muxed to an alternate function.
12109                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12110                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12111                  * detect eDP ports.
12112                  */
12113                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12114                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12115                                         PORT_B);
12116                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12117                     intel_dp_is_edp(dev, PORT_B))
12118                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12119
12120                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12121                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12122                                         PORT_C);
12123                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12124                     intel_dp_is_edp(dev, PORT_C))
12125                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12126
12127                 if (IS_CHERRYVIEW(dev)) {
12128                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12129                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12130                                                 PORT_D);
12131                         /* eDP not supported on port D, so don't check VBT */
12132                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12133                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12134                 }
12135
12136                 intel_dsi_init(dev);
12137         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12138                 bool found = false;
12139
12140                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12141                         DRM_DEBUG_KMS("probing SDVOB\n");
12142                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12143                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12144                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12145                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12146                         }
12147
12148                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12149                                 intel_dp_init(dev, DP_B, PORT_B);
12150                 }
12151
12152                 /* Before G4X SDVOC doesn't have its own detect register */
12153
12154                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12155                         DRM_DEBUG_KMS("probing SDVOC\n");
12156                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12157                 }
12158
12159                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12160
12161                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12162                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12163                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12164                         }
12165                         if (SUPPORTS_INTEGRATED_DP(dev))
12166                                 intel_dp_init(dev, DP_C, PORT_C);
12167                 }
12168
12169                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12170                     (I915_READ(DP_D) & DP_DETECTED))
12171                         intel_dp_init(dev, DP_D, PORT_D);
12172         } else if (IS_GEN2(dev))
12173                 intel_dvo_init(dev);
12174
12175         if (SUPPORTS_TV(dev))
12176                 intel_tv_init(dev);
12177
12178         intel_edp_psr_init(dev);
12179
12180         for_each_intel_encoder(dev, encoder) {
12181                 encoder->base.possible_crtcs = encoder->crtc_mask;
12182                 encoder->base.possible_clones =
12183                         intel_encoder_clones(encoder);
12184         }
12185
12186         intel_init_pch_refclk(dev);
12187
12188         drm_helper_move_panel_connectors_to_head(dev);
12189 }
12190
12191 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12192 {
12193         struct drm_device *dev = fb->dev;
12194         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12195
12196         drm_framebuffer_cleanup(fb);
12197         mutex_lock(&dev->struct_mutex);
12198         WARN_ON(!intel_fb->obj->framebuffer_references--);
12199         drm_gem_object_unreference(&intel_fb->obj->base);
12200         mutex_unlock(&dev->struct_mutex);
12201         kfree(intel_fb);
12202 }
12203
12204 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12205                                                 struct drm_file *file,
12206                                                 unsigned int *handle)
12207 {
12208         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12209         struct drm_i915_gem_object *obj = intel_fb->obj;
12210
12211         return drm_gem_handle_create(file, &obj->base, handle);
12212 }
12213
12214 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12215         .destroy = intel_user_framebuffer_destroy,
12216         .create_handle = intel_user_framebuffer_create_handle,
12217 };
12218
12219 static int intel_framebuffer_init(struct drm_device *dev,
12220                                   struct intel_framebuffer *intel_fb,
12221                                   struct drm_mode_fb_cmd2 *mode_cmd,
12222                                   struct drm_i915_gem_object *obj)
12223 {
12224         int aligned_height;
12225         int pitch_limit;
12226         int ret;
12227
12228         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12229
12230         if (obj->tiling_mode == I915_TILING_Y) {
12231                 DRM_DEBUG("hardware does not support tiling Y\n");
12232                 return -EINVAL;
12233         }
12234
12235         if (mode_cmd->pitches[0] & 63) {
12236                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12237                           mode_cmd->pitches[0]);
12238                 return -EINVAL;
12239         }
12240
12241         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12242                 pitch_limit = 32*1024;
12243         } else if (INTEL_INFO(dev)->gen >= 4) {
12244                 if (obj->tiling_mode)
12245                         pitch_limit = 16*1024;
12246                 else
12247                         pitch_limit = 32*1024;
12248         } else if (INTEL_INFO(dev)->gen >= 3) {
12249                 if (obj->tiling_mode)
12250                         pitch_limit = 8*1024;
12251                 else
12252                         pitch_limit = 16*1024;
12253         } else
12254                 /* XXX DSPC is limited to 4k tiled */
12255                 pitch_limit = 8*1024;
12256
12257         if (mode_cmd->pitches[0] > pitch_limit) {
12258                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12259                           obj->tiling_mode ? "tiled" : "linear",
12260                           mode_cmd->pitches[0], pitch_limit);
12261                 return -EINVAL;
12262         }
12263
12264         if (obj->tiling_mode != I915_TILING_NONE &&
12265             mode_cmd->pitches[0] != obj->stride) {
12266                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12267                           mode_cmd->pitches[0], obj->stride);
12268                 return -EINVAL;
12269         }
12270
12271         /* Reject formats not supported by any plane early. */
12272         switch (mode_cmd->pixel_format) {
12273         case DRM_FORMAT_C8:
12274         case DRM_FORMAT_RGB565:
12275         case DRM_FORMAT_XRGB8888:
12276         case DRM_FORMAT_ARGB8888:
12277                 break;
12278         case DRM_FORMAT_XRGB1555:
12279         case DRM_FORMAT_ARGB1555:
12280                 if (INTEL_INFO(dev)->gen > 3) {
12281                         DRM_DEBUG("unsupported pixel format: %s\n",
12282                                   drm_get_format_name(mode_cmd->pixel_format));
12283                         return -EINVAL;
12284                 }
12285                 break;
12286         case DRM_FORMAT_XBGR8888:
12287         case DRM_FORMAT_ABGR8888:
12288         case DRM_FORMAT_XRGB2101010:
12289         case DRM_FORMAT_ARGB2101010:
12290         case DRM_FORMAT_XBGR2101010:
12291         case DRM_FORMAT_ABGR2101010:
12292                 if (INTEL_INFO(dev)->gen < 4) {
12293                         DRM_DEBUG("unsupported pixel format: %s\n",
12294                                   drm_get_format_name(mode_cmd->pixel_format));
12295                         return -EINVAL;
12296                 }
12297                 break;
12298         case DRM_FORMAT_YUYV:
12299         case DRM_FORMAT_UYVY:
12300         case DRM_FORMAT_YVYU:
12301         case DRM_FORMAT_VYUY:
12302                 if (INTEL_INFO(dev)->gen < 5) {
12303                         DRM_DEBUG("unsupported pixel format: %s\n",
12304                                   drm_get_format_name(mode_cmd->pixel_format));
12305                         return -EINVAL;
12306                 }
12307                 break;
12308         default:
12309                 DRM_DEBUG("unsupported pixel format: %s\n",
12310                           drm_get_format_name(mode_cmd->pixel_format));
12311                 return -EINVAL;
12312         }
12313
12314         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12315         if (mode_cmd->offsets[0] != 0)
12316                 return -EINVAL;
12317
12318         aligned_height = intel_align_height(dev, mode_cmd->height,
12319                                             obj->tiling_mode);
12320         /* FIXME drm helper for size checks (especially planar formats)? */
12321         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12322                 return -EINVAL;
12323
12324         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12325         intel_fb->obj = obj;
12326         intel_fb->obj->framebuffer_references++;
12327
12328         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12329         if (ret) {
12330                 DRM_ERROR("framebuffer init failed %d\n", ret);
12331                 return ret;
12332         }
12333
12334         return 0;
12335 }
12336
12337 static struct drm_framebuffer *
12338 intel_user_framebuffer_create(struct drm_device *dev,
12339                               struct drm_file *filp,
12340                               struct drm_mode_fb_cmd2 *mode_cmd)
12341 {
12342         struct drm_i915_gem_object *obj;
12343
12344         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12345                                                 mode_cmd->handles[0]));
12346         if (&obj->base == NULL)
12347                 return ERR_PTR(-ENOENT);
12348
12349         return intel_framebuffer_create(dev, mode_cmd, obj);
12350 }
12351
12352 #ifndef CONFIG_DRM_I915_FBDEV
12353 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12354 {
12355 }
12356 #endif
12357
12358 static const struct drm_mode_config_funcs intel_mode_funcs = {
12359         .fb_create = intel_user_framebuffer_create,
12360         .output_poll_changed = intel_fbdev_output_poll_changed,
12361 };
12362
12363 /* Set up chip specific display functions */
12364 static void intel_init_display(struct drm_device *dev)
12365 {
12366         struct drm_i915_private *dev_priv = dev->dev_private;
12367
12368         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12369                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12370         else if (IS_CHERRYVIEW(dev))
12371                 dev_priv->display.find_dpll = chv_find_best_dpll;
12372         else if (IS_VALLEYVIEW(dev))
12373                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12374         else if (IS_PINEVIEW(dev))
12375                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12376         else
12377                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12378
12379         if (HAS_DDI(dev)) {
12380                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12381                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12382                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12383                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12384                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12385                 dev_priv->display.off = ironlake_crtc_off;
12386                 if (INTEL_INFO(dev)->gen >= 9)
12387                         dev_priv->display.update_primary_plane =
12388                                 skylake_update_primary_plane;
12389                 else
12390                         dev_priv->display.update_primary_plane =
12391                                 ironlake_update_primary_plane;
12392         } else if (HAS_PCH_SPLIT(dev)) {
12393                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12394                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12395                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12396                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12397                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12398                 dev_priv->display.off = ironlake_crtc_off;
12399                 dev_priv->display.update_primary_plane =
12400                         ironlake_update_primary_plane;
12401         } else if (IS_VALLEYVIEW(dev)) {
12402                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12403                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12404                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12405                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12406                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12407                 dev_priv->display.off = i9xx_crtc_off;
12408                 dev_priv->display.update_primary_plane =
12409                         i9xx_update_primary_plane;
12410         } else {
12411                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12412                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12413                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12414                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12415                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12416                 dev_priv->display.off = i9xx_crtc_off;
12417                 dev_priv->display.update_primary_plane =
12418                         i9xx_update_primary_plane;
12419         }
12420
12421         /* Returns the core display clock speed */
12422         if (IS_VALLEYVIEW(dev))
12423                 dev_priv->display.get_display_clock_speed =
12424                         valleyview_get_display_clock_speed;
12425         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12426                 dev_priv->display.get_display_clock_speed =
12427                         i945_get_display_clock_speed;
12428         else if (IS_I915G(dev))
12429                 dev_priv->display.get_display_clock_speed =
12430                         i915_get_display_clock_speed;
12431         else if (IS_I945GM(dev) || IS_845G(dev))
12432                 dev_priv->display.get_display_clock_speed =
12433                         i9xx_misc_get_display_clock_speed;
12434         else if (IS_PINEVIEW(dev))
12435                 dev_priv->display.get_display_clock_speed =
12436                         pnv_get_display_clock_speed;
12437         else if (IS_I915GM(dev))
12438                 dev_priv->display.get_display_clock_speed =
12439                         i915gm_get_display_clock_speed;
12440         else if (IS_I865G(dev))
12441                 dev_priv->display.get_display_clock_speed =
12442                         i865_get_display_clock_speed;
12443         else if (IS_I85X(dev))
12444                 dev_priv->display.get_display_clock_speed =
12445                         i855_get_display_clock_speed;
12446         else /* 852, 830 */
12447                 dev_priv->display.get_display_clock_speed =
12448                         i830_get_display_clock_speed;
12449
12450         if (IS_GEN5(dev)) {
12451                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12452         } else if (IS_GEN6(dev)) {
12453                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12454                 dev_priv->display.modeset_global_resources =
12455                         snb_modeset_global_resources;
12456         } else if (IS_IVYBRIDGE(dev)) {
12457                 /* FIXME: detect B0+ stepping and use auto training */
12458                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12459                 dev_priv->display.modeset_global_resources =
12460                         ivb_modeset_global_resources;
12461         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12462                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12463                 dev_priv->display.modeset_global_resources =
12464                         haswell_modeset_global_resources;
12465         } else if (IS_VALLEYVIEW(dev)) {
12466                 dev_priv->display.modeset_global_resources =
12467                         valleyview_modeset_global_resources;
12468         } else if (INTEL_INFO(dev)->gen >= 9) {
12469                 dev_priv->display.modeset_global_resources =
12470                         haswell_modeset_global_resources;
12471         }
12472
12473         /* Default just returns -ENODEV to indicate unsupported */
12474         dev_priv->display.queue_flip = intel_default_queue_flip;
12475
12476         switch (INTEL_INFO(dev)->gen) {
12477         case 2:
12478                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12479                 break;
12480
12481         case 3:
12482                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12483                 break;
12484
12485         case 4:
12486         case 5:
12487                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12488                 break;
12489
12490         case 6:
12491                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12492                 break;
12493         case 7:
12494         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12495                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12496                 break;
12497         }
12498
12499         intel_panel_init_backlight_funcs(dev);
12500
12501         mutex_init(&dev_priv->pps_mutex);
12502 }
12503
12504 /*
12505  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12506  * resume, or other times.  This quirk makes sure that's the case for
12507  * affected systems.
12508  */
12509 static void quirk_pipea_force(struct drm_device *dev)
12510 {
12511         struct drm_i915_private *dev_priv = dev->dev_private;
12512
12513         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12514         DRM_INFO("applying pipe a force quirk\n");
12515 }
12516
12517 static void quirk_pipeb_force(struct drm_device *dev)
12518 {
12519         struct drm_i915_private *dev_priv = dev->dev_private;
12520
12521         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12522         DRM_INFO("applying pipe b force quirk\n");
12523 }
12524
12525 /*
12526  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12527  */
12528 static void quirk_ssc_force_disable(struct drm_device *dev)
12529 {
12530         struct drm_i915_private *dev_priv = dev->dev_private;
12531         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12532         DRM_INFO("applying lvds SSC disable quirk\n");
12533 }
12534
12535 /*
12536  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12537  * brightness value
12538  */
12539 static void quirk_invert_brightness(struct drm_device *dev)
12540 {
12541         struct drm_i915_private *dev_priv = dev->dev_private;
12542         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12543         DRM_INFO("applying inverted panel brightness quirk\n");
12544 }
12545
12546 /* Some VBT's incorrectly indicate no backlight is present */
12547 static void quirk_backlight_present(struct drm_device *dev)
12548 {
12549         struct drm_i915_private *dev_priv = dev->dev_private;
12550         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12551         DRM_INFO("applying backlight present quirk\n");
12552 }
12553
12554 struct intel_quirk {
12555         int device;
12556         int subsystem_vendor;
12557         int subsystem_device;
12558         void (*hook)(struct drm_device *dev);
12559 };
12560
12561 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12562 struct intel_dmi_quirk {
12563         void (*hook)(struct drm_device *dev);
12564         const struct dmi_system_id (*dmi_id_list)[];
12565 };
12566
12567 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12568 {
12569         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12570         return 1;
12571 }
12572
12573 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12574         {
12575                 .dmi_id_list = &(const struct dmi_system_id[]) {
12576                         {
12577                                 .callback = intel_dmi_reverse_brightness,
12578                                 .ident = "NCR Corporation",
12579                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12580                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12581                                 },
12582                         },
12583                         { }  /* terminating entry */
12584                 },
12585                 .hook = quirk_invert_brightness,
12586         },
12587 };
12588
12589 static struct intel_quirk intel_quirks[] = {
12590         /* HP Mini needs pipe A force quirk (LP: #322104) */
12591         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12592
12593         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12594         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12595
12596         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12597         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12598
12599         /* 830 needs to leave pipe A & dpll A up */
12600         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12601
12602         /* 830 needs to leave pipe B & dpll B up */
12603         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12604
12605         /* Lenovo U160 cannot use SSC on LVDS */
12606         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12607
12608         /* Sony Vaio Y cannot use SSC on LVDS */
12609         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12610
12611         /* Acer Aspire 5734Z must invert backlight brightness */
12612         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12613
12614         /* Acer/eMachines G725 */
12615         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12616
12617         /* Acer/eMachines e725 */
12618         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12619
12620         /* Acer/Packard Bell NCL20 */
12621         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12622
12623         /* Acer Aspire 4736Z */
12624         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12625
12626         /* Acer Aspire 5336 */
12627         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12628
12629         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12630         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12631
12632         /* Acer C720 Chromebook (Core i3 4005U) */
12633         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12634
12635         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12636         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12637
12638         /* HP Chromebook 14 (Celeron 2955U) */
12639         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12640 };
12641
12642 static void intel_init_quirks(struct drm_device *dev)
12643 {
12644         struct pci_dev *d = dev->pdev;
12645         int i;
12646
12647         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12648                 struct intel_quirk *q = &intel_quirks[i];
12649
12650                 if (d->device == q->device &&
12651                     (d->subsystem_vendor == q->subsystem_vendor ||
12652                      q->subsystem_vendor == PCI_ANY_ID) &&
12653                     (d->subsystem_device == q->subsystem_device ||
12654                      q->subsystem_device == PCI_ANY_ID))
12655                         q->hook(dev);
12656         }
12657         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12658                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12659                         intel_dmi_quirks[i].hook(dev);
12660         }
12661 }
12662
12663 /* Disable the VGA plane that we never use */
12664 static void i915_disable_vga(struct drm_device *dev)
12665 {
12666         struct drm_i915_private *dev_priv = dev->dev_private;
12667         u8 sr1;
12668         u32 vga_reg = i915_vgacntrl_reg(dev);
12669
12670         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12671         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12672         outb(SR01, VGA_SR_INDEX);
12673         sr1 = inb(VGA_SR_DATA);
12674         outb(sr1 | 1<<5, VGA_SR_DATA);
12675         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12676         udelay(300);
12677
12678         /*
12679          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12680          * from S3 without preserving (some of?) the other bits.
12681          */
12682         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12683         POSTING_READ(vga_reg);
12684 }
12685
12686 void intel_modeset_init_hw(struct drm_device *dev)
12687 {
12688         intel_prepare_ddi(dev);
12689
12690         if (IS_VALLEYVIEW(dev))
12691                 vlv_update_cdclk(dev);
12692
12693         intel_init_clock_gating(dev);
12694
12695         intel_enable_gt_powersave(dev);
12696 }
12697
12698 void intel_modeset_init(struct drm_device *dev)
12699 {
12700         struct drm_i915_private *dev_priv = dev->dev_private;
12701         int sprite, ret;
12702         enum pipe pipe;
12703         struct intel_crtc *crtc;
12704
12705         drm_mode_config_init(dev);
12706
12707         dev->mode_config.min_width = 0;
12708         dev->mode_config.min_height = 0;
12709
12710         dev->mode_config.preferred_depth = 24;
12711         dev->mode_config.prefer_shadow = 1;
12712
12713         dev->mode_config.funcs = &intel_mode_funcs;
12714
12715         intel_init_quirks(dev);
12716
12717         intel_init_pm(dev);
12718
12719         if (INTEL_INFO(dev)->num_pipes == 0)
12720                 return;
12721
12722         intel_init_display(dev);
12723         intel_init_audio(dev);
12724
12725         if (IS_GEN2(dev)) {
12726                 dev->mode_config.max_width = 2048;
12727                 dev->mode_config.max_height = 2048;
12728         } else if (IS_GEN3(dev)) {
12729                 dev->mode_config.max_width = 4096;
12730                 dev->mode_config.max_height = 4096;
12731         } else {
12732                 dev->mode_config.max_width = 8192;
12733                 dev->mode_config.max_height = 8192;
12734         }
12735
12736         if (IS_845G(dev) || IS_I865G(dev)) {
12737                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12738                 dev->mode_config.cursor_height = 1023;
12739         } else if (IS_GEN2(dev)) {
12740                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12741                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12742         } else {
12743                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12744                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12745         }
12746
12747         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12748
12749         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12750                       INTEL_INFO(dev)->num_pipes,
12751                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12752
12753         for_each_pipe(dev_priv, pipe) {
12754                 intel_crtc_init(dev, pipe);
12755                 for_each_sprite(pipe, sprite) {
12756                         ret = intel_plane_init(dev, pipe, sprite);
12757                         if (ret)
12758                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12759                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12760                 }
12761         }
12762
12763         intel_init_dpio(dev);
12764
12765         intel_shared_dpll_init(dev);
12766
12767         /* save the BIOS value before clobbering it */
12768         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12769         /* Just disable it once at startup */
12770         i915_disable_vga(dev);
12771         intel_setup_outputs(dev);
12772
12773         /* Just in case the BIOS is doing something questionable. */
12774         intel_disable_fbc(dev);
12775
12776         drm_modeset_lock_all(dev);
12777         intel_modeset_setup_hw_state(dev, false);
12778         drm_modeset_unlock_all(dev);
12779
12780         for_each_intel_crtc(dev, crtc) {
12781                 if (!crtc->active)
12782                         continue;
12783
12784                 /*
12785                  * Note that reserving the BIOS fb up front prevents us
12786                  * from stuffing other stolen allocations like the ring
12787                  * on top.  This prevents some ugliness at boot time, and
12788                  * can even allow for smooth boot transitions if the BIOS
12789                  * fb is large enough for the active pipe configuration.
12790                  */
12791                 if (dev_priv->display.get_plane_config) {
12792                         dev_priv->display.get_plane_config(crtc,
12793                                                            &crtc->plane_config);
12794                         /*
12795                          * If the fb is shared between multiple heads, we'll
12796                          * just get the first one.
12797                          */
12798                         intel_find_plane_obj(crtc, &crtc->plane_config);
12799                 }
12800         }
12801 }
12802
12803 static void intel_enable_pipe_a(struct drm_device *dev)
12804 {
12805         struct intel_connector *connector;
12806         struct drm_connector *crt = NULL;
12807         struct intel_load_detect_pipe load_detect_temp;
12808         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12809
12810         /* We can't just switch on the pipe A, we need to set things up with a
12811          * proper mode and output configuration. As a gross hack, enable pipe A
12812          * by enabling the load detect pipe once. */
12813         list_for_each_entry(connector,
12814                             &dev->mode_config.connector_list,
12815                             base.head) {
12816                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12817                         crt = &connector->base;
12818                         break;
12819                 }
12820         }
12821
12822         if (!crt)
12823                 return;
12824
12825         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12826                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12827 }
12828
12829 static bool
12830 intel_check_plane_mapping(struct intel_crtc *crtc)
12831 {
12832         struct drm_device *dev = crtc->base.dev;
12833         struct drm_i915_private *dev_priv = dev->dev_private;
12834         u32 reg, val;
12835
12836         if (INTEL_INFO(dev)->num_pipes == 1)
12837                 return true;
12838
12839         reg = DSPCNTR(!crtc->plane);
12840         val = I915_READ(reg);
12841
12842         if ((val & DISPLAY_PLANE_ENABLE) &&
12843             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12844                 return false;
12845
12846         return true;
12847 }
12848
12849 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12850 {
12851         struct drm_device *dev = crtc->base.dev;
12852         struct drm_i915_private *dev_priv = dev->dev_private;
12853         u32 reg;
12854
12855         /* Clear any frame start delays used for debugging left by the BIOS */
12856         reg = PIPECONF(crtc->config.cpu_transcoder);
12857         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12858
12859         /* restore vblank interrupts to correct state */
12860         if (crtc->active) {
12861                 update_scanline_offset(crtc);
12862                 drm_vblank_on(dev, crtc->pipe);
12863         } else
12864                 drm_vblank_off(dev, crtc->pipe);
12865
12866         /* We need to sanitize the plane -> pipe mapping first because this will
12867          * disable the crtc (and hence change the state) if it is wrong. Note
12868          * that gen4+ has a fixed plane -> pipe mapping.  */
12869         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12870                 struct intel_connector *connector;
12871                 bool plane;
12872
12873                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12874                               crtc->base.base.id);
12875
12876                 /* Pipe has the wrong plane attached and the plane is active.
12877                  * Temporarily change the plane mapping and disable everything
12878                  * ...  */
12879                 plane = crtc->plane;
12880                 crtc->plane = !plane;
12881                 crtc->primary_enabled = true;
12882                 dev_priv->display.crtc_disable(&crtc->base);
12883                 crtc->plane = plane;
12884
12885                 /* ... and break all links. */
12886                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12887                                     base.head) {
12888                         if (connector->encoder->base.crtc != &crtc->base)
12889                                 continue;
12890
12891                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12892                         connector->base.encoder = NULL;
12893                 }
12894                 /* multiple connectors may have the same encoder:
12895                  *  handle them and break crtc link separately */
12896                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12897                                     base.head)
12898                         if (connector->encoder->base.crtc == &crtc->base) {
12899                                 connector->encoder->base.crtc = NULL;
12900                                 connector->encoder->connectors_active = false;
12901                         }
12902
12903                 WARN_ON(crtc->active);
12904                 crtc->base.enabled = false;
12905         }
12906
12907         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12908             crtc->pipe == PIPE_A && !crtc->active) {
12909                 /* BIOS forgot to enable pipe A, this mostly happens after
12910                  * resume. Force-enable the pipe to fix this, the update_dpms
12911                  * call below we restore the pipe to the right state, but leave
12912                  * the required bits on. */
12913                 intel_enable_pipe_a(dev);
12914         }
12915
12916         /* Adjust the state of the output pipe according to whether we
12917          * have active connectors/encoders. */
12918         intel_crtc_update_dpms(&crtc->base);
12919
12920         if (crtc->active != crtc->base.enabled) {
12921                 struct intel_encoder *encoder;
12922
12923                 /* This can happen either due to bugs in the get_hw_state
12924                  * functions or because the pipe is force-enabled due to the
12925                  * pipe A quirk. */
12926                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12927                               crtc->base.base.id,
12928                               crtc->base.enabled ? "enabled" : "disabled",
12929                               crtc->active ? "enabled" : "disabled");
12930
12931                 crtc->base.enabled = crtc->active;
12932
12933                 /* Because we only establish the connector -> encoder ->
12934                  * crtc links if something is active, this means the
12935                  * crtc is now deactivated. Break the links. connector
12936                  * -> encoder links are only establish when things are
12937                  *  actually up, hence no need to break them. */
12938                 WARN_ON(crtc->active);
12939
12940                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12941                         WARN_ON(encoder->connectors_active);
12942                         encoder->base.crtc = NULL;
12943                 }
12944         }
12945
12946         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12947                 /*
12948                  * We start out with underrun reporting disabled to avoid races.
12949                  * For correct bookkeeping mark this on active crtcs.
12950                  *
12951                  * Also on gmch platforms we dont have any hardware bits to
12952                  * disable the underrun reporting. Which means we need to start
12953                  * out with underrun reporting disabled also on inactive pipes,
12954                  * since otherwise we'll complain about the garbage we read when
12955                  * e.g. coming up after runtime pm.
12956                  *
12957                  * No protection against concurrent access is required - at
12958                  * worst a fifo underrun happens which also sets this to false.
12959                  */
12960                 crtc->cpu_fifo_underrun_disabled = true;
12961                 crtc->pch_fifo_underrun_disabled = true;
12962         }
12963 }
12964
12965 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12966 {
12967         struct intel_connector *connector;
12968         struct drm_device *dev = encoder->base.dev;
12969
12970         /* We need to check both for a crtc link (meaning that the
12971          * encoder is active and trying to read from a pipe) and the
12972          * pipe itself being active. */
12973         bool has_active_crtc = encoder->base.crtc &&
12974                 to_intel_crtc(encoder->base.crtc)->active;
12975
12976         if (encoder->connectors_active && !has_active_crtc) {
12977                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12978                               encoder->base.base.id,
12979                               encoder->base.name);
12980
12981                 /* Connector is active, but has no active pipe. This is
12982                  * fallout from our resume register restoring. Disable
12983                  * the encoder manually again. */
12984                 if (encoder->base.crtc) {
12985                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12986                                       encoder->base.base.id,
12987                                       encoder->base.name);
12988                         encoder->disable(encoder);
12989                         if (encoder->post_disable)
12990                                 encoder->post_disable(encoder);
12991                 }
12992                 encoder->base.crtc = NULL;
12993                 encoder->connectors_active = false;
12994
12995                 /* Inconsistent output/port/pipe state happens presumably due to
12996                  * a bug in one of the get_hw_state functions. Or someplace else
12997                  * in our code, like the register restore mess on resume. Clamp
12998                  * things to off as a safer default. */
12999                 list_for_each_entry(connector,
13000                                     &dev->mode_config.connector_list,
13001                                     base.head) {
13002                         if (connector->encoder != encoder)
13003                                 continue;
13004                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13005                         connector->base.encoder = NULL;
13006                 }
13007         }
13008         /* Enabled encoders without active connectors will be fixed in
13009          * the crtc fixup. */
13010 }
13011
13012 void i915_redisable_vga_power_on(struct drm_device *dev)
13013 {
13014         struct drm_i915_private *dev_priv = dev->dev_private;
13015         u32 vga_reg = i915_vgacntrl_reg(dev);
13016
13017         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13018                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13019                 i915_disable_vga(dev);
13020         }
13021 }
13022
13023 void i915_redisable_vga(struct drm_device *dev)
13024 {
13025         struct drm_i915_private *dev_priv = dev->dev_private;
13026
13027         /* This function can be called both from intel_modeset_setup_hw_state or
13028          * at a very early point in our resume sequence, where the power well
13029          * structures are not yet restored. Since this function is at a very
13030          * paranoid "someone might have enabled VGA while we were not looking"
13031          * level, just check if the power well is enabled instead of trying to
13032          * follow the "don't touch the power well if we don't need it" policy
13033          * the rest of the driver uses. */
13034         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13035                 return;
13036
13037         i915_redisable_vga_power_on(dev);
13038 }
13039
13040 static bool primary_get_hw_state(struct intel_crtc *crtc)
13041 {
13042         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13043
13044         if (!crtc->active)
13045                 return false;
13046
13047         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13048 }
13049
13050 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13051 {
13052         struct drm_i915_private *dev_priv = dev->dev_private;
13053         enum pipe pipe;
13054         struct intel_crtc *crtc;
13055         struct intel_encoder *encoder;
13056         struct intel_connector *connector;
13057         int i;
13058
13059         for_each_intel_crtc(dev, crtc) {
13060                 memset(&crtc->config, 0, sizeof(crtc->config));
13061
13062                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13063
13064                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13065                                                                  &crtc->config);
13066
13067                 crtc->base.enabled = crtc->active;
13068                 crtc->primary_enabled = primary_get_hw_state(crtc);
13069
13070                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13071                               crtc->base.base.id,
13072                               crtc->active ? "enabled" : "disabled");
13073         }
13074
13075         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13076                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13077
13078                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13079                 pll->active = 0;
13080                 for_each_intel_crtc(dev, crtc) {
13081                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13082                                 pll->active++;
13083                 }
13084                 pll->refcount = pll->active;
13085
13086                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13087                               pll->name, pll->refcount, pll->on);
13088
13089                 if (pll->refcount)
13090                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13091         }
13092
13093         for_each_intel_encoder(dev, encoder) {
13094                 pipe = 0;
13095
13096                 if (encoder->get_hw_state(encoder, &pipe)) {
13097                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13098                         encoder->base.crtc = &crtc->base;
13099                         encoder->get_config(encoder, &crtc->config);
13100                 } else {
13101                         encoder->base.crtc = NULL;
13102                 }
13103
13104                 encoder->connectors_active = false;
13105                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13106                               encoder->base.base.id,
13107                               encoder->base.name,
13108                               encoder->base.crtc ? "enabled" : "disabled",
13109                               pipe_name(pipe));
13110         }
13111
13112         list_for_each_entry(connector, &dev->mode_config.connector_list,
13113                             base.head) {
13114                 if (connector->get_hw_state(connector)) {
13115                         connector->base.dpms = DRM_MODE_DPMS_ON;
13116                         connector->encoder->connectors_active = true;
13117                         connector->base.encoder = &connector->encoder->base;
13118                 } else {
13119                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13120                         connector->base.encoder = NULL;
13121                 }
13122                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13123                               connector->base.base.id,
13124                               connector->base.name,
13125                               connector->base.encoder ? "enabled" : "disabled");
13126         }
13127 }
13128
13129 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13130  * and i915 state tracking structures. */
13131 void intel_modeset_setup_hw_state(struct drm_device *dev,
13132                                   bool force_restore)
13133 {
13134         struct drm_i915_private *dev_priv = dev->dev_private;
13135         enum pipe pipe;
13136         struct intel_crtc *crtc;
13137         struct intel_encoder *encoder;
13138         int i;
13139
13140         intel_modeset_readout_hw_state(dev);
13141
13142         /*
13143          * Now that we have the config, copy it to each CRTC struct
13144          * Note that this could go away if we move to using crtc_config
13145          * checking everywhere.
13146          */
13147         for_each_intel_crtc(dev, crtc) {
13148                 if (crtc->active && i915.fastboot) {
13149                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13150                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13151                                       crtc->base.base.id);
13152                         drm_mode_debug_printmodeline(&crtc->base.mode);
13153                 }
13154         }
13155
13156         /* HW state is read out, now we need to sanitize this mess. */
13157         for_each_intel_encoder(dev, encoder) {
13158                 intel_sanitize_encoder(encoder);
13159         }
13160
13161         for_each_pipe(dev_priv, pipe) {
13162                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13163                 intel_sanitize_crtc(crtc);
13164                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13165         }
13166
13167         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13168                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13169
13170                 if (!pll->on || pll->active)
13171                         continue;
13172
13173                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13174
13175                 pll->disable(dev_priv, pll);
13176                 pll->on = false;
13177         }
13178
13179         if (HAS_PCH_SPLIT(dev))
13180                 ilk_wm_get_hw_state(dev);
13181
13182         if (force_restore) {
13183                 i915_redisable_vga(dev);
13184
13185                 /*
13186                  * We need to use raw interfaces for restoring state to avoid
13187                  * checking (bogus) intermediate states.
13188                  */
13189                 for_each_pipe(dev_priv, pipe) {
13190                         struct drm_crtc *crtc =
13191                                 dev_priv->pipe_to_crtc_mapping[pipe];
13192
13193                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13194                                          crtc->primary->fb);
13195                 }
13196         } else {
13197                 intel_modeset_update_staged_output_state(dev);
13198         }
13199
13200         intel_modeset_check_state(dev);
13201 }
13202
13203 void intel_modeset_gem_init(struct drm_device *dev)
13204 {
13205         struct drm_crtc *c;
13206         struct drm_i915_gem_object *obj;
13207
13208         mutex_lock(&dev->struct_mutex);
13209         intel_init_gt_powersave(dev);
13210         mutex_unlock(&dev->struct_mutex);
13211
13212         intel_modeset_init_hw(dev);
13213
13214         intel_setup_overlay(dev);
13215
13216         /*
13217          * Make sure any fbs we allocated at startup are properly
13218          * pinned & fenced.  When we do the allocation it's too early
13219          * for this.
13220          */
13221         mutex_lock(&dev->struct_mutex);
13222         for_each_crtc(dev, c) {
13223                 obj = intel_fb_obj(c->primary->fb);
13224                 if (obj == NULL)
13225                         continue;
13226
13227                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13228                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13229                                   to_intel_crtc(c)->pipe);
13230                         drm_framebuffer_unreference(c->primary->fb);
13231                         c->primary->fb = NULL;
13232                 }
13233         }
13234         mutex_unlock(&dev->struct_mutex);
13235 }
13236
13237 void intel_connector_unregister(struct intel_connector *intel_connector)
13238 {
13239         struct drm_connector *connector = &intel_connector->base;
13240
13241         intel_panel_destroy_backlight(connector);
13242         drm_connector_unregister(connector);
13243 }
13244
13245 void intel_modeset_cleanup(struct drm_device *dev)
13246 {
13247         struct drm_i915_private *dev_priv = dev->dev_private;
13248         struct drm_connector *connector;
13249
13250         /*
13251          * Interrupts and polling as the first thing to avoid creating havoc.
13252          * Too much stuff here (turning of rps, connectors, ...) would
13253          * experience fancy races otherwise.
13254          */
13255         intel_irq_uninstall(dev_priv);
13256
13257         /*
13258          * Due to the hpd irq storm handling the hotplug work can re-arm the
13259          * poll handlers. Hence disable polling after hpd handling is shut down.
13260          */
13261         drm_kms_helper_poll_fini(dev);
13262
13263         mutex_lock(&dev->struct_mutex);
13264
13265         intel_unregister_dsm_handler();
13266
13267         intel_disable_fbc(dev);
13268
13269         intel_disable_gt_powersave(dev);
13270
13271         ironlake_teardown_rc6(dev);
13272
13273         mutex_unlock(&dev->struct_mutex);
13274
13275         /* flush any delayed tasks or pending work */
13276         flush_scheduled_work();
13277
13278         /* destroy the backlight and sysfs files before encoders/connectors */
13279         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13280                 struct intel_connector *intel_connector;
13281
13282                 intel_connector = to_intel_connector(connector);
13283                 intel_connector->unregister(intel_connector);
13284         }
13285
13286         drm_mode_config_cleanup(dev);
13287
13288         intel_cleanup_overlay(dev);
13289
13290         mutex_lock(&dev->struct_mutex);
13291         intel_cleanup_gt_powersave(dev);
13292         mutex_unlock(&dev->struct_mutex);
13293 }
13294
13295 /*
13296  * Return which encoder is currently attached for connector.
13297  */
13298 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13299 {
13300         return &intel_attached_encoder(connector)->base;
13301 }
13302
13303 void intel_connector_attach_encoder(struct intel_connector *connector,
13304                                     struct intel_encoder *encoder)
13305 {
13306         connector->encoder = encoder;
13307         drm_mode_connector_attach_encoder(&connector->base,
13308                                           &encoder->base);
13309 }
13310
13311 /*
13312  * set vga decode state - true == enable VGA decode
13313  */
13314 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13315 {
13316         struct drm_i915_private *dev_priv = dev->dev_private;
13317         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13318         u16 gmch_ctrl;
13319
13320         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13321                 DRM_ERROR("failed to read control word\n");
13322                 return -EIO;
13323         }
13324
13325         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13326                 return 0;
13327
13328         if (state)
13329                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13330         else
13331                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13332
13333         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13334                 DRM_ERROR("failed to write control word\n");
13335                 return -EIO;
13336         }
13337
13338         return 0;
13339 }
13340
13341 struct intel_display_error_state {
13342
13343         u32 power_well_driver;
13344
13345         int num_transcoders;
13346
13347         struct intel_cursor_error_state {
13348                 u32 control;
13349                 u32 position;
13350                 u32 base;
13351                 u32 size;
13352         } cursor[I915_MAX_PIPES];
13353
13354         struct intel_pipe_error_state {
13355                 bool power_domain_on;
13356                 u32 source;
13357                 u32 stat;
13358         } pipe[I915_MAX_PIPES];
13359
13360         struct intel_plane_error_state {
13361                 u32 control;
13362                 u32 stride;
13363                 u32 size;
13364                 u32 pos;
13365                 u32 addr;
13366                 u32 surface;
13367                 u32 tile_offset;
13368         } plane[I915_MAX_PIPES];
13369
13370         struct intel_transcoder_error_state {
13371                 bool power_domain_on;
13372                 enum transcoder cpu_transcoder;
13373
13374                 u32 conf;
13375
13376                 u32 htotal;
13377                 u32 hblank;
13378                 u32 hsync;
13379                 u32 vtotal;
13380                 u32 vblank;
13381                 u32 vsync;
13382         } transcoder[4];
13383 };
13384
13385 struct intel_display_error_state *
13386 intel_display_capture_error_state(struct drm_device *dev)
13387 {
13388         struct drm_i915_private *dev_priv = dev->dev_private;
13389         struct intel_display_error_state *error;
13390         int transcoders[] = {
13391                 TRANSCODER_A,
13392                 TRANSCODER_B,
13393                 TRANSCODER_C,
13394                 TRANSCODER_EDP,
13395         };
13396         int i;
13397
13398         if (INTEL_INFO(dev)->num_pipes == 0)
13399                 return NULL;
13400
13401         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13402         if (error == NULL)
13403                 return NULL;
13404
13405         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13406                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13407
13408         for_each_pipe(dev_priv, i) {
13409                 error->pipe[i].power_domain_on =
13410                         __intel_display_power_is_enabled(dev_priv,
13411                                                          POWER_DOMAIN_PIPE(i));
13412                 if (!error->pipe[i].power_domain_on)
13413                         continue;
13414
13415                 error->cursor[i].control = I915_READ(CURCNTR(i));
13416                 error->cursor[i].position = I915_READ(CURPOS(i));
13417                 error->cursor[i].base = I915_READ(CURBASE(i));
13418
13419                 error->plane[i].control = I915_READ(DSPCNTR(i));
13420                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13421                 if (INTEL_INFO(dev)->gen <= 3) {
13422                         error->plane[i].size = I915_READ(DSPSIZE(i));
13423                         error->plane[i].pos = I915_READ(DSPPOS(i));
13424                 }
13425                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13426                         error->plane[i].addr = I915_READ(DSPADDR(i));
13427                 if (INTEL_INFO(dev)->gen >= 4) {
13428                         error->plane[i].surface = I915_READ(DSPSURF(i));
13429                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13430                 }
13431
13432                 error->pipe[i].source = I915_READ(PIPESRC(i));
13433
13434                 if (HAS_GMCH_DISPLAY(dev))
13435                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13436         }
13437
13438         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13439         if (HAS_DDI(dev_priv->dev))
13440                 error->num_transcoders++; /* Account for eDP. */
13441
13442         for (i = 0; i < error->num_transcoders; i++) {
13443                 enum transcoder cpu_transcoder = transcoders[i];
13444
13445                 error->transcoder[i].power_domain_on =
13446                         __intel_display_power_is_enabled(dev_priv,
13447                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13448                 if (!error->transcoder[i].power_domain_on)
13449                         continue;
13450
13451                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13452
13453                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13454                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13455                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13456                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13457                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13458                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13459                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13460         }
13461
13462         return error;
13463 }
13464
13465 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13466
13467 void
13468 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13469                                 struct drm_device *dev,
13470                                 struct intel_display_error_state *error)
13471 {
13472         struct drm_i915_private *dev_priv = dev->dev_private;
13473         int i;
13474
13475         if (!error)
13476                 return;
13477
13478         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13479         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13480                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13481                            error->power_well_driver);
13482         for_each_pipe(dev_priv, i) {
13483                 err_printf(m, "Pipe [%d]:\n", i);
13484                 err_printf(m, "  Power: %s\n",
13485                            error->pipe[i].power_domain_on ? "on" : "off");
13486                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13487                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13488
13489                 err_printf(m, "Plane [%d]:\n", i);
13490                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13491                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13492                 if (INTEL_INFO(dev)->gen <= 3) {
13493                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13494                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13495                 }
13496                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13497                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13498                 if (INTEL_INFO(dev)->gen >= 4) {
13499                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13500                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13501                 }
13502
13503                 err_printf(m, "Cursor [%d]:\n", i);
13504                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13505                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13506                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13507         }
13508
13509         for (i = 0; i < error->num_transcoders; i++) {
13510                 err_printf(m, "CPU transcoder: %c\n",
13511                            transcoder_name(error->transcoder[i].cpu_transcoder));
13512                 err_printf(m, "  Power: %s\n",
13513                            error->transcoder[i].power_domain_on ? "on" : "off");
13514                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13515                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13516                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13517                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13518                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13519                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13520                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13521         }
13522 }
13523
13524 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13525 {
13526         struct intel_crtc *crtc;
13527
13528         for_each_intel_crtc(dev, crtc) {
13529                 struct intel_unpin_work *work;
13530
13531                 spin_lock_irq(&dev->event_lock);
13532
13533                 work = crtc->unpin_work;
13534
13535                 if (work && work->event &&
13536                     work->event->base.file_priv == file) {
13537                         kfree(work->event);
13538                         work->event = NULL;
13539                 }
13540
13541                 spin_unlock_irq(&dev->event_lock);
13542         }
13543 }