drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807 }
1808
1809 /**
1810  * intel_disable_pipe - disable a pipe, asserting requirements
1811  * @dev_priv: i915 private structure
1812  * @pipe: pipe to disable
1813  *
1814  * Disable @pipe, making sure that various hardware specific requirements
1815  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1816  *
1817  * @pipe should be %PIPE_A or %PIPE_B.
1818  *
1819  * Will wait until the pipe has shut down before returning.
1820  */
1821 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1822                                enum pipe pipe)
1823 {
1824         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1825                                                                       pipe);
1826         int reg;
1827         u32 val;
1828
1829         /*
1830          * Make sure planes won't keep trying to pump pixels to us,
1831          * or we might hang the display.
1832          */
1833         assert_planes_disabled(dev_priv, pipe);
1834         assert_cursor_disabled(dev_priv, pipe);
1835         assert_sprites_disabled(dev_priv, pipe);
1836
1837         /* Don't disable pipe A or pipe A PLLs if needed */
1838         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1839                 return;
1840
1841         reg = PIPECONF(cpu_transcoder);
1842         val = I915_READ(reg);
1843         if ((val & PIPECONF_ENABLE) == 0)
1844                 return;
1845
1846         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1847         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1848 }
1849
1850 /*
1851  * Plane regs are double buffered, going from enabled->disabled needs a
1852  * trigger in order to latch.  The display address reg provides this.
1853  */
1854 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1855                                enum plane plane)
1856 {
1857         struct drm_device *dev = dev_priv->dev;
1858         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1859
1860         I915_WRITE(reg, I915_READ(reg));
1861         POSTING_READ(reg);
1862 }
1863
1864 /**
1865  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1866  * @dev_priv: i915 private structure
1867  * @plane: plane to enable
1868  * @pipe: pipe being fed
1869  *
1870  * Enable @plane on @pipe, making sure that @pipe is running first.
1871  */
1872 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1873                                           enum plane plane, enum pipe pipe)
1874 {
1875         struct intel_crtc *intel_crtc =
1876                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1877         int reg;
1878         u32 val;
1879
1880         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1881         assert_pipe_enabled(dev_priv, pipe);
1882
1883         if (intel_crtc->primary_enabled)
1884                 return;
1885
1886         intel_crtc->primary_enabled = true;
1887
1888         reg = DSPCNTR(plane);
1889         val = I915_READ(reg);
1890         WARN_ON(val & DISPLAY_PLANE_ENABLE);
1891
1892         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1893         intel_flush_primary_plane(dev_priv, plane);
1894         intel_wait_for_vblank(dev_priv->dev, pipe);
1895 }
1896
1897 /**
1898  * intel_disable_primary_hw_plane - disable the primary hardware plane
1899  * @dev_priv: i915 private structure
1900  * @plane: plane to disable
1901  * @pipe: pipe consuming the data
1902  *
1903  * Disable @plane; should be an independent operation.
1904  */
1905 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1906                                            enum plane plane, enum pipe pipe)
1907 {
1908         struct intel_crtc *intel_crtc =
1909                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1910         int reg;
1911         u32 val;
1912
1913         if (!intel_crtc->primary_enabled)
1914                 return;
1915
1916         intel_crtc->primary_enabled = false;
1917
1918         reg = DSPCNTR(plane);
1919         val = I915_READ(reg);
1920         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
1921
1922         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1923         intel_flush_primary_plane(dev_priv, plane);
1924         intel_wait_for_vblank(dev_priv->dev, pipe);
1925 }
1926
1927 static bool need_vtd_wa(struct drm_device *dev)
1928 {
1929 #ifdef CONFIG_INTEL_IOMMU
1930         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1931                 return true;
1932 #endif
1933         return false;
1934 }
1935
1936 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1937 {
1938         int tile_height;
1939
1940         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1941         return ALIGN(height, tile_height);
1942 }
1943
1944 int
1945 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1946                            struct drm_i915_gem_object *obj,
1947                            struct intel_ring_buffer *pipelined)
1948 {
1949         struct drm_i915_private *dev_priv = dev->dev_private;
1950         u32 alignment;
1951         int ret;
1952
1953         switch (obj->tiling_mode) {
1954         case I915_TILING_NONE:
1955                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1956                         alignment = 128 * 1024;
1957                 else if (INTEL_INFO(dev)->gen >= 4)
1958                         alignment = 4 * 1024;
1959                 else
1960                         alignment = 64 * 1024;
1961                 break;
1962         case I915_TILING_X:
1963                 /* pin() will align the object as required by fence */
1964                 alignment = 0;
1965                 break;
1966         case I915_TILING_Y:
1967                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1968                 return -EINVAL;
1969         default:
1970                 BUG();
1971         }
1972
1973         /* Note that the w/a also requires 64 PTE of padding following the
1974          * bo. We currently fill all unused PTE with the shadow page and so
1975          * we should always have valid PTE following the scanout preventing
1976          * the VT-d warning.
1977          */
1978         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1979                 alignment = 256 * 1024;
1980
1981         dev_priv->mm.interruptible = false;
1982         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1983         if (ret)
1984                 goto err_interruptible;
1985
1986         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1987          * fence, whereas 965+ only requires a fence if using
1988          * framebuffer compression.  For simplicity, we always install
1989          * a fence as the cost is not that onerous.
1990          */
1991         ret = i915_gem_object_get_fence(obj);
1992         if (ret)
1993                 goto err_unpin;
1994
1995         i915_gem_object_pin_fence(obj);
1996
1997         dev_priv->mm.interruptible = true;
1998         return 0;
1999
2000 err_unpin:
2001         i915_gem_object_unpin_from_display_plane(obj);
2002 err_interruptible:
2003         dev_priv->mm.interruptible = true;
2004         return ret;
2005 }
2006
2007 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2008 {
2009         i915_gem_object_unpin_fence(obj);
2010         i915_gem_object_unpin_from_display_plane(obj);
2011 }
2012
2013 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2014  * is assumed to be a power-of-two. */
2015 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2016                                              unsigned int tiling_mode,
2017                                              unsigned int cpp,
2018                                              unsigned int pitch)
2019 {
2020         if (tiling_mode != I915_TILING_NONE) {
2021                 unsigned int tile_rows, tiles;
2022
2023                 tile_rows = *y / 8;
2024                 *y %= 8;
2025
2026                 tiles = *x / (512/cpp);
2027                 *x %= 512/cpp;
2028
2029                 return tile_rows * pitch * 8 + tiles * 4096;
2030         } else {
2031                 unsigned int offset;
2032
2033                 offset = *y * pitch + *x * cpp;
2034                 *y = 0;
2035                 *x = (offset & 4095) / cpp;
2036                 return offset & -4096;
2037         }
2038 }
2039
2040 int intel_format_to_fourcc(int format)
2041 {
2042         switch (format) {
2043         case DISPPLANE_8BPP:
2044                 return DRM_FORMAT_C8;
2045         case DISPPLANE_BGRX555:
2046                 return DRM_FORMAT_XRGB1555;
2047         case DISPPLANE_BGRX565:
2048                 return DRM_FORMAT_RGB565;
2049         default:
2050         case DISPPLANE_BGRX888:
2051                 return DRM_FORMAT_XRGB8888;
2052         case DISPPLANE_RGBX888:
2053                 return DRM_FORMAT_XBGR8888;
2054         case DISPPLANE_BGRX101010:
2055                 return DRM_FORMAT_XRGB2101010;
2056         case DISPPLANE_RGBX101010:
2057                 return DRM_FORMAT_XBGR2101010;
2058         }
2059 }
2060
2061 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2062                                   struct intel_plane_config *plane_config)
2063 {
2064         struct drm_device *dev = crtc->base.dev;
2065         struct drm_i915_gem_object *obj = NULL;
2066         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2067         u32 base = plane_config->base;
2068
2069         if (plane_config->size == 0)
2070                 return false;
2071
2072         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2073                                                              plane_config->size);
2074         if (!obj)
2075                 return false;
2076
2077         if (plane_config->tiled) {
2078                 obj->tiling_mode = I915_TILING_X;
2079                 obj->stride = crtc->base.primary->fb->pitches[0];
2080         }
2081
2082         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2083         mode_cmd.width = crtc->base.primary->fb->width;
2084         mode_cmd.height = crtc->base.primary->fb->height;
2085         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2086
2087         mutex_lock(&dev->struct_mutex);
2088
2089         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2090                                    &mode_cmd, obj)) {
2091                 DRM_DEBUG_KMS("intel fb init failed\n");
2092                 goto out_unref_obj;
2093         }
2094
2095         mutex_unlock(&dev->struct_mutex);
2096
2097         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2098         return true;
2099
2100 out_unref_obj:
2101         drm_gem_object_unreference(&obj->base);
2102         mutex_unlock(&dev->struct_mutex);
2103         return false;
2104 }
2105
2106 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2107                                  struct intel_plane_config *plane_config)
2108 {
2109         struct drm_device *dev = intel_crtc->base.dev;
2110         struct drm_crtc *c;
2111         struct intel_crtc *i;
2112         struct intel_framebuffer *fb;
2113
2114         if (!intel_crtc->base.primary->fb)
2115                 return;
2116
2117         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2118                 return;
2119
2120         kfree(intel_crtc->base.primary->fb);
2121         intel_crtc->base.primary->fb = NULL;
2122
2123         /*
2124          * Failed to alloc the obj, check to see if we should share
2125          * an fb with another CRTC instead
2126          */
2127         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2128                 i = to_intel_crtc(c);
2129
2130                 if (c == &intel_crtc->base)
2131                         continue;
2132
2133                 if (!i->active || !c->primary->fb)
2134                         continue;
2135
2136                 fb = to_intel_framebuffer(c->primary->fb);
2137                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2138                         drm_framebuffer_reference(c->primary->fb);
2139                         intel_crtc->base.primary->fb = c->primary->fb;
2140                         break;
2141                 }
2142         }
2143 }
2144
2145 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2146                                      struct drm_framebuffer *fb,
2147                                      int x, int y)
2148 {
2149         struct drm_device *dev = crtc->dev;
2150         struct drm_i915_private *dev_priv = dev->dev_private;
2151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2152         struct intel_framebuffer *intel_fb;
2153         struct drm_i915_gem_object *obj;
2154         int plane = intel_crtc->plane;
2155         unsigned long linear_offset;
2156         u32 dspcntr;
2157         u32 reg;
2158
2159         intel_fb = to_intel_framebuffer(fb);
2160         obj = intel_fb->obj;
2161
2162         reg = DSPCNTR(plane);
2163         dspcntr = I915_READ(reg);
2164         /* Mask out pixel format bits in case we change it */
2165         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2166         switch (fb->pixel_format) {
2167         case DRM_FORMAT_C8:
2168                 dspcntr |= DISPPLANE_8BPP;
2169                 break;
2170         case DRM_FORMAT_XRGB1555:
2171         case DRM_FORMAT_ARGB1555:
2172                 dspcntr |= DISPPLANE_BGRX555;
2173                 break;
2174         case DRM_FORMAT_RGB565:
2175                 dspcntr |= DISPPLANE_BGRX565;
2176                 break;
2177         case DRM_FORMAT_XRGB8888:
2178         case DRM_FORMAT_ARGB8888:
2179                 dspcntr |= DISPPLANE_BGRX888;
2180                 break;
2181         case DRM_FORMAT_XBGR8888:
2182         case DRM_FORMAT_ABGR8888:
2183                 dspcntr |= DISPPLANE_RGBX888;
2184                 break;
2185         case DRM_FORMAT_XRGB2101010:
2186         case DRM_FORMAT_ARGB2101010:
2187                 dspcntr |= DISPPLANE_BGRX101010;
2188                 break;
2189         case DRM_FORMAT_XBGR2101010:
2190         case DRM_FORMAT_ABGR2101010:
2191                 dspcntr |= DISPPLANE_RGBX101010;
2192                 break;
2193         default:
2194                 BUG();
2195         }
2196
2197         if (INTEL_INFO(dev)->gen >= 4) {
2198                 if (obj->tiling_mode != I915_TILING_NONE)
2199                         dspcntr |= DISPPLANE_TILED;
2200                 else
2201                         dspcntr &= ~DISPPLANE_TILED;
2202         }
2203
2204         if (IS_G4X(dev))
2205                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2206
2207         I915_WRITE(reg, dspcntr);
2208
2209         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2210
2211         if (INTEL_INFO(dev)->gen >= 4) {
2212                 intel_crtc->dspaddr_offset =
2213                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2214                                                        fb->bits_per_pixel / 8,
2215                                                        fb->pitches[0]);
2216                 linear_offset -= intel_crtc->dspaddr_offset;
2217         } else {
2218                 intel_crtc->dspaddr_offset = linear_offset;
2219         }
2220
2221         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2222                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2223                       fb->pitches[0]);
2224         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2225         if (INTEL_INFO(dev)->gen >= 4) {
2226                 I915_WRITE(DSPSURF(plane),
2227                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2228                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2230         } else
2231                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2232         POSTING_READ(reg);
2233
2234         return 0;
2235 }
2236
2237 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2238                                          struct drm_framebuffer *fb,
2239                                          int x, int y)
2240 {
2241         struct drm_device *dev = crtc->dev;
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244         struct intel_framebuffer *intel_fb;
2245         struct drm_i915_gem_object *obj;
2246         int plane = intel_crtc->plane;
2247         unsigned long linear_offset;
2248         u32 dspcntr;
2249         u32 reg;
2250
2251         intel_fb = to_intel_framebuffer(fb);
2252         obj = intel_fb->obj;
2253
2254         reg = DSPCNTR(plane);
2255         dspcntr = I915_READ(reg);
2256         /* Mask out pixel format bits in case we change it */
2257         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2258         switch (fb->pixel_format) {
2259         case DRM_FORMAT_C8:
2260                 dspcntr |= DISPPLANE_8BPP;
2261                 break;
2262         case DRM_FORMAT_RGB565:
2263                 dspcntr |= DISPPLANE_BGRX565;
2264                 break;
2265         case DRM_FORMAT_XRGB8888:
2266         case DRM_FORMAT_ARGB8888:
2267                 dspcntr |= DISPPLANE_BGRX888;
2268                 break;
2269         case DRM_FORMAT_XBGR8888:
2270         case DRM_FORMAT_ABGR8888:
2271                 dspcntr |= DISPPLANE_RGBX888;
2272                 break;
2273         case DRM_FORMAT_XRGB2101010:
2274         case DRM_FORMAT_ARGB2101010:
2275                 dspcntr |= DISPPLANE_BGRX101010;
2276                 break;
2277         case DRM_FORMAT_XBGR2101010:
2278         case DRM_FORMAT_ABGR2101010:
2279                 dspcntr |= DISPPLANE_RGBX101010;
2280                 break;
2281         default:
2282                 BUG();
2283         }
2284
2285         if (obj->tiling_mode != I915_TILING_NONE)
2286                 dspcntr |= DISPPLANE_TILED;
2287         else
2288                 dspcntr &= ~DISPPLANE_TILED;
2289
2290         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2291                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2292         else
2293                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2294
2295         I915_WRITE(reg, dspcntr);
2296
2297         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2298         intel_crtc->dspaddr_offset =
2299                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2300                                                fb->bits_per_pixel / 8,
2301                                                fb->pitches[0]);
2302         linear_offset -= intel_crtc->dspaddr_offset;
2303
2304         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2305                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2306                       fb->pitches[0]);
2307         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2308         I915_WRITE(DSPSURF(plane),
2309                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2310         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2311                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2312         } else {
2313                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2314                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2315         }
2316         POSTING_READ(reg);
2317
2318         return 0;
2319 }
2320
2321 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2322 static int
2323 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2324                            int x, int y, enum mode_set_atomic state)
2325 {
2326         struct drm_device *dev = crtc->dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329         if (dev_priv->display.disable_fbc)
2330                 dev_priv->display.disable_fbc(dev);
2331         intel_increase_pllclock(crtc);
2332
2333         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2334 }
2335
2336 void intel_display_handle_reset(struct drm_device *dev)
2337 {
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct drm_crtc *crtc;
2340
2341         /*
2342          * Flips in the rings have been nuked by the reset,
2343          * so complete all pending flips so that user space
2344          * will get its events and not get stuck.
2345          *
2346          * Also update the base address of all primary
2347          * planes to the the last fb to make sure we're
2348          * showing the correct fb after a reset.
2349          *
2350          * Need to make two loops over the crtcs so that we
2351          * don't try to grab a crtc mutex before the
2352          * pending_flip_queue really got woken up.
2353          */
2354
2355         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2356                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357                 enum plane plane = intel_crtc->plane;
2358
2359                 intel_prepare_page_flip(dev, plane);
2360                 intel_finish_page_flip_plane(dev, plane);
2361         }
2362
2363         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2364                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365
2366                 mutex_lock(&crtc->mutex);
2367                 /*
2368                  * FIXME: Once we have proper support for primary planes (and
2369                  * disabling them without disabling the entire crtc) allow again
2370                  * a NULL crtc->primary->fb.
2371                  */
2372                 if (intel_crtc->active && crtc->primary->fb)
2373                         dev_priv->display.update_primary_plane(crtc,
2374                                                                crtc->primary->fb,
2375                                                                crtc->x,
2376                                                                crtc->y);
2377                 mutex_unlock(&crtc->mutex);
2378         }
2379 }
2380
2381 static int
2382 intel_finish_fb(struct drm_framebuffer *old_fb)
2383 {
2384         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2385         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2386         bool was_interruptible = dev_priv->mm.interruptible;
2387         int ret;
2388
2389         /* Big Hammer, we also need to ensure that any pending
2390          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2391          * current scanout is retired before unpinning the old
2392          * framebuffer.
2393          *
2394          * This should only fail upon a hung GPU, in which case we
2395          * can safely continue.
2396          */
2397         dev_priv->mm.interruptible = false;
2398         ret = i915_gem_object_finish_gpu(obj);
2399         dev_priv->mm.interruptible = was_interruptible;
2400
2401         return ret;
2402 }
2403
2404 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         unsigned long flags;
2410         bool pending;
2411
2412         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2413             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2414                 return false;
2415
2416         spin_lock_irqsave(&dev->event_lock, flags);
2417         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2418         spin_unlock_irqrestore(&dev->event_lock, flags);
2419
2420         return pending;
2421 }
2422
2423 static int
2424 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2425                     struct drm_framebuffer *fb)
2426 {
2427         struct drm_device *dev = crtc->dev;
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430         struct drm_framebuffer *old_fb;
2431         int ret;
2432
2433         if (intel_crtc_has_pending_flip(crtc)) {
2434                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2435                 return -EBUSY;
2436         }
2437
2438         /* no fb bound */
2439         if (!fb) {
2440                 DRM_ERROR("No FB bound\n");
2441                 return 0;
2442         }
2443
2444         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2445                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2446                           plane_name(intel_crtc->plane),
2447                           INTEL_INFO(dev)->num_pipes);
2448                 return -EINVAL;
2449         }
2450
2451         mutex_lock(&dev->struct_mutex);
2452         ret = intel_pin_and_fence_fb_obj(dev,
2453                                          to_intel_framebuffer(fb)->obj,
2454                                          NULL);
2455         mutex_unlock(&dev->struct_mutex);
2456         if (ret != 0) {
2457                 DRM_ERROR("pin & fence failed\n");
2458                 return ret;
2459         }
2460
2461         /*
2462          * Update pipe size and adjust fitter if needed: the reason for this is
2463          * that in compute_mode_changes we check the native mode (not the pfit
2464          * mode) to see if we can flip rather than do a full mode set. In the
2465          * fastboot case, we'll flip, but if we don't update the pipesrc and
2466          * pfit state, we'll end up with a big fb scanned out into the wrong
2467          * sized surface.
2468          *
2469          * To fix this properly, we need to hoist the checks up into
2470          * compute_mode_changes (or above), check the actual pfit state and
2471          * whether the platform allows pfit disable with pipe active, and only
2472          * then update the pipesrc and pfit state, even on the flip path.
2473          */
2474         if (i915.fastboot) {
2475                 const struct drm_display_mode *adjusted_mode =
2476                         &intel_crtc->config.adjusted_mode;
2477
2478                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2479                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2480                            (adjusted_mode->crtc_vdisplay - 1));
2481                 if (!intel_crtc->config.pch_pfit.enabled &&
2482                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2483                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2484                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2485                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2486                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2487                 }
2488                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2489                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2490         }
2491
2492         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2493         if (ret) {
2494                 mutex_lock(&dev->struct_mutex);
2495                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2496                 mutex_unlock(&dev->struct_mutex);
2497                 DRM_ERROR("failed to update base address\n");
2498                 return ret;
2499         }
2500
2501         old_fb = crtc->primary->fb;
2502         crtc->primary->fb = fb;
2503         crtc->x = x;
2504         crtc->y = y;
2505
2506         if (old_fb) {
2507                 if (intel_crtc->active && old_fb != fb)
2508                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2509                 mutex_lock(&dev->struct_mutex);
2510                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2511                 mutex_unlock(&dev->struct_mutex);
2512         }
2513
2514         mutex_lock(&dev->struct_mutex);
2515         intel_update_fbc(dev);
2516         intel_edp_psr_update(dev);
2517         mutex_unlock(&dev->struct_mutex);
2518
2519         return 0;
2520 }
2521
2522 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2523 {
2524         struct drm_device *dev = crtc->dev;
2525         struct drm_i915_private *dev_priv = dev->dev_private;
2526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2527         int pipe = intel_crtc->pipe;
2528         u32 reg, temp;
2529
2530         /* enable normal train */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         if (IS_IVYBRIDGE(dev)) {
2534                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2535                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2536         } else {
2537                 temp &= ~FDI_LINK_TRAIN_NONE;
2538                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2539         }
2540         I915_WRITE(reg, temp);
2541
2542         reg = FDI_RX_CTL(pipe);
2543         temp = I915_READ(reg);
2544         if (HAS_PCH_CPT(dev)) {
2545                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2546                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2547         } else {
2548                 temp &= ~FDI_LINK_TRAIN_NONE;
2549                 temp |= FDI_LINK_TRAIN_NONE;
2550         }
2551         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2552
2553         /* wait one idle pattern time */
2554         POSTING_READ(reg);
2555         udelay(1000);
2556
2557         /* IVB wants error correction enabled */
2558         if (IS_IVYBRIDGE(dev))
2559                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2560                            FDI_FE_ERRC_ENABLE);
2561 }
2562
2563 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2564 {
2565         return crtc->base.enabled && crtc->active &&
2566                 crtc->config.has_pch_encoder;
2567 }
2568
2569 static void ivb_modeset_global_resources(struct drm_device *dev)
2570 {
2571         struct drm_i915_private *dev_priv = dev->dev_private;
2572         struct intel_crtc *pipe_B_crtc =
2573                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2574         struct intel_crtc *pipe_C_crtc =
2575                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2576         uint32_t temp;
2577
2578         /*
2579          * When everything is off disable fdi C so that we could enable fdi B
2580          * with all lanes. Note that we don't care about enabled pipes without
2581          * an enabled pch encoder.
2582          */
2583         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2584             !pipe_has_enabled_pch(pipe_C_crtc)) {
2585                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2586                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2587
2588                 temp = I915_READ(SOUTH_CHICKEN1);
2589                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2590                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2591                 I915_WRITE(SOUTH_CHICKEN1, temp);
2592         }
2593 }
2594
2595 /* The FDI link training functions for ILK/Ibexpeak. */
2596 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         u32 reg, temp, tries;
2603
2604         /* FDI needs bits from pipe first */
2605         assert_pipe_enabled(dev_priv, pipe);
2606
2607         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608            for train result */
2609         reg = FDI_RX_IMR(pipe);
2610         temp = I915_READ(reg);
2611         temp &= ~FDI_RX_SYMBOL_LOCK;
2612         temp &= ~FDI_RX_BIT_LOCK;
2613         I915_WRITE(reg, temp);
2614         I915_READ(reg);
2615         udelay(150);
2616
2617         /* enable CPU FDI TX and PCH FDI RX */
2618         reg = FDI_TX_CTL(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2621         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2622         temp &= ~FDI_LINK_TRAIN_NONE;
2623         temp |= FDI_LINK_TRAIN_PATTERN_1;
2624         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2625
2626         reg = FDI_RX_CTL(pipe);
2627         temp = I915_READ(reg);
2628         temp &= ~FDI_LINK_TRAIN_NONE;
2629         temp |= FDI_LINK_TRAIN_PATTERN_1;
2630         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2631
2632         POSTING_READ(reg);
2633         udelay(150);
2634
2635         /* Ironlake workaround, enable clock pointer after FDI enable*/
2636         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2637         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2638                    FDI_RX_PHASE_SYNC_POINTER_EN);
2639
2640         reg = FDI_RX_IIR(pipe);
2641         for (tries = 0; tries < 5; tries++) {
2642                 temp = I915_READ(reg);
2643                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644
2645                 if ((temp & FDI_RX_BIT_LOCK)) {
2646                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2647                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2648                         break;
2649                 }
2650         }
2651         if (tries == 5)
2652                 DRM_ERROR("FDI train 1 fail!\n");
2653
2654         /* Train 2 */
2655         reg = FDI_TX_CTL(pipe);
2656         temp = I915_READ(reg);
2657         temp &= ~FDI_LINK_TRAIN_NONE;
2658         temp |= FDI_LINK_TRAIN_PATTERN_2;
2659         I915_WRITE(reg, temp);
2660
2661         reg = FDI_RX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_LINK_TRAIN_NONE;
2664         temp |= FDI_LINK_TRAIN_PATTERN_2;
2665         I915_WRITE(reg, temp);
2666
2667         POSTING_READ(reg);
2668         udelay(150);
2669
2670         reg = FDI_RX_IIR(pipe);
2671         for (tries = 0; tries < 5; tries++) {
2672                 temp = I915_READ(reg);
2673                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674
2675                 if (temp & FDI_RX_SYMBOL_LOCK) {
2676                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2677                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2678                         break;
2679                 }
2680         }
2681         if (tries == 5)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done\n");
2685
2686 }
2687
2688 static const int snb_b_fdi_train_param[] = {
2689         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2690         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2691         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2692         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2693 };
2694
2695 /* The FDI link training functions for SNB/Cougarpoint. */
2696 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2697 {
2698         struct drm_device *dev = crtc->dev;
2699         struct drm_i915_private *dev_priv = dev->dev_private;
2700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2701         int pipe = intel_crtc->pipe;
2702         u32 reg, temp, i, retry;
2703
2704         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2705            for train result */
2706         reg = FDI_RX_IMR(pipe);
2707         temp = I915_READ(reg);
2708         temp &= ~FDI_RX_SYMBOL_LOCK;
2709         temp &= ~FDI_RX_BIT_LOCK;
2710         I915_WRITE(reg, temp);
2711
2712         POSTING_READ(reg);
2713         udelay(150);
2714
2715         /* enable CPU FDI TX and PCH FDI RX */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2719         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720         temp &= ~FDI_LINK_TRAIN_NONE;
2721         temp |= FDI_LINK_TRAIN_PATTERN_1;
2722         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2723         /* SNB-B */
2724         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2725         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2726
2727         I915_WRITE(FDI_RX_MISC(pipe),
2728                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2738         }
2739         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2740
2741         POSTING_READ(reg);
2742         udelay(150);
2743
2744         for (i = 0; i < 4; i++) {
2745                 reg = FDI_TX_CTL(pipe);
2746                 temp = I915_READ(reg);
2747                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2748                 temp |= snb_b_fdi_train_param[i];
2749                 I915_WRITE(reg, temp);
2750
2751                 POSTING_READ(reg);
2752                 udelay(500);
2753
2754                 for (retry = 0; retry < 5; retry++) {
2755                         reg = FDI_RX_IIR(pipe);
2756                         temp = I915_READ(reg);
2757                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758                         if (temp & FDI_RX_BIT_LOCK) {
2759                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2761                                 break;
2762                         }
2763                         udelay(50);
2764                 }
2765                 if (retry < 5)
2766                         break;
2767         }
2768         if (i == 4)
2769                 DRM_ERROR("FDI train 1 fail!\n");
2770
2771         /* Train 2 */
2772         reg = FDI_TX_CTL(pipe);
2773         temp = I915_READ(reg);
2774         temp &= ~FDI_LINK_TRAIN_NONE;
2775         temp |= FDI_LINK_TRAIN_PATTERN_2;
2776         if (IS_GEN6(dev)) {
2777                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778                 /* SNB-B */
2779                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780         }
2781         I915_WRITE(reg, temp);
2782
2783         reg = FDI_RX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         if (HAS_PCH_CPT(dev)) {
2786                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2787                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2788         } else {
2789                 temp &= ~FDI_LINK_TRAIN_NONE;
2790                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2791         }
2792         I915_WRITE(reg, temp);
2793
2794         POSTING_READ(reg);
2795         udelay(150);
2796
2797         for (i = 0; i < 4; i++) {
2798                 reg = FDI_TX_CTL(pipe);
2799                 temp = I915_READ(reg);
2800                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2801                 temp |= snb_b_fdi_train_param[i];
2802                 I915_WRITE(reg, temp);
2803
2804                 POSTING_READ(reg);
2805                 udelay(500);
2806
2807                 for (retry = 0; retry < 5; retry++) {
2808                         reg = FDI_RX_IIR(pipe);
2809                         temp = I915_READ(reg);
2810                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811                         if (temp & FDI_RX_SYMBOL_LOCK) {
2812                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2813                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2814                                 break;
2815                         }
2816                         udelay(50);
2817                 }
2818                 if (retry < 5)
2819                         break;
2820         }
2821         if (i == 4)
2822                 DRM_ERROR("FDI train 2 fail!\n");
2823
2824         DRM_DEBUG_KMS("FDI train done.\n");
2825 }
2826
2827 /* Manual link training for Ivy Bridge A0 parts */
2828 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2829 {
2830         struct drm_device *dev = crtc->dev;
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2833         int pipe = intel_crtc->pipe;
2834         u32 reg, temp, i, j;
2835
2836         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2837            for train result */
2838         reg = FDI_RX_IMR(pipe);
2839         temp = I915_READ(reg);
2840         temp &= ~FDI_RX_SYMBOL_LOCK;
2841         temp &= ~FDI_RX_BIT_LOCK;
2842         I915_WRITE(reg, temp);
2843
2844         POSTING_READ(reg);
2845         udelay(150);
2846
2847         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2848                       I915_READ(FDI_RX_IIR(pipe)));
2849
2850         /* Try each vswing and preemphasis setting twice before moving on */
2851         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2852                 /* disable first in case we need to retry */
2853                 reg = FDI_TX_CTL(pipe);
2854                 temp = I915_READ(reg);
2855                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2856                 temp &= ~FDI_TX_ENABLE;
2857                 I915_WRITE(reg, temp);
2858
2859                 reg = FDI_RX_CTL(pipe);
2860                 temp = I915_READ(reg);
2861                 temp &= ~FDI_LINK_TRAIN_AUTO;
2862                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2863                 temp &= ~FDI_RX_ENABLE;
2864                 I915_WRITE(reg, temp);
2865
2866                 /* enable CPU FDI TX and PCH FDI RX */
2867                 reg = FDI_TX_CTL(pipe);
2868                 temp = I915_READ(reg);
2869                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2870                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2871                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2872                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2873                 temp |= snb_b_fdi_train_param[j/2];
2874                 temp |= FDI_COMPOSITE_SYNC;
2875                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2876
2877                 I915_WRITE(FDI_RX_MISC(pipe),
2878                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2879
2880                 reg = FDI_RX_CTL(pipe);
2881                 temp = I915_READ(reg);
2882                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2883                 temp |= FDI_COMPOSITE_SYNC;
2884                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2885
2886                 POSTING_READ(reg);
2887                 udelay(1); /* should be 0.5us */
2888
2889                 for (i = 0; i < 4; i++) {
2890                         reg = FDI_RX_IIR(pipe);
2891                         temp = I915_READ(reg);
2892                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2893
2894                         if (temp & FDI_RX_BIT_LOCK ||
2895                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2896                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2897                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2898                                               i);
2899                                 break;
2900                         }
2901                         udelay(1); /* should be 0.5us */
2902                 }
2903                 if (i == 4) {
2904                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2905                         continue;
2906                 }
2907
2908                 /* Train 2 */
2909                 reg = FDI_TX_CTL(pipe);
2910                 temp = I915_READ(reg);
2911                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2912                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2913                 I915_WRITE(reg, temp);
2914
2915                 reg = FDI_RX_CTL(pipe);
2916                 temp = I915_READ(reg);
2917                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2918                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2919                 I915_WRITE(reg, temp);
2920
2921                 POSTING_READ(reg);
2922                 udelay(2); /* should be 1.5us */
2923
2924                 for (i = 0; i < 4; i++) {
2925                         reg = FDI_RX_IIR(pipe);
2926                         temp = I915_READ(reg);
2927                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2928
2929                         if (temp & FDI_RX_SYMBOL_LOCK ||
2930                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2931                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2932                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2933                                               i);
2934                                 goto train_done;
2935                         }
2936                         udelay(2); /* should be 1.5us */
2937                 }
2938                 if (i == 4)
2939                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2940         }
2941
2942 train_done:
2943         DRM_DEBUG_KMS("FDI train done.\n");
2944 }
2945
2946 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2947 {
2948         struct drm_device *dev = intel_crtc->base.dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950         int pipe = intel_crtc->pipe;
2951         u32 reg, temp;
2952
2953
2954         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2955         reg = FDI_RX_CTL(pipe);
2956         temp = I915_READ(reg);
2957         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2958         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2959         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2961
2962         POSTING_READ(reg);
2963         udelay(200);
2964
2965         /* Switch from Rawclk to PCDclk */
2966         temp = I915_READ(reg);
2967         I915_WRITE(reg, temp | FDI_PCDCLK);
2968
2969         POSTING_READ(reg);
2970         udelay(200);
2971
2972         /* Enable CPU FDI TX PLL, always on for Ironlake */
2973         reg = FDI_TX_CTL(pipe);
2974         temp = I915_READ(reg);
2975         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2976                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2977
2978                 POSTING_READ(reg);
2979                 udelay(100);
2980         }
2981 }
2982
2983 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2984 {
2985         struct drm_device *dev = intel_crtc->base.dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         int pipe = intel_crtc->pipe;
2988         u32 reg, temp;
2989
2990         /* Switch from PCDclk to Rawclk */
2991         reg = FDI_RX_CTL(pipe);
2992         temp = I915_READ(reg);
2993         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2994
2995         /* Disable CPU FDI TX PLL */
2996         reg = FDI_TX_CTL(pipe);
2997         temp = I915_READ(reg);
2998         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2999
3000         POSTING_READ(reg);
3001         udelay(100);
3002
3003         reg = FDI_RX_CTL(pipe);
3004         temp = I915_READ(reg);
3005         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3006
3007         /* Wait for the clocks to turn off. */
3008         POSTING_READ(reg);
3009         udelay(100);
3010 }
3011
3012 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3013 {
3014         struct drm_device *dev = crtc->dev;
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3017         int pipe = intel_crtc->pipe;
3018         u32 reg, temp;
3019
3020         /* disable CPU FDI tx and PCH FDI rx */
3021         reg = FDI_TX_CTL(pipe);
3022         temp = I915_READ(reg);
3023         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3024         POSTING_READ(reg);
3025
3026         reg = FDI_RX_CTL(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~(0x7 << 16);
3029         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3030         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3031
3032         POSTING_READ(reg);
3033         udelay(100);
3034
3035         /* Ironlake workaround, disable clock pointer after downing FDI */
3036         if (HAS_PCH_IBX(dev)) {
3037                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3038         }
3039
3040         /* still set train pattern 1 */
3041         reg = FDI_TX_CTL(pipe);
3042         temp = I915_READ(reg);
3043         temp &= ~FDI_LINK_TRAIN_NONE;
3044         temp |= FDI_LINK_TRAIN_PATTERN_1;
3045         I915_WRITE(reg, temp);
3046
3047         reg = FDI_RX_CTL(pipe);
3048         temp = I915_READ(reg);
3049         if (HAS_PCH_CPT(dev)) {
3050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3052         } else {
3053                 temp &= ~FDI_LINK_TRAIN_NONE;
3054                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3055         }
3056         /* BPC in FDI rx is consistent with that in PIPECONF */
3057         temp &= ~(0x07 << 16);
3058         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3059         I915_WRITE(reg, temp);
3060
3061         POSTING_READ(reg);
3062         udelay(100);
3063 }
3064
3065 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3066 {
3067         struct intel_crtc *crtc;
3068
3069         /* Note that we don't need to be called with mode_config.lock here
3070          * as our list of CRTC objects is static for the lifetime of the
3071          * device and so cannot disappear as we iterate. Similarly, we can
3072          * happily treat the predicates as racy, atomic checks as userspace
3073          * cannot claim and pin a new fb without at least acquring the
3074          * struct_mutex and so serialising with us.
3075          */
3076         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3077                 if (atomic_read(&crtc->unpin_work_count) == 0)
3078                         continue;
3079
3080                 if (crtc->unpin_work)
3081                         intel_wait_for_vblank(dev, crtc->pipe);
3082
3083                 return true;
3084         }
3085
3086         return false;
3087 }
3088
3089 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3090 {
3091         struct drm_device *dev = crtc->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093
3094         if (crtc->primary->fb == NULL)
3095                 return;
3096
3097         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3098
3099         wait_event(dev_priv->pending_flip_queue,
3100                    !intel_crtc_has_pending_flip(crtc));
3101
3102         mutex_lock(&dev->struct_mutex);
3103         intel_finish_fb(crtc->primary->fb);
3104         mutex_unlock(&dev->struct_mutex);
3105 }
3106
3107 /* Program iCLKIP clock to the desired frequency */
3108 static void lpt_program_iclkip(struct drm_crtc *crtc)
3109 {
3110         struct drm_device *dev = crtc->dev;
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3113         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3114         u32 temp;
3115
3116         mutex_lock(&dev_priv->dpio_lock);
3117
3118         /* It is necessary to ungate the pixclk gate prior to programming
3119          * the divisors, and gate it back when it is done.
3120          */
3121         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3122
3123         /* Disable SSCCTL */
3124         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3125                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3126                                 SBI_SSCCTL_DISABLE,
3127                         SBI_ICLK);
3128
3129         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3130         if (clock == 20000) {
3131                 auxdiv = 1;
3132                 divsel = 0x41;
3133                 phaseinc = 0x20;
3134         } else {
3135                 /* The iCLK virtual clock root frequency is in MHz,
3136                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3137                  * divisors, it is necessary to divide one by another, so we
3138                  * convert the virtual clock precision to KHz here for higher
3139                  * precision.
3140                  */
3141                 u32 iclk_virtual_root_freq = 172800 * 1000;
3142                 u32 iclk_pi_range = 64;
3143                 u32 desired_divisor, msb_divisor_value, pi_value;
3144
3145                 desired_divisor = (iclk_virtual_root_freq / clock);
3146                 msb_divisor_value = desired_divisor / iclk_pi_range;
3147                 pi_value = desired_divisor % iclk_pi_range;
3148
3149                 auxdiv = 0;
3150                 divsel = msb_divisor_value - 2;
3151                 phaseinc = pi_value;
3152         }
3153
3154         /* This should not happen with any sane values */
3155         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3156                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3157         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3158                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3159
3160         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3161                         clock,
3162                         auxdiv,
3163                         divsel,
3164                         phasedir,
3165                         phaseinc);
3166
3167         /* Program SSCDIVINTPHASE6 */
3168         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3169         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3170         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3171         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3172         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3173         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3174         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3175         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3176
3177         /* Program SSCAUXDIV */
3178         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3179         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3180         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3181         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3182
3183         /* Enable modulator and associated divider */
3184         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3185         temp &= ~SBI_SSCCTL_DISABLE;
3186         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3187
3188         /* Wait for initialization time */
3189         udelay(24);
3190
3191         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3192
3193         mutex_unlock(&dev_priv->dpio_lock);
3194 }
3195
3196 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3197                                                 enum pipe pch_transcoder)
3198 {
3199         struct drm_device *dev = crtc->base.dev;
3200         struct drm_i915_private *dev_priv = dev->dev_private;
3201         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3202
3203         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3204                    I915_READ(HTOTAL(cpu_transcoder)));
3205         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3206                    I915_READ(HBLANK(cpu_transcoder)));
3207         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3208                    I915_READ(HSYNC(cpu_transcoder)));
3209
3210         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3211                    I915_READ(VTOTAL(cpu_transcoder)));
3212         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3213                    I915_READ(VBLANK(cpu_transcoder)));
3214         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3215                    I915_READ(VSYNC(cpu_transcoder)));
3216         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3217                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3218 }
3219
3220 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3221 {
3222         struct drm_i915_private *dev_priv = dev->dev_private;
3223         uint32_t temp;
3224
3225         temp = I915_READ(SOUTH_CHICKEN1);
3226         if (temp & FDI_BC_BIFURCATION_SELECT)
3227                 return;
3228
3229         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3230         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3231
3232         temp |= FDI_BC_BIFURCATION_SELECT;
3233         DRM_DEBUG_KMS("enabling fdi C rx\n");
3234         I915_WRITE(SOUTH_CHICKEN1, temp);
3235         POSTING_READ(SOUTH_CHICKEN1);
3236 }
3237
3238 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3239 {
3240         struct drm_device *dev = intel_crtc->base.dev;
3241         struct drm_i915_private *dev_priv = dev->dev_private;
3242
3243         switch (intel_crtc->pipe) {
3244         case PIPE_A:
3245                 break;
3246         case PIPE_B:
3247                 if (intel_crtc->config.fdi_lanes > 2)
3248                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3249                 else
3250                         cpt_enable_fdi_bc_bifurcation(dev);
3251
3252                 break;
3253         case PIPE_C:
3254                 cpt_enable_fdi_bc_bifurcation(dev);
3255
3256                 break;
3257         default:
3258                 BUG();
3259         }
3260 }
3261
3262 /*
3263  * Enable PCH resources required for PCH ports:
3264  *   - PCH PLLs
3265  *   - FDI training & RX/TX
3266  *   - update transcoder timings
3267  *   - DP transcoding bits
3268  *   - transcoder
3269  */
3270 static void ironlake_pch_enable(struct drm_crtc *crtc)
3271 {
3272         struct drm_device *dev = crtc->dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275         int pipe = intel_crtc->pipe;
3276         u32 reg, temp;
3277
3278         assert_pch_transcoder_disabled(dev_priv, pipe);
3279
3280         if (IS_IVYBRIDGE(dev))
3281                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3282
3283         /* Write the TU size bits before fdi link training, so that error
3284          * detection works. */
3285         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3286                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3287
3288         /* For PCH output, training FDI link */
3289         dev_priv->display.fdi_link_train(crtc);
3290
3291         /* We need to program the right clock selection before writing the pixel
3292          * mutliplier into the DPLL. */
3293         if (HAS_PCH_CPT(dev)) {
3294                 u32 sel;
3295
3296                 temp = I915_READ(PCH_DPLL_SEL);
3297                 temp |= TRANS_DPLL_ENABLE(pipe);
3298                 sel = TRANS_DPLLB_SEL(pipe);
3299                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3300                         temp |= sel;
3301                 else
3302                         temp &= ~sel;
3303                 I915_WRITE(PCH_DPLL_SEL, temp);
3304         }
3305
3306         /* XXX: pch pll's can be enabled any time before we enable the PCH
3307          * transcoder, and we actually should do this to not upset any PCH
3308          * transcoder that already use the clock when we share it.
3309          *
3310          * Note that enable_shared_dpll tries to do the right thing, but
3311          * get_shared_dpll unconditionally resets the pll - we need that to have
3312          * the right LVDS enable sequence. */
3313         ironlake_enable_shared_dpll(intel_crtc);
3314
3315         /* set transcoder timing, panel must allow it */
3316         assert_panel_unlocked(dev_priv, pipe);
3317         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3318
3319         intel_fdi_normal_train(crtc);
3320
3321         /* For PCH DP, enable TRANS_DP_CTL */
3322         if (HAS_PCH_CPT(dev) &&
3323             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3324              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3325                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3326                 reg = TRANS_DP_CTL(pipe);
3327                 temp = I915_READ(reg);
3328                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3329                           TRANS_DP_SYNC_MASK |
3330                           TRANS_DP_BPC_MASK);
3331                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3332                          TRANS_DP_ENH_FRAMING);
3333                 temp |= bpc << 9; /* same format but at 11:9 */
3334
3335                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3336                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3337                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3338                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3339
3340                 switch (intel_trans_dp_port_sel(crtc)) {
3341                 case PCH_DP_B:
3342                         temp |= TRANS_DP_PORT_SEL_B;
3343                         break;
3344                 case PCH_DP_C:
3345                         temp |= TRANS_DP_PORT_SEL_C;
3346                         break;
3347                 case PCH_DP_D:
3348                         temp |= TRANS_DP_PORT_SEL_D;
3349                         break;
3350                 default:
3351                         BUG();
3352                 }
3353
3354                 I915_WRITE(reg, temp);
3355         }
3356
3357         ironlake_enable_pch_transcoder(dev_priv, pipe);
3358 }
3359
3360 static void lpt_pch_enable(struct drm_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3366
3367         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3368
3369         lpt_program_iclkip(crtc);
3370
3371         /* Set transcoder timing. */
3372         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3373
3374         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3375 }
3376
3377 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3378 {
3379         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3380
3381         if (pll == NULL)
3382                 return;
3383
3384         if (pll->refcount == 0) {
3385                 WARN(1, "bad %s refcount\n", pll->name);
3386                 return;
3387         }
3388
3389         if (--pll->refcount == 0) {
3390                 WARN_ON(pll->on);
3391                 WARN_ON(pll->active);
3392         }
3393
3394         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3395 }
3396
3397 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3398 {
3399         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3400         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3401         enum intel_dpll_id i;
3402
3403         if (pll) {
3404                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3405                               crtc->base.base.id, pll->name);
3406                 intel_put_shared_dpll(crtc);
3407         }
3408
3409         if (HAS_PCH_IBX(dev_priv->dev)) {
3410                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3411                 i = (enum intel_dpll_id) crtc->pipe;
3412                 pll = &dev_priv->shared_dplls[i];
3413
3414                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3415                               crtc->base.base.id, pll->name);
3416
3417                 goto found;
3418         }
3419
3420         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3421                 pll = &dev_priv->shared_dplls[i];
3422
3423                 /* Only want to check enabled timings first */
3424                 if (pll->refcount == 0)
3425                         continue;
3426
3427                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3428                            sizeof(pll->hw_state)) == 0) {
3429                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3430                                       crtc->base.base.id,
3431                                       pll->name, pll->refcount, pll->active);
3432
3433                         goto found;
3434                 }
3435         }
3436
3437         /* Ok no matching timings, maybe there's a free one? */
3438         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3439                 pll = &dev_priv->shared_dplls[i];
3440                 if (pll->refcount == 0) {
3441                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3442                                       crtc->base.base.id, pll->name);
3443                         goto found;
3444                 }
3445         }
3446
3447         return NULL;
3448
3449 found:
3450         crtc->config.shared_dpll = i;
3451         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3452                          pipe_name(crtc->pipe));
3453
3454         if (pll->active == 0) {
3455                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3456                        sizeof(pll->hw_state));
3457
3458                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3459                 WARN_ON(pll->on);
3460                 assert_shared_dpll_disabled(dev_priv, pll);
3461
3462                 pll->mode_set(dev_priv, pll);
3463         }
3464         pll->refcount++;
3465
3466         return pll;
3467 }
3468
3469 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3470 {
3471         struct drm_i915_private *dev_priv = dev->dev_private;
3472         int dslreg = PIPEDSL(pipe);
3473         u32 temp;
3474
3475         temp = I915_READ(dslreg);
3476         udelay(500);
3477         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3478                 if (wait_for(I915_READ(dslreg) != temp, 5))
3479                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3480         }
3481 }
3482
3483 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3484 {
3485         struct drm_device *dev = crtc->base.dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         int pipe = crtc->pipe;
3488
3489         if (crtc->config.pch_pfit.enabled) {
3490                 /* Force use of hard-coded filter coefficients
3491                  * as some pre-programmed values are broken,
3492                  * e.g. x201.
3493                  */
3494                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3495                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3496                                                  PF_PIPE_SEL_IVB(pipe));
3497                 else
3498                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3499                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3500                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3501         }
3502 }
3503
3504 static void intel_enable_planes(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3508         struct drm_plane *plane;
3509         struct intel_plane *intel_plane;
3510
3511         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3512                 intel_plane = to_intel_plane(plane);
3513                 if (intel_plane->pipe == pipe)
3514                         intel_plane_restore(&intel_plane->base);
3515         }
3516 }
3517
3518 static void intel_disable_planes(struct drm_crtc *crtc)
3519 {
3520         struct drm_device *dev = crtc->dev;
3521         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3522         struct drm_plane *plane;
3523         struct intel_plane *intel_plane;
3524
3525         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3526                 intel_plane = to_intel_plane(plane);
3527                 if (intel_plane->pipe == pipe)
3528                         intel_plane_disable(&intel_plane->base);
3529         }
3530 }
3531
3532 void hsw_enable_ips(struct intel_crtc *crtc)
3533 {
3534         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3535
3536         if (!crtc->config.ips_enabled)
3537                 return;
3538
3539         /* We can only enable IPS after we enable a plane and wait for a vblank.
3540          * We guarantee that the plane is enabled by calling intel_enable_ips
3541          * only after intel_enable_plane. And intel_enable_plane already waits
3542          * for a vblank, so all we need to do here is to enable the IPS bit. */
3543         assert_plane_enabled(dev_priv, crtc->plane);
3544         if (IS_BROADWELL(crtc->base.dev)) {
3545                 mutex_lock(&dev_priv->rps.hw_lock);
3546                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3547                 mutex_unlock(&dev_priv->rps.hw_lock);
3548                 /* Quoting Art Runyan: "its not safe to expect any particular
3549                  * value in IPS_CTL bit 31 after enabling IPS through the
3550                  * mailbox." Moreover, the mailbox may return a bogus state,
3551                  * so we need to just enable it and continue on.
3552                  */
3553         } else {
3554                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3555                 /* The bit only becomes 1 in the next vblank, so this wait here
3556                  * is essentially intel_wait_for_vblank. If we don't have this
3557                  * and don't wait for vblanks until the end of crtc_enable, then
3558                  * the HW state readout code will complain that the expected
3559                  * IPS_CTL value is not the one we read. */
3560                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3561                         DRM_ERROR("Timed out waiting for IPS enable\n");
3562         }
3563 }
3564
3565 void hsw_disable_ips(struct intel_crtc *crtc)
3566 {
3567         struct drm_device *dev = crtc->base.dev;
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569
3570         if (!crtc->config.ips_enabled)
3571                 return;
3572
3573         assert_plane_enabled(dev_priv, crtc->plane);
3574         if (IS_BROADWELL(dev)) {
3575                 mutex_lock(&dev_priv->rps.hw_lock);
3576                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3577                 mutex_unlock(&dev_priv->rps.hw_lock);
3578                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3579                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3580                         DRM_ERROR("Timed out waiting for IPS disable\n");
3581         } else {
3582                 I915_WRITE(IPS_CTL, 0);
3583                 POSTING_READ(IPS_CTL);
3584         }
3585
3586         /* We need to wait for a vblank before we can disable the plane. */
3587         intel_wait_for_vblank(dev, crtc->pipe);
3588 }
3589
3590 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3591 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3592 {
3593         struct drm_device *dev = crtc->dev;
3594         struct drm_i915_private *dev_priv = dev->dev_private;
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         enum pipe pipe = intel_crtc->pipe;
3597         int palreg = PALETTE(pipe);
3598         int i;
3599         bool reenable_ips = false;
3600
3601         /* The clocks have to be on to load the palette. */
3602         if (!crtc->enabled || !intel_crtc->active)
3603                 return;
3604
3605         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3606                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3607                         assert_dsi_pll_enabled(dev_priv);
3608                 else
3609                         assert_pll_enabled(dev_priv, pipe);
3610         }
3611
3612         /* use legacy palette for Ironlake */
3613         if (HAS_PCH_SPLIT(dev))
3614                 palreg = LGC_PALETTE(pipe);
3615
3616         /* Workaround : Do not read or write the pipe palette/gamma data while
3617          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3618          */
3619         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3620             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3621              GAMMA_MODE_MODE_SPLIT)) {
3622                 hsw_disable_ips(intel_crtc);
3623                 reenable_ips = true;
3624         }
3625
3626         for (i = 0; i < 256; i++) {
3627                 I915_WRITE(palreg + 4 * i,
3628                            (intel_crtc->lut_r[i] << 16) |
3629                            (intel_crtc->lut_g[i] << 8) |
3630                            intel_crtc->lut_b[i]);
3631         }
3632
3633         if (reenable_ips)
3634                 hsw_enable_ips(intel_crtc);
3635 }
3636
3637 static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
3638 {
3639         struct drm_device *dev = crtc->dev;
3640         struct drm_i915_private *dev_priv = dev->dev_private;
3641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3642         int pipe = intel_crtc->pipe;
3643         int plane = intel_crtc->plane;
3644
3645         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3646         intel_enable_planes(crtc);
3647         intel_crtc_update_cursor(crtc, true);
3648
3649         hsw_enable_ips(intel_crtc);
3650
3651         mutex_lock(&dev->struct_mutex);
3652         intel_update_fbc(dev);
3653         mutex_unlock(&dev->struct_mutex);
3654 }
3655
3656 static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
3657 {
3658         struct drm_device *dev = crtc->dev;
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3661         int pipe = intel_crtc->pipe;
3662         int plane = intel_crtc->plane;
3663
3664         intel_crtc_wait_for_pending_flips(crtc);
3665         drm_vblank_off(dev, pipe);
3666
3667         if (dev_priv->fbc.plane == plane)
3668                 intel_disable_fbc(dev);
3669
3670         hsw_disable_ips(intel_crtc);
3671
3672         intel_crtc_update_cursor(crtc, false);
3673         intel_disable_planes(crtc);
3674         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3675 }
3676
3677 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3678 {
3679         struct drm_device *dev = crtc->dev;
3680         struct drm_i915_private *dev_priv = dev->dev_private;
3681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3682         struct intel_encoder *encoder;
3683         int pipe = intel_crtc->pipe;
3684
3685         WARN_ON(!crtc->enabled);
3686
3687         if (intel_crtc->active)
3688                 return;
3689
3690         intel_crtc->active = true;
3691
3692         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3693         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3694
3695         for_each_encoder_on_crtc(dev, crtc, encoder)
3696                 if (encoder->pre_enable)
3697                         encoder->pre_enable(encoder);
3698
3699         if (intel_crtc->config.has_pch_encoder) {
3700                 /* Note: FDI PLL enabling _must_ be done before we enable the
3701                  * cpu pipes, hence this is separate from all the other fdi/pch
3702                  * enabling. */
3703                 ironlake_fdi_pll_enable(intel_crtc);
3704         } else {
3705                 assert_fdi_tx_disabled(dev_priv, pipe);
3706                 assert_fdi_rx_disabled(dev_priv, pipe);
3707         }
3708
3709         ironlake_pfit_enable(intel_crtc);
3710
3711         /*
3712          * On ILK+ LUT must be loaded before the pipe is running but with
3713          * clocks enabled
3714          */
3715         intel_crtc_load_lut(crtc);
3716
3717         intel_update_watermarks(crtc);
3718         intel_enable_pipe(intel_crtc);
3719
3720         if (intel_crtc->config.has_pch_encoder)
3721                 ironlake_pch_enable(crtc);
3722
3723         for_each_encoder_on_crtc(dev, crtc, encoder)
3724                 encoder->enable(encoder);
3725
3726         if (HAS_PCH_CPT(dev))
3727                 cpt_verify_modeset(dev, intel_crtc->pipe);
3728
3729         ilk_crtc_enable_planes(crtc);
3730
3731         /*
3732          * There seems to be a race in PCH platform hw (at least on some
3733          * outputs) where an enabled pipe still completes any pageflip right
3734          * away (as if the pipe is off) instead of waiting for vblank. As soon
3735          * as the first vblank happend, everything works as expected. Hence just
3736          * wait for one vblank before returning to avoid strange things
3737          * happening.
3738          */
3739         intel_wait_for_vblank(dev, intel_crtc->pipe);
3740 }
3741
3742 /* IPS only exists on ULT machines and is tied to pipe A. */
3743 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3744 {
3745         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3746 }
3747
3748 /*
3749  * This implements the workaround described in the "notes" section of the mode
3750  * set sequence documentation. When going from no pipes or single pipe to
3751  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3752  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3753  */
3754 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3755 {
3756         struct drm_device *dev = crtc->base.dev;
3757         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3758
3759         /* We want to get the other_active_crtc only if there's only 1 other
3760          * active crtc. */
3761         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3762                 if (!crtc_it->active || crtc_it == crtc)
3763                         continue;
3764
3765                 if (other_active_crtc)
3766                         return;
3767
3768                 other_active_crtc = crtc_it;
3769         }
3770         if (!other_active_crtc)
3771                 return;
3772
3773         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3774         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3775 }
3776
3777 static void haswell_crtc_enable(struct drm_crtc *crtc)
3778 {
3779         struct drm_device *dev = crtc->dev;
3780         struct drm_i915_private *dev_priv = dev->dev_private;
3781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782         struct intel_encoder *encoder;
3783         int pipe = intel_crtc->pipe;
3784
3785         WARN_ON(!crtc->enabled);
3786
3787         if (intel_crtc->active)
3788                 return;
3789
3790         intel_crtc->active = true;
3791
3792         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3793         if (intel_crtc->config.has_pch_encoder)
3794                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3795
3796         if (intel_crtc->config.has_pch_encoder)
3797                 dev_priv->display.fdi_link_train(crtc);
3798
3799         for_each_encoder_on_crtc(dev, crtc, encoder)
3800                 if (encoder->pre_enable)
3801                         encoder->pre_enable(encoder);
3802
3803         intel_ddi_enable_pipe_clock(intel_crtc);
3804
3805         ironlake_pfit_enable(intel_crtc);
3806
3807         /*
3808          * On ILK+ LUT must be loaded before the pipe is running but with
3809          * clocks enabled
3810          */
3811         intel_crtc_load_lut(crtc);
3812
3813         intel_ddi_set_pipe_settings(crtc);
3814         intel_ddi_enable_transcoder_func(crtc);
3815
3816         intel_update_watermarks(crtc);
3817         intel_enable_pipe(intel_crtc);
3818
3819         if (intel_crtc->config.has_pch_encoder)
3820                 lpt_pch_enable(crtc);
3821
3822         for_each_encoder_on_crtc(dev, crtc, encoder) {
3823                 encoder->enable(encoder);
3824                 intel_opregion_notify_encoder(encoder, true);
3825         }
3826
3827         /* If we change the relative order between pipe/planes enabling, we need
3828          * to change the workaround. */
3829         haswell_mode_set_planes_workaround(intel_crtc);
3830         ilk_crtc_enable_planes(crtc);
3831 }
3832
3833 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3834 {
3835         struct drm_device *dev = crtc->base.dev;
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837         int pipe = crtc->pipe;
3838
3839         /* To avoid upsetting the power well on haswell only disable the pfit if
3840          * it's in use. The hw state code will make sure we get this right. */
3841         if (crtc->config.pch_pfit.enabled) {
3842                 I915_WRITE(PF_CTL(pipe), 0);
3843                 I915_WRITE(PF_WIN_POS(pipe), 0);
3844                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3845         }
3846 }
3847
3848 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3849 {
3850         struct drm_device *dev = crtc->dev;
3851         struct drm_i915_private *dev_priv = dev->dev_private;
3852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3853         struct intel_encoder *encoder;
3854         int pipe = intel_crtc->pipe;
3855         u32 reg, temp;
3856
3857         if (!intel_crtc->active)
3858                 return;
3859
3860         ilk_crtc_disable_planes(crtc);
3861
3862         for_each_encoder_on_crtc(dev, crtc, encoder)
3863                 encoder->disable(encoder);
3864
3865         if (intel_crtc->config.has_pch_encoder)
3866                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3867
3868         intel_disable_pipe(dev_priv, pipe);
3869
3870         ironlake_pfit_disable(intel_crtc);
3871
3872         for_each_encoder_on_crtc(dev, crtc, encoder)
3873                 if (encoder->post_disable)
3874                         encoder->post_disable(encoder);
3875
3876         if (intel_crtc->config.has_pch_encoder) {
3877                 ironlake_fdi_disable(crtc);
3878
3879                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3880                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3881
3882                 if (HAS_PCH_CPT(dev)) {
3883                         /* disable TRANS_DP_CTL */
3884                         reg = TRANS_DP_CTL(pipe);
3885                         temp = I915_READ(reg);
3886                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3887                                   TRANS_DP_PORT_SEL_MASK);
3888                         temp |= TRANS_DP_PORT_SEL_NONE;
3889                         I915_WRITE(reg, temp);
3890
3891                         /* disable DPLL_SEL */
3892                         temp = I915_READ(PCH_DPLL_SEL);
3893                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3894                         I915_WRITE(PCH_DPLL_SEL, temp);
3895                 }
3896
3897                 /* disable PCH DPLL */
3898                 intel_disable_shared_dpll(intel_crtc);
3899
3900                 ironlake_fdi_pll_disable(intel_crtc);
3901         }
3902
3903         intel_crtc->active = false;
3904         intel_update_watermarks(crtc);
3905
3906         mutex_lock(&dev->struct_mutex);
3907         intel_update_fbc(dev);
3908         mutex_unlock(&dev->struct_mutex);
3909 }
3910
3911 static void haswell_crtc_disable(struct drm_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916         struct intel_encoder *encoder;
3917         int pipe = intel_crtc->pipe;
3918         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3919
3920         if (!intel_crtc->active)
3921                 return;
3922
3923         ilk_crtc_disable_planes(crtc);
3924
3925         for_each_encoder_on_crtc(dev, crtc, encoder) {
3926                 intel_opregion_notify_encoder(encoder, false);
3927                 encoder->disable(encoder);
3928         }
3929
3930         if (intel_crtc->config.has_pch_encoder)
3931                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3932         intel_disable_pipe(dev_priv, pipe);
3933
3934         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3935
3936         ironlake_pfit_disable(intel_crtc);
3937
3938         intel_ddi_disable_pipe_clock(intel_crtc);
3939
3940         for_each_encoder_on_crtc(dev, crtc, encoder)
3941                 if (encoder->post_disable)
3942                         encoder->post_disable(encoder);
3943
3944         if (intel_crtc->config.has_pch_encoder) {
3945                 lpt_disable_pch_transcoder(dev_priv);
3946                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3947                 intel_ddi_fdi_disable(crtc);
3948         }
3949
3950         intel_crtc->active = false;
3951         intel_update_watermarks(crtc);
3952
3953         mutex_lock(&dev->struct_mutex);
3954         intel_update_fbc(dev);
3955         mutex_unlock(&dev->struct_mutex);
3956 }
3957
3958 static void ironlake_crtc_off(struct drm_crtc *crtc)
3959 {
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         intel_put_shared_dpll(intel_crtc);
3962 }
3963
3964 static void haswell_crtc_off(struct drm_crtc *crtc)
3965 {
3966         intel_ddi_put_crtc_pll(crtc);
3967 }
3968
3969 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3970 {
3971         if (!enable && intel_crtc->overlay) {
3972                 struct drm_device *dev = intel_crtc->base.dev;
3973                 struct drm_i915_private *dev_priv = dev->dev_private;
3974
3975                 mutex_lock(&dev->struct_mutex);
3976                 dev_priv->mm.interruptible = false;
3977                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3978                 dev_priv->mm.interruptible = true;
3979                 mutex_unlock(&dev->struct_mutex);
3980         }
3981
3982         /* Let userspace switch the overlay on again. In most cases userspace
3983          * has to recompute where to put it anyway.
3984          */
3985 }
3986
3987 /**
3988  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3989  * cursor plane briefly if not already running after enabling the display
3990  * plane.
3991  * This workaround avoids occasional blank screens when self refresh is
3992  * enabled.
3993  */
3994 static void
3995 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3996 {
3997         u32 cntl = I915_READ(CURCNTR(pipe));
3998
3999         if ((cntl & CURSOR_MODE) == 0) {
4000                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4001
4002                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4003                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4004                 intel_wait_for_vblank(dev_priv->dev, pipe);
4005                 I915_WRITE(CURCNTR(pipe), cntl);
4006                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4007                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4008         }
4009 }
4010
4011 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4012 {
4013         struct drm_device *dev = crtc->base.dev;
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         struct intel_crtc_config *pipe_config = &crtc->config;
4016
4017         if (!crtc->config.gmch_pfit.control)
4018                 return;
4019
4020         /*
4021          * The panel fitter should only be adjusted whilst the pipe is disabled,
4022          * according to register description and PRM.
4023          */
4024         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4025         assert_pipe_disabled(dev_priv, crtc->pipe);
4026
4027         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4028         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4029
4030         /* Border color in case we don't scale up to the full screen. Black by
4031          * default, change to something else for debugging. */
4032         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4033 }
4034
4035 #define for_each_power_domain(domain, mask)                             \
4036         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4037                 if ((1 << (domain)) & (mask))
4038
4039 enum intel_display_power_domain
4040 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4041 {
4042         struct drm_device *dev = intel_encoder->base.dev;
4043         struct intel_digital_port *intel_dig_port;
4044
4045         switch (intel_encoder->type) {
4046         case INTEL_OUTPUT_UNKNOWN:
4047                 /* Only DDI platforms should ever use this output type */
4048                 WARN_ON_ONCE(!HAS_DDI(dev));
4049         case INTEL_OUTPUT_DISPLAYPORT:
4050         case INTEL_OUTPUT_HDMI:
4051         case INTEL_OUTPUT_EDP:
4052                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4053                 switch (intel_dig_port->port) {
4054                 case PORT_A:
4055                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4056                 case PORT_B:
4057                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4058                 case PORT_C:
4059                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4060                 case PORT_D:
4061                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4062                 default:
4063                         WARN_ON_ONCE(1);
4064                         return POWER_DOMAIN_PORT_OTHER;
4065                 }
4066         case INTEL_OUTPUT_ANALOG:
4067                 return POWER_DOMAIN_PORT_CRT;
4068         case INTEL_OUTPUT_DSI:
4069                 return POWER_DOMAIN_PORT_DSI;
4070         default:
4071                 return POWER_DOMAIN_PORT_OTHER;
4072         }
4073 }
4074
4075 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4076 {
4077         struct drm_device *dev = crtc->dev;
4078         struct intel_encoder *intel_encoder;
4079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4080         enum pipe pipe = intel_crtc->pipe;
4081         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4082         unsigned long mask;
4083         enum transcoder transcoder;
4084
4085         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4086
4087         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4088         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4089         if (pfit_enabled)
4090                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4091
4092         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4093                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4094
4095         return mask;
4096 }
4097
4098 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4099                                   bool enable)
4100 {
4101         if (dev_priv->power_domains.init_power_on == enable)
4102                 return;
4103
4104         if (enable)
4105                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4106         else
4107                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4108
4109         dev_priv->power_domains.init_power_on = enable;
4110 }
4111
4112 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4113 {
4114         struct drm_i915_private *dev_priv = dev->dev_private;
4115         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4116         struct intel_crtc *crtc;
4117
4118         /*
4119          * First get all needed power domains, then put all unneeded, to avoid
4120          * any unnecessary toggling of the power wells.
4121          */
4122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4123                 enum intel_display_power_domain domain;
4124
4125                 if (!crtc->base.enabled)
4126                         continue;
4127
4128                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4129
4130                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4131                         intel_display_power_get(dev_priv, domain);
4132         }
4133
4134         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4135                 enum intel_display_power_domain domain;
4136
4137                 for_each_power_domain(domain, crtc->enabled_power_domains)
4138                         intel_display_power_put(dev_priv, domain);
4139
4140                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4141         }
4142
4143         intel_display_set_init_power(dev_priv, false);
4144 }
4145
4146 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4147 {
4148         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4149
4150         /* Obtain SKU information */
4151         mutex_lock(&dev_priv->dpio_lock);
4152         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4153                 CCK_FUSE_HPLL_FREQ_MASK;
4154         mutex_unlock(&dev_priv->dpio_lock);
4155
4156         return vco_freq[hpll_freq];
4157 }
4158
4159 /* Adjust CDclk dividers to allow high res or save power if possible */
4160 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4161 {
4162         struct drm_i915_private *dev_priv = dev->dev_private;
4163         u32 val, cmd;
4164
4165         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4166         dev_priv->vlv_cdclk_freq = cdclk;
4167
4168         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4169                 cmd = 2;
4170         else if (cdclk == 266)
4171                 cmd = 1;
4172         else
4173                 cmd = 0;
4174
4175         mutex_lock(&dev_priv->rps.hw_lock);
4176         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4177         val &= ~DSPFREQGUAR_MASK;
4178         val |= (cmd << DSPFREQGUAR_SHIFT);
4179         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4180         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4181                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4182                      50)) {
4183                 DRM_ERROR("timed out waiting for CDclk change\n");
4184         }
4185         mutex_unlock(&dev_priv->rps.hw_lock);
4186
4187         if (cdclk == 400) {
4188                 u32 divider, vco;
4189
4190                 vco = valleyview_get_vco(dev_priv);
4191                 divider = ((vco << 1) / cdclk) - 1;
4192
4193                 mutex_lock(&dev_priv->dpio_lock);
4194                 /* adjust cdclk divider */
4195                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4196                 val &= ~0xf;
4197                 val |= divider;
4198                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4199                 mutex_unlock(&dev_priv->dpio_lock);
4200         }
4201
4202         mutex_lock(&dev_priv->dpio_lock);
4203         /* adjust self-refresh exit latency value */
4204         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4205         val &= ~0x7f;
4206
4207         /*
4208          * For high bandwidth configs, we set a higher latency in the bunit
4209          * so that the core display fetch happens in time to avoid underruns.
4210          */
4211         if (cdclk == 400)
4212                 val |= 4500 / 250; /* 4.5 usec */
4213         else
4214                 val |= 3000 / 250; /* 3.0 usec */
4215         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4216         mutex_unlock(&dev_priv->dpio_lock);
4217
4218         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4219         intel_i2c_reset(dev);
4220 }
4221
4222 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4223 {
4224         int cur_cdclk, vco;
4225         int divider;
4226
4227         vco = valleyview_get_vco(dev_priv);
4228
4229         mutex_lock(&dev_priv->dpio_lock);
4230         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4231         mutex_unlock(&dev_priv->dpio_lock);
4232
4233         divider &= 0xf;
4234
4235         cur_cdclk = (vco << 1) / (divider + 1);
4236
4237         return cur_cdclk;
4238 }
4239
4240 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4241                                  int max_pixclk)
4242 {
4243         /*
4244          * Really only a few cases to deal with, as only 4 CDclks are supported:
4245          *   200MHz
4246          *   267MHz
4247          *   320MHz
4248          *   400MHz
4249          * So we check to see whether we're above 90% of the lower bin and
4250          * adjust if needed.
4251          */
4252         if (max_pixclk > 288000) {
4253                 return 400;
4254         } else if (max_pixclk > 240000) {
4255                 return 320;
4256         } else
4257                 return 266;
4258         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4259 }
4260
4261 /* compute the max pixel clock for new configuration */
4262 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4263 {
4264         struct drm_device *dev = dev_priv->dev;
4265         struct intel_crtc *intel_crtc;
4266         int max_pixclk = 0;
4267
4268         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4269                             base.head) {
4270                 if (intel_crtc->new_enabled)
4271                         max_pixclk = max(max_pixclk,
4272                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4273         }
4274
4275         return max_pixclk;
4276 }
4277
4278 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4279                                             unsigned *prepare_pipes)
4280 {
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         struct intel_crtc *intel_crtc;
4283         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4284
4285         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4286             dev_priv->vlv_cdclk_freq)
4287                 return;
4288
4289         /* disable/enable all currently active pipes while we change cdclk */
4290         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4291                             base.head)
4292                 if (intel_crtc->base.enabled)
4293                         *prepare_pipes |= (1 << intel_crtc->pipe);
4294 }
4295
4296 static void valleyview_modeset_global_resources(struct drm_device *dev)
4297 {
4298         struct drm_i915_private *dev_priv = dev->dev_private;
4299         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4300         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4301
4302         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4303                 valleyview_set_cdclk(dev, req_cdclk);
4304         modeset_update_crtc_power_domains(dev);
4305 }
4306
4307 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4308 {
4309         struct drm_device *dev = crtc->dev;
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4312         struct intel_encoder *encoder;
4313         int pipe = intel_crtc->pipe;
4314         int plane = intel_crtc->plane;
4315         bool is_dsi;
4316
4317         WARN_ON(!crtc->enabled);
4318
4319         if (intel_crtc->active)
4320                 return;
4321
4322         intel_crtc->active = true;
4323
4324         for_each_encoder_on_crtc(dev, crtc, encoder)
4325                 if (encoder->pre_pll_enable)
4326                         encoder->pre_pll_enable(encoder);
4327
4328         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4329
4330         if (!is_dsi)
4331                 vlv_enable_pll(intel_crtc);
4332
4333         for_each_encoder_on_crtc(dev, crtc, encoder)
4334                 if (encoder->pre_enable)
4335                         encoder->pre_enable(encoder);
4336
4337         i9xx_pfit_enable(intel_crtc);
4338
4339         intel_crtc_load_lut(crtc);
4340
4341         intel_update_watermarks(crtc);
4342         intel_enable_pipe(intel_crtc);
4343         intel_wait_for_vblank(dev_priv->dev, pipe);
4344         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4345
4346         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4347         intel_enable_planes(crtc);
4348         intel_crtc_update_cursor(crtc, true);
4349
4350         intel_update_fbc(dev);
4351
4352         for_each_encoder_on_crtc(dev, crtc, encoder)
4353                 encoder->enable(encoder);
4354 }
4355
4356 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4357 {
4358         struct drm_device *dev = crtc->dev;
4359         struct drm_i915_private *dev_priv = dev->dev_private;
4360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361         struct intel_encoder *encoder;
4362         int pipe = intel_crtc->pipe;
4363         int plane = intel_crtc->plane;
4364
4365         WARN_ON(!crtc->enabled);
4366
4367         if (intel_crtc->active)
4368                 return;
4369
4370         intel_crtc->active = true;
4371
4372         for_each_encoder_on_crtc(dev, crtc, encoder)
4373                 if (encoder->pre_enable)
4374                         encoder->pre_enable(encoder);
4375
4376         i9xx_enable_pll(intel_crtc);
4377
4378         i9xx_pfit_enable(intel_crtc);
4379
4380         intel_crtc_load_lut(crtc);
4381
4382         intel_update_watermarks(crtc);
4383         intel_enable_pipe(intel_crtc);
4384         intel_wait_for_vblank(dev_priv->dev, pipe);
4385         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4386
4387         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4388         intel_enable_planes(crtc);
4389         /* The fixup needs to happen before cursor is enabled */
4390         if (IS_G4X(dev))
4391                 g4x_fixup_plane(dev_priv, pipe);
4392         intel_crtc_update_cursor(crtc, true);
4393
4394         /* Give the overlay scaler a chance to enable if it's on this pipe */
4395         intel_crtc_dpms_overlay(intel_crtc, true);
4396
4397         intel_update_fbc(dev);
4398
4399         for_each_encoder_on_crtc(dev, crtc, encoder)
4400                 encoder->enable(encoder);
4401 }
4402
4403 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4404 {
4405         struct drm_device *dev = crtc->base.dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407
4408         if (!crtc->config.gmch_pfit.control)
4409                 return;
4410
4411         assert_pipe_disabled(dev_priv, crtc->pipe);
4412
4413         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4414                          I915_READ(PFIT_CONTROL));
4415         I915_WRITE(PFIT_CONTROL, 0);
4416 }
4417
4418 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4419 {
4420         struct drm_device *dev = crtc->dev;
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423         struct intel_encoder *encoder;
4424         int pipe = intel_crtc->pipe;
4425         int plane = intel_crtc->plane;
4426
4427         if (!intel_crtc->active)
4428                 return;
4429
4430         for_each_encoder_on_crtc(dev, crtc, encoder)
4431                 encoder->disable(encoder);
4432
4433         /* Give the overlay scaler a chance to disable if it's on this pipe */
4434         intel_crtc_wait_for_pending_flips(crtc);
4435         drm_vblank_off(dev, pipe);
4436
4437         if (dev_priv->fbc.plane == plane)
4438                 intel_disable_fbc(dev);
4439
4440         intel_crtc_dpms_overlay(intel_crtc, false);
4441         intel_crtc_update_cursor(crtc, false);
4442         intel_disable_planes(crtc);
4443         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4444
4445         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4446         intel_disable_pipe(dev_priv, pipe);
4447
4448         i9xx_pfit_disable(intel_crtc);
4449
4450         for_each_encoder_on_crtc(dev, crtc, encoder)
4451                 if (encoder->post_disable)
4452                         encoder->post_disable(encoder);
4453
4454         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4455                 vlv_disable_pll(dev_priv, pipe);
4456         else if (!IS_VALLEYVIEW(dev))
4457                 i9xx_disable_pll(dev_priv, pipe);
4458
4459         intel_crtc->active = false;
4460         intel_update_watermarks(crtc);
4461
4462         intel_update_fbc(dev);
4463 }
4464
4465 static void i9xx_crtc_off(struct drm_crtc *crtc)
4466 {
4467 }
4468
4469 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4470                                     bool enabled)
4471 {
4472         struct drm_device *dev = crtc->dev;
4473         struct drm_i915_master_private *master_priv;
4474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475         int pipe = intel_crtc->pipe;
4476
4477         if (!dev->primary->master)
4478                 return;
4479
4480         master_priv = dev->primary->master->driver_priv;
4481         if (!master_priv->sarea_priv)
4482                 return;
4483
4484         switch (pipe) {
4485         case 0:
4486                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4487                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4488                 break;
4489         case 1:
4490                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4491                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4492                 break;
4493         default:
4494                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4495                 break;
4496         }
4497 }
4498
4499 /**
4500  * Sets the power management mode of the pipe and plane.
4501  */
4502 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4503 {
4504         struct drm_device *dev = crtc->dev;
4505         struct drm_i915_private *dev_priv = dev->dev_private;
4506         struct intel_encoder *intel_encoder;
4507         bool enable = false;
4508
4509         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4510                 enable |= intel_encoder->connectors_active;
4511
4512         if (enable)
4513                 dev_priv->display.crtc_enable(crtc);
4514         else
4515                 dev_priv->display.crtc_disable(crtc);
4516
4517         intel_crtc_update_sarea(crtc, enable);
4518 }
4519
4520 static void intel_crtc_disable(struct drm_crtc *crtc)
4521 {
4522         struct drm_device *dev = crtc->dev;
4523         struct drm_connector *connector;
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4526
4527         /* crtc should still be enabled when we disable it. */
4528         WARN_ON(!crtc->enabled);
4529
4530         dev_priv->display.crtc_disable(crtc);
4531         intel_crtc->eld_vld = false;
4532         intel_crtc_update_sarea(crtc, false);
4533         dev_priv->display.off(crtc);
4534
4535         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4536         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4537         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4538
4539         if (crtc->primary->fb) {
4540                 mutex_lock(&dev->struct_mutex);
4541                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4542                 mutex_unlock(&dev->struct_mutex);
4543                 crtc->primary->fb = NULL;
4544         }
4545
4546         /* Update computed state. */
4547         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4548                 if (!connector->encoder || !connector->encoder->crtc)
4549                         continue;
4550
4551                 if (connector->encoder->crtc != crtc)
4552                         continue;
4553
4554                 connector->dpms = DRM_MODE_DPMS_OFF;
4555                 to_intel_encoder(connector->encoder)->connectors_active = false;
4556         }
4557 }
4558
4559 void intel_encoder_destroy(struct drm_encoder *encoder)
4560 {
4561         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4562
4563         drm_encoder_cleanup(encoder);
4564         kfree(intel_encoder);
4565 }
4566
4567 /* Simple dpms helper for encoders with just one connector, no cloning and only
4568  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4569  * state of the entire output pipe. */
4570 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4571 {
4572         if (mode == DRM_MODE_DPMS_ON) {
4573                 encoder->connectors_active = true;
4574
4575                 intel_crtc_update_dpms(encoder->base.crtc);
4576         } else {
4577                 encoder->connectors_active = false;
4578
4579                 intel_crtc_update_dpms(encoder->base.crtc);
4580         }
4581 }
4582
4583 /* Cross check the actual hw state with our own modeset state tracking (and it's
4584  * internal consistency). */
4585 static void intel_connector_check_state(struct intel_connector *connector)
4586 {
4587         if (connector->get_hw_state(connector)) {
4588                 struct intel_encoder *encoder = connector->encoder;
4589                 struct drm_crtc *crtc;
4590                 bool encoder_enabled;
4591                 enum pipe pipe;
4592
4593                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4594                               connector->base.base.id,
4595                               drm_get_connector_name(&connector->base));
4596
4597                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4598                      "wrong connector dpms state\n");
4599                 WARN(connector->base.encoder != &encoder->base,
4600                      "active connector not linked to encoder\n");
4601                 WARN(!encoder->connectors_active,
4602                      "encoder->connectors_active not set\n");
4603
4604                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4605                 WARN(!encoder_enabled, "encoder not enabled\n");
4606                 if (WARN_ON(!encoder->base.crtc))
4607                         return;
4608
4609                 crtc = encoder->base.crtc;
4610
4611                 WARN(!crtc->enabled, "crtc not enabled\n");
4612                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4613                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4614                      "encoder active on the wrong pipe\n");
4615         }
4616 }
4617
4618 /* Even simpler default implementation, if there's really no special case to
4619  * consider. */
4620 void intel_connector_dpms(struct drm_connector *connector, int mode)
4621 {
4622         /* All the simple cases only support two dpms states. */
4623         if (mode != DRM_MODE_DPMS_ON)
4624                 mode = DRM_MODE_DPMS_OFF;
4625
4626         if (mode == connector->dpms)
4627                 return;
4628
4629         connector->dpms = mode;
4630
4631         /* Only need to change hw state when actually enabled */
4632         if (connector->encoder)
4633                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4634
4635         intel_modeset_check_state(connector->dev);
4636 }
4637
4638 /* Simple connector->get_hw_state implementation for encoders that support only
4639  * one connector and no cloning and hence the encoder state determines the state
4640  * of the connector. */
4641 bool intel_connector_get_hw_state(struct intel_connector *connector)
4642 {
4643         enum pipe pipe = 0;
4644         struct intel_encoder *encoder = connector->encoder;
4645
4646         return encoder->get_hw_state(encoder, &pipe);
4647 }
4648
4649 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4650                                      struct intel_crtc_config *pipe_config)
4651 {
4652         struct drm_i915_private *dev_priv = dev->dev_private;
4653         struct intel_crtc *pipe_B_crtc =
4654                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4655
4656         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4657                       pipe_name(pipe), pipe_config->fdi_lanes);
4658         if (pipe_config->fdi_lanes > 4) {
4659                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4660                               pipe_name(pipe), pipe_config->fdi_lanes);
4661                 return false;
4662         }
4663
4664         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4665                 if (pipe_config->fdi_lanes > 2) {
4666                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4667                                       pipe_config->fdi_lanes);
4668                         return false;
4669                 } else {
4670                         return true;
4671                 }
4672         }
4673
4674         if (INTEL_INFO(dev)->num_pipes == 2)
4675                 return true;
4676
4677         /* Ivybridge 3 pipe is really complicated */
4678         switch (pipe) {
4679         case PIPE_A:
4680                 return true;
4681         case PIPE_B:
4682                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4683                     pipe_config->fdi_lanes > 2) {
4684                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4685                                       pipe_name(pipe), pipe_config->fdi_lanes);
4686                         return false;
4687                 }
4688                 return true;
4689         case PIPE_C:
4690                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4691                     pipe_B_crtc->config.fdi_lanes <= 2) {
4692                         if (pipe_config->fdi_lanes > 2) {
4693                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4694                                               pipe_name(pipe), pipe_config->fdi_lanes);
4695                                 return false;
4696                         }
4697                 } else {
4698                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4699                         return false;
4700                 }
4701                 return true;
4702         default:
4703                 BUG();
4704         }
4705 }
4706
4707 #define RETRY 1
4708 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4709                                        struct intel_crtc_config *pipe_config)
4710 {
4711         struct drm_device *dev = intel_crtc->base.dev;
4712         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4713         int lane, link_bw, fdi_dotclock;
4714         bool setup_ok, needs_recompute = false;
4715
4716 retry:
4717         /* FDI is a binary signal running at ~2.7GHz, encoding
4718          * each output octet as 10 bits. The actual frequency
4719          * is stored as a divider into a 100MHz clock, and the
4720          * mode pixel clock is stored in units of 1KHz.
4721          * Hence the bw of each lane in terms of the mode signal
4722          * is:
4723          */
4724         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4725
4726         fdi_dotclock = adjusted_mode->crtc_clock;
4727
4728         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4729                                            pipe_config->pipe_bpp);
4730
4731         pipe_config->fdi_lanes = lane;
4732
4733         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4734                                link_bw, &pipe_config->fdi_m_n);
4735
4736         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4737                                             intel_crtc->pipe, pipe_config);
4738         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4739                 pipe_config->pipe_bpp -= 2*3;
4740                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4741                               pipe_config->pipe_bpp);
4742                 needs_recompute = true;
4743                 pipe_config->bw_constrained = true;
4744
4745                 goto retry;
4746         }
4747
4748         if (needs_recompute)
4749                 return RETRY;
4750
4751         return setup_ok ? 0 : -EINVAL;
4752 }
4753
4754 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4755                                    struct intel_crtc_config *pipe_config)
4756 {
4757         pipe_config->ips_enabled = i915.enable_ips &&
4758                                    hsw_crtc_supports_ips(crtc) &&
4759                                    pipe_config->pipe_bpp <= 24;
4760 }
4761
4762 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4763                                      struct intel_crtc_config *pipe_config)
4764 {
4765         struct drm_device *dev = crtc->base.dev;
4766         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4767
4768         /* FIXME should check pixel clock limits on all platforms */
4769         if (INTEL_INFO(dev)->gen < 4) {
4770                 struct drm_i915_private *dev_priv = dev->dev_private;
4771                 int clock_limit =
4772                         dev_priv->display.get_display_clock_speed(dev);
4773
4774                 /*
4775                  * Enable pixel doubling when the dot clock
4776                  * is > 90% of the (display) core speed.
4777                  *
4778                  * GDG double wide on either pipe,
4779                  * otherwise pipe A only.
4780                  */
4781                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4782                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4783                         clock_limit *= 2;
4784                         pipe_config->double_wide = true;
4785                 }
4786
4787                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4788                         return -EINVAL;
4789         }
4790
4791         /*
4792          * Pipe horizontal size must be even in:
4793          * - DVO ganged mode
4794          * - LVDS dual channel mode
4795          * - Double wide pipe
4796          */
4797         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4798              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4799                 pipe_config->pipe_src_w &= ~1;
4800
4801         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4802          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4803          */
4804         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4805                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4806                 return -EINVAL;
4807
4808         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4809                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4810         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4811                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4812                  * for lvds. */
4813                 pipe_config->pipe_bpp = 8*3;
4814         }
4815
4816         if (HAS_IPS(dev))
4817                 hsw_compute_ips_config(crtc, pipe_config);
4818
4819         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4820          * clock survives for now. */
4821         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4822                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4823
4824         if (pipe_config->has_pch_encoder)
4825                 return ironlake_fdi_compute_config(crtc, pipe_config);
4826
4827         return 0;
4828 }
4829
4830 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4831 {
4832         return 400000; /* FIXME */
4833 }
4834
4835 static int i945_get_display_clock_speed(struct drm_device *dev)
4836 {
4837         return 400000;
4838 }
4839
4840 static int i915_get_display_clock_speed(struct drm_device *dev)
4841 {
4842         return 333000;
4843 }
4844
4845 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4846 {
4847         return 200000;
4848 }
4849
4850 static int pnv_get_display_clock_speed(struct drm_device *dev)
4851 {
4852         u16 gcfgc = 0;
4853
4854         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4855
4856         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4857         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4858                 return 267000;
4859         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4860                 return 333000;
4861         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4862                 return 444000;
4863         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4864                 return 200000;
4865         default:
4866                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4867         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4868                 return 133000;
4869         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4870                 return 167000;
4871         }
4872 }
4873
4874 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4875 {
4876         u16 gcfgc = 0;
4877
4878         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4879
4880         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4881                 return 133000;
4882         else {
4883                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4884                 case GC_DISPLAY_CLOCK_333_MHZ:
4885                         return 333000;
4886                 default:
4887                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4888                         return 190000;
4889                 }
4890         }
4891 }
4892
4893 static int i865_get_display_clock_speed(struct drm_device *dev)
4894 {
4895         return 266000;
4896 }
4897
4898 static int i855_get_display_clock_speed(struct drm_device *dev)
4899 {
4900         u16 hpllcc = 0;
4901         /* Assume that the hardware is in the high speed state.  This
4902          * should be the default.
4903          */
4904         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4905         case GC_CLOCK_133_200:
4906         case GC_CLOCK_100_200:
4907                 return 200000;
4908         case GC_CLOCK_166_250:
4909                 return 250000;
4910         case GC_CLOCK_100_133:
4911                 return 133000;
4912         }
4913
4914         /* Shouldn't happen */
4915         return 0;
4916 }
4917
4918 static int i830_get_display_clock_speed(struct drm_device *dev)
4919 {
4920         return 133000;
4921 }
4922
4923 static void
4924 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4925 {
4926         while (*num > DATA_LINK_M_N_MASK ||
4927                *den > DATA_LINK_M_N_MASK) {
4928                 *num >>= 1;
4929                 *den >>= 1;
4930         }
4931 }
4932
4933 static void compute_m_n(unsigned int m, unsigned int n,
4934                         uint32_t *ret_m, uint32_t *ret_n)
4935 {
4936         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4937         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4938         intel_reduce_m_n_ratio(ret_m, ret_n);
4939 }
4940
4941 void
4942 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4943                        int pixel_clock, int link_clock,
4944                        struct intel_link_m_n *m_n)
4945 {
4946         m_n->tu = 64;
4947
4948         compute_m_n(bits_per_pixel * pixel_clock,
4949                     link_clock * nlanes * 8,
4950                     &m_n->gmch_m, &m_n->gmch_n);
4951
4952         compute_m_n(pixel_clock, link_clock,
4953                     &m_n->link_m, &m_n->link_n);
4954 }
4955
4956 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4957 {
4958         if (i915.panel_use_ssc >= 0)
4959                 return i915.panel_use_ssc != 0;
4960         return dev_priv->vbt.lvds_use_ssc
4961                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4962 }
4963
4964 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         int refclk;
4969
4970         if (IS_VALLEYVIEW(dev)) {
4971                 refclk = 100000;
4972         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4973             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4974                 refclk = dev_priv->vbt.lvds_ssc_freq;
4975                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4976         } else if (!IS_GEN2(dev)) {
4977                 refclk = 96000;
4978         } else {
4979                 refclk = 48000;
4980         }
4981
4982         return refclk;
4983 }
4984
4985 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4986 {
4987         return (1 << dpll->n) << 16 | dpll->m2;
4988 }
4989
4990 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4991 {
4992         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4993 }
4994
4995 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4996                                      intel_clock_t *reduced_clock)
4997 {
4998         struct drm_device *dev = crtc->base.dev;
4999         struct drm_i915_private *dev_priv = dev->dev_private;
5000         int pipe = crtc->pipe;
5001         u32 fp, fp2 = 0;
5002
5003         if (IS_PINEVIEW(dev)) {
5004                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5005                 if (reduced_clock)
5006                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5007         } else {
5008                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5009                 if (reduced_clock)
5010                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5011         }
5012
5013         I915_WRITE(FP0(pipe), fp);
5014         crtc->config.dpll_hw_state.fp0 = fp;
5015
5016         crtc->lowfreq_avail = false;
5017         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5018             reduced_clock && i915.powersave) {
5019                 I915_WRITE(FP1(pipe), fp2);
5020                 crtc->config.dpll_hw_state.fp1 = fp2;
5021                 crtc->lowfreq_avail = true;
5022         } else {
5023                 I915_WRITE(FP1(pipe), fp);
5024                 crtc->config.dpll_hw_state.fp1 = fp;
5025         }
5026 }
5027
5028 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5029                 pipe)
5030 {
5031         u32 reg_val;
5032
5033         /*
5034          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5035          * and set it to a reasonable value instead.
5036          */
5037         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5038         reg_val &= 0xffffff00;
5039         reg_val |= 0x00000030;
5040         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5041
5042         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5043         reg_val &= 0x8cffffff;
5044         reg_val = 0x8c000000;
5045         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5046
5047         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5048         reg_val &= 0xffffff00;
5049         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5050
5051         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5052         reg_val &= 0x00ffffff;
5053         reg_val |= 0xb0000000;
5054         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5055 }
5056
5057 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5058                                          struct intel_link_m_n *m_n)
5059 {
5060         struct drm_device *dev = crtc->base.dev;
5061         struct drm_i915_private *dev_priv = dev->dev_private;
5062         int pipe = crtc->pipe;
5063
5064         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5065         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5066         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5067         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5068 }
5069
5070 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5071                                          struct intel_link_m_n *m_n)
5072 {
5073         struct drm_device *dev = crtc->base.dev;
5074         struct drm_i915_private *dev_priv = dev->dev_private;
5075         int pipe = crtc->pipe;
5076         enum transcoder transcoder = crtc->config.cpu_transcoder;
5077
5078         if (INTEL_INFO(dev)->gen >= 5) {
5079                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5080                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5081                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5082                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5083         } else {
5084                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5085                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5086                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5087                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5088         }
5089 }
5090
5091 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5092 {
5093         if (crtc->config.has_pch_encoder)
5094                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5095         else
5096                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5097 }
5098
5099 static void vlv_update_pll(struct intel_crtc *crtc)
5100 {
5101         struct drm_device *dev = crtc->base.dev;
5102         struct drm_i915_private *dev_priv = dev->dev_private;
5103         int pipe = crtc->pipe;
5104         u32 dpll, mdiv;
5105         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5106         u32 coreclk, reg_val, dpll_md;
5107
5108         mutex_lock(&dev_priv->dpio_lock);
5109
5110         bestn = crtc->config.dpll.n;
5111         bestm1 = crtc->config.dpll.m1;
5112         bestm2 = crtc->config.dpll.m2;
5113         bestp1 = crtc->config.dpll.p1;
5114         bestp2 = crtc->config.dpll.p2;
5115
5116         /* See eDP HDMI DPIO driver vbios notes doc */
5117
5118         /* PLL B needs special handling */
5119         if (pipe)
5120                 vlv_pllb_recal_opamp(dev_priv, pipe);
5121
5122         /* Set up Tx target for periodic Rcomp update */
5123         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5124
5125         /* Disable target IRef on PLL */
5126         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5127         reg_val &= 0x00ffffff;
5128         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5129
5130         /* Disable fast lock */
5131         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5132
5133         /* Set idtafcrecal before PLL is enabled */
5134         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5135         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5136         mdiv |= ((bestn << DPIO_N_SHIFT));
5137         mdiv |= (1 << DPIO_K_SHIFT);
5138
5139         /*
5140          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5141          * but we don't support that).
5142          * Note: don't use the DAC post divider as it seems unstable.
5143          */
5144         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5145         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5146
5147         mdiv |= DPIO_ENABLE_CALIBRATION;
5148         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5149
5150         /* Set HBR and RBR LPF coefficients */
5151         if (crtc->config.port_clock == 162000 ||
5152             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5153             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5154                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5155                                  0x009f0003);
5156         else
5157                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5158                                  0x00d0000f);
5159
5160         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5161             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5162                 /* Use SSC source */
5163                 if (!pipe)
5164                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5165                                          0x0df40000);
5166                 else
5167                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5168                                          0x0df70000);
5169         } else { /* HDMI or VGA */
5170                 /* Use bend source */
5171                 if (!pipe)
5172                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5173                                          0x0df70000);
5174                 else
5175                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5176                                          0x0df40000);
5177         }
5178
5179         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5180         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5181         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5182             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5183                 coreclk |= 0x01000000;
5184         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5185
5186         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5187
5188         /*
5189          * Enable DPIO clock input. We should never disable the reference
5190          * clock for pipe B, since VGA hotplug / manual detection depends
5191          * on it.
5192          */
5193         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5194                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5195         /* We should never disable this, set it here for state tracking */
5196         if (pipe == PIPE_B)
5197                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5198         dpll |= DPLL_VCO_ENABLE;
5199         crtc->config.dpll_hw_state.dpll = dpll;
5200
5201         dpll_md = (crtc->config.pixel_multiplier - 1)
5202                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5203         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5204
5205         mutex_unlock(&dev_priv->dpio_lock);
5206 }
5207
5208 static void i9xx_update_pll(struct intel_crtc *crtc,
5209                             intel_clock_t *reduced_clock,
5210                             int num_connectors)
5211 {
5212         struct drm_device *dev = crtc->base.dev;
5213         struct drm_i915_private *dev_priv = dev->dev_private;
5214         u32 dpll;
5215         bool is_sdvo;
5216         struct dpll *clock = &crtc->config.dpll;
5217
5218         i9xx_update_pll_dividers(crtc, reduced_clock);
5219
5220         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5221                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5222
5223         dpll = DPLL_VGA_MODE_DIS;
5224
5225         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5226                 dpll |= DPLLB_MODE_LVDS;
5227         else
5228                 dpll |= DPLLB_MODE_DAC_SERIAL;
5229
5230         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5231                 dpll |= (crtc->config.pixel_multiplier - 1)
5232                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5233         }
5234
5235         if (is_sdvo)
5236                 dpll |= DPLL_SDVO_HIGH_SPEED;
5237
5238         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5239                 dpll |= DPLL_SDVO_HIGH_SPEED;
5240
5241         /* compute bitmask from p1 value */
5242         if (IS_PINEVIEW(dev))
5243                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5244         else {
5245                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5246                 if (IS_G4X(dev) && reduced_clock)
5247                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5248         }
5249         switch (clock->p2) {
5250         case 5:
5251                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5252                 break;
5253         case 7:
5254                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5255                 break;
5256         case 10:
5257                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5258                 break;
5259         case 14:
5260                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5261                 break;
5262         }
5263         if (INTEL_INFO(dev)->gen >= 4)
5264                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5265
5266         if (crtc->config.sdvo_tv_clock)
5267                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5268         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5269                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5270                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5271         else
5272                 dpll |= PLL_REF_INPUT_DREFCLK;
5273
5274         dpll |= DPLL_VCO_ENABLE;
5275         crtc->config.dpll_hw_state.dpll = dpll;
5276
5277         if (INTEL_INFO(dev)->gen >= 4) {
5278                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5279                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5280                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5281         }
5282 }
5283
5284 static void i8xx_update_pll(struct intel_crtc *crtc,
5285                             intel_clock_t *reduced_clock,
5286                             int num_connectors)
5287 {
5288         struct drm_device *dev = crtc->base.dev;
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290         u32 dpll;
5291         struct dpll *clock = &crtc->config.dpll;
5292
5293         i9xx_update_pll_dividers(crtc, reduced_clock);
5294
5295         dpll = DPLL_VGA_MODE_DIS;
5296
5297         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5298                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5299         } else {
5300                 if (clock->p1 == 2)
5301                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5302                 else
5303                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5304                 if (clock->p2 == 4)
5305                         dpll |= PLL_P2_DIVIDE_BY_4;
5306         }
5307
5308         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5309                 dpll |= DPLL_DVO_2X_MODE;
5310
5311         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5312                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5313                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5314         else
5315                 dpll |= PLL_REF_INPUT_DREFCLK;
5316
5317         dpll |= DPLL_VCO_ENABLE;
5318         crtc->config.dpll_hw_state.dpll = dpll;
5319 }
5320
5321 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5322 {
5323         struct drm_device *dev = intel_crtc->base.dev;
5324         struct drm_i915_private *dev_priv = dev->dev_private;
5325         enum pipe pipe = intel_crtc->pipe;
5326         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5327         struct drm_display_mode *adjusted_mode =
5328                 &intel_crtc->config.adjusted_mode;
5329         uint32_t crtc_vtotal, crtc_vblank_end;
5330         int vsyncshift = 0;
5331
5332         /* We need to be careful not to changed the adjusted mode, for otherwise
5333          * the hw state checker will get angry at the mismatch. */
5334         crtc_vtotal = adjusted_mode->crtc_vtotal;
5335         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5336
5337         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5338                 /* the chip adds 2 halflines automatically */
5339                 crtc_vtotal -= 1;
5340                 crtc_vblank_end -= 1;
5341
5342                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5343                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5344                 else
5345                         vsyncshift = adjusted_mode->crtc_hsync_start -
5346                                 adjusted_mode->crtc_htotal / 2;
5347                 if (vsyncshift < 0)
5348                         vsyncshift += adjusted_mode->crtc_htotal;
5349         }
5350
5351         if (INTEL_INFO(dev)->gen > 3)
5352                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5353
5354         I915_WRITE(HTOTAL(cpu_transcoder),
5355                    (adjusted_mode->crtc_hdisplay - 1) |
5356                    ((adjusted_mode->crtc_htotal - 1) << 16));
5357         I915_WRITE(HBLANK(cpu_transcoder),
5358                    (adjusted_mode->crtc_hblank_start - 1) |
5359                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5360         I915_WRITE(HSYNC(cpu_transcoder),
5361                    (adjusted_mode->crtc_hsync_start - 1) |
5362                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5363
5364         I915_WRITE(VTOTAL(cpu_transcoder),
5365                    (adjusted_mode->crtc_vdisplay - 1) |
5366                    ((crtc_vtotal - 1) << 16));
5367         I915_WRITE(VBLANK(cpu_transcoder),
5368                    (adjusted_mode->crtc_vblank_start - 1) |
5369                    ((crtc_vblank_end - 1) << 16));
5370         I915_WRITE(VSYNC(cpu_transcoder),
5371                    (adjusted_mode->crtc_vsync_start - 1) |
5372                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5373
5374         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5375          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5376          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5377          * bits. */
5378         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5379             (pipe == PIPE_B || pipe == PIPE_C))
5380                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5381
5382         /* pipesrc controls the size that is scaled from, which should
5383          * always be the user's requested size.
5384          */
5385         I915_WRITE(PIPESRC(pipe),
5386                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5387                    (intel_crtc->config.pipe_src_h - 1));
5388 }
5389
5390 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5391                                    struct intel_crtc_config *pipe_config)
5392 {
5393         struct drm_device *dev = crtc->base.dev;
5394         struct drm_i915_private *dev_priv = dev->dev_private;
5395         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5396         uint32_t tmp;
5397
5398         tmp = I915_READ(HTOTAL(cpu_transcoder));
5399         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5400         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5401         tmp = I915_READ(HBLANK(cpu_transcoder));
5402         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5403         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5404         tmp = I915_READ(HSYNC(cpu_transcoder));
5405         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5406         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5407
5408         tmp = I915_READ(VTOTAL(cpu_transcoder));
5409         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5410         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5411         tmp = I915_READ(VBLANK(cpu_transcoder));
5412         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5413         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5414         tmp = I915_READ(VSYNC(cpu_transcoder));
5415         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5416         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5417
5418         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5419                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5420                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5421                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5422         }
5423
5424         tmp = I915_READ(PIPESRC(crtc->pipe));
5425         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5426         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5427
5428         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5429         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5430 }
5431
5432 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5433                                  struct intel_crtc_config *pipe_config)
5434 {
5435         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5436         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5437         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5438         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5439
5440         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5441         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5442         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5443         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5444
5445         mode->flags = pipe_config->adjusted_mode.flags;
5446
5447         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5448         mode->flags |= pipe_config->adjusted_mode.flags;
5449 }
5450
5451 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5452 {
5453         struct drm_device *dev = intel_crtc->base.dev;
5454         struct drm_i915_private *dev_priv = dev->dev_private;
5455         uint32_t pipeconf;
5456
5457         pipeconf = 0;
5458
5459         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5460             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5461                 pipeconf |= PIPECONF_ENABLE;
5462
5463         if (intel_crtc->config.double_wide)
5464                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5465
5466         /* only g4x and later have fancy bpc/dither controls */
5467         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5468                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5469                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5470                         pipeconf |= PIPECONF_DITHER_EN |
5471                                     PIPECONF_DITHER_TYPE_SP;
5472
5473                 switch (intel_crtc->config.pipe_bpp) {
5474                 case 18:
5475                         pipeconf |= PIPECONF_6BPC;
5476                         break;
5477                 case 24:
5478                         pipeconf |= PIPECONF_8BPC;
5479                         break;
5480                 case 30:
5481                         pipeconf |= PIPECONF_10BPC;
5482                         break;
5483                 default:
5484                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5485                         BUG();
5486                 }
5487         }
5488
5489         if (HAS_PIPE_CXSR(dev)) {
5490                 if (intel_crtc->lowfreq_avail) {
5491                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5492                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5493                 } else {
5494                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5495                 }
5496         }
5497
5498         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5499                 if (INTEL_INFO(dev)->gen < 4 ||
5500                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5501                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5502                 else
5503                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5504         } else
5505                 pipeconf |= PIPECONF_PROGRESSIVE;
5506
5507         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5508                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5509
5510         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5511         POSTING_READ(PIPECONF(intel_crtc->pipe));
5512 }
5513
5514 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5515                               int x, int y,
5516                               struct drm_framebuffer *fb)
5517 {
5518         struct drm_device *dev = crtc->dev;
5519         struct drm_i915_private *dev_priv = dev->dev_private;
5520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5521         int pipe = intel_crtc->pipe;
5522         int plane = intel_crtc->plane;
5523         int refclk, num_connectors = 0;
5524         intel_clock_t clock, reduced_clock;
5525         u32 dspcntr;
5526         bool ok, has_reduced_clock = false;
5527         bool is_lvds = false, is_dsi = false;
5528         struct intel_encoder *encoder;
5529         const intel_limit_t *limit;
5530         int ret;
5531
5532         for_each_encoder_on_crtc(dev, crtc, encoder) {
5533                 switch (encoder->type) {
5534                 case INTEL_OUTPUT_LVDS:
5535                         is_lvds = true;
5536                         break;
5537                 case INTEL_OUTPUT_DSI:
5538                         is_dsi = true;
5539                         break;
5540                 }
5541
5542                 num_connectors++;
5543         }
5544
5545         if (is_dsi)
5546                 goto skip_dpll;
5547
5548         if (!intel_crtc->config.clock_set) {
5549                 refclk = i9xx_get_refclk(crtc, num_connectors);
5550
5551                 /*
5552                  * Returns a set of divisors for the desired target clock with
5553                  * the given refclk, or FALSE.  The returned values represent
5554                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5555                  * 2) / p1 / p2.
5556                  */
5557                 limit = intel_limit(crtc, refclk);
5558                 ok = dev_priv->display.find_dpll(limit, crtc,
5559                                                  intel_crtc->config.port_clock,
5560                                                  refclk, NULL, &clock);
5561                 if (!ok) {
5562                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5563                         return -EINVAL;
5564                 }
5565
5566                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5567                         /*
5568                          * Ensure we match the reduced clock's P to the target
5569                          * clock.  If the clocks don't match, we can't switch
5570                          * the display clock by using the FP0/FP1. In such case
5571                          * we will disable the LVDS downclock feature.
5572                          */
5573                         has_reduced_clock =
5574                                 dev_priv->display.find_dpll(limit, crtc,
5575                                                             dev_priv->lvds_downclock,
5576                                                             refclk, &clock,
5577                                                             &reduced_clock);
5578                 }
5579                 /* Compat-code for transition, will disappear. */
5580                 intel_crtc->config.dpll.n = clock.n;
5581                 intel_crtc->config.dpll.m1 = clock.m1;
5582                 intel_crtc->config.dpll.m2 = clock.m2;
5583                 intel_crtc->config.dpll.p1 = clock.p1;
5584                 intel_crtc->config.dpll.p2 = clock.p2;
5585         }
5586
5587         if (IS_GEN2(dev)) {
5588                 i8xx_update_pll(intel_crtc,
5589                                 has_reduced_clock ? &reduced_clock : NULL,
5590                                 num_connectors);
5591         } else if (IS_VALLEYVIEW(dev)) {
5592                 vlv_update_pll(intel_crtc);
5593         } else {
5594                 i9xx_update_pll(intel_crtc,
5595                                 has_reduced_clock ? &reduced_clock : NULL,
5596                                 num_connectors);
5597         }
5598
5599 skip_dpll:
5600         /* Set up the display plane register */
5601         dspcntr = DISPPLANE_GAMMA_ENABLE;
5602
5603         if (!IS_VALLEYVIEW(dev)) {
5604                 if (pipe == 0)
5605                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5606                 else
5607                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5608         }
5609
5610         if (intel_crtc->config.has_dp_encoder)
5611                 intel_dp_set_m_n(intel_crtc);
5612
5613         intel_set_pipe_timings(intel_crtc);
5614
5615         /* pipesrc and dspsize control the size that is scaled from,
5616          * which should always be the user's requested size.
5617          */
5618         I915_WRITE(DSPSIZE(plane),
5619                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5620                    (intel_crtc->config.pipe_src_w - 1));
5621         I915_WRITE(DSPPOS(plane), 0);
5622
5623         i9xx_set_pipeconf(intel_crtc);
5624
5625         I915_WRITE(DSPCNTR(plane), dspcntr);
5626         POSTING_READ(DSPCNTR(plane));
5627
5628         ret = intel_pipe_set_base(crtc, x, y, fb);
5629
5630         return ret;
5631 }
5632
5633 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5634                                  struct intel_crtc_config *pipe_config)
5635 {
5636         struct drm_device *dev = crtc->base.dev;
5637         struct drm_i915_private *dev_priv = dev->dev_private;
5638         uint32_t tmp;
5639
5640         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5641                 return;
5642
5643         tmp = I915_READ(PFIT_CONTROL);
5644         if (!(tmp & PFIT_ENABLE))
5645                 return;
5646
5647         /* Check whether the pfit is attached to our pipe. */
5648         if (INTEL_INFO(dev)->gen < 4) {
5649                 if (crtc->pipe != PIPE_B)
5650                         return;
5651         } else {
5652                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5653                         return;
5654         }
5655
5656         pipe_config->gmch_pfit.control = tmp;
5657         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5658         if (INTEL_INFO(dev)->gen < 5)
5659                 pipe_config->gmch_pfit.lvds_border_bits =
5660                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5661 }
5662
5663 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5664                                struct intel_crtc_config *pipe_config)
5665 {
5666         struct drm_device *dev = crtc->base.dev;
5667         struct drm_i915_private *dev_priv = dev->dev_private;
5668         int pipe = pipe_config->cpu_transcoder;
5669         intel_clock_t clock;
5670         u32 mdiv;
5671         int refclk = 100000;
5672
5673         mutex_lock(&dev_priv->dpio_lock);
5674         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5675         mutex_unlock(&dev_priv->dpio_lock);
5676
5677         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5678         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5679         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5680         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5681         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5682
5683         vlv_clock(refclk, &clock);
5684
5685         /* clock.dot is the fast clock */
5686         pipe_config->port_clock = clock.dot / 5;
5687 }
5688
5689 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5690                                   struct intel_plane_config *plane_config)
5691 {
5692         struct drm_device *dev = crtc->base.dev;
5693         struct drm_i915_private *dev_priv = dev->dev_private;
5694         u32 val, base, offset;
5695         int pipe = crtc->pipe, plane = crtc->plane;
5696         int fourcc, pixel_format;
5697         int aligned_height;
5698
5699         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5700         if (!crtc->base.primary->fb) {
5701                 DRM_DEBUG_KMS("failed to alloc fb\n");
5702                 return;
5703         }
5704
5705         val = I915_READ(DSPCNTR(plane));
5706
5707         if (INTEL_INFO(dev)->gen >= 4)
5708                 if (val & DISPPLANE_TILED)
5709                         plane_config->tiled = true;
5710
5711         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5712         fourcc = intel_format_to_fourcc(pixel_format);
5713         crtc->base.primary->fb->pixel_format = fourcc;
5714         crtc->base.primary->fb->bits_per_pixel =
5715                 drm_format_plane_cpp(fourcc, 0) * 8;
5716
5717         if (INTEL_INFO(dev)->gen >= 4) {
5718                 if (plane_config->tiled)
5719                         offset = I915_READ(DSPTILEOFF(plane));
5720                 else
5721                         offset = I915_READ(DSPLINOFF(plane));
5722                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5723         } else {
5724                 base = I915_READ(DSPADDR(plane));
5725         }
5726         plane_config->base = base;
5727
5728         val = I915_READ(PIPESRC(pipe));
5729         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5730         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5731
5732         val = I915_READ(DSPSTRIDE(pipe));
5733         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5734
5735         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5736                                             plane_config->tiled);
5737
5738         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5739                                    aligned_height, PAGE_SIZE);
5740
5741         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5742                       pipe, plane, crtc->base.primary->fb->width,
5743                       crtc->base.primary->fb->height,
5744                       crtc->base.primary->fb->bits_per_pixel, base,
5745                       crtc->base.primary->fb->pitches[0],
5746                       plane_config->size);
5747
5748 }
5749
5750 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5751                                  struct intel_crtc_config *pipe_config)
5752 {
5753         struct drm_device *dev = crtc->base.dev;
5754         struct drm_i915_private *dev_priv = dev->dev_private;
5755         uint32_t tmp;
5756
5757         if (!intel_display_power_enabled(dev_priv,
5758                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5759                 return false;
5760
5761         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5762         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5763
5764         tmp = I915_READ(PIPECONF(crtc->pipe));
5765         if (!(tmp & PIPECONF_ENABLE))
5766                 return false;
5767
5768         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5769                 switch (tmp & PIPECONF_BPC_MASK) {
5770                 case PIPECONF_6BPC:
5771                         pipe_config->pipe_bpp = 18;
5772                         break;
5773                 case PIPECONF_8BPC:
5774                         pipe_config->pipe_bpp = 24;
5775                         break;
5776                 case PIPECONF_10BPC:
5777                         pipe_config->pipe_bpp = 30;
5778                         break;
5779                 default:
5780                         break;
5781                 }
5782         }
5783
5784         if (INTEL_INFO(dev)->gen < 4)
5785                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5786
5787         intel_get_pipe_timings(crtc, pipe_config);
5788
5789         i9xx_get_pfit_config(crtc, pipe_config);
5790
5791         if (INTEL_INFO(dev)->gen >= 4) {
5792                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5793                 pipe_config->pixel_multiplier =
5794                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5795                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5796                 pipe_config->dpll_hw_state.dpll_md = tmp;
5797         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5798                 tmp = I915_READ(DPLL(crtc->pipe));
5799                 pipe_config->pixel_multiplier =
5800                         ((tmp & SDVO_MULTIPLIER_MASK)
5801                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5802         } else {
5803                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5804                  * port and will be fixed up in the encoder->get_config
5805                  * function. */
5806                 pipe_config->pixel_multiplier = 1;
5807         }
5808         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5809         if (!IS_VALLEYVIEW(dev)) {
5810                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5811                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5812         } else {
5813                 /* Mask out read-only status bits. */
5814                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5815                                                      DPLL_PORTC_READY_MASK |
5816                                                      DPLL_PORTB_READY_MASK);
5817         }
5818
5819         if (IS_VALLEYVIEW(dev))
5820                 vlv_crtc_clock_get(crtc, pipe_config);
5821         else
5822                 i9xx_crtc_clock_get(crtc, pipe_config);
5823
5824         return true;
5825 }
5826
5827 static void ironlake_init_pch_refclk(struct drm_device *dev)
5828 {
5829         struct drm_i915_private *dev_priv = dev->dev_private;
5830         struct drm_mode_config *mode_config = &dev->mode_config;
5831         struct intel_encoder *encoder;
5832         u32 val, final;
5833         bool has_lvds = false;
5834         bool has_cpu_edp = false;
5835         bool has_panel = false;
5836         bool has_ck505 = false;
5837         bool can_ssc = false;
5838
5839         /* We need to take the global config into account */
5840         list_for_each_entry(encoder, &mode_config->encoder_list,
5841                             base.head) {
5842                 switch (encoder->type) {
5843                 case INTEL_OUTPUT_LVDS:
5844                         has_panel = true;
5845                         has_lvds = true;
5846                         break;
5847                 case INTEL_OUTPUT_EDP:
5848                         has_panel = true;
5849                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5850                                 has_cpu_edp = true;
5851                         break;
5852                 }
5853         }
5854
5855         if (HAS_PCH_IBX(dev)) {
5856                 has_ck505 = dev_priv->vbt.display_clock_mode;
5857                 can_ssc = has_ck505;
5858         } else {
5859                 has_ck505 = false;
5860                 can_ssc = true;
5861         }
5862
5863         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5864                       has_panel, has_lvds, has_ck505);
5865
5866         /* Ironlake: try to setup display ref clock before DPLL
5867          * enabling. This is only under driver's control after
5868          * PCH B stepping, previous chipset stepping should be
5869          * ignoring this setting.
5870          */
5871         val = I915_READ(PCH_DREF_CONTROL);
5872
5873         /* As we must carefully and slowly disable/enable each source in turn,
5874          * compute the final state we want first and check if we need to
5875          * make any changes at all.
5876          */
5877         final = val;
5878         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5879         if (has_ck505)
5880                 final |= DREF_NONSPREAD_CK505_ENABLE;
5881         else
5882                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5883
5884         final &= ~DREF_SSC_SOURCE_MASK;
5885         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5886         final &= ~DREF_SSC1_ENABLE;
5887
5888         if (has_panel) {
5889                 final |= DREF_SSC_SOURCE_ENABLE;
5890
5891                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5892                         final |= DREF_SSC1_ENABLE;
5893
5894                 if (has_cpu_edp) {
5895                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5896                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5897                         else
5898                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5899                 } else
5900                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5901         } else {
5902                 final |= DREF_SSC_SOURCE_DISABLE;
5903                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5904         }
5905
5906         if (final == val)
5907                 return;
5908
5909         /* Always enable nonspread source */
5910         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5911
5912         if (has_ck505)
5913                 val |= DREF_NONSPREAD_CK505_ENABLE;
5914         else
5915                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5916
5917         if (has_panel) {
5918                 val &= ~DREF_SSC_SOURCE_MASK;
5919                 val |= DREF_SSC_SOURCE_ENABLE;
5920
5921                 /* SSC must be turned on before enabling the CPU output  */
5922                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5923                         DRM_DEBUG_KMS("Using SSC on panel\n");
5924                         val |= DREF_SSC1_ENABLE;
5925                 } else
5926                         val &= ~DREF_SSC1_ENABLE;
5927
5928                 /* Get SSC going before enabling the outputs */
5929                 I915_WRITE(PCH_DREF_CONTROL, val);
5930                 POSTING_READ(PCH_DREF_CONTROL);
5931                 udelay(200);
5932
5933                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5934
5935                 /* Enable CPU source on CPU attached eDP */
5936                 if (has_cpu_edp) {
5937                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5938                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5939                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5940                         }
5941                         else
5942                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5943                 } else
5944                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5945
5946                 I915_WRITE(PCH_DREF_CONTROL, val);
5947                 POSTING_READ(PCH_DREF_CONTROL);
5948                 udelay(200);
5949         } else {
5950                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5951
5952                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5953
5954                 /* Turn off CPU output */
5955                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5956
5957                 I915_WRITE(PCH_DREF_CONTROL, val);
5958                 POSTING_READ(PCH_DREF_CONTROL);
5959                 udelay(200);
5960
5961                 /* Turn off the SSC source */
5962                 val &= ~DREF_SSC_SOURCE_MASK;
5963                 val |= DREF_SSC_SOURCE_DISABLE;
5964
5965                 /* Turn off SSC1 */
5966                 val &= ~DREF_SSC1_ENABLE;
5967
5968                 I915_WRITE(PCH_DREF_CONTROL, val);
5969                 POSTING_READ(PCH_DREF_CONTROL);
5970                 udelay(200);
5971         }
5972
5973         BUG_ON(val != final);
5974 }
5975
5976 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5977 {
5978         uint32_t tmp;
5979
5980         tmp = I915_READ(SOUTH_CHICKEN2);
5981         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5982         I915_WRITE(SOUTH_CHICKEN2, tmp);
5983
5984         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5985                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5986                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5987
5988         tmp = I915_READ(SOUTH_CHICKEN2);
5989         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5990         I915_WRITE(SOUTH_CHICKEN2, tmp);
5991
5992         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5993                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5994                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5995 }
5996
5997 /* WaMPhyProgramming:hsw */
5998 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5999 {
6000         uint32_t tmp;
6001
6002         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6003         tmp &= ~(0xFF << 24);
6004         tmp |= (0x12 << 24);
6005         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6006
6007         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6008         tmp |= (1 << 11);
6009         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6010
6011         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6012         tmp |= (1 << 11);
6013         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6014
6015         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6016         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6017         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6018
6019         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6020         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6021         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6022
6023         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6024         tmp &= ~(7 << 13);
6025         tmp |= (5 << 13);
6026         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6027
6028         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6029         tmp &= ~(7 << 13);
6030         tmp |= (5 << 13);
6031         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6032
6033         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6034         tmp &= ~0xFF;
6035         tmp |= 0x1C;
6036         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6037
6038         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6039         tmp &= ~0xFF;
6040         tmp |= 0x1C;
6041         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6042
6043         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6044         tmp &= ~(0xFF << 16);
6045         tmp |= (0x1C << 16);
6046         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6047
6048         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6049         tmp &= ~(0xFF << 16);
6050         tmp |= (0x1C << 16);
6051         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6052
6053         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6054         tmp |= (1 << 27);
6055         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6056
6057         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6058         tmp |= (1 << 27);
6059         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6060
6061         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6062         tmp &= ~(0xF << 28);
6063         tmp |= (4 << 28);
6064         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6065
6066         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6067         tmp &= ~(0xF << 28);
6068         tmp |= (4 << 28);
6069         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6070 }
6071
6072 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6073  * Programming" based on the parameters passed:
6074  * - Sequence to enable CLKOUT_DP
6075  * - Sequence to enable CLKOUT_DP without spread
6076  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6077  */
6078 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6079                                  bool with_fdi)
6080 {
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082         uint32_t reg, tmp;
6083
6084         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6085                 with_spread = true;
6086         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6087                  with_fdi, "LP PCH doesn't have FDI\n"))
6088                 with_fdi = false;
6089
6090         mutex_lock(&dev_priv->dpio_lock);
6091
6092         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6093         tmp &= ~SBI_SSCCTL_DISABLE;
6094         tmp |= SBI_SSCCTL_PATHALT;
6095         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6096
6097         udelay(24);
6098
6099         if (with_spread) {
6100                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6101                 tmp &= ~SBI_SSCCTL_PATHALT;
6102                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6103
6104                 if (with_fdi) {
6105                         lpt_reset_fdi_mphy(dev_priv);
6106                         lpt_program_fdi_mphy(dev_priv);
6107                 }
6108         }
6109
6110         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6111                SBI_GEN0 : SBI_DBUFF0;
6112         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6113         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6114         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6115
6116         mutex_unlock(&dev_priv->dpio_lock);
6117 }
6118
6119 /* Sequence to disable CLKOUT_DP */
6120 static void lpt_disable_clkout_dp(struct drm_device *dev)
6121 {
6122         struct drm_i915_private *dev_priv = dev->dev_private;
6123         uint32_t reg, tmp;
6124
6125         mutex_lock(&dev_priv->dpio_lock);
6126
6127         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6128                SBI_GEN0 : SBI_DBUFF0;
6129         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6130         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6131         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6132
6133         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6134         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6135                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6136                         tmp |= SBI_SSCCTL_PATHALT;
6137                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6138                         udelay(32);
6139                 }
6140                 tmp |= SBI_SSCCTL_DISABLE;
6141                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6142         }
6143
6144         mutex_unlock(&dev_priv->dpio_lock);
6145 }
6146
6147 static void lpt_init_pch_refclk(struct drm_device *dev)
6148 {
6149         struct drm_mode_config *mode_config = &dev->mode_config;
6150         struct intel_encoder *encoder;
6151         bool has_vga = false;
6152
6153         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6154                 switch (encoder->type) {
6155                 case INTEL_OUTPUT_ANALOG:
6156                         has_vga = true;
6157                         break;
6158                 }
6159         }
6160
6161         if (has_vga)
6162                 lpt_enable_clkout_dp(dev, true, true);
6163         else
6164                 lpt_disable_clkout_dp(dev);
6165 }
6166
6167 /*
6168  * Initialize reference clocks when the driver loads
6169  */
6170 void intel_init_pch_refclk(struct drm_device *dev)
6171 {
6172         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6173                 ironlake_init_pch_refclk(dev);
6174         else if (HAS_PCH_LPT(dev))
6175                 lpt_init_pch_refclk(dev);
6176 }
6177
6178 static int ironlake_get_refclk(struct drm_crtc *crtc)
6179 {
6180         struct drm_device *dev = crtc->dev;
6181         struct drm_i915_private *dev_priv = dev->dev_private;
6182         struct intel_encoder *encoder;
6183         int num_connectors = 0;
6184         bool is_lvds = false;
6185
6186         for_each_encoder_on_crtc(dev, crtc, encoder) {
6187                 switch (encoder->type) {
6188                 case INTEL_OUTPUT_LVDS:
6189                         is_lvds = true;
6190                         break;
6191                 }
6192                 num_connectors++;
6193         }
6194
6195         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6196                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6197                               dev_priv->vbt.lvds_ssc_freq);
6198                 return dev_priv->vbt.lvds_ssc_freq;
6199         }
6200
6201         return 120000;
6202 }
6203
6204 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6205 {
6206         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208         int pipe = intel_crtc->pipe;
6209         uint32_t val;
6210
6211         val = 0;
6212
6213         switch (intel_crtc->config.pipe_bpp) {
6214         case 18:
6215                 val |= PIPECONF_6BPC;
6216                 break;
6217         case 24:
6218                 val |= PIPECONF_8BPC;
6219                 break;
6220         case 30:
6221                 val |= PIPECONF_10BPC;
6222                 break;
6223         case 36:
6224                 val |= PIPECONF_12BPC;
6225                 break;
6226         default:
6227                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6228                 BUG();
6229         }
6230
6231         if (intel_crtc->config.dither)
6232                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6233
6234         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6235                 val |= PIPECONF_INTERLACED_ILK;
6236         else
6237                 val |= PIPECONF_PROGRESSIVE;
6238
6239         if (intel_crtc->config.limited_color_range)
6240                 val |= PIPECONF_COLOR_RANGE_SELECT;
6241
6242         I915_WRITE(PIPECONF(pipe), val);
6243         POSTING_READ(PIPECONF(pipe));
6244 }
6245
6246 /*
6247  * Set up the pipe CSC unit.
6248  *
6249  * Currently only full range RGB to limited range RGB conversion
6250  * is supported, but eventually this should handle various
6251  * RGB<->YCbCr scenarios as well.
6252  */
6253 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6254 {
6255         struct drm_device *dev = crtc->dev;
6256         struct drm_i915_private *dev_priv = dev->dev_private;
6257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6258         int pipe = intel_crtc->pipe;
6259         uint16_t coeff = 0x7800; /* 1.0 */
6260
6261         /*
6262          * TODO: Check what kind of values actually come out of the pipe
6263          * with these coeff/postoff values and adjust to get the best
6264          * accuracy. Perhaps we even need to take the bpc value into
6265          * consideration.
6266          */
6267
6268         if (intel_crtc->config.limited_color_range)
6269                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6270
6271         /*
6272          * GY/GU and RY/RU should be the other way around according
6273          * to BSpec, but reality doesn't agree. Just set them up in
6274          * a way that results in the correct picture.
6275          */
6276         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6277         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6278
6279         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6280         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6281
6282         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6283         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6284
6285         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6286         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6287         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6288
6289         if (INTEL_INFO(dev)->gen > 6) {
6290                 uint16_t postoff = 0;
6291
6292                 if (intel_crtc->config.limited_color_range)
6293                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6294
6295                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6296                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6297                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6298
6299                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6300         } else {
6301                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6302
6303                 if (intel_crtc->config.limited_color_range)
6304                         mode |= CSC_BLACK_SCREEN_OFFSET;
6305
6306                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6307         }
6308 }
6309
6310 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6311 {
6312         struct drm_device *dev = crtc->dev;
6313         struct drm_i915_private *dev_priv = dev->dev_private;
6314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315         enum pipe pipe = intel_crtc->pipe;
6316         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6317         uint32_t val;
6318
6319         val = 0;
6320
6321         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6322                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6323
6324         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6325                 val |= PIPECONF_INTERLACED_ILK;
6326         else
6327                 val |= PIPECONF_PROGRESSIVE;
6328
6329         I915_WRITE(PIPECONF(cpu_transcoder), val);
6330         POSTING_READ(PIPECONF(cpu_transcoder));
6331
6332         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6333         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6334
6335         if (IS_BROADWELL(dev)) {
6336                 val = 0;
6337
6338                 switch (intel_crtc->config.pipe_bpp) {
6339                 case 18:
6340                         val |= PIPEMISC_DITHER_6_BPC;
6341                         break;
6342                 case 24:
6343                         val |= PIPEMISC_DITHER_8_BPC;
6344                         break;
6345                 case 30:
6346                         val |= PIPEMISC_DITHER_10_BPC;
6347                         break;
6348                 case 36:
6349                         val |= PIPEMISC_DITHER_12_BPC;
6350                         break;
6351                 default:
6352                         /* Case prevented by pipe_config_set_bpp. */
6353                         BUG();
6354                 }
6355
6356                 if (intel_crtc->config.dither)
6357                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6358
6359                 I915_WRITE(PIPEMISC(pipe), val);
6360         }
6361 }
6362
6363 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6364                                     intel_clock_t *clock,
6365                                     bool *has_reduced_clock,
6366                                     intel_clock_t *reduced_clock)
6367 {
6368         struct drm_device *dev = crtc->dev;
6369         struct drm_i915_private *dev_priv = dev->dev_private;
6370         struct intel_encoder *intel_encoder;
6371         int refclk;
6372         const intel_limit_t *limit;
6373         bool ret, is_lvds = false;
6374
6375         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6376                 switch (intel_encoder->type) {
6377                 case INTEL_OUTPUT_LVDS:
6378                         is_lvds = true;
6379                         break;
6380                 }
6381         }
6382
6383         refclk = ironlake_get_refclk(crtc);
6384
6385         /*
6386          * Returns a set of divisors for the desired target clock with the given
6387          * refclk, or FALSE.  The returned values represent the clock equation:
6388          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6389          */
6390         limit = intel_limit(crtc, refclk);
6391         ret = dev_priv->display.find_dpll(limit, crtc,
6392                                           to_intel_crtc(crtc)->config.port_clock,
6393                                           refclk, NULL, clock);
6394         if (!ret)
6395                 return false;
6396
6397         if (is_lvds && dev_priv->lvds_downclock_avail) {
6398                 /*
6399                  * Ensure we match the reduced clock's P to the target clock.
6400                  * If the clocks don't match, we can't switch the display clock
6401                  * by using the FP0/FP1. In such case we will disable the LVDS
6402                  * downclock feature.
6403                 */
6404                 *has_reduced_clock =
6405                         dev_priv->display.find_dpll(limit, crtc,
6406                                                     dev_priv->lvds_downclock,
6407                                                     refclk, clock,
6408                                                     reduced_clock);
6409         }
6410
6411         return true;
6412 }
6413
6414 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6415 {
6416         /*
6417          * Account for spread spectrum to avoid
6418          * oversubscribing the link. Max center spread
6419          * is 2.5%; use 5% for safety's sake.
6420          */
6421         u32 bps = target_clock * bpp * 21 / 20;
6422         return DIV_ROUND_UP(bps, link_bw * 8);
6423 }
6424
6425 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6426 {
6427         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6428 }
6429
6430 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6431                                       u32 *fp,
6432                                       intel_clock_t *reduced_clock, u32 *fp2)
6433 {
6434         struct drm_crtc *crtc = &intel_crtc->base;
6435         struct drm_device *dev = crtc->dev;
6436         struct drm_i915_private *dev_priv = dev->dev_private;
6437         struct intel_encoder *intel_encoder;
6438         uint32_t dpll;
6439         int factor, num_connectors = 0;
6440         bool is_lvds = false, is_sdvo = false;
6441
6442         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6443                 switch (intel_encoder->type) {
6444                 case INTEL_OUTPUT_LVDS:
6445                         is_lvds = true;
6446                         break;
6447                 case INTEL_OUTPUT_SDVO:
6448                 case INTEL_OUTPUT_HDMI:
6449                         is_sdvo = true;
6450                         break;
6451                 }
6452
6453                 num_connectors++;
6454         }
6455
6456         /* Enable autotuning of the PLL clock (if permissible) */
6457         factor = 21;
6458         if (is_lvds) {
6459                 if ((intel_panel_use_ssc(dev_priv) &&
6460                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6461                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6462                         factor = 25;
6463         } else if (intel_crtc->config.sdvo_tv_clock)
6464                 factor = 20;
6465
6466         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6467                 *fp |= FP_CB_TUNE;
6468
6469         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6470                 *fp2 |= FP_CB_TUNE;
6471
6472         dpll = 0;
6473
6474         if (is_lvds)
6475                 dpll |= DPLLB_MODE_LVDS;
6476         else
6477                 dpll |= DPLLB_MODE_DAC_SERIAL;
6478
6479         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6480                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6481
6482         if (is_sdvo)
6483                 dpll |= DPLL_SDVO_HIGH_SPEED;
6484         if (intel_crtc->config.has_dp_encoder)
6485                 dpll |= DPLL_SDVO_HIGH_SPEED;
6486
6487         /* compute bitmask from p1 value */
6488         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6489         /* also FPA1 */
6490         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6491
6492         switch (intel_crtc->config.dpll.p2) {
6493         case 5:
6494                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6495                 break;
6496         case 7:
6497                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6498                 break;
6499         case 10:
6500                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6501                 break;
6502         case 14:
6503                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6504                 break;
6505         }
6506
6507         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6508                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6509         else
6510                 dpll |= PLL_REF_INPUT_DREFCLK;
6511
6512         return dpll | DPLL_VCO_ENABLE;
6513 }
6514
6515 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6516                                   int x, int y,
6517                                   struct drm_framebuffer *fb)
6518 {
6519         struct drm_device *dev = crtc->dev;
6520         struct drm_i915_private *dev_priv = dev->dev_private;
6521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6522         int pipe = intel_crtc->pipe;
6523         int plane = intel_crtc->plane;
6524         int num_connectors = 0;
6525         intel_clock_t clock, reduced_clock;
6526         u32 dpll = 0, fp = 0, fp2 = 0;
6527         bool ok, has_reduced_clock = false;
6528         bool is_lvds = false;
6529         struct intel_encoder *encoder;
6530         struct intel_shared_dpll *pll;
6531         int ret;
6532
6533         for_each_encoder_on_crtc(dev, crtc, encoder) {
6534                 switch (encoder->type) {
6535                 case INTEL_OUTPUT_LVDS:
6536                         is_lvds = true;
6537                         break;
6538                 }
6539
6540                 num_connectors++;
6541         }
6542
6543         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6544              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6545
6546         ok = ironlake_compute_clocks(crtc, &clock,
6547                                      &has_reduced_clock, &reduced_clock);
6548         if (!ok && !intel_crtc->config.clock_set) {
6549                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6550                 return -EINVAL;
6551         }
6552         /* Compat-code for transition, will disappear. */
6553         if (!intel_crtc->config.clock_set) {
6554                 intel_crtc->config.dpll.n = clock.n;
6555                 intel_crtc->config.dpll.m1 = clock.m1;
6556                 intel_crtc->config.dpll.m2 = clock.m2;
6557                 intel_crtc->config.dpll.p1 = clock.p1;
6558                 intel_crtc->config.dpll.p2 = clock.p2;
6559         }
6560
6561         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6562         if (intel_crtc->config.has_pch_encoder) {
6563                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6564                 if (has_reduced_clock)
6565                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6566
6567                 dpll = ironlake_compute_dpll(intel_crtc,
6568                                              &fp, &reduced_clock,
6569                                              has_reduced_clock ? &fp2 : NULL);
6570
6571                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6572                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6573                 if (has_reduced_clock)
6574                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6575                 else
6576                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6577
6578                 pll = intel_get_shared_dpll(intel_crtc);
6579                 if (pll == NULL) {
6580                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6581                                          pipe_name(pipe));
6582                         return -EINVAL;
6583                 }
6584         } else
6585                 intel_put_shared_dpll(intel_crtc);
6586
6587         if (intel_crtc->config.has_dp_encoder)
6588                 intel_dp_set_m_n(intel_crtc);
6589
6590         if (is_lvds && has_reduced_clock && i915.powersave)
6591                 intel_crtc->lowfreq_avail = true;
6592         else
6593                 intel_crtc->lowfreq_avail = false;
6594
6595         intel_set_pipe_timings(intel_crtc);
6596
6597         if (intel_crtc->config.has_pch_encoder) {
6598                 intel_cpu_transcoder_set_m_n(intel_crtc,
6599                                              &intel_crtc->config.fdi_m_n);
6600         }
6601
6602         ironlake_set_pipeconf(crtc);
6603
6604         /* Set up the display plane register */
6605         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6606         POSTING_READ(DSPCNTR(plane));
6607
6608         ret = intel_pipe_set_base(crtc, x, y, fb);
6609
6610         return ret;
6611 }
6612
6613 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6614                                          struct intel_link_m_n *m_n)
6615 {
6616         struct drm_device *dev = crtc->base.dev;
6617         struct drm_i915_private *dev_priv = dev->dev_private;
6618         enum pipe pipe = crtc->pipe;
6619
6620         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6621         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6622         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6623                 & ~TU_SIZE_MASK;
6624         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6625         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6626                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6627 }
6628
6629 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6630                                          enum transcoder transcoder,
6631                                          struct intel_link_m_n *m_n)
6632 {
6633         struct drm_device *dev = crtc->base.dev;
6634         struct drm_i915_private *dev_priv = dev->dev_private;
6635         enum pipe pipe = crtc->pipe;
6636
6637         if (INTEL_INFO(dev)->gen >= 5) {
6638                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6639                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6640                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6641                         & ~TU_SIZE_MASK;
6642                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6643                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6644                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6645         } else {
6646                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6647                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6648                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6649                         & ~TU_SIZE_MASK;
6650                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6651                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6652                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6653         }
6654 }
6655
6656 void intel_dp_get_m_n(struct intel_crtc *crtc,
6657                       struct intel_crtc_config *pipe_config)
6658 {
6659         if (crtc->config.has_pch_encoder)
6660                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6661         else
6662                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6663                                              &pipe_config->dp_m_n);
6664 }
6665
6666 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6667                                         struct intel_crtc_config *pipe_config)
6668 {
6669         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6670                                      &pipe_config->fdi_m_n);
6671 }
6672
6673 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6674                                      struct intel_crtc_config *pipe_config)
6675 {
6676         struct drm_device *dev = crtc->base.dev;
6677         struct drm_i915_private *dev_priv = dev->dev_private;
6678         uint32_t tmp;
6679
6680         tmp = I915_READ(PF_CTL(crtc->pipe));
6681
6682         if (tmp & PF_ENABLE) {
6683                 pipe_config->pch_pfit.enabled = true;
6684                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6685                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6686
6687                 /* We currently do not free assignements of panel fitters on
6688                  * ivb/hsw (since we don't use the higher upscaling modes which
6689                  * differentiates them) so just WARN about this case for now. */
6690                 if (IS_GEN7(dev)) {
6691                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6692                                 PF_PIPE_SEL_IVB(crtc->pipe));
6693                 }
6694         }
6695 }
6696
6697 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6698                                       struct intel_plane_config *plane_config)
6699 {
6700         struct drm_device *dev = crtc->base.dev;
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         u32 val, base, offset;
6703         int pipe = crtc->pipe, plane = crtc->plane;
6704         int fourcc, pixel_format;
6705         int aligned_height;
6706
6707         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6708         if (!crtc->base.primary->fb) {
6709                 DRM_DEBUG_KMS("failed to alloc fb\n");
6710                 return;
6711         }
6712
6713         val = I915_READ(DSPCNTR(plane));
6714
6715         if (INTEL_INFO(dev)->gen >= 4)
6716                 if (val & DISPPLANE_TILED)
6717                         plane_config->tiled = true;
6718
6719         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6720         fourcc = intel_format_to_fourcc(pixel_format);
6721         crtc->base.primary->fb->pixel_format = fourcc;
6722         crtc->base.primary->fb->bits_per_pixel =
6723                 drm_format_plane_cpp(fourcc, 0) * 8;
6724
6725         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6726         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6727                 offset = I915_READ(DSPOFFSET(plane));
6728         } else {
6729                 if (plane_config->tiled)
6730                         offset = I915_READ(DSPTILEOFF(plane));
6731                 else
6732                         offset = I915_READ(DSPLINOFF(plane));
6733         }
6734         plane_config->base = base;
6735
6736         val = I915_READ(PIPESRC(pipe));
6737         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6738         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6739
6740         val = I915_READ(DSPSTRIDE(pipe));
6741         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6742
6743         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6744                                             plane_config->tiled);
6745
6746         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6747                                    aligned_height, PAGE_SIZE);
6748
6749         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6750                       pipe, plane, crtc->base.primary->fb->width,
6751                       crtc->base.primary->fb->height,
6752                       crtc->base.primary->fb->bits_per_pixel, base,
6753                       crtc->base.primary->fb->pitches[0],
6754                       plane_config->size);
6755 }
6756
6757 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6758                                      struct intel_crtc_config *pipe_config)
6759 {
6760         struct drm_device *dev = crtc->base.dev;
6761         struct drm_i915_private *dev_priv = dev->dev_private;
6762         uint32_t tmp;
6763
6764         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6765         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6766
6767         tmp = I915_READ(PIPECONF(crtc->pipe));
6768         if (!(tmp & PIPECONF_ENABLE))
6769                 return false;
6770
6771         switch (tmp & PIPECONF_BPC_MASK) {
6772         case PIPECONF_6BPC:
6773                 pipe_config->pipe_bpp = 18;
6774                 break;
6775         case PIPECONF_8BPC:
6776                 pipe_config->pipe_bpp = 24;
6777                 break;
6778         case PIPECONF_10BPC:
6779                 pipe_config->pipe_bpp = 30;
6780                 break;
6781         case PIPECONF_12BPC:
6782                 pipe_config->pipe_bpp = 36;
6783                 break;
6784         default:
6785                 break;
6786         }
6787
6788         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6789                 struct intel_shared_dpll *pll;
6790
6791                 pipe_config->has_pch_encoder = true;
6792
6793                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6794                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6795                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6796
6797                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6798
6799                 if (HAS_PCH_IBX(dev_priv->dev)) {
6800                         pipe_config->shared_dpll =
6801                                 (enum intel_dpll_id) crtc->pipe;
6802                 } else {
6803                         tmp = I915_READ(PCH_DPLL_SEL);
6804                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6805                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6806                         else
6807                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6808                 }
6809
6810                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6811
6812                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6813                                            &pipe_config->dpll_hw_state));
6814
6815                 tmp = pipe_config->dpll_hw_state.dpll;
6816                 pipe_config->pixel_multiplier =
6817                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6818                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6819
6820                 ironlake_pch_clock_get(crtc, pipe_config);
6821         } else {
6822                 pipe_config->pixel_multiplier = 1;
6823         }
6824
6825         intel_get_pipe_timings(crtc, pipe_config);
6826
6827         ironlake_get_pfit_config(crtc, pipe_config);
6828
6829         return true;
6830 }
6831
6832 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6833 {
6834         struct drm_device *dev = dev_priv->dev;
6835         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6836         struct intel_crtc *crtc;
6837
6838         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6839                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6840                      pipe_name(crtc->pipe));
6841
6842         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6843         WARN(plls->spll_refcount, "SPLL enabled\n");
6844         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6845         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6846         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6847         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6848              "CPU PWM1 enabled\n");
6849         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6850              "CPU PWM2 enabled\n");
6851         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6852              "PCH PWM1 enabled\n");
6853         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6854              "Utility pin enabled\n");
6855         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6856
6857         /*
6858          * In theory we can still leave IRQs enabled, as long as only the HPD
6859          * interrupts remain enabled. We used to check for that, but since it's
6860          * gen-specific and since we only disable LCPLL after we fully disable
6861          * the interrupts, the check below should be enough.
6862          */
6863         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6864 }
6865
6866 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6867 {
6868         struct drm_device *dev = dev_priv->dev;
6869
6870         if (IS_HASWELL(dev)) {
6871                 mutex_lock(&dev_priv->rps.hw_lock);
6872                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6873                                             val))
6874                         DRM_ERROR("Failed to disable D_COMP\n");
6875                 mutex_unlock(&dev_priv->rps.hw_lock);
6876         } else {
6877                 I915_WRITE(D_COMP, val);
6878         }
6879         POSTING_READ(D_COMP);
6880 }
6881
6882 /*
6883  * This function implements pieces of two sequences from BSpec:
6884  * - Sequence for display software to disable LCPLL
6885  * - Sequence for display software to allow package C8+
6886  * The steps implemented here are just the steps that actually touch the LCPLL
6887  * register. Callers should take care of disabling all the display engine
6888  * functions, doing the mode unset, fixing interrupts, etc.
6889  */
6890 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6891                               bool switch_to_fclk, bool allow_power_down)
6892 {
6893         uint32_t val;
6894
6895         assert_can_disable_lcpll(dev_priv);
6896
6897         val = I915_READ(LCPLL_CTL);
6898
6899         if (switch_to_fclk) {
6900                 val |= LCPLL_CD_SOURCE_FCLK;
6901                 I915_WRITE(LCPLL_CTL, val);
6902
6903                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6904                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6905                         DRM_ERROR("Switching to FCLK failed\n");
6906
6907                 val = I915_READ(LCPLL_CTL);
6908         }
6909
6910         val |= LCPLL_PLL_DISABLE;
6911         I915_WRITE(LCPLL_CTL, val);
6912         POSTING_READ(LCPLL_CTL);
6913
6914         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6915                 DRM_ERROR("LCPLL still locked\n");
6916
6917         val = I915_READ(D_COMP);
6918         val |= D_COMP_COMP_DISABLE;
6919         hsw_write_dcomp(dev_priv, val);
6920         ndelay(100);
6921
6922         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6923                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6924
6925         if (allow_power_down) {
6926                 val = I915_READ(LCPLL_CTL);
6927                 val |= LCPLL_POWER_DOWN_ALLOW;
6928                 I915_WRITE(LCPLL_CTL, val);
6929                 POSTING_READ(LCPLL_CTL);
6930         }
6931 }
6932
6933 /*
6934  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6935  * source.
6936  */
6937 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6938 {
6939         uint32_t val;
6940         unsigned long irqflags;
6941
6942         val = I915_READ(LCPLL_CTL);
6943
6944         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6945                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6946                 return;
6947
6948         /*
6949          * Make sure we're not on PC8 state before disabling PC8, otherwise
6950          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6951          *
6952          * The other problem is that hsw_restore_lcpll() is called as part of
6953          * the runtime PM resume sequence, so we can't just call
6954          * gen6_gt_force_wake_get() because that function calls
6955          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6956          * while we are on the resume sequence. So to solve this problem we have
6957          * to call special forcewake code that doesn't touch runtime PM and
6958          * doesn't enable the forcewake delayed work.
6959          */
6960         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6961         if (dev_priv->uncore.forcewake_count++ == 0)
6962                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6963         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6964
6965         if (val & LCPLL_POWER_DOWN_ALLOW) {
6966                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6967                 I915_WRITE(LCPLL_CTL, val);
6968                 POSTING_READ(LCPLL_CTL);
6969         }
6970
6971         val = I915_READ(D_COMP);
6972         val |= D_COMP_COMP_FORCE;
6973         val &= ~D_COMP_COMP_DISABLE;
6974         hsw_write_dcomp(dev_priv, val);
6975
6976         val = I915_READ(LCPLL_CTL);
6977         val &= ~LCPLL_PLL_DISABLE;
6978         I915_WRITE(LCPLL_CTL, val);
6979
6980         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6981                 DRM_ERROR("LCPLL not locked yet\n");
6982
6983         if (val & LCPLL_CD_SOURCE_FCLK) {
6984                 val = I915_READ(LCPLL_CTL);
6985                 val &= ~LCPLL_CD_SOURCE_FCLK;
6986                 I915_WRITE(LCPLL_CTL, val);
6987
6988                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6989                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6990                         DRM_ERROR("Switching back to LCPLL failed\n");
6991         }
6992
6993         /* See the big comment above. */
6994         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6995         if (--dev_priv->uncore.forcewake_count == 0)
6996                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6997         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6998 }
6999
7000 /*
7001  * Package states C8 and deeper are really deep PC states that can only be
7002  * reached when all the devices on the system allow it, so even if the graphics
7003  * device allows PC8+, it doesn't mean the system will actually get to these
7004  * states. Our driver only allows PC8+ when going into runtime PM.
7005  *
7006  * The requirements for PC8+ are that all the outputs are disabled, the power
7007  * well is disabled and most interrupts are disabled, and these are also
7008  * requirements for runtime PM. When these conditions are met, we manually do
7009  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7010  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7011  * hang the machine.
7012  *
7013  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7014  * the state of some registers, so when we come back from PC8+ we need to
7015  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7016  * need to take care of the registers kept by RC6. Notice that this happens even
7017  * if we don't put the device in PCI D3 state (which is what currently happens
7018  * because of the runtime PM support).
7019  *
7020  * For more, read "Display Sequences for Package C8" on the hardware
7021  * documentation.
7022  */
7023 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7024 {
7025         struct drm_device *dev = dev_priv->dev;
7026         uint32_t val;
7027
7028         DRM_DEBUG_KMS("Enabling package C8+\n");
7029
7030         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7031                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7032                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7033                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7034         }
7035
7036         lpt_disable_clkout_dp(dev);
7037         hsw_disable_lcpll(dev_priv, true, true);
7038 }
7039
7040 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7041 {
7042         struct drm_device *dev = dev_priv->dev;
7043         uint32_t val;
7044
7045         DRM_DEBUG_KMS("Disabling package C8+\n");
7046
7047         hsw_restore_lcpll(dev_priv);
7048         lpt_init_pch_refclk(dev);
7049
7050         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7051                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7052                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7053                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7054         }
7055
7056         intel_prepare_ddi(dev);
7057 }
7058
7059 static void snb_modeset_global_resources(struct drm_device *dev)
7060 {
7061         modeset_update_crtc_power_domains(dev);
7062 }
7063
7064 static void haswell_modeset_global_resources(struct drm_device *dev)
7065 {
7066         modeset_update_crtc_power_domains(dev);
7067 }
7068
7069 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7070                                  int x, int y,
7071                                  struct drm_framebuffer *fb)
7072 {
7073         struct drm_device *dev = crtc->dev;
7074         struct drm_i915_private *dev_priv = dev->dev_private;
7075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076         int plane = intel_crtc->plane;
7077         int ret;
7078
7079         if (!intel_ddi_pll_select(intel_crtc))
7080                 return -EINVAL;
7081         intel_ddi_pll_enable(intel_crtc);
7082
7083         if (intel_crtc->config.has_dp_encoder)
7084                 intel_dp_set_m_n(intel_crtc);
7085
7086         intel_crtc->lowfreq_avail = false;
7087
7088         intel_set_pipe_timings(intel_crtc);
7089
7090         if (intel_crtc->config.has_pch_encoder) {
7091                 intel_cpu_transcoder_set_m_n(intel_crtc,
7092                                              &intel_crtc->config.fdi_m_n);
7093         }
7094
7095         haswell_set_pipeconf(crtc);
7096
7097         intel_set_pipe_csc(crtc);
7098
7099         /* Set up the display plane register */
7100         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7101         POSTING_READ(DSPCNTR(plane));
7102
7103         ret = intel_pipe_set_base(crtc, x, y, fb);
7104
7105         return ret;
7106 }
7107
7108 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7109                                     struct intel_crtc_config *pipe_config)
7110 {
7111         struct drm_device *dev = crtc->base.dev;
7112         struct drm_i915_private *dev_priv = dev->dev_private;
7113         enum intel_display_power_domain pfit_domain;
7114         uint32_t tmp;
7115
7116         if (!intel_display_power_enabled(dev_priv,
7117                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7118                 return false;
7119
7120         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7121         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7122
7123         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7124         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7125                 enum pipe trans_edp_pipe;
7126                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7127                 default:
7128                         WARN(1, "unknown pipe linked to edp transcoder\n");
7129                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7130                 case TRANS_DDI_EDP_INPUT_A_ON:
7131                         trans_edp_pipe = PIPE_A;
7132                         break;
7133                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7134                         trans_edp_pipe = PIPE_B;
7135                         break;
7136                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7137                         trans_edp_pipe = PIPE_C;
7138                         break;
7139                 }
7140
7141                 if (trans_edp_pipe == crtc->pipe)
7142                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7143         }
7144
7145         if (!intel_display_power_enabled(dev_priv,
7146                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7147                 return false;
7148
7149         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7150         if (!(tmp & PIPECONF_ENABLE))
7151                 return false;
7152
7153         /*
7154          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7155          * DDI E. So just check whether this pipe is wired to DDI E and whether
7156          * the PCH transcoder is on.
7157          */
7158         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7159         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7160             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7161                 pipe_config->has_pch_encoder = true;
7162
7163                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7164                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7165                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7166
7167                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7168         }
7169
7170         intel_get_pipe_timings(crtc, pipe_config);
7171
7172         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7173         if (intel_display_power_enabled(dev_priv, pfit_domain))
7174                 ironlake_get_pfit_config(crtc, pipe_config);
7175
7176         if (IS_HASWELL(dev))
7177                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7178                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7179
7180         pipe_config->pixel_multiplier = 1;
7181
7182         return true;
7183 }
7184
7185 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7186                                int x, int y,
7187                                struct drm_framebuffer *fb)
7188 {
7189         struct drm_device *dev = crtc->dev;
7190         struct drm_i915_private *dev_priv = dev->dev_private;
7191         struct intel_encoder *encoder;
7192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7194         int pipe = intel_crtc->pipe;
7195         int ret;
7196
7197         drm_vblank_pre_modeset(dev, pipe);
7198
7199         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7200
7201         drm_vblank_post_modeset(dev, pipe);
7202
7203         if (ret != 0)
7204                 return ret;
7205
7206         for_each_encoder_on_crtc(dev, crtc, encoder) {
7207                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7208                         encoder->base.base.id,
7209                         drm_get_encoder_name(&encoder->base),
7210                         mode->base.id, mode->name);
7211
7212                 if (encoder->mode_set)
7213                         encoder->mode_set(encoder);
7214         }
7215
7216         return 0;
7217 }
7218
7219 static struct {
7220         int clock;
7221         u32 config;
7222 } hdmi_audio_clock[] = {
7223         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7224         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7225         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7226         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7227         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7228         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7229         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7230         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7231         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7232         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7233 };
7234
7235 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7236 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7237 {
7238         int i;
7239
7240         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7241                 if (mode->clock == hdmi_audio_clock[i].clock)
7242                         break;
7243         }
7244
7245         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7246                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7247                 i = 1;
7248         }
7249
7250         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7251                       hdmi_audio_clock[i].clock,
7252                       hdmi_audio_clock[i].config);
7253
7254         return hdmi_audio_clock[i].config;
7255 }
7256
7257 static bool intel_eld_uptodate(struct drm_connector *connector,
7258                                int reg_eldv, uint32_t bits_eldv,
7259                                int reg_elda, uint32_t bits_elda,
7260                                int reg_edid)
7261 {
7262         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7263         uint8_t *eld = connector->eld;
7264         uint32_t i;
7265
7266         i = I915_READ(reg_eldv);
7267         i &= bits_eldv;
7268
7269         if (!eld[0])
7270                 return !i;
7271
7272         if (!i)
7273                 return false;
7274
7275         i = I915_READ(reg_elda);
7276         i &= ~bits_elda;
7277         I915_WRITE(reg_elda, i);
7278
7279         for (i = 0; i < eld[2]; i++)
7280                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7281                         return false;
7282
7283         return true;
7284 }
7285
7286 static void g4x_write_eld(struct drm_connector *connector,
7287                           struct drm_crtc *crtc,
7288                           struct drm_display_mode *mode)
7289 {
7290         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7291         uint8_t *eld = connector->eld;
7292         uint32_t eldv;
7293         uint32_t len;
7294         uint32_t i;
7295
7296         i = I915_READ(G4X_AUD_VID_DID);
7297
7298         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7299                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7300         else
7301                 eldv = G4X_ELDV_DEVCTG;
7302
7303         if (intel_eld_uptodate(connector,
7304                                G4X_AUD_CNTL_ST, eldv,
7305                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7306                                G4X_HDMIW_HDMIEDID))
7307                 return;
7308
7309         i = I915_READ(G4X_AUD_CNTL_ST);
7310         i &= ~(eldv | G4X_ELD_ADDR);
7311         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7312         I915_WRITE(G4X_AUD_CNTL_ST, i);
7313
7314         if (!eld[0])
7315                 return;
7316
7317         len = min_t(uint8_t, eld[2], len);
7318         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7319         for (i = 0; i < len; i++)
7320                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7321
7322         i = I915_READ(G4X_AUD_CNTL_ST);
7323         i |= eldv;
7324         I915_WRITE(G4X_AUD_CNTL_ST, i);
7325 }
7326
7327 static void haswell_write_eld(struct drm_connector *connector,
7328                               struct drm_crtc *crtc,
7329                               struct drm_display_mode *mode)
7330 {
7331         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7332         uint8_t *eld = connector->eld;
7333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7334         uint32_t eldv;
7335         uint32_t i;
7336         int len;
7337         int pipe = to_intel_crtc(crtc)->pipe;
7338         int tmp;
7339
7340         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7341         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7342         int aud_config = HSW_AUD_CFG(pipe);
7343         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7344
7345         /* Audio output enable */
7346         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7347         tmp = I915_READ(aud_cntrl_st2);
7348         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7349         I915_WRITE(aud_cntrl_st2, tmp);
7350         POSTING_READ(aud_cntrl_st2);
7351
7352         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7353
7354         /* Set ELD valid state */
7355         tmp = I915_READ(aud_cntrl_st2);
7356         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7357         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7358         I915_WRITE(aud_cntrl_st2, tmp);
7359         tmp = I915_READ(aud_cntrl_st2);
7360         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7361
7362         /* Enable HDMI mode */
7363         tmp = I915_READ(aud_config);
7364         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7365         /* clear N_programing_enable and N_value_index */
7366         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7367         I915_WRITE(aud_config, tmp);
7368
7369         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7370
7371         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7372         intel_crtc->eld_vld = true;
7373
7374         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7375                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7376                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7377                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7378         } else {
7379                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7380         }
7381
7382         if (intel_eld_uptodate(connector,
7383                                aud_cntrl_st2, eldv,
7384                                aud_cntl_st, IBX_ELD_ADDRESS,
7385                                hdmiw_hdmiedid))
7386                 return;
7387
7388         i = I915_READ(aud_cntrl_st2);
7389         i &= ~eldv;
7390         I915_WRITE(aud_cntrl_st2, i);
7391
7392         if (!eld[0])
7393                 return;
7394
7395         i = I915_READ(aud_cntl_st);
7396         i &= ~IBX_ELD_ADDRESS;
7397         I915_WRITE(aud_cntl_st, i);
7398         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7399         DRM_DEBUG_DRIVER("port num:%d\n", i);
7400
7401         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7402         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7403         for (i = 0; i < len; i++)
7404                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7405
7406         i = I915_READ(aud_cntrl_st2);
7407         i |= eldv;
7408         I915_WRITE(aud_cntrl_st2, i);
7409
7410 }
7411
7412 static void ironlake_write_eld(struct drm_connector *connector,
7413                                struct drm_crtc *crtc,
7414                                struct drm_display_mode *mode)
7415 {
7416         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7417         uint8_t *eld = connector->eld;
7418         uint32_t eldv;
7419         uint32_t i;
7420         int len;
7421         int hdmiw_hdmiedid;
7422         int aud_config;
7423         int aud_cntl_st;
7424         int aud_cntrl_st2;
7425         int pipe = to_intel_crtc(crtc)->pipe;
7426
7427         if (HAS_PCH_IBX(connector->dev)) {
7428                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7429                 aud_config = IBX_AUD_CFG(pipe);
7430                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7431                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7432         } else if (IS_VALLEYVIEW(connector->dev)) {
7433                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7434                 aud_config = VLV_AUD_CFG(pipe);
7435                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7436                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7437         } else {
7438                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7439                 aud_config = CPT_AUD_CFG(pipe);
7440                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7441                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7442         }
7443
7444         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7445
7446         if (IS_VALLEYVIEW(connector->dev))  {
7447                 struct intel_encoder *intel_encoder;
7448                 struct intel_digital_port *intel_dig_port;
7449
7450                 intel_encoder = intel_attached_encoder(connector);
7451                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7452                 i = intel_dig_port->port;
7453         } else {
7454                 i = I915_READ(aud_cntl_st);
7455                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7456                 /* DIP_Port_Select, 0x1 = PortB */
7457         }
7458
7459         if (!i) {
7460                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7461                 /* operate blindly on all ports */
7462                 eldv = IBX_ELD_VALIDB;
7463                 eldv |= IBX_ELD_VALIDB << 4;
7464                 eldv |= IBX_ELD_VALIDB << 8;
7465         } else {
7466                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7467                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7468         }
7469
7470         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7471                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7472                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7473                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7474         } else {
7475                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7476         }
7477
7478         if (intel_eld_uptodate(connector,
7479                                aud_cntrl_st2, eldv,
7480                                aud_cntl_st, IBX_ELD_ADDRESS,
7481                                hdmiw_hdmiedid))
7482                 return;
7483
7484         i = I915_READ(aud_cntrl_st2);
7485         i &= ~eldv;
7486         I915_WRITE(aud_cntrl_st2, i);
7487
7488         if (!eld[0])
7489                 return;
7490
7491         i = I915_READ(aud_cntl_st);
7492         i &= ~IBX_ELD_ADDRESS;
7493         I915_WRITE(aud_cntl_st, i);
7494
7495         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7496         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7497         for (i = 0; i < len; i++)
7498                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7499
7500         i = I915_READ(aud_cntrl_st2);
7501         i |= eldv;
7502         I915_WRITE(aud_cntrl_st2, i);
7503 }
7504
7505 void intel_write_eld(struct drm_encoder *encoder,
7506                      struct drm_display_mode *mode)
7507 {
7508         struct drm_crtc *crtc = encoder->crtc;
7509         struct drm_connector *connector;
7510         struct drm_device *dev = encoder->dev;
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512
7513         connector = drm_select_eld(encoder, mode);
7514         if (!connector)
7515                 return;
7516
7517         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7518                          connector->base.id,
7519                          drm_get_connector_name(connector),
7520                          connector->encoder->base.id,
7521                          drm_get_encoder_name(connector->encoder));
7522
7523         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7524
7525         if (dev_priv->display.write_eld)
7526                 dev_priv->display.write_eld(connector, crtc, mode);
7527 }
7528
7529 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7530 {
7531         struct drm_device *dev = crtc->dev;
7532         struct drm_i915_private *dev_priv = dev->dev_private;
7533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7534         bool visible = base != 0;
7535         u32 cntl;
7536
7537         if (intel_crtc->cursor_visible == visible)
7538                 return;
7539
7540         cntl = I915_READ(_CURACNTR);
7541         if (visible) {
7542                 /* On these chipsets we can only modify the base whilst
7543                  * the cursor is disabled.
7544                  */
7545                 I915_WRITE(_CURABASE, base);
7546
7547                 cntl &= ~(CURSOR_FORMAT_MASK);
7548                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7549                 cntl |= CURSOR_ENABLE |
7550                         CURSOR_GAMMA_ENABLE |
7551                         CURSOR_FORMAT_ARGB;
7552         } else
7553                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7554         I915_WRITE(_CURACNTR, cntl);
7555
7556         intel_crtc->cursor_visible = visible;
7557 }
7558
7559 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7560 {
7561         struct drm_device *dev = crtc->dev;
7562         struct drm_i915_private *dev_priv = dev->dev_private;
7563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564         int pipe = intel_crtc->pipe;
7565         bool visible = base != 0;
7566
7567         if (intel_crtc->cursor_visible != visible) {
7568                 int16_t width = intel_crtc->cursor_width;
7569                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7570                 if (base) {
7571                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7572                         cntl |= MCURSOR_GAMMA_ENABLE;
7573
7574                         switch (width) {
7575                         case 64:
7576                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7577                                 break;
7578                         case 128:
7579                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7580                                 break;
7581                         case 256:
7582                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7583                                 break;
7584                         default:
7585                                 WARN_ON(1);
7586                                 return;
7587                         }
7588                         cntl |= pipe << 28; /* Connect to correct pipe */
7589                 } else {
7590                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7591                         cntl |= CURSOR_MODE_DISABLE;
7592                 }
7593                 I915_WRITE(CURCNTR(pipe), cntl);
7594
7595                 intel_crtc->cursor_visible = visible;
7596         }
7597         /* and commit changes on next vblank */
7598         POSTING_READ(CURCNTR(pipe));
7599         I915_WRITE(CURBASE(pipe), base);
7600         POSTING_READ(CURBASE(pipe));
7601 }
7602
7603 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7604 {
7605         struct drm_device *dev = crtc->dev;
7606         struct drm_i915_private *dev_priv = dev->dev_private;
7607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7608         int pipe = intel_crtc->pipe;
7609         bool visible = base != 0;
7610
7611         if (intel_crtc->cursor_visible != visible) {
7612                 int16_t width = intel_crtc->cursor_width;
7613                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7614                 if (base) {
7615                         cntl &= ~CURSOR_MODE;
7616                         cntl |= MCURSOR_GAMMA_ENABLE;
7617                         switch (width) {
7618                         case 64:
7619                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7620                                 break;
7621                         case 128:
7622                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7623                                 break;
7624                         case 256:
7625                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7626                                 break;
7627                         default:
7628                                 WARN_ON(1);
7629                                 return;
7630                         }
7631                 } else {
7632                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7633                         cntl |= CURSOR_MODE_DISABLE;
7634                 }
7635                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7636                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7637                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7638                 }
7639                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7640
7641                 intel_crtc->cursor_visible = visible;
7642         }
7643         /* and commit changes on next vblank */
7644         POSTING_READ(CURCNTR_IVB(pipe));
7645         I915_WRITE(CURBASE_IVB(pipe), base);
7646         POSTING_READ(CURBASE_IVB(pipe));
7647 }
7648
7649 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7650 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7651                                      bool on)
7652 {
7653         struct drm_device *dev = crtc->dev;
7654         struct drm_i915_private *dev_priv = dev->dev_private;
7655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7656         int pipe = intel_crtc->pipe;
7657         int x = intel_crtc->cursor_x;
7658         int y = intel_crtc->cursor_y;
7659         u32 base = 0, pos = 0;
7660         bool visible;
7661
7662         if (on)
7663                 base = intel_crtc->cursor_addr;
7664
7665         if (x >= intel_crtc->config.pipe_src_w)
7666                 base = 0;
7667
7668         if (y >= intel_crtc->config.pipe_src_h)
7669                 base = 0;
7670
7671         if (x < 0) {
7672                 if (x + intel_crtc->cursor_width <= 0)
7673                         base = 0;
7674
7675                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7676                 x = -x;
7677         }
7678         pos |= x << CURSOR_X_SHIFT;
7679
7680         if (y < 0) {
7681                 if (y + intel_crtc->cursor_height <= 0)
7682                         base = 0;
7683
7684                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7685                 y = -y;
7686         }
7687         pos |= y << CURSOR_Y_SHIFT;
7688
7689         visible = base != 0;
7690         if (!visible && !intel_crtc->cursor_visible)
7691                 return;
7692
7693         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7694                 I915_WRITE(CURPOS_IVB(pipe), pos);
7695                 ivb_update_cursor(crtc, base);
7696         } else {
7697                 I915_WRITE(CURPOS(pipe), pos);
7698                 if (IS_845G(dev) || IS_I865G(dev))
7699                         i845_update_cursor(crtc, base);
7700                 else
7701                         i9xx_update_cursor(crtc, base);
7702         }
7703 }
7704
7705 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7706                                  struct drm_file *file,
7707                                  uint32_t handle,
7708                                  uint32_t width, uint32_t height)
7709 {
7710         struct drm_device *dev = crtc->dev;
7711         struct drm_i915_private *dev_priv = dev->dev_private;
7712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7713         struct drm_i915_gem_object *obj;
7714         unsigned old_width;
7715         uint32_t addr;
7716         int ret;
7717
7718         /* if we want to turn off the cursor ignore width and height */
7719         if (!handle) {
7720                 DRM_DEBUG_KMS("cursor off\n");
7721                 addr = 0;
7722                 obj = NULL;
7723                 mutex_lock(&dev->struct_mutex);
7724                 goto finish;
7725         }
7726
7727         /* Check for which cursor types we support */
7728         if (!((width == 64 && height == 64) ||
7729                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7730                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7731                 DRM_DEBUG("Cursor dimension not supported\n");
7732                 return -EINVAL;
7733         }
7734
7735         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7736         if (&obj->base == NULL)
7737                 return -ENOENT;
7738
7739         if (obj->base.size < width * height * 4) {
7740                 DRM_DEBUG_KMS("buffer is to small\n");
7741                 ret = -ENOMEM;
7742                 goto fail;
7743         }
7744
7745         /* we only need to pin inside GTT if cursor is non-phy */
7746         mutex_lock(&dev->struct_mutex);
7747         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7748                 unsigned alignment;
7749
7750                 if (obj->tiling_mode) {
7751                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7752                         ret = -EINVAL;
7753                         goto fail_locked;
7754                 }
7755
7756                 /* Note that the w/a also requires 2 PTE of padding following
7757                  * the bo. We currently fill all unused PTE with the shadow
7758                  * page and so we should always have valid PTE following the
7759                  * cursor preventing the VT-d warning.
7760                  */
7761                 alignment = 0;
7762                 if (need_vtd_wa(dev))
7763                         alignment = 64*1024;
7764
7765                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7766                 if (ret) {
7767                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7768                         goto fail_locked;
7769                 }
7770
7771                 ret = i915_gem_object_put_fence(obj);
7772                 if (ret) {
7773                         DRM_DEBUG_KMS("failed to release fence for cursor");
7774                         goto fail_unpin;
7775                 }
7776
7777                 addr = i915_gem_obj_ggtt_offset(obj);
7778         } else {
7779                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7780                 ret = i915_gem_attach_phys_object(dev, obj,
7781                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7782                                                   align);
7783                 if (ret) {
7784                         DRM_DEBUG_KMS("failed to attach phys object\n");
7785                         goto fail_locked;
7786                 }
7787                 addr = obj->phys_obj->handle->busaddr;
7788         }
7789
7790         if (IS_GEN2(dev))
7791                 I915_WRITE(CURSIZE, (height << 12) | width);
7792
7793  finish:
7794         if (intel_crtc->cursor_bo) {
7795                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7796                         if (intel_crtc->cursor_bo != obj)
7797                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7798                 } else
7799                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7800                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7801         }
7802
7803         mutex_unlock(&dev->struct_mutex);
7804
7805         old_width = intel_crtc->cursor_width;
7806
7807         intel_crtc->cursor_addr = addr;
7808         intel_crtc->cursor_bo = obj;
7809         intel_crtc->cursor_width = width;
7810         intel_crtc->cursor_height = height;
7811
7812         if (intel_crtc->active) {
7813                 if (old_width != width)
7814                         intel_update_watermarks(crtc);
7815                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7816         }
7817
7818         return 0;
7819 fail_unpin:
7820         i915_gem_object_unpin_from_display_plane(obj);
7821 fail_locked:
7822         mutex_unlock(&dev->struct_mutex);
7823 fail:
7824         drm_gem_object_unreference_unlocked(&obj->base);
7825         return ret;
7826 }
7827
7828 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7829 {
7830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7831
7832         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7833         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7834
7835         if (intel_crtc->active)
7836                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7837
7838         return 0;
7839 }
7840
7841 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7842                                  u16 *blue, uint32_t start, uint32_t size)
7843 {
7844         int end = (start + size > 256) ? 256 : start + size, i;
7845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7846
7847         for (i = start; i < end; i++) {
7848                 intel_crtc->lut_r[i] = red[i] >> 8;
7849                 intel_crtc->lut_g[i] = green[i] >> 8;
7850                 intel_crtc->lut_b[i] = blue[i] >> 8;
7851         }
7852
7853         intel_crtc_load_lut(crtc);
7854 }
7855
7856 /* VESA 640x480x72Hz mode to set on the pipe */
7857 static struct drm_display_mode load_detect_mode = {
7858         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7859                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7860 };
7861
7862 struct drm_framebuffer *
7863 __intel_framebuffer_create(struct drm_device *dev,
7864                            struct drm_mode_fb_cmd2 *mode_cmd,
7865                            struct drm_i915_gem_object *obj)
7866 {
7867         struct intel_framebuffer *intel_fb;
7868         int ret;
7869
7870         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7871         if (!intel_fb) {
7872                 drm_gem_object_unreference_unlocked(&obj->base);
7873                 return ERR_PTR(-ENOMEM);
7874         }
7875
7876         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7877         if (ret)
7878                 goto err;
7879
7880         return &intel_fb->base;
7881 err:
7882         drm_gem_object_unreference_unlocked(&obj->base);
7883         kfree(intel_fb);
7884
7885         return ERR_PTR(ret);
7886 }
7887
7888 static struct drm_framebuffer *
7889 intel_framebuffer_create(struct drm_device *dev,
7890                          struct drm_mode_fb_cmd2 *mode_cmd,
7891                          struct drm_i915_gem_object *obj)
7892 {
7893         struct drm_framebuffer *fb;
7894         int ret;
7895
7896         ret = i915_mutex_lock_interruptible(dev);
7897         if (ret)
7898                 return ERR_PTR(ret);
7899         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7900         mutex_unlock(&dev->struct_mutex);
7901
7902         return fb;
7903 }
7904
7905 static u32
7906 intel_framebuffer_pitch_for_width(int width, int bpp)
7907 {
7908         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7909         return ALIGN(pitch, 64);
7910 }
7911
7912 static u32
7913 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7914 {
7915         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7916         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7917 }
7918
7919 static struct drm_framebuffer *
7920 intel_framebuffer_create_for_mode(struct drm_device *dev,
7921                                   struct drm_display_mode *mode,
7922                                   int depth, int bpp)
7923 {
7924         struct drm_i915_gem_object *obj;
7925         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7926
7927         obj = i915_gem_alloc_object(dev,
7928                                     intel_framebuffer_size_for_mode(mode, bpp));
7929         if (obj == NULL)
7930                 return ERR_PTR(-ENOMEM);
7931
7932         mode_cmd.width = mode->hdisplay;
7933         mode_cmd.height = mode->vdisplay;
7934         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7935                                                                 bpp);
7936         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7937
7938         return intel_framebuffer_create(dev, &mode_cmd, obj);
7939 }
7940
7941 static struct drm_framebuffer *
7942 mode_fits_in_fbdev(struct drm_device *dev,
7943                    struct drm_display_mode *mode)
7944 {
7945 #ifdef CONFIG_DRM_I915_FBDEV
7946         struct drm_i915_private *dev_priv = dev->dev_private;
7947         struct drm_i915_gem_object *obj;
7948         struct drm_framebuffer *fb;
7949
7950         if (!dev_priv->fbdev)
7951                 return NULL;
7952
7953         if (!dev_priv->fbdev->fb)
7954                 return NULL;
7955
7956         obj = dev_priv->fbdev->fb->obj;
7957         BUG_ON(!obj);
7958
7959         fb = &dev_priv->fbdev->fb->base;
7960         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7961                                                                fb->bits_per_pixel))
7962                 return NULL;
7963
7964         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7965                 return NULL;
7966
7967         return fb;
7968 #else
7969         return NULL;
7970 #endif
7971 }
7972
7973 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7974                                 struct drm_display_mode *mode,
7975                                 struct intel_load_detect_pipe *old)
7976 {
7977         struct intel_crtc *intel_crtc;
7978         struct intel_encoder *intel_encoder =
7979                 intel_attached_encoder(connector);
7980         struct drm_crtc *possible_crtc;
7981         struct drm_encoder *encoder = &intel_encoder->base;
7982         struct drm_crtc *crtc = NULL;
7983         struct drm_device *dev = encoder->dev;
7984         struct drm_framebuffer *fb;
7985         int i = -1;
7986
7987         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7988                       connector->base.id, drm_get_connector_name(connector),
7989                       encoder->base.id, drm_get_encoder_name(encoder));
7990
7991         /*
7992          * Algorithm gets a little messy:
7993          *
7994          *   - if the connector already has an assigned crtc, use it (but make
7995          *     sure it's on first)
7996          *
7997          *   - try to find the first unused crtc that can drive this connector,
7998          *     and use that if we find one
7999          */
8000
8001         /* See if we already have a CRTC for this connector */
8002         if (encoder->crtc) {
8003                 crtc = encoder->crtc;
8004
8005                 mutex_lock(&crtc->mutex);
8006
8007                 old->dpms_mode = connector->dpms;
8008                 old->load_detect_temp = false;
8009
8010                 /* Make sure the crtc and connector are running */
8011                 if (connector->dpms != DRM_MODE_DPMS_ON)
8012                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8013
8014                 return true;
8015         }
8016
8017         /* Find an unused one (if possible) */
8018         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8019                 i++;
8020                 if (!(encoder->possible_crtcs & (1 << i)))
8021                         continue;
8022                 if (!possible_crtc->enabled) {
8023                         crtc = possible_crtc;
8024                         break;
8025                 }
8026         }
8027
8028         /*
8029          * If we didn't find an unused CRTC, don't use any.
8030          */
8031         if (!crtc) {
8032                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8033                 return false;
8034         }
8035
8036         mutex_lock(&crtc->mutex);
8037         intel_encoder->new_crtc = to_intel_crtc(crtc);
8038         to_intel_connector(connector)->new_encoder = intel_encoder;
8039
8040         intel_crtc = to_intel_crtc(crtc);
8041         intel_crtc->new_enabled = true;
8042         intel_crtc->new_config = &intel_crtc->config;
8043         old->dpms_mode = connector->dpms;
8044         old->load_detect_temp = true;
8045         old->release_fb = NULL;
8046
8047         if (!mode)
8048                 mode = &load_detect_mode;
8049
8050         /* We need a framebuffer large enough to accommodate all accesses
8051          * that the plane may generate whilst we perform load detection.
8052          * We can not rely on the fbcon either being present (we get called
8053          * during its initialisation to detect all boot displays, or it may
8054          * not even exist) or that it is large enough to satisfy the
8055          * requested mode.
8056          */
8057         fb = mode_fits_in_fbdev(dev, mode);
8058         if (fb == NULL) {
8059                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8060                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8061                 old->release_fb = fb;
8062         } else
8063                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8064         if (IS_ERR(fb)) {
8065                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8066                 goto fail;
8067         }
8068
8069         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8070                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8071                 if (old->release_fb)
8072                         old->release_fb->funcs->destroy(old->release_fb);
8073                 goto fail;
8074         }
8075
8076         /* let the connector get through one full cycle before testing */
8077         intel_wait_for_vblank(dev, intel_crtc->pipe);
8078         return true;
8079
8080  fail:
8081         intel_crtc->new_enabled = crtc->enabled;
8082         if (intel_crtc->new_enabled)
8083                 intel_crtc->new_config = &intel_crtc->config;
8084         else
8085                 intel_crtc->new_config = NULL;
8086         mutex_unlock(&crtc->mutex);
8087         return false;
8088 }
8089
8090 void intel_release_load_detect_pipe(struct drm_connector *connector,
8091                                     struct intel_load_detect_pipe *old)
8092 {
8093         struct intel_encoder *intel_encoder =
8094                 intel_attached_encoder(connector);
8095         struct drm_encoder *encoder = &intel_encoder->base;
8096         struct drm_crtc *crtc = encoder->crtc;
8097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8098
8099         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8100                       connector->base.id, drm_get_connector_name(connector),
8101                       encoder->base.id, drm_get_encoder_name(encoder));
8102
8103         if (old->load_detect_temp) {
8104                 to_intel_connector(connector)->new_encoder = NULL;
8105                 intel_encoder->new_crtc = NULL;
8106                 intel_crtc->new_enabled = false;
8107                 intel_crtc->new_config = NULL;
8108                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8109
8110                 if (old->release_fb) {
8111                         drm_framebuffer_unregister_private(old->release_fb);
8112                         drm_framebuffer_unreference(old->release_fb);
8113                 }
8114
8115                 mutex_unlock(&crtc->mutex);
8116                 return;
8117         }
8118
8119         /* Switch crtc and encoder back off if necessary */
8120         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8121                 connector->funcs->dpms(connector, old->dpms_mode);
8122
8123         mutex_unlock(&crtc->mutex);
8124 }
8125
8126 static int i9xx_pll_refclk(struct drm_device *dev,
8127                            const struct intel_crtc_config *pipe_config)
8128 {
8129         struct drm_i915_private *dev_priv = dev->dev_private;
8130         u32 dpll = pipe_config->dpll_hw_state.dpll;
8131
8132         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8133                 return dev_priv->vbt.lvds_ssc_freq;
8134         else if (HAS_PCH_SPLIT(dev))
8135                 return 120000;
8136         else if (!IS_GEN2(dev))
8137                 return 96000;
8138         else
8139                 return 48000;
8140 }
8141
8142 /* Returns the clock of the currently programmed mode of the given pipe. */
8143 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8144                                 struct intel_crtc_config *pipe_config)
8145 {
8146         struct drm_device *dev = crtc->base.dev;
8147         struct drm_i915_private *dev_priv = dev->dev_private;
8148         int pipe = pipe_config->cpu_transcoder;
8149         u32 dpll = pipe_config->dpll_hw_state.dpll;
8150         u32 fp;
8151         intel_clock_t clock;
8152         int refclk = i9xx_pll_refclk(dev, pipe_config);
8153
8154         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8155                 fp = pipe_config->dpll_hw_state.fp0;
8156         else
8157                 fp = pipe_config->dpll_hw_state.fp1;
8158
8159         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8160         if (IS_PINEVIEW(dev)) {
8161                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8162                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8163         } else {
8164                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8165                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8166         }
8167
8168         if (!IS_GEN2(dev)) {
8169                 if (IS_PINEVIEW(dev))
8170                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8171                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8172                 else
8173                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8174                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8175
8176                 switch (dpll & DPLL_MODE_MASK) {
8177                 case DPLLB_MODE_DAC_SERIAL:
8178                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8179                                 5 : 10;
8180                         break;
8181                 case DPLLB_MODE_LVDS:
8182                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8183                                 7 : 14;
8184                         break;
8185                 default:
8186                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8187                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8188                         return;
8189                 }
8190
8191                 if (IS_PINEVIEW(dev))
8192                         pineview_clock(refclk, &clock);
8193                 else
8194                         i9xx_clock(refclk, &clock);
8195         } else {
8196                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8197                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8198
8199                 if (is_lvds) {
8200                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8201                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8202
8203                         if (lvds & LVDS_CLKB_POWER_UP)
8204                                 clock.p2 = 7;
8205                         else
8206                                 clock.p2 = 14;
8207                 } else {
8208                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8209                                 clock.p1 = 2;
8210                         else {
8211                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8212                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8213                         }
8214                         if (dpll & PLL_P2_DIVIDE_BY_4)
8215                                 clock.p2 = 4;
8216                         else
8217                                 clock.p2 = 2;
8218                 }
8219
8220                 i9xx_clock(refclk, &clock);
8221         }
8222
8223         /*
8224          * This value includes pixel_multiplier. We will use
8225          * port_clock to compute adjusted_mode.crtc_clock in the
8226          * encoder's get_config() function.
8227          */
8228         pipe_config->port_clock = clock.dot;
8229 }
8230
8231 int intel_dotclock_calculate(int link_freq,
8232                              const struct intel_link_m_n *m_n)
8233 {
8234         /*
8235          * The calculation for the data clock is:
8236          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8237          * But we want to avoid losing precison if possible, so:
8238          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8239          *
8240          * and the link clock is simpler:
8241          * link_clock = (m * link_clock) / n
8242          */
8243
8244         if (!m_n->link_n)
8245                 return 0;
8246
8247         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8248 }
8249
8250 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8251                                    struct intel_crtc_config *pipe_config)
8252 {
8253         struct drm_device *dev = crtc->base.dev;
8254
8255         /* read out port_clock from the DPLL */
8256         i9xx_crtc_clock_get(crtc, pipe_config);
8257
8258         /*
8259          * This value does not include pixel_multiplier.
8260          * We will check that port_clock and adjusted_mode.crtc_clock
8261          * agree once we know their relationship in the encoder's
8262          * get_config() function.
8263          */
8264         pipe_config->adjusted_mode.crtc_clock =
8265                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8266                                          &pipe_config->fdi_m_n);
8267 }
8268
8269 /** Returns the currently programmed mode of the given pipe. */
8270 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8271                                              struct drm_crtc *crtc)
8272 {
8273         struct drm_i915_private *dev_priv = dev->dev_private;
8274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8275         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8276         struct drm_display_mode *mode;
8277         struct intel_crtc_config pipe_config;
8278         int htot = I915_READ(HTOTAL(cpu_transcoder));
8279         int hsync = I915_READ(HSYNC(cpu_transcoder));
8280         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8281         int vsync = I915_READ(VSYNC(cpu_transcoder));
8282         enum pipe pipe = intel_crtc->pipe;
8283
8284         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8285         if (!mode)
8286                 return NULL;
8287
8288         /*
8289          * Construct a pipe_config sufficient for getting the clock info
8290          * back out of crtc_clock_get.
8291          *
8292          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8293          * to use a real value here instead.
8294          */
8295         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8296         pipe_config.pixel_multiplier = 1;
8297         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8298         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8299         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8300         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8301
8302         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8303         mode->hdisplay = (htot & 0xffff) + 1;
8304         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8305         mode->hsync_start = (hsync & 0xffff) + 1;
8306         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8307         mode->vdisplay = (vtot & 0xffff) + 1;
8308         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8309         mode->vsync_start = (vsync & 0xffff) + 1;
8310         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8311
8312         drm_mode_set_name(mode);
8313
8314         return mode;
8315 }
8316
8317 static void intel_increase_pllclock(struct drm_crtc *crtc)
8318 {
8319         struct drm_device *dev = crtc->dev;
8320         struct drm_i915_private *dev_priv = dev->dev_private;
8321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8322         int pipe = intel_crtc->pipe;
8323         int dpll_reg = DPLL(pipe);
8324         int dpll;
8325
8326         if (HAS_PCH_SPLIT(dev))
8327                 return;
8328
8329         if (!dev_priv->lvds_downclock_avail)
8330                 return;
8331
8332         dpll = I915_READ(dpll_reg);
8333         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8334                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8335
8336                 assert_panel_unlocked(dev_priv, pipe);
8337
8338                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8339                 I915_WRITE(dpll_reg, dpll);
8340                 intel_wait_for_vblank(dev, pipe);
8341
8342                 dpll = I915_READ(dpll_reg);
8343                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8344                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8345         }
8346 }
8347
8348 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8349 {
8350         struct drm_device *dev = crtc->dev;
8351         struct drm_i915_private *dev_priv = dev->dev_private;
8352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8353
8354         if (HAS_PCH_SPLIT(dev))
8355                 return;
8356
8357         if (!dev_priv->lvds_downclock_avail)
8358                 return;
8359
8360         /*
8361          * Since this is called by a timer, we should never get here in
8362          * the manual case.
8363          */
8364         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8365                 int pipe = intel_crtc->pipe;
8366                 int dpll_reg = DPLL(pipe);
8367                 int dpll;
8368
8369                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8370
8371                 assert_panel_unlocked(dev_priv, pipe);
8372
8373                 dpll = I915_READ(dpll_reg);
8374                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8375                 I915_WRITE(dpll_reg, dpll);
8376                 intel_wait_for_vblank(dev, pipe);
8377                 dpll = I915_READ(dpll_reg);
8378                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8379                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8380         }
8381
8382 }
8383
8384 void intel_mark_busy(struct drm_device *dev)
8385 {
8386         struct drm_i915_private *dev_priv = dev->dev_private;
8387
8388         if (dev_priv->mm.busy)
8389                 return;
8390
8391         intel_runtime_pm_get(dev_priv);
8392         i915_update_gfx_val(dev_priv);
8393         dev_priv->mm.busy = true;
8394 }
8395
8396 void intel_mark_idle(struct drm_device *dev)
8397 {
8398         struct drm_i915_private *dev_priv = dev->dev_private;
8399         struct drm_crtc *crtc;
8400
8401         if (!dev_priv->mm.busy)
8402                 return;
8403
8404         dev_priv->mm.busy = false;
8405
8406         if (!i915.powersave)
8407                 goto out;
8408
8409         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8410                 if (!crtc->primary->fb)
8411                         continue;
8412
8413                 intel_decrease_pllclock(crtc);
8414         }
8415
8416         if (INTEL_INFO(dev)->gen >= 6)
8417                 gen6_rps_idle(dev->dev_private);
8418
8419 out:
8420         intel_runtime_pm_put(dev_priv);
8421 }
8422
8423 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8424                         struct intel_ring_buffer *ring)
8425 {
8426         struct drm_device *dev = obj->base.dev;
8427         struct drm_crtc *crtc;
8428
8429         if (!i915.powersave)
8430                 return;
8431
8432         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8433                 if (!crtc->primary->fb)
8434                         continue;
8435
8436                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8437                         continue;
8438
8439                 intel_increase_pllclock(crtc);
8440                 if (ring && intel_fbc_enabled(dev))
8441                         ring->fbc_dirty = true;
8442         }
8443 }
8444
8445 static void intel_crtc_destroy(struct drm_crtc *crtc)
8446 {
8447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8448         struct drm_device *dev = crtc->dev;
8449         struct intel_unpin_work *work;
8450         unsigned long flags;
8451
8452         spin_lock_irqsave(&dev->event_lock, flags);
8453         work = intel_crtc->unpin_work;
8454         intel_crtc->unpin_work = NULL;
8455         spin_unlock_irqrestore(&dev->event_lock, flags);
8456
8457         if (work) {
8458                 cancel_work_sync(&work->work);
8459                 kfree(work);
8460         }
8461
8462         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8463
8464         drm_crtc_cleanup(crtc);
8465
8466         kfree(intel_crtc);
8467 }
8468
8469 static void intel_unpin_work_fn(struct work_struct *__work)
8470 {
8471         struct intel_unpin_work *work =
8472                 container_of(__work, struct intel_unpin_work, work);
8473         struct drm_device *dev = work->crtc->dev;
8474
8475         mutex_lock(&dev->struct_mutex);
8476         intel_unpin_fb_obj(work->old_fb_obj);
8477         drm_gem_object_unreference(&work->pending_flip_obj->base);
8478         drm_gem_object_unreference(&work->old_fb_obj->base);
8479
8480         intel_update_fbc(dev);
8481         mutex_unlock(&dev->struct_mutex);
8482
8483         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8484         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8485
8486         kfree(work);
8487 }
8488
8489 static void do_intel_finish_page_flip(struct drm_device *dev,
8490                                       struct drm_crtc *crtc)
8491 {
8492         struct drm_i915_private *dev_priv = dev->dev_private;
8493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8494         struct intel_unpin_work *work;
8495         unsigned long flags;
8496
8497         /* Ignore early vblank irqs */
8498         if (intel_crtc == NULL)
8499                 return;
8500
8501         spin_lock_irqsave(&dev->event_lock, flags);
8502         work = intel_crtc->unpin_work;
8503
8504         /* Ensure we don't miss a work->pending update ... */
8505         smp_rmb();
8506
8507         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8508                 spin_unlock_irqrestore(&dev->event_lock, flags);
8509                 return;
8510         }
8511
8512         /* and that the unpin work is consistent wrt ->pending. */
8513         smp_rmb();
8514
8515         intel_crtc->unpin_work = NULL;
8516
8517         if (work->event)
8518                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8519
8520         drm_vblank_put(dev, intel_crtc->pipe);
8521
8522         spin_unlock_irqrestore(&dev->event_lock, flags);
8523
8524         wake_up_all(&dev_priv->pending_flip_queue);
8525
8526         queue_work(dev_priv->wq, &work->work);
8527
8528         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8529 }
8530
8531 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8532 {
8533         struct drm_i915_private *dev_priv = dev->dev_private;
8534         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8535
8536         do_intel_finish_page_flip(dev, crtc);
8537 }
8538
8539 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8540 {
8541         struct drm_i915_private *dev_priv = dev->dev_private;
8542         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8543
8544         do_intel_finish_page_flip(dev, crtc);
8545 }
8546
8547 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8548 {
8549         struct drm_i915_private *dev_priv = dev->dev_private;
8550         struct intel_crtc *intel_crtc =
8551                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8552         unsigned long flags;
8553
8554         /* NB: An MMIO update of the plane base pointer will also
8555          * generate a page-flip completion irq, i.e. every modeset
8556          * is also accompanied by a spurious intel_prepare_page_flip().
8557          */
8558         spin_lock_irqsave(&dev->event_lock, flags);
8559         if (intel_crtc->unpin_work)
8560                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8561         spin_unlock_irqrestore(&dev->event_lock, flags);
8562 }
8563
8564 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8565 {
8566         /* Ensure that the work item is consistent when activating it ... */
8567         smp_wmb();
8568         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8569         /* and that it is marked active as soon as the irq could fire. */
8570         smp_wmb();
8571 }
8572
8573 static int intel_gen2_queue_flip(struct drm_device *dev,
8574                                  struct drm_crtc *crtc,
8575                                  struct drm_framebuffer *fb,
8576                                  struct drm_i915_gem_object *obj,
8577                                  uint32_t flags)
8578 {
8579         struct drm_i915_private *dev_priv = dev->dev_private;
8580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8581         u32 flip_mask;
8582         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8583         int ret;
8584
8585         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8586         if (ret)
8587                 goto err;
8588
8589         ret = intel_ring_begin(ring, 6);
8590         if (ret)
8591                 goto err_unpin;
8592
8593         /* Can't queue multiple flips, so wait for the previous
8594          * one to finish before executing the next.
8595          */
8596         if (intel_crtc->plane)
8597                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8598         else
8599                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8600         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8601         intel_ring_emit(ring, MI_NOOP);
8602         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8603                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8604         intel_ring_emit(ring, fb->pitches[0]);
8605         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8606         intel_ring_emit(ring, 0); /* aux display base address, unused */
8607
8608         intel_mark_page_flip_active(intel_crtc);
8609         __intel_ring_advance(ring);
8610         return 0;
8611
8612 err_unpin:
8613         intel_unpin_fb_obj(obj);
8614 err:
8615         return ret;
8616 }
8617
8618 static int intel_gen3_queue_flip(struct drm_device *dev,
8619                                  struct drm_crtc *crtc,
8620                                  struct drm_framebuffer *fb,
8621                                  struct drm_i915_gem_object *obj,
8622                                  uint32_t flags)
8623 {
8624         struct drm_i915_private *dev_priv = dev->dev_private;
8625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8626         u32 flip_mask;
8627         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8628         int ret;
8629
8630         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8631         if (ret)
8632                 goto err;
8633
8634         ret = intel_ring_begin(ring, 6);
8635         if (ret)
8636                 goto err_unpin;
8637
8638         if (intel_crtc->plane)
8639                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8640         else
8641                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8642         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8643         intel_ring_emit(ring, MI_NOOP);
8644         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8645                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8646         intel_ring_emit(ring, fb->pitches[0]);
8647         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8648         intel_ring_emit(ring, MI_NOOP);
8649
8650         intel_mark_page_flip_active(intel_crtc);
8651         __intel_ring_advance(ring);
8652         return 0;
8653
8654 err_unpin:
8655         intel_unpin_fb_obj(obj);
8656 err:
8657         return ret;
8658 }
8659
8660 static int intel_gen4_queue_flip(struct drm_device *dev,
8661                                  struct drm_crtc *crtc,
8662                                  struct drm_framebuffer *fb,
8663                                  struct drm_i915_gem_object *obj,
8664                                  uint32_t flags)
8665 {
8666         struct drm_i915_private *dev_priv = dev->dev_private;
8667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8668         uint32_t pf, pipesrc;
8669         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8670         int ret;
8671
8672         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8673         if (ret)
8674                 goto err;
8675
8676         ret = intel_ring_begin(ring, 4);
8677         if (ret)
8678                 goto err_unpin;
8679
8680         /* i965+ uses the linear or tiled offsets from the
8681          * Display Registers (which do not change across a page-flip)
8682          * so we need only reprogram the base address.
8683          */
8684         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8685                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8686         intel_ring_emit(ring, fb->pitches[0]);
8687         intel_ring_emit(ring,
8688                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8689                         obj->tiling_mode);
8690
8691         /* XXX Enabling the panel-fitter across page-flip is so far
8692          * untested on non-native modes, so ignore it for now.
8693          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8694          */
8695         pf = 0;
8696         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8697         intel_ring_emit(ring, pf | pipesrc);
8698
8699         intel_mark_page_flip_active(intel_crtc);
8700         __intel_ring_advance(ring);
8701         return 0;
8702
8703 err_unpin:
8704         intel_unpin_fb_obj(obj);
8705 err:
8706         return ret;
8707 }
8708
8709 static int intel_gen6_queue_flip(struct drm_device *dev,
8710                                  struct drm_crtc *crtc,
8711                                  struct drm_framebuffer *fb,
8712                                  struct drm_i915_gem_object *obj,
8713                                  uint32_t flags)
8714 {
8715         struct drm_i915_private *dev_priv = dev->dev_private;
8716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8717         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8718         uint32_t pf, pipesrc;
8719         int ret;
8720
8721         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8722         if (ret)
8723                 goto err;
8724
8725         ret = intel_ring_begin(ring, 4);
8726         if (ret)
8727                 goto err_unpin;
8728
8729         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8730                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8731         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8732         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8733
8734         /* Contrary to the suggestions in the documentation,
8735          * "Enable Panel Fitter" does not seem to be required when page
8736          * flipping with a non-native mode, and worse causes a normal
8737          * modeset to fail.
8738          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8739          */
8740         pf = 0;
8741         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8742         intel_ring_emit(ring, pf | pipesrc);
8743
8744         intel_mark_page_flip_active(intel_crtc);
8745         __intel_ring_advance(ring);
8746         return 0;
8747
8748 err_unpin:
8749         intel_unpin_fb_obj(obj);
8750 err:
8751         return ret;
8752 }
8753
8754 static int intel_gen7_queue_flip(struct drm_device *dev,
8755                                  struct drm_crtc *crtc,
8756                                  struct drm_framebuffer *fb,
8757                                  struct drm_i915_gem_object *obj,
8758                                  uint32_t flags)
8759 {
8760         struct drm_i915_private *dev_priv = dev->dev_private;
8761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8762         struct intel_ring_buffer *ring;
8763         uint32_t plane_bit = 0;
8764         int len, ret;
8765
8766         ring = obj->ring;
8767         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8768                 ring = &dev_priv->ring[BCS];
8769
8770         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8771         if (ret)
8772                 goto err;
8773
8774         switch(intel_crtc->plane) {
8775         case PLANE_A:
8776                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8777                 break;
8778         case PLANE_B:
8779                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8780                 break;
8781         case PLANE_C:
8782                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8783                 break;
8784         default:
8785                 WARN_ONCE(1, "unknown plane in flip command\n");
8786                 ret = -ENODEV;
8787                 goto err_unpin;
8788         }
8789
8790         len = 4;
8791         if (ring->id == RCS) {
8792                 len += 6;
8793                 /*
8794                  * On Gen 8, SRM is now taking an extra dword to accommodate
8795                  * 48bits addresses, and we need a NOOP for the batch size to
8796                  * stay even.
8797                  */
8798                 if (IS_GEN8(dev))
8799                         len += 2;
8800         }
8801
8802         /*
8803          * BSpec MI_DISPLAY_FLIP for IVB:
8804          * "The full packet must be contained within the same cache line."
8805          *
8806          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8807          * cacheline, if we ever start emitting more commands before
8808          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8809          * then do the cacheline alignment, and finally emit the
8810          * MI_DISPLAY_FLIP.
8811          */
8812         ret = intel_ring_cacheline_align(ring);
8813         if (ret)
8814                 goto err_unpin;
8815
8816         ret = intel_ring_begin(ring, len);
8817         if (ret)
8818                 goto err_unpin;
8819
8820         /* Unmask the flip-done completion message. Note that the bspec says that
8821          * we should do this for both the BCS and RCS, and that we must not unmask
8822          * more than one flip event at any time (or ensure that one flip message
8823          * can be sent by waiting for flip-done prior to queueing new flips).
8824          * Experimentation says that BCS works despite DERRMR masking all
8825          * flip-done completion events and that unmasking all planes at once
8826          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8827          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8828          */
8829         if (ring->id == RCS) {
8830                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8831                 intel_ring_emit(ring, DERRMR);
8832                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8833                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8834                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8835                 if (IS_GEN8(dev))
8836                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8837                                               MI_SRM_LRM_GLOBAL_GTT);
8838                 else
8839                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8840                                               MI_SRM_LRM_GLOBAL_GTT);
8841                 intel_ring_emit(ring, DERRMR);
8842                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8843                 if (IS_GEN8(dev)) {
8844                         intel_ring_emit(ring, 0);
8845                         intel_ring_emit(ring, MI_NOOP);
8846                 }
8847         }
8848
8849         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8850         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8851         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8852         intel_ring_emit(ring, (MI_NOOP));
8853
8854         intel_mark_page_flip_active(intel_crtc);
8855         __intel_ring_advance(ring);
8856         return 0;
8857
8858 err_unpin:
8859         intel_unpin_fb_obj(obj);
8860 err:
8861         return ret;
8862 }
8863
8864 static int intel_default_queue_flip(struct drm_device *dev,
8865                                     struct drm_crtc *crtc,
8866                                     struct drm_framebuffer *fb,
8867                                     struct drm_i915_gem_object *obj,
8868                                     uint32_t flags)
8869 {
8870         return -ENODEV;
8871 }
8872
8873 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8874                                 struct drm_framebuffer *fb,
8875                                 struct drm_pending_vblank_event *event,
8876                                 uint32_t page_flip_flags)
8877 {
8878         struct drm_device *dev = crtc->dev;
8879         struct drm_i915_private *dev_priv = dev->dev_private;
8880         struct drm_framebuffer *old_fb = crtc->primary->fb;
8881         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883         struct intel_unpin_work *work;
8884         unsigned long flags;
8885         int ret;
8886
8887         /* Can't change pixel format via MI display flips. */
8888         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8889                 return -EINVAL;
8890
8891         /*
8892          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8893          * Note that pitch changes could also affect these register.
8894          */
8895         if (INTEL_INFO(dev)->gen > 3 &&
8896             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8897              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8898                 return -EINVAL;
8899
8900         if (i915_terminally_wedged(&dev_priv->gpu_error))
8901                 goto out_hang;
8902
8903         work = kzalloc(sizeof(*work), GFP_KERNEL);
8904         if (work == NULL)
8905                 return -ENOMEM;
8906
8907         work->event = event;
8908         work->crtc = crtc;
8909         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8910         INIT_WORK(&work->work, intel_unpin_work_fn);
8911
8912         ret = drm_vblank_get(dev, intel_crtc->pipe);
8913         if (ret)
8914                 goto free_work;
8915
8916         /* We borrow the event spin lock for protecting unpin_work */
8917         spin_lock_irqsave(&dev->event_lock, flags);
8918         if (intel_crtc->unpin_work) {
8919                 spin_unlock_irqrestore(&dev->event_lock, flags);
8920                 kfree(work);
8921                 drm_vblank_put(dev, intel_crtc->pipe);
8922
8923                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8924                 return -EBUSY;
8925         }
8926         intel_crtc->unpin_work = work;
8927         spin_unlock_irqrestore(&dev->event_lock, flags);
8928
8929         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8930                 flush_workqueue(dev_priv->wq);
8931
8932         ret = i915_mutex_lock_interruptible(dev);
8933         if (ret)
8934                 goto cleanup;
8935
8936         /* Reference the objects for the scheduled work. */
8937         drm_gem_object_reference(&work->old_fb_obj->base);
8938         drm_gem_object_reference(&obj->base);
8939
8940         crtc->primary->fb = fb;
8941
8942         work->pending_flip_obj = obj;
8943
8944         work->enable_stall_check = true;
8945
8946         atomic_inc(&intel_crtc->unpin_work_count);
8947         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8948
8949         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8950         if (ret)
8951                 goto cleanup_pending;
8952
8953         intel_disable_fbc(dev);
8954         intel_mark_fb_busy(obj, NULL);
8955         mutex_unlock(&dev->struct_mutex);
8956
8957         trace_i915_flip_request(intel_crtc->plane, obj);
8958
8959         return 0;
8960
8961 cleanup_pending:
8962         atomic_dec(&intel_crtc->unpin_work_count);
8963         crtc->primary->fb = old_fb;
8964         drm_gem_object_unreference(&work->old_fb_obj->base);
8965         drm_gem_object_unreference(&obj->base);
8966         mutex_unlock(&dev->struct_mutex);
8967
8968 cleanup:
8969         spin_lock_irqsave(&dev->event_lock, flags);
8970         intel_crtc->unpin_work = NULL;
8971         spin_unlock_irqrestore(&dev->event_lock, flags);
8972
8973         drm_vblank_put(dev, intel_crtc->pipe);
8974 free_work:
8975         kfree(work);
8976
8977         if (ret == -EIO) {
8978 out_hang:
8979                 intel_crtc_wait_for_pending_flips(crtc);
8980                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8981                 if (ret == 0 && event)
8982                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8983         }
8984         return ret;
8985 }
8986
8987 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8988         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8989         .load_lut = intel_crtc_load_lut,
8990 };
8991
8992 /**
8993  * intel_modeset_update_staged_output_state
8994  *
8995  * Updates the staged output configuration state, e.g. after we've read out the
8996  * current hw state.
8997  */
8998 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8999 {
9000         struct intel_crtc *crtc;
9001         struct intel_encoder *encoder;
9002         struct intel_connector *connector;
9003
9004         list_for_each_entry(connector, &dev->mode_config.connector_list,
9005                             base.head) {
9006                 connector->new_encoder =
9007                         to_intel_encoder(connector->base.encoder);
9008         }
9009
9010         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9011                             base.head) {
9012                 encoder->new_crtc =
9013                         to_intel_crtc(encoder->base.crtc);
9014         }
9015
9016         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9017                             base.head) {
9018                 crtc->new_enabled = crtc->base.enabled;
9019
9020                 if (crtc->new_enabled)
9021                         crtc->new_config = &crtc->config;
9022                 else
9023                         crtc->new_config = NULL;
9024         }
9025 }
9026
9027 /**
9028  * intel_modeset_commit_output_state
9029  *
9030  * This function copies the stage display pipe configuration to the real one.
9031  */
9032 static void intel_modeset_commit_output_state(struct drm_device *dev)
9033 {
9034         struct intel_crtc *crtc;
9035         struct intel_encoder *encoder;
9036         struct intel_connector *connector;
9037
9038         list_for_each_entry(connector, &dev->mode_config.connector_list,
9039                             base.head) {
9040                 connector->base.encoder = &connector->new_encoder->base;
9041         }
9042
9043         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9044                             base.head) {
9045                 encoder->base.crtc = &encoder->new_crtc->base;
9046         }
9047
9048         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9049                             base.head) {
9050                 crtc->base.enabled = crtc->new_enabled;
9051         }
9052 }
9053
9054 static void
9055 connected_sink_compute_bpp(struct intel_connector * connector,
9056                            struct intel_crtc_config *pipe_config)
9057 {
9058         int bpp = pipe_config->pipe_bpp;
9059
9060         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9061                 connector->base.base.id,
9062                 drm_get_connector_name(&connector->base));
9063
9064         /* Don't use an invalid EDID bpc value */
9065         if (connector->base.display_info.bpc &&
9066             connector->base.display_info.bpc * 3 < bpp) {
9067                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9068                               bpp, connector->base.display_info.bpc*3);
9069                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9070         }
9071
9072         /* Clamp bpp to 8 on screens without EDID 1.4 */
9073         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9074                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9075                               bpp);
9076                 pipe_config->pipe_bpp = 24;
9077         }
9078 }
9079
9080 static int
9081 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9082                           struct drm_framebuffer *fb,
9083                           struct intel_crtc_config *pipe_config)
9084 {
9085         struct drm_device *dev = crtc->base.dev;
9086         struct intel_connector *connector;
9087         int bpp;
9088
9089         switch (fb->pixel_format) {
9090         case DRM_FORMAT_C8:
9091                 bpp = 8*3; /* since we go through a colormap */
9092                 break;
9093         case DRM_FORMAT_XRGB1555:
9094         case DRM_FORMAT_ARGB1555:
9095                 /* checked in intel_framebuffer_init already */
9096                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9097                         return -EINVAL;
9098         case DRM_FORMAT_RGB565:
9099                 bpp = 6*3; /* min is 18bpp */
9100                 break;
9101         case DRM_FORMAT_XBGR8888:
9102         case DRM_FORMAT_ABGR8888:
9103                 /* checked in intel_framebuffer_init already */
9104                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9105                         return -EINVAL;
9106         case DRM_FORMAT_XRGB8888:
9107         case DRM_FORMAT_ARGB8888:
9108                 bpp = 8*3;
9109                 break;
9110         case DRM_FORMAT_XRGB2101010:
9111         case DRM_FORMAT_ARGB2101010:
9112         case DRM_FORMAT_XBGR2101010:
9113         case DRM_FORMAT_ABGR2101010:
9114                 /* checked in intel_framebuffer_init already */
9115                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9116                         return -EINVAL;
9117                 bpp = 10*3;
9118                 break;
9119         /* TODO: gen4+ supports 16 bpc floating point, too. */
9120         default:
9121                 DRM_DEBUG_KMS("unsupported depth\n");
9122                 return -EINVAL;
9123         }
9124
9125         pipe_config->pipe_bpp = bpp;
9126
9127         /* Clamp display bpp to EDID value */
9128         list_for_each_entry(connector, &dev->mode_config.connector_list,
9129                             base.head) {
9130                 if (!connector->new_encoder ||
9131                     connector->new_encoder->new_crtc != crtc)
9132                         continue;
9133
9134                 connected_sink_compute_bpp(connector, pipe_config);
9135         }
9136
9137         return bpp;
9138 }
9139
9140 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9141 {
9142         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9143                         "type: 0x%x flags: 0x%x\n",
9144                 mode->crtc_clock,
9145                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9146                 mode->crtc_hsync_end, mode->crtc_htotal,
9147                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9148                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9149 }
9150
9151 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9152                                    struct intel_crtc_config *pipe_config,
9153                                    const char *context)
9154 {
9155         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9156                       context, pipe_name(crtc->pipe));
9157
9158         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9159         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9160                       pipe_config->pipe_bpp, pipe_config->dither);
9161         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9162                       pipe_config->has_pch_encoder,
9163                       pipe_config->fdi_lanes,
9164                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9165                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9166                       pipe_config->fdi_m_n.tu);
9167         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9168                       pipe_config->has_dp_encoder,
9169                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9170                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9171                       pipe_config->dp_m_n.tu);
9172         DRM_DEBUG_KMS("requested mode:\n");
9173         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9174         DRM_DEBUG_KMS("adjusted mode:\n");
9175         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9176         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9177         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9178         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9179                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9180         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9181                       pipe_config->gmch_pfit.control,
9182                       pipe_config->gmch_pfit.pgm_ratios,
9183                       pipe_config->gmch_pfit.lvds_border_bits);
9184         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9185                       pipe_config->pch_pfit.pos,
9186                       pipe_config->pch_pfit.size,
9187                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9188         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9189         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9190 }
9191
9192 static bool encoders_cloneable(const struct intel_encoder *a,
9193                                const struct intel_encoder *b)
9194 {
9195         /* masks could be asymmetric, so check both ways */
9196         return a == b || (a->cloneable & (1 << b->type) &&
9197                           b->cloneable & (1 << a->type));
9198 }
9199
9200 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9201                                          struct intel_encoder *encoder)
9202 {
9203         struct drm_device *dev = crtc->base.dev;
9204         struct intel_encoder *source_encoder;
9205
9206         list_for_each_entry(source_encoder,
9207                             &dev->mode_config.encoder_list, base.head) {
9208                 if (source_encoder->new_crtc != crtc)
9209                         continue;
9210
9211                 if (!encoders_cloneable(encoder, source_encoder))
9212                         return false;
9213         }
9214
9215         return true;
9216 }
9217
9218 static bool check_encoder_cloning(struct intel_crtc *crtc)
9219 {
9220         struct drm_device *dev = crtc->base.dev;
9221         struct intel_encoder *encoder;
9222
9223         list_for_each_entry(encoder,
9224                             &dev->mode_config.encoder_list, base.head) {
9225                 if (encoder->new_crtc != crtc)
9226                         continue;
9227
9228                 if (!check_single_encoder_cloning(crtc, encoder))
9229                         return false;
9230         }
9231
9232         return true;
9233 }
9234
9235 static struct intel_crtc_config *
9236 intel_modeset_pipe_config(struct drm_crtc *crtc,
9237                           struct drm_framebuffer *fb,
9238                           struct drm_display_mode *mode)
9239 {
9240         struct drm_device *dev = crtc->dev;
9241         struct intel_encoder *encoder;
9242         struct intel_crtc_config *pipe_config;
9243         int plane_bpp, ret = -EINVAL;
9244         bool retry = true;
9245
9246         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9247                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9248                 return ERR_PTR(-EINVAL);
9249         }
9250
9251         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9252         if (!pipe_config)
9253                 return ERR_PTR(-ENOMEM);
9254
9255         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9256         drm_mode_copy(&pipe_config->requested_mode, mode);
9257
9258         pipe_config->cpu_transcoder =
9259                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9260         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9261
9262         /*
9263          * Sanitize sync polarity flags based on requested ones. If neither
9264          * positive or negative polarity is requested, treat this as meaning
9265          * negative polarity.
9266          */
9267         if (!(pipe_config->adjusted_mode.flags &
9268               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9269                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9270
9271         if (!(pipe_config->adjusted_mode.flags &
9272               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9273                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9274
9275         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9276          * plane pixel format and any sink constraints into account. Returns the
9277          * source plane bpp so that dithering can be selected on mismatches
9278          * after encoders and crtc also have had their say. */
9279         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9280                                               fb, pipe_config);
9281         if (plane_bpp < 0)
9282                 goto fail;
9283
9284         /*
9285          * Determine the real pipe dimensions. Note that stereo modes can
9286          * increase the actual pipe size due to the frame doubling and
9287          * insertion of additional space for blanks between the frame. This
9288          * is stored in the crtc timings. We use the requested mode to do this
9289          * computation to clearly distinguish it from the adjusted mode, which
9290          * can be changed by the connectors in the below retry loop.
9291          */
9292         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9293         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9294         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9295
9296 encoder_retry:
9297         /* Ensure the port clock defaults are reset when retrying. */
9298         pipe_config->port_clock = 0;
9299         pipe_config->pixel_multiplier = 1;
9300
9301         /* Fill in default crtc timings, allow encoders to overwrite them. */
9302         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9303
9304         /* Pass our mode to the connectors and the CRTC to give them a chance to
9305          * adjust it according to limitations or connector properties, and also
9306          * a chance to reject the mode entirely.
9307          */
9308         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9309                             base.head) {
9310
9311                 if (&encoder->new_crtc->base != crtc)
9312                         continue;
9313
9314                 if (!(encoder->compute_config(encoder, pipe_config))) {
9315                         DRM_DEBUG_KMS("Encoder config failure\n");
9316                         goto fail;
9317                 }
9318         }
9319
9320         /* Set default port clock if not overwritten by the encoder. Needs to be
9321          * done afterwards in case the encoder adjusts the mode. */
9322         if (!pipe_config->port_clock)
9323                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9324                         * pipe_config->pixel_multiplier;
9325
9326         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9327         if (ret < 0) {
9328                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9329                 goto fail;
9330         }
9331
9332         if (ret == RETRY) {
9333                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9334                         ret = -EINVAL;
9335                         goto fail;
9336                 }
9337
9338                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9339                 retry = false;
9340                 goto encoder_retry;
9341         }
9342
9343         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9344         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9345                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9346
9347         return pipe_config;
9348 fail:
9349         kfree(pipe_config);
9350         return ERR_PTR(ret);
9351 }
9352
9353 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9354  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9355 static void
9356 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9357                              unsigned *prepare_pipes, unsigned *disable_pipes)
9358 {
9359         struct intel_crtc *intel_crtc;
9360         struct drm_device *dev = crtc->dev;
9361         struct intel_encoder *encoder;
9362         struct intel_connector *connector;
9363         struct drm_crtc *tmp_crtc;
9364
9365         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9366
9367         /* Check which crtcs have changed outputs connected to them, these need
9368          * to be part of the prepare_pipes mask. We don't (yet) support global
9369          * modeset across multiple crtcs, so modeset_pipes will only have one
9370          * bit set at most. */
9371         list_for_each_entry(connector, &dev->mode_config.connector_list,
9372                             base.head) {
9373                 if (connector->base.encoder == &connector->new_encoder->base)
9374                         continue;
9375
9376                 if (connector->base.encoder) {
9377                         tmp_crtc = connector->base.encoder->crtc;
9378
9379                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9380                 }
9381
9382                 if (connector->new_encoder)
9383                         *prepare_pipes |=
9384                                 1 << connector->new_encoder->new_crtc->pipe;
9385         }
9386
9387         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9388                             base.head) {
9389                 if (encoder->base.crtc == &encoder->new_crtc->base)
9390                         continue;
9391
9392                 if (encoder->base.crtc) {
9393                         tmp_crtc = encoder->base.crtc;
9394
9395                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9396                 }
9397
9398                 if (encoder->new_crtc)
9399                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9400         }
9401
9402         /* Check for pipes that will be enabled/disabled ... */
9403         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9404                             base.head) {
9405                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9406                         continue;
9407
9408                 if (!intel_crtc->new_enabled)
9409                         *disable_pipes |= 1 << intel_crtc->pipe;
9410                 else
9411                         *prepare_pipes |= 1 << intel_crtc->pipe;
9412         }
9413
9414
9415         /* set_mode is also used to update properties on life display pipes. */
9416         intel_crtc = to_intel_crtc(crtc);
9417         if (intel_crtc->new_enabled)
9418                 *prepare_pipes |= 1 << intel_crtc->pipe;
9419
9420         /*
9421          * For simplicity do a full modeset on any pipe where the output routing
9422          * changed. We could be more clever, but that would require us to be
9423          * more careful with calling the relevant encoder->mode_set functions.
9424          */
9425         if (*prepare_pipes)
9426                 *modeset_pipes = *prepare_pipes;
9427
9428         /* ... and mask these out. */
9429         *modeset_pipes &= ~(*disable_pipes);
9430         *prepare_pipes &= ~(*disable_pipes);
9431
9432         /*
9433          * HACK: We don't (yet) fully support global modesets. intel_set_config
9434          * obies this rule, but the modeset restore mode of
9435          * intel_modeset_setup_hw_state does not.
9436          */
9437         *modeset_pipes &= 1 << intel_crtc->pipe;
9438         *prepare_pipes &= 1 << intel_crtc->pipe;
9439
9440         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9441                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9442 }
9443
9444 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9445 {
9446         struct drm_encoder *encoder;
9447         struct drm_device *dev = crtc->dev;
9448
9449         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9450                 if (encoder->crtc == crtc)
9451                         return true;
9452
9453         return false;
9454 }
9455
9456 static void
9457 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9458 {
9459         struct intel_encoder *intel_encoder;
9460         struct intel_crtc *intel_crtc;
9461         struct drm_connector *connector;
9462
9463         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9464                             base.head) {
9465                 if (!intel_encoder->base.crtc)
9466                         continue;
9467
9468                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9469
9470                 if (prepare_pipes & (1 << intel_crtc->pipe))
9471                         intel_encoder->connectors_active = false;
9472         }
9473
9474         intel_modeset_commit_output_state(dev);
9475
9476         /* Double check state. */
9477         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9478                             base.head) {
9479                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9480                 WARN_ON(intel_crtc->new_config &&
9481                         intel_crtc->new_config != &intel_crtc->config);
9482                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9483         }
9484
9485         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9486                 if (!connector->encoder || !connector->encoder->crtc)
9487                         continue;
9488
9489                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9490
9491                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9492                         struct drm_property *dpms_property =
9493                                 dev->mode_config.dpms_property;
9494
9495                         connector->dpms = DRM_MODE_DPMS_ON;
9496                         drm_object_property_set_value(&connector->base,
9497                                                          dpms_property,
9498                                                          DRM_MODE_DPMS_ON);
9499
9500                         intel_encoder = to_intel_encoder(connector->encoder);
9501                         intel_encoder->connectors_active = true;
9502                 }
9503         }
9504
9505 }
9506
9507 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9508 {
9509         int diff;
9510
9511         if (clock1 == clock2)
9512                 return true;
9513
9514         if (!clock1 || !clock2)
9515                 return false;
9516
9517         diff = abs(clock1 - clock2);
9518
9519         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9520                 return true;
9521
9522         return false;
9523 }
9524
9525 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9526         list_for_each_entry((intel_crtc), \
9527                             &(dev)->mode_config.crtc_list, \
9528                             base.head) \
9529                 if (mask & (1 <<(intel_crtc)->pipe))
9530
9531 static bool
9532 intel_pipe_config_compare(struct drm_device *dev,
9533                           struct intel_crtc_config *current_config,
9534                           struct intel_crtc_config *pipe_config)
9535 {
9536 #define PIPE_CONF_CHECK_X(name) \
9537         if (current_config->name != pipe_config->name) { \
9538                 DRM_ERROR("mismatch in " #name " " \
9539                           "(expected 0x%08x, found 0x%08x)\n", \
9540                           current_config->name, \
9541                           pipe_config->name); \
9542                 return false; \
9543         }
9544
9545 #define PIPE_CONF_CHECK_I(name) \
9546         if (current_config->name != pipe_config->name) { \
9547                 DRM_ERROR("mismatch in " #name " " \
9548                           "(expected %i, found %i)\n", \
9549                           current_config->name, \
9550                           pipe_config->name); \
9551                 return false; \
9552         }
9553
9554 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9555         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9556                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9557                           "(expected %i, found %i)\n", \
9558                           current_config->name & (mask), \
9559                           pipe_config->name & (mask)); \
9560                 return false; \
9561         }
9562
9563 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9564         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9565                 DRM_ERROR("mismatch in " #name " " \
9566                           "(expected %i, found %i)\n", \
9567                           current_config->name, \
9568                           pipe_config->name); \
9569                 return false; \
9570         }
9571
9572 #define PIPE_CONF_QUIRK(quirk)  \
9573         ((current_config->quirks | pipe_config->quirks) & (quirk))
9574
9575         PIPE_CONF_CHECK_I(cpu_transcoder);
9576
9577         PIPE_CONF_CHECK_I(has_pch_encoder);
9578         PIPE_CONF_CHECK_I(fdi_lanes);
9579         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9580         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9581         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9582         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9583         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9584
9585         PIPE_CONF_CHECK_I(has_dp_encoder);
9586         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9587         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9588         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9589         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9590         PIPE_CONF_CHECK_I(dp_m_n.tu);
9591
9592         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9593         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9594         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9595         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9596         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9597         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9598
9599         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9600         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9601         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9602         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9603         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9604         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9605
9606         PIPE_CONF_CHECK_I(pixel_multiplier);
9607
9608         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9609                               DRM_MODE_FLAG_INTERLACE);
9610
9611         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9612                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9613                                       DRM_MODE_FLAG_PHSYNC);
9614                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9615                                       DRM_MODE_FLAG_NHSYNC);
9616                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9617                                       DRM_MODE_FLAG_PVSYNC);
9618                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9619                                       DRM_MODE_FLAG_NVSYNC);
9620         }
9621
9622         PIPE_CONF_CHECK_I(pipe_src_w);
9623         PIPE_CONF_CHECK_I(pipe_src_h);
9624
9625         /*
9626          * FIXME: BIOS likes to set up a cloned config with lvds+external
9627          * screen. Since we don't yet re-compute the pipe config when moving
9628          * just the lvds port away to another pipe the sw tracking won't match.
9629          *
9630          * Proper atomic modesets with recomputed global state will fix this.
9631          * Until then just don't check gmch state for inherited modes.
9632          */
9633         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9634                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9635                 /* pfit ratios are autocomputed by the hw on gen4+ */
9636                 if (INTEL_INFO(dev)->gen < 4)
9637                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9638                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9639         }
9640
9641         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9642         if (current_config->pch_pfit.enabled) {
9643                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9644                 PIPE_CONF_CHECK_I(pch_pfit.size);
9645         }
9646
9647         /* BDW+ don't expose a synchronous way to read the state */
9648         if (IS_HASWELL(dev))
9649                 PIPE_CONF_CHECK_I(ips_enabled);
9650
9651         PIPE_CONF_CHECK_I(double_wide);
9652
9653         PIPE_CONF_CHECK_I(shared_dpll);
9654         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9655         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9656         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9657         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9658
9659         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9660                 PIPE_CONF_CHECK_I(pipe_bpp);
9661
9662         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9663         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9664
9665 #undef PIPE_CONF_CHECK_X
9666 #undef PIPE_CONF_CHECK_I
9667 #undef PIPE_CONF_CHECK_FLAGS
9668 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9669 #undef PIPE_CONF_QUIRK
9670
9671         return true;
9672 }
9673
9674 static void
9675 check_connector_state(struct drm_device *dev)
9676 {
9677         struct intel_connector *connector;
9678
9679         list_for_each_entry(connector, &dev->mode_config.connector_list,
9680                             base.head) {
9681                 /* This also checks the encoder/connector hw state with the
9682                  * ->get_hw_state callbacks. */
9683                 intel_connector_check_state(connector);
9684
9685                 WARN(&connector->new_encoder->base != connector->base.encoder,
9686                      "connector's staged encoder doesn't match current encoder\n");
9687         }
9688 }
9689
9690 static void
9691 check_encoder_state(struct drm_device *dev)
9692 {
9693         struct intel_encoder *encoder;
9694         struct intel_connector *connector;
9695
9696         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9697                             base.head) {
9698                 bool enabled = false;
9699                 bool active = false;
9700                 enum pipe pipe, tracked_pipe;
9701
9702                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9703                               encoder->base.base.id,
9704                               drm_get_encoder_name(&encoder->base));
9705
9706                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9707                      "encoder's stage crtc doesn't match current crtc\n");
9708                 WARN(encoder->connectors_active && !encoder->base.crtc,
9709                      "encoder's active_connectors set, but no crtc\n");
9710
9711                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9712                                     base.head) {
9713                         if (connector->base.encoder != &encoder->base)
9714                                 continue;
9715                         enabled = true;
9716                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9717                                 active = true;
9718                 }
9719                 WARN(!!encoder->base.crtc != enabled,
9720                      "encoder's enabled state mismatch "
9721                      "(expected %i, found %i)\n",
9722                      !!encoder->base.crtc, enabled);
9723                 WARN(active && !encoder->base.crtc,
9724                      "active encoder with no crtc\n");
9725
9726                 WARN(encoder->connectors_active != active,
9727                      "encoder's computed active state doesn't match tracked active state "
9728                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9729
9730                 active = encoder->get_hw_state(encoder, &pipe);
9731                 WARN(active != encoder->connectors_active,
9732                      "encoder's hw state doesn't match sw tracking "
9733                      "(expected %i, found %i)\n",
9734                      encoder->connectors_active, active);
9735
9736                 if (!encoder->base.crtc)
9737                         continue;
9738
9739                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9740                 WARN(active && pipe != tracked_pipe,
9741                      "active encoder's pipe doesn't match"
9742                      "(expected %i, found %i)\n",
9743                      tracked_pipe, pipe);
9744
9745         }
9746 }
9747
9748 static void
9749 check_crtc_state(struct drm_device *dev)
9750 {
9751         struct drm_i915_private *dev_priv = dev->dev_private;
9752         struct intel_crtc *crtc;
9753         struct intel_encoder *encoder;
9754         struct intel_crtc_config pipe_config;
9755
9756         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9757                             base.head) {
9758                 bool enabled = false;
9759                 bool active = false;
9760
9761                 memset(&pipe_config, 0, sizeof(pipe_config));
9762
9763                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9764                               crtc->base.base.id);
9765
9766                 WARN(crtc->active && !crtc->base.enabled,
9767                      "active crtc, but not enabled in sw tracking\n");
9768
9769                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9770                                     base.head) {
9771                         if (encoder->base.crtc != &crtc->base)
9772                                 continue;
9773                         enabled = true;
9774                         if (encoder->connectors_active)
9775                                 active = true;
9776                 }
9777
9778                 WARN(active != crtc->active,
9779                      "crtc's computed active state doesn't match tracked active state "
9780                      "(expected %i, found %i)\n", active, crtc->active);
9781                 WARN(enabled != crtc->base.enabled,
9782                      "crtc's computed enabled state doesn't match tracked enabled state "
9783                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9784
9785                 active = dev_priv->display.get_pipe_config(crtc,
9786                                                            &pipe_config);
9787
9788                 /* hw state is inconsistent with the pipe A quirk */
9789                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9790                         active = crtc->active;
9791
9792                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9793                                     base.head) {
9794                         enum pipe pipe;
9795                         if (encoder->base.crtc != &crtc->base)
9796                                 continue;
9797                         if (encoder->get_hw_state(encoder, &pipe))
9798                                 encoder->get_config(encoder, &pipe_config);
9799                 }
9800
9801                 WARN(crtc->active != active,
9802                      "crtc active state doesn't match with hw state "
9803                      "(expected %i, found %i)\n", crtc->active, active);
9804
9805                 if (active &&
9806                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9807                         WARN(1, "pipe state doesn't match!\n");
9808                         intel_dump_pipe_config(crtc, &pipe_config,
9809                                                "[hw state]");
9810                         intel_dump_pipe_config(crtc, &crtc->config,
9811                                                "[sw state]");
9812                 }
9813         }
9814 }
9815
9816 static void
9817 check_shared_dpll_state(struct drm_device *dev)
9818 {
9819         struct drm_i915_private *dev_priv = dev->dev_private;
9820         struct intel_crtc *crtc;
9821         struct intel_dpll_hw_state dpll_hw_state;
9822         int i;
9823
9824         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9825                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9826                 int enabled_crtcs = 0, active_crtcs = 0;
9827                 bool active;
9828
9829                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9830
9831                 DRM_DEBUG_KMS("%s\n", pll->name);
9832
9833                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9834
9835                 WARN(pll->active > pll->refcount,
9836                      "more active pll users than references: %i vs %i\n",
9837                      pll->active, pll->refcount);
9838                 WARN(pll->active && !pll->on,
9839                      "pll in active use but not on in sw tracking\n");
9840                 WARN(pll->on && !pll->active,
9841                      "pll in on but not on in use in sw tracking\n");
9842                 WARN(pll->on != active,
9843                      "pll on state mismatch (expected %i, found %i)\n",
9844                      pll->on, active);
9845
9846                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9847                                     base.head) {
9848                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9849                                 enabled_crtcs++;
9850                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9851                                 active_crtcs++;
9852                 }
9853                 WARN(pll->active != active_crtcs,
9854                      "pll active crtcs mismatch (expected %i, found %i)\n",
9855                      pll->active, active_crtcs);
9856                 WARN(pll->refcount != enabled_crtcs,
9857                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9858                      pll->refcount, enabled_crtcs);
9859
9860                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9861                                        sizeof(dpll_hw_state)),
9862                      "pll hw state mismatch\n");
9863         }
9864 }
9865
9866 void
9867 intel_modeset_check_state(struct drm_device *dev)
9868 {
9869         check_connector_state(dev);
9870         check_encoder_state(dev);
9871         check_crtc_state(dev);
9872         check_shared_dpll_state(dev);
9873 }
9874
9875 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9876                                      int dotclock)
9877 {
9878         /*
9879          * FDI already provided one idea for the dotclock.
9880          * Yell if the encoder disagrees.
9881          */
9882         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9883              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9884              pipe_config->adjusted_mode.crtc_clock, dotclock);
9885 }
9886
9887 static int __intel_set_mode(struct drm_crtc *crtc,
9888                             struct drm_display_mode *mode,
9889                             int x, int y, struct drm_framebuffer *fb)
9890 {
9891         struct drm_device *dev = crtc->dev;
9892         struct drm_i915_private *dev_priv = dev->dev_private;
9893         struct drm_display_mode *saved_mode;
9894         struct intel_crtc_config *pipe_config = NULL;
9895         struct intel_crtc *intel_crtc;
9896         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9897         int ret = 0;
9898
9899         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9900         if (!saved_mode)
9901                 return -ENOMEM;
9902
9903         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9904                                      &prepare_pipes, &disable_pipes);
9905
9906         *saved_mode = crtc->mode;
9907
9908         /* Hack: Because we don't (yet) support global modeset on multiple
9909          * crtcs, we don't keep track of the new mode for more than one crtc.
9910          * Hence simply check whether any bit is set in modeset_pipes in all the
9911          * pieces of code that are not yet converted to deal with mutliple crtcs
9912          * changing their mode at the same time. */
9913         if (modeset_pipes) {
9914                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9915                 if (IS_ERR(pipe_config)) {
9916                         ret = PTR_ERR(pipe_config);
9917                         pipe_config = NULL;
9918
9919                         goto out;
9920                 }
9921                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9922                                        "[modeset]");
9923                 to_intel_crtc(crtc)->new_config = pipe_config;
9924         }
9925
9926         /*
9927          * See if the config requires any additional preparation, e.g.
9928          * to adjust global state with pipes off.  We need to do this
9929          * here so we can get the modeset_pipe updated config for the new
9930          * mode set on this crtc.  For other crtcs we need to use the
9931          * adjusted_mode bits in the crtc directly.
9932          */
9933         if (IS_VALLEYVIEW(dev)) {
9934                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9935
9936                 /* may have added more to prepare_pipes than we should */
9937                 prepare_pipes &= ~disable_pipes;
9938         }
9939
9940         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9941                 intel_crtc_disable(&intel_crtc->base);
9942
9943         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9944                 if (intel_crtc->base.enabled)
9945                         dev_priv->display.crtc_disable(&intel_crtc->base);
9946         }
9947
9948         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9949          * to set it here already despite that we pass it down the callchain.
9950          */
9951         if (modeset_pipes) {
9952                 crtc->mode = *mode;
9953                 /* mode_set/enable/disable functions rely on a correct pipe
9954                  * config. */
9955                 to_intel_crtc(crtc)->config = *pipe_config;
9956                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9957
9958                 /*
9959                  * Calculate and store various constants which
9960                  * are later needed by vblank and swap-completion
9961                  * timestamping. They are derived from true hwmode.
9962                  */
9963                 drm_calc_timestamping_constants(crtc,
9964                                                 &pipe_config->adjusted_mode);
9965         }
9966
9967         /* Only after disabling all output pipelines that will be changed can we
9968          * update the the output configuration. */
9969         intel_modeset_update_state(dev, prepare_pipes);
9970
9971         if (dev_priv->display.modeset_global_resources)
9972                 dev_priv->display.modeset_global_resources(dev);
9973
9974         /* Set up the DPLL and any encoders state that needs to adjust or depend
9975          * on the DPLL.
9976          */
9977         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9978                 ret = intel_crtc_mode_set(&intel_crtc->base,
9979                                           x, y, fb);
9980                 if (ret)
9981                         goto done;
9982         }
9983
9984         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9985         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9986                 dev_priv->display.crtc_enable(&intel_crtc->base);
9987
9988         /* FIXME: add subpixel order */
9989 done:
9990         if (ret && crtc->enabled)
9991                 crtc->mode = *saved_mode;
9992
9993 out:
9994         kfree(pipe_config);
9995         kfree(saved_mode);
9996         return ret;
9997 }
9998
9999 static int intel_set_mode(struct drm_crtc *crtc,
10000                           struct drm_display_mode *mode,
10001                           int x, int y, struct drm_framebuffer *fb)
10002 {
10003         int ret;
10004
10005         ret = __intel_set_mode(crtc, mode, x, y, fb);
10006
10007         if (ret == 0)
10008                 intel_modeset_check_state(crtc->dev);
10009
10010         return ret;
10011 }
10012
10013 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10014 {
10015         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10016 }
10017
10018 #undef for_each_intel_crtc_masked
10019
10020 static void intel_set_config_free(struct intel_set_config *config)
10021 {
10022         if (!config)
10023                 return;
10024
10025         kfree(config->save_connector_encoders);
10026         kfree(config->save_encoder_crtcs);
10027         kfree(config->save_crtc_enabled);
10028         kfree(config);
10029 }
10030
10031 static int intel_set_config_save_state(struct drm_device *dev,
10032                                        struct intel_set_config *config)
10033 {
10034         struct drm_crtc *crtc;
10035         struct drm_encoder *encoder;
10036         struct drm_connector *connector;
10037         int count;
10038
10039         config->save_crtc_enabled =
10040                 kcalloc(dev->mode_config.num_crtc,
10041                         sizeof(bool), GFP_KERNEL);
10042         if (!config->save_crtc_enabled)
10043                 return -ENOMEM;
10044
10045         config->save_encoder_crtcs =
10046                 kcalloc(dev->mode_config.num_encoder,
10047                         sizeof(struct drm_crtc *), GFP_KERNEL);
10048         if (!config->save_encoder_crtcs)
10049                 return -ENOMEM;
10050
10051         config->save_connector_encoders =
10052                 kcalloc(dev->mode_config.num_connector,
10053                         sizeof(struct drm_encoder *), GFP_KERNEL);
10054         if (!config->save_connector_encoders)
10055                 return -ENOMEM;
10056
10057         /* Copy data. Note that driver private data is not affected.
10058          * Should anything bad happen only the expected state is
10059          * restored, not the drivers personal bookkeeping.
10060          */
10061         count = 0;
10062         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10063                 config->save_crtc_enabled[count++] = crtc->enabled;
10064         }
10065
10066         count = 0;
10067         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10068                 config->save_encoder_crtcs[count++] = encoder->crtc;
10069         }
10070
10071         count = 0;
10072         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10073                 config->save_connector_encoders[count++] = connector->encoder;
10074         }
10075
10076         return 0;
10077 }
10078
10079 static void intel_set_config_restore_state(struct drm_device *dev,
10080                                            struct intel_set_config *config)
10081 {
10082         struct intel_crtc *crtc;
10083         struct intel_encoder *encoder;
10084         struct intel_connector *connector;
10085         int count;
10086
10087         count = 0;
10088         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10089                 crtc->new_enabled = config->save_crtc_enabled[count++];
10090
10091                 if (crtc->new_enabled)
10092                         crtc->new_config = &crtc->config;
10093                 else
10094                         crtc->new_config = NULL;
10095         }
10096
10097         count = 0;
10098         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10099                 encoder->new_crtc =
10100                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10101         }
10102
10103         count = 0;
10104         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10105                 connector->new_encoder =
10106                         to_intel_encoder(config->save_connector_encoders[count++]);
10107         }
10108 }
10109
10110 static bool
10111 is_crtc_connector_off(struct drm_mode_set *set)
10112 {
10113         int i;
10114
10115         if (set->num_connectors == 0)
10116                 return false;
10117
10118         if (WARN_ON(set->connectors == NULL))
10119                 return false;
10120
10121         for (i = 0; i < set->num_connectors; i++)
10122                 if (set->connectors[i]->encoder &&
10123                     set->connectors[i]->encoder->crtc == set->crtc &&
10124                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10125                         return true;
10126
10127         return false;
10128 }
10129
10130 static void
10131 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10132                                       struct intel_set_config *config)
10133 {
10134
10135         /* We should be able to check here if the fb has the same properties
10136          * and then just flip_or_move it */
10137         if (is_crtc_connector_off(set)) {
10138                 config->mode_changed = true;
10139         } else if (set->crtc->primary->fb != set->fb) {
10140                 /* If we have no fb then treat it as a full mode set */
10141                 if (set->crtc->primary->fb == NULL) {
10142                         struct intel_crtc *intel_crtc =
10143                                 to_intel_crtc(set->crtc);
10144
10145                         if (intel_crtc->active && i915.fastboot) {
10146                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10147                                 config->fb_changed = true;
10148                         } else {
10149                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10150                                 config->mode_changed = true;
10151                         }
10152                 } else if (set->fb == NULL) {
10153                         config->mode_changed = true;
10154                 } else if (set->fb->pixel_format !=
10155                            set->crtc->primary->fb->pixel_format) {
10156                         config->mode_changed = true;
10157                 } else {
10158                         config->fb_changed = true;
10159                 }
10160         }
10161
10162         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10163                 config->fb_changed = true;
10164
10165         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10166                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10167                 drm_mode_debug_printmodeline(&set->crtc->mode);
10168                 drm_mode_debug_printmodeline(set->mode);
10169                 config->mode_changed = true;
10170         }
10171
10172         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10173                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10174 }
10175
10176 static int
10177 intel_modeset_stage_output_state(struct drm_device *dev,
10178                                  struct drm_mode_set *set,
10179                                  struct intel_set_config *config)
10180 {
10181         struct intel_connector *connector;
10182         struct intel_encoder *encoder;
10183         struct intel_crtc *crtc;
10184         int ro;
10185
10186         /* The upper layers ensure that we either disable a crtc or have a list
10187          * of connectors. For paranoia, double-check this. */
10188         WARN_ON(!set->fb && (set->num_connectors != 0));
10189         WARN_ON(set->fb && (set->num_connectors == 0));
10190
10191         list_for_each_entry(connector, &dev->mode_config.connector_list,
10192                             base.head) {
10193                 /* Otherwise traverse passed in connector list and get encoders
10194                  * for them. */
10195                 for (ro = 0; ro < set->num_connectors; ro++) {
10196                         if (set->connectors[ro] == &connector->base) {
10197                                 connector->new_encoder = connector->encoder;
10198                                 break;
10199                         }
10200                 }
10201
10202                 /* If we disable the crtc, disable all its connectors. Also, if
10203                  * the connector is on the changing crtc but not on the new
10204                  * connector list, disable it. */
10205                 if ((!set->fb || ro == set->num_connectors) &&
10206                     connector->base.encoder &&
10207                     connector->base.encoder->crtc == set->crtc) {
10208                         connector->new_encoder = NULL;
10209
10210                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10211                                 connector->base.base.id,
10212                                 drm_get_connector_name(&connector->base));
10213                 }
10214
10215
10216                 if (&connector->new_encoder->base != connector->base.encoder) {
10217                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10218                         config->mode_changed = true;
10219                 }
10220         }
10221         /* connector->new_encoder is now updated for all connectors. */
10222
10223         /* Update crtc of enabled connectors. */
10224         list_for_each_entry(connector, &dev->mode_config.connector_list,
10225                             base.head) {
10226                 struct drm_crtc *new_crtc;
10227
10228                 if (!connector->new_encoder)
10229                         continue;
10230
10231                 new_crtc = connector->new_encoder->base.crtc;
10232
10233                 for (ro = 0; ro < set->num_connectors; ro++) {
10234                         if (set->connectors[ro] == &connector->base)
10235                                 new_crtc = set->crtc;
10236                 }
10237
10238                 /* Make sure the new CRTC will work with the encoder */
10239                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10240                                          new_crtc)) {
10241                         return -EINVAL;
10242                 }
10243                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10244
10245                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10246                         connector->base.base.id,
10247                         drm_get_connector_name(&connector->base),
10248                         new_crtc->base.id);
10249         }
10250
10251         /* Check for any encoders that needs to be disabled. */
10252         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10253                             base.head) {
10254                 int num_connectors = 0;
10255                 list_for_each_entry(connector,
10256                                     &dev->mode_config.connector_list,
10257                                     base.head) {
10258                         if (connector->new_encoder == encoder) {
10259                                 WARN_ON(!connector->new_encoder->new_crtc);
10260                                 num_connectors++;
10261                         }
10262                 }
10263
10264                 if (num_connectors == 0)
10265                         encoder->new_crtc = NULL;
10266                 else if (num_connectors > 1)
10267                         return -EINVAL;
10268
10269                 /* Only now check for crtc changes so we don't miss encoders
10270                  * that will be disabled. */
10271                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10272                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10273                         config->mode_changed = true;
10274                 }
10275         }
10276         /* Now we've also updated encoder->new_crtc for all encoders. */
10277
10278         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10279                             base.head) {
10280                 crtc->new_enabled = false;
10281
10282                 list_for_each_entry(encoder,
10283                                     &dev->mode_config.encoder_list,
10284                                     base.head) {
10285                         if (encoder->new_crtc == crtc) {
10286                                 crtc->new_enabled = true;
10287                                 break;
10288                         }
10289                 }
10290
10291                 if (crtc->new_enabled != crtc->base.enabled) {
10292                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10293                                       crtc->new_enabled ? "en" : "dis");
10294                         config->mode_changed = true;
10295                 }
10296
10297                 if (crtc->new_enabled)
10298                         crtc->new_config = &crtc->config;
10299                 else
10300                         crtc->new_config = NULL;
10301         }
10302
10303         return 0;
10304 }
10305
10306 static void disable_crtc_nofb(struct intel_crtc *crtc)
10307 {
10308         struct drm_device *dev = crtc->base.dev;
10309         struct intel_encoder *encoder;
10310         struct intel_connector *connector;
10311
10312         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10313                       pipe_name(crtc->pipe));
10314
10315         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10316                 if (connector->new_encoder &&
10317                     connector->new_encoder->new_crtc == crtc)
10318                         connector->new_encoder = NULL;
10319         }
10320
10321         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10322                 if (encoder->new_crtc == crtc)
10323                         encoder->new_crtc = NULL;
10324         }
10325
10326         crtc->new_enabled = false;
10327         crtc->new_config = NULL;
10328 }
10329
10330 static int intel_crtc_set_config(struct drm_mode_set *set)
10331 {
10332         struct drm_device *dev;
10333         struct drm_mode_set save_set;
10334         struct intel_set_config *config;
10335         int ret;
10336
10337         BUG_ON(!set);
10338         BUG_ON(!set->crtc);
10339         BUG_ON(!set->crtc->helper_private);
10340
10341         /* Enforce sane interface api - has been abused by the fb helper. */
10342         BUG_ON(!set->mode && set->fb);
10343         BUG_ON(set->fb && set->num_connectors == 0);
10344
10345         if (set->fb) {
10346                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10347                                 set->crtc->base.id, set->fb->base.id,
10348                                 (int)set->num_connectors, set->x, set->y);
10349         } else {
10350                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10351         }
10352
10353         dev = set->crtc->dev;
10354
10355         ret = -ENOMEM;
10356         config = kzalloc(sizeof(*config), GFP_KERNEL);
10357         if (!config)
10358                 goto out_config;
10359
10360         ret = intel_set_config_save_state(dev, config);
10361         if (ret)
10362                 goto out_config;
10363
10364         save_set.crtc = set->crtc;
10365         save_set.mode = &set->crtc->mode;
10366         save_set.x = set->crtc->x;
10367         save_set.y = set->crtc->y;
10368         save_set.fb = set->crtc->primary->fb;
10369
10370         /* Compute whether we need a full modeset, only an fb base update or no
10371          * change at all. In the future we might also check whether only the
10372          * mode changed, e.g. for LVDS where we only change the panel fitter in
10373          * such cases. */
10374         intel_set_config_compute_mode_changes(set, config);
10375
10376         ret = intel_modeset_stage_output_state(dev, set, config);
10377         if (ret)
10378                 goto fail;
10379
10380         if (config->mode_changed) {
10381                 ret = intel_set_mode(set->crtc, set->mode,
10382                                      set->x, set->y, set->fb);
10383         } else if (config->fb_changed) {
10384                 intel_crtc_wait_for_pending_flips(set->crtc);
10385
10386                 ret = intel_pipe_set_base(set->crtc,
10387                                           set->x, set->y, set->fb);
10388                 /*
10389                  * In the fastboot case this may be our only check of the
10390                  * state after boot.  It would be better to only do it on
10391                  * the first update, but we don't have a nice way of doing that
10392                  * (and really, set_config isn't used much for high freq page
10393                  * flipping, so increasing its cost here shouldn't be a big
10394                  * deal).
10395                  */
10396                 if (i915.fastboot && ret == 0)
10397                         intel_modeset_check_state(set->crtc->dev);
10398         }
10399
10400         if (ret) {
10401                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10402                               set->crtc->base.id, ret);
10403 fail:
10404                 intel_set_config_restore_state(dev, config);
10405
10406                 /*
10407                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10408                  * force the pipe off to avoid oopsing in the modeset code
10409                  * due to fb==NULL. This should only happen during boot since
10410                  * we don't yet reconstruct the FB from the hardware state.
10411                  */
10412                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10413                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10414
10415                 /* Try to restore the config */
10416                 if (config->mode_changed &&
10417                     intel_set_mode(save_set.crtc, save_set.mode,
10418                                    save_set.x, save_set.y, save_set.fb))
10419                         DRM_ERROR("failed to restore config after modeset failure\n");
10420         }
10421
10422 out_config:
10423         intel_set_config_free(config);
10424         return ret;
10425 }
10426
10427 static const struct drm_crtc_funcs intel_crtc_funcs = {
10428         .cursor_set = intel_crtc_cursor_set,
10429         .cursor_move = intel_crtc_cursor_move,
10430         .gamma_set = intel_crtc_gamma_set,
10431         .set_config = intel_crtc_set_config,
10432         .destroy = intel_crtc_destroy,
10433         .page_flip = intel_crtc_page_flip,
10434 };
10435
10436 static void intel_cpu_pll_init(struct drm_device *dev)
10437 {
10438         if (HAS_DDI(dev))
10439                 intel_ddi_pll_init(dev);
10440 }
10441
10442 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10443                                       struct intel_shared_dpll *pll,
10444                                       struct intel_dpll_hw_state *hw_state)
10445 {
10446         uint32_t val;
10447
10448         val = I915_READ(PCH_DPLL(pll->id));
10449         hw_state->dpll = val;
10450         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10451         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10452
10453         return val & DPLL_VCO_ENABLE;
10454 }
10455
10456 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10457                                   struct intel_shared_dpll *pll)
10458 {
10459         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10460         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10461 }
10462
10463 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10464                                 struct intel_shared_dpll *pll)
10465 {
10466         /* PCH refclock must be enabled first */
10467         ibx_assert_pch_refclk_enabled(dev_priv);
10468
10469         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10470
10471         /* Wait for the clocks to stabilize. */
10472         POSTING_READ(PCH_DPLL(pll->id));
10473         udelay(150);
10474
10475         /* The pixel multiplier can only be updated once the
10476          * DPLL is enabled and the clocks are stable.
10477          *
10478          * So write it again.
10479          */
10480         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10481         POSTING_READ(PCH_DPLL(pll->id));
10482         udelay(200);
10483 }
10484
10485 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10486                                  struct intel_shared_dpll *pll)
10487 {
10488         struct drm_device *dev = dev_priv->dev;
10489         struct intel_crtc *crtc;
10490
10491         /* Make sure no transcoder isn't still depending on us. */
10492         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10493                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10494                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10495         }
10496
10497         I915_WRITE(PCH_DPLL(pll->id), 0);
10498         POSTING_READ(PCH_DPLL(pll->id));
10499         udelay(200);
10500 }
10501
10502 static char *ibx_pch_dpll_names[] = {
10503         "PCH DPLL A",
10504         "PCH DPLL B",
10505 };
10506
10507 static void ibx_pch_dpll_init(struct drm_device *dev)
10508 {
10509         struct drm_i915_private *dev_priv = dev->dev_private;
10510         int i;
10511
10512         dev_priv->num_shared_dpll = 2;
10513
10514         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10515                 dev_priv->shared_dplls[i].id = i;
10516                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10517                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10518                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10519                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10520                 dev_priv->shared_dplls[i].get_hw_state =
10521                         ibx_pch_dpll_get_hw_state;
10522         }
10523 }
10524
10525 static void intel_shared_dpll_init(struct drm_device *dev)
10526 {
10527         struct drm_i915_private *dev_priv = dev->dev_private;
10528
10529         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10530                 ibx_pch_dpll_init(dev);
10531         else
10532                 dev_priv->num_shared_dpll = 0;
10533
10534         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10535 }
10536
10537 static void intel_crtc_init(struct drm_device *dev, int pipe)
10538 {
10539         struct drm_i915_private *dev_priv = dev->dev_private;
10540         struct intel_crtc *intel_crtc;
10541         int i;
10542
10543         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10544         if (intel_crtc == NULL)
10545                 return;
10546
10547         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10548
10549         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10550         for (i = 0; i < 256; i++) {
10551                 intel_crtc->lut_r[i] = i;
10552                 intel_crtc->lut_g[i] = i;
10553                 intel_crtc->lut_b[i] = i;
10554         }
10555
10556         /*
10557          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10558          * is hooked to plane B. Hence we want plane A feeding pipe B.
10559          */
10560         intel_crtc->pipe = pipe;
10561         intel_crtc->plane = pipe;
10562         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10563                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10564                 intel_crtc->plane = !pipe;
10565         }
10566
10567         init_waitqueue_head(&intel_crtc->vbl_wait);
10568
10569         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10570                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10571         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10572         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10573
10574         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10575 }
10576
10577 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10578 {
10579         struct drm_encoder *encoder = connector->base.encoder;
10580
10581         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10582
10583         if (!encoder)
10584                 return INVALID_PIPE;
10585
10586         return to_intel_crtc(encoder->crtc)->pipe;
10587 }
10588
10589 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10590                                 struct drm_file *file)
10591 {
10592         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10593         struct drm_mode_object *drmmode_obj;
10594         struct intel_crtc *crtc;
10595
10596         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10597                 return -ENODEV;
10598
10599         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10600                         DRM_MODE_OBJECT_CRTC);
10601
10602         if (!drmmode_obj) {
10603                 DRM_ERROR("no such CRTC id\n");
10604                 return -ENOENT;
10605         }
10606
10607         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10608         pipe_from_crtc_id->pipe = crtc->pipe;
10609
10610         return 0;
10611 }
10612
10613 static int intel_encoder_clones(struct intel_encoder *encoder)
10614 {
10615         struct drm_device *dev = encoder->base.dev;
10616         struct intel_encoder *source_encoder;
10617         int index_mask = 0;
10618         int entry = 0;
10619
10620         list_for_each_entry(source_encoder,
10621                             &dev->mode_config.encoder_list, base.head) {
10622                 if (encoders_cloneable(encoder, source_encoder))
10623                         index_mask |= (1 << entry);
10624
10625                 entry++;
10626         }
10627
10628         return index_mask;
10629 }
10630
10631 static bool has_edp_a(struct drm_device *dev)
10632 {
10633         struct drm_i915_private *dev_priv = dev->dev_private;
10634
10635         if (!IS_MOBILE(dev))
10636                 return false;
10637
10638         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10639                 return false;
10640
10641         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10642                 return false;
10643
10644         return true;
10645 }
10646
10647 const char *intel_output_name(int output)
10648 {
10649         static const char *names[] = {
10650                 [INTEL_OUTPUT_UNUSED] = "Unused",
10651                 [INTEL_OUTPUT_ANALOG] = "Analog",
10652                 [INTEL_OUTPUT_DVO] = "DVO",
10653                 [INTEL_OUTPUT_SDVO] = "SDVO",
10654                 [INTEL_OUTPUT_LVDS] = "LVDS",
10655                 [INTEL_OUTPUT_TVOUT] = "TV",
10656                 [INTEL_OUTPUT_HDMI] = "HDMI",
10657                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10658                 [INTEL_OUTPUT_EDP] = "eDP",
10659                 [INTEL_OUTPUT_DSI] = "DSI",
10660                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10661         };
10662
10663         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10664                 return "Invalid";
10665
10666         return names[output];
10667 }
10668
10669 static void intel_setup_outputs(struct drm_device *dev)
10670 {
10671         struct drm_i915_private *dev_priv = dev->dev_private;
10672         struct intel_encoder *encoder;
10673         bool dpd_is_edp = false;
10674
10675         intel_lvds_init(dev);
10676
10677         if (!IS_ULT(dev))
10678                 intel_crt_init(dev);
10679
10680         if (HAS_DDI(dev)) {
10681                 int found;
10682
10683                 /* Haswell uses DDI functions to detect digital outputs */
10684                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10685                 /* DDI A only supports eDP */
10686                 if (found)
10687                         intel_ddi_init(dev, PORT_A);
10688
10689                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10690                  * register */
10691                 found = I915_READ(SFUSE_STRAP);
10692
10693                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10694                         intel_ddi_init(dev, PORT_B);
10695                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10696                         intel_ddi_init(dev, PORT_C);
10697                 if (found & SFUSE_STRAP_DDID_DETECTED)
10698                         intel_ddi_init(dev, PORT_D);
10699         } else if (HAS_PCH_SPLIT(dev)) {
10700                 int found;
10701                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10702
10703                 if (has_edp_a(dev))
10704                         intel_dp_init(dev, DP_A, PORT_A);
10705
10706                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10707                         /* PCH SDVOB multiplex with HDMIB */
10708                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10709                         if (!found)
10710                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10711                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10712                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10713                 }
10714
10715                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10716                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10717
10718                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10719                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10720
10721                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10722                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10723
10724                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10725                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10726         } else if (IS_VALLEYVIEW(dev)) {
10727                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10728                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10729                                         PORT_B);
10730                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10731                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10732                 }
10733
10734                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10735                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10736                                         PORT_C);
10737                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10738                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10739                 }
10740
10741                 intel_dsi_init(dev);
10742         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10743                 bool found = false;
10744
10745                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10746                         DRM_DEBUG_KMS("probing SDVOB\n");
10747                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10748                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10749                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10750                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10751                         }
10752
10753                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10754                                 intel_dp_init(dev, DP_B, PORT_B);
10755                 }
10756
10757                 /* Before G4X SDVOC doesn't have its own detect register */
10758
10759                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10760                         DRM_DEBUG_KMS("probing SDVOC\n");
10761                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10762                 }
10763
10764                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10765
10766                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10767                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10768                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10769                         }
10770                         if (SUPPORTS_INTEGRATED_DP(dev))
10771                                 intel_dp_init(dev, DP_C, PORT_C);
10772                 }
10773
10774                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10775                     (I915_READ(DP_D) & DP_DETECTED))
10776                         intel_dp_init(dev, DP_D, PORT_D);
10777         } else if (IS_GEN2(dev))
10778                 intel_dvo_init(dev);
10779
10780         if (SUPPORTS_TV(dev))
10781                 intel_tv_init(dev);
10782
10783         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10784                 encoder->base.possible_crtcs = encoder->crtc_mask;
10785                 encoder->base.possible_clones =
10786                         intel_encoder_clones(encoder);
10787         }
10788
10789         intel_init_pch_refclk(dev);
10790
10791         drm_helper_move_panel_connectors_to_head(dev);
10792 }
10793
10794 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10795 {
10796         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10797
10798         drm_framebuffer_cleanup(fb);
10799         WARN_ON(!intel_fb->obj->framebuffer_references--);
10800         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10801         kfree(intel_fb);
10802 }
10803
10804 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10805                                                 struct drm_file *file,
10806                                                 unsigned int *handle)
10807 {
10808         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10809         struct drm_i915_gem_object *obj = intel_fb->obj;
10810
10811         return drm_gem_handle_create(file, &obj->base, handle);
10812 }
10813
10814 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10815         .destroy = intel_user_framebuffer_destroy,
10816         .create_handle = intel_user_framebuffer_create_handle,
10817 };
10818
10819 static int intel_framebuffer_init(struct drm_device *dev,
10820                                   struct intel_framebuffer *intel_fb,
10821                                   struct drm_mode_fb_cmd2 *mode_cmd,
10822                                   struct drm_i915_gem_object *obj)
10823 {
10824         int aligned_height;
10825         int pitch_limit;
10826         int ret;
10827
10828         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10829
10830         if (obj->tiling_mode == I915_TILING_Y) {
10831                 DRM_DEBUG("hardware does not support tiling Y\n");
10832                 return -EINVAL;
10833         }
10834
10835         if (mode_cmd->pitches[0] & 63) {
10836                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10837                           mode_cmd->pitches[0]);
10838                 return -EINVAL;
10839         }
10840
10841         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10842                 pitch_limit = 32*1024;
10843         } else if (INTEL_INFO(dev)->gen >= 4) {
10844                 if (obj->tiling_mode)
10845                         pitch_limit = 16*1024;
10846                 else
10847                         pitch_limit = 32*1024;
10848         } else if (INTEL_INFO(dev)->gen >= 3) {
10849                 if (obj->tiling_mode)
10850                         pitch_limit = 8*1024;
10851                 else
10852                         pitch_limit = 16*1024;
10853         } else
10854                 /* XXX DSPC is limited to 4k tiled */
10855                 pitch_limit = 8*1024;
10856
10857         if (mode_cmd->pitches[0] > pitch_limit) {
10858                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10859                           obj->tiling_mode ? "tiled" : "linear",
10860                           mode_cmd->pitches[0], pitch_limit);
10861                 return -EINVAL;
10862         }
10863
10864         if (obj->tiling_mode != I915_TILING_NONE &&
10865             mode_cmd->pitches[0] != obj->stride) {
10866                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10867                           mode_cmd->pitches[0], obj->stride);
10868                 return -EINVAL;
10869         }
10870
10871         /* Reject formats not supported by any plane early. */
10872         switch (mode_cmd->pixel_format) {
10873         case DRM_FORMAT_C8:
10874         case DRM_FORMAT_RGB565:
10875         case DRM_FORMAT_XRGB8888:
10876         case DRM_FORMAT_ARGB8888:
10877                 break;
10878         case DRM_FORMAT_XRGB1555:
10879         case DRM_FORMAT_ARGB1555:
10880                 if (INTEL_INFO(dev)->gen > 3) {
10881                         DRM_DEBUG("unsupported pixel format: %s\n",
10882                                   drm_get_format_name(mode_cmd->pixel_format));
10883                         return -EINVAL;
10884                 }
10885                 break;
10886         case DRM_FORMAT_XBGR8888:
10887         case DRM_FORMAT_ABGR8888:
10888         case DRM_FORMAT_XRGB2101010:
10889         case DRM_FORMAT_ARGB2101010:
10890         case DRM_FORMAT_XBGR2101010:
10891         case DRM_FORMAT_ABGR2101010:
10892                 if (INTEL_INFO(dev)->gen < 4) {
10893                         DRM_DEBUG("unsupported pixel format: %s\n",
10894                                   drm_get_format_name(mode_cmd->pixel_format));
10895                         return -EINVAL;
10896                 }
10897                 break;
10898         case DRM_FORMAT_YUYV:
10899         case DRM_FORMAT_UYVY:
10900         case DRM_FORMAT_YVYU:
10901         case DRM_FORMAT_VYUY:
10902                 if (INTEL_INFO(dev)->gen < 5) {
10903                         DRM_DEBUG("unsupported pixel format: %s\n",
10904                                   drm_get_format_name(mode_cmd->pixel_format));
10905                         return -EINVAL;
10906                 }
10907                 break;
10908         default:
10909                 DRM_DEBUG("unsupported pixel format: %s\n",
10910                           drm_get_format_name(mode_cmd->pixel_format));
10911                 return -EINVAL;
10912         }
10913
10914         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10915         if (mode_cmd->offsets[0] != 0)
10916                 return -EINVAL;
10917
10918         aligned_height = intel_align_height(dev, mode_cmd->height,
10919                                             obj->tiling_mode);
10920         /* FIXME drm helper for size checks (especially planar formats)? */
10921         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10922                 return -EINVAL;
10923
10924         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10925         intel_fb->obj = obj;
10926         intel_fb->obj->framebuffer_references++;
10927
10928         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10929         if (ret) {
10930                 DRM_ERROR("framebuffer init failed %d\n", ret);
10931                 return ret;
10932         }
10933
10934         return 0;
10935 }
10936
10937 static struct drm_framebuffer *
10938 intel_user_framebuffer_create(struct drm_device *dev,
10939                               struct drm_file *filp,
10940                               struct drm_mode_fb_cmd2 *mode_cmd)
10941 {
10942         struct drm_i915_gem_object *obj;
10943
10944         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10945                                                 mode_cmd->handles[0]));
10946         if (&obj->base == NULL)
10947                 return ERR_PTR(-ENOENT);
10948
10949         return intel_framebuffer_create(dev, mode_cmd, obj);
10950 }
10951
10952 #ifndef CONFIG_DRM_I915_FBDEV
10953 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10954 {
10955 }
10956 #endif
10957
10958 static const struct drm_mode_config_funcs intel_mode_funcs = {
10959         .fb_create = intel_user_framebuffer_create,
10960         .output_poll_changed = intel_fbdev_output_poll_changed,
10961 };
10962
10963 /* Set up chip specific display functions */
10964 static void intel_init_display(struct drm_device *dev)
10965 {
10966         struct drm_i915_private *dev_priv = dev->dev_private;
10967
10968         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10969                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10970         else if (IS_VALLEYVIEW(dev))
10971                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10972         else if (IS_PINEVIEW(dev))
10973                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10974         else
10975                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10976
10977         if (HAS_DDI(dev)) {
10978                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10979                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10980                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10981                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10982                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10983                 dev_priv->display.off = haswell_crtc_off;
10984                 dev_priv->display.update_primary_plane =
10985                         ironlake_update_primary_plane;
10986         } else if (HAS_PCH_SPLIT(dev)) {
10987                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10988                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10989                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10990                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10991                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10992                 dev_priv->display.off = ironlake_crtc_off;
10993                 dev_priv->display.update_primary_plane =
10994                         ironlake_update_primary_plane;
10995         } else if (IS_VALLEYVIEW(dev)) {
10996                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10997                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10998                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10999                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11000                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11001                 dev_priv->display.off = i9xx_crtc_off;
11002                 dev_priv->display.update_primary_plane =
11003                         i9xx_update_primary_plane;
11004         } else {
11005                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11006                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11007                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11008                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11009                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11010                 dev_priv->display.off = i9xx_crtc_off;
11011                 dev_priv->display.update_primary_plane =
11012                         i9xx_update_primary_plane;
11013         }
11014
11015         /* Returns the core display clock speed */
11016         if (IS_VALLEYVIEW(dev))
11017                 dev_priv->display.get_display_clock_speed =
11018                         valleyview_get_display_clock_speed;
11019         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11020                 dev_priv->display.get_display_clock_speed =
11021                         i945_get_display_clock_speed;
11022         else if (IS_I915G(dev))
11023                 dev_priv->display.get_display_clock_speed =
11024                         i915_get_display_clock_speed;
11025         else if (IS_I945GM(dev) || IS_845G(dev))
11026                 dev_priv->display.get_display_clock_speed =
11027                         i9xx_misc_get_display_clock_speed;
11028         else if (IS_PINEVIEW(dev))
11029                 dev_priv->display.get_display_clock_speed =
11030                         pnv_get_display_clock_speed;
11031         else if (IS_I915GM(dev))
11032                 dev_priv->display.get_display_clock_speed =
11033                         i915gm_get_display_clock_speed;
11034         else if (IS_I865G(dev))
11035                 dev_priv->display.get_display_clock_speed =
11036                         i865_get_display_clock_speed;
11037         else if (IS_I85X(dev))
11038                 dev_priv->display.get_display_clock_speed =
11039                         i855_get_display_clock_speed;
11040         else /* 852, 830 */
11041                 dev_priv->display.get_display_clock_speed =
11042                         i830_get_display_clock_speed;
11043
11044         if (HAS_PCH_SPLIT(dev)) {
11045                 if (IS_GEN5(dev)) {
11046                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11047                         dev_priv->display.write_eld = ironlake_write_eld;
11048                 } else if (IS_GEN6(dev)) {
11049                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11050                         dev_priv->display.write_eld = ironlake_write_eld;
11051                         dev_priv->display.modeset_global_resources =
11052                                 snb_modeset_global_resources;
11053                 } else if (IS_IVYBRIDGE(dev)) {
11054                         /* FIXME: detect B0+ stepping and use auto training */
11055                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11056                         dev_priv->display.write_eld = ironlake_write_eld;
11057                         dev_priv->display.modeset_global_resources =
11058                                 ivb_modeset_global_resources;
11059                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11060                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11061                         dev_priv->display.write_eld = haswell_write_eld;
11062                         dev_priv->display.modeset_global_resources =
11063                                 haswell_modeset_global_resources;
11064                 }
11065         } else if (IS_G4X(dev)) {
11066                 dev_priv->display.write_eld = g4x_write_eld;
11067         } else if (IS_VALLEYVIEW(dev)) {
11068                 dev_priv->display.modeset_global_resources =
11069                         valleyview_modeset_global_resources;
11070                 dev_priv->display.write_eld = ironlake_write_eld;
11071         }
11072
11073         /* Default just returns -ENODEV to indicate unsupported */
11074         dev_priv->display.queue_flip = intel_default_queue_flip;
11075
11076         switch (INTEL_INFO(dev)->gen) {
11077         case 2:
11078                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11079                 break;
11080
11081         case 3:
11082                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11083                 break;
11084
11085         case 4:
11086         case 5:
11087                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11088                 break;
11089
11090         case 6:
11091                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11092                 break;
11093         case 7:
11094         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11095                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11096                 break;
11097         }
11098
11099         intel_panel_init_backlight_funcs(dev);
11100 }
11101
11102 /*
11103  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11104  * resume, or other times.  This quirk makes sure that's the case for
11105  * affected systems.
11106  */
11107 static void quirk_pipea_force(struct drm_device *dev)
11108 {
11109         struct drm_i915_private *dev_priv = dev->dev_private;
11110
11111         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11112         DRM_INFO("applying pipe a force quirk\n");
11113 }
11114
11115 /*
11116  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11117  */
11118 static void quirk_ssc_force_disable(struct drm_device *dev)
11119 {
11120         struct drm_i915_private *dev_priv = dev->dev_private;
11121         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11122         DRM_INFO("applying lvds SSC disable quirk\n");
11123 }
11124
11125 /*
11126  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11127  * brightness value
11128  */
11129 static void quirk_invert_brightness(struct drm_device *dev)
11130 {
11131         struct drm_i915_private *dev_priv = dev->dev_private;
11132         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11133         DRM_INFO("applying inverted panel brightness quirk\n");
11134 }
11135
11136 struct intel_quirk {
11137         int device;
11138         int subsystem_vendor;
11139         int subsystem_device;
11140         void (*hook)(struct drm_device *dev);
11141 };
11142
11143 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11144 struct intel_dmi_quirk {
11145         void (*hook)(struct drm_device *dev);
11146         const struct dmi_system_id (*dmi_id_list)[];
11147 };
11148
11149 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11150 {
11151         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11152         return 1;
11153 }
11154
11155 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11156         {
11157                 .dmi_id_list = &(const struct dmi_system_id[]) {
11158                         {
11159                                 .callback = intel_dmi_reverse_brightness,
11160                                 .ident = "NCR Corporation",
11161                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11162                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11163                                 },
11164                         },
11165                         { }  /* terminating entry */
11166                 },
11167                 .hook = quirk_invert_brightness,
11168         },
11169 };
11170
11171 static struct intel_quirk intel_quirks[] = {
11172         /* HP Mini needs pipe A force quirk (LP: #322104) */
11173         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11174
11175         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11176         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11177
11178         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11179         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11180
11181         /* 830 needs to leave pipe A & dpll A up */
11182         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11183
11184         /* Lenovo U160 cannot use SSC on LVDS */
11185         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11186
11187         /* Sony Vaio Y cannot use SSC on LVDS */
11188         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11189
11190         /* Acer Aspire 5734Z must invert backlight brightness */
11191         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11192
11193         /* Acer/eMachines G725 */
11194         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11195
11196         /* Acer/eMachines e725 */
11197         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11198
11199         /* Acer/Packard Bell NCL20 */
11200         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11201
11202         /* Acer Aspire 4736Z */
11203         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11204
11205         /* Acer Aspire 5336 */
11206         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11207 };
11208
11209 static void intel_init_quirks(struct drm_device *dev)
11210 {
11211         struct pci_dev *d = dev->pdev;
11212         int i;
11213
11214         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11215                 struct intel_quirk *q = &intel_quirks[i];
11216
11217                 if (d->device == q->device &&
11218                     (d->subsystem_vendor == q->subsystem_vendor ||
11219                      q->subsystem_vendor == PCI_ANY_ID) &&
11220                     (d->subsystem_device == q->subsystem_device ||
11221                      q->subsystem_device == PCI_ANY_ID))
11222                         q->hook(dev);
11223         }
11224         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11225                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11226                         intel_dmi_quirks[i].hook(dev);
11227         }
11228 }
11229
11230 /* Disable the VGA plane that we never use */
11231 static void i915_disable_vga(struct drm_device *dev)
11232 {
11233         struct drm_i915_private *dev_priv = dev->dev_private;
11234         u8 sr1;
11235         u32 vga_reg = i915_vgacntrl_reg(dev);
11236
11237         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11238         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11239         outb(SR01, VGA_SR_INDEX);
11240         sr1 = inb(VGA_SR_DATA);
11241         outb(sr1 | 1<<5, VGA_SR_DATA);
11242         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11243         udelay(300);
11244
11245         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11246         POSTING_READ(vga_reg);
11247 }
11248
11249 void intel_modeset_init_hw(struct drm_device *dev)
11250 {
11251         intel_prepare_ddi(dev);
11252
11253         intel_init_clock_gating(dev);
11254
11255         intel_reset_dpio(dev);
11256
11257         intel_enable_gt_powersave(dev);
11258 }
11259
11260 void intel_modeset_suspend_hw(struct drm_device *dev)
11261 {
11262         intel_suspend_hw(dev);
11263 }
11264
11265 void intel_modeset_init(struct drm_device *dev)
11266 {
11267         struct drm_i915_private *dev_priv = dev->dev_private;
11268         int sprite, ret;
11269         enum pipe pipe;
11270         struct intel_crtc *crtc;
11271
11272         drm_mode_config_init(dev);
11273
11274         dev->mode_config.min_width = 0;
11275         dev->mode_config.min_height = 0;
11276
11277         dev->mode_config.preferred_depth = 24;
11278         dev->mode_config.prefer_shadow = 1;
11279
11280         dev->mode_config.funcs = &intel_mode_funcs;
11281
11282         intel_init_quirks(dev);
11283
11284         intel_init_pm(dev);
11285
11286         if (INTEL_INFO(dev)->num_pipes == 0)
11287                 return;
11288
11289         intel_init_display(dev);
11290
11291         if (IS_GEN2(dev)) {
11292                 dev->mode_config.max_width = 2048;
11293                 dev->mode_config.max_height = 2048;
11294         } else if (IS_GEN3(dev)) {
11295                 dev->mode_config.max_width = 4096;
11296                 dev->mode_config.max_height = 4096;
11297         } else {
11298                 dev->mode_config.max_width = 8192;
11299                 dev->mode_config.max_height = 8192;
11300         }
11301
11302         if (IS_GEN2(dev)) {
11303                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11304                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11305         } else {
11306                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11307                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11308         }
11309
11310         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11311
11312         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11313                       INTEL_INFO(dev)->num_pipes,
11314                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11315
11316         for_each_pipe(pipe) {
11317                 intel_crtc_init(dev, pipe);
11318                 for_each_sprite(pipe, sprite) {
11319                         ret = intel_plane_init(dev, pipe, sprite);
11320                         if (ret)
11321                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11322                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11323                 }
11324         }
11325
11326         intel_init_dpio(dev);
11327         intel_reset_dpio(dev);
11328
11329         intel_cpu_pll_init(dev);
11330         intel_shared_dpll_init(dev);
11331
11332         /* Just disable it once at startup */
11333         i915_disable_vga(dev);
11334         intel_setup_outputs(dev);
11335
11336         /* Just in case the BIOS is doing something questionable. */
11337         intel_disable_fbc(dev);
11338
11339         mutex_lock(&dev->mode_config.mutex);
11340         intel_modeset_setup_hw_state(dev, false);
11341         mutex_unlock(&dev->mode_config.mutex);
11342
11343         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11344                             base.head) {
11345                 if (!crtc->active)
11346                         continue;
11347
11348                 /*
11349                  * Note that reserving the BIOS fb up front prevents us
11350                  * from stuffing other stolen allocations like the ring
11351                  * on top.  This prevents some ugliness at boot time, and
11352                  * can even allow for smooth boot transitions if the BIOS
11353                  * fb is large enough for the active pipe configuration.
11354                  */
11355                 if (dev_priv->display.get_plane_config) {
11356                         dev_priv->display.get_plane_config(crtc,
11357                                                            &crtc->plane_config);
11358                         /*
11359                          * If the fb is shared between multiple heads, we'll
11360                          * just get the first one.
11361                          */
11362                         intel_find_plane_obj(crtc, &crtc->plane_config);
11363                 }
11364         }
11365 }
11366
11367 static void
11368 intel_connector_break_all_links(struct intel_connector *connector)
11369 {
11370         connector->base.dpms = DRM_MODE_DPMS_OFF;
11371         connector->base.encoder = NULL;
11372         connector->encoder->connectors_active = false;
11373         connector->encoder->base.crtc = NULL;
11374 }
11375
11376 static void intel_enable_pipe_a(struct drm_device *dev)
11377 {
11378         struct intel_connector *connector;
11379         struct drm_connector *crt = NULL;
11380         struct intel_load_detect_pipe load_detect_temp;
11381
11382         /* We can't just switch on the pipe A, we need to set things up with a
11383          * proper mode and output configuration. As a gross hack, enable pipe A
11384          * by enabling the load detect pipe once. */
11385         list_for_each_entry(connector,
11386                             &dev->mode_config.connector_list,
11387                             base.head) {
11388                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11389                         crt = &connector->base;
11390                         break;
11391                 }
11392         }
11393
11394         if (!crt)
11395                 return;
11396
11397         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11398                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11399
11400
11401 }
11402
11403 static bool
11404 intel_check_plane_mapping(struct intel_crtc *crtc)
11405 {
11406         struct drm_device *dev = crtc->base.dev;
11407         struct drm_i915_private *dev_priv = dev->dev_private;
11408         u32 reg, val;
11409
11410         if (INTEL_INFO(dev)->num_pipes == 1)
11411                 return true;
11412
11413         reg = DSPCNTR(!crtc->plane);
11414         val = I915_READ(reg);
11415
11416         if ((val & DISPLAY_PLANE_ENABLE) &&
11417             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11418                 return false;
11419
11420         return true;
11421 }
11422
11423 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11424 {
11425         struct drm_device *dev = crtc->base.dev;
11426         struct drm_i915_private *dev_priv = dev->dev_private;
11427         u32 reg;
11428
11429         /* Clear any frame start delays used for debugging left by the BIOS */
11430         reg = PIPECONF(crtc->config.cpu_transcoder);
11431         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11432
11433         /* We need to sanitize the plane -> pipe mapping first because this will
11434          * disable the crtc (and hence change the state) if it is wrong. Note
11435          * that gen4+ has a fixed plane -> pipe mapping.  */
11436         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11437                 struct intel_connector *connector;
11438                 bool plane;
11439
11440                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11441                               crtc->base.base.id);
11442
11443                 /* Pipe has the wrong plane attached and the plane is active.
11444                  * Temporarily change the plane mapping and disable everything
11445                  * ...  */
11446                 plane = crtc->plane;
11447                 crtc->plane = !plane;
11448                 dev_priv->display.crtc_disable(&crtc->base);
11449                 crtc->plane = plane;
11450
11451                 /* ... and break all links. */
11452                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11453                                     base.head) {
11454                         if (connector->encoder->base.crtc != &crtc->base)
11455                                 continue;
11456
11457                         intel_connector_break_all_links(connector);
11458                 }
11459
11460                 WARN_ON(crtc->active);
11461                 crtc->base.enabled = false;
11462         }
11463
11464         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11465             crtc->pipe == PIPE_A && !crtc->active) {
11466                 /* BIOS forgot to enable pipe A, this mostly happens after
11467                  * resume. Force-enable the pipe to fix this, the update_dpms
11468                  * call below we restore the pipe to the right state, but leave
11469                  * the required bits on. */
11470                 intel_enable_pipe_a(dev);
11471         }
11472
11473         /* Adjust the state of the output pipe according to whether we
11474          * have active connectors/encoders. */
11475         intel_crtc_update_dpms(&crtc->base);
11476
11477         if (crtc->active != crtc->base.enabled) {
11478                 struct intel_encoder *encoder;
11479
11480                 /* This can happen either due to bugs in the get_hw_state
11481                  * functions or because the pipe is force-enabled due to the
11482                  * pipe A quirk. */
11483                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11484                               crtc->base.base.id,
11485                               crtc->base.enabled ? "enabled" : "disabled",
11486                               crtc->active ? "enabled" : "disabled");
11487
11488                 crtc->base.enabled = crtc->active;
11489
11490                 /* Because we only establish the connector -> encoder ->
11491                  * crtc links if something is active, this means the
11492                  * crtc is now deactivated. Break the links. connector
11493                  * -> encoder links are only establish when things are
11494                  *  actually up, hence no need to break them. */
11495                 WARN_ON(crtc->active);
11496
11497                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11498                         WARN_ON(encoder->connectors_active);
11499                         encoder->base.crtc = NULL;
11500                 }
11501         }
11502         if (crtc->active) {
11503                 /*
11504                  * We start out with underrun reporting disabled to avoid races.
11505                  * For correct bookkeeping mark this on active crtcs.
11506                  *
11507                  * No protection against concurrent access is required - at
11508                  * worst a fifo underrun happens which also sets this to false.
11509                  */
11510                 crtc->cpu_fifo_underrun_disabled = true;
11511                 crtc->pch_fifo_underrun_disabled = true;
11512         }
11513 }
11514
11515 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11516 {
11517         struct intel_connector *connector;
11518         struct drm_device *dev = encoder->base.dev;
11519
11520         /* We need to check both for a crtc link (meaning that the
11521          * encoder is active and trying to read from a pipe) and the
11522          * pipe itself being active. */
11523         bool has_active_crtc = encoder->base.crtc &&
11524                 to_intel_crtc(encoder->base.crtc)->active;
11525
11526         if (encoder->connectors_active && !has_active_crtc) {
11527                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11528                               encoder->base.base.id,
11529                               drm_get_encoder_name(&encoder->base));
11530
11531                 /* Connector is active, but has no active pipe. This is
11532                  * fallout from our resume register restoring. Disable
11533                  * the encoder manually again. */
11534                 if (encoder->base.crtc) {
11535                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11536                                       encoder->base.base.id,
11537                                       drm_get_encoder_name(&encoder->base));
11538                         encoder->disable(encoder);
11539                 }
11540
11541                 /* Inconsistent output/port/pipe state happens presumably due to
11542                  * a bug in one of the get_hw_state functions. Or someplace else
11543                  * in our code, like the register restore mess on resume. Clamp
11544                  * things to off as a safer default. */
11545                 list_for_each_entry(connector,
11546                                     &dev->mode_config.connector_list,
11547                                     base.head) {
11548                         if (connector->encoder != encoder)
11549                                 continue;
11550
11551                         intel_connector_break_all_links(connector);
11552                 }
11553         }
11554         /* Enabled encoders without active connectors will be fixed in
11555          * the crtc fixup. */
11556 }
11557
11558 void i915_redisable_vga_power_on(struct drm_device *dev)
11559 {
11560         struct drm_i915_private *dev_priv = dev->dev_private;
11561         u32 vga_reg = i915_vgacntrl_reg(dev);
11562
11563         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11564                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11565                 i915_disable_vga(dev);
11566         }
11567 }
11568
11569 void i915_redisable_vga(struct drm_device *dev)
11570 {
11571         struct drm_i915_private *dev_priv = dev->dev_private;
11572
11573         /* This function can be called both from intel_modeset_setup_hw_state or
11574          * at a very early point in our resume sequence, where the power well
11575          * structures are not yet restored. Since this function is at a very
11576          * paranoid "someone might have enabled VGA while we were not looking"
11577          * level, just check if the power well is enabled instead of trying to
11578          * follow the "don't touch the power well if we don't need it" policy
11579          * the rest of the driver uses. */
11580         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11581                 return;
11582
11583         i915_redisable_vga_power_on(dev);
11584 }
11585
11586 static bool primary_get_hw_state(struct intel_crtc *crtc)
11587 {
11588         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11589
11590         if (!crtc->active)
11591                 return false;
11592
11593         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11594 }
11595
11596 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11597 {
11598         struct drm_i915_private *dev_priv = dev->dev_private;
11599         enum pipe pipe;
11600         struct intel_crtc *crtc;
11601         struct intel_encoder *encoder;
11602         struct intel_connector *connector;
11603         int i;
11604
11605         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11606                             base.head) {
11607                 memset(&crtc->config, 0, sizeof(crtc->config));
11608
11609                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11610
11611                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11612                                                                  &crtc->config);
11613
11614                 crtc->base.enabled = crtc->active;
11615                 crtc->primary_enabled = primary_get_hw_state(crtc);
11616
11617                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11618                               crtc->base.base.id,
11619                               crtc->active ? "enabled" : "disabled");
11620         }
11621
11622         /* FIXME: Smash this into the new shared dpll infrastructure. */
11623         if (HAS_DDI(dev))
11624                 intel_ddi_setup_hw_pll_state(dev);
11625
11626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11627                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11628
11629                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11630                 pll->active = 0;
11631                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11632                                     base.head) {
11633                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11634                                 pll->active++;
11635                 }
11636                 pll->refcount = pll->active;
11637
11638                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11639                               pll->name, pll->refcount, pll->on);
11640         }
11641
11642         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11643                             base.head) {
11644                 pipe = 0;
11645
11646                 if (encoder->get_hw_state(encoder, &pipe)) {
11647                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11648                         encoder->base.crtc = &crtc->base;
11649                         encoder->get_config(encoder, &crtc->config);
11650                 } else {
11651                         encoder->base.crtc = NULL;
11652                 }
11653
11654                 encoder->connectors_active = false;
11655                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11656                               encoder->base.base.id,
11657                               drm_get_encoder_name(&encoder->base),
11658                               encoder->base.crtc ? "enabled" : "disabled",
11659                               pipe_name(pipe));
11660         }
11661
11662         list_for_each_entry(connector, &dev->mode_config.connector_list,
11663                             base.head) {
11664                 if (connector->get_hw_state(connector)) {
11665                         connector->base.dpms = DRM_MODE_DPMS_ON;
11666                         connector->encoder->connectors_active = true;
11667                         connector->base.encoder = &connector->encoder->base;
11668                 } else {
11669                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11670                         connector->base.encoder = NULL;
11671                 }
11672                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11673                               connector->base.base.id,
11674                               drm_get_connector_name(&connector->base),
11675                               connector->base.encoder ? "enabled" : "disabled");
11676         }
11677 }
11678
11679 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11680  * and i915 state tracking structures. */
11681 void intel_modeset_setup_hw_state(struct drm_device *dev,
11682                                   bool force_restore)
11683 {
11684         struct drm_i915_private *dev_priv = dev->dev_private;
11685         enum pipe pipe;
11686         struct intel_crtc *crtc;
11687         struct intel_encoder *encoder;
11688         int i;
11689
11690         intel_modeset_readout_hw_state(dev);
11691
11692         /*
11693          * Now that we have the config, copy it to each CRTC struct
11694          * Note that this could go away if we move to using crtc_config
11695          * checking everywhere.
11696          */
11697         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11698                             base.head) {
11699                 if (crtc->active && i915.fastboot) {
11700                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11701                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11702                                       crtc->base.base.id);
11703                         drm_mode_debug_printmodeline(&crtc->base.mode);
11704                 }
11705         }
11706
11707         /* HW state is read out, now we need to sanitize this mess. */
11708         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11709                             base.head) {
11710                 intel_sanitize_encoder(encoder);
11711         }
11712
11713         for_each_pipe(pipe) {
11714                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11715                 intel_sanitize_crtc(crtc);
11716                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11717         }
11718
11719         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11720                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11721
11722                 if (!pll->on || pll->active)
11723                         continue;
11724
11725                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11726
11727                 pll->disable(dev_priv, pll);
11728                 pll->on = false;
11729         }
11730
11731         if (HAS_PCH_SPLIT(dev))
11732                 ilk_wm_get_hw_state(dev);
11733
11734         if (force_restore) {
11735                 i915_redisable_vga(dev);
11736
11737                 /*
11738                  * We need to use raw interfaces for restoring state to avoid
11739                  * checking (bogus) intermediate states.
11740                  */
11741                 for_each_pipe(pipe) {
11742                         struct drm_crtc *crtc =
11743                                 dev_priv->pipe_to_crtc_mapping[pipe];
11744
11745                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11746                                          crtc->primary->fb);
11747                 }
11748         } else {
11749                 intel_modeset_update_staged_output_state(dev);
11750         }
11751
11752         intel_modeset_check_state(dev);
11753 }
11754
11755 void intel_modeset_gem_init(struct drm_device *dev)
11756 {
11757         struct drm_crtc *c;
11758         struct intel_framebuffer *fb;
11759
11760         mutex_lock(&dev->struct_mutex);
11761         intel_init_gt_powersave(dev);
11762         mutex_unlock(&dev->struct_mutex);
11763
11764         intel_modeset_init_hw(dev);
11765
11766         intel_setup_overlay(dev);
11767
11768         /*
11769          * Make sure any fbs we allocated at startup are properly
11770          * pinned & fenced.  When we do the allocation it's too early
11771          * for this.
11772          */
11773         mutex_lock(&dev->struct_mutex);
11774         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11775                 if (!c->primary->fb)
11776                         continue;
11777
11778                 fb = to_intel_framebuffer(c->primary->fb);
11779                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11780                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11781                                   to_intel_crtc(c)->pipe);
11782                         drm_framebuffer_unreference(c->primary->fb);
11783                         c->primary->fb = NULL;
11784                 }
11785         }
11786         mutex_unlock(&dev->struct_mutex);
11787 }
11788
11789 void intel_connector_unregister(struct intel_connector *intel_connector)
11790 {
11791         struct drm_connector *connector = &intel_connector->base;
11792
11793         intel_panel_destroy_backlight(connector);
11794         drm_sysfs_connector_remove(connector);
11795 }
11796
11797 void intel_modeset_cleanup(struct drm_device *dev)
11798 {
11799         struct drm_i915_private *dev_priv = dev->dev_private;
11800         struct drm_crtc *crtc;
11801         struct drm_connector *connector;
11802
11803         /*
11804          * Interrupts and polling as the first thing to avoid creating havoc.
11805          * Too much stuff here (turning of rps, connectors, ...) would
11806          * experience fancy races otherwise.
11807          */
11808         drm_irq_uninstall(dev);
11809         cancel_work_sync(&dev_priv->hotplug_work);
11810         /*
11811          * Due to the hpd irq storm handling the hotplug work can re-arm the
11812          * poll handlers. Hence disable polling after hpd handling is shut down.
11813          */
11814         drm_kms_helper_poll_fini(dev);
11815
11816         mutex_lock(&dev->struct_mutex);
11817
11818         intel_unregister_dsm_handler();
11819
11820         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11821                 /* Skip inactive CRTCs */
11822                 if (!crtc->primary->fb)
11823                         continue;
11824
11825                 intel_increase_pllclock(crtc);
11826         }
11827
11828         intel_disable_fbc(dev);
11829
11830         intel_disable_gt_powersave(dev);
11831
11832         ironlake_teardown_rc6(dev);
11833
11834         mutex_unlock(&dev->struct_mutex);
11835
11836         /* flush any delayed tasks or pending work */
11837         flush_scheduled_work();
11838
11839         /* destroy the backlight and sysfs files before encoders/connectors */
11840         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11841                 struct intel_connector *intel_connector;
11842
11843                 intel_connector = to_intel_connector(connector);
11844                 intel_connector->unregister(intel_connector);
11845         }
11846
11847         drm_mode_config_cleanup(dev);
11848
11849         intel_cleanup_overlay(dev);
11850
11851         mutex_lock(&dev->struct_mutex);
11852         intel_cleanup_gt_powersave(dev);
11853         mutex_unlock(&dev->struct_mutex);
11854 }
11855
11856 /*
11857  * Return which encoder is currently attached for connector.
11858  */
11859 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11860 {
11861         return &intel_attached_encoder(connector)->base;
11862 }
11863
11864 void intel_connector_attach_encoder(struct intel_connector *connector,
11865                                     struct intel_encoder *encoder)
11866 {
11867         connector->encoder = encoder;
11868         drm_mode_connector_attach_encoder(&connector->base,
11869                                           &encoder->base);
11870 }
11871
11872 /*
11873  * set vga decode state - true == enable VGA decode
11874  */
11875 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11876 {
11877         struct drm_i915_private *dev_priv = dev->dev_private;
11878         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11879         u16 gmch_ctrl;
11880
11881         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11882                 DRM_ERROR("failed to read control word\n");
11883                 return -EIO;
11884         }
11885
11886         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11887                 return 0;
11888
11889         if (state)
11890                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11891         else
11892                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11893
11894         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11895                 DRM_ERROR("failed to write control word\n");
11896                 return -EIO;
11897         }
11898
11899         return 0;
11900 }
11901
11902 struct intel_display_error_state {
11903
11904         u32 power_well_driver;
11905
11906         int num_transcoders;
11907
11908         struct intel_cursor_error_state {
11909                 u32 control;
11910                 u32 position;
11911                 u32 base;
11912                 u32 size;
11913         } cursor[I915_MAX_PIPES];
11914
11915         struct intel_pipe_error_state {
11916                 bool power_domain_on;
11917                 u32 source;
11918                 u32 stat;
11919         } pipe[I915_MAX_PIPES];
11920
11921         struct intel_plane_error_state {
11922                 u32 control;
11923                 u32 stride;
11924                 u32 size;
11925                 u32 pos;
11926                 u32 addr;
11927                 u32 surface;
11928                 u32 tile_offset;
11929         } plane[I915_MAX_PIPES];
11930
11931         struct intel_transcoder_error_state {
11932                 bool power_domain_on;
11933                 enum transcoder cpu_transcoder;
11934
11935                 u32 conf;
11936
11937                 u32 htotal;
11938                 u32 hblank;
11939                 u32 hsync;
11940                 u32 vtotal;
11941                 u32 vblank;
11942                 u32 vsync;
11943         } transcoder[4];
11944 };
11945
11946 struct intel_display_error_state *
11947 intel_display_capture_error_state(struct drm_device *dev)
11948 {
11949         struct drm_i915_private *dev_priv = dev->dev_private;
11950         struct intel_display_error_state *error;
11951         int transcoders[] = {
11952                 TRANSCODER_A,
11953                 TRANSCODER_B,
11954                 TRANSCODER_C,
11955                 TRANSCODER_EDP,
11956         };
11957         int i;
11958
11959         if (INTEL_INFO(dev)->num_pipes == 0)
11960                 return NULL;
11961
11962         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11963         if (error == NULL)
11964                 return NULL;
11965
11966         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11967                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11968
11969         for_each_pipe(i) {
11970                 error->pipe[i].power_domain_on =
11971                         intel_display_power_enabled_sw(dev_priv,
11972                                                        POWER_DOMAIN_PIPE(i));
11973                 if (!error->pipe[i].power_domain_on)
11974                         continue;
11975
11976                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11977                         error->cursor[i].control = I915_READ(CURCNTR(i));
11978                         error->cursor[i].position = I915_READ(CURPOS(i));
11979                         error->cursor[i].base = I915_READ(CURBASE(i));
11980                 } else {
11981                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11982                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11983                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11984                 }
11985
11986                 error->plane[i].control = I915_READ(DSPCNTR(i));
11987                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11988                 if (INTEL_INFO(dev)->gen <= 3) {
11989                         error->plane[i].size = I915_READ(DSPSIZE(i));
11990                         error->plane[i].pos = I915_READ(DSPPOS(i));
11991                 }
11992                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11993                         error->plane[i].addr = I915_READ(DSPADDR(i));
11994                 if (INTEL_INFO(dev)->gen >= 4) {
11995                         error->plane[i].surface = I915_READ(DSPSURF(i));
11996                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11997                 }
11998
11999                 error->pipe[i].source = I915_READ(PIPESRC(i));
12000
12001                 if (!HAS_PCH_SPLIT(dev))
12002                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12003         }
12004
12005         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12006         if (HAS_DDI(dev_priv->dev))
12007                 error->num_transcoders++; /* Account for eDP. */
12008
12009         for (i = 0; i < error->num_transcoders; i++) {
12010                 enum transcoder cpu_transcoder = transcoders[i];
12011
12012                 error->transcoder[i].power_domain_on =
12013                         intel_display_power_enabled_sw(dev_priv,
12014                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12015                 if (!error->transcoder[i].power_domain_on)
12016                         continue;
12017
12018                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12019
12020                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12021                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12022                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12023                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12024                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12025                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12026                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12027         }
12028
12029         return error;
12030 }
12031
12032 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12033
12034 void
12035 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12036                                 struct drm_device *dev,
12037                                 struct intel_display_error_state *error)
12038 {
12039         int i;
12040
12041         if (!error)
12042                 return;
12043
12044         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12045         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12046                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12047                            error->power_well_driver);
12048         for_each_pipe(i) {
12049                 err_printf(m, "Pipe [%d]:\n", i);
12050                 err_printf(m, "  Power: %s\n",
12051                            error->pipe[i].power_domain_on ? "on" : "off");
12052                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12053                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12054
12055                 err_printf(m, "Plane [%d]:\n", i);
12056                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12057                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12058                 if (INTEL_INFO(dev)->gen <= 3) {
12059                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12060                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12061                 }
12062                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12063                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12064                 if (INTEL_INFO(dev)->gen >= 4) {
12065                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12066                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12067                 }
12068
12069                 err_printf(m, "Cursor [%d]:\n", i);
12070                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12071                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12072                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12073         }
12074
12075         for (i = 0; i < error->num_transcoders; i++) {
12076                 err_printf(m, "CPU transcoder: %c\n",
12077                            transcoder_name(error->transcoder[i].cpu_transcoder));
12078                 err_printf(m, "  Power: %s\n",
12079                            error->transcoder[i].power_domain_on ? "on" : "off");
12080                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12081                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12082                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12083                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12084                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12085                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12086                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12087         }
12088 }