drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 typedef struct intel_limit intel_limit_t;
  63 struct intel_limit {
  64         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  65         intel_p2_t          p2;
  66 };
  67
  68 /* FDI */
  69 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv_dac = {
 313         .dot = { .min = 25000, .max = 270000 },
 314         .vco = { .min = 4000000, .max = 6000000 },
 315         .n = { .min = 1, .max = 7 },
 316         .m = { .min = 22, .max = 450 }, /* guess */
 317         .m1 = { .min = 2, .max = 3 },
 318         .m2 = { .min = 11, .max = 156 },
 319         .p = { .min = 10, .max = 30 },
 320         .p1 = { .min = 1, .max = 3 },
 321         .p2 = { .dot_limit = 270000,
 322                 .p2_slow = 2, .p2_fast = 20 },
 323 };
 324
 325 static const intel_limit_t intel_limits_vlv_hdmi = {
 326         .dot = { .min = 25000, .max = 270000 },
 327         .vco = { .min = 4000000, .max = 6000000 },
 328         .n = { .min = 1, .max = 7 },
 329         .m = { .min = 60, .max = 300 }, /* guess */
 330         .m1 = { .min = 2, .max = 3 },
 331         .m2 = { .min = 11, .max = 156 },
 332         .p = { .min = 10, .max = 30 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .dot_limit = 270000,
 335                 .p2_slow = 2, .p2_fast = 20 },
 336 };
 337
 338 static const intel_limit_t intel_limits_vlv_dp = {
 339         .dot = { .min = 25000, .max = 270000 },
 340         .vco = { .min = 4000000, .max = 6000000 },
 341         .n = { .min = 1, .max = 7 },
 342         .m = { .min = 22, .max = 450 },
 343         .m1 = { .min = 2, .max = 3 },
 344         .m2 = { .min = 11, .max = 156 },
 345         .p = { .min = 10, .max = 30 },
 346         .p1 = { .min = 1, .max = 3 },
 347         .p2 = { .dot_limit = 270000,
 348                 .p2_slow = 2, .p2_fast = 20 },
 349 };
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 412                         limit = &intel_limits_vlv_dac;
 413                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 414                         limit = &intel_limits_vlv_hdmi;
 415                 else
 416                         limit = &intel_limits_vlv_dp;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         clock->vco = refclk * clock->m / clock->n;
 439         clock->dot = clock->vco / clock->p;
 440 }
 441
 442 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 443 {
 444         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 445 }
 446
 447 static void i9xx_clock(int refclk, intel_clock_t *clock)
 448 {
 449         clock->m = i9xx_dpll_compute_m(clock);
 450         clock->p = clock->p1 * clock->p2;
 451         clock->vco = refclk * clock->m / (clock->n + 2);
 452         clock->dot = clock->vco / clock->p;
 453 }
 454
 455 /**
 456  * Returns whether any output on the specified pipe is of the specified type
 457  */
 458 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 459 {
 460         struct drm_device *dev = crtc->dev;
 461         struct intel_encoder *encoder;
 462
 463         for_each_encoder_on_crtc(dev, crtc, encoder)
 464                 if (encoder->type == type)
 465                         return true;
 466
 467         return false;
 468 }
 469
 470 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 471 /**
 472  * Returns whether the given set of divisors are valid for a given refclk with
 473  * the given connectors.
 474  */
 475
 476 static bool intel_PLL_is_valid(struct drm_device *dev,
 477                                const intel_limit_t *limit,
 478                                const intel_clock_t *clock)
 479 {
 480         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 481                 INTELPllInvalid("p1 out of range\n");
 482         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 483                 INTELPllInvalid("p out of range\n");
 484         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 485                 INTELPllInvalid("m2 out of range\n");
 486         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 487                 INTELPllInvalid("m1 out of range\n");
 488         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 489                 INTELPllInvalid("m1 <= m2\n");
 490         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 491                 INTELPllInvalid("m out of range\n");
 492         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 493                 INTELPllInvalid("n out of range\n");
 494         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 495                 INTELPllInvalid("vco out of range\n");
 496         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 497          * connector, etc., rather than just a single range.
 498          */
 499         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 500                 INTELPllInvalid("dot out of range\n");
 501
 502         return true;
 503 }
 504
 505 static bool
 506 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 507                     int target, int refclk, intel_clock_t *match_clock,
 508                     intel_clock_t *best_clock)
 509 {
 510         struct drm_device *dev = crtc->dev;
 511         intel_clock_t clock;
 512         int err = target;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 /*
 516                  * For LVDS just rely on its current settings for dual-channel.
 517                  * We haven't figured out how to reliably set up different
 518                  * single/dual channel state, if we even can.
 519                  */
 520                 if (intel_is_dual_link_lvds(dev))
 521                         clock.p2 = limit->p2.p2_fast;
 522                 else
 523                         clock.p2 = limit->p2.p2_slow;
 524         } else {
 525                 if (target < limit->p2.dot_limit)
 526                         clock.p2 = limit->p2.p2_slow;
 527                 else
 528                         clock.p2 = limit->p2.p2_fast;
 529         }
 530
 531         memset(best_clock, 0, sizeof(*best_clock));
 532
 533         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 534              clock.m1++) {
 535                 for (clock.m2 = limit->m2.min;
 536                      clock.m2 <= limit->m2.max; clock.m2++) {
 537                         if (clock.m2 >= clock.m1)
 538                                 break;
 539                         for (clock.n = limit->n.min;
 540                              clock.n <= limit->n.max; clock.n++) {
 541                                 for (clock.p1 = limit->p1.min;
 542                                         clock.p1 <= limit->p1.max; clock.p1++) {
 543                                         int this_err;
 544
 545                                         i9xx_clock(refclk, &clock);
 546                                         if (!intel_PLL_is_valid(dev, limit,
 547                                                                 &clock))
 548                                                 continue;
 549                                         if (match_clock &&
 550                                             clock.p != match_clock->p)
 551                                                 continue;
 552
 553                                         this_err = abs(clock.dot - target);
 554                                         if (this_err < err) {
 555                                                 *best_clock = clock;
 556                                                 err = this_err;
 557                                         }
 558                                 }
 559                         }
 560                 }
 561         }
 562
 563         return (err != target);
 564 }
 565
 566 static bool
 567 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 568                    int target, int refclk, intel_clock_t *match_clock,
 569                    intel_clock_t *best_clock)
 570 {
 571         struct drm_device *dev = crtc->dev;
 572         intel_clock_t clock;
 573         int err = target;
 574
 575         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 576                 /*
 577                  * For LVDS just rely on its current settings for dual-channel.
 578                  * We haven't figured out how to reliably set up different
 579                  * single/dual channel state, if we even can.
 580                  */
 581                 if (intel_is_dual_link_lvds(dev))
 582                         clock.p2 = limit->p2.p2_fast;
 583                 else
 584                         clock.p2 = limit->p2.p2_slow;
 585         } else {
 586                 if (target < limit->p2.dot_limit)
 587                         clock.p2 = limit->p2.p2_slow;
 588                 else
 589                         clock.p2 = limit->p2.p2_fast;
 590         }
 591
 592         memset(best_clock, 0, sizeof(*best_clock));
 593
 594         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 595              clock.m1++) {
 596                 for (clock.m2 = limit->m2.min;
 597                      clock.m2 <= limit->m2.max; clock.m2++) {
 598                         for (clock.n = limit->n.min;
 599                              clock.n <= limit->n.max; clock.n++) {
 600                                 for (clock.p1 = limit->p1.min;
 601                                         clock.p1 <= limit->p1.max; clock.p1++) {
 602                                         int this_err;
 603
 604                                         pineview_clock(refclk, &clock);
 605                                         if (!intel_PLL_is_valid(dev, limit,
 606                                                                 &clock))
 607                                                 continue;
 608                                         if (match_clock &&
 609                                             clock.p != match_clock->p)
 610                                                 continue;
 611
 612                                         this_err = abs(clock.dot - target);
 613                                         if (this_err < err) {
 614                                                 *best_clock = clock;
 615                                                 err = this_err;
 616                                         }
 617                                 }
 618                         }
 619                 }
 620         }
 621
 622         return (err != target);
 623 }
 624
 625 static bool
 626 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                    int target, int refclk, intel_clock_t *match_clock,
 628                    intel_clock_t *best_clock)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         intel_clock_t clock;
 632         int max_n;
 633         bool found;
 634         /* approximately equals target * 0.00585 */
 635         int err_most = (target >> 8) + (target >> 9);
 636         found = false;
 637
 638         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 639                 if (intel_is_dual_link_lvds(dev))
 640                         clock.p2 = limit->p2.p2_fast;
 641                 else
 642                         clock.p2 = limit->p2.p2_slow;
 643         } else {
 644                 if (target < limit->p2.dot_limit)
 645                         clock.p2 = limit->p2.p2_slow;
 646                 else
 647                         clock.p2 = limit->p2.p2_fast;
 648         }
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651         max_n = limit->n.max;
 652         /* based on hardware requirement, prefer smaller n to precision */
 653         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 654                 /* based on hardware requirement, prefere larger m1,m2 */
 655                 for (clock.m1 = limit->m1.max;
 656                      clock.m1 >= limit->m1.min; clock.m1--) {
 657                         for (clock.m2 = limit->m2.max;
 658                              clock.m2 >= limit->m2.min; clock.m2--) {
 659                                 for (clock.p1 = limit->p1.max;
 660                                      clock.p1 >= limit->p1.min; clock.p1--) {
 661                                         int this_err;
 662
 663                                         i9xx_clock(refclk, &clock);
 664                                         if (!intel_PLL_is_valid(dev, limit,
 665                                                                 &clock))
 666                                                 continue;
 667
 668                                         this_err = abs(clock.dot - target);
 669                                         if (this_err < err_most) {
 670                                                 *best_clock = clock;
 671                                                 err_most = this_err;
 672                                                 max_n = clock.n;
 673                                                 found = true;
 674                                         }
 675                                 }
 676                         }
 677                 }
 678         }
 679         return found;
 680 }
 681
 682 static bool
 683 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                    int target, int refclk, intel_clock_t *match_clock,
 685                    intel_clock_t *best_clock)
 686 {
 687         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 688         u32 m, n, fastclk;
 689         u32 updrate, minupdate, fracbits, p;
 690         unsigned long bestppm, ppm, absppm;
 691         int dotclk, flag;
 692
 693         flag = 0;
 694         dotclk = target * 1000;
 695         bestppm = 1000000;
 696         ppm = absppm = 0;
 697         fastclk = dotclk / (2*100);
 698         updrate = 0;
 699         minupdate = 19200;
 700         fracbits = 1;
 701         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 702         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 703
 704         /* based on hardware requirement, prefer smaller n to precision */
 705         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 706                 updrate = refclk / n;
 707                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 708                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 709                                 if (p2 > 10)
 710                                         p2 = p2 - 1;
 711                                 p = p1 * p2;
 712                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 713                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 714                                         m2 = (((2*(fastclk * p * n / m1 )) +
 715                                                refclk) / (2*refclk));
 716                                         m = m1 * m2;
 717                                         vco = updrate * m;
 718                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 719                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 720                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 721                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 722                                                         bestppm = 0;
 723                                                         flag = 1;
 724                                                 }
 725                                                 if (absppm < bestppm - 10) {
 726                                                         bestppm = absppm;
 727                                                         flag = 1;
 728                                                 }
 729                                                 if (flag) {
 730                                                         bestn = n;
 731                                                         bestm1 = m1;
 732                                                         bestm2 = m2;
 733                                                         bestp1 = p1;
 734                                                         bestp2 = p2;
 735                                                         flag = 0;
 736                                                 }
 737                                         }
 738                                 }
 739                         }
 740                 }
 741         }
 742         best_clock->n = bestn;
 743         best_clock->m1 = bestm1;
 744         best_clock->m2 = bestm2;
 745         best_clock->p1 = bestp1;
 746         best_clock->p2 = bestp2;
 747
 748         return true;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPEFRAME(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (INTEL_INFO(dev)->gen >= 5) {
 785                 ironlake_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 /*
 813  * intel_wait_for_pipe_off - wait for pipe to turn off
 814  * @dev: drm device
 815  * @pipe: pipe to wait for
 816  *
 817  * After disabling a pipe, we can't wait for vblank in the usual way,
 818  * spinning on the vblank interrupt status bit, since we won't actually
 819  * see an interrupt when the pipe is disabled.
 820  *
 821  * On Gen4 and above:
 822  *   wait for the pipe register state bit to turn off
 823  *
 824  * Otherwise:
 825  *   wait for the display line value to settle (it usually
 826  *   ends up stopping at the start of the next frame).
 827  *
 828  */
 829 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 830 {
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 833                                                                       pipe);
 834
 835         if (INTEL_INFO(dev)->gen >= 4) {
 836                 int reg = PIPECONF(cpu_transcoder);
 837
 838                 /* Wait for the Pipe State to go off */
 839                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 840                              100))
 841                         WARN(1, "pipe_off wait timed out\n");
 842         } else {
 843                 u32 last_line, line_mask;
 844                 int reg = PIPEDSL(pipe);
 845                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 846
 847                 if (IS_GEN2(dev))
 848                         line_mask = DSL_LINEMASK_GEN2;
 849                 else
 850                         line_mask = DSL_LINEMASK_GEN3;
 851
 852                 /* Wait for the display line to settle */
 853                 do {
 854                         last_line = I915_READ(reg) & line_mask;
 855                         mdelay(5);
 856                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 857                          time_after(timeout, jiffies));
 858                 if (time_after(jiffies, timeout))
 859                         WARN(1, "pipe_off wait timed out\n");
 860         }
 861 }
 862
 863 /*
 864  * ibx_digital_port_connected - is the specified port connected?
 865  * @dev_priv: i915 private structure
 866  * @port: the port to test
 867  *
 868  * Returns true if @port is connected, false otherwise.
 869  */
 870 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 871                                 struct intel_digital_port *port)
 872 {
 873         u32 bit;
 874
 875         if (HAS_PCH_IBX(dev_priv->dev)) {
 876                 switch(port->port) {
 877                 case PORT_B:
 878                         bit = SDE_PORTB_HOTPLUG;
 879                         break;
 880                 case PORT_C:
 881                         bit = SDE_PORTC_HOTPLUG;
 882                         break;
 883                 case PORT_D:
 884                         bit = SDE_PORTD_HOTPLUG;
 885                         break;
 886                 default:
 887                         return true;
 888                 }
 889         } else {
 890                 switch(port->port) {
 891                 case PORT_B:
 892                         bit = SDE_PORTB_HOTPLUG_CPT;
 893                         break;
 894                 case PORT_C:
 895                         bit = SDE_PORTC_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_D:
 898                         bit = SDE_PORTD_HOTPLUG_CPT;
 899                         break;
 900                 default:
 901                         return true;
 902                 }
 903         }
 904
 905         return I915_READ(SDEISR) & bit;
 906 }
 907
 908 static const char *state_string(bool enabled)
 909 {
 910         return enabled ? "on" : "off";
 911 }
 912
 913 /* Only for pre-ILK configs */
 914 void assert_pll(struct drm_i915_private *dev_priv,
 915                 enum pipe pipe, bool state)
 916 {
 917         int reg;
 918         u32 val;
 919         bool cur_state;
 920
 921         reg = DPLL(pipe);
 922         val = I915_READ(reg);
 923         cur_state = !!(val & DPLL_VCO_ENABLE);
 924         WARN(cur_state != state,
 925              "PLL state assertion failure (expected %s, current %s)\n",
 926              state_string(state), state_string(cur_state));
 927 }
 928
 929 struct intel_shared_dpll *
 930 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 931 {
 932         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 933
 934         if (crtc->config.shared_dpll < 0)
 935                 return NULL;
 936
 937         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 938 }
 939
 940 /* For ILK+ */
 941 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 942                         struct intel_shared_dpll *pll,
 943                         bool state)
 944 {
 945         bool cur_state;
 946         struct intel_dpll_hw_state hw_state;
 947
 948         if (HAS_PCH_LPT(dev_priv->dev)) {
 949                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 950                 return;
 951         }
 952
 953         if (WARN (!pll,
 954                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 955                 return;
 956
 957         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 958         WARN(cur_state != state,
 959              "%s assertion failure (expected %s, current %s)\n",
 960              pll->name, state_string(state), state_string(cur_state));
 961 }
 962
 963 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 964                           enum pipe pipe, bool state)
 965 {
 966         int reg;
 967         u32 val;
 968         bool cur_state;
 969         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 970                                                                       pipe);
 971
 972         if (HAS_DDI(dev_priv->dev)) {
 973                 /* DDI does not have a specific FDI_TX register */
 974                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 975                 val = I915_READ(reg);
 976                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 977         } else {
 978                 reg = FDI_TX_CTL(pipe);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & FDI_TX_ENABLE);
 981         }
 982         WARN(cur_state != state,
 983              "FDI TX state assertion failure (expected %s, current %s)\n",
 984              state_string(state), state_string(cur_state));
 985 }
 986 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 987 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 988
 989 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 990                           enum pipe pipe, bool state)
 991 {
 992         int reg;
 993         u32 val;
 994         bool cur_state;
 995
 996         reg = FDI_RX_CTL(pipe);
 997         val = I915_READ(reg);
 998         cur_state = !!(val & FDI_RX_ENABLE);
 999         WARN(cur_state != state,
1000              "FDI RX state assertion failure (expected %s, current %s)\n",
1001              state_string(state), state_string(cur_state));
1002 }
1003 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1004 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1005
1006 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1007                                       enum pipe pipe)
1008 {
1009         int reg;
1010         u32 val;
1011
1012         /* ILK FDI PLL is always enabled */
1013         if (dev_priv->info->gen == 5)
1014                 return;
1015
1016         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1017         if (HAS_DDI(dev_priv->dev))
1018                 return;
1019
1020         reg = FDI_TX_CTL(pipe);
1021         val = I915_READ(reg);
1022         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1023 }
1024
1025 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1026                        enum pipe pipe, bool state)
1027 {
1028         int reg;
1029         u32 val;
1030         bool cur_state;
1031
1032         reg = FDI_RX_CTL(pipe);
1033         val = I915_READ(reg);
1034         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1035         WARN(cur_state != state,
1036              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1037              state_string(state), state_string(cur_state));
1038 }
1039
1040 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1041                                   enum pipe pipe)
1042 {
1043         int pp_reg, lvds_reg;
1044         u32 val;
1045         enum pipe panel_pipe = PIPE_A;
1046         bool locked = true;
1047
1048         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1049                 pp_reg = PCH_PP_CONTROL;
1050                 lvds_reg = PCH_LVDS;
1051         } else {
1052                 pp_reg = PP_CONTROL;
1053                 lvds_reg = LVDS;
1054         }
1055
1056         val = I915_READ(pp_reg);
1057         if (!(val & PANEL_POWER_ON) ||
1058             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1059                 locked = false;
1060
1061         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1062                 panel_pipe = PIPE_B;
1063
1064         WARN(panel_pipe == pipe && locked,
1065              "panel assertion failure, pipe %c regs locked\n",
1066              pipe_name(pipe));
1067 }
1068
1069 void assert_pipe(struct drm_i915_private *dev_priv,
1070                  enum pipe pipe, bool state)
1071 {
1072         int reg;
1073         u32 val;
1074         bool cur_state;
1075         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1076                                                                       pipe);
1077
1078         /* if we need the pipe A quirk it must be always on */
1079         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1080                 state = true;
1081
1082         if (!intel_display_power_enabled(dev_priv->dev,
1083                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1084                 cur_state = false;
1085         } else {
1086                 reg = PIPECONF(cpu_transcoder);
1087                 val = I915_READ(reg);
1088                 cur_state = !!(val & PIPECONF_ENABLE);
1089         }
1090
1091         WARN(cur_state != state,
1092              "pipe %c assertion failure (expected %s, current %s)\n",
1093              pipe_name(pipe), state_string(state), state_string(cur_state));
1094 }
1095
1096 static void assert_plane(struct drm_i915_private *dev_priv,
1097                          enum plane plane, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = DSPCNTR(plane);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1106         WARN(cur_state != state,
1107              "plane %c assertion failure (expected %s, current %s)\n",
1108              plane_name(plane), state_string(state), state_string(cur_state));
1109 }
1110
1111 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1112 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1113
1114 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1115                                    enum pipe pipe)
1116 {
1117         struct drm_device *dev = dev_priv->dev;
1118         int reg, i;
1119         u32 val;
1120         int cur_pipe;
1121
1122         /* Primary planes are fixed to pipes on gen4+ */
1123         if (INTEL_INFO(dev)->gen >= 4) {
1124                 reg = DSPCNTR(pipe);
1125                 val = I915_READ(reg);
1126                 WARN((val & DISPLAY_PLANE_ENABLE),
1127                      "plane %c assertion failure, should be disabled but not\n",
1128                      plane_name(pipe));
1129                 return;
1130         }
1131
1132         /* Need to check both planes against the pipe */
1133         for_each_pipe(i) {
1134                 reg = DSPCNTR(i);
1135                 val = I915_READ(reg);
1136                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1137                         DISPPLANE_SEL_PIPE_SHIFT;
1138                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1139                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1140                      plane_name(i), pipe_name(pipe));
1141         }
1142 }
1143
1144 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1145                                     enum pipe pipe)
1146 {
1147         struct drm_device *dev = dev_priv->dev;
1148         int reg, i;
1149         u32 val;
1150
1151         if (IS_VALLEYVIEW(dev)) {
1152                 for (i = 0; i < dev_priv->num_plane; i++) {
1153                         reg = SPCNTR(pipe, i);
1154                         val = I915_READ(reg);
1155                         WARN((val & SP_ENABLE),
1156                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1157                              sprite_name(pipe, i), pipe_name(pipe));
1158                 }
1159         } else if (INTEL_INFO(dev)->gen >= 7) {
1160                 reg = SPRCTL(pipe);
1161                 val = I915_READ(reg);
1162                 WARN((val & SPRITE_ENABLE),
1163                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1164                      plane_name(pipe), pipe_name(pipe));
1165         } else if (INTEL_INFO(dev)->gen >= 5) {
1166                 reg = DVSCNTR(pipe);
1167                 val = I915_READ(reg);
1168                 WARN((val & DVS_ENABLE),
1169                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(pipe), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1175 {
1176         u32 val;
1177         bool enabled;
1178
1179         if (HAS_PCH_LPT(dev_priv->dev)) {
1180                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1181                 return;
1182         }
1183
1184         val = I915_READ(PCH_DREF_CONTROL);
1185         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1186                             DREF_SUPERSPREAD_SOURCE_MASK));
1187         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1191                                            enum pipe pipe)
1192 {
1193         int reg;
1194         u32 val;
1195         bool enabled;
1196
1197         reg = PCH_TRANSCONF(pipe);
1198         val = I915_READ(reg);
1199         enabled = !!(val & TRANS_ENABLE);
1200         WARN(enabled,
1201              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1202              pipe_name(pipe));
1203 }
1204
1205 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1206                             enum pipe pipe, u32 port_sel, u32 val)
1207 {
1208         if ((val & DP_PORT_EN) == 0)
1209                 return false;
1210
1211         if (HAS_PCH_CPT(dev_priv->dev)) {
1212                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1213                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1214                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1215                         return false;
1216         } else {
1217                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1218                         return false;
1219         }
1220         return true;
1221 }
1222
1223 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1224                               enum pipe pipe, u32 val)
1225 {
1226         if ((val & SDVO_ENABLE) == 0)
1227                 return false;
1228
1229         if (HAS_PCH_CPT(dev_priv->dev)) {
1230                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1231                         return false;
1232         } else {
1233                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1234                         return false;
1235         }
1236         return true;
1237 }
1238
1239 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1240                               enum pipe pipe, u32 val)
1241 {
1242         if ((val & LVDS_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1247                         return false;
1248         } else {
1249                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1250                         return false;
1251         }
1252         return true;
1253 }
1254
1255 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1256                               enum pipe pipe, u32 val)
1257 {
1258         if ((val & ADPA_DAC_ENABLE) == 0)
1259                 return false;
1260         if (HAS_PCH_CPT(dev_priv->dev)) {
1261                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1262                         return false;
1263         } else {
1264                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1265                         return false;
1266         }
1267         return true;
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271                                    enum pipe pipe, int reg, u32 port_sel)
1272 {
1273         u32 val = I915_READ(reg);
1274         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1275              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276              reg, pipe_name(pipe));
1277
1278         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1279              && (val & DP_PIPEB_SELECT),
1280              "IBX PCH dp port still using transcoder B\n");
1281 }
1282
1283 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1284                                      enum pipe pipe, int reg)
1285 {
1286         u32 val = I915_READ(reg);
1287         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1288              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1289              reg, pipe_name(pipe));
1290
1291         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1292              && (val & SDVO_PIPE_B_SELECT),
1293              "IBX PCH hdmi port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1297                                       enum pipe pipe)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1305
1306         reg = PCH_ADPA;
1307         val = I915_READ(reg);
1308         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1309              "PCH VGA enabled on transcoder %c, should be disabled\n",
1310              pipe_name(pipe));
1311
1312         reg = PCH_LVDS;
1313         val = I915_READ(reg);
1314         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1315              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1316              pipe_name(pipe));
1317
1318         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1321 }
1322
1323 static void vlv_enable_pll(struct intel_crtc *crtc)
1324 {
1325         struct drm_device *dev = crtc->base.dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         int reg = DPLL(crtc->pipe);
1328         u32 dpll = crtc->config.dpll_hw_state.dpll;
1329
1330         assert_pipe_disabled(dev_priv, crtc->pipe);
1331
1332         /* No really, not for ILK+ */
1333         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1334
1335         /* PLL is protected by panel, make sure we can write it */
1336         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1337                 assert_panel_unlocked(dev_priv, crtc->pipe);
1338
1339         I915_WRITE(reg, dpll);
1340         POSTING_READ(reg);
1341         udelay(150);
1342
1343         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1344                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1345
1346         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1347         POSTING_READ(DPLL_MD(crtc->pipe));
1348
1349         /* We do this three times for luck */
1350         I915_WRITE(reg, dpll);
1351         POSTING_READ(reg);
1352         udelay(150); /* wait for warmup */
1353         I915_WRITE(reg, dpll);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, dpll);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359 }
1360
1361 static void i9xx_enable_pll(struct intel_crtc *crtc)
1362 {
1363         struct drm_device *dev = crtc->base.dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         int reg = DPLL(crtc->pipe);
1366         u32 dpll = crtc->config.dpll_hw_state.dpll;
1367
1368         assert_pipe_disabled(dev_priv, crtc->pipe);
1369
1370         /* No really, not for ILK+ */
1371         BUG_ON(dev_priv->info->gen >= 5);
1372
1373         /* PLL is protected by panel, make sure we can write it */
1374         if (IS_MOBILE(dev) && !IS_I830(dev))
1375                 assert_panel_unlocked(dev_priv, crtc->pipe);
1376
1377         I915_WRITE(reg, dpll);
1378
1379         /* Wait for the clocks to stabilize. */
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (INTEL_INFO(dev)->gen >= 4) {
1384                 I915_WRITE(DPLL_MD(crtc->pipe),
1385                            crtc->config.dpll_hw_state.dpll_md);
1386         } else {
1387                 /* The pixel multiplier can only be updated once the
1388                  * DPLL is enabled and the clocks are stable.
1389                  *
1390                  * So write it again.
1391                  */
1392                 I915_WRITE(reg, dpll);
1393         }
1394
1395         /* We do this three times for luck */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405 }
1406
1407 /**
1408  * i9xx_disable_pll - disable a PLL
1409  * @dev_priv: i915 private structure
1410  * @pipe: pipe PLL to disable
1411  *
1412  * Disable the PLL for @pipe, making sure the pipe is off first.
1413  *
1414  * Note!  This is for pre-ILK only.
1415  */
1416 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1417 {
1418         /* Don't disable pipe A or pipe A PLLs if needed */
1419         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1420                 return;
1421
1422         /* Make sure the pipe isn't still relying on us */
1423         assert_pipe_disabled(dev_priv, pipe);
1424
1425         I915_WRITE(DPLL(pipe), 0);
1426         POSTING_READ(DPLL(pipe));
1427 }
1428
1429 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1430 {
1431         u32 port_mask;
1432
1433         if (!port)
1434                 port_mask = DPLL_PORTB_READY_MASK;
1435         else
1436                 port_mask = DPLL_PORTC_READY_MASK;
1437
1438         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1439                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1440                      'B' + port, I915_READ(DPLL(0)));
1441 }
1442
1443 /**
1444  * ironlake_enable_shared_dpll - enable PCH PLL
1445  * @dev_priv: i915 private structure
1446  * @pipe: pipe PLL to enable
1447  *
1448  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1449  * drives the transcoder clock.
1450  */
1451 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1452 {
1453         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1454         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1455
1456         /* PCH PLLs only available on ILK, SNB and IVB */
1457         BUG_ON(dev_priv->info->gen < 5);
1458         if (WARN_ON(pll == NULL))
1459                 return;
1460
1461         if (WARN_ON(pll->refcount == 0))
1462                 return;
1463
1464         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1465                       pll->name, pll->active, pll->on,
1466                       crtc->base.base.id);
1467
1468         if (pll->active++) {
1469                 WARN_ON(!pll->on);
1470                 assert_shared_dpll_enabled(dev_priv, pll);
1471                 return;
1472         }
1473         WARN_ON(pll->on);
1474
1475         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1476         pll->enable(dev_priv, pll);
1477         pll->on = true;
1478 }
1479
1480 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1481 {
1482         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1483         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1484
1485         /* PCH only available on ILK+ */
1486         BUG_ON(dev_priv->info->gen < 5);
1487         if (WARN_ON(pll == NULL))
1488                return;
1489
1490         if (WARN_ON(pll->refcount == 0))
1491                 return;
1492
1493         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1494                       pll->name, pll->active, pll->on,
1495                       crtc->base.base.id);
1496
1497         if (WARN_ON(pll->active == 0)) {
1498                 assert_shared_dpll_disabled(dev_priv, pll);
1499                 return;
1500         }
1501
1502         assert_shared_dpll_enabled(dev_priv, pll);
1503         WARN_ON(!pll->on);
1504         if (--pll->active)
1505                 return;
1506
1507         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1508         pll->disable(dev_priv, pll);
1509         pll->on = false;
1510 }
1511
1512 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1513                                            enum pipe pipe)
1514 {
1515         struct drm_device *dev = dev_priv->dev;
1516         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1518         uint32_t reg, val, pipeconf_val;
1519
1520         /* PCH only available on ILK+ */
1521         BUG_ON(dev_priv->info->gen < 5);
1522
1523         /* Make sure PCH DPLL is enabled */
1524         assert_shared_dpll_enabled(dev_priv,
1525                                    intel_crtc_to_shared_dpll(intel_crtc));
1526
1527         /* FDI must be feeding us bits for PCH ports */
1528         assert_fdi_tx_enabled(dev_priv, pipe);
1529         assert_fdi_rx_enabled(dev_priv, pipe);
1530
1531         if (HAS_PCH_CPT(dev)) {
1532                 /* Workaround: Set the timing override bit before enabling the
1533                  * pch transcoder. */
1534                 reg = TRANS_CHICKEN2(pipe);
1535                 val = I915_READ(reg);
1536                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1537                 I915_WRITE(reg, val);
1538         }
1539
1540         reg = PCH_TRANSCONF(pipe);
1541         val = I915_READ(reg);
1542         pipeconf_val = I915_READ(PIPECONF(pipe));
1543
1544         if (HAS_PCH_IBX(dev_priv->dev)) {
1545                 /*
1546                  * make the BPC in transcoder be consistent with
1547                  * that in pipeconf reg.
1548                  */
1549                 val &= ~PIPECONF_BPC_MASK;
1550                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1551         }
1552
1553         val &= ~TRANS_INTERLACE_MASK;
1554         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1555                 if (HAS_PCH_IBX(dev_priv->dev) &&
1556                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1557                         val |= TRANS_LEGACY_INTERLACED_ILK;
1558                 else
1559                         val |= TRANS_INTERLACED;
1560         else
1561                 val |= TRANS_PROGRESSIVE;
1562
1563         I915_WRITE(reg, val | TRANS_ENABLE);
1564         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1565                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1566 }
1567
1568 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1569                                       enum transcoder cpu_transcoder)
1570 {
1571         u32 val, pipeconf_val;
1572
1573         /* PCH only available on ILK+ */
1574         BUG_ON(dev_priv->info->gen < 5);
1575
1576         /* FDI must be feeding us bits for PCH ports */
1577         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1578         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1579
1580         /* Workaround: set timing override bit. */
1581         val = I915_READ(_TRANSA_CHICKEN2);
1582         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1583         I915_WRITE(_TRANSA_CHICKEN2, val);
1584
1585         val = TRANS_ENABLE;
1586         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1587
1588         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1589             PIPECONF_INTERLACED_ILK)
1590                 val |= TRANS_INTERLACED;
1591         else
1592                 val |= TRANS_PROGRESSIVE;
1593
1594         I915_WRITE(LPT_TRANSCONF, val);
1595         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1596                 DRM_ERROR("Failed to enable PCH transcoder\n");
1597 }
1598
1599 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1600                                             enum pipe pipe)
1601 {
1602         struct drm_device *dev = dev_priv->dev;
1603         uint32_t reg, val;
1604
1605         /* FDI relies on the transcoder */
1606         assert_fdi_tx_disabled(dev_priv, pipe);
1607         assert_fdi_rx_disabled(dev_priv, pipe);
1608
1609         /* Ports must be off as well */
1610         assert_pch_ports_disabled(dev_priv, pipe);
1611
1612         reg = PCH_TRANSCONF(pipe);
1613         val = I915_READ(reg);
1614         val &= ~TRANS_ENABLE;
1615         I915_WRITE(reg, val);
1616         /* wait for PCH transcoder off, transcoder state */
1617         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1618                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1619
1620         if (!HAS_PCH_IBX(dev)) {
1621                 /* Workaround: Clear the timing override chicken bit again. */
1622                 reg = TRANS_CHICKEN2(pipe);
1623                 val = I915_READ(reg);
1624                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1625                 I915_WRITE(reg, val);
1626         }
1627 }
1628
1629 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1630 {
1631         u32 val;
1632
1633         val = I915_READ(LPT_TRANSCONF);
1634         val &= ~TRANS_ENABLE;
1635         I915_WRITE(LPT_TRANSCONF, val);
1636         /* wait for PCH transcoder off, transcoder state */
1637         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1638                 DRM_ERROR("Failed to disable PCH transcoder\n");
1639
1640         /* Workaround: clear timing override bit. */
1641         val = I915_READ(_TRANSA_CHICKEN2);
1642         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1643         I915_WRITE(_TRANSA_CHICKEN2, val);
1644 }
1645
1646 /**
1647  * intel_enable_pipe - enable a pipe, asserting requirements
1648  * @dev_priv: i915 private structure
1649  * @pipe: pipe to enable
1650  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1651  *
1652  * Enable @pipe, making sure that various hardware specific requirements
1653  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1654  *
1655  * @pipe should be %PIPE_A or %PIPE_B.
1656  *
1657  * Will wait until the pipe is actually running (i.e. first vblank) before
1658  * returning.
1659  */
1660 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1661                               bool pch_port)
1662 {
1663         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1664                                                                       pipe);
1665         enum pipe pch_transcoder;
1666         int reg;
1667         u32 val;
1668
1669         assert_planes_disabled(dev_priv, pipe);
1670         assert_sprites_disabled(dev_priv, pipe);
1671
1672         if (HAS_PCH_LPT(dev_priv->dev))
1673                 pch_transcoder = TRANSCODER_A;
1674         else
1675                 pch_transcoder = pipe;
1676
1677         /*
1678          * A pipe without a PLL won't actually be able to drive bits from
1679          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1680          * need the check.
1681          */
1682         if (!HAS_PCH_SPLIT(dev_priv->dev))
1683                 assert_pll_enabled(dev_priv, pipe);
1684         else {
1685                 if (pch_port) {
1686                         /* if driving the PCH, we need FDI enabled */
1687                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1688                         assert_fdi_tx_pll_enabled(dev_priv,
1689                                                   (enum pipe) cpu_transcoder);
1690                 }
1691                 /* FIXME: assert CPU port conditions for SNB+ */
1692         }
1693
1694         reg = PIPECONF(cpu_transcoder);
1695         val = I915_READ(reg);
1696         if (val & PIPECONF_ENABLE)
1697                 return;
1698
1699         I915_WRITE(reg, val | PIPECONF_ENABLE);
1700         intel_wait_for_vblank(dev_priv->dev, pipe);
1701 }
1702
1703 /**
1704  * intel_disable_pipe - disable a pipe, asserting requirements
1705  * @dev_priv: i915 private structure
1706  * @pipe: pipe to disable
1707  *
1708  * Disable @pipe, making sure that various hardware specific requirements
1709  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1710  *
1711  * @pipe should be %PIPE_A or %PIPE_B.
1712  *
1713  * Will wait until the pipe has shut down before returning.
1714  */
1715 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1716                                enum pipe pipe)
1717 {
1718         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1719                                                                       pipe);
1720         int reg;
1721         u32 val;
1722
1723         /*
1724          * Make sure planes won't keep trying to pump pixels to us,
1725          * or we might hang the display.
1726          */
1727         assert_planes_disabled(dev_priv, pipe);
1728         assert_sprites_disabled(dev_priv, pipe);
1729
1730         /* Don't disable pipe A or pipe A PLLs if needed */
1731         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1732                 return;
1733
1734         reg = PIPECONF(cpu_transcoder);
1735         val = I915_READ(reg);
1736         if ((val & PIPECONF_ENABLE) == 0)
1737                 return;
1738
1739         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1740         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1741 }
1742
1743 /*
1744  * Plane regs are double buffered, going from enabled->disabled needs a
1745  * trigger in order to latch.  The display address reg provides this.
1746  */
1747 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1748                                       enum plane plane)
1749 {
1750         if (dev_priv->info->gen >= 4)
1751                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1752         else
1753                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1754 }
1755
1756 /**
1757  * intel_enable_plane - enable a display plane on a given pipe
1758  * @dev_priv: i915 private structure
1759  * @plane: plane to enable
1760  * @pipe: pipe being fed
1761  *
1762  * Enable @plane on @pipe, making sure that @pipe is running first.
1763  */
1764 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1765                                enum plane plane, enum pipe pipe)
1766 {
1767         int reg;
1768         u32 val;
1769
1770         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1771         assert_pipe_enabled(dev_priv, pipe);
1772
1773         reg = DSPCNTR(plane);
1774         val = I915_READ(reg);
1775         if (val & DISPLAY_PLANE_ENABLE)
1776                 return;
1777
1778         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1779         intel_flush_display_plane(dev_priv, plane);
1780         intel_wait_for_vblank(dev_priv->dev, pipe);
1781 }
1782
1783 /**
1784  * intel_disable_plane - disable a display plane
1785  * @dev_priv: i915 private structure
1786  * @plane: plane to disable
1787  * @pipe: pipe consuming the data
1788  *
1789  * Disable @plane; should be an independent operation.
1790  */
1791 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1792                                 enum plane plane, enum pipe pipe)
1793 {
1794         int reg;
1795         u32 val;
1796
1797         reg = DSPCNTR(plane);
1798         val = I915_READ(reg);
1799         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1800                 return;
1801
1802         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1803         intel_flush_display_plane(dev_priv, plane);
1804         intel_wait_for_vblank(dev_priv->dev, pipe);
1805 }
1806
1807 static bool need_vtd_wa(struct drm_device *dev)
1808 {
1809 #ifdef CONFIG_INTEL_IOMMU
1810         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1811                 return true;
1812 #endif
1813         return false;
1814 }
1815
1816 int
1817 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1818                            struct drm_i915_gem_object *obj,
1819                            struct intel_ring_buffer *pipelined)
1820 {
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         u32 alignment;
1823         int ret;
1824
1825         switch (obj->tiling_mode) {
1826         case I915_TILING_NONE:
1827                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1828                         alignment = 128 * 1024;
1829                 else if (INTEL_INFO(dev)->gen >= 4)
1830                         alignment = 4 * 1024;
1831                 else
1832                         alignment = 64 * 1024;
1833                 break;
1834         case I915_TILING_X:
1835                 /* pin() will align the object as required by fence */
1836                 alignment = 0;
1837                 break;
1838         case I915_TILING_Y:
1839                 /* Despite that we check this in framebuffer_init userspace can
1840                  * screw us over and change the tiling after the fact. Only
1841                  * pinned buffers can't change their tiling. */
1842                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1843                 return -EINVAL;
1844         default:
1845                 BUG();
1846         }
1847
1848         /* Note that the w/a also requires 64 PTE of padding following the
1849          * bo. We currently fill all unused PTE with the shadow page and so
1850          * we should always have valid PTE following the scanout preventing
1851          * the VT-d warning.
1852          */
1853         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1854                 alignment = 256 * 1024;
1855
1856         dev_priv->mm.interruptible = false;
1857         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1858         if (ret)
1859                 goto err_interruptible;
1860
1861         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1862          * fence, whereas 965+ only requires a fence if using
1863          * framebuffer compression.  For simplicity, we always install
1864          * a fence as the cost is not that onerous.
1865          */
1866         ret = i915_gem_object_get_fence(obj);
1867         if (ret)
1868                 goto err_unpin;
1869
1870         i915_gem_object_pin_fence(obj);
1871
1872         dev_priv->mm.interruptible = true;
1873         return 0;
1874
1875 err_unpin:
1876         i915_gem_object_unpin(obj);
1877 err_interruptible:
1878         dev_priv->mm.interruptible = true;
1879         return ret;
1880 }
1881
1882 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1883 {
1884         i915_gem_object_unpin_fence(obj);
1885         i915_gem_object_unpin(obj);
1886 }
1887
1888 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1889  * is assumed to be a power-of-two. */
1890 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1891                                              unsigned int tiling_mode,
1892                                              unsigned int cpp,
1893                                              unsigned int pitch)
1894 {
1895         if (tiling_mode != I915_TILING_NONE) {
1896                 unsigned int tile_rows, tiles;
1897
1898                 tile_rows = *y / 8;
1899                 *y %= 8;
1900
1901                 tiles = *x / (512/cpp);
1902                 *x %= 512/cpp;
1903
1904                 return tile_rows * pitch * 8 + tiles * 4096;
1905         } else {
1906                 unsigned int offset;
1907
1908                 offset = *y * pitch + *x * cpp;
1909                 *y = 0;
1910                 *x = (offset & 4095) / cpp;
1911                 return offset & -4096;
1912         }
1913 }
1914
1915 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1916                              int x, int y)
1917 {
1918         struct drm_device *dev = crtc->dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         struct intel_framebuffer *intel_fb;
1922         struct drm_i915_gem_object *obj;
1923         int plane = intel_crtc->plane;
1924         unsigned long linear_offset;
1925         u32 dspcntr;
1926         u32 reg;
1927
1928         switch (plane) {
1929         case 0:
1930         case 1:
1931                 break;
1932         default:
1933                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1934                 return -EINVAL;
1935         }
1936
1937         intel_fb = to_intel_framebuffer(fb);
1938         obj = intel_fb->obj;
1939
1940         reg = DSPCNTR(plane);
1941         dspcntr = I915_READ(reg);
1942         /* Mask out pixel format bits in case we change it */
1943         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1944         switch (fb->pixel_format) {
1945         case DRM_FORMAT_C8:
1946                 dspcntr |= DISPPLANE_8BPP;
1947                 break;
1948         case DRM_FORMAT_XRGB1555:
1949         case DRM_FORMAT_ARGB1555:
1950                 dspcntr |= DISPPLANE_BGRX555;
1951                 break;
1952         case DRM_FORMAT_RGB565:
1953                 dspcntr |= DISPPLANE_BGRX565;
1954                 break;
1955         case DRM_FORMAT_XRGB8888:
1956         case DRM_FORMAT_ARGB8888:
1957                 dspcntr |= DISPPLANE_BGRX888;
1958                 break;
1959         case DRM_FORMAT_XBGR8888:
1960         case DRM_FORMAT_ABGR8888:
1961                 dspcntr |= DISPPLANE_RGBX888;
1962                 break;
1963         case DRM_FORMAT_XRGB2101010:
1964         case DRM_FORMAT_ARGB2101010:
1965                 dspcntr |= DISPPLANE_BGRX101010;
1966                 break;
1967         case DRM_FORMAT_XBGR2101010:
1968         case DRM_FORMAT_ABGR2101010:
1969                 dspcntr |= DISPPLANE_RGBX101010;
1970                 break;
1971         default:
1972                 BUG();
1973         }
1974
1975         if (INTEL_INFO(dev)->gen >= 4) {
1976                 if (obj->tiling_mode != I915_TILING_NONE)
1977                         dspcntr |= DISPPLANE_TILED;
1978                 else
1979                         dspcntr &= ~DISPPLANE_TILED;
1980         }
1981
1982         if (IS_G4X(dev))
1983                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1984
1985         I915_WRITE(reg, dspcntr);
1986
1987         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1988
1989         if (INTEL_INFO(dev)->gen >= 4) {
1990                 intel_crtc->dspaddr_offset =
1991                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1992                                                        fb->bits_per_pixel / 8,
1993                                                        fb->pitches[0]);
1994                 linear_offset -= intel_crtc->dspaddr_offset;
1995         } else {
1996                 intel_crtc->dspaddr_offset = linear_offset;
1997         }
1998
1999         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2000                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2001                       fb->pitches[0]);
2002         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2003         if (INTEL_INFO(dev)->gen >= 4) {
2004                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2005                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2006                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2007                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2008         } else
2009                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2010         POSTING_READ(reg);
2011
2012         return 0;
2013 }
2014
2015 static int ironlake_update_plane(struct drm_crtc *crtc,
2016                                  struct drm_framebuffer *fb, int x, int y)
2017 {
2018         struct drm_device *dev = crtc->dev;
2019         struct drm_i915_private *dev_priv = dev->dev_private;
2020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021         struct intel_framebuffer *intel_fb;
2022         struct drm_i915_gem_object *obj;
2023         int plane = intel_crtc->plane;
2024         unsigned long linear_offset;
2025         u32 dspcntr;
2026         u32 reg;
2027
2028         switch (plane) {
2029         case 0:
2030         case 1:
2031         case 2:
2032                 break;
2033         default:
2034                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2035                 return -EINVAL;
2036         }
2037
2038         intel_fb = to_intel_framebuffer(fb);
2039         obj = intel_fb->obj;
2040
2041         reg = DSPCNTR(plane);
2042         dspcntr = I915_READ(reg);
2043         /* Mask out pixel format bits in case we change it */
2044         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045         switch (fb->pixel_format) {
2046         case DRM_FORMAT_C8:
2047                 dspcntr |= DISPPLANE_8BPP;
2048                 break;
2049         case DRM_FORMAT_RGB565:
2050                 dspcntr |= DISPPLANE_BGRX565;
2051                 break;
2052         case DRM_FORMAT_XRGB8888:
2053         case DRM_FORMAT_ARGB8888:
2054                 dspcntr |= DISPPLANE_BGRX888;
2055                 break;
2056         case DRM_FORMAT_XBGR8888:
2057         case DRM_FORMAT_ABGR8888:
2058                 dspcntr |= DISPPLANE_RGBX888;
2059                 break;
2060         case DRM_FORMAT_XRGB2101010:
2061         case DRM_FORMAT_ARGB2101010:
2062                 dspcntr |= DISPPLANE_BGRX101010;
2063                 break;
2064         case DRM_FORMAT_XBGR2101010:
2065         case DRM_FORMAT_ABGR2101010:
2066                 dspcntr |= DISPPLANE_RGBX101010;
2067                 break;
2068         default:
2069                 BUG();
2070         }
2071
2072         if (obj->tiling_mode != I915_TILING_NONE)
2073                 dspcntr |= DISPPLANE_TILED;
2074         else
2075                 dspcntr &= ~DISPPLANE_TILED;
2076
2077         /* must disable */
2078         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2079
2080         I915_WRITE(reg, dspcntr);
2081
2082         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2083         intel_crtc->dspaddr_offset =
2084                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2085                                                fb->bits_per_pixel / 8,
2086                                                fb->pitches[0]);
2087         linear_offset -= intel_crtc->dspaddr_offset;
2088
2089         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2090                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2091                       fb->pitches[0]);
2092         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2093         I915_MODIFY_DISPBASE(DSPSURF(plane),
2094                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2095         if (IS_HASWELL(dev)) {
2096                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2097         } else {
2098                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2099                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2100         }
2101         POSTING_READ(reg);
2102
2103         return 0;
2104 }
2105
2106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2107 static int
2108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2109                            int x, int y, enum mode_set_atomic state)
2110 {
2111         struct drm_device *dev = crtc->dev;
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114         if (dev_priv->display.disable_fbc)
2115                 dev_priv->display.disable_fbc(dev);
2116         intel_increase_pllclock(crtc);
2117
2118         return dev_priv->display.update_plane(crtc, fb, x, y);
2119 }
2120
2121 void intel_display_handle_reset(struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct drm_crtc *crtc;
2125
2126         /*
2127          * Flips in the rings have been nuked by the reset,
2128          * so complete all pending flips so that user space
2129          * will get its events and not get stuck.
2130          *
2131          * Also update the base address of all primary
2132          * planes to the the last fb to make sure we're
2133          * showing the correct fb after a reset.
2134          *
2135          * Need to make two loops over the crtcs so that we
2136          * don't try to grab a crtc mutex before the
2137          * pending_flip_queue really got woken up.
2138          */
2139
2140         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2141                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2142                 enum plane plane = intel_crtc->plane;
2143
2144                 intel_prepare_page_flip(dev, plane);
2145                 intel_finish_page_flip_plane(dev, plane);
2146         }
2147
2148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150
2151                 mutex_lock(&crtc->mutex);
2152                 if (intel_crtc->active)
2153                         dev_priv->display.update_plane(crtc, crtc->fb,
2154                                                        crtc->x, crtc->y);
2155                 mutex_unlock(&crtc->mutex);
2156         }
2157 }
2158
2159 static int
2160 intel_finish_fb(struct drm_framebuffer *old_fb)
2161 {
2162         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2163         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2164         bool was_interruptible = dev_priv->mm.interruptible;
2165         int ret;
2166
2167         /* Big Hammer, we also need to ensure that any pending
2168          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2169          * current scanout is retired before unpinning the old
2170          * framebuffer.
2171          *
2172          * This should only fail upon a hung GPU, in which case we
2173          * can safely continue.
2174          */
2175         dev_priv->mm.interruptible = false;
2176         ret = i915_gem_object_finish_gpu(obj);
2177         dev_priv->mm.interruptible = was_interruptible;
2178
2179         return ret;
2180 }
2181
2182 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_master_private *master_priv;
2186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2187
2188         if (!dev->primary->master)
2189                 return;
2190
2191         master_priv = dev->primary->master->driver_priv;
2192         if (!master_priv->sarea_priv)
2193                 return;
2194
2195         switch (intel_crtc->pipe) {
2196         case 0:
2197                 master_priv->sarea_priv->pipeA_x = x;
2198                 master_priv->sarea_priv->pipeA_y = y;
2199                 break;
2200         case 1:
2201                 master_priv->sarea_priv->pipeB_x = x;
2202                 master_priv->sarea_priv->pipeB_y = y;
2203                 break;
2204         default:
2205                 break;
2206         }
2207 }
2208
2209 static int
2210 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2211                     struct drm_framebuffer *fb)
2212 {
2213         struct drm_device *dev = crtc->dev;
2214         struct drm_i915_private *dev_priv = dev->dev_private;
2215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216         struct drm_framebuffer *old_fb;
2217         int ret;
2218
2219         /* no fb bound */
2220         if (!fb) {
2221                 DRM_ERROR("No FB bound\n");
2222                 return 0;
2223         }
2224
2225         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2226                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2227                           plane_name(intel_crtc->plane),
2228                           INTEL_INFO(dev)->num_pipes);
2229                 return -EINVAL;
2230         }
2231
2232         mutex_lock(&dev->struct_mutex);
2233         ret = intel_pin_and_fence_fb_obj(dev,
2234                                          to_intel_framebuffer(fb)->obj,
2235                                          NULL);
2236         if (ret != 0) {
2237                 mutex_unlock(&dev->struct_mutex);
2238                 DRM_ERROR("pin & fence failed\n");
2239                 return ret;
2240         }
2241
2242         /* Update pipe size and adjust fitter if needed */
2243         if (i915_fastboot) {
2244                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2245                            ((crtc->mode.hdisplay - 1) << 16) |
2246                            (crtc->mode.vdisplay - 1));
2247                 if (!intel_crtc->config.pch_pfit.size &&
2248                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2249                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2250                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2251                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2253                 }
2254         }
2255
2256         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2257         if (ret) {
2258                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("failed to update base address\n");
2261                 return ret;
2262         }
2263
2264         old_fb = crtc->fb;
2265         crtc->fb = fb;
2266         crtc->x = x;
2267         crtc->y = y;
2268
2269         if (old_fb) {
2270                 if (intel_crtc->active && old_fb != fb)
2271                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2272                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2273         }
2274
2275         intel_update_fbc(dev);
2276         intel_edp_psr_update(dev);
2277         mutex_unlock(&dev->struct_mutex);
2278
2279         intel_crtc_update_sarea_pos(crtc, x, y);
2280
2281         return 0;
2282 }
2283
2284 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         u32 reg, temp;
2291
2292         /* enable normal train */
2293         reg = FDI_TX_CTL(pipe);
2294         temp = I915_READ(reg);
2295         if (IS_IVYBRIDGE(dev)) {
2296                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2297                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2298         } else {
2299                 temp &= ~FDI_LINK_TRAIN_NONE;
2300                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2301         }
2302         I915_WRITE(reg, temp);
2303
2304         reg = FDI_RX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         if (HAS_PCH_CPT(dev)) {
2307                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2308                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2309         } else {
2310                 temp &= ~FDI_LINK_TRAIN_NONE;
2311                 temp |= FDI_LINK_TRAIN_NONE;
2312         }
2313         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2314
2315         /* wait one idle pattern time */
2316         POSTING_READ(reg);
2317         udelay(1000);
2318
2319         /* IVB wants error correction enabled */
2320         if (IS_IVYBRIDGE(dev))
2321                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2322                            FDI_FE_ERRC_ENABLE);
2323 }
2324
2325 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2326 {
2327         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2328 }
2329
2330 static void ivb_modeset_global_resources(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *pipe_B_crtc =
2334                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2335         struct intel_crtc *pipe_C_crtc =
2336                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2337         uint32_t temp;
2338
2339         /*
2340          * When everything is off disable fdi C so that we could enable fdi B
2341          * with all lanes. Note that we don't care about enabled pipes without
2342          * an enabled pch encoder.
2343          */
2344         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2345             !pipe_has_enabled_pch(pipe_C_crtc)) {
2346                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2348
2349                 temp = I915_READ(SOUTH_CHICKEN1);
2350                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2351                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2352                 I915_WRITE(SOUTH_CHICKEN1, temp);
2353         }
2354 }
2355
2356 /* The FDI link training functions for ILK/Ibexpeak. */
2357 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         int plane = intel_crtc->plane;
2364         u32 reg, temp, tries;
2365
2366         /* FDI needs bits from pipe & plane first */
2367         assert_pipe_enabled(dev_priv, pipe);
2368         assert_plane_enabled(dev_priv, plane);
2369
2370         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2371            for train result */
2372         reg = FDI_RX_IMR(pipe);
2373         temp = I915_READ(reg);
2374         temp &= ~FDI_RX_SYMBOL_LOCK;
2375         temp &= ~FDI_RX_BIT_LOCK;
2376         I915_WRITE(reg, temp);
2377         I915_READ(reg);
2378         udelay(150);
2379
2380         /* enable CPU FDI TX and PCH FDI RX */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2384         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_1;
2387         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2388
2389         reg = FDI_RX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2394
2395         POSTING_READ(reg);
2396         udelay(150);
2397
2398         /* Ironlake workaround, enable clock pointer after FDI enable*/
2399         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401                    FDI_RX_PHASE_SYNC_POINTER_EN);
2402
2403         reg = FDI_RX_IIR(pipe);
2404         for (tries = 0; tries < 5; tries++) {
2405                 temp = I915_READ(reg);
2406                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408                 if ((temp & FDI_RX_BIT_LOCK)) {
2409                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2410                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2411                         break;
2412                 }
2413         }
2414         if (tries == 5)
2415                 DRM_ERROR("FDI train 1 fail!\n");
2416
2417         /* Train 2 */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~FDI_LINK_TRAIN_NONE;
2421         temp |= FDI_LINK_TRAIN_PATTERN_2;
2422         I915_WRITE(reg, temp);
2423
2424         reg = FDI_RX_CTL(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_2;
2428         I915_WRITE(reg, temp);
2429
2430         POSTING_READ(reg);
2431         udelay(150);
2432
2433         reg = FDI_RX_IIR(pipe);
2434         for (tries = 0; tries < 5; tries++) {
2435                 temp = I915_READ(reg);
2436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438                 if (temp & FDI_RX_SYMBOL_LOCK) {
2439                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2441                         break;
2442                 }
2443         }
2444         if (tries == 5)
2445                 DRM_ERROR("FDI train 2 fail!\n");
2446
2447         DRM_DEBUG_KMS("FDI train done\n");
2448
2449 }
2450
2451 static const int snb_b_fdi_train_param[] = {
2452         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2456 };
2457
2458 /* The FDI link training functions for SNB/Cougarpoint. */
2459 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         u32 reg, temp, i, retry;
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474
2475         POSTING_READ(reg);
2476         udelay(150);
2477
2478         /* enable CPU FDI TX and PCH FDI RX */
2479         reg = FDI_TX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2482         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486         /* SNB-B */
2487         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2488         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2489
2490         I915_WRITE(FDI_RX_MISC(pipe),
2491                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2501         }
2502         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_BIT_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 1 fail!\n");
2533
2534         /* Train 2 */
2535         reg = FDI_TX_CTL(pipe);
2536         temp = I915_READ(reg);
2537         temp &= ~FDI_LINK_TRAIN_NONE;
2538         temp |= FDI_LINK_TRAIN_PATTERN_2;
2539         if (IS_GEN6(dev)) {
2540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541                 /* SNB-B */
2542                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2543         }
2544         I915_WRITE(reg, temp);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554         }
2555         I915_WRITE(reg, temp);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         for (i = 0; i < 4; i++) {
2561                 reg = FDI_TX_CTL(pipe);
2562                 temp = I915_READ(reg);
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 temp |= snb_b_fdi_train_param[i];
2565                 I915_WRITE(reg, temp);
2566
2567                 POSTING_READ(reg);
2568                 udelay(500);
2569
2570                 for (retry = 0; retry < 5; retry++) {
2571                         reg = FDI_RX_IIR(pipe);
2572                         temp = I915_READ(reg);
2573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574                         if (temp & FDI_RX_SYMBOL_LOCK) {
2575                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2576                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577                                 break;
2578                         }
2579                         udelay(50);
2580                 }
2581                 if (retry < 5)
2582                         break;
2583         }
2584         if (i == 4)
2585                 DRM_ERROR("FDI train 2 fail!\n");
2586
2587         DRM_DEBUG_KMS("FDI train done.\n");
2588 }
2589
2590 /* Manual link training for Ivy Bridge A0 parts */
2591 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596         int pipe = intel_crtc->pipe;
2597         u32 reg, temp, i;
2598
2599         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600            for train result */
2601         reg = FDI_RX_IMR(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_RX_SYMBOL_LOCK;
2604         temp &= ~FDI_RX_BIT_LOCK;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2611                       I915_READ(FDI_RX_IIR(pipe)));
2612
2613         /* enable CPU FDI TX and PCH FDI RX */
2614         reg = FDI_TX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2617         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2618         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2619         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2620         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2622         temp |= FDI_COMPOSITE_SYNC;
2623         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625         I915_WRITE(FDI_RX_MISC(pipe),
2626                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_AUTO;
2631         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         temp |= FDI_COMPOSITE_SYNC;
2634         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636         POSTING_READ(reg);
2637         udelay(150);
2638
2639         for (i = 0; i < 4; i++) {
2640                 reg = FDI_TX_CTL(pipe);
2641                 temp = I915_READ(reg);
2642                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643                 temp |= snb_b_fdi_train_param[i];
2644                 I915_WRITE(reg, temp);
2645
2646                 POSTING_READ(reg);
2647                 udelay(500);
2648
2649                 reg = FDI_RX_IIR(pipe);
2650                 temp = I915_READ(reg);
2651                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653                 if (temp & FDI_RX_BIT_LOCK ||
2654                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2655                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2656                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2657                         break;
2658                 }
2659         }
2660         if (i == 4)
2661                 DRM_ERROR("FDI train 1 fail!\n");
2662
2663         /* Train 2 */
2664         reg = FDI_TX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2667         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2668         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2670         I915_WRITE(reg, temp);
2671
2672         reg = FDI_RX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(150);
2680
2681         for (i = 0; i < 4; i++) {
2682                 reg = FDI_TX_CTL(pipe);
2683                 temp = I915_READ(reg);
2684                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685                 temp |= snb_b_fdi_train_param[i];
2686                 I915_WRITE(reg, temp);
2687
2688                 POSTING_READ(reg);
2689                 udelay(500);
2690
2691                 reg = FDI_RX_IIR(pipe);
2692                 temp = I915_READ(reg);
2693                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695                 if (temp & FDI_RX_SYMBOL_LOCK) {
2696                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 2 fail!\n");
2703
2704         DRM_DEBUG_KMS("FDI train done.\n");
2705 }
2706
2707 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2708 {
2709         struct drm_device *dev = intel_crtc->base.dev;
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp;
2713
2714
2715         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2719         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2721         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(200);
2725
2726         /* Switch from Rawclk to PCDclk */
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp | FDI_PCDCLK);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Enable CPU FDI TX PLL, always on for Ironlake */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2737                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2738
2739                 POSTING_READ(reg);
2740                 udelay(100);
2741         }
2742 }
2743
2744 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         int pipe = intel_crtc->pipe;
2749         u32 reg, temp;
2750
2751         /* Switch from PCDclk to Rawclk */
2752         reg = FDI_RX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2755
2756         /* Disable CPU FDI TX PLL */
2757         reg = FDI_TX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2760
2761         POSTING_READ(reg);
2762         udelay(100);
2763
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2767
2768         /* Wait for the clocks to turn off. */
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799         }
2800
2801         /* still set train pattern 1 */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         if (HAS_PCH_CPT(dev)) {
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813         } else {
2814                 temp &= ~FDI_LINK_TRAIN_NONE;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816         }
2817         /* BPC in FDI rx is consistent with that in PIPECONF */
2818         temp &= ~(0x07 << 16);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824 }
2825
2826 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2831         unsigned long flags;
2832         bool pending;
2833
2834         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2835             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2836                 return false;
2837
2838         spin_lock_irqsave(&dev->event_lock, flags);
2839         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2840         spin_unlock_irqrestore(&dev->event_lock, flags);
2841
2842         return pending;
2843 }
2844
2845 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850         if (crtc->fb == NULL)
2851                 return;
2852
2853         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2854
2855         wait_event(dev_priv->pending_flip_queue,
2856                    !intel_crtc_has_pending_flip(crtc));
2857
2858         mutex_lock(&dev->struct_mutex);
2859         intel_finish_fb(crtc->fb);
2860         mutex_unlock(&dev->struct_mutex);
2861 }
2862
2863 /* Program iCLKIP clock to the desired frequency */
2864 static void lpt_program_iclkip(struct drm_crtc *crtc)
2865 {
2866         struct drm_device *dev = crtc->dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2869         u32 temp;
2870
2871         mutex_lock(&dev_priv->dpio_lock);
2872
2873         /* It is necessary to ungate the pixclk gate prior to programming
2874          * the divisors, and gate it back when it is done.
2875          */
2876         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2877
2878         /* Disable SSCCTL */
2879         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2880                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2881                                 SBI_SSCCTL_DISABLE,
2882                         SBI_ICLK);
2883
2884         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2885         if (crtc->mode.clock == 20000) {
2886                 auxdiv = 1;
2887                 divsel = 0x41;
2888                 phaseinc = 0x20;
2889         } else {
2890                 /* The iCLK virtual clock root frequency is in MHz,
2891                  * but the crtc->mode.clock in in KHz. To get the divisors,
2892                  * it is necessary to divide one by another, so we
2893                  * convert the virtual clock precision to KHz here for higher
2894                  * precision.
2895                  */
2896                 u32 iclk_virtual_root_freq = 172800 * 1000;
2897                 u32 iclk_pi_range = 64;
2898                 u32 desired_divisor, msb_divisor_value, pi_value;
2899
2900                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2901                 msb_divisor_value = desired_divisor / iclk_pi_range;
2902                 pi_value = desired_divisor % iclk_pi_range;
2903
2904                 auxdiv = 0;
2905                 divsel = msb_divisor_value - 2;
2906                 phaseinc = pi_value;
2907         }
2908
2909         /* This should not happen with any sane values */
2910         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2911                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2912         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2913                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2914
2915         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2916                         crtc->mode.clock,
2917                         auxdiv,
2918                         divsel,
2919                         phasedir,
2920                         phaseinc);
2921
2922         /* Program SSCDIVINTPHASE6 */
2923         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2924         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2925         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2926         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2927         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2928         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2929         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2930         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2931
2932         /* Program SSCAUXDIV */
2933         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2934         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2935         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2936         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2937
2938         /* Enable modulator and associated divider */
2939         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2940         temp &= ~SBI_SSCCTL_DISABLE;
2941         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2942
2943         /* Wait for initialization time */
2944         udelay(24);
2945
2946         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2947
2948         mutex_unlock(&dev_priv->dpio_lock);
2949 }
2950
2951 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2952                                                 enum pipe pch_transcoder)
2953 {
2954         struct drm_device *dev = crtc->base.dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2957
2958         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2959                    I915_READ(HTOTAL(cpu_transcoder)));
2960         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2961                    I915_READ(HBLANK(cpu_transcoder)));
2962         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2963                    I915_READ(HSYNC(cpu_transcoder)));
2964
2965         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2966                    I915_READ(VTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2968                    I915_READ(VBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2970                    I915_READ(VSYNC(cpu_transcoder)));
2971         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2972                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2973 }
2974
2975 /*
2976  * Enable PCH resources required for PCH ports:
2977  *   - PCH PLLs
2978  *   - FDI training & RX/TX
2979  *   - update transcoder timings
2980  *   - DP transcoding bits
2981  *   - transcoder
2982  */
2983 static void ironlake_pch_enable(struct drm_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         int pipe = intel_crtc->pipe;
2989         u32 reg, temp;
2990
2991         assert_pch_transcoder_disabled(dev_priv, pipe);
2992
2993         /* Write the TU size bits before fdi link training, so that error
2994          * detection works. */
2995         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2996                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2997
2998         /* For PCH output, training FDI link */
2999         dev_priv->display.fdi_link_train(crtc);
3000
3001         /* We need to program the right clock selection before writing the pixel
3002          * mutliplier into the DPLL. */
3003         if (HAS_PCH_CPT(dev)) {
3004                 u32 sel;
3005
3006                 temp = I915_READ(PCH_DPLL_SEL);
3007                 temp |= TRANS_DPLL_ENABLE(pipe);
3008                 sel = TRANS_DPLLB_SEL(pipe);
3009                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3010                         temp |= sel;
3011                 else
3012                         temp &= ~sel;
3013                 I915_WRITE(PCH_DPLL_SEL, temp);
3014         }
3015
3016         /* XXX: pch pll's can be enabled any time before we enable the PCH
3017          * transcoder, and we actually should do this to not upset any PCH
3018          * transcoder that already use the clock when we share it.
3019          *
3020          * Note that enable_shared_dpll tries to do the right thing, but
3021          * get_shared_dpll unconditionally resets the pll - we need that to have
3022          * the right LVDS enable sequence. */
3023         ironlake_enable_shared_dpll(intel_crtc);
3024
3025         /* set transcoder timing, panel must allow it */
3026         assert_panel_unlocked(dev_priv, pipe);
3027         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3028
3029         intel_fdi_normal_train(crtc);
3030
3031         /* For PCH DP, enable TRANS_DP_CTL */
3032         if (HAS_PCH_CPT(dev) &&
3033             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3035                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3036                 reg = TRANS_DP_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3039                           TRANS_DP_SYNC_MASK |
3040                           TRANS_DP_BPC_MASK);
3041                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042                          TRANS_DP_ENH_FRAMING);
3043                 temp |= bpc << 9; /* same format but at 11:9 */
3044
3045                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3046                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3048                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3049
3050                 switch (intel_trans_dp_port_sel(crtc)) {
3051                 case PCH_DP_B:
3052                         temp |= TRANS_DP_PORT_SEL_B;
3053                         break;
3054                 case PCH_DP_C:
3055                         temp |= TRANS_DP_PORT_SEL_C;
3056                         break;
3057                 case PCH_DP_D:
3058                         temp |= TRANS_DP_PORT_SEL_D;
3059                         break;
3060                 default:
3061                         BUG();
3062                 }
3063
3064                 I915_WRITE(reg, temp);
3065         }
3066
3067         ironlake_enable_pch_transcoder(dev_priv, pipe);
3068 }
3069
3070 static void lpt_pch_enable(struct drm_crtc *crtc)
3071 {
3072         struct drm_device *dev = crtc->dev;
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3076
3077         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3078
3079         lpt_program_iclkip(crtc);
3080
3081         /* Set transcoder timing. */
3082         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3083
3084         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3085 }
3086
3087 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3088 {
3089         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090
3091         if (pll == NULL)
3092                 return;
3093
3094         if (pll->refcount == 0) {
3095                 WARN(1, "bad %s refcount\n", pll->name);
3096                 return;
3097         }
3098
3099         if (--pll->refcount == 0) {
3100                 WARN_ON(pll->on);
3101                 WARN_ON(pll->active);
3102         }
3103
3104         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3105 }
3106
3107 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3108 {
3109         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3110         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3111         enum intel_dpll_id i;
3112
3113         if (pll) {
3114                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3115                               crtc->base.base.id, pll->name);
3116                 intel_put_shared_dpll(crtc);
3117         }
3118
3119         if (HAS_PCH_IBX(dev_priv->dev)) {
3120                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3121                 i = (enum intel_dpll_id) crtc->pipe;
3122                 pll = &dev_priv->shared_dplls[i];
3123
3124                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3125                               crtc->base.base.id, pll->name);
3126
3127                 goto found;
3128         }
3129
3130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3131                 pll = &dev_priv->shared_dplls[i];
3132
3133                 /* Only want to check enabled timings first */
3134                 if (pll->refcount == 0)
3135                         continue;
3136
3137                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3138                            sizeof(pll->hw_state)) == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3140                                       crtc->base.base.id,
3141                                       pll->name, pll->refcount, pll->active);
3142
3143                         goto found;
3144                 }
3145         }
3146
3147         /* Ok no matching timings, maybe there's a free one? */
3148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3149                 pll = &dev_priv->shared_dplls[i];
3150                 if (pll->refcount == 0) {
3151                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3152                                       crtc->base.base.id, pll->name);
3153                         goto found;
3154                 }
3155         }
3156
3157         return NULL;
3158
3159 found:
3160         crtc->config.shared_dpll = i;
3161         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3162                          pipe_name(crtc->pipe));
3163
3164         if (pll->active == 0) {
3165                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3166                        sizeof(pll->hw_state));
3167
3168                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3169                 WARN_ON(pll->on);
3170                 assert_shared_dpll_disabled(dev_priv, pll);
3171
3172                 pll->mode_set(dev_priv, pll);
3173         }
3174         pll->refcount++;
3175
3176         return pll;
3177 }
3178
3179 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         int dslreg = PIPEDSL(pipe);
3183         u32 temp;
3184
3185         temp = I915_READ(dslreg);
3186         udelay(500);
3187         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3190         }
3191 }
3192
3193 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->base.dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         int pipe = crtc->pipe;
3198
3199         if (crtc->config.pch_pfit.size) {
3200                 /* Force use of hard-coded filter coefficients
3201                  * as some pre-programmed values are broken,
3202                  * e.g. x201.
3203                  */
3204                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3205                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3206                                                  PF_PIPE_SEL_IVB(pipe));
3207                 else
3208                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3209                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3210                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3211         }
3212 }
3213
3214 static void intel_enable_planes(struct drm_crtc *crtc)
3215 {
3216         struct drm_device *dev = crtc->dev;
3217         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3218         struct intel_plane *intel_plane;
3219
3220         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3221                 if (intel_plane->pipe == pipe)
3222                         intel_plane_restore(&intel_plane->base);
3223 }
3224
3225 static void intel_disable_planes(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3229         struct intel_plane *intel_plane;
3230
3231         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3232                 if (intel_plane->pipe == pipe)
3233                         intel_plane_disable(&intel_plane->base);
3234 }
3235
3236 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         struct intel_encoder *encoder;
3242         int pipe = intel_crtc->pipe;
3243         int plane = intel_crtc->plane;
3244
3245         WARN_ON(!crtc->enabled);
3246
3247         if (intel_crtc->active)
3248                 return;
3249
3250         intel_crtc->active = true;
3251
3252         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3253         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3254
3255         intel_update_watermarks(dev);
3256
3257         for_each_encoder_on_crtc(dev, crtc, encoder)
3258                 if (encoder->pre_enable)
3259                         encoder->pre_enable(encoder);
3260
3261         if (intel_crtc->config.has_pch_encoder) {
3262                 /* Note: FDI PLL enabling _must_ be done before we enable the
3263                  * cpu pipes, hence this is separate from all the other fdi/pch
3264                  * enabling. */
3265                 ironlake_fdi_pll_enable(intel_crtc);
3266         } else {
3267                 assert_fdi_tx_disabled(dev_priv, pipe);
3268                 assert_fdi_rx_disabled(dev_priv, pipe);
3269         }
3270
3271         ironlake_pfit_enable(intel_crtc);
3272
3273         /*
3274          * On ILK+ LUT must be loaded before the pipe is running but with
3275          * clocks enabled
3276          */
3277         intel_crtc_load_lut(crtc);
3278
3279         intel_enable_pipe(dev_priv, pipe,
3280                           intel_crtc->config.has_pch_encoder);
3281         intel_enable_plane(dev_priv, plane, pipe);
3282         intel_enable_planes(crtc);
3283         intel_crtc_update_cursor(crtc, true);
3284
3285         if (intel_crtc->config.has_pch_encoder)
3286                 ironlake_pch_enable(crtc);
3287
3288         mutex_lock(&dev->struct_mutex);
3289         intel_update_fbc(dev);
3290         mutex_unlock(&dev->struct_mutex);
3291
3292         for_each_encoder_on_crtc(dev, crtc, encoder)
3293                 encoder->enable(encoder);
3294
3295         if (HAS_PCH_CPT(dev))
3296                 cpt_verify_modeset(dev, intel_crtc->pipe);
3297
3298         /*
3299          * There seems to be a race in PCH platform hw (at least on some
3300          * outputs) where an enabled pipe still completes any pageflip right
3301          * away (as if the pipe is off) instead of waiting for vblank. As soon
3302          * as the first vblank happend, everything works as expected. Hence just
3303          * wait for one vblank before returning to avoid strange things
3304          * happening.
3305          */
3306         intel_wait_for_vblank(dev, intel_crtc->pipe);
3307 }
3308
3309 /* IPS only exists on ULT machines and is tied to pipe A. */
3310 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3311 {
3312         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3313 }
3314
3315 static void hsw_enable_ips(struct intel_crtc *crtc)
3316 {
3317         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3318
3319         if (!crtc->config.ips_enabled)
3320                 return;
3321
3322         /* We can only enable IPS after we enable a plane and wait for a vblank.
3323          * We guarantee that the plane is enabled by calling intel_enable_ips
3324          * only after intel_enable_plane. And intel_enable_plane already waits
3325          * for a vblank, so all we need to do here is to enable the IPS bit. */
3326         assert_plane_enabled(dev_priv, crtc->plane);
3327         I915_WRITE(IPS_CTL, IPS_ENABLE);
3328 }
3329
3330 static void hsw_disable_ips(struct intel_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->base.dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335         if (!crtc->config.ips_enabled)
3336                 return;
3337
3338         assert_plane_enabled(dev_priv, crtc->plane);
3339         I915_WRITE(IPS_CTL, 0);
3340
3341         /* We need to wait for a vblank before we can disable the plane. */
3342         intel_wait_for_vblank(dev, crtc->pipe);
3343 }
3344
3345 static void haswell_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353
3354         WARN_ON(!crtc->enabled);
3355
3356         if (intel_crtc->active)
3357                 return;
3358
3359         intel_crtc->active = true;
3360
3361         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3362         if (intel_crtc->config.has_pch_encoder)
3363                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3364
3365         intel_update_watermarks(dev);
3366
3367         if (intel_crtc->config.has_pch_encoder)
3368                 dev_priv->display.fdi_link_train(crtc);
3369
3370         for_each_encoder_on_crtc(dev, crtc, encoder)
3371                 if (encoder->pre_enable)
3372                         encoder->pre_enable(encoder);
3373
3374         intel_ddi_enable_pipe_clock(intel_crtc);
3375
3376         ironlake_pfit_enable(intel_crtc);
3377
3378         /*
3379          * On ILK+ LUT must be loaded before the pipe is running but with
3380          * clocks enabled
3381          */
3382         intel_crtc_load_lut(crtc);
3383
3384         intel_ddi_set_pipe_settings(crtc);
3385         intel_ddi_enable_transcoder_func(crtc);
3386
3387         intel_enable_pipe(dev_priv, pipe,
3388                           intel_crtc->config.has_pch_encoder);
3389         intel_enable_plane(dev_priv, plane, pipe);
3390         intel_enable_planes(crtc);
3391         intel_crtc_update_cursor(crtc, true);
3392
3393         hsw_enable_ips(intel_crtc);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 lpt_pch_enable(crtc);
3397
3398         mutex_lock(&dev->struct_mutex);
3399         intel_update_fbc(dev);
3400         mutex_unlock(&dev->struct_mutex);
3401
3402         for_each_encoder_on_crtc(dev, crtc, encoder)
3403                 encoder->enable(encoder);
3404
3405         /*
3406          * There seems to be a race in PCH platform hw (at least on some
3407          * outputs) where an enabled pipe still completes any pageflip right
3408          * away (as if the pipe is off) instead of waiting for vblank. As soon
3409          * as the first vblank happend, everything works as expected. Hence just
3410          * wait for one vblank before returning to avoid strange things
3411          * happening.
3412          */
3413         intel_wait_for_vblank(dev, intel_crtc->pipe);
3414 }
3415
3416 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->base.dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         int pipe = crtc->pipe;
3421
3422         /* To avoid upsetting the power well on haswell only disable the pfit if
3423          * it's in use. The hw state code will make sure we get this right. */
3424         if (crtc->config.pch_pfit.size) {
3425                 I915_WRITE(PF_CTL(pipe), 0);
3426                 I915_WRITE(PF_WIN_POS(pipe), 0);
3427                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3428         }
3429 }
3430
3431 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436         struct intel_encoder *encoder;
3437         int pipe = intel_crtc->pipe;
3438         int plane = intel_crtc->plane;
3439         u32 reg, temp;
3440
3441
3442         if (!intel_crtc->active)
3443                 return;
3444
3445         for_each_encoder_on_crtc(dev, crtc, encoder)
3446                 encoder->disable(encoder);
3447
3448         intel_crtc_wait_for_pending_flips(crtc);
3449         drm_vblank_off(dev, pipe);
3450
3451         if (dev_priv->fbc.plane == plane)
3452                 intel_disable_fbc(dev);
3453
3454         intel_crtc_update_cursor(crtc, false);
3455         intel_disable_planes(crtc);
3456         intel_disable_plane(dev_priv, plane, pipe);
3457
3458         if (intel_crtc->config.has_pch_encoder)
3459                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3460
3461         intel_disable_pipe(dev_priv, pipe);
3462
3463         ironlake_pfit_disable(intel_crtc);
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 if (encoder->post_disable)
3467                         encoder->post_disable(encoder);
3468
3469         if (intel_crtc->config.has_pch_encoder) {
3470                 ironlake_fdi_disable(crtc);
3471
3472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3473                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3474
3475                 if (HAS_PCH_CPT(dev)) {
3476                         /* disable TRANS_DP_CTL */
3477                         reg = TRANS_DP_CTL(pipe);
3478                         temp = I915_READ(reg);
3479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3480                                   TRANS_DP_PORT_SEL_MASK);
3481                         temp |= TRANS_DP_PORT_SEL_NONE;
3482                         I915_WRITE(reg, temp);
3483
3484                         /* disable DPLL_SEL */
3485                         temp = I915_READ(PCH_DPLL_SEL);
3486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3487                         I915_WRITE(PCH_DPLL_SEL, temp);
3488                 }
3489
3490                 /* disable PCH DPLL */
3491                 intel_disable_shared_dpll(intel_crtc);
3492
3493                 ironlake_fdi_pll_disable(intel_crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void haswell_crtc_disable(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509         struct intel_encoder *encoder;
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3513
3514         if (!intel_crtc->active)
3515                 return;
3516
3517         for_each_encoder_on_crtc(dev, crtc, encoder)
3518                 encoder->disable(encoder);
3519
3520         intel_crtc_wait_for_pending_flips(crtc);
3521         drm_vblank_off(dev, pipe);
3522
3523         /* FBC must be disabled before disabling the plane on HSW. */
3524         if (dev_priv->fbc.plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         hsw_disable_ips(intel_crtc);
3528
3529         intel_crtc_update_cursor(crtc, false);
3530         intel_disable_planes(crtc);
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (intel_crtc->config.has_pch_encoder)
3534                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3538
3539         ironlake_pfit_disable(intel_crtc);
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_shared_dpll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         intel_ddi_put_crtc_pll(crtc);
3570 }
3571
3572 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573 {
3574         if (!enable && intel_crtc->overlay) {
3575                 struct drm_device *dev = intel_crtc->base.dev;
3576                 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578                 mutex_lock(&dev->struct_mutex);
3579                 dev_priv->mm.interruptible = false;
3580                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581                 dev_priv->mm.interruptible = true;
3582                 mutex_unlock(&dev->struct_mutex);
3583         }
3584
3585         /* Let userspace switch the overlay on again. In most cases userspace
3586          * has to recompute where to put it anyway.
3587          */
3588 }
3589
3590 /**
3591  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3592  * cursor plane briefly if not already running after enabling the display
3593  * plane.
3594  * This workaround avoids occasional blank screens when self refresh is
3595  * enabled.
3596  */
3597 static void
3598 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3599 {
3600         u32 cntl = I915_READ(CURCNTR(pipe));
3601
3602         if ((cntl & CURSOR_MODE) == 0) {
3603                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3604
3605                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3606                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3607                 intel_wait_for_vblank(dev_priv->dev, pipe);
3608                 I915_WRITE(CURCNTR(pipe), cntl);
3609                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3611         }
3612 }
3613
3614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->base.dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc_config *pipe_config = &crtc->config;
3619
3620         if (!crtc->config.gmch_pfit.control)
3621                 return;
3622
3623         /*
3624          * The panel fitter should only be adjusted whilst the pipe is disabled,
3625          * according to register description and PRM.
3626          */
3627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3628         assert_pipe_disabled(dev_priv, crtc->pipe);
3629
3630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3632
3633         /* Border color in case we don't scale up to the full screen. Black by
3634          * default, change to something else for debugging. */
3635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3636 }
3637
3638 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         struct intel_encoder *encoder;
3644         int pipe = intel_crtc->pipe;
3645         int plane = intel_crtc->plane;
3646
3647         WARN_ON(!crtc->enabled);
3648
3649         if (intel_crtc->active)
3650                 return;
3651
3652         intel_crtc->active = true;
3653         intel_update_watermarks(dev);
3654
3655         for_each_encoder_on_crtc(dev, crtc, encoder)
3656                 if (encoder->pre_pll_enable)
3657                         encoder->pre_pll_enable(encoder);
3658
3659         vlv_enable_pll(intel_crtc);
3660
3661         for_each_encoder_on_crtc(dev, crtc, encoder)
3662                 if (encoder->pre_enable)
3663                         encoder->pre_enable(encoder);
3664
3665         i9xx_pfit_enable(intel_crtc);
3666
3667         intel_crtc_load_lut(crtc);
3668
3669         intel_enable_pipe(dev_priv, pipe, false);
3670         intel_enable_plane(dev_priv, plane, pipe);
3671         intel_enable_planes(crtc);
3672         intel_crtc_update_cursor(crtc, true);
3673
3674         intel_update_fbc(dev);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 encoder->enable(encoder);
3678 }
3679
3680 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3681 {
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685         struct intel_encoder *encoder;
3686         int pipe = intel_crtc->pipe;
3687         int plane = intel_crtc->plane;
3688
3689         WARN_ON(!crtc->enabled);
3690
3691         if (intel_crtc->active)
3692                 return;
3693
3694         intel_crtc->active = true;
3695         intel_update_watermarks(dev);
3696
3697         for_each_encoder_on_crtc(dev, crtc, encoder)
3698                 if (encoder->pre_enable)
3699                         encoder->pre_enable(encoder);
3700
3701         i9xx_enable_pll(intel_crtc);
3702
3703         i9xx_pfit_enable(intel_crtc);
3704
3705         intel_crtc_load_lut(crtc);
3706
3707         intel_enable_pipe(dev_priv, pipe, false);
3708         intel_enable_plane(dev_priv, plane, pipe);
3709         intel_enable_planes(crtc);
3710         /* The fixup needs to happen before cursor is enabled */
3711         if (IS_G4X(dev))
3712                 g4x_fixup_plane(dev_priv, pipe);
3713         intel_crtc_update_cursor(crtc, true);
3714
3715         /* Give the overlay scaler a chance to enable if it's on this pipe */
3716         intel_crtc_dpms_overlay(intel_crtc, true);
3717
3718         intel_update_fbc(dev);
3719
3720         for_each_encoder_on_crtc(dev, crtc, encoder)
3721                 encoder->enable(encoder);
3722 }
3723
3724 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3725 {
3726         struct drm_device *dev = crtc->base.dev;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728
3729         if (!crtc->config.gmch_pfit.control)
3730                 return;
3731
3732         assert_pipe_disabled(dev_priv, crtc->pipe);
3733
3734         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3735                          I915_READ(PFIT_CONTROL));
3736         I915_WRITE(PFIT_CONTROL, 0);
3737 }
3738
3739 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3740 {
3741         struct drm_device *dev = crtc->dev;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744         struct intel_encoder *encoder;
3745         int pipe = intel_crtc->pipe;
3746         int plane = intel_crtc->plane;
3747
3748         if (!intel_crtc->active)
3749                 return;
3750
3751         for_each_encoder_on_crtc(dev, crtc, encoder)
3752                 encoder->disable(encoder);
3753
3754         /* Give the overlay scaler a chance to disable if it's on this pipe */
3755         intel_crtc_wait_for_pending_flips(crtc);
3756         drm_vblank_off(dev, pipe);
3757
3758         if (dev_priv->fbc.plane == plane)
3759                 intel_disable_fbc(dev);
3760
3761         intel_crtc_dpms_overlay(intel_crtc, false);
3762         intel_crtc_update_cursor(crtc, false);
3763         intel_disable_planes(crtc);
3764         intel_disable_plane(dev_priv, plane, pipe);
3765
3766         intel_disable_pipe(dev_priv, pipe);
3767
3768         i9xx_pfit_disable(intel_crtc);
3769
3770         for_each_encoder_on_crtc(dev, crtc, encoder)
3771                 if (encoder->post_disable)
3772                         encoder->post_disable(encoder);
3773
3774         i9xx_disable_pll(dev_priv, pipe);
3775
3776         intel_crtc->active = false;
3777         intel_update_fbc(dev);
3778         intel_update_watermarks(dev);
3779 }
3780
3781 static void i9xx_crtc_off(struct drm_crtc *crtc)
3782 {
3783 }
3784
3785 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3786                                     bool enabled)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_i915_master_private *master_priv;
3790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3791         int pipe = intel_crtc->pipe;
3792
3793         if (!dev->primary->master)
3794                 return;
3795
3796         master_priv = dev->primary->master->driver_priv;
3797         if (!master_priv->sarea_priv)
3798                 return;
3799
3800         switch (pipe) {
3801         case 0:
3802                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3803                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3804                 break;
3805         case 1:
3806                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3807                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3808                 break;
3809         default:
3810                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3811                 break;
3812         }
3813 }
3814
3815 /**
3816  * Sets the power management mode of the pipe and plane.
3817  */
3818 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         struct intel_encoder *intel_encoder;
3823         bool enable = false;
3824
3825         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3826                 enable |= intel_encoder->connectors_active;
3827
3828         if (enable)
3829                 dev_priv->display.crtc_enable(crtc);
3830         else
3831                 dev_priv->display.crtc_disable(crtc);
3832
3833         intel_crtc_update_sarea(crtc, enable);
3834 }
3835
3836 static void intel_crtc_disable(struct drm_crtc *crtc)
3837 {
3838         struct drm_device *dev = crtc->dev;
3839         struct drm_connector *connector;
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842
3843         /* crtc should still be enabled when we disable it. */
3844         WARN_ON(!crtc->enabled);
3845
3846         dev_priv->display.crtc_disable(crtc);
3847         intel_crtc->eld_vld = false;
3848         intel_crtc_update_sarea(crtc, false);
3849         dev_priv->display.off(crtc);
3850
3851         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3852         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3853
3854         if (crtc->fb) {
3855                 mutex_lock(&dev->struct_mutex);
3856                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3857                 mutex_unlock(&dev->struct_mutex);
3858                 crtc->fb = NULL;
3859         }
3860
3861         /* Update computed state. */
3862         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3863                 if (!connector->encoder || !connector->encoder->crtc)
3864                         continue;
3865
3866                 if (connector->encoder->crtc != crtc)
3867                         continue;
3868
3869                 connector->dpms = DRM_MODE_DPMS_OFF;
3870                 to_intel_encoder(connector->encoder)->connectors_active = false;
3871         }
3872 }
3873
3874 void intel_encoder_destroy(struct drm_encoder *encoder)
3875 {
3876         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3877
3878         drm_encoder_cleanup(encoder);
3879         kfree(intel_encoder);
3880 }
3881
3882 /* Simple dpms helper for encoders with just one connector, no cloning and only
3883  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884  * state of the entire output pipe. */
3885 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3886 {
3887         if (mode == DRM_MODE_DPMS_ON) {
3888                 encoder->connectors_active = true;
3889
3890                 intel_crtc_update_dpms(encoder->base.crtc);
3891         } else {
3892                 encoder->connectors_active = false;
3893
3894                 intel_crtc_update_dpms(encoder->base.crtc);
3895         }
3896 }
3897
3898 /* Cross check the actual hw state with our own modeset state tracking (and it's
3899  * internal consistency). */
3900 static void intel_connector_check_state(struct intel_connector *connector)
3901 {
3902         if (connector->get_hw_state(connector)) {
3903                 struct intel_encoder *encoder = connector->encoder;
3904                 struct drm_crtc *crtc;
3905                 bool encoder_enabled;
3906                 enum pipe pipe;
3907
3908                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909                               connector->base.base.id,
3910                               drm_get_connector_name(&connector->base));
3911
3912                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913                      "wrong connector dpms state\n");
3914                 WARN(connector->base.encoder != &encoder->base,
3915                      "active connector not linked to encoder\n");
3916                 WARN(!encoder->connectors_active,
3917                      "encoder->connectors_active not set\n");
3918
3919                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920                 WARN(!encoder_enabled, "encoder not enabled\n");
3921                 if (WARN_ON(!encoder->base.crtc))
3922                         return;
3923
3924                 crtc = encoder->base.crtc;
3925
3926                 WARN(!crtc->enabled, "crtc not enabled\n");
3927                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929                      "encoder active on the wrong pipe\n");
3930         }
3931 }
3932
3933 /* Even simpler default implementation, if there's really no special case to
3934  * consider. */
3935 void intel_connector_dpms(struct drm_connector *connector, int mode)
3936 {
3937         struct intel_encoder *encoder = intel_attached_encoder(connector);
3938
3939         /* All the simple cases only support two dpms states. */
3940         if (mode != DRM_MODE_DPMS_ON)
3941                 mode = DRM_MODE_DPMS_OFF;
3942
3943         if (mode == connector->dpms)
3944                 return;
3945
3946         connector->dpms = mode;
3947
3948         /* Only need to change hw state when actually enabled */
3949         if (encoder->base.crtc)
3950                 intel_encoder_dpms(encoder, mode);
3951         else
3952                 WARN_ON(encoder->connectors_active != false);
3953
3954         intel_modeset_check_state(connector->dev);
3955 }
3956
3957 /* Simple connector->get_hw_state implementation for encoders that support only
3958  * one connector and no cloning and hence the encoder state determines the state
3959  * of the connector. */
3960 bool intel_connector_get_hw_state(struct intel_connector *connector)
3961 {
3962         enum pipe pipe = 0;
3963         struct intel_encoder *encoder = connector->encoder;
3964
3965         return encoder->get_hw_state(encoder, &pipe);
3966 }
3967
3968 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3969                                      struct intel_crtc_config *pipe_config)
3970 {
3971         struct drm_i915_private *dev_priv = dev->dev_private;
3972         struct intel_crtc *pipe_B_crtc =
3973                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3974
3975         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3976                       pipe_name(pipe), pipe_config->fdi_lanes);
3977         if (pipe_config->fdi_lanes > 4) {
3978                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3979                               pipe_name(pipe), pipe_config->fdi_lanes);
3980                 return false;
3981         }
3982
3983         if (IS_HASWELL(dev)) {
3984                 if (pipe_config->fdi_lanes > 2) {
3985                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3986                                       pipe_config->fdi_lanes);
3987                         return false;
3988                 } else {
3989                         return true;
3990                 }
3991         }
3992
3993         if (INTEL_INFO(dev)->num_pipes == 2)
3994                 return true;
3995
3996         /* Ivybridge 3 pipe is really complicated */
3997         switch (pipe) {
3998         case PIPE_A:
3999                 return true;
4000         case PIPE_B:
4001                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4002                     pipe_config->fdi_lanes > 2) {
4003                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4004                                       pipe_name(pipe), pipe_config->fdi_lanes);
4005                         return false;
4006                 }
4007                 return true;
4008         case PIPE_C:
4009                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4010                     pipe_B_crtc->config.fdi_lanes <= 2) {
4011                         if (pipe_config->fdi_lanes > 2) {
4012                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4013                                               pipe_name(pipe), pipe_config->fdi_lanes);
4014                                 return false;
4015                         }
4016                 } else {
4017                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4018                         return false;
4019                 }
4020                 return true;
4021         default:
4022                 BUG();
4023         }
4024 }
4025
4026 #define RETRY 1
4027 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4028                                        struct intel_crtc_config *pipe_config)
4029 {
4030         struct drm_device *dev = intel_crtc->base.dev;
4031         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4032         int lane, link_bw, fdi_dotclock;
4033         bool setup_ok, needs_recompute = false;
4034
4035 retry:
4036         /* FDI is a binary signal running at ~2.7GHz, encoding
4037          * each output octet as 10 bits. The actual frequency
4038          * is stored as a divider into a 100MHz clock, and the
4039          * mode pixel clock is stored in units of 1KHz.
4040          * Hence the bw of each lane in terms of the mode signal
4041          * is:
4042          */
4043         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4044
4045         fdi_dotclock = adjusted_mode->clock;
4046         fdi_dotclock /= pipe_config->pixel_multiplier;
4047
4048         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4049                                            pipe_config->pipe_bpp);
4050
4051         pipe_config->fdi_lanes = lane;
4052
4053         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4054                                link_bw, &pipe_config->fdi_m_n);
4055
4056         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4057                                             intel_crtc->pipe, pipe_config);
4058         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4059                 pipe_config->pipe_bpp -= 2*3;
4060                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4061                               pipe_config->pipe_bpp);
4062                 needs_recompute = true;
4063                 pipe_config->bw_constrained = true;
4064
4065                 goto retry;
4066         }
4067
4068         if (needs_recompute)
4069                 return RETRY;
4070
4071         return setup_ok ? 0 : -EINVAL;
4072 }
4073
4074 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4075                                    struct intel_crtc_config *pipe_config)
4076 {
4077         pipe_config->ips_enabled = i915_enable_ips &&
4078                                    hsw_crtc_supports_ips(crtc) &&
4079                                    pipe_config->pipe_bpp <= 24;
4080 }
4081
4082 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4083                                      struct intel_crtc_config *pipe_config)
4084 {
4085         struct drm_device *dev = crtc->base.dev;
4086         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4087
4088         if (HAS_PCH_SPLIT(dev)) {
4089                 /* FDI link clock is fixed at 2.7G */
4090                 if (pipe_config->requested_mode.clock * 3
4091                     > IRONLAKE_FDI_FREQ * 4)
4092                         return -EINVAL;
4093         }
4094
4095         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4096          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4097          */
4098         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4099                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4100                 return -EINVAL;
4101
4102         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4103                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4104         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4105                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4106                  * for lvds. */
4107                 pipe_config->pipe_bpp = 8*3;
4108         }
4109
4110         if (HAS_IPS(dev))
4111                 hsw_compute_ips_config(crtc, pipe_config);
4112
4113         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4114          * clock survives for now. */
4115         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4116                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4117
4118         if (pipe_config->has_pch_encoder)
4119                 return ironlake_fdi_compute_config(crtc, pipe_config);
4120
4121         return 0;
4122 }
4123
4124 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4125 {
4126         return 400000; /* FIXME */
4127 }
4128
4129 static int i945_get_display_clock_speed(struct drm_device *dev)
4130 {
4131         return 400000;
4132 }
4133
4134 static int i915_get_display_clock_speed(struct drm_device *dev)
4135 {
4136         return 333000;
4137 }
4138
4139 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4140 {
4141         return 200000;
4142 }
4143
4144 static int pnv_get_display_clock_speed(struct drm_device *dev)
4145 {
4146         u16 gcfgc = 0;
4147
4148         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4149
4150         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4151         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4152                 return 267000;
4153         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4154                 return 333000;
4155         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4156                 return 444000;
4157         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4158                 return 200000;
4159         default:
4160                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4161         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4162                 return 133000;
4163         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4164                 return 167000;
4165         }
4166 }
4167
4168 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4169 {
4170         u16 gcfgc = 0;
4171
4172         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4173
4174         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4175                 return 133000;
4176         else {
4177                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4178                 case GC_DISPLAY_CLOCK_333_MHZ:
4179                         return 333000;
4180                 default:
4181                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4182                         return 190000;
4183                 }
4184         }
4185 }
4186
4187 static int i865_get_display_clock_speed(struct drm_device *dev)
4188 {
4189         return 266000;
4190 }
4191
4192 static int i855_get_display_clock_speed(struct drm_device *dev)
4193 {
4194         u16 hpllcc = 0;
4195         /* Assume that the hardware is in the high speed state.  This
4196          * should be the default.
4197          */
4198         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4199         case GC_CLOCK_133_200:
4200         case GC_CLOCK_100_200:
4201                 return 200000;
4202         case GC_CLOCK_166_250:
4203                 return 250000;
4204         case GC_CLOCK_100_133:
4205                 return 133000;
4206         }
4207
4208         /* Shouldn't happen */
4209         return 0;
4210 }
4211
4212 static int i830_get_display_clock_speed(struct drm_device *dev)
4213 {
4214         return 133000;
4215 }
4216
4217 static void
4218 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4219 {
4220         while (*num > DATA_LINK_M_N_MASK ||
4221                *den > DATA_LINK_M_N_MASK) {
4222                 *num >>= 1;
4223                 *den >>= 1;
4224         }
4225 }
4226
4227 static void compute_m_n(unsigned int m, unsigned int n,
4228                         uint32_t *ret_m, uint32_t *ret_n)
4229 {
4230         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4231         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4232         intel_reduce_m_n_ratio(ret_m, ret_n);
4233 }
4234
4235 void
4236 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4237                        int pixel_clock, int link_clock,
4238                        struct intel_link_m_n *m_n)
4239 {
4240         m_n->tu = 64;
4241
4242         compute_m_n(bits_per_pixel * pixel_clock,
4243                     link_clock * nlanes * 8,
4244                     &m_n->gmch_m, &m_n->gmch_n);
4245
4246         compute_m_n(pixel_clock, link_clock,
4247                     &m_n->link_m, &m_n->link_n);
4248 }
4249
4250 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4251 {
4252         if (i915_panel_use_ssc >= 0)
4253                 return i915_panel_use_ssc != 0;
4254         return dev_priv->vbt.lvds_use_ssc
4255                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4256 }
4257
4258 static int vlv_get_refclk(struct drm_crtc *crtc)
4259 {
4260         struct drm_device *dev = crtc->dev;
4261         struct drm_i915_private *dev_priv = dev->dev_private;
4262         int refclk = 27000; /* for DP & HDMI */
4263
4264         return 100000; /* only one validated so far */
4265
4266         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4267                 refclk = 96000;
4268         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4269                 if (intel_panel_use_ssc(dev_priv))
4270                         refclk = 100000;
4271                 else
4272                         refclk = 96000;
4273         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4274                 refclk = 100000;
4275         }
4276
4277         return refclk;
4278 }
4279
4280 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         int refclk;
4285
4286         if (IS_VALLEYVIEW(dev)) {
4287                 refclk = vlv_get_refclk(crtc);
4288         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4289             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4290                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4291                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4292                               refclk / 1000);
4293         } else if (!IS_GEN2(dev)) {
4294                 refclk = 96000;
4295         } else {
4296                 refclk = 48000;
4297         }
4298
4299         return refclk;
4300 }
4301
4302 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4303 {
4304         return (1 << dpll->n) << 16 | dpll->m2;
4305 }
4306
4307 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4308 {
4309         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4310 }
4311
4312 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4313                                      intel_clock_t *reduced_clock)
4314 {
4315         struct drm_device *dev = crtc->base.dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         int pipe = crtc->pipe;
4318         u32 fp, fp2 = 0;
4319
4320         if (IS_PINEVIEW(dev)) {
4321                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4322                 if (reduced_clock)
4323                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4324         } else {
4325                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4326                 if (reduced_clock)
4327                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4328         }
4329
4330         I915_WRITE(FP0(pipe), fp);
4331         crtc->config.dpll_hw_state.fp0 = fp;
4332
4333         crtc->lowfreq_avail = false;
4334         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4335             reduced_clock && i915_powersave) {
4336                 I915_WRITE(FP1(pipe), fp2);
4337                 crtc->config.dpll_hw_state.fp1 = fp2;
4338                 crtc->lowfreq_avail = true;
4339         } else {
4340                 I915_WRITE(FP1(pipe), fp);
4341                 crtc->config.dpll_hw_state.fp1 = fp;
4342         }
4343 }
4344
4345 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4346 {
4347         u32 reg_val;
4348
4349         /*
4350          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4351          * and set it to a reasonable value instead.
4352          */
4353         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4354         reg_val &= 0xffffff00;
4355         reg_val |= 0x00000030;
4356         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4357
4358         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4359         reg_val &= 0x8cffffff;
4360         reg_val = 0x8c000000;
4361         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4362
4363         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4364         reg_val &= 0xffffff00;
4365         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4366
4367         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4368         reg_val &= 0x00ffffff;
4369         reg_val |= 0xb0000000;
4370         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4371 }
4372
4373 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4374                                          struct intel_link_m_n *m_n)
4375 {
4376         struct drm_device *dev = crtc->base.dev;
4377         struct drm_i915_private *dev_priv = dev->dev_private;
4378         int pipe = crtc->pipe;
4379
4380         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4381         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4382         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4383         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4384 }
4385
4386 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4387                                          struct intel_link_m_n *m_n)
4388 {
4389         struct drm_device *dev = crtc->base.dev;
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391         int pipe = crtc->pipe;
4392         enum transcoder transcoder = crtc->config.cpu_transcoder;
4393
4394         if (INTEL_INFO(dev)->gen >= 5) {
4395                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4396                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4397                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4398                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4399         } else {
4400                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4401                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4402                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4403                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4404         }
4405 }
4406
4407 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4408 {
4409         if (crtc->config.has_pch_encoder)
4410                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4411         else
4412                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4413 }
4414
4415 static void vlv_update_pll(struct intel_crtc *crtc)
4416 {
4417         struct drm_device *dev = crtc->base.dev;
4418         struct drm_i915_private *dev_priv = dev->dev_private;
4419         int pipe = crtc->pipe;
4420         u32 dpll, mdiv;
4421         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4422         bool is_hdmi;
4423         u32 coreclk, reg_val, dpll_md;
4424
4425         mutex_lock(&dev_priv->dpio_lock);
4426
4427         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4428
4429         bestn = crtc->config.dpll.n;
4430         bestm1 = crtc->config.dpll.m1;
4431         bestm2 = crtc->config.dpll.m2;
4432         bestp1 = crtc->config.dpll.p1;
4433         bestp2 = crtc->config.dpll.p2;
4434
4435         /* See eDP HDMI DPIO driver vbios notes doc */
4436
4437         /* PLL B needs special handling */
4438         if (pipe)
4439                 vlv_pllb_recal_opamp(dev_priv);
4440
4441         /* Set up Tx target for periodic Rcomp update */
4442         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4443
4444         /* Disable target IRef on PLL */
4445         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4446         reg_val &= 0x00ffffff;
4447         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4448
4449         /* Disable fast lock */
4450         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4451
4452         /* Set idtafcrecal before PLL is enabled */
4453         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4454         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4455         mdiv |= ((bestn << DPIO_N_SHIFT));
4456         mdiv |= (1 << DPIO_K_SHIFT);
4457
4458         /*
4459          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4460          * but we don't support that).
4461          * Note: don't use the DAC post divider as it seems unstable.
4462          */
4463         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4464         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4465
4466         mdiv |= DPIO_ENABLE_CALIBRATION;
4467         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4468
4469         /* Set HBR and RBR LPF coefficients */
4470         if (crtc->config.port_clock == 162000 ||
4471             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4472             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4473                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4474                                  0x009f0003);
4475         else
4476                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4477                                  0x00d0000f);
4478
4479         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4480             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4481                 /* Use SSC source */
4482                 if (!pipe)
4483                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4484                                          0x0df40000);
4485                 else
4486                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4487                                          0x0df70000);
4488         } else { /* HDMI or VGA */
4489                 /* Use bend source */
4490                 if (!pipe)
4491                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4492                                          0x0df70000);
4493                 else
4494                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4495                                          0x0df40000);
4496         }
4497
4498         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4499         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4500         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4501             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4502                 coreclk |= 0x01000000;
4503         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4504
4505         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4506
4507         /* Enable DPIO clock input */
4508         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4509                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4510         if (pipe)
4511                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4512
4513         dpll |= DPLL_VCO_ENABLE;
4514         crtc->config.dpll_hw_state.dpll = dpll;
4515
4516         dpll_md = (crtc->config.pixel_multiplier - 1)
4517                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4518         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4519
4520         if (crtc->config.has_dp_encoder)
4521                 intel_dp_set_m_n(crtc);
4522
4523         mutex_unlock(&dev_priv->dpio_lock);
4524 }
4525
4526 static void i9xx_update_pll(struct intel_crtc *crtc,
4527                             intel_clock_t *reduced_clock,
4528                             int num_connectors)
4529 {
4530         struct drm_device *dev = crtc->base.dev;
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532         u32 dpll;
4533         bool is_sdvo;
4534         struct dpll *clock = &crtc->config.dpll;
4535
4536         i9xx_update_pll_dividers(crtc, reduced_clock);
4537
4538         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4540
4541         dpll = DPLL_VGA_MODE_DIS;
4542
4543         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4544                 dpll |= DPLLB_MODE_LVDS;
4545         else
4546                 dpll |= DPLLB_MODE_DAC_SERIAL;
4547
4548         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4549                 dpll |= (crtc->config.pixel_multiplier - 1)
4550                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4551         }
4552
4553         if (is_sdvo)
4554                 dpll |= DPLL_SDVO_HIGH_SPEED;
4555
4556         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4557                 dpll |= DPLL_SDVO_HIGH_SPEED;
4558
4559         /* compute bitmask from p1 value */
4560         if (IS_PINEVIEW(dev))
4561                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4562         else {
4563                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564                 if (IS_G4X(dev) && reduced_clock)
4565                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4566         }
4567         switch (clock->p2) {
4568         case 5:
4569                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4570                 break;
4571         case 7:
4572                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4573                 break;
4574         case 10:
4575                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4576                 break;
4577         case 14:
4578                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4579                 break;
4580         }
4581         if (INTEL_INFO(dev)->gen >= 4)
4582                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4583
4584         if (crtc->config.sdvo_tv_clock)
4585                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4586         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4587                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4588                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4589         else
4590                 dpll |= PLL_REF_INPUT_DREFCLK;
4591
4592         dpll |= DPLL_VCO_ENABLE;
4593         crtc->config.dpll_hw_state.dpll = dpll;
4594
4595         if (INTEL_INFO(dev)->gen >= 4) {
4596                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4597                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4598                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4599         }
4600
4601         if (crtc->config.has_dp_encoder)
4602                 intel_dp_set_m_n(crtc);
4603 }
4604
4605 static void i8xx_update_pll(struct intel_crtc *crtc,
4606                             intel_clock_t *reduced_clock,
4607                             int num_connectors)
4608 {
4609         struct drm_device *dev = crtc->base.dev;
4610         struct drm_i915_private *dev_priv = dev->dev_private;
4611         u32 dpll;
4612         struct dpll *clock = &crtc->config.dpll;
4613
4614         i9xx_update_pll_dividers(crtc, reduced_clock);
4615
4616         dpll = DPLL_VGA_MODE_DIS;
4617
4618         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4619                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620         } else {
4621                 if (clock->p1 == 2)
4622                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4623                 else
4624                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625                 if (clock->p2 == 4)
4626                         dpll |= PLL_P2_DIVIDE_BY_4;
4627         }
4628
4629         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4630                 dpll |= DPLL_DVO_2X_MODE;
4631
4632         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4633                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4634                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4635         else
4636                 dpll |= PLL_REF_INPUT_DREFCLK;
4637
4638         dpll |= DPLL_VCO_ENABLE;
4639         crtc->config.dpll_hw_state.dpll = dpll;
4640 }
4641
4642 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4643 {
4644         struct drm_device *dev = intel_crtc->base.dev;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         enum pipe pipe = intel_crtc->pipe;
4647         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4648         struct drm_display_mode *adjusted_mode =
4649                 &intel_crtc->config.adjusted_mode;
4650         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4651         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4652
4653         /* We need to be careful not to changed the adjusted mode, for otherwise
4654          * the hw state checker will get angry at the mismatch. */
4655         crtc_vtotal = adjusted_mode->crtc_vtotal;
4656         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4657
4658         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4659                 /* the chip adds 2 halflines automatically */
4660                 crtc_vtotal -= 1;
4661                 crtc_vblank_end -= 1;
4662                 vsyncshift = adjusted_mode->crtc_hsync_start
4663                              - adjusted_mode->crtc_htotal / 2;
4664         } else {
4665                 vsyncshift = 0;
4666         }
4667
4668         if (INTEL_INFO(dev)->gen > 3)
4669                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4670
4671         I915_WRITE(HTOTAL(cpu_transcoder),
4672                    (adjusted_mode->crtc_hdisplay - 1) |
4673                    ((adjusted_mode->crtc_htotal - 1) << 16));
4674         I915_WRITE(HBLANK(cpu_transcoder),
4675                    (adjusted_mode->crtc_hblank_start - 1) |
4676                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4677         I915_WRITE(HSYNC(cpu_transcoder),
4678                    (adjusted_mode->crtc_hsync_start - 1) |
4679                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4680
4681         I915_WRITE(VTOTAL(cpu_transcoder),
4682                    (adjusted_mode->crtc_vdisplay - 1) |
4683                    ((crtc_vtotal - 1) << 16));
4684         I915_WRITE(VBLANK(cpu_transcoder),
4685                    (adjusted_mode->crtc_vblank_start - 1) |
4686                    ((crtc_vblank_end - 1) << 16));
4687         I915_WRITE(VSYNC(cpu_transcoder),
4688                    (adjusted_mode->crtc_vsync_start - 1) |
4689                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4690
4691         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4692          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4693          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4694          * bits. */
4695         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4696             (pipe == PIPE_B || pipe == PIPE_C))
4697                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4698
4699         /* pipesrc controls the size that is scaled from, which should
4700          * always be the user's requested size.
4701          */
4702         I915_WRITE(PIPESRC(pipe),
4703                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4704 }
4705
4706 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4707                                    struct intel_crtc_config *pipe_config)
4708 {
4709         struct drm_device *dev = crtc->base.dev;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4712         uint32_t tmp;
4713
4714         tmp = I915_READ(HTOTAL(cpu_transcoder));
4715         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4716         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4717         tmp = I915_READ(HBLANK(cpu_transcoder));
4718         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4719         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4720         tmp = I915_READ(HSYNC(cpu_transcoder));
4721         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4722         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4723
4724         tmp = I915_READ(VTOTAL(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4727         tmp = I915_READ(VBLANK(cpu_transcoder));
4728         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4729         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4730         tmp = I915_READ(VSYNC(cpu_transcoder));
4731         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4732         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4733
4734         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4735                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4736                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4737                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4738         }
4739
4740         tmp = I915_READ(PIPESRC(crtc->pipe));
4741         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4742         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4743 }
4744
4745 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4746                                              struct intel_crtc_config *pipe_config)
4747 {
4748         struct drm_crtc *crtc = &intel_crtc->base;
4749
4750         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4751         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4752         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4753         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4754
4755         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4756         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4757         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4758         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4759
4760         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4761
4762         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4763         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4764 }
4765
4766 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4767 {
4768         struct drm_device *dev = intel_crtc->base.dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         uint32_t pipeconf;
4771
4772         pipeconf = 0;
4773
4774         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4775                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4776                  * core speed.
4777                  *
4778                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4779                  * pipe == 0 check?
4780                  */
4781                 if (intel_crtc->config.requested_mode.clock >
4782                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4783                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4784         }
4785
4786         /* only g4x and later have fancy bpc/dither controls */
4787         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4788                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4789                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4790                         pipeconf |= PIPECONF_DITHER_EN |
4791                                     PIPECONF_DITHER_TYPE_SP;
4792
4793                 switch (intel_crtc->config.pipe_bpp) {
4794                 case 18:
4795                         pipeconf |= PIPECONF_6BPC;
4796                         break;
4797                 case 24:
4798                         pipeconf |= PIPECONF_8BPC;
4799                         break;
4800                 case 30:
4801                         pipeconf |= PIPECONF_10BPC;
4802                         break;
4803                 default:
4804                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4805                         BUG();
4806                 }
4807         }
4808
4809         if (HAS_PIPE_CXSR(dev)) {
4810                 if (intel_crtc->lowfreq_avail) {
4811                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4812                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4813                 } else {
4814                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4815                 }
4816         }
4817
4818         if (!IS_GEN2(dev) &&
4819             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4820                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4821         else
4822                 pipeconf |= PIPECONF_PROGRESSIVE;
4823
4824         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4825                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4826
4827         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4828         POSTING_READ(PIPECONF(intel_crtc->pipe));
4829 }
4830
4831 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4832                               int x, int y,
4833                               struct drm_framebuffer *fb)
4834 {
4835         struct drm_device *dev = crtc->dev;
4836         struct drm_i915_private *dev_priv = dev->dev_private;
4837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4838         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4839         int pipe = intel_crtc->pipe;
4840         int plane = intel_crtc->plane;
4841         int refclk, num_connectors = 0;
4842         intel_clock_t clock, reduced_clock;
4843         u32 dspcntr;
4844         bool ok, has_reduced_clock = false;
4845         bool is_lvds = false;
4846         struct intel_encoder *encoder;
4847         const intel_limit_t *limit;
4848         int ret;
4849
4850         for_each_encoder_on_crtc(dev, crtc, encoder) {
4851                 switch (encoder->type) {
4852                 case INTEL_OUTPUT_LVDS:
4853                         is_lvds = true;
4854                         break;
4855                 }
4856
4857                 num_connectors++;
4858         }
4859
4860         refclk = i9xx_get_refclk(crtc, num_connectors);
4861
4862         /*
4863          * Returns a set of divisors for the desired target clock with the given
4864          * refclk, or FALSE.  The returned values represent the clock equation:
4865          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4866          */
4867         limit = intel_limit(crtc, refclk);
4868         ok = dev_priv->display.find_dpll(limit, crtc,
4869                                          intel_crtc->config.port_clock,
4870                                          refclk, NULL, &clock);
4871         if (!ok && !intel_crtc->config.clock_set) {
4872                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4873                 return -EINVAL;
4874         }
4875
4876         /* Ensure that the cursor is valid for the new mode before changing... */
4877         intel_crtc_update_cursor(crtc, true);
4878
4879         if (is_lvds && dev_priv->lvds_downclock_avail) {
4880                 /*
4881                  * Ensure we match the reduced clock's P to the target clock.
4882                  * If the clocks don't match, we can't switch the display clock
4883                  * by using the FP0/FP1. In such case we will disable the LVDS
4884                  * downclock feature.
4885                 */
4886                 has_reduced_clock =
4887                         dev_priv->display.find_dpll(limit, crtc,
4888                                                     dev_priv->lvds_downclock,
4889                                                     refclk, &clock,
4890                                                     &reduced_clock);
4891         }
4892         /* Compat-code for transition, will disappear. */
4893         if (!intel_crtc->config.clock_set) {
4894                 intel_crtc->config.dpll.n = clock.n;
4895                 intel_crtc->config.dpll.m1 = clock.m1;
4896                 intel_crtc->config.dpll.m2 = clock.m2;
4897                 intel_crtc->config.dpll.p1 = clock.p1;
4898                 intel_crtc->config.dpll.p2 = clock.p2;
4899         }
4900
4901         if (IS_GEN2(dev))
4902                 i8xx_update_pll(intel_crtc,
4903                                 has_reduced_clock ? &reduced_clock : NULL,
4904                                 num_connectors);
4905         else if (IS_VALLEYVIEW(dev))
4906                 vlv_update_pll(intel_crtc);
4907         else
4908                 i9xx_update_pll(intel_crtc,
4909                                 has_reduced_clock ? &reduced_clock : NULL,
4910                                 num_connectors);
4911
4912         /* Set up the display plane register */
4913         dspcntr = DISPPLANE_GAMMA_ENABLE;
4914
4915         if (!IS_VALLEYVIEW(dev)) {
4916                 if (pipe == 0)
4917                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4918                 else
4919                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4920         }
4921
4922         intel_set_pipe_timings(intel_crtc);
4923
4924         /* pipesrc and dspsize control the size that is scaled from,
4925          * which should always be the user's requested size.
4926          */
4927         I915_WRITE(DSPSIZE(plane),
4928                    ((mode->vdisplay - 1) << 16) |
4929                    (mode->hdisplay - 1));
4930         I915_WRITE(DSPPOS(plane), 0);
4931
4932         i9xx_set_pipeconf(intel_crtc);
4933
4934         I915_WRITE(DSPCNTR(plane), dspcntr);
4935         POSTING_READ(DSPCNTR(plane));
4936
4937         ret = intel_pipe_set_base(crtc, x, y, fb);
4938
4939         intel_update_watermarks(dev);
4940
4941         return ret;
4942 }
4943
4944 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4945                                  struct intel_crtc_config *pipe_config)
4946 {
4947         struct drm_device *dev = crtc->base.dev;
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949         uint32_t tmp;
4950
4951         tmp = I915_READ(PFIT_CONTROL);
4952         if (!(tmp & PFIT_ENABLE))
4953                 return;
4954
4955         /* Check whether the pfit is attached to our pipe. */
4956         if (INTEL_INFO(dev)->gen < 4) {
4957                 if (crtc->pipe != PIPE_B)
4958                         return;
4959         } else {
4960                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4961                         return;
4962         }
4963
4964         pipe_config->gmch_pfit.control = tmp;
4965         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4966         if (INTEL_INFO(dev)->gen < 5)
4967                 pipe_config->gmch_pfit.lvds_border_bits =
4968                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4969 }
4970
4971 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4972                                  struct intel_crtc_config *pipe_config)
4973 {
4974         struct drm_device *dev = crtc->base.dev;
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976         uint32_t tmp;
4977
4978         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4979         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4980
4981         tmp = I915_READ(PIPECONF(crtc->pipe));
4982         if (!(tmp & PIPECONF_ENABLE))
4983                 return false;
4984
4985         intel_get_pipe_timings(crtc, pipe_config);
4986
4987         i9xx_get_pfit_config(crtc, pipe_config);
4988
4989         if (INTEL_INFO(dev)->gen >= 4) {
4990                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4991                 pipe_config->pixel_multiplier =
4992                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4993                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4994                 pipe_config->dpll_hw_state.dpll_md = tmp;
4995         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4996                 tmp = I915_READ(DPLL(crtc->pipe));
4997                 pipe_config->pixel_multiplier =
4998                         ((tmp & SDVO_MULTIPLIER_MASK)
4999                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5000         } else {
5001                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5002                  * port and will be fixed up in the encoder->get_config
5003                  * function. */
5004                 pipe_config->pixel_multiplier = 1;
5005         }
5006         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5007         if (!IS_VALLEYVIEW(dev)) {
5008                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5009                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5010         } else {
5011                 /* Mask out read-only status bits. */
5012                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5013                                                      DPLL_PORTC_READY_MASK |
5014                                                      DPLL_PORTB_READY_MASK);
5015         }
5016
5017         return true;
5018 }
5019
5020 static void ironlake_init_pch_refclk(struct drm_device *dev)
5021 {
5022         struct drm_i915_private *dev_priv = dev->dev_private;
5023         struct drm_mode_config *mode_config = &dev->mode_config;
5024         struct intel_encoder *encoder;
5025         u32 val, final;
5026         bool has_lvds = false;
5027         bool has_cpu_edp = false;
5028         bool has_panel = false;
5029         bool has_ck505 = false;
5030         bool can_ssc = false;
5031
5032         /* We need to take the global config into account */
5033         list_for_each_entry(encoder, &mode_config->encoder_list,
5034                             base.head) {
5035                 switch (encoder->type) {
5036                 case INTEL_OUTPUT_LVDS:
5037                         has_panel = true;
5038                         has_lvds = true;
5039                         break;
5040                 case INTEL_OUTPUT_EDP:
5041                         has_panel = true;
5042                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5043                                 has_cpu_edp = true;
5044                         break;
5045                 }
5046         }
5047
5048         if (HAS_PCH_IBX(dev)) {
5049                 has_ck505 = dev_priv->vbt.display_clock_mode;
5050                 can_ssc = has_ck505;
5051         } else {
5052                 has_ck505 = false;
5053                 can_ssc = true;
5054         }
5055
5056         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5057                       has_panel, has_lvds, has_ck505);
5058
5059         /* Ironlake: try to setup display ref clock before DPLL
5060          * enabling. This is only under driver's control after
5061          * PCH B stepping, previous chipset stepping should be
5062          * ignoring this setting.
5063          */
5064         val = I915_READ(PCH_DREF_CONTROL);
5065
5066         /* As we must carefully and slowly disable/enable each source in turn,
5067          * compute the final state we want first and check if we need to
5068          * make any changes at all.
5069          */
5070         final = val;
5071         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5072         if (has_ck505)
5073                 final |= DREF_NONSPREAD_CK505_ENABLE;
5074         else
5075                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5076
5077         final &= ~DREF_SSC_SOURCE_MASK;
5078         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5079         final &= ~DREF_SSC1_ENABLE;
5080
5081         if (has_panel) {
5082                 final |= DREF_SSC_SOURCE_ENABLE;
5083
5084                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5085                         final |= DREF_SSC1_ENABLE;
5086
5087                 if (has_cpu_edp) {
5088                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5090                         else
5091                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5092                 } else
5093                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5094         } else {
5095                 final |= DREF_SSC_SOURCE_DISABLE;
5096                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097         }
5098
5099         if (final == val)
5100                 return;
5101
5102         /* Always enable nonspread source */
5103         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5104
5105         if (has_ck505)
5106                 val |= DREF_NONSPREAD_CK505_ENABLE;
5107         else
5108                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5109
5110         if (has_panel) {
5111                 val &= ~DREF_SSC_SOURCE_MASK;
5112                 val |= DREF_SSC_SOURCE_ENABLE;
5113
5114                 /* SSC must be turned on before enabling the CPU output  */
5115                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5116                         DRM_DEBUG_KMS("Using SSC on panel\n");
5117                         val |= DREF_SSC1_ENABLE;
5118                 } else
5119                         val &= ~DREF_SSC1_ENABLE;
5120
5121                 /* Get SSC going before enabling the outputs */
5122                 I915_WRITE(PCH_DREF_CONTROL, val);
5123                 POSTING_READ(PCH_DREF_CONTROL);
5124                 udelay(200);
5125
5126                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5127
5128                 /* Enable CPU source on CPU attached eDP */
5129                 if (has_cpu_edp) {
5130                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5131                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5132                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5133                         }
5134                         else
5135                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5136                 } else
5137                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5138
5139                 I915_WRITE(PCH_DREF_CONTROL, val);
5140                 POSTING_READ(PCH_DREF_CONTROL);
5141                 udelay(200);
5142         } else {
5143                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5144
5145                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5146
5147                 /* Turn off CPU output */
5148                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5149
5150                 I915_WRITE(PCH_DREF_CONTROL, val);
5151                 POSTING_READ(PCH_DREF_CONTROL);
5152                 udelay(200);
5153
5154                 /* Turn off the SSC source */
5155                 val &= ~DREF_SSC_SOURCE_MASK;
5156                 val |= DREF_SSC_SOURCE_DISABLE;
5157
5158                 /* Turn off SSC1 */
5159                 val &= ~DREF_SSC1_ENABLE;
5160
5161                 I915_WRITE(PCH_DREF_CONTROL, val);
5162                 POSTING_READ(PCH_DREF_CONTROL);
5163                 udelay(200);
5164         }
5165
5166         BUG_ON(val != final);
5167 }
5168
5169 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5170 {
5171         uint32_t tmp;
5172
5173         tmp = I915_READ(SOUTH_CHICKEN2);
5174         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5175         I915_WRITE(SOUTH_CHICKEN2, tmp);
5176
5177         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5178                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5179                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5180
5181         tmp = I915_READ(SOUTH_CHICKEN2);
5182         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5183         I915_WRITE(SOUTH_CHICKEN2, tmp);
5184
5185         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5186                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5187                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5188 }
5189
5190 /* WaMPhyProgramming:hsw */
5191 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5192 {
5193         uint32_t tmp;
5194
5195         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5196         tmp &= ~(0xFF << 24);
5197         tmp |= (0x12 << 24);
5198         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5199
5200         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5201         tmp |= (1 << 11);
5202         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5203
5204         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5205         tmp |= (1 << 11);
5206         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5207
5208         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5209         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5210         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5211
5212         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5213         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5214         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5215
5216         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5217         tmp &= ~(7 << 13);
5218         tmp |= (5 << 13);
5219         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5220
5221         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5222         tmp &= ~(7 << 13);
5223         tmp |= (5 << 13);
5224         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5227         tmp &= ~0xFF;
5228         tmp |= 0x1C;
5229         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5230
5231         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5232         tmp &= ~0xFF;
5233         tmp |= 0x1C;
5234         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5235
5236         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5237         tmp &= ~(0xFF << 16);
5238         tmp |= (0x1C << 16);
5239         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5240
5241         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5242         tmp &= ~(0xFF << 16);
5243         tmp |= (0x1C << 16);
5244         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5247         tmp |= (1 << 27);
5248         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5249
5250         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5251         tmp |= (1 << 27);
5252         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5255         tmp &= ~(0xF << 28);
5256         tmp |= (4 << 28);
5257         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5258
5259         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5260         tmp &= ~(0xF << 28);
5261         tmp |= (4 << 28);
5262         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5263 }
5264
5265 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5266  * Programming" based on the parameters passed:
5267  * - Sequence to enable CLKOUT_DP
5268  * - Sequence to enable CLKOUT_DP without spread
5269  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5270  */
5271 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5272                                  bool with_fdi)
5273 {
5274         struct drm_i915_private *dev_priv = dev->dev_private;
5275         uint32_t reg, tmp;
5276
5277         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5278                 with_spread = true;
5279         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5280                  with_fdi, "LP PCH doesn't have FDI\n"))
5281                 with_fdi = false;
5282
5283         mutex_lock(&dev_priv->dpio_lock);
5284
5285         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5286         tmp &= ~SBI_SSCCTL_DISABLE;
5287         tmp |= SBI_SSCCTL_PATHALT;
5288         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5289
5290         udelay(24);
5291
5292         if (with_spread) {
5293                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5294                 tmp &= ~SBI_SSCCTL_PATHALT;
5295                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5296
5297                 if (with_fdi) {
5298                         lpt_reset_fdi_mphy(dev_priv);
5299                         lpt_program_fdi_mphy(dev_priv);
5300                 }
5301         }
5302
5303         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5304                SBI_GEN0 : SBI_DBUFF0;
5305         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5306         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5307         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5308
5309         mutex_unlock(&dev_priv->dpio_lock);
5310 }
5311
5312 /* Sequence to disable CLKOUT_DP */
5313 static void lpt_disable_clkout_dp(struct drm_device *dev)
5314 {
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         uint32_t reg, tmp;
5317
5318         mutex_lock(&dev_priv->dpio_lock);
5319
5320         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5321                SBI_GEN0 : SBI_DBUFF0;
5322         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5323         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5324         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5325
5326         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5327         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5328                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5329                         tmp |= SBI_SSCCTL_PATHALT;
5330                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5331                         udelay(32);
5332                 }
5333                 tmp |= SBI_SSCCTL_DISABLE;
5334                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5335         }
5336
5337         mutex_unlock(&dev_priv->dpio_lock);
5338 }
5339
5340 static void lpt_init_pch_refclk(struct drm_device *dev)
5341 {
5342         struct drm_mode_config *mode_config = &dev->mode_config;
5343         struct intel_encoder *encoder;
5344         bool has_vga = false;
5345
5346         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5347                 switch (encoder->type) {
5348                 case INTEL_OUTPUT_ANALOG:
5349                         has_vga = true;
5350                         break;
5351                 }
5352         }
5353
5354         if (has_vga)
5355                 lpt_enable_clkout_dp(dev, true, true);
5356         else
5357                 lpt_disable_clkout_dp(dev);
5358 }
5359
5360 /*
5361  * Initialize reference clocks when the driver loads
5362  */
5363 void intel_init_pch_refclk(struct drm_device *dev)
5364 {
5365         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5366                 ironlake_init_pch_refclk(dev);
5367         else if (HAS_PCH_LPT(dev))
5368                 lpt_init_pch_refclk(dev);
5369 }
5370
5371 static int ironlake_get_refclk(struct drm_crtc *crtc)
5372 {
5373         struct drm_device *dev = crtc->dev;
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct intel_encoder *encoder;
5376         int num_connectors = 0;
5377         bool is_lvds = false;
5378
5379         for_each_encoder_on_crtc(dev, crtc, encoder) {
5380                 switch (encoder->type) {
5381                 case INTEL_OUTPUT_LVDS:
5382                         is_lvds = true;
5383                         break;
5384                 }
5385                 num_connectors++;
5386         }
5387
5388         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5389                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5390                               dev_priv->vbt.lvds_ssc_freq);
5391                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5392         }
5393
5394         return 120000;
5395 }
5396
5397 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5398 {
5399         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401         int pipe = intel_crtc->pipe;
5402         uint32_t val;
5403
5404         val = 0;
5405
5406         switch (intel_crtc->config.pipe_bpp) {
5407         case 18:
5408                 val |= PIPECONF_6BPC;
5409                 break;
5410         case 24:
5411                 val |= PIPECONF_8BPC;
5412                 break;
5413         case 30:
5414                 val |= PIPECONF_10BPC;
5415                 break;
5416         case 36:
5417                 val |= PIPECONF_12BPC;
5418                 break;
5419         default:
5420                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5421                 BUG();
5422         }
5423
5424         if (intel_crtc->config.dither)
5425                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5426
5427         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5428                 val |= PIPECONF_INTERLACED_ILK;
5429         else
5430                 val |= PIPECONF_PROGRESSIVE;
5431
5432         if (intel_crtc->config.limited_color_range)
5433                 val |= PIPECONF_COLOR_RANGE_SELECT;
5434
5435         I915_WRITE(PIPECONF(pipe), val);
5436         POSTING_READ(PIPECONF(pipe));
5437 }
5438
5439 /*
5440  * Set up the pipe CSC unit.
5441  *
5442  * Currently only full range RGB to limited range RGB conversion
5443  * is supported, but eventually this should handle various
5444  * RGB<->YCbCr scenarios as well.
5445  */
5446 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5447 {
5448         struct drm_device *dev = crtc->dev;
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5451         int pipe = intel_crtc->pipe;
5452         uint16_t coeff = 0x7800; /* 1.0 */
5453
5454         /*
5455          * TODO: Check what kind of values actually come out of the pipe
5456          * with these coeff/postoff values and adjust to get the best
5457          * accuracy. Perhaps we even need to take the bpc value into
5458          * consideration.
5459          */
5460
5461         if (intel_crtc->config.limited_color_range)
5462                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5463
5464         /*
5465          * GY/GU and RY/RU should be the other way around according
5466          * to BSpec, but reality doesn't agree. Just set them up in
5467          * a way that results in the correct picture.
5468          */
5469         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5470         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5471
5472         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5473         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5474
5475         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5476         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5477
5478         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5479         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5480         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5481
5482         if (INTEL_INFO(dev)->gen > 6) {
5483                 uint16_t postoff = 0;
5484
5485                 if (intel_crtc->config.limited_color_range)
5486                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5487
5488                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5489                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5490                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5491
5492                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5493         } else {
5494                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5495
5496                 if (intel_crtc->config.limited_color_range)
5497                         mode |= CSC_BLACK_SCREEN_OFFSET;
5498
5499                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5500         }
5501 }
5502
5503 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5504 {
5505         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5508         uint32_t val;
5509
5510         val = 0;
5511
5512         if (intel_crtc->config.dither)
5513                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5514
5515         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5516                 val |= PIPECONF_INTERLACED_ILK;
5517         else
5518                 val |= PIPECONF_PROGRESSIVE;
5519
5520         I915_WRITE(PIPECONF(cpu_transcoder), val);
5521         POSTING_READ(PIPECONF(cpu_transcoder));
5522
5523         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5524         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5525 }
5526
5527 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5528                                     intel_clock_t *clock,
5529                                     bool *has_reduced_clock,
5530                                     intel_clock_t *reduced_clock)
5531 {
5532         struct drm_device *dev = crtc->dev;
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         struct intel_encoder *intel_encoder;
5535         int refclk;
5536         const intel_limit_t *limit;
5537         bool ret, is_lvds = false;
5538
5539         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5540                 switch (intel_encoder->type) {
5541                 case INTEL_OUTPUT_LVDS:
5542                         is_lvds = true;
5543                         break;
5544                 }
5545         }
5546
5547         refclk = ironlake_get_refclk(crtc);
5548
5549         /*
5550          * Returns a set of divisors for the desired target clock with the given
5551          * refclk, or FALSE.  The returned values represent the clock equation:
5552          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5553          */
5554         limit = intel_limit(crtc, refclk);
5555         ret = dev_priv->display.find_dpll(limit, crtc,
5556                                           to_intel_crtc(crtc)->config.port_clock,
5557                                           refclk, NULL, clock);
5558         if (!ret)
5559                 return false;
5560
5561         if (is_lvds && dev_priv->lvds_downclock_avail) {
5562                 /*
5563                  * Ensure we match the reduced clock's P to the target clock.
5564                  * If the clocks don't match, we can't switch the display clock
5565                  * by using the FP0/FP1. In such case we will disable the LVDS
5566                  * downclock feature.
5567                 */
5568                 *has_reduced_clock =
5569                         dev_priv->display.find_dpll(limit, crtc,
5570                                                     dev_priv->lvds_downclock,
5571                                                     refclk, clock,
5572                                                     reduced_clock);
5573         }
5574
5575         return true;
5576 }
5577
5578 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5579 {
5580         struct drm_i915_private *dev_priv = dev->dev_private;
5581         uint32_t temp;
5582
5583         temp = I915_READ(SOUTH_CHICKEN1);
5584         if (temp & FDI_BC_BIFURCATION_SELECT)
5585                 return;
5586
5587         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5588         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5589
5590         temp |= FDI_BC_BIFURCATION_SELECT;
5591         DRM_DEBUG_KMS("enabling fdi C rx\n");
5592         I915_WRITE(SOUTH_CHICKEN1, temp);
5593         POSTING_READ(SOUTH_CHICKEN1);
5594 }
5595
5596 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5597 {
5598         struct drm_device *dev = intel_crtc->base.dev;
5599         struct drm_i915_private *dev_priv = dev->dev_private;
5600
5601         switch (intel_crtc->pipe) {
5602         case PIPE_A:
5603                 break;
5604         case PIPE_B:
5605                 if (intel_crtc->config.fdi_lanes > 2)
5606                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5607                 else
5608                         cpt_enable_fdi_bc_bifurcation(dev);
5609
5610                 break;
5611         case PIPE_C:
5612                 cpt_enable_fdi_bc_bifurcation(dev);
5613
5614                 break;
5615         default:
5616                 BUG();
5617         }
5618 }
5619
5620 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5621 {
5622         /*
5623          * Account for spread spectrum to avoid
5624          * oversubscribing the link. Max center spread
5625          * is 2.5%; use 5% for safety's sake.
5626          */
5627         u32 bps = target_clock * bpp * 21 / 20;
5628         return bps / (link_bw * 8) + 1;
5629 }
5630
5631 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5632 {
5633         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5634 }
5635
5636 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5637                                       u32 *fp,
5638                                       intel_clock_t *reduced_clock, u32 *fp2)
5639 {
5640         struct drm_crtc *crtc = &intel_crtc->base;
5641         struct drm_device *dev = crtc->dev;
5642         struct drm_i915_private *dev_priv = dev->dev_private;
5643         struct intel_encoder *intel_encoder;
5644         uint32_t dpll;
5645         int factor, num_connectors = 0;
5646         bool is_lvds = false, is_sdvo = false;
5647
5648         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5649                 switch (intel_encoder->type) {
5650                 case INTEL_OUTPUT_LVDS:
5651                         is_lvds = true;
5652                         break;
5653                 case INTEL_OUTPUT_SDVO:
5654                 case INTEL_OUTPUT_HDMI:
5655                         is_sdvo = true;
5656                         break;
5657                 }
5658
5659                 num_connectors++;
5660         }
5661
5662         /* Enable autotuning of the PLL clock (if permissible) */
5663         factor = 21;
5664         if (is_lvds) {
5665                 if ((intel_panel_use_ssc(dev_priv) &&
5666                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5667                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5668                         factor = 25;
5669         } else if (intel_crtc->config.sdvo_tv_clock)
5670                 factor = 20;
5671
5672         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5673                 *fp |= FP_CB_TUNE;
5674
5675         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5676                 *fp2 |= FP_CB_TUNE;
5677
5678         dpll = 0;
5679
5680         if (is_lvds)
5681                 dpll |= DPLLB_MODE_LVDS;
5682         else
5683                 dpll |= DPLLB_MODE_DAC_SERIAL;
5684
5685         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5686                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5687
5688         if (is_sdvo)
5689                 dpll |= DPLL_SDVO_HIGH_SPEED;
5690         if (intel_crtc->config.has_dp_encoder)
5691                 dpll |= DPLL_SDVO_HIGH_SPEED;
5692
5693         /* compute bitmask from p1 value */
5694         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5695         /* also FPA1 */
5696         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5697
5698         switch (intel_crtc->config.dpll.p2) {
5699         case 5:
5700                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5701                 break;
5702         case 7:
5703                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5704                 break;
5705         case 10:
5706                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5707                 break;
5708         case 14:
5709                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5710                 break;
5711         }
5712
5713         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5714                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5715         else
5716                 dpll |= PLL_REF_INPUT_DREFCLK;
5717
5718         return dpll | DPLL_VCO_ENABLE;
5719 }
5720
5721 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5722                                   int x, int y,
5723                                   struct drm_framebuffer *fb)
5724 {
5725         struct drm_device *dev = crtc->dev;
5726         struct drm_i915_private *dev_priv = dev->dev_private;
5727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5728         int pipe = intel_crtc->pipe;
5729         int plane = intel_crtc->plane;
5730         int num_connectors = 0;
5731         intel_clock_t clock, reduced_clock;
5732         u32 dpll = 0, fp = 0, fp2 = 0;
5733         bool ok, has_reduced_clock = false;
5734         bool is_lvds = false;
5735         struct intel_encoder *encoder;
5736         struct intel_shared_dpll *pll;
5737         int ret;
5738
5739         for_each_encoder_on_crtc(dev, crtc, encoder) {
5740                 switch (encoder->type) {
5741                 case INTEL_OUTPUT_LVDS:
5742                         is_lvds = true;
5743                         break;
5744                 }
5745
5746                 num_connectors++;
5747         }
5748
5749         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5750              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5751
5752         ok = ironlake_compute_clocks(crtc, &clock,
5753                                      &has_reduced_clock, &reduced_clock);
5754         if (!ok && !intel_crtc->config.clock_set) {
5755                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5756                 return -EINVAL;
5757         }
5758         /* Compat-code for transition, will disappear. */
5759         if (!intel_crtc->config.clock_set) {
5760                 intel_crtc->config.dpll.n = clock.n;
5761                 intel_crtc->config.dpll.m1 = clock.m1;
5762                 intel_crtc->config.dpll.m2 = clock.m2;
5763                 intel_crtc->config.dpll.p1 = clock.p1;
5764                 intel_crtc->config.dpll.p2 = clock.p2;
5765         }
5766
5767         /* Ensure that the cursor is valid for the new mode before changing... */
5768         intel_crtc_update_cursor(crtc, true);
5769
5770         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5771         if (intel_crtc->config.has_pch_encoder) {
5772                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5773                 if (has_reduced_clock)
5774                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5775
5776                 dpll = ironlake_compute_dpll(intel_crtc,
5777                                              &fp, &reduced_clock,
5778                                              has_reduced_clock ? &fp2 : NULL);
5779
5780                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5781                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5782                 if (has_reduced_clock)
5783                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5784                 else
5785                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5786
5787                 pll = intel_get_shared_dpll(intel_crtc);
5788                 if (pll == NULL) {
5789                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5790                                          pipe_name(pipe));
5791                         return -EINVAL;
5792                 }
5793         } else
5794                 intel_put_shared_dpll(intel_crtc);
5795
5796         if (intel_crtc->config.has_dp_encoder)
5797                 intel_dp_set_m_n(intel_crtc);
5798
5799         if (is_lvds && has_reduced_clock && i915_powersave)
5800                 intel_crtc->lowfreq_avail = true;
5801         else
5802                 intel_crtc->lowfreq_avail = false;
5803
5804         if (intel_crtc->config.has_pch_encoder) {
5805                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5806
5807         }
5808
5809         intel_set_pipe_timings(intel_crtc);
5810
5811         if (intel_crtc->config.has_pch_encoder) {
5812                 intel_cpu_transcoder_set_m_n(intel_crtc,
5813                                              &intel_crtc->config.fdi_m_n);
5814         }
5815
5816         if (IS_IVYBRIDGE(dev))
5817                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5818
5819         ironlake_set_pipeconf(crtc);
5820
5821         /* Set up the display plane register */
5822         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5823         POSTING_READ(DSPCNTR(plane));
5824
5825         ret = intel_pipe_set_base(crtc, x, y, fb);
5826
5827         intel_update_watermarks(dev);
5828
5829         return ret;
5830 }
5831
5832 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5833                                         struct intel_crtc_config *pipe_config)
5834 {
5835         struct drm_device *dev = crtc->base.dev;
5836         struct drm_i915_private *dev_priv = dev->dev_private;
5837         enum transcoder transcoder = pipe_config->cpu_transcoder;
5838
5839         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5840         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5841         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5842                                         & ~TU_SIZE_MASK;
5843         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5844         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5845                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5846 }
5847
5848 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5849                                      struct intel_crtc_config *pipe_config)
5850 {
5851         struct drm_device *dev = crtc->base.dev;
5852         struct drm_i915_private *dev_priv = dev->dev_private;
5853         uint32_t tmp;
5854
5855         tmp = I915_READ(PF_CTL(crtc->pipe));
5856
5857         if (tmp & PF_ENABLE) {
5858                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5859                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5860
5861                 /* We currently do not free assignements of panel fitters on
5862                  * ivb/hsw (since we don't use the higher upscaling modes which
5863                  * differentiates them) so just WARN about this case for now. */
5864                 if (IS_GEN7(dev)) {
5865                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5866                                 PF_PIPE_SEL_IVB(crtc->pipe));
5867                 }
5868         }
5869 }
5870
5871 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5872                                      struct intel_crtc_config *pipe_config)
5873 {
5874         struct drm_device *dev = crtc->base.dev;
5875         struct drm_i915_private *dev_priv = dev->dev_private;
5876         uint32_t tmp;
5877
5878         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5879         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5880
5881         tmp = I915_READ(PIPECONF(crtc->pipe));
5882         if (!(tmp & PIPECONF_ENABLE))
5883                 return false;
5884
5885         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5886                 struct intel_shared_dpll *pll;
5887
5888                 pipe_config->has_pch_encoder = true;
5889
5890                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5891                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5892                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5893
5894                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5895
5896                 if (HAS_PCH_IBX(dev_priv->dev)) {
5897                         pipe_config->shared_dpll =
5898                                 (enum intel_dpll_id) crtc->pipe;
5899                 } else {
5900                         tmp = I915_READ(PCH_DPLL_SEL);
5901                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5902                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5903                         else
5904                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5905                 }
5906
5907                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5908
5909                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5910                                            &pipe_config->dpll_hw_state));
5911
5912                 tmp = pipe_config->dpll_hw_state.dpll;
5913                 pipe_config->pixel_multiplier =
5914                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5915                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5916         } else {
5917                 pipe_config->pixel_multiplier = 1;
5918         }
5919
5920         intel_get_pipe_timings(crtc, pipe_config);
5921
5922         ironlake_get_pfit_config(crtc, pipe_config);
5923
5924         return true;
5925 }
5926
5927 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5928 {
5929         struct drm_device *dev = dev_priv->dev;
5930         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5931         struct intel_crtc *crtc;
5932         unsigned long irqflags;
5933         uint32_t val, pch_hpd_mask;
5934
5935         pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5936         if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5937                 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5938
5939         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5940                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5941                      pipe_name(crtc->pipe));
5942
5943         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5944         WARN(plls->spll_refcount, "SPLL enabled\n");
5945         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5946         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5947         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5948         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5949              "CPU PWM1 enabled\n");
5950         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5951              "CPU PWM2 enabled\n");
5952         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5953              "PCH PWM1 enabled\n");
5954         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5955              "Utility pin enabled\n");
5956         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5957
5958         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5959         val = I915_READ(DEIMR);
5960         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5961              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5962         val = I915_READ(SDEIMR);
5963         WARN((val & ~pch_hpd_mask) != val,
5964              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5965         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5966 }
5967
5968 /*
5969  * This function implements pieces of two sequences from BSpec:
5970  * - Sequence for display software to disable LCPLL
5971  * - Sequence for display software to allow package C8+
5972  * The steps implemented here are just the steps that actually touch the LCPLL
5973  * register. Callers should take care of disabling all the display engine
5974  * functions, doing the mode unset, fixing interrupts, etc.
5975  */
5976 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5977                        bool switch_to_fclk, bool allow_power_down)
5978 {
5979         uint32_t val;
5980
5981         assert_can_disable_lcpll(dev_priv);
5982
5983         val = I915_READ(LCPLL_CTL);
5984
5985         if (switch_to_fclk) {
5986                 val |= LCPLL_CD_SOURCE_FCLK;
5987                 I915_WRITE(LCPLL_CTL, val);
5988
5989                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5990                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
5991                         DRM_ERROR("Switching to FCLK failed\n");
5992
5993                 val = I915_READ(LCPLL_CTL);
5994         }
5995
5996         val |= LCPLL_PLL_DISABLE;
5997         I915_WRITE(LCPLL_CTL, val);
5998         POSTING_READ(LCPLL_CTL);
5999
6000         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6001                 DRM_ERROR("LCPLL still locked\n");
6002
6003         val = I915_READ(D_COMP);
6004         val |= D_COMP_COMP_DISABLE;
6005         I915_WRITE(D_COMP, val);
6006         POSTING_READ(D_COMP);
6007         ndelay(100);
6008
6009         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6010                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6011
6012         if (allow_power_down) {
6013                 val = I915_READ(LCPLL_CTL);
6014                 val |= LCPLL_POWER_DOWN_ALLOW;
6015                 I915_WRITE(LCPLL_CTL, val);
6016                 POSTING_READ(LCPLL_CTL);
6017         }
6018 }
6019
6020 /*
6021  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6022  * source.
6023  */
6024 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6025 {
6026         uint32_t val;
6027
6028         val = I915_READ(LCPLL_CTL);
6029
6030         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6031                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6032                 return;
6033
6034         if (val & LCPLL_POWER_DOWN_ALLOW) {
6035                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6036                 I915_WRITE(LCPLL_CTL, val);
6037         }
6038
6039         val = I915_READ(D_COMP);
6040         val |= D_COMP_COMP_FORCE;
6041         val &= ~D_COMP_COMP_DISABLE;
6042         I915_WRITE(D_COMP, val);
6043         I915_READ(D_COMP);
6044
6045         val = I915_READ(LCPLL_CTL);
6046         val &= ~LCPLL_PLL_DISABLE;
6047         I915_WRITE(LCPLL_CTL, val);
6048
6049         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6050                 DRM_ERROR("LCPLL not locked yet\n");
6051
6052         if (val & LCPLL_CD_SOURCE_FCLK) {
6053                 val = I915_READ(LCPLL_CTL);
6054                 val &= ~LCPLL_CD_SOURCE_FCLK;
6055                 I915_WRITE(LCPLL_CTL, val);
6056
6057                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6058                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6059                         DRM_ERROR("Switching back to LCPLL failed\n");
6060         }
6061 }
6062
6063 static void haswell_modeset_global_resources(struct drm_device *dev)
6064 {
6065         bool enable = false;
6066         struct intel_crtc *crtc;
6067
6068         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6069                 if (!crtc->base.enabled)
6070                         continue;
6071
6072                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6073                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6074                         enable = true;
6075         }
6076
6077         intel_set_power_well(dev, enable);
6078 }
6079
6080 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6081                                  int x, int y,
6082                                  struct drm_framebuffer *fb)
6083 {
6084         struct drm_device *dev = crtc->dev;
6085         struct drm_i915_private *dev_priv = dev->dev_private;
6086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087         int plane = intel_crtc->plane;
6088         int ret;
6089
6090         if (!intel_ddi_pll_mode_set(crtc))
6091                 return -EINVAL;
6092
6093         /* Ensure that the cursor is valid for the new mode before changing... */
6094         intel_crtc_update_cursor(crtc, true);
6095
6096         if (intel_crtc->config.has_dp_encoder)
6097                 intel_dp_set_m_n(intel_crtc);
6098
6099         intel_crtc->lowfreq_avail = false;
6100
6101         intel_set_pipe_timings(intel_crtc);
6102
6103         if (intel_crtc->config.has_pch_encoder) {
6104                 intel_cpu_transcoder_set_m_n(intel_crtc,
6105                                              &intel_crtc->config.fdi_m_n);
6106         }
6107
6108         haswell_set_pipeconf(crtc);
6109
6110         intel_set_pipe_csc(crtc);
6111
6112         /* Set up the display plane register */
6113         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6114         POSTING_READ(DSPCNTR(plane));
6115
6116         ret = intel_pipe_set_base(crtc, x, y, fb);
6117
6118         intel_update_watermarks(dev);
6119
6120         return ret;
6121 }
6122
6123 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6124                                     struct intel_crtc_config *pipe_config)
6125 {
6126         struct drm_device *dev = crtc->base.dev;
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         enum intel_display_power_domain pfit_domain;
6129         uint32_t tmp;
6130
6131         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6132         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6133
6134         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6135         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6136                 enum pipe trans_edp_pipe;
6137                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6138                 default:
6139                         WARN(1, "unknown pipe linked to edp transcoder\n");
6140                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6141                 case TRANS_DDI_EDP_INPUT_A_ON:
6142                         trans_edp_pipe = PIPE_A;
6143                         break;
6144                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6145                         trans_edp_pipe = PIPE_B;
6146                         break;
6147                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6148                         trans_edp_pipe = PIPE_C;
6149                         break;
6150                 }
6151
6152                 if (trans_edp_pipe == crtc->pipe)
6153                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6154         }
6155
6156         if (!intel_display_power_enabled(dev,
6157                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6158                 return false;
6159
6160         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6161         if (!(tmp & PIPECONF_ENABLE))
6162                 return false;
6163
6164         /*
6165          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6166          * DDI E. So just check whether this pipe is wired to DDI E and whether
6167          * the PCH transcoder is on.
6168          */
6169         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6170         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6171             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6172                 pipe_config->has_pch_encoder = true;
6173
6174                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6175                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6176                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6177
6178                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6179         }
6180
6181         intel_get_pipe_timings(crtc, pipe_config);
6182
6183         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6184         if (intel_display_power_enabled(dev, pfit_domain))
6185                 ironlake_get_pfit_config(crtc, pipe_config);
6186
6187         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6188                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6189
6190         pipe_config->pixel_multiplier = 1;
6191
6192         return true;
6193 }
6194
6195 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6196                                int x, int y,
6197                                struct drm_framebuffer *fb)
6198 {
6199         struct drm_device *dev = crtc->dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201         struct intel_encoder *encoder;
6202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6204         int pipe = intel_crtc->pipe;
6205         int ret;
6206
6207         drm_vblank_pre_modeset(dev, pipe);
6208
6209         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6210
6211         drm_vblank_post_modeset(dev, pipe);
6212
6213         if (ret != 0)
6214                 return ret;
6215
6216         for_each_encoder_on_crtc(dev, crtc, encoder) {
6217                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6218                         encoder->base.base.id,
6219                         drm_get_encoder_name(&encoder->base),
6220                         mode->base.id, mode->name);
6221                 encoder->mode_set(encoder);
6222         }
6223
6224         return 0;
6225 }
6226
6227 static bool intel_eld_uptodate(struct drm_connector *connector,
6228                                int reg_eldv, uint32_t bits_eldv,
6229                                int reg_elda, uint32_t bits_elda,
6230                                int reg_edid)
6231 {
6232         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6233         uint8_t *eld = connector->eld;
6234         uint32_t i;
6235
6236         i = I915_READ(reg_eldv);
6237         i &= bits_eldv;
6238
6239         if (!eld[0])
6240                 return !i;
6241
6242         if (!i)
6243                 return false;
6244
6245         i = I915_READ(reg_elda);
6246         i &= ~bits_elda;
6247         I915_WRITE(reg_elda, i);
6248
6249         for (i = 0; i < eld[2]; i++)
6250                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6251                         return false;
6252
6253         return true;
6254 }
6255
6256 static void g4x_write_eld(struct drm_connector *connector,
6257                           struct drm_crtc *crtc)
6258 {
6259         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6260         uint8_t *eld = connector->eld;
6261         uint32_t eldv;
6262         uint32_t len;
6263         uint32_t i;
6264
6265         i = I915_READ(G4X_AUD_VID_DID);
6266
6267         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6268                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6269         else
6270                 eldv = G4X_ELDV_DEVCTG;
6271
6272         if (intel_eld_uptodate(connector,
6273                                G4X_AUD_CNTL_ST, eldv,
6274                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6275                                G4X_HDMIW_HDMIEDID))
6276                 return;
6277
6278         i = I915_READ(G4X_AUD_CNTL_ST);
6279         i &= ~(eldv | G4X_ELD_ADDR);
6280         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6281         I915_WRITE(G4X_AUD_CNTL_ST, i);
6282
6283         if (!eld[0])
6284                 return;
6285
6286         len = min_t(uint8_t, eld[2], len);
6287         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6288         for (i = 0; i < len; i++)
6289                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6290
6291         i = I915_READ(G4X_AUD_CNTL_ST);
6292         i |= eldv;
6293         I915_WRITE(G4X_AUD_CNTL_ST, i);
6294 }
6295
6296 static void haswell_write_eld(struct drm_connector *connector,
6297                                      struct drm_crtc *crtc)
6298 {
6299         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6300         uint8_t *eld = connector->eld;
6301         struct drm_device *dev = crtc->dev;
6302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303         uint32_t eldv;
6304         uint32_t i;
6305         int len;
6306         int pipe = to_intel_crtc(crtc)->pipe;
6307         int tmp;
6308
6309         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6310         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6311         int aud_config = HSW_AUD_CFG(pipe);
6312         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6313
6314
6315         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6316
6317         /* Audio output enable */
6318         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6319         tmp = I915_READ(aud_cntrl_st2);
6320         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6321         I915_WRITE(aud_cntrl_st2, tmp);
6322
6323         /* Wait for 1 vertical blank */
6324         intel_wait_for_vblank(dev, pipe);
6325
6326         /* Set ELD valid state */
6327         tmp = I915_READ(aud_cntrl_st2);
6328         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6329         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6330         I915_WRITE(aud_cntrl_st2, tmp);
6331         tmp = I915_READ(aud_cntrl_st2);
6332         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6333
6334         /* Enable HDMI mode */
6335         tmp = I915_READ(aud_config);
6336         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6337         /* clear N_programing_enable and N_value_index */
6338         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6339         I915_WRITE(aud_config, tmp);
6340
6341         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6342
6343         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6344         intel_crtc->eld_vld = true;
6345
6346         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6347                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6348                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6349                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6350         } else
6351                 I915_WRITE(aud_config, 0);
6352
6353         if (intel_eld_uptodate(connector,
6354                                aud_cntrl_st2, eldv,
6355                                aud_cntl_st, IBX_ELD_ADDRESS,
6356                                hdmiw_hdmiedid))
6357                 return;
6358
6359         i = I915_READ(aud_cntrl_st2);
6360         i &= ~eldv;
6361         I915_WRITE(aud_cntrl_st2, i);
6362
6363         if (!eld[0])
6364                 return;
6365
6366         i = I915_READ(aud_cntl_st);
6367         i &= ~IBX_ELD_ADDRESS;
6368         I915_WRITE(aud_cntl_st, i);
6369         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6370         DRM_DEBUG_DRIVER("port num:%d\n", i);
6371
6372         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6373         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6374         for (i = 0; i < len; i++)
6375                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6376
6377         i = I915_READ(aud_cntrl_st2);
6378         i |= eldv;
6379         I915_WRITE(aud_cntrl_st2, i);
6380
6381 }
6382
6383 static void ironlake_write_eld(struct drm_connector *connector,
6384                                      struct drm_crtc *crtc)
6385 {
6386         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6387         uint8_t *eld = connector->eld;
6388         uint32_t eldv;
6389         uint32_t i;
6390         int len;
6391         int hdmiw_hdmiedid;
6392         int aud_config;
6393         int aud_cntl_st;
6394         int aud_cntrl_st2;
6395         int pipe = to_intel_crtc(crtc)->pipe;
6396
6397         if (HAS_PCH_IBX(connector->dev)) {
6398                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6399                 aud_config = IBX_AUD_CFG(pipe);
6400                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6401                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6402         } else {
6403                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6404                 aud_config = CPT_AUD_CFG(pipe);
6405                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6406                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6407         }
6408
6409         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6410
6411         i = I915_READ(aud_cntl_st);
6412         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6413         if (!i) {
6414                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6415                 /* operate blindly on all ports */
6416                 eldv = IBX_ELD_VALIDB;
6417                 eldv |= IBX_ELD_VALIDB << 4;
6418                 eldv |= IBX_ELD_VALIDB << 8;
6419         } else {
6420                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6421                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6422         }
6423
6424         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6425                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6426                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6427                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6428         } else
6429                 I915_WRITE(aud_config, 0);
6430
6431         if (intel_eld_uptodate(connector,
6432                                aud_cntrl_st2, eldv,
6433                                aud_cntl_st, IBX_ELD_ADDRESS,
6434                                hdmiw_hdmiedid))
6435                 return;
6436
6437         i = I915_READ(aud_cntrl_st2);
6438         i &= ~eldv;
6439         I915_WRITE(aud_cntrl_st2, i);
6440
6441         if (!eld[0])
6442                 return;
6443
6444         i = I915_READ(aud_cntl_st);
6445         i &= ~IBX_ELD_ADDRESS;
6446         I915_WRITE(aud_cntl_st, i);
6447
6448         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6449         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6450         for (i = 0; i < len; i++)
6451                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6452
6453         i = I915_READ(aud_cntrl_st2);
6454         i |= eldv;
6455         I915_WRITE(aud_cntrl_st2, i);
6456 }
6457
6458 void intel_write_eld(struct drm_encoder *encoder,
6459                      struct drm_display_mode *mode)
6460 {
6461         struct drm_crtc *crtc = encoder->crtc;
6462         struct drm_connector *connector;
6463         struct drm_device *dev = encoder->dev;
6464         struct drm_i915_private *dev_priv = dev->dev_private;
6465
6466         connector = drm_select_eld(encoder, mode);
6467         if (!connector)
6468                 return;
6469
6470         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6471                          connector->base.id,
6472                          drm_get_connector_name(connector),
6473                          connector->encoder->base.id,
6474                          drm_get_encoder_name(connector->encoder));
6475
6476         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6477
6478         if (dev_priv->display.write_eld)
6479                 dev_priv->display.write_eld(connector, crtc);
6480 }
6481
6482 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6483 void intel_crtc_load_lut(struct drm_crtc *crtc)
6484 {
6485         struct drm_device *dev = crtc->dev;
6486         struct drm_i915_private *dev_priv = dev->dev_private;
6487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6488         enum pipe pipe = intel_crtc->pipe;
6489         int palreg = PALETTE(pipe);
6490         int i;
6491         bool reenable_ips = false;
6492
6493         /* The clocks have to be on to load the palette. */
6494         if (!crtc->enabled || !intel_crtc->active)
6495                 return;
6496
6497         if (!HAS_PCH_SPLIT(dev_priv->dev))
6498                 assert_pll_enabled(dev_priv, pipe);
6499
6500         /* use legacy palette for Ironlake */
6501         if (HAS_PCH_SPLIT(dev))
6502                 palreg = LGC_PALETTE(pipe);
6503
6504         /* Workaround : Do not read or write the pipe palette/gamma data while
6505          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6506          */
6507         if (intel_crtc->config.ips_enabled &&
6508             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6509              GAMMA_MODE_MODE_SPLIT)) {
6510                 hsw_disable_ips(intel_crtc);
6511                 reenable_ips = true;
6512         }
6513
6514         for (i = 0; i < 256; i++) {
6515                 I915_WRITE(palreg + 4 * i,
6516                            (intel_crtc->lut_r[i] << 16) |
6517                            (intel_crtc->lut_g[i] << 8) |
6518                            intel_crtc->lut_b[i]);
6519         }
6520
6521         if (reenable_ips)
6522                 hsw_enable_ips(intel_crtc);
6523 }
6524
6525 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6526 {
6527         struct drm_device *dev = crtc->dev;
6528         struct drm_i915_private *dev_priv = dev->dev_private;
6529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6530         bool visible = base != 0;
6531         u32 cntl;
6532
6533         if (intel_crtc->cursor_visible == visible)
6534                 return;
6535
6536         cntl = I915_READ(_CURACNTR);
6537         if (visible) {
6538                 /* On these chipsets we can only modify the base whilst
6539                  * the cursor is disabled.
6540                  */
6541                 I915_WRITE(_CURABASE, base);
6542
6543                 cntl &= ~(CURSOR_FORMAT_MASK);
6544                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6545                 cntl |= CURSOR_ENABLE |
6546                         CURSOR_GAMMA_ENABLE |
6547                         CURSOR_FORMAT_ARGB;
6548         } else
6549                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6550         I915_WRITE(_CURACNTR, cntl);
6551
6552         intel_crtc->cursor_visible = visible;
6553 }
6554
6555 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6556 {
6557         struct drm_device *dev = crtc->dev;
6558         struct drm_i915_private *dev_priv = dev->dev_private;
6559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6560         int pipe = intel_crtc->pipe;
6561         bool visible = base != 0;
6562
6563         if (intel_crtc->cursor_visible != visible) {
6564                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6565                 if (base) {
6566                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6567                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6568                         cntl |= pipe << 28; /* Connect to correct pipe */
6569                 } else {
6570                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6571                         cntl |= CURSOR_MODE_DISABLE;
6572                 }
6573                 I915_WRITE(CURCNTR(pipe), cntl);
6574
6575                 intel_crtc->cursor_visible = visible;
6576         }
6577         /* and commit changes on next vblank */
6578         I915_WRITE(CURBASE(pipe), base);
6579 }
6580
6581 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6582 {
6583         struct drm_device *dev = crtc->dev;
6584         struct drm_i915_private *dev_priv = dev->dev_private;
6585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586         int pipe = intel_crtc->pipe;
6587         bool visible = base != 0;
6588
6589         if (intel_crtc->cursor_visible != visible) {
6590                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6591                 if (base) {
6592                         cntl &= ~CURSOR_MODE;
6593                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6594                 } else {
6595                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6596                         cntl |= CURSOR_MODE_DISABLE;
6597                 }
6598                 if (IS_HASWELL(dev))
6599                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6600                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6601
6602                 intel_crtc->cursor_visible = visible;
6603         }
6604         /* and commit changes on next vblank */
6605         I915_WRITE(CURBASE_IVB(pipe), base);
6606 }
6607
6608 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6609 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6610                                      bool on)
6611 {
6612         struct drm_device *dev = crtc->dev;
6613         struct drm_i915_private *dev_priv = dev->dev_private;
6614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615         int pipe = intel_crtc->pipe;
6616         int x = intel_crtc->cursor_x;
6617         int y = intel_crtc->cursor_y;
6618         u32 base, pos;
6619         bool visible;
6620
6621         pos = 0;
6622
6623         if (on && crtc->enabled && crtc->fb) {
6624                 base = intel_crtc->cursor_addr;
6625                 if (x > (int) crtc->fb->width)
6626                         base = 0;
6627
6628                 if (y > (int) crtc->fb->height)
6629                         base = 0;
6630         } else
6631                 base = 0;
6632
6633         if (x < 0) {
6634                 if (x + intel_crtc->cursor_width < 0)
6635                         base = 0;
6636
6637                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6638                 x = -x;
6639         }
6640         pos |= x << CURSOR_X_SHIFT;
6641
6642         if (y < 0) {
6643                 if (y + intel_crtc->cursor_height < 0)
6644                         base = 0;
6645
6646                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6647                 y = -y;
6648         }
6649         pos |= y << CURSOR_Y_SHIFT;
6650
6651         visible = base != 0;
6652         if (!visible && !intel_crtc->cursor_visible)
6653                 return;
6654
6655         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6656                 I915_WRITE(CURPOS_IVB(pipe), pos);
6657                 ivb_update_cursor(crtc, base);
6658         } else {
6659                 I915_WRITE(CURPOS(pipe), pos);
6660                 if (IS_845G(dev) || IS_I865G(dev))
6661                         i845_update_cursor(crtc, base);
6662                 else
6663                         i9xx_update_cursor(crtc, base);
6664         }
6665 }
6666
6667 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6668                                  struct drm_file *file,
6669                                  uint32_t handle,
6670                                  uint32_t width, uint32_t height)
6671 {
6672         struct drm_device *dev = crtc->dev;
6673         struct drm_i915_private *dev_priv = dev->dev_private;
6674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675         struct drm_i915_gem_object *obj;
6676         uint32_t addr;
6677         int ret;
6678
6679         /* if we want to turn off the cursor ignore width and height */
6680         if (!handle) {
6681                 DRM_DEBUG_KMS("cursor off\n");
6682                 addr = 0;
6683                 obj = NULL;
6684                 mutex_lock(&dev->struct_mutex);
6685                 goto finish;
6686         }
6687
6688         /* Currently we only support 64x64 cursors */
6689         if (width != 64 || height != 64) {
6690                 DRM_ERROR("we currently only support 64x64 cursors\n");
6691                 return -EINVAL;
6692         }
6693
6694         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6695         if (&obj->base == NULL)
6696                 return -ENOENT;
6697
6698         if (obj->base.size < width * height * 4) {
6699                 DRM_ERROR("buffer is to small\n");
6700                 ret = -ENOMEM;
6701                 goto fail;
6702         }
6703
6704         /* we only need to pin inside GTT if cursor is non-phy */
6705         mutex_lock(&dev->struct_mutex);
6706         if (!dev_priv->info->cursor_needs_physical) {
6707                 unsigned alignment;
6708
6709                 if (obj->tiling_mode) {
6710                         DRM_ERROR("cursor cannot be tiled\n");
6711                         ret = -EINVAL;
6712                         goto fail_locked;
6713                 }
6714
6715                 /* Note that the w/a also requires 2 PTE of padding following
6716                  * the bo. We currently fill all unused PTE with the shadow
6717                  * page and so we should always have valid PTE following the
6718                  * cursor preventing the VT-d warning.
6719                  */
6720                 alignment = 0;
6721                 if (need_vtd_wa(dev))
6722                         alignment = 64*1024;
6723
6724                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6725                 if (ret) {
6726                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6727                         goto fail_locked;
6728                 }
6729
6730                 ret = i915_gem_object_put_fence(obj);
6731                 if (ret) {
6732                         DRM_ERROR("failed to release fence for cursor");
6733                         goto fail_unpin;
6734                 }
6735
6736                 addr = i915_gem_obj_ggtt_offset(obj);
6737         } else {
6738                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6739                 ret = i915_gem_attach_phys_object(dev, obj,
6740                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6741                                                   align);
6742                 if (ret) {
6743                         DRM_ERROR("failed to attach phys object\n");
6744                         goto fail_locked;
6745                 }
6746                 addr = obj->phys_obj->handle->busaddr;
6747         }
6748
6749         if (IS_GEN2(dev))
6750                 I915_WRITE(CURSIZE, (height << 12) | width);
6751
6752  finish:
6753         if (intel_crtc->cursor_bo) {
6754                 if (dev_priv->info->cursor_needs_physical) {
6755                         if (intel_crtc->cursor_bo != obj)
6756                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6757                 } else
6758                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6759                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6760         }
6761
6762         mutex_unlock(&dev->struct_mutex);
6763
6764         intel_crtc->cursor_addr = addr;
6765         intel_crtc->cursor_bo = obj;
6766         intel_crtc->cursor_width = width;
6767         intel_crtc->cursor_height = height;
6768
6769         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6770
6771         return 0;
6772 fail_unpin:
6773         i915_gem_object_unpin(obj);
6774 fail_locked:
6775         mutex_unlock(&dev->struct_mutex);
6776 fail:
6777         drm_gem_object_unreference_unlocked(&obj->base);
6778         return ret;
6779 }
6780
6781 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6782 {
6783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784
6785         intel_crtc->cursor_x = x;
6786         intel_crtc->cursor_y = y;
6787
6788         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6789
6790         return 0;
6791 }
6792
6793 /** Sets the color ramps on behalf of RandR */
6794 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6795                                  u16 blue, int regno)
6796 {
6797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6798
6799         intel_crtc->lut_r[regno] = red >> 8;
6800         intel_crtc->lut_g[regno] = green >> 8;
6801         intel_crtc->lut_b[regno] = blue >> 8;
6802 }
6803
6804 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6805                              u16 *blue, int regno)
6806 {
6807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808
6809         *red = intel_crtc->lut_r[regno] << 8;
6810         *green = intel_crtc->lut_g[regno] << 8;
6811         *blue = intel_crtc->lut_b[regno] << 8;
6812 }
6813
6814 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6815                                  u16 *blue, uint32_t start, uint32_t size)
6816 {
6817         int end = (start + size > 256) ? 256 : start + size, i;
6818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819
6820         for (i = start; i < end; i++) {
6821                 intel_crtc->lut_r[i] = red[i] >> 8;
6822                 intel_crtc->lut_g[i] = green[i] >> 8;
6823                 intel_crtc->lut_b[i] = blue[i] >> 8;
6824         }
6825
6826         intel_crtc_load_lut(crtc);
6827 }
6828
6829 /* VESA 640x480x72Hz mode to set on the pipe */
6830 static struct drm_display_mode load_detect_mode = {
6831         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6832                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6833 };
6834
6835 static struct drm_framebuffer *
6836 intel_framebuffer_create(struct drm_device *dev,
6837                          struct drm_mode_fb_cmd2 *mode_cmd,
6838                          struct drm_i915_gem_object *obj)
6839 {
6840         struct intel_framebuffer *intel_fb;
6841         int ret;
6842
6843         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6844         if (!intel_fb) {
6845                 drm_gem_object_unreference_unlocked(&obj->base);
6846                 return ERR_PTR(-ENOMEM);
6847         }
6848
6849         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6850         if (ret) {
6851                 drm_gem_object_unreference_unlocked(&obj->base);
6852                 kfree(intel_fb);
6853                 return ERR_PTR(ret);
6854         }
6855
6856         return &intel_fb->base;
6857 }
6858
6859 static u32
6860 intel_framebuffer_pitch_for_width(int width, int bpp)
6861 {
6862         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6863         return ALIGN(pitch, 64);
6864 }
6865
6866 static u32
6867 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6868 {
6869         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6870         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6871 }
6872
6873 static struct drm_framebuffer *
6874 intel_framebuffer_create_for_mode(struct drm_device *dev,
6875                                   struct drm_display_mode *mode,
6876                                   int depth, int bpp)
6877 {
6878         struct drm_i915_gem_object *obj;
6879         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6880
6881         obj = i915_gem_alloc_object(dev,
6882                                     intel_framebuffer_size_for_mode(mode, bpp));
6883         if (obj == NULL)
6884                 return ERR_PTR(-ENOMEM);
6885
6886         mode_cmd.width = mode->hdisplay;
6887         mode_cmd.height = mode->vdisplay;
6888         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6889                                                                 bpp);
6890         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6891
6892         return intel_framebuffer_create(dev, &mode_cmd, obj);
6893 }
6894
6895 static struct drm_framebuffer *
6896 mode_fits_in_fbdev(struct drm_device *dev,
6897                    struct drm_display_mode *mode)
6898 {
6899         struct drm_i915_private *dev_priv = dev->dev_private;
6900         struct drm_i915_gem_object *obj;
6901         struct drm_framebuffer *fb;
6902
6903         if (dev_priv->fbdev == NULL)
6904                 return NULL;
6905
6906         obj = dev_priv->fbdev->ifb.obj;
6907         if (obj == NULL)
6908                 return NULL;
6909
6910         fb = &dev_priv->fbdev->ifb.base;
6911         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6912                                                                fb->bits_per_pixel))
6913                 return NULL;
6914
6915         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6916                 return NULL;
6917
6918         return fb;
6919 }
6920
6921 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6922                                 struct drm_display_mode *mode,
6923                                 struct intel_load_detect_pipe *old)
6924 {
6925         struct intel_crtc *intel_crtc;
6926         struct intel_encoder *intel_encoder =
6927                 intel_attached_encoder(connector);
6928         struct drm_crtc *possible_crtc;
6929         struct drm_encoder *encoder = &intel_encoder->base;
6930         struct drm_crtc *crtc = NULL;
6931         struct drm_device *dev = encoder->dev;
6932         struct drm_framebuffer *fb;
6933         int i = -1;
6934
6935         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6936                       connector->base.id, drm_get_connector_name(connector),
6937                       encoder->base.id, drm_get_encoder_name(encoder));
6938
6939         /*
6940          * Algorithm gets a little messy:
6941          *
6942          *   - if the connector already has an assigned crtc, use it (but make
6943          *     sure it's on first)
6944          *
6945          *   - try to find the first unused crtc that can drive this connector,
6946          *     and use that if we find one
6947          */
6948
6949         /* See if we already have a CRTC for this connector */
6950         if (encoder->crtc) {
6951                 crtc = encoder->crtc;
6952
6953                 mutex_lock(&crtc->mutex);
6954
6955                 old->dpms_mode = connector->dpms;
6956                 old->load_detect_temp = false;
6957
6958                 /* Make sure the crtc and connector are running */
6959                 if (connector->dpms != DRM_MODE_DPMS_ON)
6960                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6961
6962                 return true;
6963         }
6964
6965         /* Find an unused one (if possible) */
6966         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6967                 i++;
6968                 if (!(encoder->possible_crtcs & (1 << i)))
6969                         continue;
6970                 if (!possible_crtc->enabled) {
6971                         crtc = possible_crtc;
6972                         break;
6973                 }
6974         }
6975
6976         /*
6977          * If we didn't find an unused CRTC, don't use any.
6978          */
6979         if (!crtc) {
6980                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6981                 return false;
6982         }
6983
6984         mutex_lock(&crtc->mutex);
6985         intel_encoder->new_crtc = to_intel_crtc(crtc);
6986         to_intel_connector(connector)->new_encoder = intel_encoder;
6987
6988         intel_crtc = to_intel_crtc(crtc);
6989         old->dpms_mode = connector->dpms;
6990         old->load_detect_temp = true;
6991         old->release_fb = NULL;
6992
6993         if (!mode)
6994                 mode = &load_detect_mode;
6995
6996         /* We need a framebuffer large enough to accommodate all accesses
6997          * that the plane may generate whilst we perform load detection.
6998          * We can not rely on the fbcon either being present (we get called
6999          * during its initialisation to detect all boot displays, or it may
7000          * not even exist) or that it is large enough to satisfy the
7001          * requested mode.
7002          */
7003         fb = mode_fits_in_fbdev(dev, mode);
7004         if (fb == NULL) {
7005                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7006                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7007                 old->release_fb = fb;
7008         } else
7009                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7010         if (IS_ERR(fb)) {
7011                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7012                 mutex_unlock(&crtc->mutex);
7013                 return false;
7014         }
7015
7016         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7017                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7018                 if (old->release_fb)
7019                         old->release_fb->funcs->destroy(old->release_fb);
7020                 mutex_unlock(&crtc->mutex);
7021                 return false;
7022         }
7023
7024         /* let the connector get through one full cycle before testing */
7025         intel_wait_for_vblank(dev, intel_crtc->pipe);
7026         return true;
7027 }
7028
7029 void intel_release_load_detect_pipe(struct drm_connector *connector,
7030                                     struct intel_load_detect_pipe *old)
7031 {
7032         struct intel_encoder *intel_encoder =
7033                 intel_attached_encoder(connector);
7034         struct drm_encoder *encoder = &intel_encoder->base;
7035         struct drm_crtc *crtc = encoder->crtc;
7036
7037         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7038                       connector->base.id, drm_get_connector_name(connector),
7039                       encoder->base.id, drm_get_encoder_name(encoder));
7040
7041         if (old->load_detect_temp) {
7042                 to_intel_connector(connector)->new_encoder = NULL;
7043                 intel_encoder->new_crtc = NULL;
7044                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7045
7046                 if (old->release_fb) {
7047                         drm_framebuffer_unregister_private(old->release_fb);
7048                         drm_framebuffer_unreference(old->release_fb);
7049                 }
7050
7051                 mutex_unlock(&crtc->mutex);
7052                 return;
7053         }
7054
7055         /* Switch crtc and encoder back off if necessary */
7056         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7057                 connector->funcs->dpms(connector, old->dpms_mode);
7058
7059         mutex_unlock(&crtc->mutex);
7060 }
7061
7062 /* Returns the clock of the currently programmed mode of the given pipe. */
7063 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7064                                 struct intel_crtc_config *pipe_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         int pipe = pipe_config->cpu_transcoder;
7069         u32 dpll = I915_READ(DPLL(pipe));
7070         u32 fp;
7071         intel_clock_t clock;
7072
7073         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7074                 fp = I915_READ(FP0(pipe));
7075         else
7076                 fp = I915_READ(FP1(pipe));
7077
7078         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7079         if (IS_PINEVIEW(dev)) {
7080                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7081                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7082         } else {
7083                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7084                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7085         }
7086
7087         if (!IS_GEN2(dev)) {
7088                 if (IS_PINEVIEW(dev))
7089                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7090                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7091                 else
7092                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7093                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7094
7095                 switch (dpll & DPLL_MODE_MASK) {
7096                 case DPLLB_MODE_DAC_SERIAL:
7097                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7098                                 5 : 10;
7099                         break;
7100                 case DPLLB_MODE_LVDS:
7101                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7102                                 7 : 14;
7103                         break;
7104                 default:
7105                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7106                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7107                         pipe_config->adjusted_mode.clock = 0;
7108                         return;
7109                 }
7110
7111                 if (IS_PINEVIEW(dev))
7112                         pineview_clock(96000, &clock);
7113                 else
7114                         i9xx_clock(96000, &clock);
7115         } else {
7116                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7117
7118                 if (is_lvds) {
7119                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7120                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7121                         clock.p2 = 14;
7122
7123                         if ((dpll & PLL_REF_INPUT_MASK) ==
7124                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7125                                 /* XXX: might not be 66MHz */
7126                                 i9xx_clock(66000, &clock);
7127                         } else
7128                                 i9xx_clock(48000, &clock);
7129                 } else {
7130                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7131                                 clock.p1 = 2;
7132                         else {
7133                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7134                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7135                         }
7136                         if (dpll & PLL_P2_DIVIDE_BY_4)
7137                                 clock.p2 = 4;
7138                         else
7139                                 clock.p2 = 2;
7140
7141                         i9xx_clock(48000, &clock);
7142                 }
7143         }
7144
7145         pipe_config->adjusted_mode.clock = clock.dot *
7146                 pipe_config->pixel_multiplier;
7147 }
7148
7149 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7150                                     struct intel_crtc_config *pipe_config)
7151 {
7152         struct drm_device *dev = crtc->base.dev;
7153         struct drm_i915_private *dev_priv = dev->dev_private;
7154         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7155         int link_freq, repeat;
7156         u64 clock;
7157         u32 link_m, link_n;
7158
7159         repeat = pipe_config->pixel_multiplier;
7160
7161         /*
7162          * The calculation for the data clock is:
7163          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7164          * But we want to avoid losing precison if possible, so:
7165          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7166          *
7167          * and the link clock is simpler:
7168          * link_clock = (m * link_clock * repeat) / n
7169          */
7170
7171         /*
7172          * We need to get the FDI or DP link clock here to derive
7173          * the M/N dividers.
7174          *
7175          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7176          * For DP, it's either 1.62GHz or 2.7GHz.
7177          * We do our calculations in 10*MHz since we don't need much precison.
7178          */
7179         if (pipe_config->has_pch_encoder)
7180                 link_freq = intel_fdi_link_freq(dev) * 10000;
7181         else
7182                 link_freq = pipe_config->port_clock;
7183
7184         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7185         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7186
7187         if (!link_m || !link_n)
7188                 return;
7189
7190         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7191         do_div(clock, link_n);
7192
7193         pipe_config->adjusted_mode.clock = clock;
7194 }
7195
7196 /** Returns the currently programmed mode of the given pipe. */
7197 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7198                                              struct drm_crtc *crtc)
7199 {
7200         struct drm_i915_private *dev_priv = dev->dev_private;
7201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7203         struct drm_display_mode *mode;
7204         struct intel_crtc_config pipe_config;
7205         int htot = I915_READ(HTOTAL(cpu_transcoder));
7206         int hsync = I915_READ(HSYNC(cpu_transcoder));
7207         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7208         int vsync = I915_READ(VSYNC(cpu_transcoder));
7209
7210         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7211         if (!mode)
7212                 return NULL;
7213
7214         /*
7215          * Construct a pipe_config sufficient for getting the clock info
7216          * back out of crtc_clock_get.
7217          *
7218          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7219          * to use a real value here instead.
7220          */
7221         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7222         pipe_config.pixel_multiplier = 1;
7223         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7224
7225         mode->clock = pipe_config.adjusted_mode.clock;
7226         mode->hdisplay = (htot & 0xffff) + 1;
7227         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7228         mode->hsync_start = (hsync & 0xffff) + 1;
7229         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7230         mode->vdisplay = (vtot & 0xffff) + 1;
7231         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7232         mode->vsync_start = (vsync & 0xffff) + 1;
7233         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7234
7235         drm_mode_set_name(mode);
7236
7237         return mode;
7238 }
7239
7240 static void intel_increase_pllclock(struct drm_crtc *crtc)
7241 {
7242         struct drm_device *dev = crtc->dev;
7243         drm_i915_private_t *dev_priv = dev->dev_private;
7244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245         int pipe = intel_crtc->pipe;
7246         int dpll_reg = DPLL(pipe);
7247         int dpll;
7248
7249         if (HAS_PCH_SPLIT(dev))
7250                 return;
7251
7252         if (!dev_priv->lvds_downclock_avail)
7253                 return;
7254
7255         dpll = I915_READ(dpll_reg);
7256         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7257                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7258
7259                 assert_panel_unlocked(dev_priv, pipe);
7260
7261                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7262                 I915_WRITE(dpll_reg, dpll);
7263                 intel_wait_for_vblank(dev, pipe);
7264
7265                 dpll = I915_READ(dpll_reg);
7266                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7267                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7268         }
7269 }
7270
7271 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7272 {
7273         struct drm_device *dev = crtc->dev;
7274         drm_i915_private_t *dev_priv = dev->dev_private;
7275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7276
7277         if (HAS_PCH_SPLIT(dev))
7278                 return;
7279
7280         if (!dev_priv->lvds_downclock_avail)
7281                 return;
7282
7283         /*
7284          * Since this is called by a timer, we should never get here in
7285          * the manual case.
7286          */
7287         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7288                 int pipe = intel_crtc->pipe;
7289                 int dpll_reg = DPLL(pipe);
7290                 int dpll;
7291
7292                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7293
7294                 assert_panel_unlocked(dev_priv, pipe);
7295
7296                 dpll = I915_READ(dpll_reg);
7297                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7298                 I915_WRITE(dpll_reg, dpll);
7299                 intel_wait_for_vblank(dev, pipe);
7300                 dpll = I915_READ(dpll_reg);
7301                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7302                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7303         }
7304
7305 }
7306
7307 void intel_mark_busy(struct drm_device *dev)
7308 {
7309         i915_update_gfx_val(dev->dev_private);
7310 }
7311
7312 void intel_mark_idle(struct drm_device *dev)
7313 {
7314         struct drm_crtc *crtc;
7315
7316         if (!i915_powersave)
7317                 return;
7318
7319         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7320                 if (!crtc->fb)
7321                         continue;
7322
7323                 intel_decrease_pllclock(crtc);
7324         }
7325 }
7326
7327 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7328                         struct intel_ring_buffer *ring)
7329 {
7330         struct drm_device *dev = obj->base.dev;
7331         struct drm_crtc *crtc;
7332
7333         if (!i915_powersave)
7334                 return;
7335
7336         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7337                 if (!crtc->fb)
7338                         continue;
7339
7340                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7341                         continue;
7342
7343                 intel_increase_pllclock(crtc);
7344                 if (ring && intel_fbc_enabled(dev))
7345                         ring->fbc_dirty = true;
7346         }
7347 }
7348
7349 static void intel_crtc_destroy(struct drm_crtc *crtc)
7350 {
7351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7352         struct drm_device *dev = crtc->dev;
7353         struct intel_unpin_work *work;
7354         unsigned long flags;
7355
7356         spin_lock_irqsave(&dev->event_lock, flags);
7357         work = intel_crtc->unpin_work;
7358         intel_crtc->unpin_work = NULL;
7359         spin_unlock_irqrestore(&dev->event_lock, flags);
7360
7361         if (work) {
7362                 cancel_work_sync(&work->work);
7363                 kfree(work);
7364         }
7365
7366         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7367
7368         drm_crtc_cleanup(crtc);
7369
7370         kfree(intel_crtc);
7371 }
7372
7373 static void intel_unpin_work_fn(struct work_struct *__work)
7374 {
7375         struct intel_unpin_work *work =
7376                 container_of(__work, struct intel_unpin_work, work);
7377         struct drm_device *dev = work->crtc->dev;
7378
7379         mutex_lock(&dev->struct_mutex);
7380         intel_unpin_fb_obj(work->old_fb_obj);
7381         drm_gem_object_unreference(&work->pending_flip_obj->base);
7382         drm_gem_object_unreference(&work->old_fb_obj->base);
7383
7384         intel_update_fbc(dev);
7385         mutex_unlock(&dev->struct_mutex);
7386
7387         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7388         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7389
7390         kfree(work);
7391 }
7392
7393 static void do_intel_finish_page_flip(struct drm_device *dev,
7394                                       struct drm_crtc *crtc)
7395 {
7396         drm_i915_private_t *dev_priv = dev->dev_private;
7397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398         struct intel_unpin_work *work;
7399         unsigned long flags;
7400
7401         /* Ignore early vblank irqs */
7402         if (intel_crtc == NULL)
7403                 return;
7404
7405         spin_lock_irqsave(&dev->event_lock, flags);
7406         work = intel_crtc->unpin_work;
7407
7408         /* Ensure we don't miss a work->pending update ... */
7409         smp_rmb();
7410
7411         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7412                 spin_unlock_irqrestore(&dev->event_lock, flags);
7413                 return;
7414         }
7415
7416         /* and that the unpin work is consistent wrt ->pending. */
7417         smp_rmb();
7418
7419         intel_crtc->unpin_work = NULL;
7420
7421         if (work->event)
7422                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7423
7424         drm_vblank_put(dev, intel_crtc->pipe);
7425
7426         spin_unlock_irqrestore(&dev->event_lock, flags);
7427
7428         wake_up_all(&dev_priv->pending_flip_queue);
7429
7430         queue_work(dev_priv->wq, &work->work);
7431
7432         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7433 }
7434
7435 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7436 {
7437         drm_i915_private_t *dev_priv = dev->dev_private;
7438         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7439
7440         do_intel_finish_page_flip(dev, crtc);
7441 }
7442
7443 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7444 {
7445         drm_i915_private_t *dev_priv = dev->dev_private;
7446         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7447
7448         do_intel_finish_page_flip(dev, crtc);
7449 }
7450
7451 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7452 {
7453         drm_i915_private_t *dev_priv = dev->dev_private;
7454         struct intel_crtc *intel_crtc =
7455                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7456         unsigned long flags;
7457
7458         /* NB: An MMIO update of the plane base pointer will also
7459          * generate a page-flip completion irq, i.e. every modeset
7460          * is also accompanied by a spurious intel_prepare_page_flip().
7461          */
7462         spin_lock_irqsave(&dev->event_lock, flags);
7463         if (intel_crtc->unpin_work)
7464                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7465         spin_unlock_irqrestore(&dev->event_lock, flags);
7466 }
7467
7468 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7469 {
7470         /* Ensure that the work item is consistent when activating it ... */
7471         smp_wmb();
7472         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7473         /* and that it is marked active as soon as the irq could fire. */
7474         smp_wmb();
7475 }
7476
7477 static int intel_gen2_queue_flip(struct drm_device *dev,
7478                                  struct drm_crtc *crtc,
7479                                  struct drm_framebuffer *fb,
7480                                  struct drm_i915_gem_object *obj)
7481 {
7482         struct drm_i915_private *dev_priv = dev->dev_private;
7483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7484         u32 flip_mask;
7485         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7486         int ret;
7487
7488         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7489         if (ret)
7490                 goto err;
7491
7492         ret = intel_ring_begin(ring, 6);
7493         if (ret)
7494                 goto err_unpin;
7495
7496         /* Can't queue multiple flips, so wait for the previous
7497          * one to finish before executing the next.
7498          */
7499         if (intel_crtc->plane)
7500                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7501         else
7502                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7503         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7504         intel_ring_emit(ring, MI_NOOP);
7505         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7506                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7507         intel_ring_emit(ring, fb->pitches[0]);
7508         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7509         intel_ring_emit(ring, 0); /* aux display base address, unused */
7510
7511         intel_mark_page_flip_active(intel_crtc);
7512         intel_ring_advance(ring);
7513         return 0;
7514
7515 err_unpin:
7516         intel_unpin_fb_obj(obj);
7517 err:
7518         return ret;
7519 }
7520
7521 static int intel_gen3_queue_flip(struct drm_device *dev,
7522                                  struct drm_crtc *crtc,
7523                                  struct drm_framebuffer *fb,
7524                                  struct drm_i915_gem_object *obj)
7525 {
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7528         u32 flip_mask;
7529         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7530         int ret;
7531
7532         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7533         if (ret)
7534                 goto err;
7535
7536         ret = intel_ring_begin(ring, 6);
7537         if (ret)
7538                 goto err_unpin;
7539
7540         if (intel_crtc->plane)
7541                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7542         else
7543                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7544         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7545         intel_ring_emit(ring, MI_NOOP);
7546         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7547                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7548         intel_ring_emit(ring, fb->pitches[0]);
7549         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7550         intel_ring_emit(ring, MI_NOOP);
7551
7552         intel_mark_page_flip_active(intel_crtc);
7553         intel_ring_advance(ring);
7554         return 0;
7555
7556 err_unpin:
7557         intel_unpin_fb_obj(obj);
7558 err:
7559         return ret;
7560 }
7561
7562 static int intel_gen4_queue_flip(struct drm_device *dev,
7563                                  struct drm_crtc *crtc,
7564                                  struct drm_framebuffer *fb,
7565                                  struct drm_i915_gem_object *obj)
7566 {
7567         struct drm_i915_private *dev_priv = dev->dev_private;
7568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7569         uint32_t pf, pipesrc;
7570         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7571         int ret;
7572
7573         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7574         if (ret)
7575                 goto err;
7576
7577         ret = intel_ring_begin(ring, 4);
7578         if (ret)
7579                 goto err_unpin;
7580
7581         /* i965+ uses the linear or tiled offsets from the
7582          * Display Registers (which do not change across a page-flip)
7583          * so we need only reprogram the base address.
7584          */
7585         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7586                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7587         intel_ring_emit(ring, fb->pitches[0]);
7588         intel_ring_emit(ring,
7589                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7590                         obj->tiling_mode);
7591
7592         /* XXX Enabling the panel-fitter across page-flip is so far
7593          * untested on non-native modes, so ignore it for now.
7594          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7595          */
7596         pf = 0;
7597         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7598         intel_ring_emit(ring, pf | pipesrc);
7599
7600         intel_mark_page_flip_active(intel_crtc);
7601         intel_ring_advance(ring);
7602         return 0;
7603
7604 err_unpin:
7605         intel_unpin_fb_obj(obj);
7606 err:
7607         return ret;
7608 }
7609
7610 static int intel_gen6_queue_flip(struct drm_device *dev,
7611                                  struct drm_crtc *crtc,
7612                                  struct drm_framebuffer *fb,
7613                                  struct drm_i915_gem_object *obj)
7614 {
7615         struct drm_i915_private *dev_priv = dev->dev_private;
7616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7617         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7618         uint32_t pf, pipesrc;
7619         int ret;
7620
7621         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7622         if (ret)
7623                 goto err;
7624
7625         ret = intel_ring_begin(ring, 4);
7626         if (ret)
7627                 goto err_unpin;
7628
7629         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7630                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7631         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7632         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7633
7634         /* Contrary to the suggestions in the documentation,
7635          * "Enable Panel Fitter" does not seem to be required when page
7636          * flipping with a non-native mode, and worse causes a normal
7637          * modeset to fail.
7638          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7639          */
7640         pf = 0;
7641         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7642         intel_ring_emit(ring, pf | pipesrc);
7643
7644         intel_mark_page_flip_active(intel_crtc);
7645         intel_ring_advance(ring);
7646         return 0;
7647
7648 err_unpin:
7649         intel_unpin_fb_obj(obj);
7650 err:
7651         return ret;
7652 }
7653
7654 /*
7655  * On gen7 we currently use the blit ring because (in early silicon at least)
7656  * the render ring doesn't give us interrpts for page flip completion, which
7657  * means clients will hang after the first flip is queued.  Fortunately the
7658  * blit ring generates interrupts properly, so use it instead.
7659  */
7660 static int intel_gen7_queue_flip(struct drm_device *dev,
7661                                  struct drm_crtc *crtc,
7662                                  struct drm_framebuffer *fb,
7663                                  struct drm_i915_gem_object *obj)
7664 {
7665         struct drm_i915_private *dev_priv = dev->dev_private;
7666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7667         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7668         uint32_t plane_bit = 0;
7669         int ret;
7670
7671         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7672         if (ret)
7673                 goto err;
7674
7675         switch(intel_crtc->plane) {
7676         case PLANE_A:
7677                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7678                 break;
7679         case PLANE_B:
7680                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7681                 break;
7682         case PLANE_C:
7683                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7684                 break;
7685         default:
7686                 WARN_ONCE(1, "unknown plane in flip command\n");
7687                 ret = -ENODEV;
7688                 goto err_unpin;
7689         }
7690
7691         ret = intel_ring_begin(ring, 4);
7692         if (ret)
7693                 goto err_unpin;
7694
7695         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7696         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7697         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7698         intel_ring_emit(ring, (MI_NOOP));
7699
7700         intel_mark_page_flip_active(intel_crtc);
7701         intel_ring_advance(ring);
7702         return 0;
7703
7704 err_unpin:
7705         intel_unpin_fb_obj(obj);
7706 err:
7707         return ret;
7708 }
7709
7710 static int intel_default_queue_flip(struct drm_device *dev,
7711                                     struct drm_crtc *crtc,
7712                                     struct drm_framebuffer *fb,
7713                                     struct drm_i915_gem_object *obj)
7714 {
7715         return -ENODEV;
7716 }
7717
7718 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7719                                 struct drm_framebuffer *fb,
7720                                 struct drm_pending_vblank_event *event)
7721 {
7722         struct drm_device *dev = crtc->dev;
7723         struct drm_i915_private *dev_priv = dev->dev_private;
7724         struct drm_framebuffer *old_fb = crtc->fb;
7725         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7727         struct intel_unpin_work *work;
7728         unsigned long flags;
7729         int ret;
7730
7731         /* Can't change pixel format via MI display flips. */
7732         if (fb->pixel_format != crtc->fb->pixel_format)
7733                 return -EINVAL;
7734
7735         /*
7736          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7737          * Note that pitch changes could also affect these register.
7738          */
7739         if (INTEL_INFO(dev)->gen > 3 &&
7740             (fb->offsets[0] != crtc->fb->offsets[0] ||
7741              fb->pitches[0] != crtc->fb->pitches[0]))
7742                 return -EINVAL;
7743
7744         work = kzalloc(sizeof *work, GFP_KERNEL);
7745         if (work == NULL)
7746                 return -ENOMEM;
7747
7748         work->event = event;
7749         work->crtc = crtc;
7750         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7751         INIT_WORK(&work->work, intel_unpin_work_fn);
7752
7753         ret = drm_vblank_get(dev, intel_crtc->pipe);
7754         if (ret)
7755                 goto free_work;
7756
7757         /* We borrow the event spin lock for protecting unpin_work */
7758         spin_lock_irqsave(&dev->event_lock, flags);
7759         if (intel_crtc->unpin_work) {
7760                 spin_unlock_irqrestore(&dev->event_lock, flags);
7761                 kfree(work);
7762                 drm_vblank_put(dev, intel_crtc->pipe);
7763
7764                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7765                 return -EBUSY;
7766         }
7767         intel_crtc->unpin_work = work;
7768         spin_unlock_irqrestore(&dev->event_lock, flags);
7769
7770         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7771                 flush_workqueue(dev_priv->wq);
7772
7773         ret = i915_mutex_lock_interruptible(dev);
7774         if (ret)
7775                 goto cleanup;
7776
7777         /* Reference the objects for the scheduled work. */
7778         drm_gem_object_reference(&work->old_fb_obj->base);
7779         drm_gem_object_reference(&obj->base);
7780
7781         crtc->fb = fb;
7782
7783         work->pending_flip_obj = obj;
7784
7785         work->enable_stall_check = true;
7786
7787         atomic_inc(&intel_crtc->unpin_work_count);
7788         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7789
7790         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7791         if (ret)
7792                 goto cleanup_pending;
7793
7794         intel_disable_fbc(dev);
7795         intel_mark_fb_busy(obj, NULL);
7796         mutex_unlock(&dev->struct_mutex);
7797
7798         trace_i915_flip_request(intel_crtc->plane, obj);
7799
7800         return 0;
7801
7802 cleanup_pending:
7803         atomic_dec(&intel_crtc->unpin_work_count);
7804         crtc->fb = old_fb;
7805         drm_gem_object_unreference(&work->old_fb_obj->base);
7806         drm_gem_object_unreference(&obj->base);
7807         mutex_unlock(&dev->struct_mutex);
7808
7809 cleanup:
7810         spin_lock_irqsave(&dev->event_lock, flags);
7811         intel_crtc->unpin_work = NULL;
7812         spin_unlock_irqrestore(&dev->event_lock, flags);
7813
7814         drm_vblank_put(dev, intel_crtc->pipe);
7815 free_work:
7816         kfree(work);
7817
7818         return ret;
7819 }
7820
7821 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7822         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7823         .load_lut = intel_crtc_load_lut,
7824 };
7825
7826 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7827                                   struct drm_crtc *crtc)
7828 {
7829         struct drm_device *dev;
7830         struct drm_crtc *tmp;
7831         int crtc_mask = 1;
7832
7833         WARN(!crtc, "checking null crtc?\n");
7834
7835         dev = crtc->dev;
7836
7837         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7838                 if (tmp == crtc)
7839                         break;
7840                 crtc_mask <<= 1;
7841         }
7842
7843         if (encoder->possible_crtcs & crtc_mask)
7844                 return true;
7845         return false;
7846 }
7847
7848 /**
7849  * intel_modeset_update_staged_output_state
7850  *
7851  * Updates the staged output configuration state, e.g. after we've read out the
7852  * current hw state.
7853  */
7854 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7855 {
7856         struct intel_encoder *encoder;
7857         struct intel_connector *connector;
7858
7859         list_for_each_entry(connector, &dev->mode_config.connector_list,
7860                             base.head) {
7861                 connector->new_encoder =
7862                         to_intel_encoder(connector->base.encoder);
7863         }
7864
7865         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7866                             base.head) {
7867                 encoder->new_crtc =
7868                         to_intel_crtc(encoder->base.crtc);
7869         }
7870 }
7871
7872 /**
7873  * intel_modeset_commit_output_state
7874  *
7875  * This function copies the stage display pipe configuration to the real one.
7876  */
7877 static void intel_modeset_commit_output_state(struct drm_device *dev)
7878 {
7879         struct intel_encoder *encoder;
7880         struct intel_connector *connector;
7881
7882         list_for_each_entry(connector, &dev->mode_config.connector_list,
7883                             base.head) {
7884                 connector->base.encoder = &connector->new_encoder->base;
7885         }
7886
7887         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7888                             base.head) {
7889                 encoder->base.crtc = &encoder->new_crtc->base;
7890         }
7891 }
7892
7893 static void
7894 connected_sink_compute_bpp(struct intel_connector * connector,
7895                            struct intel_crtc_config *pipe_config)
7896 {
7897         int bpp = pipe_config->pipe_bpp;
7898
7899         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7900                 connector->base.base.id,
7901                 drm_get_connector_name(&connector->base));
7902
7903         /* Don't use an invalid EDID bpc value */
7904         if (connector->base.display_info.bpc &&
7905             connector->base.display_info.bpc * 3 < bpp) {
7906                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7907                               bpp, connector->base.display_info.bpc*3);
7908                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7909         }
7910
7911         /* Clamp bpp to 8 on screens without EDID 1.4 */
7912         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7913                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7914                               bpp);
7915                 pipe_config->pipe_bpp = 24;
7916         }
7917 }
7918
7919 static int
7920 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7921                           struct drm_framebuffer *fb,
7922                           struct intel_crtc_config *pipe_config)
7923 {
7924         struct drm_device *dev = crtc->base.dev;
7925         struct intel_connector *connector;
7926         int bpp;
7927
7928         switch (fb->pixel_format) {
7929         case DRM_FORMAT_C8:
7930                 bpp = 8*3; /* since we go through a colormap */
7931                 break;
7932         case DRM_FORMAT_XRGB1555:
7933         case DRM_FORMAT_ARGB1555:
7934                 /* checked in intel_framebuffer_init already */
7935                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7936                         return -EINVAL;
7937         case DRM_FORMAT_RGB565:
7938                 bpp = 6*3; /* min is 18bpp */
7939                 break;
7940         case DRM_FORMAT_XBGR8888:
7941         case DRM_FORMAT_ABGR8888:
7942                 /* checked in intel_framebuffer_init already */
7943                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7944                         return -EINVAL;
7945         case DRM_FORMAT_XRGB8888:
7946         case DRM_FORMAT_ARGB8888:
7947                 bpp = 8*3;
7948                 break;
7949         case DRM_FORMAT_XRGB2101010:
7950         case DRM_FORMAT_ARGB2101010:
7951         case DRM_FORMAT_XBGR2101010:
7952         case DRM_FORMAT_ABGR2101010:
7953                 /* checked in intel_framebuffer_init already */
7954                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7955                         return -EINVAL;
7956                 bpp = 10*3;
7957                 break;
7958         /* TODO: gen4+ supports 16 bpc floating point, too. */
7959         default:
7960                 DRM_DEBUG_KMS("unsupported depth\n");
7961                 return -EINVAL;
7962         }
7963
7964         pipe_config->pipe_bpp = bpp;
7965
7966         /* Clamp display bpp to EDID value */
7967         list_for_each_entry(connector, &dev->mode_config.connector_list,
7968                             base.head) {
7969                 if (!connector->new_encoder ||
7970                     connector->new_encoder->new_crtc != crtc)
7971                         continue;
7972
7973                 connected_sink_compute_bpp(connector, pipe_config);
7974         }
7975
7976         return bpp;
7977 }
7978
7979 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7980                                    struct intel_crtc_config *pipe_config,
7981                                    const char *context)
7982 {
7983         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7984                       context, pipe_name(crtc->pipe));
7985
7986         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7987         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7988                       pipe_config->pipe_bpp, pipe_config->dither);
7989         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7990                       pipe_config->has_pch_encoder,
7991                       pipe_config->fdi_lanes,
7992                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7993                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7994                       pipe_config->fdi_m_n.tu);
7995         DRM_DEBUG_KMS("requested mode:\n");
7996         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7997         DRM_DEBUG_KMS("adjusted mode:\n");
7998         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7999         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8000                       pipe_config->gmch_pfit.control,
8001                       pipe_config->gmch_pfit.pgm_ratios,
8002                       pipe_config->gmch_pfit.lvds_border_bits);
8003         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8004                       pipe_config->pch_pfit.pos,
8005                       pipe_config->pch_pfit.size);
8006         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8007 }
8008
8009 static bool check_encoder_cloning(struct drm_crtc *crtc)
8010 {
8011         int num_encoders = 0;
8012         bool uncloneable_encoders = false;
8013         struct intel_encoder *encoder;
8014
8015         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8016                             base.head) {
8017                 if (&encoder->new_crtc->base != crtc)
8018                         continue;
8019
8020                 num_encoders++;
8021                 if (!encoder->cloneable)
8022                         uncloneable_encoders = true;
8023         }
8024
8025         return !(num_encoders > 1 && uncloneable_encoders);
8026 }
8027
8028 static struct intel_crtc_config *
8029 intel_modeset_pipe_config(struct drm_crtc *crtc,
8030                           struct drm_framebuffer *fb,
8031                           struct drm_display_mode *mode)
8032 {
8033         struct drm_device *dev = crtc->dev;
8034         struct intel_encoder *encoder;
8035         struct intel_crtc_config *pipe_config;
8036         int plane_bpp, ret = -EINVAL;
8037         bool retry = true;
8038
8039         if (!check_encoder_cloning(crtc)) {
8040                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8041                 return ERR_PTR(-EINVAL);
8042         }
8043
8044         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8045         if (!pipe_config)
8046                 return ERR_PTR(-ENOMEM);
8047
8048         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8049         drm_mode_copy(&pipe_config->requested_mode, mode);
8050         pipe_config->cpu_transcoder =
8051                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8052         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8053
8054         /*
8055          * Sanitize sync polarity flags based on requested ones. If neither
8056          * positive or negative polarity is requested, treat this as meaning
8057          * negative polarity.
8058          */
8059         if (!(pipe_config->adjusted_mode.flags &
8060               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8061                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8062
8063         if (!(pipe_config->adjusted_mode.flags &
8064               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8065                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8066
8067         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8068          * plane pixel format and any sink constraints into account. Returns the
8069          * source plane bpp so that dithering can be selected on mismatches
8070          * after encoders and crtc also have had their say. */
8071         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8072                                               fb, pipe_config);
8073         if (plane_bpp < 0)
8074                 goto fail;
8075
8076 encoder_retry:
8077         /* Ensure the port clock defaults are reset when retrying. */
8078         pipe_config->port_clock = 0;
8079         pipe_config->pixel_multiplier = 1;
8080
8081         /* Fill in default crtc timings, allow encoders to overwrite them. */
8082         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8083
8084         /* Pass our mode to the connectors and the CRTC to give them a chance to
8085          * adjust it according to limitations or connector properties, and also
8086          * a chance to reject the mode entirely.
8087          */
8088         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8089                             base.head) {
8090
8091                 if (&encoder->new_crtc->base != crtc)
8092                         continue;
8093
8094                 if (!(encoder->compute_config(encoder, pipe_config))) {
8095                         DRM_DEBUG_KMS("Encoder config failure\n");
8096                         goto fail;
8097                 }
8098         }
8099
8100         /* Set default port clock if not overwritten by the encoder. Needs to be
8101          * done afterwards in case the encoder adjusts the mode. */
8102         if (!pipe_config->port_clock)
8103                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8104
8105         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8106         if (ret < 0) {
8107                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8108                 goto fail;
8109         }
8110
8111         if (ret == RETRY) {
8112                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8113                         ret = -EINVAL;
8114                         goto fail;
8115                 }
8116
8117                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8118                 retry = false;
8119                 goto encoder_retry;
8120         }
8121
8122         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8123         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8124                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8125
8126         return pipe_config;
8127 fail:
8128         kfree(pipe_config);
8129         return ERR_PTR(ret);
8130 }
8131
8132 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8133  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8134 static void
8135 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8136                              unsigned *prepare_pipes, unsigned *disable_pipes)
8137 {
8138         struct intel_crtc *intel_crtc;
8139         struct drm_device *dev = crtc->dev;
8140         struct intel_encoder *encoder;
8141         struct intel_connector *connector;
8142         struct drm_crtc *tmp_crtc;
8143
8144         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8145
8146         /* Check which crtcs have changed outputs connected to them, these need
8147          * to be part of the prepare_pipes mask. We don't (yet) support global
8148          * modeset across multiple crtcs, so modeset_pipes will only have one
8149          * bit set at most. */
8150         list_for_each_entry(connector, &dev->mode_config.connector_list,
8151                             base.head) {
8152                 if (connector->base.encoder == &connector->new_encoder->base)
8153                         continue;
8154
8155                 if (connector->base.encoder) {
8156                         tmp_crtc = connector->base.encoder->crtc;
8157
8158                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8159                 }
8160
8161                 if (connector->new_encoder)
8162                         *prepare_pipes |=
8163                                 1 << connector->new_encoder->new_crtc->pipe;
8164         }
8165
8166         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8167                             base.head) {
8168                 if (encoder->base.crtc == &encoder->new_crtc->base)
8169                         continue;
8170
8171                 if (encoder->base.crtc) {
8172                         tmp_crtc = encoder->base.crtc;
8173
8174                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8175                 }
8176
8177                 if (encoder->new_crtc)
8178                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8179         }
8180
8181         /* Check for any pipes that will be fully disabled ... */
8182         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8183                             base.head) {
8184                 bool used = false;
8185
8186                 /* Don't try to disable disabled crtcs. */
8187                 if (!intel_crtc->base.enabled)
8188                         continue;
8189
8190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8191                                     base.head) {
8192                         if (encoder->new_crtc == intel_crtc)
8193                                 used = true;
8194                 }
8195
8196                 if (!used)
8197                         *disable_pipes |= 1 << intel_crtc->pipe;
8198         }
8199
8200
8201         /* set_mode is also used to update properties on life display pipes. */
8202         intel_crtc = to_intel_crtc(crtc);
8203         if (crtc->enabled)
8204                 *prepare_pipes |= 1 << intel_crtc->pipe;
8205
8206         /*
8207          * For simplicity do a full modeset on any pipe where the output routing
8208          * changed. We could be more clever, but that would require us to be
8209          * more careful with calling the relevant encoder->mode_set functions.
8210          */
8211         if (*prepare_pipes)
8212                 *modeset_pipes = *prepare_pipes;
8213
8214         /* ... and mask these out. */
8215         *modeset_pipes &= ~(*disable_pipes);
8216         *prepare_pipes &= ~(*disable_pipes);
8217
8218         /*
8219          * HACK: We don't (yet) fully support global modesets. intel_set_config
8220          * obies this rule, but the modeset restore mode of
8221          * intel_modeset_setup_hw_state does not.
8222          */
8223         *modeset_pipes &= 1 << intel_crtc->pipe;
8224         *prepare_pipes &= 1 << intel_crtc->pipe;
8225
8226         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8227                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8228 }
8229
8230 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8231 {
8232         struct drm_encoder *encoder;
8233         struct drm_device *dev = crtc->dev;
8234
8235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8236                 if (encoder->crtc == crtc)
8237                         return true;
8238
8239         return false;
8240 }
8241
8242 static void
8243 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8244 {
8245         struct intel_encoder *intel_encoder;
8246         struct intel_crtc *intel_crtc;
8247         struct drm_connector *connector;
8248
8249         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8250                             base.head) {
8251                 if (!intel_encoder->base.crtc)
8252                         continue;
8253
8254                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8255
8256                 if (prepare_pipes & (1 << intel_crtc->pipe))
8257                         intel_encoder->connectors_active = false;
8258         }
8259
8260         intel_modeset_commit_output_state(dev);
8261
8262         /* Update computed state. */
8263         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8264                             base.head) {
8265                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8266         }
8267
8268         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8269                 if (!connector->encoder || !connector->encoder->crtc)
8270                         continue;
8271
8272                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8273
8274                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8275                         struct drm_property *dpms_property =
8276                                 dev->mode_config.dpms_property;
8277
8278                         connector->dpms = DRM_MODE_DPMS_ON;
8279                         drm_object_property_set_value(&connector->base,
8280                                                          dpms_property,
8281                                                          DRM_MODE_DPMS_ON);
8282
8283                         intel_encoder = to_intel_encoder(connector->encoder);
8284                         intel_encoder->connectors_active = true;
8285                 }
8286         }
8287
8288 }
8289
8290 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8291                                     struct intel_crtc_config *new)
8292 {
8293         int clock1, clock2, diff;
8294
8295         clock1 = cur->adjusted_mode.clock;
8296         clock2 = new->adjusted_mode.clock;
8297
8298         if (clock1 == clock2)
8299                 return true;
8300
8301         if (!clock1 || !clock2)
8302                 return false;
8303
8304         diff = abs(clock1 - clock2);
8305
8306         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8307                 return true;
8308
8309         return false;
8310 }
8311
8312 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8313         list_for_each_entry((intel_crtc), \
8314                             &(dev)->mode_config.crtc_list, \
8315                             base.head) \
8316                 if (mask & (1 <<(intel_crtc)->pipe))
8317
8318 static bool
8319 intel_pipe_config_compare(struct drm_device *dev,
8320                           struct intel_crtc_config *current_config,
8321                           struct intel_crtc_config *pipe_config)
8322 {
8323 #define PIPE_CONF_CHECK_X(name) \
8324         if (current_config->name != pipe_config->name) { \
8325                 DRM_ERROR("mismatch in " #name " " \
8326                           "(expected 0x%08x, found 0x%08x)\n", \
8327                           current_config->name, \
8328                           pipe_config->name); \
8329                 return false; \
8330         }
8331
8332 #define PIPE_CONF_CHECK_I(name) \
8333         if (current_config->name != pipe_config->name) { \
8334                 DRM_ERROR("mismatch in " #name " " \
8335                           "(expected %i, found %i)\n", \
8336                           current_config->name, \
8337                           pipe_config->name); \
8338                 return false; \
8339         }
8340
8341 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8342         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8343                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8344                           "(expected %i, found %i)\n", \
8345                           current_config->name & (mask), \
8346                           pipe_config->name & (mask)); \
8347                 return false; \
8348         }
8349
8350 #define PIPE_CONF_QUIRK(quirk)  \
8351         ((current_config->quirks | pipe_config->quirks) & (quirk))
8352
8353         PIPE_CONF_CHECK_I(cpu_transcoder);
8354
8355         PIPE_CONF_CHECK_I(has_pch_encoder);
8356         PIPE_CONF_CHECK_I(fdi_lanes);
8357         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8358         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8359         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8360         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8361         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8362
8363         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8364         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8365         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8366         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8367         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8368         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8369
8370         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8371         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8372         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8373         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8375         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8376
8377         PIPE_CONF_CHECK_I(pixel_multiplier);
8378
8379         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8380                               DRM_MODE_FLAG_INTERLACE);
8381
8382         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8383                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8384                                       DRM_MODE_FLAG_PHSYNC);
8385                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8386                                       DRM_MODE_FLAG_NHSYNC);
8387                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8388                                       DRM_MODE_FLAG_PVSYNC);
8389                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390                                       DRM_MODE_FLAG_NVSYNC);
8391         }
8392
8393         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8394         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8395
8396         PIPE_CONF_CHECK_I(gmch_pfit.control);
8397         /* pfit ratios are autocomputed by the hw on gen4+ */
8398         if (INTEL_INFO(dev)->gen < 4)
8399                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8400         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8401         PIPE_CONF_CHECK_I(pch_pfit.pos);
8402         PIPE_CONF_CHECK_I(pch_pfit.size);
8403
8404         PIPE_CONF_CHECK_I(ips_enabled);
8405
8406         PIPE_CONF_CHECK_I(shared_dpll);
8407         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8408         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8409         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8410         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8411
8412 #undef PIPE_CONF_CHECK_X
8413 #undef PIPE_CONF_CHECK_I
8414 #undef PIPE_CONF_CHECK_FLAGS
8415 #undef PIPE_CONF_QUIRK
8416
8417         if (!IS_HASWELL(dev)) {
8418                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8419                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8420                                   current_config->adjusted_mode.clock,
8421                                   pipe_config->adjusted_mode.clock);
8422                         return false;
8423                 }
8424         }
8425
8426         return true;
8427 }
8428
8429 static void
8430 check_connector_state(struct drm_device *dev)
8431 {
8432         struct intel_connector *connector;
8433
8434         list_for_each_entry(connector, &dev->mode_config.connector_list,
8435                             base.head) {
8436                 /* This also checks the encoder/connector hw state with the
8437                  * ->get_hw_state callbacks. */
8438                 intel_connector_check_state(connector);
8439
8440                 WARN(&connector->new_encoder->base != connector->base.encoder,
8441                      "connector's staged encoder doesn't match current encoder\n");
8442         }
8443 }
8444
8445 static void
8446 check_encoder_state(struct drm_device *dev)
8447 {
8448         struct intel_encoder *encoder;
8449         struct intel_connector *connector;
8450
8451         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8452                             base.head) {
8453                 bool enabled = false;
8454                 bool active = false;
8455                 enum pipe pipe, tracked_pipe;
8456
8457                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8458                               encoder->base.base.id,
8459                               drm_get_encoder_name(&encoder->base));
8460
8461                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8462                      "encoder's stage crtc doesn't match current crtc\n");
8463                 WARN(encoder->connectors_active && !encoder->base.crtc,
8464                      "encoder's active_connectors set, but no crtc\n");
8465
8466                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8467                                     base.head) {
8468                         if (connector->base.encoder != &encoder->base)
8469                                 continue;
8470                         enabled = true;
8471                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8472                                 active = true;
8473                 }
8474                 WARN(!!encoder->base.crtc != enabled,
8475                      "encoder's enabled state mismatch "
8476                      "(expected %i, found %i)\n",
8477                      !!encoder->base.crtc, enabled);
8478                 WARN(active && !encoder->base.crtc,
8479                      "active encoder with no crtc\n");
8480
8481                 WARN(encoder->connectors_active != active,
8482                      "encoder's computed active state doesn't match tracked active state "
8483                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8484
8485                 active = encoder->get_hw_state(encoder, &pipe);
8486                 WARN(active != encoder->connectors_active,
8487                      "encoder's hw state doesn't match sw tracking "
8488                      "(expected %i, found %i)\n",
8489                      encoder->connectors_active, active);
8490
8491                 if (!encoder->base.crtc)
8492                         continue;
8493
8494                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8495                 WARN(active && pipe != tracked_pipe,
8496                      "active encoder's pipe doesn't match"
8497                      "(expected %i, found %i)\n",
8498                      tracked_pipe, pipe);
8499
8500         }
8501 }
8502
8503 static void
8504 check_crtc_state(struct drm_device *dev)
8505 {
8506         drm_i915_private_t *dev_priv = dev->dev_private;
8507         struct intel_crtc *crtc;
8508         struct intel_encoder *encoder;
8509         struct intel_crtc_config pipe_config;
8510
8511         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8512                             base.head) {
8513                 bool enabled = false;
8514                 bool active = false;
8515
8516                 memset(&pipe_config, 0, sizeof(pipe_config));
8517
8518                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8519                               crtc->base.base.id);
8520
8521                 WARN(crtc->active && !crtc->base.enabled,
8522                      "active crtc, but not enabled in sw tracking\n");
8523
8524                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8525                                     base.head) {
8526                         if (encoder->base.crtc != &crtc->base)
8527                                 continue;
8528                         enabled = true;
8529                         if (encoder->connectors_active)
8530                                 active = true;
8531                 }
8532
8533                 WARN(active != crtc->active,
8534                      "crtc's computed active state doesn't match tracked active state "
8535                      "(expected %i, found %i)\n", active, crtc->active);
8536                 WARN(enabled != crtc->base.enabled,
8537                      "crtc's computed enabled state doesn't match tracked enabled state "
8538                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8539
8540                 active = dev_priv->display.get_pipe_config(crtc,
8541                                                            &pipe_config);
8542
8543                 /* hw state is inconsistent with the pipe A quirk */
8544                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8545                         active = crtc->active;
8546
8547                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8548                                     base.head) {
8549                         if (encoder->base.crtc != &crtc->base)
8550                                 continue;
8551                         if (encoder->get_config)
8552                                 encoder->get_config(encoder, &pipe_config);
8553                 }
8554
8555                 if (dev_priv->display.get_clock)
8556                         dev_priv->display.get_clock(crtc, &pipe_config);
8557
8558                 WARN(crtc->active != active,
8559                      "crtc active state doesn't match with hw state "
8560                      "(expected %i, found %i)\n", crtc->active, active);
8561
8562                 if (active &&
8563                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8564                         WARN(1, "pipe state doesn't match!\n");
8565                         intel_dump_pipe_config(crtc, &pipe_config,
8566                                                "[hw state]");
8567                         intel_dump_pipe_config(crtc, &crtc->config,
8568                                                "[sw state]");
8569                 }
8570         }
8571 }
8572
8573 static void
8574 check_shared_dpll_state(struct drm_device *dev)
8575 {
8576         drm_i915_private_t *dev_priv = dev->dev_private;
8577         struct intel_crtc *crtc;
8578         struct intel_dpll_hw_state dpll_hw_state;
8579         int i;
8580
8581         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8582                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8583                 int enabled_crtcs = 0, active_crtcs = 0;
8584                 bool active;
8585
8586                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8587
8588                 DRM_DEBUG_KMS("%s\n", pll->name);
8589
8590                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8591
8592                 WARN(pll->active > pll->refcount,
8593                      "more active pll users than references: %i vs %i\n",
8594                      pll->active, pll->refcount);
8595                 WARN(pll->active && !pll->on,
8596                      "pll in active use but not on in sw tracking\n");
8597                 WARN(pll->on && !pll->active,
8598                      "pll in on but not on in use in sw tracking\n");
8599                 WARN(pll->on != active,
8600                      "pll on state mismatch (expected %i, found %i)\n",
8601                      pll->on, active);
8602
8603                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8604                                     base.head) {
8605                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8606                                 enabled_crtcs++;
8607                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8608                                 active_crtcs++;
8609                 }
8610                 WARN(pll->active != active_crtcs,
8611                      "pll active crtcs mismatch (expected %i, found %i)\n",
8612                      pll->active, active_crtcs);
8613                 WARN(pll->refcount != enabled_crtcs,
8614                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8615                      pll->refcount, enabled_crtcs);
8616
8617                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8618                                        sizeof(dpll_hw_state)),
8619                      "pll hw state mismatch\n");
8620         }
8621 }
8622
8623 void
8624 intel_modeset_check_state(struct drm_device *dev)
8625 {
8626         check_connector_state(dev);
8627         check_encoder_state(dev);
8628         check_crtc_state(dev);
8629         check_shared_dpll_state(dev);
8630 }
8631
8632 static int __intel_set_mode(struct drm_crtc *crtc,
8633                             struct drm_display_mode *mode,
8634                             int x, int y, struct drm_framebuffer *fb)
8635 {
8636         struct drm_device *dev = crtc->dev;
8637         drm_i915_private_t *dev_priv = dev->dev_private;
8638         struct drm_display_mode *saved_mode, *saved_hwmode;
8639         struct intel_crtc_config *pipe_config = NULL;
8640         struct intel_crtc *intel_crtc;
8641         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8642         int ret = 0;
8643
8644         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8645         if (!saved_mode)
8646                 return -ENOMEM;
8647         saved_hwmode = saved_mode + 1;
8648
8649         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8650                                      &prepare_pipes, &disable_pipes);
8651
8652         *saved_hwmode = crtc->hwmode;
8653         *saved_mode = crtc->mode;
8654
8655         /* Hack: Because we don't (yet) support global modeset on multiple
8656          * crtcs, we don't keep track of the new mode for more than one crtc.
8657          * Hence simply check whether any bit is set in modeset_pipes in all the
8658          * pieces of code that are not yet converted to deal with mutliple crtcs
8659          * changing their mode at the same time. */
8660         if (modeset_pipes) {
8661                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8662                 if (IS_ERR(pipe_config)) {
8663                         ret = PTR_ERR(pipe_config);
8664                         pipe_config = NULL;
8665
8666                         goto out;
8667                 }
8668                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8669                                        "[modeset]");
8670         }
8671
8672         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8673                 intel_crtc_disable(&intel_crtc->base);
8674
8675         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8676                 if (intel_crtc->base.enabled)
8677                         dev_priv->display.crtc_disable(&intel_crtc->base);
8678         }
8679
8680         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8681          * to set it here already despite that we pass it down the callchain.
8682          */
8683         if (modeset_pipes) {
8684                 crtc->mode = *mode;
8685                 /* mode_set/enable/disable functions rely on a correct pipe
8686                  * config. */
8687                 to_intel_crtc(crtc)->config = *pipe_config;
8688         }
8689
8690         /* Only after disabling all output pipelines that will be changed can we
8691          * update the the output configuration. */
8692         intel_modeset_update_state(dev, prepare_pipes);
8693
8694         if (dev_priv->display.modeset_global_resources)
8695                 dev_priv->display.modeset_global_resources(dev);
8696
8697         /* Set up the DPLL and any encoders state that needs to adjust or depend
8698          * on the DPLL.
8699          */
8700         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8701                 ret = intel_crtc_mode_set(&intel_crtc->base,
8702                                           x, y, fb);
8703                 if (ret)
8704                         goto done;
8705         }
8706
8707         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8708         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8709                 dev_priv->display.crtc_enable(&intel_crtc->base);
8710
8711         if (modeset_pipes) {
8712                 /* Store real post-adjustment hardware mode. */
8713                 crtc->hwmode = pipe_config->adjusted_mode;
8714
8715                 /* Calculate and store various constants which
8716                  * are later needed by vblank and swap-completion
8717                  * timestamping. They are derived from true hwmode.
8718                  */
8719                 drm_calc_timestamping_constants(crtc);
8720         }
8721
8722         /* FIXME: add subpixel order */
8723 done:
8724         if (ret && crtc->enabled) {
8725                 crtc->hwmode = *saved_hwmode;
8726                 crtc->mode = *saved_mode;
8727         }
8728
8729 out:
8730         kfree(pipe_config);
8731         kfree(saved_mode);
8732         return ret;
8733 }
8734
8735 int intel_set_mode(struct drm_crtc *crtc,
8736                      struct drm_display_mode *mode,
8737                      int x, int y, struct drm_framebuffer *fb)
8738 {
8739         int ret;
8740
8741         ret = __intel_set_mode(crtc, mode, x, y, fb);
8742
8743         if (ret == 0)
8744                 intel_modeset_check_state(crtc->dev);
8745
8746         return ret;
8747 }
8748
8749 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8750 {
8751         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8752 }
8753
8754 #undef for_each_intel_crtc_masked
8755
8756 static void intel_set_config_free(struct intel_set_config *config)
8757 {
8758         if (!config)
8759                 return;
8760
8761         kfree(config->save_connector_encoders);
8762         kfree(config->save_encoder_crtcs);
8763         kfree(config);
8764 }
8765
8766 static int intel_set_config_save_state(struct drm_device *dev,
8767                                        struct intel_set_config *config)
8768 {
8769         struct drm_encoder *encoder;
8770         struct drm_connector *connector;
8771         int count;
8772
8773         config->save_encoder_crtcs =
8774                 kcalloc(dev->mode_config.num_encoder,
8775                         sizeof(struct drm_crtc *), GFP_KERNEL);
8776         if (!config->save_encoder_crtcs)
8777                 return -ENOMEM;
8778
8779         config->save_connector_encoders =
8780                 kcalloc(dev->mode_config.num_connector,
8781                         sizeof(struct drm_encoder *), GFP_KERNEL);
8782         if (!config->save_connector_encoders)
8783                 return -ENOMEM;
8784
8785         /* Copy data. Note that driver private data is not affected.
8786          * Should anything bad happen only the expected state is
8787          * restored, not the drivers personal bookkeeping.
8788          */
8789         count = 0;
8790         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8791                 config->save_encoder_crtcs[count++] = encoder->crtc;
8792         }
8793
8794         count = 0;
8795         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8796                 config->save_connector_encoders[count++] = connector->encoder;
8797         }
8798
8799         return 0;
8800 }
8801
8802 static void intel_set_config_restore_state(struct drm_device *dev,
8803                                            struct intel_set_config *config)
8804 {
8805         struct intel_encoder *encoder;
8806         struct intel_connector *connector;
8807         int count;
8808
8809         count = 0;
8810         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8811                 encoder->new_crtc =
8812                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8813         }
8814
8815         count = 0;
8816         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8817                 connector->new_encoder =
8818                         to_intel_encoder(config->save_connector_encoders[count++]);
8819         }
8820 }
8821
8822 static bool
8823 is_crtc_connector_off(struct drm_mode_set *set)
8824 {
8825         int i;
8826
8827         if (set->num_connectors == 0)
8828                 return false;
8829
8830         if (WARN_ON(set->connectors == NULL))
8831                 return false;
8832
8833         for (i = 0; i < set->num_connectors; i++)
8834                 if (set->connectors[i]->encoder &&
8835                     set->connectors[i]->encoder->crtc == set->crtc &&
8836                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8837                         return true;
8838
8839         return false;
8840 }
8841
8842 static void
8843 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8844                                       struct intel_set_config *config)
8845 {
8846
8847         /* We should be able to check here if the fb has the same properties
8848          * and then just flip_or_move it */
8849         if (is_crtc_connector_off(set)) {
8850                 config->mode_changed = true;
8851         } else if (set->crtc->fb != set->fb) {
8852                 /* If we have no fb then treat it as a full mode set */
8853                 if (set->crtc->fb == NULL) {
8854                         struct intel_crtc *intel_crtc =
8855                                 to_intel_crtc(set->crtc);
8856
8857                         if (intel_crtc->active && i915_fastboot) {
8858                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8859                                 config->fb_changed = true;
8860                         } else {
8861                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8862                                 config->mode_changed = true;
8863                         }
8864                 } else if (set->fb == NULL) {
8865                         config->mode_changed = true;
8866                 } else if (set->fb->pixel_format !=
8867                            set->crtc->fb->pixel_format) {
8868                         config->mode_changed = true;
8869                 } else {
8870                         config->fb_changed = true;
8871                 }
8872         }
8873
8874         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8875                 config->fb_changed = true;
8876
8877         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8878                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8879                 drm_mode_debug_printmodeline(&set->crtc->mode);
8880                 drm_mode_debug_printmodeline(set->mode);
8881                 config->mode_changed = true;
8882         }
8883 }
8884
8885 static int
8886 intel_modeset_stage_output_state(struct drm_device *dev,
8887                                  struct drm_mode_set *set,
8888                                  struct intel_set_config *config)
8889 {
8890         struct drm_crtc *new_crtc;
8891         struct intel_connector *connector;
8892         struct intel_encoder *encoder;
8893         int count, ro;
8894
8895         /* The upper layers ensure that we either disable a crtc or have a list
8896          * of connectors. For paranoia, double-check this. */
8897         WARN_ON(!set->fb && (set->num_connectors != 0));
8898         WARN_ON(set->fb && (set->num_connectors == 0));
8899
8900         count = 0;
8901         list_for_each_entry(connector, &dev->mode_config.connector_list,
8902                             base.head) {
8903                 /* Otherwise traverse passed in connector list and get encoders
8904                  * for them. */
8905                 for (ro = 0; ro < set->num_connectors; ro++) {
8906                         if (set->connectors[ro] == &connector->base) {
8907                                 connector->new_encoder = connector->encoder;
8908                                 break;
8909                         }
8910                 }
8911
8912                 /* If we disable the crtc, disable all its connectors. Also, if
8913                  * the connector is on the changing crtc but not on the new
8914                  * connector list, disable it. */
8915                 if ((!set->fb || ro == set->num_connectors) &&
8916                     connector->base.encoder &&
8917                     connector->base.encoder->crtc == set->crtc) {
8918                         connector->new_encoder = NULL;
8919
8920                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8921                                 connector->base.base.id,
8922                                 drm_get_connector_name(&connector->base));
8923                 }
8924
8925
8926                 if (&connector->new_encoder->base != connector->base.encoder) {
8927                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8928                         config->mode_changed = true;
8929                 }
8930         }
8931         /* connector->new_encoder is now updated for all connectors. */
8932
8933         /* Update crtc of enabled connectors. */
8934         count = 0;
8935         list_for_each_entry(connector, &dev->mode_config.connector_list,
8936                             base.head) {
8937                 if (!connector->new_encoder)
8938                         continue;
8939
8940                 new_crtc = connector->new_encoder->base.crtc;
8941
8942                 for (ro = 0; ro < set->num_connectors; ro++) {
8943                         if (set->connectors[ro] == &connector->base)
8944                                 new_crtc = set->crtc;
8945                 }
8946
8947                 /* Make sure the new CRTC will work with the encoder */
8948                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8949                                            new_crtc)) {
8950                         return -EINVAL;
8951                 }
8952                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8953
8954                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8955                         connector->base.base.id,
8956                         drm_get_connector_name(&connector->base),
8957                         new_crtc->base.id);
8958         }
8959
8960         /* Check for any encoders that needs to be disabled. */
8961         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8962                             base.head) {
8963                 list_for_each_entry(connector,
8964                                     &dev->mode_config.connector_list,
8965                                     base.head) {
8966                         if (connector->new_encoder == encoder) {
8967                                 WARN_ON(!connector->new_encoder->new_crtc);
8968
8969                                 goto next_encoder;
8970                         }
8971                 }
8972                 encoder->new_crtc = NULL;
8973 next_encoder:
8974                 /* Only now check for crtc changes so we don't miss encoders
8975                  * that will be disabled. */
8976                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8977                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8978                         config->mode_changed = true;
8979                 }
8980         }
8981         /* Now we've also updated encoder->new_crtc for all encoders. */
8982
8983         return 0;
8984 }
8985
8986 static int intel_crtc_set_config(struct drm_mode_set *set)
8987 {
8988         struct drm_device *dev;
8989         struct drm_mode_set save_set;
8990         struct intel_set_config *config;
8991         int ret;
8992
8993         BUG_ON(!set);
8994         BUG_ON(!set->crtc);
8995         BUG_ON(!set->crtc->helper_private);
8996
8997         /* Enforce sane interface api - has been abused by the fb helper. */
8998         BUG_ON(!set->mode && set->fb);
8999         BUG_ON(set->fb && set->num_connectors == 0);
9000
9001         if (set->fb) {
9002                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9003                                 set->crtc->base.id, set->fb->base.id,
9004                                 (int)set->num_connectors, set->x, set->y);
9005         } else {
9006                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9007         }
9008
9009         dev = set->crtc->dev;
9010
9011         ret = -ENOMEM;
9012         config = kzalloc(sizeof(*config), GFP_KERNEL);
9013         if (!config)
9014                 goto out_config;
9015
9016         ret = intel_set_config_save_state(dev, config);
9017         if (ret)
9018                 goto out_config;
9019
9020         save_set.crtc = set->crtc;
9021         save_set.mode = &set->crtc->mode;
9022         save_set.x = set->crtc->x;
9023         save_set.y = set->crtc->y;
9024         save_set.fb = set->crtc->fb;
9025
9026         /* Compute whether we need a full modeset, only an fb base update or no
9027          * change at all. In the future we might also check whether only the
9028          * mode changed, e.g. for LVDS where we only change the panel fitter in
9029          * such cases. */
9030         intel_set_config_compute_mode_changes(set, config);
9031
9032         ret = intel_modeset_stage_output_state(dev, set, config);
9033         if (ret)
9034                 goto fail;
9035
9036         if (config->mode_changed) {
9037                 ret = intel_set_mode(set->crtc, set->mode,
9038                                      set->x, set->y, set->fb);
9039         } else if (config->fb_changed) {
9040                 intel_crtc_wait_for_pending_flips(set->crtc);
9041
9042                 ret = intel_pipe_set_base(set->crtc,
9043                                           set->x, set->y, set->fb);
9044         }
9045
9046         if (ret) {
9047                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9048                               set->crtc->base.id, ret);
9049 fail:
9050                 intel_set_config_restore_state(dev, config);
9051
9052                 /* Try to restore the config */
9053                 if (config->mode_changed &&
9054                     intel_set_mode(save_set.crtc, save_set.mode,
9055                                    save_set.x, save_set.y, save_set.fb))
9056                         DRM_ERROR("failed to restore config after modeset failure\n");
9057         }
9058
9059 out_config:
9060         intel_set_config_free(config);
9061         return ret;
9062 }
9063
9064 static const struct drm_crtc_funcs intel_crtc_funcs = {
9065         .cursor_set = intel_crtc_cursor_set,
9066         .cursor_move = intel_crtc_cursor_move,
9067         .gamma_set = intel_crtc_gamma_set,
9068         .set_config = intel_crtc_set_config,
9069         .destroy = intel_crtc_destroy,
9070         .page_flip = intel_crtc_page_flip,
9071 };
9072
9073 static void intel_cpu_pll_init(struct drm_device *dev)
9074 {
9075         if (HAS_DDI(dev))
9076                 intel_ddi_pll_init(dev);
9077 }
9078
9079 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9080                                       struct intel_shared_dpll *pll,
9081                                       struct intel_dpll_hw_state *hw_state)
9082 {
9083         uint32_t val;
9084
9085         val = I915_READ(PCH_DPLL(pll->id));
9086         hw_state->dpll = val;
9087         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9088         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9089
9090         return val & DPLL_VCO_ENABLE;
9091 }
9092
9093 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9094                                   struct intel_shared_dpll *pll)
9095 {
9096         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9097         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9098 }
9099
9100 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9101                                 struct intel_shared_dpll *pll)
9102 {
9103         /* PCH refclock must be enabled first */
9104         assert_pch_refclk_enabled(dev_priv);
9105
9106         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9107
9108         /* Wait for the clocks to stabilize. */
9109         POSTING_READ(PCH_DPLL(pll->id));
9110         udelay(150);
9111
9112         /* The pixel multiplier can only be updated once the
9113          * DPLL is enabled and the clocks are stable.
9114          *
9115          * So write it again.
9116          */
9117         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9118         POSTING_READ(PCH_DPLL(pll->id));
9119         udelay(200);
9120 }
9121
9122 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9123                                  struct intel_shared_dpll *pll)
9124 {
9125         struct drm_device *dev = dev_priv->dev;
9126         struct intel_crtc *crtc;
9127
9128         /* Make sure no transcoder isn't still depending on us. */
9129         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9130                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9131                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9132         }
9133
9134         I915_WRITE(PCH_DPLL(pll->id), 0);
9135         POSTING_READ(PCH_DPLL(pll->id));
9136         udelay(200);
9137 }
9138
9139 static char *ibx_pch_dpll_names[] = {
9140         "PCH DPLL A",
9141         "PCH DPLL B",
9142 };
9143
9144 static void ibx_pch_dpll_init(struct drm_device *dev)
9145 {
9146         struct drm_i915_private *dev_priv = dev->dev_private;
9147         int i;
9148
9149         dev_priv->num_shared_dpll = 2;
9150
9151         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9152                 dev_priv->shared_dplls[i].id = i;
9153                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9154                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9155                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9156                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9157                 dev_priv->shared_dplls[i].get_hw_state =
9158                         ibx_pch_dpll_get_hw_state;
9159         }
9160 }
9161
9162 static void intel_shared_dpll_init(struct drm_device *dev)
9163 {
9164         struct drm_i915_private *dev_priv = dev->dev_private;
9165
9166         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9167                 ibx_pch_dpll_init(dev);
9168         else
9169                 dev_priv->num_shared_dpll = 0;
9170
9171         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9172         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9173                       dev_priv->num_shared_dpll);
9174 }
9175
9176 static void intel_crtc_init(struct drm_device *dev, int pipe)
9177 {
9178         drm_i915_private_t *dev_priv = dev->dev_private;
9179         struct intel_crtc *intel_crtc;
9180         int i;
9181
9182         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9183         if (intel_crtc == NULL)
9184                 return;
9185
9186         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9187
9188         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9189         for (i = 0; i < 256; i++) {
9190                 intel_crtc->lut_r[i] = i;
9191                 intel_crtc->lut_g[i] = i;
9192                 intel_crtc->lut_b[i] = i;
9193         }
9194
9195         /* Swap pipes & planes for FBC on pre-965 */
9196         intel_crtc->pipe = pipe;
9197         intel_crtc->plane = pipe;
9198         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9199                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9200                 intel_crtc->plane = !pipe;
9201         }
9202
9203         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9204                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9205         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9206         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9207
9208         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9209 }
9210
9211 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9212                                 struct drm_file *file)
9213 {
9214         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9215         struct drm_mode_object *drmmode_obj;
9216         struct intel_crtc *crtc;
9217
9218         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9219                 return -ENODEV;
9220
9221         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9222                         DRM_MODE_OBJECT_CRTC);
9223
9224         if (!drmmode_obj) {
9225                 DRM_ERROR("no such CRTC id\n");
9226                 return -EINVAL;
9227         }
9228
9229         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9230         pipe_from_crtc_id->pipe = crtc->pipe;
9231
9232         return 0;
9233 }
9234
9235 static int intel_encoder_clones(struct intel_encoder *encoder)
9236 {
9237         struct drm_device *dev = encoder->base.dev;
9238         struct intel_encoder *source_encoder;
9239         int index_mask = 0;
9240         int entry = 0;
9241
9242         list_for_each_entry(source_encoder,
9243                             &dev->mode_config.encoder_list, base.head) {
9244
9245                 if (encoder == source_encoder)
9246                         index_mask |= (1 << entry);
9247
9248                 /* Intel hw has only one MUX where enocoders could be cloned. */
9249                 if (encoder->cloneable && source_encoder->cloneable)
9250                         index_mask |= (1 << entry);
9251
9252                 entry++;
9253         }
9254
9255         return index_mask;
9256 }
9257
9258 static bool has_edp_a(struct drm_device *dev)
9259 {
9260         struct drm_i915_private *dev_priv = dev->dev_private;
9261
9262         if (!IS_MOBILE(dev))
9263                 return false;
9264
9265         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9266                 return false;
9267
9268         if (IS_GEN5(dev) &&
9269             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9270                 return false;
9271
9272         return true;
9273 }
9274
9275 static void intel_setup_outputs(struct drm_device *dev)
9276 {
9277         struct drm_i915_private *dev_priv = dev->dev_private;
9278         struct intel_encoder *encoder;
9279         bool dpd_is_edp = false;
9280
9281         intel_lvds_init(dev);
9282
9283         if (!IS_ULT(dev))
9284                 intel_crt_init(dev);
9285
9286         if (HAS_DDI(dev)) {
9287                 int found;
9288
9289                 /* Haswell uses DDI functions to detect digital outputs */
9290                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9291                 /* DDI A only supports eDP */
9292                 if (found)
9293                         intel_ddi_init(dev, PORT_A);
9294
9295                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9296                  * register */
9297                 found = I915_READ(SFUSE_STRAP);
9298
9299                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9300                         intel_ddi_init(dev, PORT_B);
9301                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9302                         intel_ddi_init(dev, PORT_C);
9303                 if (found & SFUSE_STRAP_DDID_DETECTED)
9304                         intel_ddi_init(dev, PORT_D);
9305         } else if (HAS_PCH_SPLIT(dev)) {
9306                 int found;
9307                 dpd_is_edp = intel_dpd_is_edp(dev);
9308
9309                 if (has_edp_a(dev))
9310                         intel_dp_init(dev, DP_A, PORT_A);
9311
9312                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9313                         /* PCH SDVOB multiplex with HDMIB */
9314                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9315                         if (!found)
9316                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9317                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9318                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9319                 }
9320
9321                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9322                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9323
9324                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9325                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9326
9327                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9328                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9329
9330                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9331                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9332         } else if (IS_VALLEYVIEW(dev)) {
9333                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9334                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9335                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9336
9337                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9338                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9339                                         PORT_B);
9340                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9341                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9342                 }
9343         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9344                 bool found = false;
9345
9346                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9347                         DRM_DEBUG_KMS("probing SDVOB\n");
9348                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9349                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9350                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9351                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9352                         }
9353
9354                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9355                                 intel_dp_init(dev, DP_B, PORT_B);
9356                 }
9357
9358                 /* Before G4X SDVOC doesn't have its own detect register */
9359
9360                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9361                         DRM_DEBUG_KMS("probing SDVOC\n");
9362                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9363                 }
9364
9365                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9366
9367                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9368                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9369                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9370                         }
9371                         if (SUPPORTS_INTEGRATED_DP(dev))
9372                                 intel_dp_init(dev, DP_C, PORT_C);
9373                 }
9374
9375                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9376                     (I915_READ(DP_D) & DP_DETECTED))
9377                         intel_dp_init(dev, DP_D, PORT_D);
9378         } else if (IS_GEN2(dev))
9379                 intel_dvo_init(dev);
9380
9381         if (SUPPORTS_TV(dev))
9382                 intel_tv_init(dev);
9383
9384         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9385                 encoder->base.possible_crtcs = encoder->crtc_mask;
9386                 encoder->base.possible_clones =
9387                         intel_encoder_clones(encoder);
9388         }
9389
9390         intel_init_pch_refclk(dev);
9391
9392         drm_helper_move_panel_connectors_to_head(dev);
9393 }
9394
9395 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9396 {
9397         drm_framebuffer_cleanup(&fb->base);
9398         drm_gem_object_unreference_unlocked(&fb->obj->base);
9399 }
9400
9401 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9402 {
9403         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9404
9405         intel_framebuffer_fini(intel_fb);
9406         kfree(intel_fb);
9407 }
9408
9409 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9410                                                 struct drm_file *file,
9411                                                 unsigned int *handle)
9412 {
9413         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9414         struct drm_i915_gem_object *obj = intel_fb->obj;
9415
9416         return drm_gem_handle_create(file, &obj->base, handle);
9417 }
9418
9419 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9420         .destroy = intel_user_framebuffer_destroy,
9421         .create_handle = intel_user_framebuffer_create_handle,
9422 };
9423
9424 int intel_framebuffer_init(struct drm_device *dev,
9425                            struct intel_framebuffer *intel_fb,
9426                            struct drm_mode_fb_cmd2 *mode_cmd,
9427                            struct drm_i915_gem_object *obj)
9428 {
9429         int pitch_limit;
9430         int ret;
9431
9432         if (obj->tiling_mode == I915_TILING_Y) {
9433                 DRM_DEBUG("hardware does not support tiling Y\n");
9434                 return -EINVAL;
9435         }
9436
9437         if (mode_cmd->pitches[0] & 63) {
9438                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9439                           mode_cmd->pitches[0]);
9440                 return -EINVAL;
9441         }
9442
9443         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9444                 pitch_limit = 32*1024;
9445         } else if (INTEL_INFO(dev)->gen >= 4) {
9446                 if (obj->tiling_mode)
9447                         pitch_limit = 16*1024;
9448                 else
9449                         pitch_limit = 32*1024;
9450         } else if (INTEL_INFO(dev)->gen >= 3) {
9451                 if (obj->tiling_mode)
9452                         pitch_limit = 8*1024;
9453                 else
9454                         pitch_limit = 16*1024;
9455         } else
9456                 /* XXX DSPC is limited to 4k tiled */
9457                 pitch_limit = 8*1024;
9458
9459         if (mode_cmd->pitches[0] > pitch_limit) {
9460                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9461                           obj->tiling_mode ? "tiled" : "linear",
9462                           mode_cmd->pitches[0], pitch_limit);
9463                 return -EINVAL;
9464         }
9465
9466         if (obj->tiling_mode != I915_TILING_NONE &&
9467             mode_cmd->pitches[0] != obj->stride) {
9468                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9469                           mode_cmd->pitches[0], obj->stride);
9470                 return -EINVAL;
9471         }
9472
9473         /* Reject formats not supported by any plane early. */
9474         switch (mode_cmd->pixel_format) {
9475         case DRM_FORMAT_C8:
9476         case DRM_FORMAT_RGB565:
9477         case DRM_FORMAT_XRGB8888:
9478         case DRM_FORMAT_ARGB8888:
9479                 break;
9480         case DRM_FORMAT_XRGB1555:
9481         case DRM_FORMAT_ARGB1555:
9482                 if (INTEL_INFO(dev)->gen > 3) {
9483                         DRM_DEBUG("unsupported pixel format: %s\n",
9484                                   drm_get_format_name(mode_cmd->pixel_format));
9485                         return -EINVAL;
9486                 }
9487                 break;
9488         case DRM_FORMAT_XBGR8888:
9489         case DRM_FORMAT_ABGR8888:
9490         case DRM_FORMAT_XRGB2101010:
9491         case DRM_FORMAT_ARGB2101010:
9492         case DRM_FORMAT_XBGR2101010:
9493         case DRM_FORMAT_ABGR2101010:
9494                 if (INTEL_INFO(dev)->gen < 4) {
9495                         DRM_DEBUG("unsupported pixel format: %s\n",
9496                                   drm_get_format_name(mode_cmd->pixel_format));
9497                         return -EINVAL;
9498                 }
9499                 break;
9500         case DRM_FORMAT_YUYV:
9501         case DRM_FORMAT_UYVY:
9502         case DRM_FORMAT_YVYU:
9503         case DRM_FORMAT_VYUY:
9504                 if (INTEL_INFO(dev)->gen < 5) {
9505                         DRM_DEBUG("unsupported pixel format: %s\n",
9506                                   drm_get_format_name(mode_cmd->pixel_format));
9507                         return -EINVAL;
9508                 }
9509                 break;
9510         default:
9511                 DRM_DEBUG("unsupported pixel format: %s\n",
9512                           drm_get_format_name(mode_cmd->pixel_format));
9513                 return -EINVAL;
9514         }
9515
9516         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9517         if (mode_cmd->offsets[0] != 0)
9518                 return -EINVAL;
9519
9520         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9521         intel_fb->obj = obj;
9522
9523         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9524         if (ret) {
9525                 DRM_ERROR("framebuffer init failed %d\n", ret);
9526                 return ret;
9527         }
9528
9529         return 0;
9530 }
9531
9532 static struct drm_framebuffer *
9533 intel_user_framebuffer_create(struct drm_device *dev,
9534                               struct drm_file *filp,
9535                               struct drm_mode_fb_cmd2 *mode_cmd)
9536 {
9537         struct drm_i915_gem_object *obj;
9538
9539         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9540                                                 mode_cmd->handles[0]));
9541         if (&obj->base == NULL)
9542                 return ERR_PTR(-ENOENT);
9543
9544         return intel_framebuffer_create(dev, mode_cmd, obj);
9545 }
9546
9547 static const struct drm_mode_config_funcs intel_mode_funcs = {
9548         .fb_create = intel_user_framebuffer_create,
9549         .output_poll_changed = intel_fb_output_poll_changed,
9550 };
9551
9552 /* Set up chip specific display functions */
9553 static void intel_init_display(struct drm_device *dev)
9554 {
9555         struct drm_i915_private *dev_priv = dev->dev_private;
9556
9557         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9558                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9559         else if (IS_VALLEYVIEW(dev))
9560                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9561         else if (IS_PINEVIEW(dev))
9562                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9563         else
9564                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9565
9566         if (HAS_DDI(dev)) {
9567                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9568                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9569                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9570                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9571                 dev_priv->display.off = haswell_crtc_off;
9572                 dev_priv->display.update_plane = ironlake_update_plane;
9573         } else if (HAS_PCH_SPLIT(dev)) {
9574                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9575                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9576                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9577                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9578                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9579                 dev_priv->display.off = ironlake_crtc_off;
9580                 dev_priv->display.update_plane = ironlake_update_plane;
9581         } else if (IS_VALLEYVIEW(dev)) {
9582                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9583                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9584                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9585                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9586                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9587                 dev_priv->display.off = i9xx_crtc_off;
9588                 dev_priv->display.update_plane = i9xx_update_plane;
9589         } else {
9590                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9591                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9592                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9593                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9594                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9595                 dev_priv->display.off = i9xx_crtc_off;
9596                 dev_priv->display.update_plane = i9xx_update_plane;
9597         }
9598
9599         /* Returns the core display clock speed */
9600         if (IS_VALLEYVIEW(dev))
9601                 dev_priv->display.get_display_clock_speed =
9602                         valleyview_get_display_clock_speed;
9603         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9604                 dev_priv->display.get_display_clock_speed =
9605                         i945_get_display_clock_speed;
9606         else if (IS_I915G(dev))
9607                 dev_priv->display.get_display_clock_speed =
9608                         i915_get_display_clock_speed;
9609         else if (IS_I945GM(dev) || IS_845G(dev))
9610                 dev_priv->display.get_display_clock_speed =
9611                         i9xx_misc_get_display_clock_speed;
9612         else if (IS_PINEVIEW(dev))
9613                 dev_priv->display.get_display_clock_speed =
9614                         pnv_get_display_clock_speed;
9615         else if (IS_I915GM(dev))
9616                 dev_priv->display.get_display_clock_speed =
9617                         i915gm_get_display_clock_speed;
9618         else if (IS_I865G(dev))
9619                 dev_priv->display.get_display_clock_speed =
9620                         i865_get_display_clock_speed;
9621         else if (IS_I85X(dev))
9622                 dev_priv->display.get_display_clock_speed =
9623                         i855_get_display_clock_speed;
9624         else /* 852, 830 */
9625                 dev_priv->display.get_display_clock_speed =
9626                         i830_get_display_clock_speed;
9627
9628         if (HAS_PCH_SPLIT(dev)) {
9629                 if (IS_GEN5(dev)) {
9630                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9631                         dev_priv->display.write_eld = ironlake_write_eld;
9632                 } else if (IS_GEN6(dev)) {
9633                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9634                         dev_priv->display.write_eld = ironlake_write_eld;
9635                 } else if (IS_IVYBRIDGE(dev)) {
9636                         /* FIXME: detect B0+ stepping and use auto training */
9637                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9638                         dev_priv->display.write_eld = ironlake_write_eld;
9639                         dev_priv->display.modeset_global_resources =
9640                                 ivb_modeset_global_resources;
9641                 } else if (IS_HASWELL(dev)) {
9642                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9643                         dev_priv->display.write_eld = haswell_write_eld;
9644                         dev_priv->display.modeset_global_resources =
9645                                 haswell_modeset_global_resources;
9646                 }
9647         } else if (IS_G4X(dev)) {
9648                 dev_priv->display.write_eld = g4x_write_eld;
9649         }
9650
9651         /* Default just returns -ENODEV to indicate unsupported */
9652         dev_priv->display.queue_flip = intel_default_queue_flip;
9653
9654         switch (INTEL_INFO(dev)->gen) {
9655         case 2:
9656                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9657                 break;
9658
9659         case 3:
9660                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9661                 break;
9662
9663         case 4:
9664         case 5:
9665                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9666                 break;
9667
9668         case 6:
9669                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9670                 break;
9671         case 7:
9672                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9673                 break;
9674         }
9675 }
9676
9677 /*
9678  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9679  * resume, or other times.  This quirk makes sure that's the case for
9680  * affected systems.
9681  */
9682 static void quirk_pipea_force(struct drm_device *dev)
9683 {
9684         struct drm_i915_private *dev_priv = dev->dev_private;
9685
9686         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9687         DRM_INFO("applying pipe a force quirk\n");
9688 }
9689
9690 /*
9691  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9692  */
9693 static void quirk_ssc_force_disable(struct drm_device *dev)
9694 {
9695         struct drm_i915_private *dev_priv = dev->dev_private;
9696         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9697         DRM_INFO("applying lvds SSC disable quirk\n");
9698 }
9699
9700 /*
9701  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9702  * brightness value
9703  */
9704 static void quirk_invert_brightness(struct drm_device *dev)
9705 {
9706         struct drm_i915_private *dev_priv = dev->dev_private;
9707         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9708         DRM_INFO("applying inverted panel brightness quirk\n");
9709 }
9710
9711 /*
9712  * Some machines (Dell XPS13) suffer broken backlight controls if
9713  * BLM_PCH_PWM_ENABLE is set.
9714  */
9715 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9716 {
9717         struct drm_i915_private *dev_priv = dev->dev_private;
9718         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9719         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9720 }
9721
9722 struct intel_quirk {
9723         int device;
9724         int subsystem_vendor;
9725         int subsystem_device;
9726         void (*hook)(struct drm_device *dev);
9727 };
9728
9729 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9730 struct intel_dmi_quirk {
9731         void (*hook)(struct drm_device *dev);
9732         const struct dmi_system_id (*dmi_id_list)[];
9733 };
9734
9735 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9736 {
9737         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9738         return 1;
9739 }
9740
9741 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9742         {
9743                 .dmi_id_list = &(const struct dmi_system_id[]) {
9744                         {
9745                                 .callback = intel_dmi_reverse_brightness,
9746                                 .ident = "NCR Corporation",
9747                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9748                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9749                                 },
9750                         },
9751                         { }  /* terminating entry */
9752                 },
9753                 .hook = quirk_invert_brightness,
9754         },
9755 };
9756
9757 static struct intel_quirk intel_quirks[] = {
9758         /* HP Mini needs pipe A force quirk (LP: #322104) */
9759         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9760
9761         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9762         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9763
9764         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9765         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9766
9767         /* 830/845 need to leave pipe A & dpll A up */
9768         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9769         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9770
9771         /* Lenovo U160 cannot use SSC on LVDS */
9772         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9773
9774         /* Sony Vaio Y cannot use SSC on LVDS */
9775         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9776
9777         /* Acer Aspire 5734Z must invert backlight brightness */
9778         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9779
9780         /* Acer/eMachines G725 */
9781         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9782
9783         /* Acer/eMachines e725 */
9784         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9785
9786         /* Acer/Packard Bell NCL20 */
9787         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9788
9789         /* Acer Aspire 4736Z */
9790         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9791
9792         /* Dell XPS13 HD Sandy Bridge */
9793         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9794         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9795         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9796 };
9797
9798 static void intel_init_quirks(struct drm_device *dev)
9799 {
9800         struct pci_dev *d = dev->pdev;
9801         int i;
9802
9803         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9804                 struct intel_quirk *q = &intel_quirks[i];
9805
9806                 if (d->device == q->device &&
9807                     (d->subsystem_vendor == q->subsystem_vendor ||
9808                      q->subsystem_vendor == PCI_ANY_ID) &&
9809                     (d->subsystem_device == q->subsystem_device ||
9810                      q->subsystem_device == PCI_ANY_ID))
9811                         q->hook(dev);
9812         }
9813         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9814                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9815                         intel_dmi_quirks[i].hook(dev);
9816         }
9817 }
9818
9819 /* Disable the VGA plane that we never use */
9820 static void i915_disable_vga(struct drm_device *dev)
9821 {
9822         struct drm_i915_private *dev_priv = dev->dev_private;
9823         u8 sr1;
9824         u32 vga_reg = i915_vgacntrl_reg(dev);
9825
9826         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9827         outb(SR01, VGA_SR_INDEX);
9828         sr1 = inb(VGA_SR_DATA);
9829         outb(sr1 | 1<<5, VGA_SR_DATA);
9830         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9831         udelay(300);
9832
9833         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9834         POSTING_READ(vga_reg);
9835 }
9836
9837 void intel_modeset_init_hw(struct drm_device *dev)
9838 {
9839         intel_init_power_well(dev);
9840
9841         intel_prepare_ddi(dev);
9842
9843         intel_init_clock_gating(dev);
9844
9845         mutex_lock(&dev->struct_mutex);
9846         intel_enable_gt_powersave(dev);
9847         mutex_unlock(&dev->struct_mutex);
9848 }
9849
9850 void intel_modeset_suspend_hw(struct drm_device *dev)
9851 {
9852         intel_suspend_hw(dev);
9853 }
9854
9855 void intel_modeset_init(struct drm_device *dev)
9856 {
9857         struct drm_i915_private *dev_priv = dev->dev_private;
9858         int i, j, ret;
9859
9860         drm_mode_config_init(dev);
9861
9862         dev->mode_config.min_width = 0;
9863         dev->mode_config.min_height = 0;
9864
9865         dev->mode_config.preferred_depth = 24;
9866         dev->mode_config.prefer_shadow = 1;
9867
9868         dev->mode_config.funcs = &intel_mode_funcs;
9869
9870         intel_init_quirks(dev);
9871
9872         intel_init_pm(dev);
9873
9874         if (INTEL_INFO(dev)->num_pipes == 0)
9875                 return;
9876
9877         intel_init_display(dev);
9878
9879         if (IS_GEN2(dev)) {
9880                 dev->mode_config.max_width = 2048;
9881                 dev->mode_config.max_height = 2048;
9882         } else if (IS_GEN3(dev)) {
9883                 dev->mode_config.max_width = 4096;
9884                 dev->mode_config.max_height = 4096;
9885         } else {
9886                 dev->mode_config.max_width = 8192;
9887                 dev->mode_config.max_height = 8192;
9888         }
9889         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9890
9891         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9892                       INTEL_INFO(dev)->num_pipes,
9893                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9894
9895         for_each_pipe(i) {
9896                 intel_crtc_init(dev, i);
9897                 for (j = 0; j < dev_priv->num_plane; j++) {
9898                         ret = intel_plane_init(dev, i, j);
9899                         if (ret)
9900                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9901                                               pipe_name(i), sprite_name(i, j), ret);
9902                 }
9903         }
9904
9905         intel_cpu_pll_init(dev);
9906         intel_shared_dpll_init(dev);
9907
9908         /* Just disable it once at startup */
9909         i915_disable_vga(dev);
9910         intel_setup_outputs(dev);
9911
9912         /* Just in case the BIOS is doing something questionable. */
9913         intel_disable_fbc(dev);
9914 }
9915
9916 static void
9917 intel_connector_break_all_links(struct intel_connector *connector)
9918 {
9919         connector->base.dpms = DRM_MODE_DPMS_OFF;
9920         connector->base.encoder = NULL;
9921         connector->encoder->connectors_active = false;
9922         connector->encoder->base.crtc = NULL;
9923 }
9924
9925 static void intel_enable_pipe_a(struct drm_device *dev)
9926 {
9927         struct intel_connector *connector;
9928         struct drm_connector *crt = NULL;
9929         struct intel_load_detect_pipe load_detect_temp;
9930
9931         /* We can't just switch on the pipe A, we need to set things up with a
9932          * proper mode and output configuration. As a gross hack, enable pipe A
9933          * by enabling the load detect pipe once. */
9934         list_for_each_entry(connector,
9935                             &dev->mode_config.connector_list,
9936                             base.head) {
9937                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9938                         crt = &connector->base;
9939                         break;
9940                 }
9941         }
9942
9943         if (!crt)
9944                 return;
9945
9946         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9947                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9948
9949
9950 }
9951
9952 static bool
9953 intel_check_plane_mapping(struct intel_crtc *crtc)
9954 {
9955         struct drm_device *dev = crtc->base.dev;
9956         struct drm_i915_private *dev_priv = dev->dev_private;
9957         u32 reg, val;
9958
9959         if (INTEL_INFO(dev)->num_pipes == 1)
9960                 return true;
9961
9962         reg = DSPCNTR(!crtc->plane);
9963         val = I915_READ(reg);
9964
9965         if ((val & DISPLAY_PLANE_ENABLE) &&
9966             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9967                 return false;
9968
9969         return true;
9970 }
9971
9972 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9973 {
9974         struct drm_device *dev = crtc->base.dev;
9975         struct drm_i915_private *dev_priv = dev->dev_private;
9976         u32 reg;
9977
9978         /* Clear any frame start delays used for debugging left by the BIOS */
9979         reg = PIPECONF(crtc->config.cpu_transcoder);
9980         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9981
9982         /* We need to sanitize the plane -> pipe mapping first because this will
9983          * disable the crtc (and hence change the state) if it is wrong. Note
9984          * that gen4+ has a fixed plane -> pipe mapping.  */
9985         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9986                 struct intel_connector *connector;
9987                 bool plane;
9988
9989                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9990                               crtc->base.base.id);
9991
9992                 /* Pipe has the wrong plane attached and the plane is active.
9993                  * Temporarily change the plane mapping and disable everything
9994                  * ...  */
9995                 plane = crtc->plane;
9996                 crtc->plane = !plane;
9997                 dev_priv->display.crtc_disable(&crtc->base);
9998                 crtc->plane = plane;
9999
10000                 /* ... and break all links. */
10001                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10002                                     base.head) {
10003                         if (connector->encoder->base.crtc != &crtc->base)
10004                                 continue;
10005
10006                         intel_connector_break_all_links(connector);
10007                 }
10008
10009                 WARN_ON(crtc->active);
10010                 crtc->base.enabled = false;
10011         }
10012
10013         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10014             crtc->pipe == PIPE_A && !crtc->active) {
10015                 /* BIOS forgot to enable pipe A, this mostly happens after
10016                  * resume. Force-enable the pipe to fix this, the update_dpms
10017                  * call below we restore the pipe to the right state, but leave
10018                  * the required bits on. */
10019                 intel_enable_pipe_a(dev);
10020         }
10021
10022         /* Adjust the state of the output pipe according to whether we
10023          * have active connectors/encoders. */
10024         intel_crtc_update_dpms(&crtc->base);
10025
10026         if (crtc->active != crtc->base.enabled) {
10027                 struct intel_encoder *encoder;
10028
10029                 /* This can happen either due to bugs in the get_hw_state
10030                  * functions or because the pipe is force-enabled due to the
10031                  * pipe A quirk. */
10032                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10033                               crtc->base.base.id,
10034                               crtc->base.enabled ? "enabled" : "disabled",
10035                               crtc->active ? "enabled" : "disabled");
10036
10037                 crtc->base.enabled = crtc->active;
10038
10039                 /* Because we only establish the connector -> encoder ->
10040                  * crtc links if something is active, this means the
10041                  * crtc is now deactivated. Break the links. connector
10042                  * -> encoder links are only establish when things are
10043                  *  actually up, hence no need to break them. */
10044                 WARN_ON(crtc->active);
10045
10046                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10047                         WARN_ON(encoder->connectors_active);
10048                         encoder->base.crtc = NULL;
10049                 }
10050         }
10051 }
10052
10053 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10054 {
10055         struct intel_connector *connector;
10056         struct drm_device *dev = encoder->base.dev;
10057
10058         /* We need to check both for a crtc link (meaning that the
10059          * encoder is active and trying to read from a pipe) and the
10060          * pipe itself being active. */
10061         bool has_active_crtc = encoder->base.crtc &&
10062                 to_intel_crtc(encoder->base.crtc)->active;
10063
10064         if (encoder->connectors_active && !has_active_crtc) {
10065                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10066                               encoder->base.base.id,
10067                               drm_get_encoder_name(&encoder->base));
10068
10069                 /* Connector is active, but has no active pipe. This is
10070                  * fallout from our resume register restoring. Disable
10071                  * the encoder manually again. */
10072                 if (encoder->base.crtc) {
10073                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10074                                       encoder->base.base.id,
10075                                       drm_get_encoder_name(&encoder->base));
10076                         encoder->disable(encoder);
10077                 }
10078
10079                 /* Inconsistent output/port/pipe state happens presumably due to
10080                  * a bug in one of the get_hw_state functions. Or someplace else
10081                  * in our code, like the register restore mess on resume. Clamp
10082                  * things to off as a safer default. */
10083                 list_for_each_entry(connector,
10084                                     &dev->mode_config.connector_list,
10085                                     base.head) {
10086                         if (connector->encoder != encoder)
10087                                 continue;
10088
10089                         intel_connector_break_all_links(connector);
10090                 }
10091         }
10092         /* Enabled encoders without active connectors will be fixed in
10093          * the crtc fixup. */
10094 }
10095
10096 void i915_redisable_vga(struct drm_device *dev)
10097 {
10098         struct drm_i915_private *dev_priv = dev->dev_private;
10099         u32 vga_reg = i915_vgacntrl_reg(dev);
10100
10101         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10102                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10103                 i915_disable_vga(dev);
10104         }
10105 }
10106
10107 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10108 {
10109         struct drm_i915_private *dev_priv = dev->dev_private;
10110         enum pipe pipe;
10111         struct intel_crtc *crtc;
10112         struct intel_encoder *encoder;
10113         struct intel_connector *connector;
10114         int i;
10115
10116         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10117                             base.head) {
10118                 memset(&crtc->config, 0, sizeof(crtc->config));
10119
10120                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10121                                                                  &crtc->config);
10122
10123                 crtc->base.enabled = crtc->active;
10124
10125                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10126                               crtc->base.base.id,
10127                               crtc->active ? "enabled" : "disabled");
10128         }
10129
10130         /* FIXME: Smash this into the new shared dpll infrastructure. */
10131         if (HAS_DDI(dev))
10132                 intel_ddi_setup_hw_pll_state(dev);
10133
10134         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10135                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10136
10137                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10138                 pll->active = 0;
10139                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10140                                     base.head) {
10141                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10142                                 pll->active++;
10143                 }
10144                 pll->refcount = pll->active;
10145
10146                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10147                               pll->name, pll->refcount, pll->on);
10148         }
10149
10150         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10151                             base.head) {
10152                 pipe = 0;
10153
10154                 if (encoder->get_hw_state(encoder, &pipe)) {
10155                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10156                         encoder->base.crtc = &crtc->base;
10157                         if (encoder->get_config)
10158                                 encoder->get_config(encoder, &crtc->config);
10159                 } else {
10160                         encoder->base.crtc = NULL;
10161                 }
10162
10163                 encoder->connectors_active = false;
10164                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10165                               encoder->base.base.id,
10166                               drm_get_encoder_name(&encoder->base),
10167                               encoder->base.crtc ? "enabled" : "disabled",
10168                               pipe);
10169         }
10170
10171         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10172                             base.head) {
10173                 if (!crtc->active)
10174                         continue;
10175                 if (dev_priv->display.get_clock)
10176                         dev_priv->display.get_clock(crtc,
10177                                                     &crtc->config);
10178         }
10179
10180         list_for_each_entry(connector, &dev->mode_config.connector_list,
10181                             base.head) {
10182                 if (connector->get_hw_state(connector)) {
10183                         connector->base.dpms = DRM_MODE_DPMS_ON;
10184                         connector->encoder->connectors_active = true;
10185                         connector->base.encoder = &connector->encoder->base;
10186                 } else {
10187                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10188                         connector->base.encoder = NULL;
10189                 }
10190                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10191                               connector->base.base.id,
10192                               drm_get_connector_name(&connector->base),
10193                               connector->base.encoder ? "enabled" : "disabled");
10194         }
10195 }
10196
10197 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10198  * and i915 state tracking structures. */
10199 void intel_modeset_setup_hw_state(struct drm_device *dev,
10200                                   bool force_restore)
10201 {
10202         struct drm_i915_private *dev_priv = dev->dev_private;
10203         enum pipe pipe;
10204         struct drm_plane *plane;
10205         struct intel_crtc *crtc;
10206         struct intel_encoder *encoder;
10207         int i;
10208
10209         intel_modeset_readout_hw_state(dev);
10210
10211         /*
10212          * Now that we have the config, copy it to each CRTC struct
10213          * Note that this could go away if we move to using crtc_config
10214          * checking everywhere.
10215          */
10216         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10217                             base.head) {
10218                 if (crtc->active && i915_fastboot) {
10219                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10220
10221                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10222                                       crtc->base.base.id);
10223                         drm_mode_debug_printmodeline(&crtc->base.mode);
10224                 }
10225         }
10226
10227         /* HW state is read out, now we need to sanitize this mess. */
10228         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10229                             base.head) {
10230                 intel_sanitize_encoder(encoder);
10231         }
10232
10233         for_each_pipe(pipe) {
10234                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10235                 intel_sanitize_crtc(crtc);
10236                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10237         }
10238
10239         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10240                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10241
10242                 if (!pll->on || pll->active)
10243                         continue;
10244
10245                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10246
10247                 pll->disable(dev_priv, pll);
10248                 pll->on = false;
10249         }
10250
10251         if (force_restore) {
10252                 /*
10253                  * We need to use raw interfaces for restoring state to avoid
10254                  * checking (bogus) intermediate states.
10255                  */
10256                 for_each_pipe(pipe) {
10257                         struct drm_crtc *crtc =
10258                                 dev_priv->pipe_to_crtc_mapping[pipe];
10259
10260                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10261                                          crtc->fb);
10262                 }
10263                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10264                         intel_plane_restore(plane);
10265
10266                 i915_redisable_vga(dev);
10267         } else {
10268                 intel_modeset_update_staged_output_state(dev);
10269         }
10270
10271         intel_modeset_check_state(dev);
10272
10273         drm_mode_config_reset(dev);
10274 }
10275
10276 void intel_modeset_gem_init(struct drm_device *dev)
10277 {
10278         intel_modeset_init_hw(dev);
10279
10280         intel_setup_overlay(dev);
10281
10282         intel_modeset_setup_hw_state(dev, false);
10283 }
10284
10285 void intel_modeset_cleanup(struct drm_device *dev)
10286 {
10287         struct drm_i915_private *dev_priv = dev->dev_private;
10288         struct drm_crtc *crtc;
10289         struct intel_crtc *intel_crtc;
10290
10291         /*
10292          * Interrupts and polling as the first thing to avoid creating havoc.
10293          * Too much stuff here (turning of rps, connectors, ...) would
10294          * experience fancy races otherwise.
10295          */
10296         drm_irq_uninstall(dev);
10297         cancel_work_sync(&dev_priv->hotplug_work);
10298         /*
10299          * Due to the hpd irq storm handling the hotplug work can re-arm the
10300          * poll handlers. Hence disable polling after hpd handling is shut down.
10301          */
10302         drm_kms_helper_poll_fini(dev);
10303
10304         mutex_lock(&dev->struct_mutex);
10305
10306         intel_unregister_dsm_handler();
10307
10308         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10309                 /* Skip inactive CRTCs */
10310                 if (!crtc->fb)
10311                         continue;
10312
10313                 intel_crtc = to_intel_crtc(crtc);
10314                 intel_increase_pllclock(crtc);
10315         }
10316
10317         intel_disable_fbc(dev);
10318
10319         intel_disable_gt_powersave(dev);
10320
10321         ironlake_teardown_rc6(dev);
10322
10323         mutex_unlock(&dev->struct_mutex);
10324
10325         /* flush any delayed tasks or pending work */
10326         flush_scheduled_work();
10327
10328         /* destroy backlight, if any, before the connectors */
10329         intel_panel_destroy_backlight(dev);
10330
10331         drm_mode_config_cleanup(dev);
10332
10333         intel_cleanup_overlay(dev);
10334 }
10335
10336 /*
10337  * Return which encoder is currently attached for connector.
10338  */
10339 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10340 {
10341         return &intel_attached_encoder(connector)->base;
10342 }
10343
10344 void intel_connector_attach_encoder(struct intel_connector *connector,
10345                                     struct intel_encoder *encoder)
10346 {
10347         connector->encoder = encoder;
10348         drm_mode_connector_attach_encoder(&connector->base,
10349                                           &encoder->base);
10350 }
10351
10352 /*
10353  * set vga decode state - true == enable VGA decode
10354  */
10355 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10356 {
10357         struct drm_i915_private *dev_priv = dev->dev_private;
10358         u16 gmch_ctrl;
10359
10360         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10361         if (state)
10362                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10363         else
10364                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10365         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10366         return 0;
10367 }
10368
10369 struct intel_display_error_state {
10370
10371         u32 power_well_driver;
10372
10373         struct intel_cursor_error_state {
10374                 u32 control;
10375                 u32 position;
10376                 u32 base;
10377                 u32 size;
10378         } cursor[I915_MAX_PIPES];
10379
10380         struct intel_pipe_error_state {
10381                 enum transcoder cpu_transcoder;
10382                 u32 conf;
10383                 u32 source;
10384
10385                 u32 htotal;
10386                 u32 hblank;
10387                 u32 hsync;
10388                 u32 vtotal;
10389                 u32 vblank;
10390                 u32 vsync;
10391         } pipe[I915_MAX_PIPES];
10392
10393         struct intel_plane_error_state {
10394                 u32 control;
10395                 u32 stride;
10396                 u32 size;
10397                 u32 pos;
10398                 u32 addr;
10399                 u32 surface;
10400                 u32 tile_offset;
10401         } plane[I915_MAX_PIPES];
10402 };
10403
10404 struct intel_display_error_state *
10405 intel_display_capture_error_state(struct drm_device *dev)
10406 {
10407         drm_i915_private_t *dev_priv = dev->dev_private;
10408         struct intel_display_error_state *error;
10409         enum transcoder cpu_transcoder;
10410         int i;
10411
10412         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10413         if (error == NULL)
10414                 return NULL;
10415
10416         if (HAS_POWER_WELL(dev))
10417                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10418
10419         for_each_pipe(i) {
10420                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10421                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10422
10423                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10424                         error->cursor[i].control = I915_READ(CURCNTR(i));
10425                         error->cursor[i].position = I915_READ(CURPOS(i));
10426                         error->cursor[i].base = I915_READ(CURBASE(i));
10427                 } else {
10428                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10429                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10430                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10431                 }
10432
10433                 error->plane[i].control = I915_READ(DSPCNTR(i));
10434                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10435                 if (INTEL_INFO(dev)->gen <= 3) {
10436                         error->plane[i].size = I915_READ(DSPSIZE(i));
10437                         error->plane[i].pos = I915_READ(DSPPOS(i));
10438                 }
10439                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10440                         error->plane[i].addr = I915_READ(DSPADDR(i));
10441                 if (INTEL_INFO(dev)->gen >= 4) {
10442                         error->plane[i].surface = I915_READ(DSPSURF(i));
10443                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10444                 }
10445
10446                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10447                 error->pipe[i].source = I915_READ(PIPESRC(i));
10448                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10449                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10450                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10451                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10452                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10453                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10454         }
10455
10456         /* In the code above we read the registers without checking if the power
10457          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10458          * prevent the next I915_WRITE from detecting it and printing an error
10459          * message. */
10460         intel_uncore_clear_errors(dev);
10461
10462         return error;
10463 }
10464
10465 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10466
10467 void
10468 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10469                                 struct drm_device *dev,
10470                                 struct intel_display_error_state *error)
10471 {
10472         int i;
10473
10474         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10475         if (HAS_POWER_WELL(dev))
10476                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10477                            error->power_well_driver);
10478         for_each_pipe(i) {
10479                 err_printf(m, "Pipe [%d]:\n", i);
10480                 err_printf(m, "  CPU transcoder: %c\n",
10481                            transcoder_name(error->pipe[i].cpu_transcoder));
10482                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10483                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10484                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10485                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10486                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10487                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10488                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10489                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10490
10491                 err_printf(m, "Plane [%d]:\n", i);
10492                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10493                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10494                 if (INTEL_INFO(dev)->gen <= 3) {
10495                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10496                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10497                 }
10498                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10499                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10500                 if (INTEL_INFO(dev)->gen >= 4) {
10501                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10502                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10503                 }
10504
10505                 err_printf(m, "Cursor [%d]:\n", i);
10506                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10507                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10508                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10509         }
10510 }