drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 #define INTEL_P2_NUM                  2
  63 typedef struct intel_limit intel_limit_t;
  64 struct intel_limit {
  65         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  66         intel_p2_t          p2;
  67 };
  68
  69 /* FDI */
  70 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t intel_limits_vlv_dp = {
 340         .dot = { .min = 25000, .max = 270000 },
 341         .vco = { .min = 4000000, .max = 6000000 },
 342         .n = { .min = 1, .max = 7 },
 343         .m = { .min = 22, .max = 450 },
 344         .m1 = { .min = 2, .max = 3 },
 345         .m2 = { .min = 11, .max = 156 },
 346         .p = { .min = 10, .max = 30 },
 347         .p1 = { .min = 1, .max = 3 },
 348         .p2 = { .dot_limit = 270000,
 349                 .p2_slow = 2, .p2_fast = 20 },
 350 };
 351
 352 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 353                                                 int refclk)
 354 {
 355         struct drm_device *dev = crtc->dev;
 356         const intel_limit_t *limit;
 357
 358         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 359                 if (intel_is_dual_link_lvds(dev)) {
 360                         if (refclk == 100000)
 361                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 362                         else
 363                                 limit = &intel_limits_ironlake_dual_lvds;
 364                 } else {
 365                         if (refclk == 100000)
 366                                 limit = &intel_limits_ironlake_single_lvds_100m;
 367                         else
 368                                 limit = &intel_limits_ironlake_single_lvds;
 369                 }
 370         } else
 371                 limit = &intel_limits_ironlake_dac;
 372
 373         return limit;
 374 }
 375
 376 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev))
 383                         limit = &intel_limits_g4x_dual_channel_lvds;
 384                 else
 385                         limit = &intel_limits_g4x_single_channel_lvds;
 386         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 387                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 388                 limit = &intel_limits_g4x_hdmi;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 390                 limit = &intel_limits_g4x_sdvo;
 391         } else /* The option is for other outputs */
 392                 limit = &intel_limits_i9xx_sdvo;
 393
 394         return limit;
 395 }
 396
 397 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 398 {
 399         struct drm_device *dev = crtc->dev;
 400         const intel_limit_t *limit;
 401
 402         if (HAS_PCH_SPLIT(dev))
 403                 limit = intel_ironlake_limit(crtc, refclk);
 404         else if (IS_G4X(dev)) {
 405                 limit = intel_g4x_limit(crtc);
 406         } else if (IS_PINEVIEW(dev)) {
 407                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 408                         limit = &intel_limits_pineview_lvds;
 409                 else
 410                         limit = &intel_limits_pineview_sdvo;
 411         } else if (IS_VALLEYVIEW(dev)) {
 412                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 413                         limit = &intel_limits_vlv_dac;
 414                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 415                         limit = &intel_limits_vlv_hdmi;
 416                 else
 417                         limit = &intel_limits_vlv_dp;
 418         } else if (!IS_GEN2(dev)) {
 419                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 420                         limit = &intel_limits_i9xx_lvds;
 421                 else
 422                         limit = &intel_limits_i9xx_sdvo;
 423         } else {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_i8xx_lvds;
 426                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 427                         limit = &intel_limits_i8xx_dvo;
 428                 else
 429                         limit = &intel_limits_i8xx_dac;
 430         }
 431         return limit;
 432 }
 433
 434 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 435 static void pineview_clock(int refclk, intel_clock_t *clock)
 436 {
 437         clock->m = clock->m2 + 2;
 438         clock->p = clock->p1 * clock->p2;
 439         clock->vco = refclk * clock->m / clock->n;
 440         clock->dot = clock->vco / clock->p;
 441 }
 442
 443 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 444 {
 445         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 446 }
 447
 448 static void i9xx_clock(int refclk, intel_clock_t *clock)
 449 {
 450         clock->m = i9xx_dpll_compute_m(clock);
 451         clock->p = clock->p1 * clock->p2;
 452         clock->vco = refclk * clock->m / (clock->n + 2);
 453         clock->dot = clock->vco / clock->p;
 454 }
 455
 456 /**
 457  * Returns whether any output on the specified pipe is of the specified type
 458  */
 459 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 460 {
 461         struct drm_device *dev = crtc->dev;
 462         struct intel_encoder *encoder;
 463
 464         for_each_encoder_on_crtc(dev, crtc, encoder)
 465                 if (encoder->type == type)
 466                         return true;
 467
 468         return false;
 469 }
 470
 471 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 472 /**
 473  * Returns whether the given set of divisors are valid for a given refclk with
 474  * the given connectors.
 475  */
 476
 477 static bool intel_PLL_is_valid(struct drm_device *dev,
 478                                const intel_limit_t *limit,
 479                                const intel_clock_t *clock)
 480 {
 481         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 482                 INTELPllInvalid("p1 out of range\n");
 483         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 484                 INTELPllInvalid("p out of range\n");
 485         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 486                 INTELPllInvalid("m2 out of range\n");
 487         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 488                 INTELPllInvalid("m1 out of range\n");
 489         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 490                 INTELPllInvalid("m1 <= m2\n");
 491         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 492                 INTELPllInvalid("m out of range\n");
 493         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 494                 INTELPllInvalid("n out of range\n");
 495         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 496                 INTELPllInvalid("vco out of range\n");
 497         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 498          * connector, etc., rather than just a single range.
 499          */
 500         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 501                 INTELPllInvalid("dot out of range\n");
 502
 503         return true;
 504 }
 505
 506 static bool
 507 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 508                     int target, int refclk, intel_clock_t *match_clock,
 509                     intel_clock_t *best_clock)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         intel_clock_t clock;
 513         int err = target;
 514
 515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 516                 /*
 517                  * For LVDS just rely on its current settings for dual-channel.
 518                  * We haven't figured out how to reliably set up different
 519                  * single/dual channel state, if we even can.
 520                  */
 521                 if (intel_is_dual_link_lvds(dev))
 522                         clock.p2 = limit->p2.p2_fast;
 523                 else
 524                         clock.p2 = limit->p2.p2_slow;
 525         } else {
 526                 if (target < limit->p2.dot_limit)
 527                         clock.p2 = limit->p2.p2_slow;
 528                 else
 529                         clock.p2 = limit->p2.p2_fast;
 530         }
 531
 532         memset(best_clock, 0, sizeof(*best_clock));
 533
 534         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 535              clock.m1++) {
 536                 for (clock.m2 = limit->m2.min;
 537                      clock.m2 <= limit->m2.max; clock.m2++) {
 538                         if (clock.m2 >= clock.m1)
 539                                 break;
 540                         for (clock.n = limit->n.min;
 541                              clock.n <= limit->n.max; clock.n++) {
 542                                 for (clock.p1 = limit->p1.min;
 543                                         clock.p1 <= limit->p1.max; clock.p1++) {
 544                                         int this_err;
 545
 546                                         i9xx_clock(refclk, &clock);
 547                                         if (!intel_PLL_is_valid(dev, limit,
 548                                                                 &clock))
 549                                                 continue;
 550                                         if (match_clock &&
 551                                             clock.p != match_clock->p)
 552                                                 continue;
 553
 554                                         this_err = abs(clock.dot - target);
 555                                         if (this_err < err) {
 556                                                 *best_clock = clock;
 557                                                 err = this_err;
 558                                         }
 559                                 }
 560                         }
 561                 }
 562         }
 563
 564         return (err != target);
 565 }
 566
 567 static bool
 568 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 569                    int target, int refclk, intel_clock_t *match_clock,
 570                    intel_clock_t *best_clock)
 571 {
 572         struct drm_device *dev = crtc->dev;
 573         intel_clock_t clock;
 574         int err = target;
 575
 576         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 577                 /*
 578                  * For LVDS just rely on its current settings for dual-channel.
 579                  * We haven't figured out how to reliably set up different
 580                  * single/dual channel state, if we even can.
 581                  */
 582                 if (intel_is_dual_link_lvds(dev))
 583                         clock.p2 = limit->p2.p2_fast;
 584                 else
 585                         clock.p2 = limit->p2.p2_slow;
 586         } else {
 587                 if (target < limit->p2.dot_limit)
 588                         clock.p2 = limit->p2.p2_slow;
 589                 else
 590                         clock.p2 = limit->p2.p2_fast;
 591         }
 592
 593         memset(best_clock, 0, sizeof(*best_clock));
 594
 595         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 596              clock.m1++) {
 597                 for (clock.m2 = limit->m2.min;
 598                      clock.m2 <= limit->m2.max; clock.m2++) {
 599                         for (clock.n = limit->n.min;
 600                              clock.n <= limit->n.max; clock.n++) {
 601                                 for (clock.p1 = limit->p1.min;
 602                                         clock.p1 <= limit->p1.max; clock.p1++) {
 603                                         int this_err;
 604
 605                                         pineview_clock(refclk, &clock);
 606                                         if (!intel_PLL_is_valid(dev, limit,
 607                                                                 &clock))
 608                                                 continue;
 609                                         if (match_clock &&
 610                                             clock.p != match_clock->p)
 611                                                 continue;
 612
 613                                         this_err = abs(clock.dot - target);
 614                                         if (this_err < err) {
 615                                                 *best_clock = clock;
 616                                                 err = this_err;
 617                                         }
 618                                 }
 619                         }
 620                 }
 621         }
 622
 623         return (err != target);
 624 }
 625
 626 static bool
 627 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 628                    int target, int refclk, intel_clock_t *match_clock,
 629                    intel_clock_t *best_clock)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int max_n;
 634         bool found;
 635         /* approximately equals target * 0.00585 */
 636         int err_most = (target >> 8) + (target >> 9);
 637         found = false;
 638
 639         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 640                 if (intel_is_dual_link_lvds(dev))
 641                         clock.p2 = limit->p2.p2_fast;
 642                 else
 643                         clock.p2 = limit->p2.p2_slow;
 644         } else {
 645                 if (target < limit->p2.dot_limit)
 646                         clock.p2 = limit->p2.p2_slow;
 647                 else
 648                         clock.p2 = limit->p2.p2_fast;
 649         }
 650
 651         memset(best_clock, 0, sizeof(*best_clock));
 652         max_n = limit->n.max;
 653         /* based on hardware requirement, prefer smaller n to precision */
 654         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 655                 /* based on hardware requirement, prefere larger m1,m2 */
 656                 for (clock.m1 = limit->m1.max;
 657                      clock.m1 >= limit->m1.min; clock.m1--) {
 658                         for (clock.m2 = limit->m2.max;
 659                              clock.m2 >= limit->m2.min; clock.m2--) {
 660                                 for (clock.p1 = limit->p1.max;
 661                                      clock.p1 >= limit->p1.min; clock.p1--) {
 662                                         int this_err;
 663
 664                                         i9xx_clock(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(dev, limit,
 666                                                                 &clock))
 667                                                 continue;
 668
 669                                         this_err = abs(clock.dot - target);
 670                                         if (this_err < err_most) {
 671                                                 *best_clock = clock;
 672                                                 err_most = this_err;
 673                                                 max_n = clock.n;
 674                                                 found = true;
 675                                         }
 676                                 }
 677                         }
 678                 }
 679         }
 680         return found;
 681 }
 682
 683 static bool
 684 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 685                    int target, int refclk, intel_clock_t *match_clock,
 686                    intel_clock_t *best_clock)
 687 {
 688         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 689         u32 m, n, fastclk;
 690         u32 updrate, minupdate, fracbits, p;
 691         unsigned long bestppm, ppm, absppm;
 692         int dotclk, flag;
 693
 694         flag = 0;
 695         dotclk = target * 1000;
 696         bestppm = 1000000;
 697         ppm = absppm = 0;
 698         fastclk = dotclk / (2*100);
 699         updrate = 0;
 700         minupdate = 19200;
 701         fracbits = 1;
 702         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 703         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 704
 705         /* based on hardware requirement, prefer smaller n to precision */
 706         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 707                 updrate = refclk / n;
 708                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 709                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 710                                 if (p2 > 10)
 711                                         p2 = p2 - 1;
 712                                 p = p1 * p2;
 713                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 714                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 715                                         m2 = (((2*(fastclk * p * n / m1 )) +
 716                                                refclk) / (2*refclk));
 717                                         m = m1 * m2;
 718                                         vco = updrate * m;
 719                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 720                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 721                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 722                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 723                                                         bestppm = 0;
 724                                                         flag = 1;
 725                                                 }
 726                                                 if (absppm < bestppm - 10) {
 727                                                         bestppm = absppm;
 728                                                         flag = 1;
 729                                                 }
 730                                                 if (flag) {
 731                                                         bestn = n;
 732                                                         bestm1 = m1;
 733                                                         bestm2 = m2;
 734                                                         bestp1 = p1;
 735                                                         bestp2 = p2;
 736                                                         flag = 0;
 737                                                 }
 738                                         }
 739                                 }
 740                         }
 741                 }
 742         }
 743         best_clock->n = bestn;
 744         best_clock->m1 = bestm1;
 745         best_clock->m2 = bestm2;
 746         best_clock->p1 = bestp1;
 747         best_clock->p2 = bestp2;
 748
 749         return true;
 750 }
 751
 752 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 753                                              enum pipe pipe)
 754 {
 755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757
 758         return intel_crtc->config.cpu_transcoder;
 759 }
 760
 761 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 762 {
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         u32 frame, frame_reg = PIPEFRAME(pipe);
 765
 766         frame = I915_READ(frame_reg);
 767
 768         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 769                 DRM_DEBUG_KMS("vblank wait timed out\n");
 770 }
 771
 772 /**
 773  * intel_wait_for_vblank - wait for vblank on a given pipe
 774  * @dev: drm device
 775  * @pipe: pipe to wait for
 776  *
 777  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 778  * mode setting code.
 779  */
 780 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 781 {
 782         struct drm_i915_private *dev_priv = dev->dev_private;
 783         int pipestat_reg = PIPESTAT(pipe);
 784
 785         if (INTEL_INFO(dev)->gen >= 5) {
 786                 ironlake_wait_for_vblank(dev, pipe);
 787                 return;
 788         }
 789
 790         /* Clear existing vblank status. Note this will clear any other
 791          * sticky status fields as well.
 792          *
 793          * This races with i915_driver_irq_handler() with the result
 794          * that either function could miss a vblank event.  Here it is not
 795          * fatal, as we will either wait upon the next vblank interrupt or
 796          * timeout.  Generally speaking intel_wait_for_vblank() is only
 797          * called during modeset at which time the GPU should be idle and
 798          * should *not* be performing page flips and thus not waiting on
 799          * vblanks...
 800          * Currently, the result of us stealing a vblank from the irq
 801          * handler is that a single frame will be skipped during swapbuffers.
 802          */
 803         I915_WRITE(pipestat_reg,
 804                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 805
 806         /* Wait for vblank interrupt bit to set */
 807         if (wait_for(I915_READ(pipestat_reg) &
 808                      PIPE_VBLANK_INTERRUPT_STATUS,
 809                      50))
 810                 DRM_DEBUG_KMS("vblank wait timed out\n");
 811 }
 812
 813 /*
 814  * intel_wait_for_pipe_off - wait for pipe to turn off
 815  * @dev: drm device
 816  * @pipe: pipe to wait for
 817  *
 818  * After disabling a pipe, we can't wait for vblank in the usual way,
 819  * spinning on the vblank interrupt status bit, since we won't actually
 820  * see an interrupt when the pipe is disabled.
 821  *
 822  * On Gen4 and above:
 823  *   wait for the pipe register state bit to turn off
 824  *
 825  * Otherwise:
 826  *   wait for the display line value to settle (it usually
 827  *   ends up stopping at the start of the next frame).
 828  *
 829  */
 830 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 834                                                                       pipe);
 835
 836         if (INTEL_INFO(dev)->gen >= 4) {
 837                 int reg = PIPECONF(cpu_transcoder);
 838
 839                 /* Wait for the Pipe State to go off */
 840                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 841                              100))
 842                         WARN(1, "pipe_off wait timed out\n");
 843         } else {
 844                 u32 last_line, line_mask;
 845                 int reg = PIPEDSL(pipe);
 846                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 847
 848                 if (IS_GEN2(dev))
 849                         line_mask = DSL_LINEMASK_GEN2;
 850                 else
 851                         line_mask = DSL_LINEMASK_GEN3;
 852
 853                 /* Wait for the display line to settle */
 854                 do {
 855                         last_line = I915_READ(reg) & line_mask;
 856                         mdelay(5);
 857                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 858                          time_after(timeout, jiffies));
 859                 if (time_after(jiffies, timeout))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         }
 862 }
 863
 864 /*
 865  * ibx_digital_port_connected - is the specified port connected?
 866  * @dev_priv: i915 private structure
 867  * @port: the port to test
 868  *
 869  * Returns true if @port is connected, false otherwise.
 870  */
 871 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 872                                 struct intel_digital_port *port)
 873 {
 874         u32 bit;
 875
 876         if (HAS_PCH_IBX(dev_priv->dev)) {
 877                 switch(port->port) {
 878                 case PORT_B:
 879                         bit = SDE_PORTB_HOTPLUG;
 880                         break;
 881                 case PORT_C:
 882                         bit = SDE_PORTC_HOTPLUG;
 883                         break;
 884                 case PORT_D:
 885                         bit = SDE_PORTD_HOTPLUG;
 886                         break;
 887                 default:
 888                         return true;
 889                 }
 890         } else {
 891                 switch(port->port) {
 892                 case PORT_B:
 893                         bit = SDE_PORTB_HOTPLUG_CPT;
 894                         break;
 895                 case PORT_C:
 896                         bit = SDE_PORTC_HOTPLUG_CPT;
 897                         break;
 898                 case PORT_D:
 899                         bit = SDE_PORTD_HOTPLUG_CPT;
 900                         break;
 901                 default:
 902                         return true;
 903                 }
 904         }
 905
 906         return I915_READ(SDEISR) & bit;
 907 }
 908
 909 static const char *state_string(bool enabled)
 910 {
 911         return enabled ? "on" : "off";
 912 }
 913
 914 /* Only for pre-ILK configs */
 915 void assert_pll(struct drm_i915_private *dev_priv,
 916                 enum pipe pipe, bool state)
 917 {
 918         int reg;
 919         u32 val;
 920         bool cur_state;
 921
 922         reg = DPLL(pipe);
 923         val = I915_READ(reg);
 924         cur_state = !!(val & DPLL_VCO_ENABLE);
 925         WARN(cur_state != state,
 926              "PLL state assertion failure (expected %s, current %s)\n",
 927              state_string(state), state_string(cur_state));
 928 }
 929
 930 struct intel_shared_dpll *
 931 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 932 {
 933         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 934
 935         if (crtc->config.shared_dpll < 0)
 936                 return NULL;
 937
 938         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 939 }
 940
 941 /* For ILK+ */
 942 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 943                         struct intel_shared_dpll *pll,
 944                         bool state)
 945 {
 946         bool cur_state;
 947         struct intel_dpll_hw_state hw_state;
 948
 949         if (HAS_PCH_LPT(dev_priv->dev)) {
 950                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 951                 return;
 952         }
 953
 954         if (WARN (!pll,
 955                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 956                 return;
 957
 958         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 959         WARN(cur_state != state,
 960              "%s assertion failure (expected %s, current %s)\n",
 961              pll->name, state_string(state), state_string(cur_state));
 962 }
 963
 964 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 965                           enum pipe pipe, bool state)
 966 {
 967         int reg;
 968         u32 val;
 969         bool cur_state;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (HAS_DDI(dev_priv->dev)) {
 974                 /* DDI does not have a specific FDI_TX register */
 975                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 976                 val = I915_READ(reg);
 977                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 978         } else {
 979                 reg = FDI_TX_CTL(pipe);
 980                 val = I915_READ(reg);
 981                 cur_state = !!(val & FDI_TX_ENABLE);
 982         }
 983         WARN(cur_state != state,
 984              "FDI TX state assertion failure (expected %s, current %s)\n",
 985              state_string(state), state_string(cur_state));
 986 }
 987 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 988 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 989
 990 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 991                           enum pipe pipe, bool state)
 992 {
 993         int reg;
 994         u32 val;
 995         bool cur_state;
 996
 997         reg = FDI_RX_CTL(pipe);
 998         val = I915_READ(reg);
 999         cur_state = !!(val & FDI_RX_ENABLE);
1000         WARN(cur_state != state,
1001              "FDI RX state assertion failure (expected %s, current %s)\n",
1002              state_string(state), state_string(cur_state));
1003 }
1004 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008                                       enum pipe pipe)
1009 {
1010         int reg;
1011         u32 val;
1012
1013         /* ILK FDI PLL is always enabled */
1014         if (dev_priv->info->gen == 5)
1015                 return;
1016
1017         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1018         if (HAS_DDI(dev_priv->dev))
1019                 return;
1020
1021         reg = FDI_TX_CTL(pipe);
1022         val = I915_READ(reg);
1023         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024 }
1025
1026 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027                        enum pipe pipe, bool state)
1028 {
1029         int reg;
1030         u32 val;
1031         bool cur_state;
1032
1033         reg = FDI_RX_CTL(pipe);
1034         val = I915_READ(reg);
1035         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036         WARN(cur_state != state,
1037              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038              state_string(state), state_string(cur_state));
1039 }
1040
1041 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042                                   enum pipe pipe)
1043 {
1044         int pp_reg, lvds_reg;
1045         u32 val;
1046         enum pipe panel_pipe = PIPE_A;
1047         bool locked = true;
1048
1049         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050                 pp_reg = PCH_PP_CONTROL;
1051                 lvds_reg = PCH_LVDS;
1052         } else {
1053                 pp_reg = PP_CONTROL;
1054                 lvds_reg = LVDS;
1055         }
1056
1057         val = I915_READ(pp_reg);
1058         if (!(val & PANEL_POWER_ON) ||
1059             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060                 locked = false;
1061
1062         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063                 panel_pipe = PIPE_B;
1064
1065         WARN(panel_pipe == pipe && locked,
1066              "panel assertion failure, pipe %c regs locked\n",
1067              pipe_name(pipe));
1068 }
1069
1070 void assert_pipe(struct drm_i915_private *dev_priv,
1071                  enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         /* if we need the pipe A quirk it must be always on */
1080         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081                 state = true;
1082
1083         if (!intel_display_power_enabled(dev_priv->dev,
1084                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1085                 cur_state = false;
1086         } else {
1087                 reg = PIPECONF(cpu_transcoder);
1088                 val = I915_READ(reg);
1089                 cur_state = !!(val & PIPECONF_ENABLE);
1090         }
1091
1092         WARN(cur_state != state,
1093              "pipe %c assertion failure (expected %s, current %s)\n",
1094              pipe_name(pipe), state_string(state), state_string(cur_state));
1095 }
1096
1097 static void assert_plane(struct drm_i915_private *dev_priv,
1098                          enum plane plane, bool state)
1099 {
1100         int reg;
1101         u32 val;
1102         bool cur_state;
1103
1104         reg = DSPCNTR(plane);
1105         val = I915_READ(reg);
1106         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107         WARN(cur_state != state,
1108              "plane %c assertion failure (expected %s, current %s)\n",
1109              plane_name(plane), state_string(state), state_string(cur_state));
1110 }
1111
1112 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
1115 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116                                    enum pipe pipe)
1117 {
1118         struct drm_device *dev = dev_priv->dev;
1119         int reg, i;
1120         u32 val;
1121         int cur_pipe;
1122
1123         /* Primary planes are fixed to pipes on gen4+ */
1124         if (INTEL_INFO(dev)->gen >= 4) {
1125                 reg = DSPCNTR(pipe);
1126                 val = I915_READ(reg);
1127                 WARN((val & DISPLAY_PLANE_ENABLE),
1128                      "plane %c assertion failure, should be disabled but not\n",
1129                      plane_name(pipe));
1130                 return;
1131         }
1132
1133         /* Need to check both planes against the pipe */
1134         for_each_pipe(i) {
1135                 reg = DSPCNTR(i);
1136                 val = I915_READ(reg);
1137                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138                         DISPPLANE_SEL_PIPE_SHIFT;
1139                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1140                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141                      plane_name(i), pipe_name(pipe));
1142         }
1143 }
1144
1145 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146                                     enum pipe pipe)
1147 {
1148         struct drm_device *dev = dev_priv->dev;
1149         int reg, i;
1150         u32 val;
1151
1152         if (IS_VALLEYVIEW(dev)) {
1153                 for (i = 0; i < dev_priv->num_plane; i++) {
1154                         reg = SPCNTR(pipe, i);
1155                         val = I915_READ(reg);
1156                         WARN((val & SP_ENABLE),
1157                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158                              sprite_name(pipe, i), pipe_name(pipe));
1159                 }
1160         } else if (INTEL_INFO(dev)->gen >= 7) {
1161                 reg = SPRCTL(pipe);
1162                 val = I915_READ(reg);
1163                 WARN((val & SPRITE_ENABLE),
1164                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1165                      plane_name(pipe), pipe_name(pipe));
1166         } else if (INTEL_INFO(dev)->gen >= 5) {
1167                 reg = DVSCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN((val & DVS_ENABLE),
1170                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1171                      plane_name(pipe), pipe_name(pipe));
1172         }
1173 }
1174
1175 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176 {
1177         u32 val;
1178         bool enabled;
1179
1180         if (HAS_PCH_LPT(dev_priv->dev)) {
1181                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182                 return;
1183         }
1184
1185         val = I915_READ(PCH_DREF_CONTROL);
1186         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187                             DREF_SUPERSPREAD_SOURCE_MASK));
1188         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189 }
1190
1191 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192                                            enum pipe pipe)
1193 {
1194         int reg;
1195         u32 val;
1196         bool enabled;
1197
1198         reg = PCH_TRANSCONF(pipe);
1199         val = I915_READ(reg);
1200         enabled = !!(val & TRANS_ENABLE);
1201         WARN(enabled,
1202              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203              pipe_name(pipe));
1204 }
1205
1206 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207                             enum pipe pipe, u32 port_sel, u32 val)
1208 {
1209         if ((val & DP_PORT_EN) == 0)
1210                 return false;
1211
1212         if (HAS_PCH_CPT(dev_priv->dev)) {
1213                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216                         return false;
1217         } else {
1218                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219                         return false;
1220         }
1221         return true;
1222 }
1223
1224 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225                               enum pipe pipe, u32 val)
1226 {
1227         if ((val & SDVO_ENABLE) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1232                         return false;
1233         } else {
1234                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1235                         return false;
1236         }
1237         return true;
1238 }
1239
1240 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241                               enum pipe pipe, u32 val)
1242 {
1243         if ((val & LVDS_PORT_EN) == 0)
1244                 return false;
1245
1246         if (HAS_PCH_CPT(dev_priv->dev)) {
1247                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248                         return false;
1249         } else {
1250                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251                         return false;
1252         }
1253         return true;
1254 }
1255
1256 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257                               enum pipe pipe, u32 val)
1258 {
1259         if ((val & ADPA_DAC_ENABLE) == 0)
1260                 return false;
1261         if (HAS_PCH_CPT(dev_priv->dev)) {
1262                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263                         return false;
1264         } else {
1265                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266                         return false;
1267         }
1268         return true;
1269 }
1270
1271 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe, int reg, u32 port_sel)
1273 {
1274         u32 val = I915_READ(reg);
1275         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1276              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1277              reg, pipe_name(pipe));
1278
1279         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280              && (val & DP_PIPEB_SELECT),
1281              "IBX PCH dp port still using transcoder B\n");
1282 }
1283
1284 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285                                      enum pipe pipe, int reg)
1286 {
1287         u32 val = I915_READ(reg);
1288         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1289              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290              reg, pipe_name(pipe));
1291
1292         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1293              && (val & SDVO_PIPE_B_SELECT),
1294              "IBX PCH hdmi port still using transcoder B\n");
1295 }
1296
1297 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298                                       enum pipe pipe)
1299 {
1300         int reg;
1301         u32 val;
1302
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1306
1307         reg = PCH_ADPA;
1308         val = I915_READ(reg);
1309         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1310              "PCH VGA enabled on transcoder %c, should be disabled\n",
1311              pipe_name(pipe));
1312
1313         reg = PCH_LVDS;
1314         val = I915_READ(reg);
1315         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1316              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1317              pipe_name(pipe));
1318
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1322 }
1323
1324 static void vlv_enable_pll(struct intel_crtc *crtc)
1325 {
1326         struct drm_device *dev = crtc->base.dev;
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         int reg = DPLL(crtc->pipe);
1329         u32 dpll = crtc->config.dpll_hw_state.dpll;
1330
1331         assert_pipe_disabled(dev_priv, crtc->pipe);
1332
1333         /* No really, not for ILK+ */
1334         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1335
1336         /* PLL is protected by panel, make sure we can write it */
1337         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1338                 assert_panel_unlocked(dev_priv, crtc->pipe);
1339
1340         I915_WRITE(reg, dpll);
1341         POSTING_READ(reg);
1342         udelay(150);
1343
1344         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1345                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1346
1347         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1348         POSTING_READ(DPLL_MD(crtc->pipe));
1349
1350         /* We do this three times for luck */
1351         I915_WRITE(reg, dpll);
1352         POSTING_READ(reg);
1353         udelay(150); /* wait for warmup */
1354         I915_WRITE(reg, dpll);
1355         POSTING_READ(reg);
1356         udelay(150); /* wait for warmup */
1357         I915_WRITE(reg, dpll);
1358         POSTING_READ(reg);
1359         udelay(150); /* wait for warmup */
1360 }
1361
1362 static void i9xx_enable_pll(struct intel_crtc *crtc)
1363 {
1364         struct drm_device *dev = crtc->base.dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         int reg = DPLL(crtc->pipe);
1367         u32 dpll = crtc->config.dpll_hw_state.dpll;
1368
1369         assert_pipe_disabled(dev_priv, crtc->pipe);
1370
1371         /* No really, not for ILK+ */
1372         BUG_ON(dev_priv->info->gen >= 5);
1373
1374         /* PLL is protected by panel, make sure we can write it */
1375         if (IS_MOBILE(dev) && !IS_I830(dev))
1376                 assert_panel_unlocked(dev_priv, crtc->pipe);
1377
1378         I915_WRITE(reg, dpll);
1379
1380         /* Wait for the clocks to stabilize. */
1381         POSTING_READ(reg);
1382         udelay(150);
1383
1384         if (INTEL_INFO(dev)->gen >= 4) {
1385                 I915_WRITE(DPLL_MD(crtc->pipe),
1386                            crtc->config.dpll_hw_state.dpll_md);
1387         } else {
1388                 /* The pixel multiplier can only be updated once the
1389                  * DPLL is enabled and the clocks are stable.
1390                  *
1391                  * So write it again.
1392                  */
1393                 I915_WRITE(reg, dpll);
1394         }
1395
1396         /* We do this three times for luck */
1397         I915_WRITE(reg, dpll);
1398         POSTING_READ(reg);
1399         udelay(150); /* wait for warmup */
1400         I915_WRITE(reg, dpll);
1401         POSTING_READ(reg);
1402         udelay(150); /* wait for warmup */
1403         I915_WRITE(reg, dpll);
1404         POSTING_READ(reg);
1405         udelay(150); /* wait for warmup */
1406 }
1407
1408 /**
1409  * i9xx_disable_pll - disable a PLL
1410  * @dev_priv: i915 private structure
1411  * @pipe: pipe PLL to disable
1412  *
1413  * Disable the PLL for @pipe, making sure the pipe is off first.
1414  *
1415  * Note!  This is for pre-ILK only.
1416  */
1417 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1418 {
1419         /* Don't disable pipe A or pipe A PLLs if needed */
1420         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1421                 return;
1422
1423         /* Make sure the pipe isn't still relying on us */
1424         assert_pipe_disabled(dev_priv, pipe);
1425
1426         I915_WRITE(DPLL(pipe), 0);
1427         POSTING_READ(DPLL(pipe));
1428 }
1429
1430 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431 {
1432         u32 port_mask;
1433
1434         if (!port)
1435                 port_mask = DPLL_PORTB_READY_MASK;
1436         else
1437                 port_mask = DPLL_PORTC_READY_MASK;
1438
1439         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441                      'B' + port, I915_READ(DPLL(0)));
1442 }
1443
1444 /**
1445  * ironlake_enable_shared_dpll - enable PCH PLL
1446  * @dev_priv: i915 private structure
1447  * @pipe: pipe PLL to enable
1448  *
1449  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450  * drives the transcoder clock.
1451  */
1452 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1453 {
1454         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1455         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1456
1457         /* PCH PLLs only available on ILK, SNB and IVB */
1458         BUG_ON(dev_priv->info->gen < 5);
1459         if (WARN_ON(pll == NULL))
1460                 return;
1461
1462         if (WARN_ON(pll->refcount == 0))
1463                 return;
1464
1465         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466                       pll->name, pll->active, pll->on,
1467                       crtc->base.base.id);
1468
1469         if (pll->active++) {
1470                 WARN_ON(!pll->on);
1471                 assert_shared_dpll_enabled(dev_priv, pll);
1472                 return;
1473         }
1474         WARN_ON(pll->on);
1475
1476         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1477         pll->enable(dev_priv, pll);
1478         pll->on = true;
1479 }
1480
1481 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1482 {
1483         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1484         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1485
1486         /* PCH only available on ILK+ */
1487         BUG_ON(dev_priv->info->gen < 5);
1488         if (WARN_ON(pll == NULL))
1489                return;
1490
1491         if (WARN_ON(pll->refcount == 0))
1492                 return;
1493
1494         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495                       pll->name, pll->active, pll->on,
1496                       crtc->base.base.id);
1497
1498         if (WARN_ON(pll->active == 0)) {
1499                 assert_shared_dpll_disabled(dev_priv, pll);
1500                 return;
1501         }
1502
1503         assert_shared_dpll_enabled(dev_priv, pll);
1504         WARN_ON(!pll->on);
1505         if (--pll->active)
1506                 return;
1507
1508         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1509         pll->disable(dev_priv, pll);
1510         pll->on = false;
1511 }
1512
1513 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1514                                            enum pipe pipe)
1515 {
1516         struct drm_device *dev = dev_priv->dev;
1517         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519         uint32_t reg, val, pipeconf_val;
1520
1521         /* PCH only available on ILK+ */
1522         BUG_ON(dev_priv->info->gen < 5);
1523
1524         /* Make sure PCH DPLL is enabled */
1525         assert_shared_dpll_enabled(dev_priv,
1526                                    intel_crtc_to_shared_dpll(intel_crtc));
1527
1528         /* FDI must be feeding us bits for PCH ports */
1529         assert_fdi_tx_enabled(dev_priv, pipe);
1530         assert_fdi_rx_enabled(dev_priv, pipe);
1531
1532         if (HAS_PCH_CPT(dev)) {
1533                 /* Workaround: Set the timing override bit before enabling the
1534                  * pch transcoder. */
1535                 reg = TRANS_CHICKEN2(pipe);
1536                 val = I915_READ(reg);
1537                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1538                 I915_WRITE(reg, val);
1539         }
1540
1541         reg = PCH_TRANSCONF(pipe);
1542         val = I915_READ(reg);
1543         pipeconf_val = I915_READ(PIPECONF(pipe));
1544
1545         if (HAS_PCH_IBX(dev_priv->dev)) {
1546                 /*
1547                  * make the BPC in transcoder be consistent with
1548                  * that in pipeconf reg.
1549                  */
1550                 val &= ~PIPECONF_BPC_MASK;
1551                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1552         }
1553
1554         val &= ~TRANS_INTERLACE_MASK;
1555         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1556                 if (HAS_PCH_IBX(dev_priv->dev) &&
1557                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1558                         val |= TRANS_LEGACY_INTERLACED_ILK;
1559                 else
1560                         val |= TRANS_INTERLACED;
1561         else
1562                 val |= TRANS_PROGRESSIVE;
1563
1564         I915_WRITE(reg, val | TRANS_ENABLE);
1565         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1566                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1567 }
1568
1569 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1570                                       enum transcoder cpu_transcoder)
1571 {
1572         u32 val, pipeconf_val;
1573
1574         /* PCH only available on ILK+ */
1575         BUG_ON(dev_priv->info->gen < 5);
1576
1577         /* FDI must be feeding us bits for PCH ports */
1578         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1579         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1580
1581         /* Workaround: set timing override bit. */
1582         val = I915_READ(_TRANSA_CHICKEN2);
1583         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1584         I915_WRITE(_TRANSA_CHICKEN2, val);
1585
1586         val = TRANS_ENABLE;
1587         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1588
1589         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1590             PIPECONF_INTERLACED_ILK)
1591                 val |= TRANS_INTERLACED;
1592         else
1593                 val |= TRANS_PROGRESSIVE;
1594
1595         I915_WRITE(LPT_TRANSCONF, val);
1596         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1597                 DRM_ERROR("Failed to enable PCH transcoder\n");
1598 }
1599
1600 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1601                                             enum pipe pipe)
1602 {
1603         struct drm_device *dev = dev_priv->dev;
1604         uint32_t reg, val;
1605
1606         /* FDI relies on the transcoder */
1607         assert_fdi_tx_disabled(dev_priv, pipe);
1608         assert_fdi_rx_disabled(dev_priv, pipe);
1609
1610         /* Ports must be off as well */
1611         assert_pch_ports_disabled(dev_priv, pipe);
1612
1613         reg = PCH_TRANSCONF(pipe);
1614         val = I915_READ(reg);
1615         val &= ~TRANS_ENABLE;
1616         I915_WRITE(reg, val);
1617         /* wait for PCH transcoder off, transcoder state */
1618         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1619                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1620
1621         if (!HAS_PCH_IBX(dev)) {
1622                 /* Workaround: Clear the timing override chicken bit again. */
1623                 reg = TRANS_CHICKEN2(pipe);
1624                 val = I915_READ(reg);
1625                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1626                 I915_WRITE(reg, val);
1627         }
1628 }
1629
1630 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1631 {
1632         u32 val;
1633
1634         val = I915_READ(LPT_TRANSCONF);
1635         val &= ~TRANS_ENABLE;
1636         I915_WRITE(LPT_TRANSCONF, val);
1637         /* wait for PCH transcoder off, transcoder state */
1638         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1639                 DRM_ERROR("Failed to disable PCH transcoder\n");
1640
1641         /* Workaround: clear timing override bit. */
1642         val = I915_READ(_TRANSA_CHICKEN2);
1643         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1644         I915_WRITE(_TRANSA_CHICKEN2, val);
1645 }
1646
1647 /**
1648  * intel_enable_pipe - enable a pipe, asserting requirements
1649  * @dev_priv: i915 private structure
1650  * @pipe: pipe to enable
1651  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1652  *
1653  * Enable @pipe, making sure that various hardware specific requirements
1654  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1655  *
1656  * @pipe should be %PIPE_A or %PIPE_B.
1657  *
1658  * Will wait until the pipe is actually running (i.e. first vblank) before
1659  * returning.
1660  */
1661 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1662                               bool pch_port)
1663 {
1664         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665                                                                       pipe);
1666         enum pipe pch_transcoder;
1667         int reg;
1668         u32 val;
1669
1670         assert_planes_disabled(dev_priv, pipe);
1671         assert_sprites_disabled(dev_priv, pipe);
1672
1673         if (HAS_PCH_LPT(dev_priv->dev))
1674                 pch_transcoder = TRANSCODER_A;
1675         else
1676                 pch_transcoder = pipe;
1677
1678         /*
1679          * A pipe without a PLL won't actually be able to drive bits from
1680          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1681          * need the check.
1682          */
1683         if (!HAS_PCH_SPLIT(dev_priv->dev))
1684                 assert_pll_enabled(dev_priv, pipe);
1685         else {
1686                 if (pch_port) {
1687                         /* if driving the PCH, we need FDI enabled */
1688                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1689                         assert_fdi_tx_pll_enabled(dev_priv,
1690                                                   (enum pipe) cpu_transcoder);
1691                 }
1692                 /* FIXME: assert CPU port conditions for SNB+ */
1693         }
1694
1695         reg = PIPECONF(cpu_transcoder);
1696         val = I915_READ(reg);
1697         if (val & PIPECONF_ENABLE)
1698                 return;
1699
1700         I915_WRITE(reg, val | PIPECONF_ENABLE);
1701         intel_wait_for_vblank(dev_priv->dev, pipe);
1702 }
1703
1704 /**
1705  * intel_disable_pipe - disable a pipe, asserting requirements
1706  * @dev_priv: i915 private structure
1707  * @pipe: pipe to disable
1708  *
1709  * Disable @pipe, making sure that various hardware specific requirements
1710  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1711  *
1712  * @pipe should be %PIPE_A or %PIPE_B.
1713  *
1714  * Will wait until the pipe has shut down before returning.
1715  */
1716 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1717                                enum pipe pipe)
1718 {
1719         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1720                                                                       pipe);
1721         int reg;
1722         u32 val;
1723
1724         /*
1725          * Make sure planes won't keep trying to pump pixels to us,
1726          * or we might hang the display.
1727          */
1728         assert_planes_disabled(dev_priv, pipe);
1729         assert_sprites_disabled(dev_priv, pipe);
1730
1731         /* Don't disable pipe A or pipe A PLLs if needed */
1732         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1733                 return;
1734
1735         reg = PIPECONF(cpu_transcoder);
1736         val = I915_READ(reg);
1737         if ((val & PIPECONF_ENABLE) == 0)
1738                 return;
1739
1740         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1741         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1742 }
1743
1744 /*
1745  * Plane regs are double buffered, going from enabled->disabled needs a
1746  * trigger in order to latch.  The display address reg provides this.
1747  */
1748 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1749                                       enum plane plane)
1750 {
1751         if (dev_priv->info->gen >= 4)
1752                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1753         else
1754                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1755 }
1756
1757 /**
1758  * intel_enable_plane - enable a display plane on a given pipe
1759  * @dev_priv: i915 private structure
1760  * @plane: plane to enable
1761  * @pipe: pipe being fed
1762  *
1763  * Enable @plane on @pipe, making sure that @pipe is running first.
1764  */
1765 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1766                                enum plane plane, enum pipe pipe)
1767 {
1768         int reg;
1769         u32 val;
1770
1771         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772         assert_pipe_enabled(dev_priv, pipe);
1773
1774         reg = DSPCNTR(plane);
1775         val = I915_READ(reg);
1776         if (val & DISPLAY_PLANE_ENABLE)
1777                 return;
1778
1779         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1780         intel_flush_display_plane(dev_priv, plane);
1781         intel_wait_for_vblank(dev_priv->dev, pipe);
1782 }
1783
1784 /**
1785  * intel_disable_plane - disable a display plane
1786  * @dev_priv: i915 private structure
1787  * @plane: plane to disable
1788  * @pipe: pipe consuming the data
1789  *
1790  * Disable @plane; should be an independent operation.
1791  */
1792 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1793                                 enum plane plane, enum pipe pipe)
1794 {
1795         int reg;
1796         u32 val;
1797
1798         reg = DSPCNTR(plane);
1799         val = I915_READ(reg);
1800         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1801                 return;
1802
1803         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1804         intel_flush_display_plane(dev_priv, plane);
1805         intel_wait_for_vblank(dev_priv->dev, pipe);
1806 }
1807
1808 static bool need_vtd_wa(struct drm_device *dev)
1809 {
1810 #ifdef CONFIG_INTEL_IOMMU
1811         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1812                 return true;
1813 #endif
1814         return false;
1815 }
1816
1817 int
1818 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1819                            struct drm_i915_gem_object *obj,
1820                            struct intel_ring_buffer *pipelined)
1821 {
1822         struct drm_i915_private *dev_priv = dev->dev_private;
1823         u32 alignment;
1824         int ret;
1825
1826         switch (obj->tiling_mode) {
1827         case I915_TILING_NONE:
1828                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1829                         alignment = 128 * 1024;
1830                 else if (INTEL_INFO(dev)->gen >= 4)
1831                         alignment = 4 * 1024;
1832                 else
1833                         alignment = 64 * 1024;
1834                 break;
1835         case I915_TILING_X:
1836                 /* pin() will align the object as required by fence */
1837                 alignment = 0;
1838                 break;
1839         case I915_TILING_Y:
1840                 /* Despite that we check this in framebuffer_init userspace can
1841                  * screw us over and change the tiling after the fact. Only
1842                  * pinned buffers can't change their tiling. */
1843                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1844                 return -EINVAL;
1845         default:
1846                 BUG();
1847         }
1848
1849         /* Note that the w/a also requires 64 PTE of padding following the
1850          * bo. We currently fill all unused PTE with the shadow page and so
1851          * we should always have valid PTE following the scanout preventing
1852          * the VT-d warning.
1853          */
1854         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1855                 alignment = 256 * 1024;
1856
1857         dev_priv->mm.interruptible = false;
1858         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1859         if (ret)
1860                 goto err_interruptible;
1861
1862         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863          * fence, whereas 965+ only requires a fence if using
1864          * framebuffer compression.  For simplicity, we always install
1865          * a fence as the cost is not that onerous.
1866          */
1867         ret = i915_gem_object_get_fence(obj);
1868         if (ret)
1869                 goto err_unpin;
1870
1871         i915_gem_object_pin_fence(obj);
1872
1873         dev_priv->mm.interruptible = true;
1874         return 0;
1875
1876 err_unpin:
1877         i915_gem_object_unpin(obj);
1878 err_interruptible:
1879         dev_priv->mm.interruptible = true;
1880         return ret;
1881 }
1882
1883 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1884 {
1885         i915_gem_object_unpin_fence(obj);
1886         i915_gem_object_unpin(obj);
1887 }
1888
1889 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890  * is assumed to be a power-of-two. */
1891 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1892                                              unsigned int tiling_mode,
1893                                              unsigned int cpp,
1894                                              unsigned int pitch)
1895 {
1896         if (tiling_mode != I915_TILING_NONE) {
1897                 unsigned int tile_rows, tiles;
1898
1899                 tile_rows = *y / 8;
1900                 *y %= 8;
1901
1902                 tiles = *x / (512/cpp);
1903                 *x %= 512/cpp;
1904
1905                 return tile_rows * pitch * 8 + tiles * 4096;
1906         } else {
1907                 unsigned int offset;
1908
1909                 offset = *y * pitch + *x * cpp;
1910                 *y = 0;
1911                 *x = (offset & 4095) / cpp;
1912                 return offset & -4096;
1913         }
1914 }
1915
1916 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1917                              int x, int y)
1918 {
1919         struct drm_device *dev = crtc->dev;
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922         struct intel_framebuffer *intel_fb;
1923         struct drm_i915_gem_object *obj;
1924         int plane = intel_crtc->plane;
1925         unsigned long linear_offset;
1926         u32 dspcntr;
1927         u32 reg;
1928
1929         switch (plane) {
1930         case 0:
1931         case 1:
1932                 break;
1933         default:
1934                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1935                 return -EINVAL;
1936         }
1937
1938         intel_fb = to_intel_framebuffer(fb);
1939         obj = intel_fb->obj;
1940
1941         reg = DSPCNTR(plane);
1942         dspcntr = I915_READ(reg);
1943         /* Mask out pixel format bits in case we change it */
1944         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1945         switch (fb->pixel_format) {
1946         case DRM_FORMAT_C8:
1947                 dspcntr |= DISPPLANE_8BPP;
1948                 break;
1949         case DRM_FORMAT_XRGB1555:
1950         case DRM_FORMAT_ARGB1555:
1951                 dspcntr |= DISPPLANE_BGRX555;
1952                 break;
1953         case DRM_FORMAT_RGB565:
1954                 dspcntr |= DISPPLANE_BGRX565;
1955                 break;
1956         case DRM_FORMAT_XRGB8888:
1957         case DRM_FORMAT_ARGB8888:
1958                 dspcntr |= DISPPLANE_BGRX888;
1959                 break;
1960         case DRM_FORMAT_XBGR8888:
1961         case DRM_FORMAT_ABGR8888:
1962                 dspcntr |= DISPPLANE_RGBX888;
1963                 break;
1964         case DRM_FORMAT_XRGB2101010:
1965         case DRM_FORMAT_ARGB2101010:
1966                 dspcntr |= DISPPLANE_BGRX101010;
1967                 break;
1968         case DRM_FORMAT_XBGR2101010:
1969         case DRM_FORMAT_ABGR2101010:
1970                 dspcntr |= DISPPLANE_RGBX101010;
1971                 break;
1972         default:
1973                 BUG();
1974         }
1975
1976         if (INTEL_INFO(dev)->gen >= 4) {
1977                 if (obj->tiling_mode != I915_TILING_NONE)
1978                         dspcntr |= DISPPLANE_TILED;
1979                 else
1980                         dspcntr &= ~DISPPLANE_TILED;
1981         }
1982
1983         if (IS_G4X(dev))
1984                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1985
1986         I915_WRITE(reg, dspcntr);
1987
1988         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1989
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 intel_crtc->dspaddr_offset =
1992                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1993                                                        fb->bits_per_pixel / 8,
1994                                                        fb->pitches[0]);
1995                 linear_offset -= intel_crtc->dspaddr_offset;
1996         } else {
1997                 intel_crtc->dspaddr_offset = linear_offset;
1998         }
1999
2000         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2002                       fb->pitches[0]);
2003         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2004         if (INTEL_INFO(dev)->gen >= 4) {
2005                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2006                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2007                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2009         } else
2010                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2011         POSTING_READ(reg);
2012
2013         return 0;
2014 }
2015
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017                                  struct drm_framebuffer *fb, int x, int y)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022         struct intel_framebuffer *intel_fb;
2023         struct drm_i915_gem_object *obj;
2024         int plane = intel_crtc->plane;
2025         unsigned long linear_offset;
2026         u32 dspcntr;
2027         u32 reg;
2028
2029         switch (plane) {
2030         case 0:
2031         case 1:
2032         case 2:
2033                 break;
2034         default:
2035                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2036                 return -EINVAL;
2037         }
2038
2039         intel_fb = to_intel_framebuffer(fb);
2040         obj = intel_fb->obj;
2041
2042         reg = DSPCNTR(plane);
2043         dspcntr = I915_READ(reg);
2044         /* Mask out pixel format bits in case we change it */
2045         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2046         switch (fb->pixel_format) {
2047         case DRM_FORMAT_C8:
2048                 dspcntr |= DISPPLANE_8BPP;
2049                 break;
2050         case DRM_FORMAT_RGB565:
2051                 dspcntr |= DISPPLANE_BGRX565;
2052                 break;
2053         case DRM_FORMAT_XRGB8888:
2054         case DRM_FORMAT_ARGB8888:
2055                 dspcntr |= DISPPLANE_BGRX888;
2056                 break;
2057         case DRM_FORMAT_XBGR8888:
2058         case DRM_FORMAT_ABGR8888:
2059                 dspcntr |= DISPPLANE_RGBX888;
2060                 break;
2061         case DRM_FORMAT_XRGB2101010:
2062         case DRM_FORMAT_ARGB2101010:
2063                 dspcntr |= DISPPLANE_BGRX101010;
2064                 break;
2065         case DRM_FORMAT_XBGR2101010:
2066         case DRM_FORMAT_ABGR2101010:
2067                 dspcntr |= DISPPLANE_RGBX101010;
2068                 break;
2069         default:
2070                 BUG();
2071         }
2072
2073         if (obj->tiling_mode != I915_TILING_NONE)
2074                 dspcntr |= DISPPLANE_TILED;
2075         else
2076                 dspcntr &= ~DISPPLANE_TILED;
2077
2078         /* must disable */
2079         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2084         intel_crtc->dspaddr_offset =
2085                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2086                                                fb->bits_per_pixel / 8,
2087                                                fb->pitches[0]);
2088         linear_offset -= intel_crtc->dspaddr_offset;
2089
2090         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2092                       fb->pitches[0]);
2093         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2094         I915_MODIFY_DISPBASE(DSPSURF(plane),
2095                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2096         if (IS_HASWELL(dev)) {
2097                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2098         } else {
2099                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2100                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2101         }
2102         POSTING_READ(reg);
2103
2104         return 0;
2105 }
2106
2107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2108 static int
2109 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110                            int x, int y, enum mode_set_atomic state)
2111 {
2112         struct drm_device *dev = crtc->dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115         if (dev_priv->display.disable_fbc)
2116                 dev_priv->display.disable_fbc(dev);
2117         intel_increase_pllclock(crtc);
2118
2119         return dev_priv->display.update_plane(crtc, fb, x, y);
2120 }
2121
2122 void intel_display_handle_reset(struct drm_device *dev)
2123 {
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         struct drm_crtc *crtc;
2126
2127         /*
2128          * Flips in the rings have been nuked by the reset,
2129          * so complete all pending flips so that user space
2130          * will get its events and not get stuck.
2131          *
2132          * Also update the base address of all primary
2133          * planes to the the last fb to make sure we're
2134          * showing the correct fb after a reset.
2135          *
2136          * Need to make two loops over the crtcs so that we
2137          * don't try to grab a crtc mutex before the
2138          * pending_flip_queue really got woken up.
2139          */
2140
2141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2142                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143                 enum plane plane = intel_crtc->plane;
2144
2145                 intel_prepare_page_flip(dev, plane);
2146                 intel_finish_page_flip_plane(dev, plane);
2147         }
2148
2149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151
2152                 mutex_lock(&crtc->mutex);
2153                 if (intel_crtc->active)
2154                         dev_priv->display.update_plane(crtc, crtc->fb,
2155                                                        crtc->x, crtc->y);
2156                 mutex_unlock(&crtc->mutex);
2157         }
2158 }
2159
2160 static int
2161 intel_finish_fb(struct drm_framebuffer *old_fb)
2162 {
2163         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2164         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2165         bool was_interruptible = dev_priv->mm.interruptible;
2166         int ret;
2167
2168         /* Big Hammer, we also need to ensure that any pending
2169          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170          * current scanout is retired before unpinning the old
2171          * framebuffer.
2172          *
2173          * This should only fail upon a hung GPU, in which case we
2174          * can safely continue.
2175          */
2176         dev_priv->mm.interruptible = false;
2177         ret = i915_gem_object_finish_gpu(obj);
2178         dev_priv->mm.interruptible = was_interruptible;
2179
2180         return ret;
2181 }
2182
2183 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2184 {
2185         struct drm_device *dev = crtc->dev;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188
2189         if (!dev->primary->master)
2190                 return;
2191
2192         master_priv = dev->primary->master->driver_priv;
2193         if (!master_priv->sarea_priv)
2194                 return;
2195
2196         switch (intel_crtc->pipe) {
2197         case 0:
2198                 master_priv->sarea_priv->pipeA_x = x;
2199                 master_priv->sarea_priv->pipeA_y = y;
2200                 break;
2201         case 1:
2202                 master_priv->sarea_priv->pipeB_x = x;
2203                 master_priv->sarea_priv->pipeB_y = y;
2204                 break;
2205         default:
2206                 break;
2207         }
2208 }
2209
2210 static int
2211 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2212                     struct drm_framebuffer *fb)
2213 {
2214         struct drm_device *dev = crtc->dev;
2215         struct drm_i915_private *dev_priv = dev->dev_private;
2216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217         struct drm_framebuffer *old_fb;
2218         int ret;
2219
2220         /* no fb bound */
2221         if (!fb) {
2222                 DRM_ERROR("No FB bound\n");
2223                 return 0;
2224         }
2225
2226         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2227                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228                           plane_name(intel_crtc->plane),
2229                           INTEL_INFO(dev)->num_pipes);
2230                 return -EINVAL;
2231         }
2232
2233         mutex_lock(&dev->struct_mutex);
2234         ret = intel_pin_and_fence_fb_obj(dev,
2235                                          to_intel_framebuffer(fb)->obj,
2236                                          NULL);
2237         if (ret != 0) {
2238                 mutex_unlock(&dev->struct_mutex);
2239                 DRM_ERROR("pin & fence failed\n");
2240                 return ret;
2241         }
2242
2243         /* Update pipe size and adjust fitter if needed */
2244         if (i915_fastboot) {
2245                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2246                            ((crtc->mode.hdisplay - 1) << 16) |
2247                            (crtc->mode.vdisplay - 1));
2248                 if (!intel_crtc->config.pch_pfit.size &&
2249                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2250                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2251                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2253                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2254                 }
2255         }
2256
2257         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2258         if (ret) {
2259                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2260                 mutex_unlock(&dev->struct_mutex);
2261                 DRM_ERROR("failed to update base address\n");
2262                 return ret;
2263         }
2264
2265         old_fb = crtc->fb;
2266         crtc->fb = fb;
2267         crtc->x = x;
2268         crtc->y = y;
2269
2270         if (old_fb) {
2271                 if (intel_crtc->active && old_fb != fb)
2272                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2273                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2274         }
2275
2276         intel_update_fbc(dev);
2277         mutex_unlock(&dev->struct_mutex);
2278
2279         intel_crtc_update_sarea_pos(crtc, x, y);
2280
2281         return 0;
2282 }
2283
2284 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         u32 reg, temp;
2291
2292         /* enable normal train */
2293         reg = FDI_TX_CTL(pipe);
2294         temp = I915_READ(reg);
2295         if (IS_IVYBRIDGE(dev)) {
2296                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2297                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2298         } else {
2299                 temp &= ~FDI_LINK_TRAIN_NONE;
2300                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2301         }
2302         I915_WRITE(reg, temp);
2303
2304         reg = FDI_RX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         if (HAS_PCH_CPT(dev)) {
2307                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2308                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2309         } else {
2310                 temp &= ~FDI_LINK_TRAIN_NONE;
2311                 temp |= FDI_LINK_TRAIN_NONE;
2312         }
2313         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2314
2315         /* wait one idle pattern time */
2316         POSTING_READ(reg);
2317         udelay(1000);
2318
2319         /* IVB wants error correction enabled */
2320         if (IS_IVYBRIDGE(dev))
2321                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2322                            FDI_FE_ERRC_ENABLE);
2323 }
2324
2325 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2326 {
2327         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2328 }
2329
2330 static void ivb_modeset_global_resources(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *pipe_B_crtc =
2334                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2335         struct intel_crtc *pipe_C_crtc =
2336                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2337         uint32_t temp;
2338
2339         /*
2340          * When everything is off disable fdi C so that we could enable fdi B
2341          * with all lanes. Note that we don't care about enabled pipes without
2342          * an enabled pch encoder.
2343          */
2344         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2345             !pipe_has_enabled_pch(pipe_C_crtc)) {
2346                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2348
2349                 temp = I915_READ(SOUTH_CHICKEN1);
2350                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2351                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2352                 I915_WRITE(SOUTH_CHICKEN1, temp);
2353         }
2354 }
2355
2356 /* The FDI link training functions for ILK/Ibexpeak. */
2357 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         int plane = intel_crtc->plane;
2364         u32 reg, temp, tries;
2365
2366         /* FDI needs bits from pipe & plane first */
2367         assert_pipe_enabled(dev_priv, pipe);
2368         assert_plane_enabled(dev_priv, plane);
2369
2370         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2371            for train result */
2372         reg = FDI_RX_IMR(pipe);
2373         temp = I915_READ(reg);
2374         temp &= ~FDI_RX_SYMBOL_LOCK;
2375         temp &= ~FDI_RX_BIT_LOCK;
2376         I915_WRITE(reg, temp);
2377         I915_READ(reg);
2378         udelay(150);
2379
2380         /* enable CPU FDI TX and PCH FDI RX */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2384         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_1;
2387         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2388
2389         reg = FDI_RX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2394
2395         POSTING_READ(reg);
2396         udelay(150);
2397
2398         /* Ironlake workaround, enable clock pointer after FDI enable*/
2399         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401                    FDI_RX_PHASE_SYNC_POINTER_EN);
2402
2403         reg = FDI_RX_IIR(pipe);
2404         for (tries = 0; tries < 5; tries++) {
2405                 temp = I915_READ(reg);
2406                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408                 if ((temp & FDI_RX_BIT_LOCK)) {
2409                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2410                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2411                         break;
2412                 }
2413         }
2414         if (tries == 5)
2415                 DRM_ERROR("FDI train 1 fail!\n");
2416
2417         /* Train 2 */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~FDI_LINK_TRAIN_NONE;
2421         temp |= FDI_LINK_TRAIN_PATTERN_2;
2422         I915_WRITE(reg, temp);
2423
2424         reg = FDI_RX_CTL(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_2;
2428         I915_WRITE(reg, temp);
2429
2430         POSTING_READ(reg);
2431         udelay(150);
2432
2433         reg = FDI_RX_IIR(pipe);
2434         for (tries = 0; tries < 5; tries++) {
2435                 temp = I915_READ(reg);
2436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438                 if (temp & FDI_RX_SYMBOL_LOCK) {
2439                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2441                         break;
2442                 }
2443         }
2444         if (tries == 5)
2445                 DRM_ERROR("FDI train 2 fail!\n");
2446
2447         DRM_DEBUG_KMS("FDI train done\n");
2448
2449 }
2450
2451 static const int snb_b_fdi_train_param[] = {
2452         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2456 };
2457
2458 /* The FDI link training functions for SNB/Cougarpoint. */
2459 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         u32 reg, temp, i, retry;
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474
2475         POSTING_READ(reg);
2476         udelay(150);
2477
2478         /* enable CPU FDI TX and PCH FDI RX */
2479         reg = FDI_TX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2482         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486         /* SNB-B */
2487         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2488         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2489
2490         I915_WRITE(FDI_RX_MISC(pipe),
2491                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2501         }
2502         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_BIT_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 1 fail!\n");
2533
2534         /* Train 2 */
2535         reg = FDI_TX_CTL(pipe);
2536         temp = I915_READ(reg);
2537         temp &= ~FDI_LINK_TRAIN_NONE;
2538         temp |= FDI_LINK_TRAIN_PATTERN_2;
2539         if (IS_GEN6(dev)) {
2540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541                 /* SNB-B */
2542                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2543         }
2544         I915_WRITE(reg, temp);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554         }
2555         I915_WRITE(reg, temp);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         for (i = 0; i < 4; i++) {
2561                 reg = FDI_TX_CTL(pipe);
2562                 temp = I915_READ(reg);
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 temp |= snb_b_fdi_train_param[i];
2565                 I915_WRITE(reg, temp);
2566
2567                 POSTING_READ(reg);
2568                 udelay(500);
2569
2570                 for (retry = 0; retry < 5; retry++) {
2571                         reg = FDI_RX_IIR(pipe);
2572                         temp = I915_READ(reg);
2573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574                         if (temp & FDI_RX_SYMBOL_LOCK) {
2575                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2576                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577                                 break;
2578                         }
2579                         udelay(50);
2580                 }
2581                 if (retry < 5)
2582                         break;
2583         }
2584         if (i == 4)
2585                 DRM_ERROR("FDI train 2 fail!\n");
2586
2587         DRM_DEBUG_KMS("FDI train done.\n");
2588 }
2589
2590 /* Manual link training for Ivy Bridge A0 parts */
2591 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596         int pipe = intel_crtc->pipe;
2597         u32 reg, temp, i;
2598
2599         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600            for train result */
2601         reg = FDI_RX_IMR(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_RX_SYMBOL_LOCK;
2604         temp &= ~FDI_RX_BIT_LOCK;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2611                       I915_READ(FDI_RX_IIR(pipe)));
2612
2613         /* enable CPU FDI TX and PCH FDI RX */
2614         reg = FDI_TX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2617         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2618         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2619         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2620         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2622         temp |= FDI_COMPOSITE_SYNC;
2623         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625         I915_WRITE(FDI_RX_MISC(pipe),
2626                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_AUTO;
2631         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         temp |= FDI_COMPOSITE_SYNC;
2634         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636         POSTING_READ(reg);
2637         udelay(150);
2638
2639         for (i = 0; i < 4; i++) {
2640                 reg = FDI_TX_CTL(pipe);
2641                 temp = I915_READ(reg);
2642                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643                 temp |= snb_b_fdi_train_param[i];
2644                 I915_WRITE(reg, temp);
2645
2646                 POSTING_READ(reg);
2647                 udelay(500);
2648
2649                 reg = FDI_RX_IIR(pipe);
2650                 temp = I915_READ(reg);
2651                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653                 if (temp & FDI_RX_BIT_LOCK ||
2654                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2655                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2656                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2657                         break;
2658                 }
2659         }
2660         if (i == 4)
2661                 DRM_ERROR("FDI train 1 fail!\n");
2662
2663         /* Train 2 */
2664         reg = FDI_TX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2667         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2668         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2670         I915_WRITE(reg, temp);
2671
2672         reg = FDI_RX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(150);
2680
2681         for (i = 0; i < 4; i++) {
2682                 reg = FDI_TX_CTL(pipe);
2683                 temp = I915_READ(reg);
2684                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685                 temp |= snb_b_fdi_train_param[i];
2686                 I915_WRITE(reg, temp);
2687
2688                 POSTING_READ(reg);
2689                 udelay(500);
2690
2691                 reg = FDI_RX_IIR(pipe);
2692                 temp = I915_READ(reg);
2693                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695                 if (temp & FDI_RX_SYMBOL_LOCK) {
2696                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 2 fail!\n");
2703
2704         DRM_DEBUG_KMS("FDI train done.\n");
2705 }
2706
2707 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2708 {
2709         struct drm_device *dev = intel_crtc->base.dev;
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp;
2713
2714
2715         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2719         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2721         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(200);
2725
2726         /* Switch from Rawclk to PCDclk */
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp | FDI_PCDCLK);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Enable CPU FDI TX PLL, always on for Ironlake */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2737                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2738
2739                 POSTING_READ(reg);
2740                 udelay(100);
2741         }
2742 }
2743
2744 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         int pipe = intel_crtc->pipe;
2749         u32 reg, temp;
2750
2751         /* Switch from PCDclk to Rawclk */
2752         reg = FDI_RX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2755
2756         /* Disable CPU FDI TX PLL */
2757         reg = FDI_TX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2760
2761         POSTING_READ(reg);
2762         udelay(100);
2763
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2767
2768         /* Wait for the clocks to turn off. */
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799         }
2800
2801         /* still set train pattern 1 */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         if (HAS_PCH_CPT(dev)) {
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813         } else {
2814                 temp &= ~FDI_LINK_TRAIN_NONE;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816         }
2817         /* BPC in FDI rx is consistent with that in PIPECONF */
2818         temp &= ~(0x07 << 16);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824 }
2825
2826 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2831         unsigned long flags;
2832         bool pending;
2833
2834         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2835             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2836                 return false;
2837
2838         spin_lock_irqsave(&dev->event_lock, flags);
2839         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2840         spin_unlock_irqrestore(&dev->event_lock, flags);
2841
2842         return pending;
2843 }
2844
2845 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850         if (crtc->fb == NULL)
2851                 return;
2852
2853         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2854
2855         wait_event(dev_priv->pending_flip_queue,
2856                    !intel_crtc_has_pending_flip(crtc));
2857
2858         mutex_lock(&dev->struct_mutex);
2859         intel_finish_fb(crtc->fb);
2860         mutex_unlock(&dev->struct_mutex);
2861 }
2862
2863 /* Program iCLKIP clock to the desired frequency */
2864 static void lpt_program_iclkip(struct drm_crtc *crtc)
2865 {
2866         struct drm_device *dev = crtc->dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2869         u32 temp;
2870
2871         mutex_lock(&dev_priv->dpio_lock);
2872
2873         /* It is necessary to ungate the pixclk gate prior to programming
2874          * the divisors, and gate it back when it is done.
2875          */
2876         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2877
2878         /* Disable SSCCTL */
2879         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2880                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2881                                 SBI_SSCCTL_DISABLE,
2882                         SBI_ICLK);
2883
2884         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2885         if (crtc->mode.clock == 20000) {
2886                 auxdiv = 1;
2887                 divsel = 0x41;
2888                 phaseinc = 0x20;
2889         } else {
2890                 /* The iCLK virtual clock root frequency is in MHz,
2891                  * but the crtc->mode.clock in in KHz. To get the divisors,
2892                  * it is necessary to divide one by another, so we
2893                  * convert the virtual clock precision to KHz here for higher
2894                  * precision.
2895                  */
2896                 u32 iclk_virtual_root_freq = 172800 * 1000;
2897                 u32 iclk_pi_range = 64;
2898                 u32 desired_divisor, msb_divisor_value, pi_value;
2899
2900                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2901                 msb_divisor_value = desired_divisor / iclk_pi_range;
2902                 pi_value = desired_divisor % iclk_pi_range;
2903
2904                 auxdiv = 0;
2905                 divsel = msb_divisor_value - 2;
2906                 phaseinc = pi_value;
2907         }
2908
2909         /* This should not happen with any sane values */
2910         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2911                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2912         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2913                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2914
2915         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2916                         crtc->mode.clock,
2917                         auxdiv,
2918                         divsel,
2919                         phasedir,
2920                         phaseinc);
2921
2922         /* Program SSCDIVINTPHASE6 */
2923         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2924         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2925         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2926         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2927         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2928         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2929         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2930         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2931
2932         /* Program SSCAUXDIV */
2933         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2934         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2935         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2936         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2937
2938         /* Enable modulator and associated divider */
2939         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2940         temp &= ~SBI_SSCCTL_DISABLE;
2941         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2942
2943         /* Wait for initialization time */
2944         udelay(24);
2945
2946         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2947
2948         mutex_unlock(&dev_priv->dpio_lock);
2949 }
2950
2951 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2952                                                 enum pipe pch_transcoder)
2953 {
2954         struct drm_device *dev = crtc->base.dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2957
2958         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2959                    I915_READ(HTOTAL(cpu_transcoder)));
2960         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2961                    I915_READ(HBLANK(cpu_transcoder)));
2962         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2963                    I915_READ(HSYNC(cpu_transcoder)));
2964
2965         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2966                    I915_READ(VTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2968                    I915_READ(VBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2970                    I915_READ(VSYNC(cpu_transcoder)));
2971         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2972                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2973 }
2974
2975 /*
2976  * Enable PCH resources required for PCH ports:
2977  *   - PCH PLLs
2978  *   - FDI training & RX/TX
2979  *   - update transcoder timings
2980  *   - DP transcoding bits
2981  *   - transcoder
2982  */
2983 static void ironlake_pch_enable(struct drm_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         int pipe = intel_crtc->pipe;
2989         u32 reg, temp;
2990
2991         assert_pch_transcoder_disabled(dev_priv, pipe);
2992
2993         /* Write the TU size bits before fdi link training, so that error
2994          * detection works. */
2995         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2996                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2997
2998         /* For PCH output, training FDI link */
2999         dev_priv->display.fdi_link_train(crtc);
3000
3001         /* We need to program the right clock selection before writing the pixel
3002          * mutliplier into the DPLL. */
3003         if (HAS_PCH_CPT(dev)) {
3004                 u32 sel;
3005
3006                 temp = I915_READ(PCH_DPLL_SEL);
3007                 temp |= TRANS_DPLL_ENABLE(pipe);
3008                 sel = TRANS_DPLLB_SEL(pipe);
3009                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3010                         temp |= sel;
3011                 else
3012                         temp &= ~sel;
3013                 I915_WRITE(PCH_DPLL_SEL, temp);
3014         }
3015
3016         /* XXX: pch pll's can be enabled any time before we enable the PCH
3017          * transcoder, and we actually should do this to not upset any PCH
3018          * transcoder that already use the clock when we share it.
3019          *
3020          * Note that enable_shared_dpll tries to do the right thing, but
3021          * get_shared_dpll unconditionally resets the pll - we need that to have
3022          * the right LVDS enable sequence. */
3023         ironlake_enable_shared_dpll(intel_crtc);
3024
3025         /* set transcoder timing, panel must allow it */
3026         assert_panel_unlocked(dev_priv, pipe);
3027         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3028
3029         intel_fdi_normal_train(crtc);
3030
3031         /* For PCH DP, enable TRANS_DP_CTL */
3032         if (HAS_PCH_CPT(dev) &&
3033             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3035                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3036                 reg = TRANS_DP_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3039                           TRANS_DP_SYNC_MASK |
3040                           TRANS_DP_BPC_MASK);
3041                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042                          TRANS_DP_ENH_FRAMING);
3043                 temp |= bpc << 9; /* same format but at 11:9 */
3044
3045                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3046                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3048                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3049
3050                 switch (intel_trans_dp_port_sel(crtc)) {
3051                 case PCH_DP_B:
3052                         temp |= TRANS_DP_PORT_SEL_B;
3053                         break;
3054                 case PCH_DP_C:
3055                         temp |= TRANS_DP_PORT_SEL_C;
3056                         break;
3057                 case PCH_DP_D:
3058                         temp |= TRANS_DP_PORT_SEL_D;
3059                         break;
3060                 default:
3061                         BUG();
3062                 }
3063
3064                 I915_WRITE(reg, temp);
3065         }
3066
3067         ironlake_enable_pch_transcoder(dev_priv, pipe);
3068 }
3069
3070 static void lpt_pch_enable(struct drm_crtc *crtc)
3071 {
3072         struct drm_device *dev = crtc->dev;
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3076
3077         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3078
3079         lpt_program_iclkip(crtc);
3080
3081         /* Set transcoder timing. */
3082         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3083
3084         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3085 }
3086
3087 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3088 {
3089         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090
3091         if (pll == NULL)
3092                 return;
3093
3094         if (pll->refcount == 0) {
3095                 WARN(1, "bad %s refcount\n", pll->name);
3096                 return;
3097         }
3098
3099         if (--pll->refcount == 0) {
3100                 WARN_ON(pll->on);
3101                 WARN_ON(pll->active);
3102         }
3103
3104         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3105 }
3106
3107 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3108 {
3109         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3110         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3111         enum intel_dpll_id i;
3112
3113         if (pll) {
3114                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3115                               crtc->base.base.id, pll->name);
3116                 intel_put_shared_dpll(crtc);
3117         }
3118
3119         if (HAS_PCH_IBX(dev_priv->dev)) {
3120                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3121                 i = (enum intel_dpll_id) crtc->pipe;
3122                 pll = &dev_priv->shared_dplls[i];
3123
3124                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3125                               crtc->base.base.id, pll->name);
3126
3127                 goto found;
3128         }
3129
3130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3131                 pll = &dev_priv->shared_dplls[i];
3132
3133                 /* Only want to check enabled timings first */
3134                 if (pll->refcount == 0)
3135                         continue;
3136
3137                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3138                            sizeof(pll->hw_state)) == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3140                                       crtc->base.base.id,
3141                                       pll->name, pll->refcount, pll->active);
3142
3143                         goto found;
3144                 }
3145         }
3146
3147         /* Ok no matching timings, maybe there's a free one? */
3148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3149                 pll = &dev_priv->shared_dplls[i];
3150                 if (pll->refcount == 0) {
3151                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3152                                       crtc->base.base.id, pll->name);
3153                         goto found;
3154                 }
3155         }
3156
3157         return NULL;
3158
3159 found:
3160         crtc->config.shared_dpll = i;
3161         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3162                          pipe_name(crtc->pipe));
3163
3164         if (pll->active == 0) {
3165                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3166                        sizeof(pll->hw_state));
3167
3168                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3169                 WARN_ON(pll->on);
3170                 assert_shared_dpll_disabled(dev_priv, pll);
3171
3172                 pll->mode_set(dev_priv, pll);
3173         }
3174         pll->refcount++;
3175
3176         return pll;
3177 }
3178
3179 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         int dslreg = PIPEDSL(pipe);
3183         u32 temp;
3184
3185         temp = I915_READ(dslreg);
3186         udelay(500);
3187         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3190         }
3191 }
3192
3193 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->base.dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         int pipe = crtc->pipe;
3198
3199         if (crtc->config.pch_pfit.size) {
3200                 /* Force use of hard-coded filter coefficients
3201                  * as some pre-programmed values are broken,
3202                  * e.g. x201.
3203                  */
3204                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3205                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3206                                                  PF_PIPE_SEL_IVB(pipe));
3207                 else
3208                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3209                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3210                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3211         }
3212 }
3213
3214 static void intel_enable_planes(struct drm_crtc *crtc)
3215 {
3216         struct drm_device *dev = crtc->dev;
3217         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3218         struct intel_plane *intel_plane;
3219
3220         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3221                 if (intel_plane->pipe == pipe)
3222                         intel_plane_restore(&intel_plane->base);
3223 }
3224
3225 static void intel_disable_planes(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3229         struct intel_plane *intel_plane;
3230
3231         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3232                 if (intel_plane->pipe == pipe)
3233                         intel_plane_disable(&intel_plane->base);
3234 }
3235
3236 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         struct intel_encoder *encoder;
3242         int pipe = intel_crtc->pipe;
3243         int plane = intel_crtc->plane;
3244
3245         WARN_ON(!crtc->enabled);
3246
3247         if (intel_crtc->active)
3248                 return;
3249
3250         intel_crtc->active = true;
3251
3252         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3253         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3254
3255         intel_update_watermarks(dev);
3256
3257         for_each_encoder_on_crtc(dev, crtc, encoder)
3258                 if (encoder->pre_enable)
3259                         encoder->pre_enable(encoder);
3260
3261         if (intel_crtc->config.has_pch_encoder) {
3262                 /* Note: FDI PLL enabling _must_ be done before we enable the
3263                  * cpu pipes, hence this is separate from all the other fdi/pch
3264                  * enabling. */
3265                 ironlake_fdi_pll_enable(intel_crtc);
3266         } else {
3267                 assert_fdi_tx_disabled(dev_priv, pipe);
3268                 assert_fdi_rx_disabled(dev_priv, pipe);
3269         }
3270
3271         ironlake_pfit_enable(intel_crtc);
3272
3273         /*
3274          * On ILK+ LUT must be loaded before the pipe is running but with
3275          * clocks enabled
3276          */
3277         intel_crtc_load_lut(crtc);
3278
3279         intel_enable_pipe(dev_priv, pipe,
3280                           intel_crtc->config.has_pch_encoder);
3281         intel_enable_plane(dev_priv, plane, pipe);
3282         intel_enable_planes(crtc);
3283         intel_crtc_update_cursor(crtc, true);
3284
3285         if (intel_crtc->config.has_pch_encoder)
3286                 ironlake_pch_enable(crtc);
3287
3288         mutex_lock(&dev->struct_mutex);
3289         intel_update_fbc(dev);
3290         mutex_unlock(&dev->struct_mutex);
3291
3292         for_each_encoder_on_crtc(dev, crtc, encoder)
3293                 encoder->enable(encoder);
3294
3295         if (HAS_PCH_CPT(dev))
3296                 cpt_verify_modeset(dev, intel_crtc->pipe);
3297
3298         /*
3299          * There seems to be a race in PCH platform hw (at least on some
3300          * outputs) where an enabled pipe still completes any pageflip right
3301          * away (as if the pipe is off) instead of waiting for vblank. As soon
3302          * as the first vblank happend, everything works as expected. Hence just
3303          * wait for one vblank before returning to avoid strange things
3304          * happening.
3305          */
3306         intel_wait_for_vblank(dev, intel_crtc->pipe);
3307 }
3308
3309 /* IPS only exists on ULT machines and is tied to pipe A. */
3310 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3311 {
3312         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3313 }
3314
3315 static void hsw_enable_ips(struct intel_crtc *crtc)
3316 {
3317         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3318
3319         if (!crtc->config.ips_enabled)
3320                 return;
3321
3322         /* We can only enable IPS after we enable a plane and wait for a vblank.
3323          * We guarantee that the plane is enabled by calling intel_enable_ips
3324          * only after intel_enable_plane. And intel_enable_plane already waits
3325          * for a vblank, so all we need to do here is to enable the IPS bit. */
3326         assert_plane_enabled(dev_priv, crtc->plane);
3327         I915_WRITE(IPS_CTL, IPS_ENABLE);
3328 }
3329
3330 static void hsw_disable_ips(struct intel_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->base.dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335         if (!crtc->config.ips_enabled)
3336                 return;
3337
3338         assert_plane_enabled(dev_priv, crtc->plane);
3339         I915_WRITE(IPS_CTL, 0);
3340
3341         /* We need to wait for a vblank before we can disable the plane. */
3342         intel_wait_for_vblank(dev, crtc->pipe);
3343 }
3344
3345 static void haswell_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353
3354         WARN_ON(!crtc->enabled);
3355
3356         if (intel_crtc->active)
3357                 return;
3358
3359         intel_crtc->active = true;
3360
3361         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3362         if (intel_crtc->config.has_pch_encoder)
3363                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3364
3365         intel_update_watermarks(dev);
3366
3367         if (intel_crtc->config.has_pch_encoder)
3368                 dev_priv->display.fdi_link_train(crtc);
3369
3370         for_each_encoder_on_crtc(dev, crtc, encoder)
3371                 if (encoder->pre_enable)
3372                         encoder->pre_enable(encoder);
3373
3374         intel_ddi_enable_pipe_clock(intel_crtc);
3375
3376         ironlake_pfit_enable(intel_crtc);
3377
3378         /*
3379          * On ILK+ LUT must be loaded before the pipe is running but with
3380          * clocks enabled
3381          */
3382         intel_crtc_load_lut(crtc);
3383
3384         intel_ddi_set_pipe_settings(crtc);
3385         intel_ddi_enable_transcoder_func(crtc);
3386
3387         intel_enable_pipe(dev_priv, pipe,
3388                           intel_crtc->config.has_pch_encoder);
3389         intel_enable_plane(dev_priv, plane, pipe);
3390         intel_enable_planes(crtc);
3391         intel_crtc_update_cursor(crtc, true);
3392
3393         hsw_enable_ips(intel_crtc);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 lpt_pch_enable(crtc);
3397
3398         mutex_lock(&dev->struct_mutex);
3399         intel_update_fbc(dev);
3400         mutex_unlock(&dev->struct_mutex);
3401
3402         for_each_encoder_on_crtc(dev, crtc, encoder)
3403                 encoder->enable(encoder);
3404
3405         /*
3406          * There seems to be a race in PCH platform hw (at least on some
3407          * outputs) where an enabled pipe still completes any pageflip right
3408          * away (as if the pipe is off) instead of waiting for vblank. As soon
3409          * as the first vblank happend, everything works as expected. Hence just
3410          * wait for one vblank before returning to avoid strange things
3411          * happening.
3412          */
3413         intel_wait_for_vblank(dev, intel_crtc->pipe);
3414 }
3415
3416 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->base.dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         int pipe = crtc->pipe;
3421
3422         /* To avoid upsetting the power well on haswell only disable the pfit if
3423          * it's in use. The hw state code will make sure we get this right. */
3424         if (crtc->config.pch_pfit.size) {
3425                 I915_WRITE(PF_CTL(pipe), 0);
3426                 I915_WRITE(PF_WIN_POS(pipe), 0);
3427                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3428         }
3429 }
3430
3431 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436         struct intel_encoder *encoder;
3437         int pipe = intel_crtc->pipe;
3438         int plane = intel_crtc->plane;
3439         u32 reg, temp;
3440
3441
3442         if (!intel_crtc->active)
3443                 return;
3444
3445         for_each_encoder_on_crtc(dev, crtc, encoder)
3446                 encoder->disable(encoder);
3447
3448         intel_crtc_wait_for_pending_flips(crtc);
3449         drm_vblank_off(dev, pipe);
3450
3451         if (dev_priv->fbc.plane == plane)
3452                 intel_disable_fbc(dev);
3453
3454         intel_crtc_update_cursor(crtc, false);
3455         intel_disable_planes(crtc);
3456         intel_disable_plane(dev_priv, plane, pipe);
3457
3458         if (intel_crtc->config.has_pch_encoder)
3459                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3460
3461         intel_disable_pipe(dev_priv, pipe);
3462
3463         ironlake_pfit_disable(intel_crtc);
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 if (encoder->post_disable)
3467                         encoder->post_disable(encoder);
3468
3469         if (intel_crtc->config.has_pch_encoder) {
3470                 ironlake_fdi_disable(crtc);
3471
3472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3473                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3474
3475                 if (HAS_PCH_CPT(dev)) {
3476                         /* disable TRANS_DP_CTL */
3477                         reg = TRANS_DP_CTL(pipe);
3478                         temp = I915_READ(reg);
3479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3480                                   TRANS_DP_PORT_SEL_MASK);
3481                         temp |= TRANS_DP_PORT_SEL_NONE;
3482                         I915_WRITE(reg, temp);
3483
3484                         /* disable DPLL_SEL */
3485                         temp = I915_READ(PCH_DPLL_SEL);
3486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3487                         I915_WRITE(PCH_DPLL_SEL, temp);
3488                 }
3489
3490                 /* disable PCH DPLL */
3491                 intel_disable_shared_dpll(intel_crtc);
3492
3493                 ironlake_fdi_pll_disable(intel_crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void haswell_crtc_disable(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509         struct intel_encoder *encoder;
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3513
3514         if (!intel_crtc->active)
3515                 return;
3516
3517         for_each_encoder_on_crtc(dev, crtc, encoder)
3518                 encoder->disable(encoder);
3519
3520         intel_crtc_wait_for_pending_flips(crtc);
3521         drm_vblank_off(dev, pipe);
3522
3523         /* FBC must be disabled before disabling the plane on HSW. */
3524         if (dev_priv->fbc.plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         hsw_disable_ips(intel_crtc);
3528
3529         intel_crtc_update_cursor(crtc, false);
3530         intel_disable_planes(crtc);
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (intel_crtc->config.has_pch_encoder)
3534                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3538
3539         ironlake_pfit_disable(intel_crtc);
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_shared_dpll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         intel_ddi_put_crtc_pll(crtc);
3570 }
3571
3572 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573 {
3574         if (!enable && intel_crtc->overlay) {
3575                 struct drm_device *dev = intel_crtc->base.dev;
3576                 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578                 mutex_lock(&dev->struct_mutex);
3579                 dev_priv->mm.interruptible = false;
3580                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581                 dev_priv->mm.interruptible = true;
3582                 mutex_unlock(&dev->struct_mutex);
3583         }
3584
3585         /* Let userspace switch the overlay on again. In most cases userspace
3586          * has to recompute where to put it anyway.
3587          */
3588 }
3589
3590 /**
3591  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3592  * cursor plane briefly if not already running after enabling the display
3593  * plane.
3594  * This workaround avoids occasional blank screens when self refresh is
3595  * enabled.
3596  */
3597 static void
3598 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3599 {
3600         u32 cntl = I915_READ(CURCNTR(pipe));
3601
3602         if ((cntl & CURSOR_MODE) == 0) {
3603                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3604
3605                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3606                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3607                 intel_wait_for_vblank(dev_priv->dev, pipe);
3608                 I915_WRITE(CURCNTR(pipe), cntl);
3609                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3611         }
3612 }
3613
3614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->base.dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc_config *pipe_config = &crtc->config;
3619
3620         if (!crtc->config.gmch_pfit.control)
3621                 return;
3622
3623         /*
3624          * The panel fitter should only be adjusted whilst the pipe is disabled,
3625          * according to register description and PRM.
3626          */
3627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3628         assert_pipe_disabled(dev_priv, crtc->pipe);
3629
3630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3632
3633         /* Border color in case we don't scale up to the full screen. Black by
3634          * default, change to something else for debugging. */
3635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3636 }
3637
3638 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         struct intel_encoder *encoder;
3644         int pipe = intel_crtc->pipe;
3645         int plane = intel_crtc->plane;
3646
3647         WARN_ON(!crtc->enabled);
3648
3649         if (intel_crtc->active)
3650                 return;
3651
3652         intel_crtc->active = true;
3653         intel_update_watermarks(dev);
3654
3655         mutex_lock(&dev_priv->dpio_lock);
3656
3657         for_each_encoder_on_crtc(dev, crtc, encoder)
3658                 if (encoder->pre_pll_enable)
3659                         encoder->pre_pll_enable(encoder);
3660
3661         vlv_enable_pll(intel_crtc);
3662
3663         for_each_encoder_on_crtc(dev, crtc, encoder)
3664                 if (encoder->pre_enable)
3665                         encoder->pre_enable(encoder);
3666
3667         /* VLV wants encoder enabling _before_ the pipe is up. */
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->enable(encoder);
3670
3671         i9xx_pfit_enable(intel_crtc);
3672
3673         intel_crtc_load_lut(crtc);
3674
3675         intel_enable_pipe(dev_priv, pipe, false);
3676         intel_enable_plane(dev_priv, plane, pipe);
3677         intel_enable_planes(crtc);
3678         intel_crtc_update_cursor(crtc, true);
3679
3680         intel_update_fbc(dev);
3681
3682         mutex_unlock(&dev_priv->dpio_lock);
3683 }
3684
3685 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3686 {
3687         struct drm_device *dev = crtc->dev;
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690         struct intel_encoder *encoder;
3691         int pipe = intel_crtc->pipe;
3692         int plane = intel_crtc->plane;
3693
3694         WARN_ON(!crtc->enabled);
3695
3696         if (intel_crtc->active)
3697                 return;
3698
3699         intel_crtc->active = true;
3700         intel_update_watermarks(dev);
3701
3702         for_each_encoder_on_crtc(dev, crtc, encoder)
3703                 if (encoder->pre_enable)
3704                         encoder->pre_enable(encoder);
3705
3706         i9xx_enable_pll(intel_crtc);
3707
3708         i9xx_pfit_enable(intel_crtc);
3709
3710         intel_crtc_load_lut(crtc);
3711
3712         intel_enable_pipe(dev_priv, pipe, false);
3713         intel_enable_plane(dev_priv, plane, pipe);
3714         intel_enable_planes(crtc);
3715         /* The fixup needs to happen before cursor is enabled */
3716         if (IS_G4X(dev))
3717                 g4x_fixup_plane(dev_priv, pipe);
3718         intel_crtc_update_cursor(crtc, true);
3719
3720         /* Give the overlay scaler a chance to enable if it's on this pipe */
3721         intel_crtc_dpms_overlay(intel_crtc, true);
3722
3723         intel_update_fbc(dev);
3724
3725         for_each_encoder_on_crtc(dev, crtc, encoder)
3726                 encoder->enable(encoder);
3727 }
3728
3729 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3730 {
3731         struct drm_device *dev = crtc->base.dev;
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733
3734         if (!crtc->config.gmch_pfit.control)
3735                 return;
3736
3737         assert_pipe_disabled(dev_priv, crtc->pipe);
3738
3739         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3740                          I915_READ(PFIT_CONTROL));
3741         I915_WRITE(PFIT_CONTROL, 0);
3742 }
3743
3744 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3749         struct intel_encoder *encoder;
3750         int pipe = intel_crtc->pipe;
3751         int plane = intel_crtc->plane;
3752
3753         if (!intel_crtc->active)
3754                 return;
3755
3756         for_each_encoder_on_crtc(dev, crtc, encoder)
3757                 encoder->disable(encoder);
3758
3759         /* Give the overlay scaler a chance to disable if it's on this pipe */
3760         intel_crtc_wait_for_pending_flips(crtc);
3761         drm_vblank_off(dev, pipe);
3762
3763         if (dev_priv->fbc.plane == plane)
3764                 intel_disable_fbc(dev);
3765
3766         intel_crtc_dpms_overlay(intel_crtc, false);
3767         intel_crtc_update_cursor(crtc, false);
3768         intel_disable_planes(crtc);
3769         intel_disable_plane(dev_priv, plane, pipe);
3770
3771         intel_disable_pipe(dev_priv, pipe);
3772
3773         i9xx_pfit_disable(intel_crtc);
3774
3775         for_each_encoder_on_crtc(dev, crtc, encoder)
3776                 if (encoder->post_disable)
3777                         encoder->post_disable(encoder);
3778
3779         i9xx_disable_pll(dev_priv, pipe);
3780
3781         intel_crtc->active = false;
3782         intel_update_fbc(dev);
3783         intel_update_watermarks(dev);
3784 }
3785
3786 static void i9xx_crtc_off(struct drm_crtc *crtc)
3787 {
3788 }
3789
3790 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3791                                     bool enabled)
3792 {
3793         struct drm_device *dev = crtc->dev;
3794         struct drm_i915_master_private *master_priv;
3795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796         int pipe = intel_crtc->pipe;
3797
3798         if (!dev->primary->master)
3799                 return;
3800
3801         master_priv = dev->primary->master->driver_priv;
3802         if (!master_priv->sarea_priv)
3803                 return;
3804
3805         switch (pipe) {
3806         case 0:
3807                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3808                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3809                 break;
3810         case 1:
3811                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3812                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3813                 break;
3814         default:
3815                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3816                 break;
3817         }
3818 }
3819
3820 /**
3821  * Sets the power management mode of the pipe and plane.
3822  */
3823 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_encoder *intel_encoder;
3828         bool enable = false;
3829
3830         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3831                 enable |= intel_encoder->connectors_active;
3832
3833         if (enable)
3834                 dev_priv->display.crtc_enable(crtc);
3835         else
3836                 dev_priv->display.crtc_disable(crtc);
3837
3838         intel_crtc_update_sarea(crtc, enable);
3839 }
3840
3841 static void intel_crtc_disable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_connector *connector;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847
3848         /* crtc should still be enabled when we disable it. */
3849         WARN_ON(!crtc->enabled);
3850
3851         dev_priv->display.crtc_disable(crtc);
3852         intel_crtc->eld_vld = false;
3853         intel_crtc_update_sarea(crtc, false);
3854         dev_priv->display.off(crtc);
3855
3856         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3857         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3858
3859         if (crtc->fb) {
3860                 mutex_lock(&dev->struct_mutex);
3861                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3862                 mutex_unlock(&dev->struct_mutex);
3863                 crtc->fb = NULL;
3864         }
3865
3866         /* Update computed state. */
3867         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3868                 if (!connector->encoder || !connector->encoder->crtc)
3869                         continue;
3870
3871                 if (connector->encoder->crtc != crtc)
3872                         continue;
3873
3874                 connector->dpms = DRM_MODE_DPMS_OFF;
3875                 to_intel_encoder(connector->encoder)->connectors_active = false;
3876         }
3877 }
3878
3879 void intel_modeset_disable(struct drm_device *dev)
3880 {
3881         struct drm_crtc *crtc;
3882
3883         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3884                 if (crtc->enabled)
3885                         intel_crtc_disable(crtc);
3886         }
3887 }
3888
3889 void intel_encoder_destroy(struct drm_encoder *encoder)
3890 {
3891         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3892
3893         drm_encoder_cleanup(encoder);
3894         kfree(intel_encoder);
3895 }
3896
3897 /* Simple dpms helper for encodres with just one connector, no cloning and only
3898  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3899  * state of the entire output pipe. */
3900 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3901 {
3902         if (mode == DRM_MODE_DPMS_ON) {
3903                 encoder->connectors_active = true;
3904
3905                 intel_crtc_update_dpms(encoder->base.crtc);
3906         } else {
3907                 encoder->connectors_active = false;
3908
3909                 intel_crtc_update_dpms(encoder->base.crtc);
3910         }
3911 }
3912
3913 /* Cross check the actual hw state with our own modeset state tracking (and it's
3914  * internal consistency). */
3915 static void intel_connector_check_state(struct intel_connector *connector)
3916 {
3917         if (connector->get_hw_state(connector)) {
3918                 struct intel_encoder *encoder = connector->encoder;
3919                 struct drm_crtc *crtc;
3920                 bool encoder_enabled;
3921                 enum pipe pipe;
3922
3923                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3924                               connector->base.base.id,
3925                               drm_get_connector_name(&connector->base));
3926
3927                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3928                      "wrong connector dpms state\n");
3929                 WARN(connector->base.encoder != &encoder->base,
3930                      "active connector not linked to encoder\n");
3931                 WARN(!encoder->connectors_active,
3932                      "encoder->connectors_active not set\n");
3933
3934                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3935                 WARN(!encoder_enabled, "encoder not enabled\n");
3936                 if (WARN_ON(!encoder->base.crtc))
3937                         return;
3938
3939                 crtc = encoder->base.crtc;
3940
3941                 WARN(!crtc->enabled, "crtc not enabled\n");
3942                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3943                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3944                      "encoder active on the wrong pipe\n");
3945         }
3946 }
3947
3948 /* Even simpler default implementation, if there's really no special case to
3949  * consider. */
3950 void intel_connector_dpms(struct drm_connector *connector, int mode)
3951 {
3952         struct intel_encoder *encoder = intel_attached_encoder(connector);
3953
3954         /* All the simple cases only support two dpms states. */
3955         if (mode != DRM_MODE_DPMS_ON)
3956                 mode = DRM_MODE_DPMS_OFF;
3957
3958         if (mode == connector->dpms)
3959                 return;
3960
3961         connector->dpms = mode;
3962
3963         /* Only need to change hw state when actually enabled */
3964         if (encoder->base.crtc)
3965                 intel_encoder_dpms(encoder, mode);
3966         else
3967                 WARN_ON(encoder->connectors_active != false);
3968
3969         intel_modeset_check_state(connector->dev);
3970 }
3971
3972 /* Simple connector->get_hw_state implementation for encoders that support only
3973  * one connector and no cloning and hence the encoder state determines the state
3974  * of the connector. */
3975 bool intel_connector_get_hw_state(struct intel_connector *connector)
3976 {
3977         enum pipe pipe = 0;
3978         struct intel_encoder *encoder = connector->encoder;
3979
3980         return encoder->get_hw_state(encoder, &pipe);
3981 }
3982
3983 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3984                                      struct intel_crtc_config *pipe_config)
3985 {
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         struct intel_crtc *pipe_B_crtc =
3988                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3989
3990         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3991                       pipe_name(pipe), pipe_config->fdi_lanes);
3992         if (pipe_config->fdi_lanes > 4) {
3993                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3994                               pipe_name(pipe), pipe_config->fdi_lanes);
3995                 return false;
3996         }
3997
3998         if (IS_HASWELL(dev)) {
3999                 if (pipe_config->fdi_lanes > 2) {
4000                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4001                                       pipe_config->fdi_lanes);
4002                         return false;
4003                 } else {
4004                         return true;
4005                 }
4006         }
4007
4008         if (INTEL_INFO(dev)->num_pipes == 2)
4009                 return true;
4010
4011         /* Ivybridge 3 pipe is really complicated */
4012         switch (pipe) {
4013         case PIPE_A:
4014                 return true;
4015         case PIPE_B:
4016                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4017                     pipe_config->fdi_lanes > 2) {
4018                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4019                                       pipe_name(pipe), pipe_config->fdi_lanes);
4020                         return false;
4021                 }
4022                 return true;
4023         case PIPE_C:
4024                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4025                     pipe_B_crtc->config.fdi_lanes <= 2) {
4026                         if (pipe_config->fdi_lanes > 2) {
4027                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4028                                               pipe_name(pipe), pipe_config->fdi_lanes);
4029                                 return false;
4030                         }
4031                 } else {
4032                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4033                         return false;
4034                 }
4035                 return true;
4036         default:
4037                 BUG();
4038         }
4039 }
4040
4041 #define RETRY 1
4042 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4043                                        struct intel_crtc_config *pipe_config)
4044 {
4045         struct drm_device *dev = intel_crtc->base.dev;
4046         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047         int lane, link_bw, fdi_dotclock;
4048         bool setup_ok, needs_recompute = false;
4049
4050 retry:
4051         /* FDI is a binary signal running at ~2.7GHz, encoding
4052          * each output octet as 10 bits. The actual frequency
4053          * is stored as a divider into a 100MHz clock, and the
4054          * mode pixel clock is stored in units of 1KHz.
4055          * Hence the bw of each lane in terms of the mode signal
4056          * is:
4057          */
4058         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4059
4060         fdi_dotclock = adjusted_mode->clock;
4061         fdi_dotclock /= pipe_config->pixel_multiplier;
4062
4063         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4064                                            pipe_config->pipe_bpp);
4065
4066         pipe_config->fdi_lanes = lane;
4067
4068         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4069                                link_bw, &pipe_config->fdi_m_n);
4070
4071         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4072                                             intel_crtc->pipe, pipe_config);
4073         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4074                 pipe_config->pipe_bpp -= 2*3;
4075                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4076                               pipe_config->pipe_bpp);
4077                 needs_recompute = true;
4078                 pipe_config->bw_constrained = true;
4079
4080                 goto retry;
4081         }
4082
4083         if (needs_recompute)
4084                 return RETRY;
4085
4086         return setup_ok ? 0 : -EINVAL;
4087 }
4088
4089 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4090                                    struct intel_crtc_config *pipe_config)
4091 {
4092         pipe_config->ips_enabled = i915_enable_ips &&
4093                                    hsw_crtc_supports_ips(crtc) &&
4094                                    pipe_config->pipe_bpp == 24;
4095 }
4096
4097 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4098                                      struct intel_crtc_config *pipe_config)
4099 {
4100         struct drm_device *dev = crtc->base.dev;
4101         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4102
4103         if (HAS_PCH_SPLIT(dev)) {
4104                 /* FDI link clock is fixed at 2.7G */
4105                 if (pipe_config->requested_mode.clock * 3
4106                     > IRONLAKE_FDI_FREQ * 4)
4107                         return -EINVAL;
4108         }
4109
4110         /* All interlaced capable intel hw wants timings in frames. Note though
4111          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4112          * timings, so we need to be careful not to clobber these.*/
4113         if (!pipe_config->timings_set)
4114                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4115
4116         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4117          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4118          */
4119         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4120                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4121                 return -EINVAL;
4122
4123         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4124                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4125         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4126                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4127                  * for lvds. */
4128                 pipe_config->pipe_bpp = 8*3;
4129         }
4130
4131         if (HAS_IPS(dev))
4132                 hsw_compute_ips_config(crtc, pipe_config);
4133
4134         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4135          * clock survives for now. */
4136         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4137                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4138
4139         if (pipe_config->has_pch_encoder)
4140                 return ironlake_fdi_compute_config(crtc, pipe_config);
4141
4142         return 0;
4143 }
4144
4145 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4146 {
4147         return 400000; /* FIXME */
4148 }
4149
4150 static int i945_get_display_clock_speed(struct drm_device *dev)
4151 {
4152         return 400000;
4153 }
4154
4155 static int i915_get_display_clock_speed(struct drm_device *dev)
4156 {
4157         return 333000;
4158 }
4159
4160 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4161 {
4162         return 200000;
4163 }
4164
4165 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4166 {
4167         u16 gcfgc = 0;
4168
4169         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4170
4171         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4172                 return 133000;
4173         else {
4174                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4175                 case GC_DISPLAY_CLOCK_333_MHZ:
4176                         return 333000;
4177                 default:
4178                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4179                         return 190000;
4180                 }
4181         }
4182 }
4183
4184 static int i865_get_display_clock_speed(struct drm_device *dev)
4185 {
4186         return 266000;
4187 }
4188
4189 static int i855_get_display_clock_speed(struct drm_device *dev)
4190 {
4191         u16 hpllcc = 0;
4192         /* Assume that the hardware is in the high speed state.  This
4193          * should be the default.
4194          */
4195         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4196         case GC_CLOCK_133_200:
4197         case GC_CLOCK_100_200:
4198                 return 200000;
4199         case GC_CLOCK_166_250:
4200                 return 250000;
4201         case GC_CLOCK_100_133:
4202                 return 133000;
4203         }
4204
4205         /* Shouldn't happen */
4206         return 0;
4207 }
4208
4209 static int i830_get_display_clock_speed(struct drm_device *dev)
4210 {
4211         return 133000;
4212 }
4213
4214 static void
4215 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4216 {
4217         while (*num > DATA_LINK_M_N_MASK ||
4218                *den > DATA_LINK_M_N_MASK) {
4219                 *num >>= 1;
4220                 *den >>= 1;
4221         }
4222 }
4223
4224 static void compute_m_n(unsigned int m, unsigned int n,
4225                         uint32_t *ret_m, uint32_t *ret_n)
4226 {
4227         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4228         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4229         intel_reduce_m_n_ratio(ret_m, ret_n);
4230 }
4231
4232 void
4233 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4234                        int pixel_clock, int link_clock,
4235                        struct intel_link_m_n *m_n)
4236 {
4237         m_n->tu = 64;
4238
4239         compute_m_n(bits_per_pixel * pixel_clock,
4240                     link_clock * nlanes * 8,
4241                     &m_n->gmch_m, &m_n->gmch_n);
4242
4243         compute_m_n(pixel_clock, link_clock,
4244                     &m_n->link_m, &m_n->link_n);
4245 }
4246
4247 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4248 {
4249         if (i915_panel_use_ssc >= 0)
4250                 return i915_panel_use_ssc != 0;
4251         return dev_priv->vbt.lvds_use_ssc
4252                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4253 }
4254
4255 static int vlv_get_refclk(struct drm_crtc *crtc)
4256 {
4257         struct drm_device *dev = crtc->dev;
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         int refclk = 27000; /* for DP & HDMI */
4260
4261         return 100000; /* only one validated so far */
4262
4263         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4264                 refclk = 96000;
4265         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4266                 if (intel_panel_use_ssc(dev_priv))
4267                         refclk = 100000;
4268                 else
4269                         refclk = 96000;
4270         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4271                 refclk = 100000;
4272         }
4273
4274         return refclk;
4275 }
4276
4277 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4278 {
4279         struct drm_device *dev = crtc->dev;
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         int refclk;
4282
4283         if (IS_VALLEYVIEW(dev)) {
4284                 refclk = vlv_get_refclk(crtc);
4285         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4286             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4287                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4288                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4289                               refclk / 1000);
4290         } else if (!IS_GEN2(dev)) {
4291                 refclk = 96000;
4292         } else {
4293                 refclk = 48000;
4294         }
4295
4296         return refclk;
4297 }
4298
4299 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4300 {
4301         return (1 << dpll->n) << 16 | dpll->m2;
4302 }
4303
4304 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4305 {
4306         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4307 }
4308
4309 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4310                                      intel_clock_t *reduced_clock)
4311 {
4312         struct drm_device *dev = crtc->base.dev;
4313         struct drm_i915_private *dev_priv = dev->dev_private;
4314         int pipe = crtc->pipe;
4315         u32 fp, fp2 = 0;
4316
4317         if (IS_PINEVIEW(dev)) {
4318                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4319                 if (reduced_clock)
4320                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4321         } else {
4322                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4323                 if (reduced_clock)
4324                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4325         }
4326
4327         I915_WRITE(FP0(pipe), fp);
4328         crtc->config.dpll_hw_state.fp0 = fp;
4329
4330         crtc->lowfreq_avail = false;
4331         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4332             reduced_clock && i915_powersave) {
4333                 I915_WRITE(FP1(pipe), fp2);
4334                 crtc->config.dpll_hw_state.fp1 = fp2;
4335                 crtc->lowfreq_avail = true;
4336         } else {
4337                 I915_WRITE(FP1(pipe), fp);
4338                 crtc->config.dpll_hw_state.fp1 = fp;
4339         }
4340 }
4341
4342 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4343 {
4344         u32 reg_val;
4345
4346         /*
4347          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4348          * and set it to a reasonable value instead.
4349          */
4350         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4351         reg_val &= 0xffffff00;
4352         reg_val |= 0x00000030;
4353         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4354
4355         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4356         reg_val &= 0x8cffffff;
4357         reg_val = 0x8c000000;
4358         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4359
4360         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4361         reg_val &= 0xffffff00;
4362         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4363
4364         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4365         reg_val &= 0x00ffffff;
4366         reg_val |= 0xb0000000;
4367         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4368 }
4369
4370 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4371                                          struct intel_link_m_n *m_n)
4372 {
4373         struct drm_device *dev = crtc->base.dev;
4374         struct drm_i915_private *dev_priv = dev->dev_private;
4375         int pipe = crtc->pipe;
4376
4377         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4378         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4379         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4380         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4381 }
4382
4383 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4384                                          struct intel_link_m_n *m_n)
4385 {
4386         struct drm_device *dev = crtc->base.dev;
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         int pipe = crtc->pipe;
4389         enum transcoder transcoder = crtc->config.cpu_transcoder;
4390
4391         if (INTEL_INFO(dev)->gen >= 5) {
4392                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4393                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4394                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4395                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4396         } else {
4397                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4398                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4399                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4400                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4401         }
4402 }
4403
4404 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4405 {
4406         if (crtc->config.has_pch_encoder)
4407                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4408         else
4409                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4410 }
4411
4412 static void vlv_update_pll(struct intel_crtc *crtc)
4413 {
4414         struct drm_device *dev = crtc->base.dev;
4415         struct drm_i915_private *dev_priv = dev->dev_private;
4416         int pipe = crtc->pipe;
4417         u32 dpll, mdiv;
4418         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4419         bool is_hdmi;
4420         u32 coreclk, reg_val, dpll_md;
4421
4422         mutex_lock(&dev_priv->dpio_lock);
4423
4424         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4425
4426         bestn = crtc->config.dpll.n;
4427         bestm1 = crtc->config.dpll.m1;
4428         bestm2 = crtc->config.dpll.m2;
4429         bestp1 = crtc->config.dpll.p1;
4430         bestp2 = crtc->config.dpll.p2;
4431
4432         /* See eDP HDMI DPIO driver vbios notes doc */
4433
4434         /* PLL B needs special handling */
4435         if (pipe)
4436                 vlv_pllb_recal_opamp(dev_priv);
4437
4438         /* Set up Tx target for periodic Rcomp update */
4439         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4440
4441         /* Disable target IRef on PLL */
4442         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4443         reg_val &= 0x00ffffff;
4444         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4445
4446         /* Disable fast lock */
4447         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4448
4449         /* Set idtafcrecal before PLL is enabled */
4450         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4451         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4452         mdiv |= ((bestn << DPIO_N_SHIFT));
4453         mdiv |= (1 << DPIO_K_SHIFT);
4454
4455         /*
4456          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4457          * but we don't support that).
4458          * Note: don't use the DAC post divider as it seems unstable.
4459          */
4460         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4461         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4462
4463         mdiv |= DPIO_ENABLE_CALIBRATION;
4464         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4465
4466         /* Set HBR and RBR LPF coefficients */
4467         if (crtc->config.port_clock == 162000 ||
4468             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4469             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4470                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4471                                  0x009f0003);
4472         else
4473                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4474                                  0x00d0000f);
4475
4476         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4477             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4478                 /* Use SSC source */
4479                 if (!pipe)
4480                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4481                                          0x0df40000);
4482                 else
4483                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4484                                          0x0df70000);
4485         } else { /* HDMI or VGA */
4486                 /* Use bend source */
4487                 if (!pipe)
4488                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4489                                          0x0df70000);
4490                 else
4491                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4492                                          0x0df40000);
4493         }
4494
4495         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4496         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4497         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4498             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4499                 coreclk |= 0x01000000;
4500         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4501
4502         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4503
4504         /* Enable DPIO clock input */
4505         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4506                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4507         if (pipe)
4508                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4509
4510         dpll |= DPLL_VCO_ENABLE;
4511         crtc->config.dpll_hw_state.dpll = dpll;
4512
4513         dpll_md = (crtc->config.pixel_multiplier - 1)
4514                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4515         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4516
4517         if (crtc->config.has_dp_encoder)
4518                 intel_dp_set_m_n(crtc);
4519
4520         mutex_unlock(&dev_priv->dpio_lock);
4521 }
4522
4523 static void i9xx_update_pll(struct intel_crtc *crtc,
4524                             intel_clock_t *reduced_clock,
4525                             int num_connectors)
4526 {
4527         struct drm_device *dev = crtc->base.dev;
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529         u32 dpll;
4530         bool is_sdvo;
4531         struct dpll *clock = &crtc->config.dpll;
4532
4533         i9xx_update_pll_dividers(crtc, reduced_clock);
4534
4535         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4536                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4537
4538         dpll = DPLL_VGA_MODE_DIS;
4539
4540         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4541                 dpll |= DPLLB_MODE_LVDS;
4542         else
4543                 dpll |= DPLLB_MODE_DAC_SERIAL;
4544
4545         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4546                 dpll |= (crtc->config.pixel_multiplier - 1)
4547                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4548         }
4549
4550         if (is_sdvo)
4551                 dpll |= DPLL_SDVO_HIGH_SPEED;
4552
4553         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4554                 dpll |= DPLL_SDVO_HIGH_SPEED;
4555
4556         /* compute bitmask from p1 value */
4557         if (IS_PINEVIEW(dev))
4558                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4559         else {
4560                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4561                 if (IS_G4X(dev) && reduced_clock)
4562                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4563         }
4564         switch (clock->p2) {
4565         case 5:
4566                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4567                 break;
4568         case 7:
4569                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4570                 break;
4571         case 10:
4572                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4573                 break;
4574         case 14:
4575                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4576                 break;
4577         }
4578         if (INTEL_INFO(dev)->gen >= 4)
4579                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4580
4581         if (crtc->config.sdvo_tv_clock)
4582                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4583         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4584                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4585                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4586         else
4587                 dpll |= PLL_REF_INPUT_DREFCLK;
4588
4589         dpll |= DPLL_VCO_ENABLE;
4590         crtc->config.dpll_hw_state.dpll = dpll;
4591
4592         if (INTEL_INFO(dev)->gen >= 4) {
4593                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4594                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4595                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4596         }
4597
4598         if (crtc->config.has_dp_encoder)
4599                 intel_dp_set_m_n(crtc);
4600 }
4601
4602 static void i8xx_update_pll(struct intel_crtc *crtc,
4603                             intel_clock_t *reduced_clock,
4604                             int num_connectors)
4605 {
4606         struct drm_device *dev = crtc->base.dev;
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608         u32 dpll;
4609         struct dpll *clock = &crtc->config.dpll;
4610
4611         i9xx_update_pll_dividers(crtc, reduced_clock);
4612
4613         dpll = DPLL_VGA_MODE_DIS;
4614
4615         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4616                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4617         } else {
4618                 if (clock->p1 == 2)
4619                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4620                 else
4621                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4622                 if (clock->p2 == 4)
4623                         dpll |= PLL_P2_DIVIDE_BY_4;
4624         }
4625
4626         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4627                 dpll |= DPLL_DVO_2X_MODE;
4628
4629         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4630                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4631                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4632         else
4633                 dpll |= PLL_REF_INPUT_DREFCLK;
4634
4635         dpll |= DPLL_VCO_ENABLE;
4636         crtc->config.dpll_hw_state.dpll = dpll;
4637 }
4638
4639 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4640 {
4641         struct drm_device *dev = intel_crtc->base.dev;
4642         struct drm_i915_private *dev_priv = dev->dev_private;
4643         enum pipe pipe = intel_crtc->pipe;
4644         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4645         struct drm_display_mode *adjusted_mode =
4646                 &intel_crtc->config.adjusted_mode;
4647         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4648         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4649
4650         /* We need to be careful not to changed the adjusted mode, for otherwise
4651          * the hw state checker will get angry at the mismatch. */
4652         crtc_vtotal = adjusted_mode->crtc_vtotal;
4653         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4654
4655         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4656                 /* the chip adds 2 halflines automatically */
4657                 crtc_vtotal -= 1;
4658                 crtc_vblank_end -= 1;
4659                 vsyncshift = adjusted_mode->crtc_hsync_start
4660                              - adjusted_mode->crtc_htotal / 2;
4661         } else {
4662                 vsyncshift = 0;
4663         }
4664
4665         if (INTEL_INFO(dev)->gen > 3)
4666                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4667
4668         I915_WRITE(HTOTAL(cpu_transcoder),
4669                    (adjusted_mode->crtc_hdisplay - 1) |
4670                    ((adjusted_mode->crtc_htotal - 1) << 16));
4671         I915_WRITE(HBLANK(cpu_transcoder),
4672                    (adjusted_mode->crtc_hblank_start - 1) |
4673                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4674         I915_WRITE(HSYNC(cpu_transcoder),
4675                    (adjusted_mode->crtc_hsync_start - 1) |
4676                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4677
4678         I915_WRITE(VTOTAL(cpu_transcoder),
4679                    (adjusted_mode->crtc_vdisplay - 1) |
4680                    ((crtc_vtotal - 1) << 16));
4681         I915_WRITE(VBLANK(cpu_transcoder),
4682                    (adjusted_mode->crtc_vblank_start - 1) |
4683                    ((crtc_vblank_end - 1) << 16));
4684         I915_WRITE(VSYNC(cpu_transcoder),
4685                    (adjusted_mode->crtc_vsync_start - 1) |
4686                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4687
4688         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4689          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4690          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4691          * bits. */
4692         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4693             (pipe == PIPE_B || pipe == PIPE_C))
4694                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4695
4696         /* pipesrc controls the size that is scaled from, which should
4697          * always be the user's requested size.
4698          */
4699         I915_WRITE(PIPESRC(pipe),
4700                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4701 }
4702
4703 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4704                                    struct intel_crtc_config *pipe_config)
4705 {
4706         struct drm_device *dev = crtc->base.dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4709         uint32_t tmp;
4710
4711         tmp = I915_READ(HTOTAL(cpu_transcoder));
4712         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4713         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4714         tmp = I915_READ(HBLANK(cpu_transcoder));
4715         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4716         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4717         tmp = I915_READ(HSYNC(cpu_transcoder));
4718         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4719         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4720
4721         tmp = I915_READ(VTOTAL(cpu_transcoder));
4722         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4723         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4724         tmp = I915_READ(VBLANK(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4727         tmp = I915_READ(VSYNC(cpu_transcoder));
4728         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4729         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4730
4731         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4732                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4733                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4734                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4735         }
4736
4737         tmp = I915_READ(PIPESRC(crtc->pipe));
4738         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4739         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4740 }
4741
4742 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4743                                              struct intel_crtc_config *pipe_config)
4744 {
4745         struct drm_crtc *crtc = &intel_crtc->base;
4746
4747         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4748         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4749         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4750         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4751
4752         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4753         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4754         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4755         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4756
4757         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4758
4759         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4760         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4761 }
4762
4763 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4764 {
4765         struct drm_device *dev = intel_crtc->base.dev;
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         uint32_t pipeconf;
4768
4769         pipeconf = 0;
4770
4771         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4772                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4773                  * core speed.
4774                  *
4775                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4776                  * pipe == 0 check?
4777                  */
4778                 if (intel_crtc->config.requested_mode.clock >
4779                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4780                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4781         }
4782
4783         /* only g4x and later have fancy bpc/dither controls */
4784         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4785                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4786                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4787                         pipeconf |= PIPECONF_DITHER_EN |
4788                                     PIPECONF_DITHER_TYPE_SP;
4789
4790                 switch (intel_crtc->config.pipe_bpp) {
4791                 case 18:
4792                         pipeconf |= PIPECONF_6BPC;
4793                         break;
4794                 case 24:
4795                         pipeconf |= PIPECONF_8BPC;
4796                         break;
4797                 case 30:
4798                         pipeconf |= PIPECONF_10BPC;
4799                         break;
4800                 default:
4801                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4802                         BUG();
4803                 }
4804         }
4805
4806         if (HAS_PIPE_CXSR(dev)) {
4807                 if (intel_crtc->lowfreq_avail) {
4808                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4809                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4810                 } else {
4811                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4812                 }
4813         }
4814
4815         if (!IS_GEN2(dev) &&
4816             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4817                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4818         else
4819                 pipeconf |= PIPECONF_PROGRESSIVE;
4820
4821         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4822                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4823
4824         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4825         POSTING_READ(PIPECONF(intel_crtc->pipe));
4826 }
4827
4828 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4829                               int x, int y,
4830                               struct drm_framebuffer *fb)
4831 {
4832         struct drm_device *dev = crtc->dev;
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4836         int pipe = intel_crtc->pipe;
4837         int plane = intel_crtc->plane;
4838         int refclk, num_connectors = 0;
4839         intel_clock_t clock, reduced_clock;
4840         u32 dspcntr;
4841         bool ok, has_reduced_clock = false;
4842         bool is_lvds = false;
4843         struct intel_encoder *encoder;
4844         const intel_limit_t *limit;
4845         int ret;
4846
4847         for_each_encoder_on_crtc(dev, crtc, encoder) {
4848                 switch (encoder->type) {
4849                 case INTEL_OUTPUT_LVDS:
4850                         is_lvds = true;
4851                         break;
4852                 }
4853
4854                 num_connectors++;
4855         }
4856
4857         refclk = i9xx_get_refclk(crtc, num_connectors);
4858
4859         /*
4860          * Returns a set of divisors for the desired target clock with the given
4861          * refclk, or FALSE.  The returned values represent the clock equation:
4862          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4863          */
4864         limit = intel_limit(crtc, refclk);
4865         ok = dev_priv->display.find_dpll(limit, crtc,
4866                                          intel_crtc->config.port_clock,
4867                                          refclk, NULL, &clock);
4868         if (!ok && !intel_crtc->config.clock_set) {
4869                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4870                 return -EINVAL;
4871         }
4872
4873         /* Ensure that the cursor is valid for the new mode before changing... */
4874         intel_crtc_update_cursor(crtc, true);
4875
4876         if (is_lvds && dev_priv->lvds_downclock_avail) {
4877                 /*
4878                  * Ensure we match the reduced clock's P to the target clock.
4879                  * If the clocks don't match, we can't switch the display clock
4880                  * by using the FP0/FP1. In such case we will disable the LVDS
4881                  * downclock feature.
4882                 */
4883                 has_reduced_clock =
4884                         dev_priv->display.find_dpll(limit, crtc,
4885                                                     dev_priv->lvds_downclock,
4886                                                     refclk, &clock,
4887                                                     &reduced_clock);
4888         }
4889         /* Compat-code for transition, will disappear. */
4890         if (!intel_crtc->config.clock_set) {
4891                 intel_crtc->config.dpll.n = clock.n;
4892                 intel_crtc->config.dpll.m1 = clock.m1;
4893                 intel_crtc->config.dpll.m2 = clock.m2;
4894                 intel_crtc->config.dpll.p1 = clock.p1;
4895                 intel_crtc->config.dpll.p2 = clock.p2;
4896         }
4897
4898         if (IS_GEN2(dev))
4899                 i8xx_update_pll(intel_crtc,
4900                                 has_reduced_clock ? &reduced_clock : NULL,
4901                                 num_connectors);
4902         else if (IS_VALLEYVIEW(dev))
4903                 vlv_update_pll(intel_crtc);
4904         else
4905                 i9xx_update_pll(intel_crtc,
4906                                 has_reduced_clock ? &reduced_clock : NULL,
4907                                 num_connectors);
4908
4909         /* Set up the display plane register */
4910         dspcntr = DISPPLANE_GAMMA_ENABLE;
4911
4912         if (!IS_VALLEYVIEW(dev)) {
4913                 if (pipe == 0)
4914                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4915                 else
4916                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4917         }
4918
4919         intel_set_pipe_timings(intel_crtc);
4920
4921         /* pipesrc and dspsize control the size that is scaled from,
4922          * which should always be the user's requested size.
4923          */
4924         I915_WRITE(DSPSIZE(plane),
4925                    ((mode->vdisplay - 1) << 16) |
4926                    (mode->hdisplay - 1));
4927         I915_WRITE(DSPPOS(plane), 0);
4928
4929         i9xx_set_pipeconf(intel_crtc);
4930
4931         I915_WRITE(DSPCNTR(plane), dspcntr);
4932         POSTING_READ(DSPCNTR(plane));
4933
4934         ret = intel_pipe_set_base(crtc, x, y, fb);
4935
4936         intel_update_watermarks(dev);
4937
4938         return ret;
4939 }
4940
4941 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4942                                  struct intel_crtc_config *pipe_config)
4943 {
4944         struct drm_device *dev = crtc->base.dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         uint32_t tmp;
4947
4948         tmp = I915_READ(PFIT_CONTROL);
4949
4950         if (INTEL_INFO(dev)->gen < 4) {
4951                 if (crtc->pipe != PIPE_B)
4952                         return;
4953
4954                 /* gen2/3 store dither state in pfit control, needs to match */
4955                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4956         } else {
4957                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4958                         return;
4959         }
4960
4961         if (!(tmp & PFIT_ENABLE))
4962                 return;
4963
4964         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4965         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4966         if (INTEL_INFO(dev)->gen < 5)
4967                 pipe_config->gmch_pfit.lvds_border_bits =
4968                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4969 }
4970
4971 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4972                                  struct intel_crtc_config *pipe_config)
4973 {
4974         struct drm_device *dev = crtc->base.dev;
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976         uint32_t tmp;
4977
4978         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4979         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4980
4981         tmp = I915_READ(PIPECONF(crtc->pipe));
4982         if (!(tmp & PIPECONF_ENABLE))
4983                 return false;
4984
4985         intel_get_pipe_timings(crtc, pipe_config);
4986
4987         i9xx_get_pfit_config(crtc, pipe_config);
4988
4989         if (INTEL_INFO(dev)->gen >= 4) {
4990                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4991                 pipe_config->pixel_multiplier =
4992                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4993                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4994                 pipe_config->dpll_hw_state.dpll_md = tmp;
4995         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4996                 tmp = I915_READ(DPLL(crtc->pipe));
4997                 pipe_config->pixel_multiplier =
4998                         ((tmp & SDVO_MULTIPLIER_MASK)
4999                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5000         } else {
5001                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5002                  * port and will be fixed up in the encoder->get_config
5003                  * function. */
5004                 pipe_config->pixel_multiplier = 1;
5005         }
5006         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5007         if (!IS_VALLEYVIEW(dev)) {
5008                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5009                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5010         } else {
5011                 /* Mask out read-only status bits. */
5012                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5013                                                      DPLL_PORTC_READY_MASK |
5014                                                      DPLL_PORTB_READY_MASK);
5015         }
5016
5017         return true;
5018 }
5019
5020 static void ironlake_init_pch_refclk(struct drm_device *dev)
5021 {
5022         struct drm_i915_private *dev_priv = dev->dev_private;
5023         struct drm_mode_config *mode_config = &dev->mode_config;
5024         struct intel_encoder *encoder;
5025         u32 val, final;
5026         bool has_lvds = false;
5027         bool has_cpu_edp = false;
5028         bool has_panel = false;
5029         bool has_ck505 = false;
5030         bool can_ssc = false;
5031
5032         /* We need to take the global config into account */
5033         list_for_each_entry(encoder, &mode_config->encoder_list,
5034                             base.head) {
5035                 switch (encoder->type) {
5036                 case INTEL_OUTPUT_LVDS:
5037                         has_panel = true;
5038                         has_lvds = true;
5039                         break;
5040                 case INTEL_OUTPUT_EDP:
5041                         has_panel = true;
5042                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5043                                 has_cpu_edp = true;
5044                         break;
5045                 }
5046         }
5047
5048         if (HAS_PCH_IBX(dev)) {
5049                 has_ck505 = dev_priv->vbt.display_clock_mode;
5050                 can_ssc = has_ck505;
5051         } else {
5052                 has_ck505 = false;
5053                 can_ssc = true;
5054         }
5055
5056         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5057                       has_panel, has_lvds, has_ck505);
5058
5059         /* Ironlake: try to setup display ref clock before DPLL
5060          * enabling. This is only under driver's control after
5061          * PCH B stepping, previous chipset stepping should be
5062          * ignoring this setting.
5063          */
5064         val = I915_READ(PCH_DREF_CONTROL);
5065
5066         /* As we must carefully and slowly disable/enable each source in turn,
5067          * compute the final state we want first and check if we need to
5068          * make any changes at all.
5069          */
5070         final = val;
5071         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5072         if (has_ck505)
5073                 final |= DREF_NONSPREAD_CK505_ENABLE;
5074         else
5075                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5076
5077         final &= ~DREF_SSC_SOURCE_MASK;
5078         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5079         final &= ~DREF_SSC1_ENABLE;
5080
5081         if (has_panel) {
5082                 final |= DREF_SSC_SOURCE_ENABLE;
5083
5084                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5085                         final |= DREF_SSC1_ENABLE;
5086
5087                 if (has_cpu_edp) {
5088                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5090                         else
5091                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5092                 } else
5093                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5094         } else {
5095                 final |= DREF_SSC_SOURCE_DISABLE;
5096                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097         }
5098
5099         if (final == val)
5100                 return;
5101
5102         /* Always enable nonspread source */
5103         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5104
5105         if (has_ck505)
5106                 val |= DREF_NONSPREAD_CK505_ENABLE;
5107         else
5108                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5109
5110         if (has_panel) {
5111                 val &= ~DREF_SSC_SOURCE_MASK;
5112                 val |= DREF_SSC_SOURCE_ENABLE;
5113
5114                 /* SSC must be turned on before enabling the CPU output  */
5115                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5116                         DRM_DEBUG_KMS("Using SSC on panel\n");
5117                         val |= DREF_SSC1_ENABLE;
5118                 } else
5119                         val &= ~DREF_SSC1_ENABLE;
5120
5121                 /* Get SSC going before enabling the outputs */
5122                 I915_WRITE(PCH_DREF_CONTROL, val);
5123                 POSTING_READ(PCH_DREF_CONTROL);
5124                 udelay(200);
5125
5126                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5127
5128                 /* Enable CPU source on CPU attached eDP */
5129                 if (has_cpu_edp) {
5130                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5131                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5132                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5133                         }
5134                         else
5135                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5136                 } else
5137                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5138
5139                 I915_WRITE(PCH_DREF_CONTROL, val);
5140                 POSTING_READ(PCH_DREF_CONTROL);
5141                 udelay(200);
5142         } else {
5143                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5144
5145                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5146
5147                 /* Turn off CPU output */
5148                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5149
5150                 I915_WRITE(PCH_DREF_CONTROL, val);
5151                 POSTING_READ(PCH_DREF_CONTROL);
5152                 udelay(200);
5153
5154                 /* Turn off the SSC source */
5155                 val &= ~DREF_SSC_SOURCE_MASK;
5156                 val |= DREF_SSC_SOURCE_DISABLE;
5157
5158                 /* Turn off SSC1 */
5159                 val &= ~DREF_SSC1_ENABLE;
5160
5161                 I915_WRITE(PCH_DREF_CONTROL, val);
5162                 POSTING_READ(PCH_DREF_CONTROL);
5163                 udelay(200);
5164         }
5165
5166         BUG_ON(val != final);
5167 }
5168
5169 /*
5170  * Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O.
5171  * WaMPhyProgramming:hsw
5172  */
5173 static void lpt_init_pch_refclk(struct drm_device *dev)
5174 {
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176         struct drm_mode_config *mode_config = &dev->mode_config;
5177         struct intel_encoder *encoder;
5178         bool has_vga = false;
5179         bool is_sdv = false;
5180         u32 tmp;
5181
5182         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5183                 switch (encoder->type) {
5184                 case INTEL_OUTPUT_ANALOG:
5185                         has_vga = true;
5186                         break;
5187                 }
5188         }
5189
5190         if (!has_vga)
5191                 return;
5192
5193         mutex_lock(&dev_priv->dpio_lock);
5194
5195         /* XXX: Rip out SDV support once Haswell ships for real. */
5196         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5197                 is_sdv = true;
5198
5199         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5200         tmp &= ~SBI_SSCCTL_DISABLE;
5201         tmp |= SBI_SSCCTL_PATHALT;
5202         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5203
5204         udelay(24);
5205
5206         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5207         tmp &= ~SBI_SSCCTL_PATHALT;
5208         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5209
5210         if (!is_sdv) {
5211                 tmp = I915_READ(SOUTH_CHICKEN2);
5212                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5213                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5214
5215                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5216                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5217                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5218
5219                 tmp = I915_READ(SOUTH_CHICKEN2);
5220                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5221                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5222
5223                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5224                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5225                                        100))
5226                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5227         }
5228
5229         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5230         tmp &= ~(0xFF << 24);
5231         tmp |= (0x12 << 24);
5232         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5233
5234         if (is_sdv) {
5235                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5236                 tmp |= 0x7FFF;
5237                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5238         }
5239
5240         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5241         tmp |= (1 << 11);
5242         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5243
5244         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5245         tmp |= (1 << 11);
5246         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5247
5248         if (is_sdv) {
5249                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5250                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5251                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5252
5253                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5254                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5255                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5256
5257                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5258                 tmp |= (0x3F << 8);
5259                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5260
5261                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5262                 tmp |= (0x3F << 8);
5263                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5264         }
5265
5266         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5267         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5268         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5269
5270         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5271         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5272         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5273
5274         if (!is_sdv) {
5275                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5276                 tmp &= ~(7 << 13);
5277                 tmp |= (5 << 13);
5278                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5279
5280                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5281                 tmp &= ~(7 << 13);
5282                 tmp |= (5 << 13);
5283                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5284         }
5285
5286         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5287         tmp &= ~0xFF;
5288         tmp |= 0x1C;
5289         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5290
5291         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5292         tmp &= ~0xFF;
5293         tmp |= 0x1C;
5294         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5295
5296         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5297         tmp &= ~(0xFF << 16);
5298         tmp |= (0x1C << 16);
5299         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5300
5301         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5302         tmp &= ~(0xFF << 16);
5303         tmp |= (0x1C << 16);
5304         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5305
5306         if (!is_sdv) {
5307                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5308                 tmp |= (1 << 27);
5309                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5310
5311                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5312                 tmp |= (1 << 27);
5313                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5314
5315                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5316                 tmp &= ~(0xF << 28);
5317                 tmp |= (4 << 28);
5318                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5319
5320                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5321                 tmp &= ~(0xF << 28);
5322                 tmp |= (4 << 28);
5323                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5324         }
5325
5326         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5327         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5328         tmp |= SBI_DBUFF0_ENABLE;
5329         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5330
5331         mutex_unlock(&dev_priv->dpio_lock);
5332 }
5333
5334 /*
5335  * Initialize reference clocks when the driver loads
5336  */
5337 void intel_init_pch_refclk(struct drm_device *dev)
5338 {
5339         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5340                 ironlake_init_pch_refclk(dev);
5341         else if (HAS_PCH_LPT(dev))
5342                 lpt_init_pch_refclk(dev);
5343 }
5344
5345 static int ironlake_get_refclk(struct drm_crtc *crtc)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349         struct intel_encoder *encoder;
5350         int num_connectors = 0;
5351         bool is_lvds = false;
5352
5353         for_each_encoder_on_crtc(dev, crtc, encoder) {
5354                 switch (encoder->type) {
5355                 case INTEL_OUTPUT_LVDS:
5356                         is_lvds = true;
5357                         break;
5358                 }
5359                 num_connectors++;
5360         }
5361
5362         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5363                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5364                               dev_priv->vbt.lvds_ssc_freq);
5365                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5366         }
5367
5368         return 120000;
5369 }
5370
5371 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5372 {
5373         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         int pipe = intel_crtc->pipe;
5376         uint32_t val;
5377
5378         val = 0;
5379
5380         switch (intel_crtc->config.pipe_bpp) {
5381         case 18:
5382                 val |= PIPECONF_6BPC;
5383                 break;
5384         case 24:
5385                 val |= PIPECONF_8BPC;
5386                 break;
5387         case 30:
5388                 val |= PIPECONF_10BPC;
5389                 break;
5390         case 36:
5391                 val |= PIPECONF_12BPC;
5392                 break;
5393         default:
5394                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5395                 BUG();
5396         }
5397
5398         if (intel_crtc->config.dither)
5399                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5400
5401         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5402                 val |= PIPECONF_INTERLACED_ILK;
5403         else
5404                 val |= PIPECONF_PROGRESSIVE;
5405
5406         if (intel_crtc->config.limited_color_range)
5407                 val |= PIPECONF_COLOR_RANGE_SELECT;
5408
5409         I915_WRITE(PIPECONF(pipe), val);
5410         POSTING_READ(PIPECONF(pipe));
5411 }
5412
5413 /*
5414  * Set up the pipe CSC unit.
5415  *
5416  * Currently only full range RGB to limited range RGB conversion
5417  * is supported, but eventually this should handle various
5418  * RGB<->YCbCr scenarios as well.
5419  */
5420 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5421 {
5422         struct drm_device *dev = crtc->dev;
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5425         int pipe = intel_crtc->pipe;
5426         uint16_t coeff = 0x7800; /* 1.0 */
5427
5428         /*
5429          * TODO: Check what kind of values actually come out of the pipe
5430          * with these coeff/postoff values and adjust to get the best
5431          * accuracy. Perhaps we even need to take the bpc value into
5432          * consideration.
5433          */
5434
5435         if (intel_crtc->config.limited_color_range)
5436                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5437
5438         /*
5439          * GY/GU and RY/RU should be the other way around according
5440          * to BSpec, but reality doesn't agree. Just set them up in
5441          * a way that results in the correct picture.
5442          */
5443         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5444         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5445
5446         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5447         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5448
5449         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5450         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5451
5452         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5453         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5454         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5455
5456         if (INTEL_INFO(dev)->gen > 6) {
5457                 uint16_t postoff = 0;
5458
5459                 if (intel_crtc->config.limited_color_range)
5460                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5461
5462                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5463                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5464                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5465
5466                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5467         } else {
5468                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5469
5470                 if (intel_crtc->config.limited_color_range)
5471                         mode |= CSC_BLACK_SCREEN_OFFSET;
5472
5473                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5474         }
5475 }
5476
5477 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5478 {
5479         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5481         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5482         uint32_t val;
5483
5484         val = 0;
5485
5486         if (intel_crtc->config.dither)
5487                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5488
5489         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5490                 val |= PIPECONF_INTERLACED_ILK;
5491         else
5492                 val |= PIPECONF_PROGRESSIVE;
5493
5494         I915_WRITE(PIPECONF(cpu_transcoder), val);
5495         POSTING_READ(PIPECONF(cpu_transcoder));
5496
5497         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5498         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5499 }
5500
5501 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5502                                     intel_clock_t *clock,
5503                                     bool *has_reduced_clock,
5504                                     intel_clock_t *reduced_clock)
5505 {
5506         struct drm_device *dev = crtc->dev;
5507         struct drm_i915_private *dev_priv = dev->dev_private;
5508         struct intel_encoder *intel_encoder;
5509         int refclk;
5510         const intel_limit_t *limit;
5511         bool ret, is_lvds = false;
5512
5513         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5514                 switch (intel_encoder->type) {
5515                 case INTEL_OUTPUT_LVDS:
5516                         is_lvds = true;
5517                         break;
5518                 }
5519         }
5520
5521         refclk = ironlake_get_refclk(crtc);
5522
5523         /*
5524          * Returns a set of divisors for the desired target clock with the given
5525          * refclk, or FALSE.  The returned values represent the clock equation:
5526          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5527          */
5528         limit = intel_limit(crtc, refclk);
5529         ret = dev_priv->display.find_dpll(limit, crtc,
5530                                           to_intel_crtc(crtc)->config.port_clock,
5531                                           refclk, NULL, clock);
5532         if (!ret)
5533                 return false;
5534
5535         if (is_lvds && dev_priv->lvds_downclock_avail) {
5536                 /*
5537                  * Ensure we match the reduced clock's P to the target clock.
5538                  * If the clocks don't match, we can't switch the display clock
5539                  * by using the FP0/FP1. In such case we will disable the LVDS
5540                  * downclock feature.
5541                 */
5542                 *has_reduced_clock =
5543                         dev_priv->display.find_dpll(limit, crtc,
5544                                                     dev_priv->lvds_downclock,
5545                                                     refclk, clock,
5546                                                     reduced_clock);
5547         }
5548
5549         return true;
5550 }
5551
5552 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5553 {
5554         struct drm_i915_private *dev_priv = dev->dev_private;
5555         uint32_t temp;
5556
5557         temp = I915_READ(SOUTH_CHICKEN1);
5558         if (temp & FDI_BC_BIFURCATION_SELECT)
5559                 return;
5560
5561         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5562         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5563
5564         temp |= FDI_BC_BIFURCATION_SELECT;
5565         DRM_DEBUG_KMS("enabling fdi C rx\n");
5566         I915_WRITE(SOUTH_CHICKEN1, temp);
5567         POSTING_READ(SOUTH_CHICKEN1);
5568 }
5569
5570 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5571 {
5572         struct drm_device *dev = intel_crtc->base.dev;
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574
5575         switch (intel_crtc->pipe) {
5576         case PIPE_A:
5577                 break;
5578         case PIPE_B:
5579                 if (intel_crtc->config.fdi_lanes > 2)
5580                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5581                 else
5582                         cpt_enable_fdi_bc_bifurcation(dev);
5583
5584                 break;
5585         case PIPE_C:
5586                 cpt_enable_fdi_bc_bifurcation(dev);
5587
5588                 break;
5589         default:
5590                 BUG();
5591         }
5592 }
5593
5594 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5595 {
5596         /*
5597          * Account for spread spectrum to avoid
5598          * oversubscribing the link. Max center spread
5599          * is 2.5%; use 5% for safety's sake.
5600          */
5601         u32 bps = target_clock * bpp * 21 / 20;
5602         return bps / (link_bw * 8) + 1;
5603 }
5604
5605 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5606 {
5607         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5608 }
5609
5610 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5611                                       u32 *fp,
5612                                       intel_clock_t *reduced_clock, u32 *fp2)
5613 {
5614         struct drm_crtc *crtc = &intel_crtc->base;
5615         struct drm_device *dev = crtc->dev;
5616         struct drm_i915_private *dev_priv = dev->dev_private;
5617         struct intel_encoder *intel_encoder;
5618         uint32_t dpll;
5619         int factor, num_connectors = 0;
5620         bool is_lvds = false, is_sdvo = false;
5621
5622         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5623                 switch (intel_encoder->type) {
5624                 case INTEL_OUTPUT_LVDS:
5625                         is_lvds = true;
5626                         break;
5627                 case INTEL_OUTPUT_SDVO:
5628                 case INTEL_OUTPUT_HDMI:
5629                         is_sdvo = true;
5630                         break;
5631                 }
5632
5633                 num_connectors++;
5634         }
5635
5636         /* Enable autotuning of the PLL clock (if permissible) */
5637         factor = 21;
5638         if (is_lvds) {
5639                 if ((intel_panel_use_ssc(dev_priv) &&
5640                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5641                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5642                         factor = 25;
5643         } else if (intel_crtc->config.sdvo_tv_clock)
5644                 factor = 20;
5645
5646         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5647                 *fp |= FP_CB_TUNE;
5648
5649         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5650                 *fp2 |= FP_CB_TUNE;
5651
5652         dpll = 0;
5653
5654         if (is_lvds)
5655                 dpll |= DPLLB_MODE_LVDS;
5656         else
5657                 dpll |= DPLLB_MODE_DAC_SERIAL;
5658
5659         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5660                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5661
5662         if (is_sdvo)
5663                 dpll |= DPLL_SDVO_HIGH_SPEED;
5664         if (intel_crtc->config.has_dp_encoder)
5665                 dpll |= DPLL_SDVO_HIGH_SPEED;
5666
5667         /* compute bitmask from p1 value */
5668         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5669         /* also FPA1 */
5670         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5671
5672         switch (intel_crtc->config.dpll.p2) {
5673         case 5:
5674                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5675                 break;
5676         case 7:
5677                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5678                 break;
5679         case 10:
5680                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5681                 break;
5682         case 14:
5683                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5684                 break;
5685         }
5686
5687         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5688                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5689         else
5690                 dpll |= PLL_REF_INPUT_DREFCLK;
5691
5692         return dpll | DPLL_VCO_ENABLE;
5693 }
5694
5695 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5696                                   int x, int y,
5697                                   struct drm_framebuffer *fb)
5698 {
5699         struct drm_device *dev = crtc->dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702         int pipe = intel_crtc->pipe;
5703         int plane = intel_crtc->plane;
5704         int num_connectors = 0;
5705         intel_clock_t clock, reduced_clock;
5706         u32 dpll = 0, fp = 0, fp2 = 0;
5707         bool ok, has_reduced_clock = false;
5708         bool is_lvds = false;
5709         struct intel_encoder *encoder;
5710         struct intel_shared_dpll *pll;
5711         int ret;
5712
5713         for_each_encoder_on_crtc(dev, crtc, encoder) {
5714                 switch (encoder->type) {
5715                 case INTEL_OUTPUT_LVDS:
5716                         is_lvds = true;
5717                         break;
5718                 }
5719
5720                 num_connectors++;
5721         }
5722
5723         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5724              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5725
5726         ok = ironlake_compute_clocks(crtc, &clock,
5727                                      &has_reduced_clock, &reduced_clock);
5728         if (!ok && !intel_crtc->config.clock_set) {
5729                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5730                 return -EINVAL;
5731         }
5732         /* Compat-code for transition, will disappear. */
5733         if (!intel_crtc->config.clock_set) {
5734                 intel_crtc->config.dpll.n = clock.n;
5735                 intel_crtc->config.dpll.m1 = clock.m1;
5736                 intel_crtc->config.dpll.m2 = clock.m2;
5737                 intel_crtc->config.dpll.p1 = clock.p1;
5738                 intel_crtc->config.dpll.p2 = clock.p2;
5739         }
5740
5741         /* Ensure that the cursor is valid for the new mode before changing... */
5742         intel_crtc_update_cursor(crtc, true);
5743
5744         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5745         if (intel_crtc->config.has_pch_encoder) {
5746                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5747                 if (has_reduced_clock)
5748                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5749
5750                 dpll = ironlake_compute_dpll(intel_crtc,
5751                                              &fp, &reduced_clock,
5752                                              has_reduced_clock ? &fp2 : NULL);
5753
5754                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5755                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5756                 if (has_reduced_clock)
5757                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5758                 else
5759                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5760
5761                 pll = intel_get_shared_dpll(intel_crtc);
5762                 if (pll == NULL) {
5763                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5764                                          pipe_name(pipe));
5765                         return -EINVAL;
5766                 }
5767         } else
5768                 intel_put_shared_dpll(intel_crtc);
5769
5770         if (intel_crtc->config.has_dp_encoder)
5771                 intel_dp_set_m_n(intel_crtc);
5772
5773         if (is_lvds && has_reduced_clock && i915_powersave)
5774                 intel_crtc->lowfreq_avail = true;
5775         else
5776                 intel_crtc->lowfreq_avail = false;
5777
5778         if (intel_crtc->config.has_pch_encoder) {
5779                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5780
5781         }
5782
5783         intel_set_pipe_timings(intel_crtc);
5784
5785         if (intel_crtc->config.has_pch_encoder) {
5786                 intel_cpu_transcoder_set_m_n(intel_crtc,
5787                                              &intel_crtc->config.fdi_m_n);
5788         }
5789
5790         if (IS_IVYBRIDGE(dev))
5791                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5792
5793         ironlake_set_pipeconf(crtc);
5794
5795         /* Set up the display plane register */
5796         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5797         POSTING_READ(DSPCNTR(plane));
5798
5799         ret = intel_pipe_set_base(crtc, x, y, fb);
5800
5801         intel_update_watermarks(dev);
5802
5803         return ret;
5804 }
5805
5806 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5807                                         struct intel_crtc_config *pipe_config)
5808 {
5809         struct drm_device *dev = crtc->base.dev;
5810         struct drm_i915_private *dev_priv = dev->dev_private;
5811         enum transcoder transcoder = pipe_config->cpu_transcoder;
5812
5813         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5814         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5815         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5816                                         & ~TU_SIZE_MASK;
5817         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5818         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5819                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5820 }
5821
5822 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5823                                      struct intel_crtc_config *pipe_config)
5824 {
5825         struct drm_device *dev = crtc->base.dev;
5826         struct drm_i915_private *dev_priv = dev->dev_private;
5827         uint32_t tmp;
5828
5829         tmp = I915_READ(PF_CTL(crtc->pipe));
5830
5831         if (tmp & PF_ENABLE) {
5832                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5833                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5834
5835                 /* We currently do not free assignements of panel fitters on
5836                  * ivb/hsw (since we don't use the higher upscaling modes which
5837                  * differentiates them) so just WARN about this case for now. */
5838                 if (IS_GEN7(dev)) {
5839                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5840                                 PF_PIPE_SEL_IVB(crtc->pipe));
5841                 }
5842         }
5843 }
5844
5845 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5846                                      struct intel_crtc_config *pipe_config)
5847 {
5848         struct drm_device *dev = crtc->base.dev;
5849         struct drm_i915_private *dev_priv = dev->dev_private;
5850         uint32_t tmp;
5851
5852         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5853         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5854
5855         tmp = I915_READ(PIPECONF(crtc->pipe));
5856         if (!(tmp & PIPECONF_ENABLE))
5857                 return false;
5858
5859         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5860                 struct intel_shared_dpll *pll;
5861
5862                 pipe_config->has_pch_encoder = true;
5863
5864                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5865                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5866                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5867
5868                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5869
5870                 if (HAS_PCH_IBX(dev_priv->dev)) {
5871                         pipe_config->shared_dpll =
5872                                 (enum intel_dpll_id) crtc->pipe;
5873                 } else {
5874                         tmp = I915_READ(PCH_DPLL_SEL);
5875                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5876                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5877                         else
5878                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5879                 }
5880
5881                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5882
5883                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5884                                            &pipe_config->dpll_hw_state));
5885
5886                 tmp = pipe_config->dpll_hw_state.dpll;
5887                 pipe_config->pixel_multiplier =
5888                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5889                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5890         } else {
5891                 pipe_config->pixel_multiplier = 1;
5892         }
5893
5894         intel_get_pipe_timings(crtc, pipe_config);
5895
5896         ironlake_get_pfit_config(crtc, pipe_config);
5897
5898         return true;
5899 }
5900
5901 static void haswell_modeset_global_resources(struct drm_device *dev)
5902 {
5903         bool enable = false;
5904         struct intel_crtc *crtc;
5905
5906         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5907                 if (!crtc->base.enabled)
5908                         continue;
5909
5910                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5911                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5912                         enable = true;
5913         }
5914
5915         intel_set_power_well(dev, enable);
5916 }
5917
5918 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5919                                  int x, int y,
5920                                  struct drm_framebuffer *fb)
5921 {
5922         struct drm_device *dev = crtc->dev;
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925         int plane = intel_crtc->plane;
5926         int ret;
5927
5928         if (!intel_ddi_pll_mode_set(crtc))
5929                 return -EINVAL;
5930
5931         /* Ensure that the cursor is valid for the new mode before changing... */
5932         intel_crtc_update_cursor(crtc, true);
5933
5934         if (intel_crtc->config.has_dp_encoder)
5935                 intel_dp_set_m_n(intel_crtc);
5936
5937         intel_crtc->lowfreq_avail = false;
5938
5939         intel_set_pipe_timings(intel_crtc);
5940
5941         if (intel_crtc->config.has_pch_encoder) {
5942                 intel_cpu_transcoder_set_m_n(intel_crtc,
5943                                              &intel_crtc->config.fdi_m_n);
5944         }
5945
5946         haswell_set_pipeconf(crtc);
5947
5948         intel_set_pipe_csc(crtc);
5949
5950         /* Set up the display plane register */
5951         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5952         POSTING_READ(DSPCNTR(plane));
5953
5954         ret = intel_pipe_set_base(crtc, x, y, fb);
5955
5956         intel_update_watermarks(dev);
5957
5958         return ret;
5959 }
5960
5961 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5962                                     struct intel_crtc_config *pipe_config)
5963 {
5964         struct drm_device *dev = crtc->base.dev;
5965         struct drm_i915_private *dev_priv = dev->dev_private;
5966         enum intel_display_power_domain pfit_domain;
5967         uint32_t tmp;
5968
5969         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5970         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5971
5972         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5973         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5974                 enum pipe trans_edp_pipe;
5975                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5976                 default:
5977                         WARN(1, "unknown pipe linked to edp transcoder\n");
5978                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5979                 case TRANS_DDI_EDP_INPUT_A_ON:
5980                         trans_edp_pipe = PIPE_A;
5981                         break;
5982                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5983                         trans_edp_pipe = PIPE_B;
5984                         break;
5985                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5986                         trans_edp_pipe = PIPE_C;
5987                         break;
5988                 }
5989
5990                 if (trans_edp_pipe == crtc->pipe)
5991                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5992         }
5993
5994         if (!intel_display_power_enabled(dev,
5995                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5996                 return false;
5997
5998         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5999         if (!(tmp & PIPECONF_ENABLE))
6000                 return false;
6001
6002         /*
6003          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6004          * DDI E. So just check whether this pipe is wired to DDI E and whether
6005          * the PCH transcoder is on.
6006          */
6007         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6008         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6009             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6010                 pipe_config->has_pch_encoder = true;
6011
6012                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6013                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6014                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6015
6016                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6017         }
6018
6019         intel_get_pipe_timings(crtc, pipe_config);
6020
6021         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6022         if (intel_display_power_enabled(dev, pfit_domain))
6023                 ironlake_get_pfit_config(crtc, pipe_config);
6024
6025         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6026                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6027
6028         pipe_config->pixel_multiplier = 1;
6029
6030         return true;
6031 }
6032
6033 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6034                                int x, int y,
6035                                struct drm_framebuffer *fb)
6036 {
6037         struct drm_device *dev = crtc->dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         struct drm_encoder_helper_funcs *encoder_funcs;
6040         struct intel_encoder *encoder;
6041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6042         struct drm_display_mode *adjusted_mode =
6043                 &intel_crtc->config.adjusted_mode;
6044         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6045         int pipe = intel_crtc->pipe;
6046         int ret;
6047
6048         drm_vblank_pre_modeset(dev, pipe);
6049
6050         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6051
6052         drm_vblank_post_modeset(dev, pipe);
6053
6054         if (ret != 0)
6055                 return ret;
6056
6057         for_each_encoder_on_crtc(dev, crtc, encoder) {
6058                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6059                         encoder->base.base.id,
6060                         drm_get_encoder_name(&encoder->base),
6061                         mode->base.id, mode->name);
6062                 if (encoder->mode_set) {
6063                         encoder->mode_set(encoder);
6064                 } else {
6065                         encoder_funcs = encoder->base.helper_private;
6066                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6067                 }
6068         }
6069
6070         return 0;
6071 }
6072
6073 static bool intel_eld_uptodate(struct drm_connector *connector,
6074                                int reg_eldv, uint32_t bits_eldv,
6075                                int reg_elda, uint32_t bits_elda,
6076                                int reg_edid)
6077 {
6078         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079         uint8_t *eld = connector->eld;
6080         uint32_t i;
6081
6082         i = I915_READ(reg_eldv);
6083         i &= bits_eldv;
6084
6085         if (!eld[0])
6086                 return !i;
6087
6088         if (!i)
6089                 return false;
6090
6091         i = I915_READ(reg_elda);
6092         i &= ~bits_elda;
6093         I915_WRITE(reg_elda, i);
6094
6095         for (i = 0; i < eld[2]; i++)
6096                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6097                         return false;
6098
6099         return true;
6100 }
6101
6102 static void g4x_write_eld(struct drm_connector *connector,
6103                           struct drm_crtc *crtc)
6104 {
6105         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106         uint8_t *eld = connector->eld;
6107         uint32_t eldv;
6108         uint32_t len;
6109         uint32_t i;
6110
6111         i = I915_READ(G4X_AUD_VID_DID);
6112
6113         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6114                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6115         else
6116                 eldv = G4X_ELDV_DEVCTG;
6117
6118         if (intel_eld_uptodate(connector,
6119                                G4X_AUD_CNTL_ST, eldv,
6120                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6121                                G4X_HDMIW_HDMIEDID))
6122                 return;
6123
6124         i = I915_READ(G4X_AUD_CNTL_ST);
6125         i &= ~(eldv | G4X_ELD_ADDR);
6126         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6127         I915_WRITE(G4X_AUD_CNTL_ST, i);
6128
6129         if (!eld[0])
6130                 return;
6131
6132         len = min_t(uint8_t, eld[2], len);
6133         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6134         for (i = 0; i < len; i++)
6135                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6136
6137         i = I915_READ(G4X_AUD_CNTL_ST);
6138         i |= eldv;
6139         I915_WRITE(G4X_AUD_CNTL_ST, i);
6140 }
6141
6142 static void haswell_write_eld(struct drm_connector *connector,
6143                                      struct drm_crtc *crtc)
6144 {
6145         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6146         uint8_t *eld = connector->eld;
6147         struct drm_device *dev = crtc->dev;
6148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149         uint32_t eldv;
6150         uint32_t i;
6151         int len;
6152         int pipe = to_intel_crtc(crtc)->pipe;
6153         int tmp;
6154
6155         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6156         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6157         int aud_config = HSW_AUD_CFG(pipe);
6158         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6159
6160
6161         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6162
6163         /* Audio output enable */
6164         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6165         tmp = I915_READ(aud_cntrl_st2);
6166         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6167         I915_WRITE(aud_cntrl_st2, tmp);
6168
6169         /* Wait for 1 vertical blank */
6170         intel_wait_for_vblank(dev, pipe);
6171
6172         /* Set ELD valid state */
6173         tmp = I915_READ(aud_cntrl_st2);
6174         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6175         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6176         I915_WRITE(aud_cntrl_st2, tmp);
6177         tmp = I915_READ(aud_cntrl_st2);
6178         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6179
6180         /* Enable HDMI mode */
6181         tmp = I915_READ(aud_config);
6182         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6183         /* clear N_programing_enable and N_value_index */
6184         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6185         I915_WRITE(aud_config, tmp);
6186
6187         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6188
6189         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6190         intel_crtc->eld_vld = true;
6191
6192         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6193                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6194                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6195                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6196         } else
6197                 I915_WRITE(aud_config, 0);
6198
6199         if (intel_eld_uptodate(connector,
6200                                aud_cntrl_st2, eldv,
6201                                aud_cntl_st, IBX_ELD_ADDRESS,
6202                                hdmiw_hdmiedid))
6203                 return;
6204
6205         i = I915_READ(aud_cntrl_st2);
6206         i &= ~eldv;
6207         I915_WRITE(aud_cntrl_st2, i);
6208
6209         if (!eld[0])
6210                 return;
6211
6212         i = I915_READ(aud_cntl_st);
6213         i &= ~IBX_ELD_ADDRESS;
6214         I915_WRITE(aud_cntl_st, i);
6215         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6216         DRM_DEBUG_DRIVER("port num:%d\n", i);
6217
6218         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6219         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6220         for (i = 0; i < len; i++)
6221                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6222
6223         i = I915_READ(aud_cntrl_st2);
6224         i |= eldv;
6225         I915_WRITE(aud_cntrl_st2, i);
6226
6227 }
6228
6229 static void ironlake_write_eld(struct drm_connector *connector,
6230                                      struct drm_crtc *crtc)
6231 {
6232         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6233         uint8_t *eld = connector->eld;
6234         uint32_t eldv;
6235         uint32_t i;
6236         int len;
6237         int hdmiw_hdmiedid;
6238         int aud_config;
6239         int aud_cntl_st;
6240         int aud_cntrl_st2;
6241         int pipe = to_intel_crtc(crtc)->pipe;
6242
6243         if (HAS_PCH_IBX(connector->dev)) {
6244                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6245                 aud_config = IBX_AUD_CFG(pipe);
6246                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6247                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6248         } else {
6249                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6250                 aud_config = CPT_AUD_CFG(pipe);
6251                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6252                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6253         }
6254
6255         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6256
6257         i = I915_READ(aud_cntl_st);
6258         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6259         if (!i) {
6260                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6261                 /* operate blindly on all ports */
6262                 eldv = IBX_ELD_VALIDB;
6263                 eldv |= IBX_ELD_VALIDB << 4;
6264                 eldv |= IBX_ELD_VALIDB << 8;
6265         } else {
6266                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6267                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6268         }
6269
6270         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6271                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6272                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6273                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6274         } else
6275                 I915_WRITE(aud_config, 0);
6276
6277         if (intel_eld_uptodate(connector,
6278                                aud_cntrl_st2, eldv,
6279                                aud_cntl_st, IBX_ELD_ADDRESS,
6280                                hdmiw_hdmiedid))
6281                 return;
6282
6283         i = I915_READ(aud_cntrl_st2);
6284         i &= ~eldv;
6285         I915_WRITE(aud_cntrl_st2, i);
6286
6287         if (!eld[0])
6288                 return;
6289
6290         i = I915_READ(aud_cntl_st);
6291         i &= ~IBX_ELD_ADDRESS;
6292         I915_WRITE(aud_cntl_st, i);
6293
6294         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6295         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6296         for (i = 0; i < len; i++)
6297                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6298
6299         i = I915_READ(aud_cntrl_st2);
6300         i |= eldv;
6301         I915_WRITE(aud_cntrl_st2, i);
6302 }
6303
6304 void intel_write_eld(struct drm_encoder *encoder,
6305                      struct drm_display_mode *mode)
6306 {
6307         struct drm_crtc *crtc = encoder->crtc;
6308         struct drm_connector *connector;
6309         struct drm_device *dev = encoder->dev;
6310         struct drm_i915_private *dev_priv = dev->dev_private;
6311
6312         connector = drm_select_eld(encoder, mode);
6313         if (!connector)
6314                 return;
6315
6316         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6317                          connector->base.id,
6318                          drm_get_connector_name(connector),
6319                          connector->encoder->base.id,
6320                          drm_get_encoder_name(connector->encoder));
6321
6322         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6323
6324         if (dev_priv->display.write_eld)
6325                 dev_priv->display.write_eld(connector, crtc);
6326 }
6327
6328 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6329 void intel_crtc_load_lut(struct drm_crtc *crtc)
6330 {
6331         struct drm_device *dev = crtc->dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334         enum pipe pipe = intel_crtc->pipe;
6335         int palreg = PALETTE(pipe);
6336         int i;
6337         bool reenable_ips = false;
6338
6339         /* The clocks have to be on to load the palette. */
6340         if (!crtc->enabled || !intel_crtc->active)
6341                 return;
6342
6343         if (!HAS_PCH_SPLIT(dev_priv->dev))
6344                 assert_pll_enabled(dev_priv, pipe);
6345
6346         /* use legacy palette for Ironlake */
6347         if (HAS_PCH_SPLIT(dev))
6348                 palreg = LGC_PALETTE(pipe);
6349
6350         /* Workaround : Do not read or write the pipe palette/gamma data while
6351          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6352          */
6353         if (intel_crtc->config.ips_enabled &&
6354             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6355              GAMMA_MODE_MODE_SPLIT)) {
6356                 hsw_disable_ips(intel_crtc);
6357                 reenable_ips = true;
6358         }
6359
6360         for (i = 0; i < 256; i++) {
6361                 I915_WRITE(palreg + 4 * i,
6362                            (intel_crtc->lut_r[i] << 16) |
6363                            (intel_crtc->lut_g[i] << 8) |
6364                            intel_crtc->lut_b[i]);
6365         }
6366
6367         if (reenable_ips)
6368                 hsw_enable_ips(intel_crtc);
6369 }
6370
6371 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6372 {
6373         struct drm_device *dev = crtc->dev;
6374         struct drm_i915_private *dev_priv = dev->dev_private;
6375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376         bool visible = base != 0;
6377         u32 cntl;
6378
6379         if (intel_crtc->cursor_visible == visible)
6380                 return;
6381
6382         cntl = I915_READ(_CURACNTR);
6383         if (visible) {
6384                 /* On these chipsets we can only modify the base whilst
6385                  * the cursor is disabled.
6386                  */
6387                 I915_WRITE(_CURABASE, base);
6388
6389                 cntl &= ~(CURSOR_FORMAT_MASK);
6390                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6391                 cntl |= CURSOR_ENABLE |
6392                         CURSOR_GAMMA_ENABLE |
6393                         CURSOR_FORMAT_ARGB;
6394         } else
6395                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6396         I915_WRITE(_CURACNTR, cntl);
6397
6398         intel_crtc->cursor_visible = visible;
6399 }
6400
6401 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6402 {
6403         struct drm_device *dev = crtc->dev;
6404         struct drm_i915_private *dev_priv = dev->dev_private;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406         int pipe = intel_crtc->pipe;
6407         bool visible = base != 0;
6408
6409         if (intel_crtc->cursor_visible != visible) {
6410                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6411                 if (base) {
6412                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6413                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6414                         cntl |= pipe << 28; /* Connect to correct pipe */
6415                 } else {
6416                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6417                         cntl |= CURSOR_MODE_DISABLE;
6418                 }
6419                 I915_WRITE(CURCNTR(pipe), cntl);
6420
6421                 intel_crtc->cursor_visible = visible;
6422         }
6423         /* and commit changes on next vblank */
6424         I915_WRITE(CURBASE(pipe), base);
6425 }
6426
6427 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6428 {
6429         struct drm_device *dev = crtc->dev;
6430         struct drm_i915_private *dev_priv = dev->dev_private;
6431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432         int pipe = intel_crtc->pipe;
6433         bool visible = base != 0;
6434
6435         if (intel_crtc->cursor_visible != visible) {
6436                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6437                 if (base) {
6438                         cntl &= ~CURSOR_MODE;
6439                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6440                 } else {
6441                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6442                         cntl |= CURSOR_MODE_DISABLE;
6443                 }
6444                 if (IS_HASWELL(dev))
6445                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6446                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6447
6448                 intel_crtc->cursor_visible = visible;
6449         }
6450         /* and commit changes on next vblank */
6451         I915_WRITE(CURBASE_IVB(pipe), base);
6452 }
6453
6454 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6455 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6456                                      bool on)
6457 {
6458         struct drm_device *dev = crtc->dev;
6459         struct drm_i915_private *dev_priv = dev->dev_private;
6460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461         int pipe = intel_crtc->pipe;
6462         int x = intel_crtc->cursor_x;
6463         int y = intel_crtc->cursor_y;
6464         u32 base, pos;
6465         bool visible;
6466
6467         pos = 0;
6468
6469         if (on && crtc->enabled && crtc->fb) {
6470                 base = intel_crtc->cursor_addr;
6471                 if (x > (int) crtc->fb->width)
6472                         base = 0;
6473
6474                 if (y > (int) crtc->fb->height)
6475                         base = 0;
6476         } else
6477                 base = 0;
6478
6479         if (x < 0) {
6480                 if (x + intel_crtc->cursor_width < 0)
6481                         base = 0;
6482
6483                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6484                 x = -x;
6485         }
6486         pos |= x << CURSOR_X_SHIFT;
6487
6488         if (y < 0) {
6489                 if (y + intel_crtc->cursor_height < 0)
6490                         base = 0;
6491
6492                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6493                 y = -y;
6494         }
6495         pos |= y << CURSOR_Y_SHIFT;
6496
6497         visible = base != 0;
6498         if (!visible && !intel_crtc->cursor_visible)
6499                 return;
6500
6501         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6502                 I915_WRITE(CURPOS_IVB(pipe), pos);
6503                 ivb_update_cursor(crtc, base);
6504         } else {
6505                 I915_WRITE(CURPOS(pipe), pos);
6506                 if (IS_845G(dev) || IS_I865G(dev))
6507                         i845_update_cursor(crtc, base);
6508                 else
6509                         i9xx_update_cursor(crtc, base);
6510         }
6511 }
6512
6513 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6514                                  struct drm_file *file,
6515                                  uint32_t handle,
6516                                  uint32_t width, uint32_t height)
6517 {
6518         struct drm_device *dev = crtc->dev;
6519         struct drm_i915_private *dev_priv = dev->dev_private;
6520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6521         struct drm_i915_gem_object *obj;
6522         uint32_t addr;
6523         int ret;
6524
6525         /* if we want to turn off the cursor ignore width and height */
6526         if (!handle) {
6527                 DRM_DEBUG_KMS("cursor off\n");
6528                 addr = 0;
6529                 obj = NULL;
6530                 mutex_lock(&dev->struct_mutex);
6531                 goto finish;
6532         }
6533
6534         /* Currently we only support 64x64 cursors */
6535         if (width != 64 || height != 64) {
6536                 DRM_ERROR("we currently only support 64x64 cursors\n");
6537                 return -EINVAL;
6538         }
6539
6540         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6541         if (&obj->base == NULL)
6542                 return -ENOENT;
6543
6544         if (obj->base.size < width * height * 4) {
6545                 DRM_ERROR("buffer is to small\n");
6546                 ret = -ENOMEM;
6547                 goto fail;
6548         }
6549
6550         /* we only need to pin inside GTT if cursor is non-phy */
6551         mutex_lock(&dev->struct_mutex);
6552         if (!dev_priv->info->cursor_needs_physical) {
6553                 unsigned alignment;
6554
6555                 if (obj->tiling_mode) {
6556                         DRM_ERROR("cursor cannot be tiled\n");
6557                         ret = -EINVAL;
6558                         goto fail_locked;
6559                 }
6560
6561                 /* Note that the w/a also requires 2 PTE of padding following
6562                  * the bo. We currently fill all unused PTE with the shadow
6563                  * page and so we should always have valid PTE following the
6564                  * cursor preventing the VT-d warning.
6565                  */
6566                 alignment = 0;
6567                 if (need_vtd_wa(dev))
6568                         alignment = 64*1024;
6569
6570                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6571                 if (ret) {
6572                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6573                         goto fail_locked;
6574                 }
6575
6576                 ret = i915_gem_object_put_fence(obj);
6577                 if (ret) {
6578                         DRM_ERROR("failed to release fence for cursor");
6579                         goto fail_unpin;
6580                 }
6581
6582                 addr = i915_gem_obj_ggtt_offset(obj);
6583         } else {
6584                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6585                 ret = i915_gem_attach_phys_object(dev, obj,
6586                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6587                                                   align);
6588                 if (ret) {
6589                         DRM_ERROR("failed to attach phys object\n");
6590                         goto fail_locked;
6591                 }
6592                 addr = obj->phys_obj->handle->busaddr;
6593         }
6594
6595         if (IS_GEN2(dev))
6596                 I915_WRITE(CURSIZE, (height << 12) | width);
6597
6598  finish:
6599         if (intel_crtc->cursor_bo) {
6600                 if (dev_priv->info->cursor_needs_physical) {
6601                         if (intel_crtc->cursor_bo != obj)
6602                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6603                 } else
6604                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6605                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6606         }
6607
6608         mutex_unlock(&dev->struct_mutex);
6609
6610         intel_crtc->cursor_addr = addr;
6611         intel_crtc->cursor_bo = obj;
6612         intel_crtc->cursor_width = width;
6613         intel_crtc->cursor_height = height;
6614
6615         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6616
6617         return 0;
6618 fail_unpin:
6619         i915_gem_object_unpin(obj);
6620 fail_locked:
6621         mutex_unlock(&dev->struct_mutex);
6622 fail:
6623         drm_gem_object_unreference_unlocked(&obj->base);
6624         return ret;
6625 }
6626
6627 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6628 {
6629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6630
6631         intel_crtc->cursor_x = x;
6632         intel_crtc->cursor_y = y;
6633
6634         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6635
6636         return 0;
6637 }
6638
6639 /** Sets the color ramps on behalf of RandR */
6640 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6641                                  u16 blue, int regno)
6642 {
6643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645         intel_crtc->lut_r[regno] = red >> 8;
6646         intel_crtc->lut_g[regno] = green >> 8;
6647         intel_crtc->lut_b[regno] = blue >> 8;
6648 }
6649
6650 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6651                              u16 *blue, int regno)
6652 {
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654
6655         *red = intel_crtc->lut_r[regno] << 8;
6656         *green = intel_crtc->lut_g[regno] << 8;
6657         *blue = intel_crtc->lut_b[regno] << 8;
6658 }
6659
6660 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6661                                  u16 *blue, uint32_t start, uint32_t size)
6662 {
6663         int end = (start + size > 256) ? 256 : start + size, i;
6664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665
6666         for (i = start; i < end; i++) {
6667                 intel_crtc->lut_r[i] = red[i] >> 8;
6668                 intel_crtc->lut_g[i] = green[i] >> 8;
6669                 intel_crtc->lut_b[i] = blue[i] >> 8;
6670         }
6671
6672         intel_crtc_load_lut(crtc);
6673 }
6674
6675 /* VESA 640x480x72Hz mode to set on the pipe */
6676 static struct drm_display_mode load_detect_mode = {
6677         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6678                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6679 };
6680
6681 static struct drm_framebuffer *
6682 intel_framebuffer_create(struct drm_device *dev,
6683                          struct drm_mode_fb_cmd2 *mode_cmd,
6684                          struct drm_i915_gem_object *obj)
6685 {
6686         struct intel_framebuffer *intel_fb;
6687         int ret;
6688
6689         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6690         if (!intel_fb) {
6691                 drm_gem_object_unreference_unlocked(&obj->base);
6692                 return ERR_PTR(-ENOMEM);
6693         }
6694
6695         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6696         if (ret) {
6697                 drm_gem_object_unreference_unlocked(&obj->base);
6698                 kfree(intel_fb);
6699                 return ERR_PTR(ret);
6700         }
6701
6702         return &intel_fb->base;
6703 }
6704
6705 static u32
6706 intel_framebuffer_pitch_for_width(int width, int bpp)
6707 {
6708         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6709         return ALIGN(pitch, 64);
6710 }
6711
6712 static u32
6713 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6714 {
6715         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6716         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6717 }
6718
6719 static struct drm_framebuffer *
6720 intel_framebuffer_create_for_mode(struct drm_device *dev,
6721                                   struct drm_display_mode *mode,
6722                                   int depth, int bpp)
6723 {
6724         struct drm_i915_gem_object *obj;
6725         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6726
6727         obj = i915_gem_alloc_object(dev,
6728                                     intel_framebuffer_size_for_mode(mode, bpp));
6729         if (obj == NULL)
6730                 return ERR_PTR(-ENOMEM);
6731
6732         mode_cmd.width = mode->hdisplay;
6733         mode_cmd.height = mode->vdisplay;
6734         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6735                                                                 bpp);
6736         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6737
6738         return intel_framebuffer_create(dev, &mode_cmd, obj);
6739 }
6740
6741 static struct drm_framebuffer *
6742 mode_fits_in_fbdev(struct drm_device *dev,
6743                    struct drm_display_mode *mode)
6744 {
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746         struct drm_i915_gem_object *obj;
6747         struct drm_framebuffer *fb;
6748
6749         if (dev_priv->fbdev == NULL)
6750                 return NULL;
6751
6752         obj = dev_priv->fbdev->ifb.obj;
6753         if (obj == NULL)
6754                 return NULL;
6755
6756         fb = &dev_priv->fbdev->ifb.base;
6757         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6758                                                                fb->bits_per_pixel))
6759                 return NULL;
6760
6761         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6762                 return NULL;
6763
6764         return fb;
6765 }
6766
6767 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6768                                 struct drm_display_mode *mode,
6769                                 struct intel_load_detect_pipe *old)
6770 {
6771         struct intel_crtc *intel_crtc;
6772         struct intel_encoder *intel_encoder =
6773                 intel_attached_encoder(connector);
6774         struct drm_crtc *possible_crtc;
6775         struct drm_encoder *encoder = &intel_encoder->base;
6776         struct drm_crtc *crtc = NULL;
6777         struct drm_device *dev = encoder->dev;
6778         struct drm_framebuffer *fb;
6779         int i = -1;
6780
6781         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782                       connector->base.id, drm_get_connector_name(connector),
6783                       encoder->base.id, drm_get_encoder_name(encoder));
6784
6785         /*
6786          * Algorithm gets a little messy:
6787          *
6788          *   - if the connector already has an assigned crtc, use it (but make
6789          *     sure it's on first)
6790          *
6791          *   - try to find the first unused crtc that can drive this connector,
6792          *     and use that if we find one
6793          */
6794
6795         /* See if we already have a CRTC for this connector */
6796         if (encoder->crtc) {
6797                 crtc = encoder->crtc;
6798
6799                 mutex_lock(&crtc->mutex);
6800
6801                 old->dpms_mode = connector->dpms;
6802                 old->load_detect_temp = false;
6803
6804                 /* Make sure the crtc and connector are running */
6805                 if (connector->dpms != DRM_MODE_DPMS_ON)
6806                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6807
6808                 return true;
6809         }
6810
6811         /* Find an unused one (if possible) */
6812         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6813                 i++;
6814                 if (!(encoder->possible_crtcs & (1 << i)))
6815                         continue;
6816                 if (!possible_crtc->enabled) {
6817                         crtc = possible_crtc;
6818                         break;
6819                 }
6820         }
6821
6822         /*
6823          * If we didn't find an unused CRTC, don't use any.
6824          */
6825         if (!crtc) {
6826                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6827                 return false;
6828         }
6829
6830         mutex_lock(&crtc->mutex);
6831         intel_encoder->new_crtc = to_intel_crtc(crtc);
6832         to_intel_connector(connector)->new_encoder = intel_encoder;
6833
6834         intel_crtc = to_intel_crtc(crtc);
6835         old->dpms_mode = connector->dpms;
6836         old->load_detect_temp = true;
6837         old->release_fb = NULL;
6838
6839         if (!mode)
6840                 mode = &load_detect_mode;
6841
6842         /* We need a framebuffer large enough to accommodate all accesses
6843          * that the plane may generate whilst we perform load detection.
6844          * We can not rely on the fbcon either being present (we get called
6845          * during its initialisation to detect all boot displays, or it may
6846          * not even exist) or that it is large enough to satisfy the
6847          * requested mode.
6848          */
6849         fb = mode_fits_in_fbdev(dev, mode);
6850         if (fb == NULL) {
6851                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6852                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6853                 old->release_fb = fb;
6854         } else
6855                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6856         if (IS_ERR(fb)) {
6857                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6858                 mutex_unlock(&crtc->mutex);
6859                 return false;
6860         }
6861
6862         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6863                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6864                 if (old->release_fb)
6865                         old->release_fb->funcs->destroy(old->release_fb);
6866                 mutex_unlock(&crtc->mutex);
6867                 return false;
6868         }
6869
6870         /* let the connector get through one full cycle before testing */
6871         intel_wait_for_vblank(dev, intel_crtc->pipe);
6872         return true;
6873 }
6874
6875 void intel_release_load_detect_pipe(struct drm_connector *connector,
6876                                     struct intel_load_detect_pipe *old)
6877 {
6878         struct intel_encoder *intel_encoder =
6879                 intel_attached_encoder(connector);
6880         struct drm_encoder *encoder = &intel_encoder->base;
6881         struct drm_crtc *crtc = encoder->crtc;
6882
6883         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6884                       connector->base.id, drm_get_connector_name(connector),
6885                       encoder->base.id, drm_get_encoder_name(encoder));
6886
6887         if (old->load_detect_temp) {
6888                 to_intel_connector(connector)->new_encoder = NULL;
6889                 intel_encoder->new_crtc = NULL;
6890                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6891
6892                 if (old->release_fb) {
6893                         drm_framebuffer_unregister_private(old->release_fb);
6894                         drm_framebuffer_unreference(old->release_fb);
6895                 }
6896
6897                 mutex_unlock(&crtc->mutex);
6898                 return;
6899         }
6900
6901         /* Switch crtc and encoder back off if necessary */
6902         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6903                 connector->funcs->dpms(connector, old->dpms_mode);
6904
6905         mutex_unlock(&crtc->mutex);
6906 }
6907
6908 /* Returns the clock of the currently programmed mode of the given pipe. */
6909 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6910                                 struct intel_crtc_config *pipe_config)
6911 {
6912         struct drm_device *dev = crtc->base.dev;
6913         struct drm_i915_private *dev_priv = dev->dev_private;
6914         int pipe = pipe_config->cpu_transcoder;
6915         u32 dpll = I915_READ(DPLL(pipe));
6916         u32 fp;
6917         intel_clock_t clock;
6918
6919         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6920                 fp = I915_READ(FP0(pipe));
6921         else
6922                 fp = I915_READ(FP1(pipe));
6923
6924         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6925         if (IS_PINEVIEW(dev)) {
6926                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6927                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6928         } else {
6929                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6930                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6931         }
6932
6933         if (!IS_GEN2(dev)) {
6934                 if (IS_PINEVIEW(dev))
6935                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6936                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6937                 else
6938                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6939                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6940
6941                 switch (dpll & DPLL_MODE_MASK) {
6942                 case DPLLB_MODE_DAC_SERIAL:
6943                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6944                                 5 : 10;
6945                         break;
6946                 case DPLLB_MODE_LVDS:
6947                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6948                                 7 : 14;
6949                         break;
6950                 default:
6951                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6952                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6953                         pipe_config->adjusted_mode.clock = 0;
6954                         return;
6955                 }
6956
6957                 if (IS_PINEVIEW(dev))
6958                         pineview_clock(96000, &clock);
6959                 else
6960                         i9xx_clock(96000, &clock);
6961         } else {
6962                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6963
6964                 if (is_lvds) {
6965                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6966                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6967                         clock.p2 = 14;
6968
6969                         if ((dpll & PLL_REF_INPUT_MASK) ==
6970                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6971                                 /* XXX: might not be 66MHz */
6972                                 i9xx_clock(66000, &clock);
6973                         } else
6974                                 i9xx_clock(48000, &clock);
6975                 } else {
6976                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6977                                 clock.p1 = 2;
6978                         else {
6979                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6980                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6981                         }
6982                         if (dpll & PLL_P2_DIVIDE_BY_4)
6983                                 clock.p2 = 4;
6984                         else
6985                                 clock.p2 = 2;
6986
6987                         i9xx_clock(48000, &clock);
6988                 }
6989         }
6990
6991         pipe_config->adjusted_mode.clock = clock.dot *
6992                 pipe_config->pixel_multiplier;
6993 }
6994
6995 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6996                                     struct intel_crtc_config *pipe_config)
6997 {
6998         struct drm_device *dev = crtc->base.dev;
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7001         int link_freq, repeat;
7002         u64 clock;
7003         u32 link_m, link_n;
7004
7005         repeat = pipe_config->pixel_multiplier;
7006
7007         /*
7008          * The calculation for the data clock is:
7009          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7010          * But we want to avoid losing precison if possible, so:
7011          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7012          *
7013          * and the link clock is simpler:
7014          * link_clock = (m * link_clock * repeat) / n
7015          */
7016
7017         /*
7018          * We need to get the FDI or DP link clock here to derive
7019          * the M/N dividers.
7020          *
7021          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7022          * For DP, it's either 1.62GHz or 2.7GHz.
7023          * We do our calculations in 10*MHz since we don't need much precison.
7024          */
7025         if (pipe_config->has_pch_encoder)
7026                 link_freq = intel_fdi_link_freq(dev) * 10000;
7027         else
7028                 link_freq = pipe_config->port_clock;
7029
7030         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7031         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7032
7033         if (!link_m || !link_n)
7034                 return;
7035
7036         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7037         do_div(clock, link_n);
7038
7039         pipe_config->adjusted_mode.clock = clock;
7040 }
7041
7042 /** Returns the currently programmed mode of the given pipe. */
7043 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7044                                              struct drm_crtc *crtc)
7045 {
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7049         struct drm_display_mode *mode;
7050         struct intel_crtc_config pipe_config;
7051         int htot = I915_READ(HTOTAL(cpu_transcoder));
7052         int hsync = I915_READ(HSYNC(cpu_transcoder));
7053         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7054         int vsync = I915_READ(VSYNC(cpu_transcoder));
7055
7056         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7057         if (!mode)
7058                 return NULL;
7059
7060         /*
7061          * Construct a pipe_config sufficient for getting the clock info
7062          * back out of crtc_clock_get.
7063          *
7064          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7065          * to use a real value here instead.
7066          */
7067         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7068         pipe_config.pixel_multiplier = 1;
7069         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7070
7071         mode->clock = pipe_config.adjusted_mode.clock;
7072         mode->hdisplay = (htot & 0xffff) + 1;
7073         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7074         mode->hsync_start = (hsync & 0xffff) + 1;
7075         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7076         mode->vdisplay = (vtot & 0xffff) + 1;
7077         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7078         mode->vsync_start = (vsync & 0xffff) + 1;
7079         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7080
7081         drm_mode_set_name(mode);
7082
7083         return mode;
7084 }
7085
7086 static void intel_increase_pllclock(struct drm_crtc *crtc)
7087 {
7088         struct drm_device *dev = crtc->dev;
7089         drm_i915_private_t *dev_priv = dev->dev_private;
7090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091         int pipe = intel_crtc->pipe;
7092         int dpll_reg = DPLL(pipe);
7093         int dpll;
7094
7095         if (HAS_PCH_SPLIT(dev))
7096                 return;
7097
7098         if (!dev_priv->lvds_downclock_avail)
7099                 return;
7100
7101         dpll = I915_READ(dpll_reg);
7102         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7103                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7104
7105                 assert_panel_unlocked(dev_priv, pipe);
7106
7107                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7108                 I915_WRITE(dpll_reg, dpll);
7109                 intel_wait_for_vblank(dev, pipe);
7110
7111                 dpll = I915_READ(dpll_reg);
7112                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7113                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7114         }
7115 }
7116
7117 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7118 {
7119         struct drm_device *dev = crtc->dev;
7120         drm_i915_private_t *dev_priv = dev->dev_private;
7121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7122
7123         if (HAS_PCH_SPLIT(dev))
7124                 return;
7125
7126         if (!dev_priv->lvds_downclock_avail)
7127                 return;
7128
7129         /*
7130          * Since this is called by a timer, we should never get here in
7131          * the manual case.
7132          */
7133         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7134                 int pipe = intel_crtc->pipe;
7135                 int dpll_reg = DPLL(pipe);
7136                 int dpll;
7137
7138                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7139
7140                 assert_panel_unlocked(dev_priv, pipe);
7141
7142                 dpll = I915_READ(dpll_reg);
7143                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7144                 I915_WRITE(dpll_reg, dpll);
7145                 intel_wait_for_vblank(dev, pipe);
7146                 dpll = I915_READ(dpll_reg);
7147                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7148                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7149         }
7150
7151 }
7152
7153 void intel_mark_busy(struct drm_device *dev)
7154 {
7155         i915_update_gfx_val(dev->dev_private);
7156 }
7157
7158 void intel_mark_idle(struct drm_device *dev)
7159 {
7160         struct drm_crtc *crtc;
7161
7162         if (!i915_powersave)
7163                 return;
7164
7165         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7166                 if (!crtc->fb)
7167                         continue;
7168
7169                 intel_decrease_pllclock(crtc);
7170         }
7171 }
7172
7173 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7174                         struct intel_ring_buffer *ring)
7175 {
7176         struct drm_device *dev = obj->base.dev;
7177         struct drm_crtc *crtc;
7178
7179         if (!i915_powersave)
7180                 return;
7181
7182         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7183                 if (!crtc->fb)
7184                         continue;
7185
7186                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7187                         continue;
7188
7189                 intel_increase_pllclock(crtc);
7190                 if (ring && intel_fbc_enabled(dev))
7191                         ring->fbc_dirty = true;
7192         }
7193 }
7194
7195 static void intel_crtc_destroy(struct drm_crtc *crtc)
7196 {
7197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7198         struct drm_device *dev = crtc->dev;
7199         struct intel_unpin_work *work;
7200         unsigned long flags;
7201
7202         spin_lock_irqsave(&dev->event_lock, flags);
7203         work = intel_crtc->unpin_work;
7204         intel_crtc->unpin_work = NULL;
7205         spin_unlock_irqrestore(&dev->event_lock, flags);
7206
7207         if (work) {
7208                 cancel_work_sync(&work->work);
7209                 kfree(work);
7210         }
7211
7212         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7213
7214         drm_crtc_cleanup(crtc);
7215
7216         kfree(intel_crtc);
7217 }
7218
7219 static void intel_unpin_work_fn(struct work_struct *__work)
7220 {
7221         struct intel_unpin_work *work =
7222                 container_of(__work, struct intel_unpin_work, work);
7223         struct drm_device *dev = work->crtc->dev;
7224
7225         mutex_lock(&dev->struct_mutex);
7226         intel_unpin_fb_obj(work->old_fb_obj);
7227         drm_gem_object_unreference(&work->pending_flip_obj->base);
7228         drm_gem_object_unreference(&work->old_fb_obj->base);
7229
7230         intel_update_fbc(dev);
7231         mutex_unlock(&dev->struct_mutex);
7232
7233         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7234         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7235
7236         kfree(work);
7237 }
7238
7239 static void do_intel_finish_page_flip(struct drm_device *dev,
7240                                       struct drm_crtc *crtc)
7241 {
7242         drm_i915_private_t *dev_priv = dev->dev_private;
7243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244         struct intel_unpin_work *work;
7245         unsigned long flags;
7246
7247         /* Ignore early vblank irqs */
7248         if (intel_crtc == NULL)
7249                 return;
7250
7251         spin_lock_irqsave(&dev->event_lock, flags);
7252         work = intel_crtc->unpin_work;
7253
7254         /* Ensure we don't miss a work->pending update ... */
7255         smp_rmb();
7256
7257         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7258                 spin_unlock_irqrestore(&dev->event_lock, flags);
7259                 return;
7260         }
7261
7262         /* and that the unpin work is consistent wrt ->pending. */
7263         smp_rmb();
7264
7265         intel_crtc->unpin_work = NULL;
7266
7267         if (work->event)
7268                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7269
7270         drm_vblank_put(dev, intel_crtc->pipe);
7271
7272         spin_unlock_irqrestore(&dev->event_lock, flags);
7273
7274         wake_up_all(&dev_priv->pending_flip_queue);
7275
7276         queue_work(dev_priv->wq, &work->work);
7277
7278         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7279 }
7280
7281 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7282 {
7283         drm_i915_private_t *dev_priv = dev->dev_private;
7284         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7285
7286         do_intel_finish_page_flip(dev, crtc);
7287 }
7288
7289 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7290 {
7291         drm_i915_private_t *dev_priv = dev->dev_private;
7292         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7293
7294         do_intel_finish_page_flip(dev, crtc);
7295 }
7296
7297 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7298 {
7299         drm_i915_private_t *dev_priv = dev->dev_private;
7300         struct intel_crtc *intel_crtc =
7301                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7302         unsigned long flags;
7303
7304         /* NB: An MMIO update of the plane base pointer will also
7305          * generate a page-flip completion irq, i.e. every modeset
7306          * is also accompanied by a spurious intel_prepare_page_flip().
7307          */
7308         spin_lock_irqsave(&dev->event_lock, flags);
7309         if (intel_crtc->unpin_work)
7310                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7311         spin_unlock_irqrestore(&dev->event_lock, flags);
7312 }
7313
7314 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7315 {
7316         /* Ensure that the work item is consistent when activating it ... */
7317         smp_wmb();
7318         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7319         /* and that it is marked active as soon as the irq could fire. */
7320         smp_wmb();
7321 }
7322
7323 static int intel_gen2_queue_flip(struct drm_device *dev,
7324                                  struct drm_crtc *crtc,
7325                                  struct drm_framebuffer *fb,
7326                                  struct drm_i915_gem_object *obj)
7327 {
7328         struct drm_i915_private *dev_priv = dev->dev_private;
7329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330         u32 flip_mask;
7331         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7332         int ret;
7333
7334         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7335         if (ret)
7336                 goto err;
7337
7338         ret = intel_ring_begin(ring, 6);
7339         if (ret)
7340                 goto err_unpin;
7341
7342         /* Can't queue multiple flips, so wait for the previous
7343          * one to finish before executing the next.
7344          */
7345         if (intel_crtc->plane)
7346                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7347         else
7348                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7349         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7350         intel_ring_emit(ring, MI_NOOP);
7351         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7352                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7353         intel_ring_emit(ring, fb->pitches[0]);
7354         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7355         intel_ring_emit(ring, 0); /* aux display base address, unused */
7356
7357         intel_mark_page_flip_active(intel_crtc);
7358         intel_ring_advance(ring);
7359         return 0;
7360
7361 err_unpin:
7362         intel_unpin_fb_obj(obj);
7363 err:
7364         return ret;
7365 }
7366
7367 static int intel_gen3_queue_flip(struct drm_device *dev,
7368                                  struct drm_crtc *crtc,
7369                                  struct drm_framebuffer *fb,
7370                                  struct drm_i915_gem_object *obj)
7371 {
7372         struct drm_i915_private *dev_priv = dev->dev_private;
7373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7374         u32 flip_mask;
7375         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7376         int ret;
7377
7378         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7379         if (ret)
7380                 goto err;
7381
7382         ret = intel_ring_begin(ring, 6);
7383         if (ret)
7384                 goto err_unpin;
7385
7386         if (intel_crtc->plane)
7387                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7388         else
7389                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7390         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7391         intel_ring_emit(ring, MI_NOOP);
7392         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7393                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7394         intel_ring_emit(ring, fb->pitches[0]);
7395         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7396         intel_ring_emit(ring, MI_NOOP);
7397
7398         intel_mark_page_flip_active(intel_crtc);
7399         intel_ring_advance(ring);
7400         return 0;
7401
7402 err_unpin:
7403         intel_unpin_fb_obj(obj);
7404 err:
7405         return ret;
7406 }
7407
7408 static int intel_gen4_queue_flip(struct drm_device *dev,
7409                                  struct drm_crtc *crtc,
7410                                  struct drm_framebuffer *fb,
7411                                  struct drm_i915_gem_object *obj)
7412 {
7413         struct drm_i915_private *dev_priv = dev->dev_private;
7414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415         uint32_t pf, pipesrc;
7416         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7417         int ret;
7418
7419         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7420         if (ret)
7421                 goto err;
7422
7423         ret = intel_ring_begin(ring, 4);
7424         if (ret)
7425                 goto err_unpin;
7426
7427         /* i965+ uses the linear or tiled offsets from the
7428          * Display Registers (which do not change across a page-flip)
7429          * so we need only reprogram the base address.
7430          */
7431         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7432                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7433         intel_ring_emit(ring, fb->pitches[0]);
7434         intel_ring_emit(ring,
7435                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7436                         obj->tiling_mode);
7437
7438         /* XXX Enabling the panel-fitter across page-flip is so far
7439          * untested on non-native modes, so ignore it for now.
7440          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7441          */
7442         pf = 0;
7443         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7444         intel_ring_emit(ring, pf | pipesrc);
7445
7446         intel_mark_page_flip_active(intel_crtc);
7447         intel_ring_advance(ring);
7448         return 0;
7449
7450 err_unpin:
7451         intel_unpin_fb_obj(obj);
7452 err:
7453         return ret;
7454 }
7455
7456 static int intel_gen6_queue_flip(struct drm_device *dev,
7457                                  struct drm_crtc *crtc,
7458                                  struct drm_framebuffer *fb,
7459                                  struct drm_i915_gem_object *obj)
7460 {
7461         struct drm_i915_private *dev_priv = dev->dev_private;
7462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7463         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7464         uint32_t pf, pipesrc;
7465         int ret;
7466
7467         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7468         if (ret)
7469                 goto err;
7470
7471         ret = intel_ring_begin(ring, 4);
7472         if (ret)
7473                 goto err_unpin;
7474
7475         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7476                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7477         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7478         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7479
7480         /* Contrary to the suggestions in the documentation,
7481          * "Enable Panel Fitter" does not seem to be required when page
7482          * flipping with a non-native mode, and worse causes a normal
7483          * modeset to fail.
7484          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7485          */
7486         pf = 0;
7487         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7488         intel_ring_emit(ring, pf | pipesrc);
7489
7490         intel_mark_page_flip_active(intel_crtc);
7491         intel_ring_advance(ring);
7492         return 0;
7493
7494 err_unpin:
7495         intel_unpin_fb_obj(obj);
7496 err:
7497         return ret;
7498 }
7499
7500 /*
7501  * On gen7 we currently use the blit ring because (in early silicon at least)
7502  * the render ring doesn't give us interrpts for page flip completion, which
7503  * means clients will hang after the first flip is queued.  Fortunately the
7504  * blit ring generates interrupts properly, so use it instead.
7505  */
7506 static int intel_gen7_queue_flip(struct drm_device *dev,
7507                                  struct drm_crtc *crtc,
7508                                  struct drm_framebuffer *fb,
7509                                  struct drm_i915_gem_object *obj)
7510 {
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7513         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7514         uint32_t plane_bit = 0;
7515         int ret;
7516
7517         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7518         if (ret)
7519                 goto err;
7520
7521         switch(intel_crtc->plane) {
7522         case PLANE_A:
7523                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7524                 break;
7525         case PLANE_B:
7526                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7527                 break;
7528         case PLANE_C:
7529                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7530                 break;
7531         default:
7532                 WARN_ONCE(1, "unknown plane in flip command\n");
7533                 ret = -ENODEV;
7534                 goto err_unpin;
7535         }
7536
7537         ret = intel_ring_begin(ring, 4);
7538         if (ret)
7539                 goto err_unpin;
7540
7541         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7542         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7543         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7544         intel_ring_emit(ring, (MI_NOOP));
7545
7546         intel_mark_page_flip_active(intel_crtc);
7547         intel_ring_advance(ring);
7548         return 0;
7549
7550 err_unpin:
7551         intel_unpin_fb_obj(obj);
7552 err:
7553         return ret;
7554 }
7555
7556 static int intel_default_queue_flip(struct drm_device *dev,
7557                                     struct drm_crtc *crtc,
7558                                     struct drm_framebuffer *fb,
7559                                     struct drm_i915_gem_object *obj)
7560 {
7561         return -ENODEV;
7562 }
7563
7564 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7565                                 struct drm_framebuffer *fb,
7566                                 struct drm_pending_vblank_event *event)
7567 {
7568         struct drm_device *dev = crtc->dev;
7569         struct drm_i915_private *dev_priv = dev->dev_private;
7570         struct drm_framebuffer *old_fb = crtc->fb;
7571         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7573         struct intel_unpin_work *work;
7574         unsigned long flags;
7575         int ret;
7576
7577         /* Can't change pixel format via MI display flips. */
7578         if (fb->pixel_format != crtc->fb->pixel_format)
7579                 return -EINVAL;
7580
7581         /*
7582          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7583          * Note that pitch changes could also affect these register.
7584          */
7585         if (INTEL_INFO(dev)->gen > 3 &&
7586             (fb->offsets[0] != crtc->fb->offsets[0] ||
7587              fb->pitches[0] != crtc->fb->pitches[0]))
7588                 return -EINVAL;
7589
7590         work = kzalloc(sizeof *work, GFP_KERNEL);
7591         if (work == NULL)
7592                 return -ENOMEM;
7593
7594         work->event = event;
7595         work->crtc = crtc;
7596         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7597         INIT_WORK(&work->work, intel_unpin_work_fn);
7598
7599         ret = drm_vblank_get(dev, intel_crtc->pipe);
7600         if (ret)
7601                 goto free_work;
7602
7603         /* We borrow the event spin lock for protecting unpin_work */
7604         spin_lock_irqsave(&dev->event_lock, flags);
7605         if (intel_crtc->unpin_work) {
7606                 spin_unlock_irqrestore(&dev->event_lock, flags);
7607                 kfree(work);
7608                 drm_vblank_put(dev, intel_crtc->pipe);
7609
7610                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7611                 return -EBUSY;
7612         }
7613         intel_crtc->unpin_work = work;
7614         spin_unlock_irqrestore(&dev->event_lock, flags);
7615
7616         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7617                 flush_workqueue(dev_priv->wq);
7618
7619         ret = i915_mutex_lock_interruptible(dev);
7620         if (ret)
7621                 goto cleanup;
7622
7623         /* Reference the objects for the scheduled work. */
7624         drm_gem_object_reference(&work->old_fb_obj->base);
7625         drm_gem_object_reference(&obj->base);
7626
7627         crtc->fb = fb;
7628
7629         work->pending_flip_obj = obj;
7630
7631         work->enable_stall_check = true;
7632
7633         atomic_inc(&intel_crtc->unpin_work_count);
7634         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7635
7636         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7637         if (ret)
7638                 goto cleanup_pending;
7639
7640         intel_disable_fbc(dev);
7641         intel_mark_fb_busy(obj, NULL);
7642         mutex_unlock(&dev->struct_mutex);
7643
7644         trace_i915_flip_request(intel_crtc->plane, obj);
7645
7646         return 0;
7647
7648 cleanup_pending:
7649         atomic_dec(&intel_crtc->unpin_work_count);
7650         crtc->fb = old_fb;
7651         drm_gem_object_unreference(&work->old_fb_obj->base);
7652         drm_gem_object_unreference(&obj->base);
7653         mutex_unlock(&dev->struct_mutex);
7654
7655 cleanup:
7656         spin_lock_irqsave(&dev->event_lock, flags);
7657         intel_crtc->unpin_work = NULL;
7658         spin_unlock_irqrestore(&dev->event_lock, flags);
7659
7660         drm_vblank_put(dev, intel_crtc->pipe);
7661 free_work:
7662         kfree(work);
7663
7664         return ret;
7665 }
7666
7667 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7668         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7669         .load_lut = intel_crtc_load_lut,
7670 };
7671
7672 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7673                                   struct drm_crtc *crtc)
7674 {
7675         struct drm_device *dev;
7676         struct drm_crtc *tmp;
7677         int crtc_mask = 1;
7678
7679         WARN(!crtc, "checking null crtc?\n");
7680
7681         dev = crtc->dev;
7682
7683         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7684                 if (tmp == crtc)
7685                         break;
7686                 crtc_mask <<= 1;
7687         }
7688
7689         if (encoder->possible_crtcs & crtc_mask)
7690                 return true;
7691         return false;
7692 }
7693
7694 /**
7695  * intel_modeset_update_staged_output_state
7696  *
7697  * Updates the staged output configuration state, e.g. after we've read out the
7698  * current hw state.
7699  */
7700 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7701 {
7702         struct intel_encoder *encoder;
7703         struct intel_connector *connector;
7704
7705         list_for_each_entry(connector, &dev->mode_config.connector_list,
7706                             base.head) {
7707                 connector->new_encoder =
7708                         to_intel_encoder(connector->base.encoder);
7709         }
7710
7711         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7712                             base.head) {
7713                 encoder->new_crtc =
7714                         to_intel_crtc(encoder->base.crtc);
7715         }
7716 }
7717
7718 /**
7719  * intel_modeset_commit_output_state
7720  *
7721  * This function copies the stage display pipe configuration to the real one.
7722  */
7723 static void intel_modeset_commit_output_state(struct drm_device *dev)
7724 {
7725         struct intel_encoder *encoder;
7726         struct intel_connector *connector;
7727
7728         list_for_each_entry(connector, &dev->mode_config.connector_list,
7729                             base.head) {
7730                 connector->base.encoder = &connector->new_encoder->base;
7731         }
7732
7733         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7734                             base.head) {
7735                 encoder->base.crtc = &encoder->new_crtc->base;
7736         }
7737 }
7738
7739 static void
7740 connected_sink_compute_bpp(struct intel_connector * connector,
7741                            struct intel_crtc_config *pipe_config)
7742 {
7743         int bpp = pipe_config->pipe_bpp;
7744
7745         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7746                 connector->base.base.id,
7747                 drm_get_connector_name(&connector->base));
7748
7749         /* Don't use an invalid EDID bpc value */
7750         if (connector->base.display_info.bpc &&
7751             connector->base.display_info.bpc * 3 < bpp) {
7752                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7753                               bpp, connector->base.display_info.bpc*3);
7754                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7755         }
7756
7757         /* Clamp bpp to 8 on screens without EDID 1.4 */
7758         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7759                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7760                               bpp);
7761                 pipe_config->pipe_bpp = 24;
7762         }
7763 }
7764
7765 static int
7766 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7767                           struct drm_framebuffer *fb,
7768                           struct intel_crtc_config *pipe_config)
7769 {
7770         struct drm_device *dev = crtc->base.dev;
7771         struct intel_connector *connector;
7772         int bpp;
7773
7774         switch (fb->pixel_format) {
7775         case DRM_FORMAT_C8:
7776                 bpp = 8*3; /* since we go through a colormap */
7777                 break;
7778         case DRM_FORMAT_XRGB1555:
7779         case DRM_FORMAT_ARGB1555:
7780                 /* checked in intel_framebuffer_init already */
7781                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7782                         return -EINVAL;
7783         case DRM_FORMAT_RGB565:
7784                 bpp = 6*3; /* min is 18bpp */
7785                 break;
7786         case DRM_FORMAT_XBGR8888:
7787         case DRM_FORMAT_ABGR8888:
7788                 /* checked in intel_framebuffer_init already */
7789                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7790                         return -EINVAL;
7791         case DRM_FORMAT_XRGB8888:
7792         case DRM_FORMAT_ARGB8888:
7793                 bpp = 8*3;
7794                 break;
7795         case DRM_FORMAT_XRGB2101010:
7796         case DRM_FORMAT_ARGB2101010:
7797         case DRM_FORMAT_XBGR2101010:
7798         case DRM_FORMAT_ABGR2101010:
7799                 /* checked in intel_framebuffer_init already */
7800                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7801                         return -EINVAL;
7802                 bpp = 10*3;
7803                 break;
7804         /* TODO: gen4+ supports 16 bpc floating point, too. */
7805         default:
7806                 DRM_DEBUG_KMS("unsupported depth\n");
7807                 return -EINVAL;
7808         }
7809
7810         pipe_config->pipe_bpp = bpp;
7811
7812         /* Clamp display bpp to EDID value */
7813         list_for_each_entry(connector, &dev->mode_config.connector_list,
7814                             base.head) {
7815                 if (!connector->new_encoder ||
7816                     connector->new_encoder->new_crtc != crtc)
7817                         continue;
7818
7819                 connected_sink_compute_bpp(connector, pipe_config);
7820         }
7821
7822         return bpp;
7823 }
7824
7825 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7826                                    struct intel_crtc_config *pipe_config,
7827                                    const char *context)
7828 {
7829         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7830                       context, pipe_name(crtc->pipe));
7831
7832         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7833         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7834                       pipe_config->pipe_bpp, pipe_config->dither);
7835         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7836                       pipe_config->has_pch_encoder,
7837                       pipe_config->fdi_lanes,
7838                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7839                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7840                       pipe_config->fdi_m_n.tu);
7841         DRM_DEBUG_KMS("requested mode:\n");
7842         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7843         DRM_DEBUG_KMS("adjusted mode:\n");
7844         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7845         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7846                       pipe_config->gmch_pfit.control,
7847                       pipe_config->gmch_pfit.pgm_ratios,
7848                       pipe_config->gmch_pfit.lvds_border_bits);
7849         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7850                       pipe_config->pch_pfit.pos,
7851                       pipe_config->pch_pfit.size);
7852         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7853 }
7854
7855 static bool check_encoder_cloning(struct drm_crtc *crtc)
7856 {
7857         int num_encoders = 0;
7858         bool uncloneable_encoders = false;
7859         struct intel_encoder *encoder;
7860
7861         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7862                             base.head) {
7863                 if (&encoder->new_crtc->base != crtc)
7864                         continue;
7865
7866                 num_encoders++;
7867                 if (!encoder->cloneable)
7868                         uncloneable_encoders = true;
7869         }
7870
7871         return !(num_encoders > 1 && uncloneable_encoders);
7872 }
7873
7874 static struct intel_crtc_config *
7875 intel_modeset_pipe_config(struct drm_crtc *crtc,
7876                           struct drm_framebuffer *fb,
7877                           struct drm_display_mode *mode)
7878 {
7879         struct drm_device *dev = crtc->dev;
7880         struct drm_encoder_helper_funcs *encoder_funcs;
7881         struct intel_encoder *encoder;
7882         struct intel_crtc_config *pipe_config;
7883         int plane_bpp, ret = -EINVAL;
7884         bool retry = true;
7885
7886         if (!check_encoder_cloning(crtc)) {
7887                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7888                 return ERR_PTR(-EINVAL);
7889         }
7890
7891         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7892         if (!pipe_config)
7893                 return ERR_PTR(-ENOMEM);
7894
7895         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7896         drm_mode_copy(&pipe_config->requested_mode, mode);
7897         pipe_config->cpu_transcoder =
7898                 (enum transcoder) to_intel_crtc(crtc)->pipe;
7899         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7900
7901         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7902          * plane pixel format and any sink constraints into account. Returns the
7903          * source plane bpp so that dithering can be selected on mismatches
7904          * after encoders and crtc also have had their say. */
7905         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7906                                               fb, pipe_config);
7907         if (plane_bpp < 0)
7908                 goto fail;
7909
7910 encoder_retry:
7911         /* Ensure the port clock defaults are reset when retrying. */
7912         pipe_config->port_clock = 0;
7913         pipe_config->pixel_multiplier = 1;
7914
7915         /* Pass our mode to the connectors and the CRTC to give them a chance to
7916          * adjust it according to limitations or connector properties, and also
7917          * a chance to reject the mode entirely.
7918          */
7919         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7920                             base.head) {
7921
7922                 if (&encoder->new_crtc->base != crtc)
7923                         continue;
7924
7925                 if (encoder->compute_config) {
7926                         if (!(encoder->compute_config(encoder, pipe_config))) {
7927                                 DRM_DEBUG_KMS("Encoder config failure\n");
7928                                 goto fail;
7929                         }
7930
7931                         continue;
7932                 }
7933
7934                 encoder_funcs = encoder->base.helper_private;
7935                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7936                                                 &pipe_config->requested_mode,
7937                                                 &pipe_config->adjusted_mode))) {
7938                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7939                         goto fail;
7940                 }
7941         }
7942
7943         /* Set default port clock if not overwritten by the encoder. Needs to be
7944          * done afterwards in case the encoder adjusts the mode. */
7945         if (!pipe_config->port_clock)
7946                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7947
7948         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7949         if (ret < 0) {
7950                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7951                 goto fail;
7952         }
7953
7954         if (ret == RETRY) {
7955                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7956                         ret = -EINVAL;
7957                         goto fail;
7958                 }
7959
7960                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7961                 retry = false;
7962                 goto encoder_retry;
7963         }
7964
7965         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7966         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7967                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7968
7969         return pipe_config;
7970 fail:
7971         kfree(pipe_config);
7972         return ERR_PTR(ret);
7973 }
7974
7975 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7976  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7977 static void
7978 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7979                              unsigned *prepare_pipes, unsigned *disable_pipes)
7980 {
7981         struct intel_crtc *intel_crtc;
7982         struct drm_device *dev = crtc->dev;
7983         struct intel_encoder *encoder;
7984         struct intel_connector *connector;
7985         struct drm_crtc *tmp_crtc;
7986
7987         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7988
7989         /* Check which crtcs have changed outputs connected to them, these need
7990          * to be part of the prepare_pipes mask. We don't (yet) support global
7991          * modeset across multiple crtcs, so modeset_pipes will only have one
7992          * bit set at most. */
7993         list_for_each_entry(connector, &dev->mode_config.connector_list,
7994                             base.head) {
7995                 if (connector->base.encoder == &connector->new_encoder->base)
7996                         continue;
7997
7998                 if (connector->base.encoder) {
7999                         tmp_crtc = connector->base.encoder->crtc;
8000
8001                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8002                 }
8003
8004                 if (connector->new_encoder)
8005                         *prepare_pipes |=
8006                                 1 << connector->new_encoder->new_crtc->pipe;
8007         }
8008
8009         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8010                             base.head) {
8011                 if (encoder->base.crtc == &encoder->new_crtc->base)
8012                         continue;
8013
8014                 if (encoder->base.crtc) {
8015                         tmp_crtc = encoder->base.crtc;
8016
8017                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8018                 }
8019
8020                 if (encoder->new_crtc)
8021                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8022         }
8023
8024         /* Check for any pipes that will be fully disabled ... */
8025         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8026                             base.head) {
8027                 bool used = false;
8028
8029                 /* Don't try to disable disabled crtcs. */
8030                 if (!intel_crtc->base.enabled)
8031                         continue;
8032
8033                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8034                                     base.head) {
8035                         if (encoder->new_crtc == intel_crtc)
8036                                 used = true;
8037                 }
8038
8039                 if (!used)
8040                         *disable_pipes |= 1 << intel_crtc->pipe;
8041         }
8042
8043
8044         /* set_mode is also used to update properties on life display pipes. */
8045         intel_crtc = to_intel_crtc(crtc);
8046         if (crtc->enabled)
8047                 *prepare_pipes |= 1 << intel_crtc->pipe;
8048
8049         /*
8050          * For simplicity do a full modeset on any pipe where the output routing
8051          * changed. We could be more clever, but that would require us to be
8052          * more careful with calling the relevant encoder->mode_set functions.
8053          */
8054         if (*prepare_pipes)
8055                 *modeset_pipes = *prepare_pipes;
8056
8057         /* ... and mask these out. */
8058         *modeset_pipes &= ~(*disable_pipes);
8059         *prepare_pipes &= ~(*disable_pipes);
8060
8061         /*
8062          * HACK: We don't (yet) fully support global modesets. intel_set_config
8063          * obies this rule, but the modeset restore mode of
8064          * intel_modeset_setup_hw_state does not.
8065          */
8066         *modeset_pipes &= 1 << intel_crtc->pipe;
8067         *prepare_pipes &= 1 << intel_crtc->pipe;
8068
8069         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8070                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8071 }
8072
8073 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8074 {
8075         struct drm_encoder *encoder;
8076         struct drm_device *dev = crtc->dev;
8077
8078         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8079                 if (encoder->crtc == crtc)
8080                         return true;
8081
8082         return false;
8083 }
8084
8085 static void
8086 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8087 {
8088         struct intel_encoder *intel_encoder;
8089         struct intel_crtc *intel_crtc;
8090         struct drm_connector *connector;
8091
8092         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8093                             base.head) {
8094                 if (!intel_encoder->base.crtc)
8095                         continue;
8096
8097                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8098
8099                 if (prepare_pipes & (1 << intel_crtc->pipe))
8100                         intel_encoder->connectors_active = false;
8101         }
8102
8103         intel_modeset_commit_output_state(dev);
8104
8105         /* Update computed state. */
8106         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8107                             base.head) {
8108                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8109         }
8110
8111         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8112                 if (!connector->encoder || !connector->encoder->crtc)
8113                         continue;
8114
8115                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8116
8117                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8118                         struct drm_property *dpms_property =
8119                                 dev->mode_config.dpms_property;
8120
8121                         connector->dpms = DRM_MODE_DPMS_ON;
8122                         drm_object_property_set_value(&connector->base,
8123                                                          dpms_property,
8124                                                          DRM_MODE_DPMS_ON);
8125
8126                         intel_encoder = to_intel_encoder(connector->encoder);
8127                         intel_encoder->connectors_active = true;
8128                 }
8129         }
8130
8131 }
8132
8133 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8134                                     struct intel_crtc_config *new)
8135 {
8136         int clock1, clock2, diff;
8137
8138         clock1 = cur->adjusted_mode.clock;
8139         clock2 = new->adjusted_mode.clock;
8140
8141         if (clock1 == clock2)
8142                 return true;
8143
8144         if (!clock1 || !clock2)
8145                 return false;
8146
8147         diff = abs(clock1 - clock2);
8148
8149         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8150                 return true;
8151
8152         return false;
8153 }
8154
8155 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8156         list_for_each_entry((intel_crtc), \
8157                             &(dev)->mode_config.crtc_list, \
8158                             base.head) \
8159                 if (mask & (1 <<(intel_crtc)->pipe))
8160
8161 static bool
8162 intel_pipe_config_compare(struct drm_device *dev,
8163                           struct intel_crtc_config *current_config,
8164                           struct intel_crtc_config *pipe_config)
8165 {
8166 #define PIPE_CONF_CHECK_X(name) \
8167         if (current_config->name != pipe_config->name) { \
8168                 DRM_ERROR("mismatch in " #name " " \
8169                           "(expected 0x%08x, found 0x%08x)\n", \
8170                           current_config->name, \
8171                           pipe_config->name); \
8172                 return false; \
8173         }
8174
8175 #define PIPE_CONF_CHECK_I(name) \
8176         if (current_config->name != pipe_config->name) { \
8177                 DRM_ERROR("mismatch in " #name " " \
8178                           "(expected %i, found %i)\n", \
8179                           current_config->name, \
8180                           pipe_config->name); \
8181                 return false; \
8182         }
8183
8184 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8185         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8186                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8187                           "(expected %i, found %i)\n", \
8188                           current_config->name & (mask), \
8189                           pipe_config->name & (mask)); \
8190                 return false; \
8191         }
8192
8193 #define PIPE_CONF_QUIRK(quirk)  \
8194         ((current_config->quirks | pipe_config->quirks) & (quirk))
8195
8196         PIPE_CONF_CHECK_I(cpu_transcoder);
8197
8198         PIPE_CONF_CHECK_I(has_pch_encoder);
8199         PIPE_CONF_CHECK_I(fdi_lanes);
8200         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8201         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8202         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8203         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8204         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8205
8206         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8207         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8208         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8209         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8210         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8211         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8212
8213         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8214         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8215         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8216         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8217         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8218         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8219
8220         PIPE_CONF_CHECK_I(pixel_multiplier);
8221
8222         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8223                               DRM_MODE_FLAG_INTERLACE);
8224
8225         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8226                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8227                                       DRM_MODE_FLAG_PHSYNC);
8228                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8229                                       DRM_MODE_FLAG_NHSYNC);
8230                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8231                                       DRM_MODE_FLAG_PVSYNC);
8232                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8233                                       DRM_MODE_FLAG_NVSYNC);
8234         }
8235
8236         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8237         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8238
8239         PIPE_CONF_CHECK_I(gmch_pfit.control);
8240         /* pfit ratios are autocomputed by the hw on gen4+ */
8241         if (INTEL_INFO(dev)->gen < 4)
8242                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8243         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8244         PIPE_CONF_CHECK_I(pch_pfit.pos);
8245         PIPE_CONF_CHECK_I(pch_pfit.size);
8246
8247         PIPE_CONF_CHECK_I(ips_enabled);
8248
8249         PIPE_CONF_CHECK_I(shared_dpll);
8250         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8251         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8252         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8253         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8254
8255 #undef PIPE_CONF_CHECK_X
8256 #undef PIPE_CONF_CHECK_I
8257 #undef PIPE_CONF_CHECK_FLAGS
8258 #undef PIPE_CONF_QUIRK
8259
8260         if (!IS_HASWELL(dev)) {
8261                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8262                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8263                                   current_config->adjusted_mode.clock,
8264                                   pipe_config->adjusted_mode.clock);
8265                         return false;
8266                 }
8267         }
8268
8269         return true;
8270 }
8271
8272 static void
8273 check_connector_state(struct drm_device *dev)
8274 {
8275         struct intel_connector *connector;
8276
8277         list_for_each_entry(connector, &dev->mode_config.connector_list,
8278                             base.head) {
8279                 /* This also checks the encoder/connector hw state with the
8280                  * ->get_hw_state callbacks. */
8281                 intel_connector_check_state(connector);
8282
8283                 WARN(&connector->new_encoder->base != connector->base.encoder,
8284                      "connector's staged encoder doesn't match current encoder\n");
8285         }
8286 }
8287
8288 static void
8289 check_encoder_state(struct drm_device *dev)
8290 {
8291         struct intel_encoder *encoder;
8292         struct intel_connector *connector;
8293
8294         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8295                             base.head) {
8296                 bool enabled = false;
8297                 bool active = false;
8298                 enum pipe pipe, tracked_pipe;
8299
8300                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8301                               encoder->base.base.id,
8302                               drm_get_encoder_name(&encoder->base));
8303
8304                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8305                      "encoder's stage crtc doesn't match current crtc\n");
8306                 WARN(encoder->connectors_active && !encoder->base.crtc,
8307                      "encoder's active_connectors set, but no crtc\n");
8308
8309                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8310                                     base.head) {
8311                         if (connector->base.encoder != &encoder->base)
8312                                 continue;
8313                         enabled = true;
8314                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8315                                 active = true;
8316                 }
8317                 WARN(!!encoder->base.crtc != enabled,
8318                      "encoder's enabled state mismatch "
8319                      "(expected %i, found %i)\n",
8320                      !!encoder->base.crtc, enabled);
8321                 WARN(active && !encoder->base.crtc,
8322                      "active encoder with no crtc\n");
8323
8324                 WARN(encoder->connectors_active != active,
8325                      "encoder's computed active state doesn't match tracked active state "
8326                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8327
8328                 active = encoder->get_hw_state(encoder, &pipe);
8329                 WARN(active != encoder->connectors_active,
8330                      "encoder's hw state doesn't match sw tracking "
8331                      "(expected %i, found %i)\n",
8332                      encoder->connectors_active, active);
8333
8334                 if (!encoder->base.crtc)
8335                         continue;
8336
8337                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8338                 WARN(active && pipe != tracked_pipe,
8339                      "active encoder's pipe doesn't match"
8340                      "(expected %i, found %i)\n",
8341                      tracked_pipe, pipe);
8342
8343         }
8344 }
8345
8346 static void
8347 check_crtc_state(struct drm_device *dev)
8348 {
8349         drm_i915_private_t *dev_priv = dev->dev_private;
8350         struct intel_crtc *crtc;
8351         struct intel_encoder *encoder;
8352         struct intel_crtc_config pipe_config;
8353
8354         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8355                             base.head) {
8356                 bool enabled = false;
8357                 bool active = false;
8358
8359                 memset(&pipe_config, 0, sizeof(pipe_config));
8360
8361                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8362                               crtc->base.base.id);
8363
8364                 WARN(crtc->active && !crtc->base.enabled,
8365                      "active crtc, but not enabled in sw tracking\n");
8366
8367                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8368                                     base.head) {
8369                         if (encoder->base.crtc != &crtc->base)
8370                                 continue;
8371                         enabled = true;
8372                         if (encoder->connectors_active)
8373                                 active = true;
8374                 }
8375
8376                 WARN(active != crtc->active,
8377                      "crtc's computed active state doesn't match tracked active state "
8378                      "(expected %i, found %i)\n", active, crtc->active);
8379                 WARN(enabled != crtc->base.enabled,
8380                      "crtc's computed enabled state doesn't match tracked enabled state "
8381                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8382
8383                 active = dev_priv->display.get_pipe_config(crtc,
8384                                                            &pipe_config);
8385
8386                 /* hw state is inconsistent with the pipe A quirk */
8387                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8388                         active = crtc->active;
8389
8390                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8391                                     base.head) {
8392                         if (encoder->base.crtc != &crtc->base)
8393                                 continue;
8394                         if (encoder->get_config)
8395                                 encoder->get_config(encoder, &pipe_config);
8396                 }
8397
8398                 if (dev_priv->display.get_clock)
8399                         dev_priv->display.get_clock(crtc, &pipe_config);
8400
8401                 WARN(crtc->active != active,
8402                      "crtc active state doesn't match with hw state "
8403                      "(expected %i, found %i)\n", crtc->active, active);
8404
8405                 if (active &&
8406                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8407                         WARN(1, "pipe state doesn't match!\n");
8408                         intel_dump_pipe_config(crtc, &pipe_config,
8409                                                "[hw state]");
8410                         intel_dump_pipe_config(crtc, &crtc->config,
8411                                                "[sw state]");
8412                 }
8413         }
8414 }
8415
8416 static void
8417 check_shared_dpll_state(struct drm_device *dev)
8418 {
8419         drm_i915_private_t *dev_priv = dev->dev_private;
8420         struct intel_crtc *crtc;
8421         struct intel_dpll_hw_state dpll_hw_state;
8422         int i;
8423
8424         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8425                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8426                 int enabled_crtcs = 0, active_crtcs = 0;
8427                 bool active;
8428
8429                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8430
8431                 DRM_DEBUG_KMS("%s\n", pll->name);
8432
8433                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8434
8435                 WARN(pll->active > pll->refcount,
8436                      "more active pll users than references: %i vs %i\n",
8437                      pll->active, pll->refcount);
8438                 WARN(pll->active && !pll->on,
8439                      "pll in active use but not on in sw tracking\n");
8440                 WARN(pll->on != active,
8441                      "pll on state mismatch (expected %i, found %i)\n",
8442                      pll->on, active);
8443
8444                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8445                                     base.head) {
8446                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8447                                 enabled_crtcs++;
8448                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8449                                 active_crtcs++;
8450                 }
8451                 WARN(pll->active != active_crtcs,
8452                      "pll active crtcs mismatch (expected %i, found %i)\n",
8453                      pll->active, active_crtcs);
8454                 WARN(pll->refcount != enabled_crtcs,
8455                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8456                      pll->refcount, enabled_crtcs);
8457
8458                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8459                                        sizeof(dpll_hw_state)),
8460                      "pll hw state mismatch\n");
8461         }
8462 }
8463
8464 void
8465 intel_modeset_check_state(struct drm_device *dev)
8466 {
8467         check_connector_state(dev);
8468         check_encoder_state(dev);
8469         check_crtc_state(dev);
8470         check_shared_dpll_state(dev);
8471 }
8472
8473 static int __intel_set_mode(struct drm_crtc *crtc,
8474                             struct drm_display_mode *mode,
8475                             int x, int y, struct drm_framebuffer *fb)
8476 {
8477         struct drm_device *dev = crtc->dev;
8478         drm_i915_private_t *dev_priv = dev->dev_private;
8479         struct drm_display_mode *saved_mode, *saved_hwmode;
8480         struct intel_crtc_config *pipe_config = NULL;
8481         struct intel_crtc *intel_crtc;
8482         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8483         int ret = 0;
8484
8485         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8486         if (!saved_mode)
8487                 return -ENOMEM;
8488         saved_hwmode = saved_mode + 1;
8489
8490         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8491                                      &prepare_pipes, &disable_pipes);
8492
8493         *saved_hwmode = crtc->hwmode;
8494         *saved_mode = crtc->mode;
8495
8496         /* Hack: Because we don't (yet) support global modeset on multiple
8497          * crtcs, we don't keep track of the new mode for more than one crtc.
8498          * Hence simply check whether any bit is set in modeset_pipes in all the
8499          * pieces of code that are not yet converted to deal with mutliple crtcs
8500          * changing their mode at the same time. */
8501         if (modeset_pipes) {
8502                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8503                 if (IS_ERR(pipe_config)) {
8504                         ret = PTR_ERR(pipe_config);
8505                         pipe_config = NULL;
8506
8507                         goto out;
8508                 }
8509                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8510                                        "[modeset]");
8511         }
8512
8513         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8514                 intel_crtc_disable(&intel_crtc->base);
8515
8516         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8517                 if (intel_crtc->base.enabled)
8518                         dev_priv->display.crtc_disable(&intel_crtc->base);
8519         }
8520
8521         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8522          * to set it here already despite that we pass it down the callchain.
8523          */
8524         if (modeset_pipes) {
8525                 crtc->mode = *mode;
8526                 /* mode_set/enable/disable functions rely on a correct pipe
8527                  * config. */
8528                 to_intel_crtc(crtc)->config = *pipe_config;
8529         }
8530
8531         /* Only after disabling all output pipelines that will be changed can we
8532          * update the the output configuration. */
8533         intel_modeset_update_state(dev, prepare_pipes);
8534
8535         if (dev_priv->display.modeset_global_resources)
8536                 dev_priv->display.modeset_global_resources(dev);
8537
8538         /* Set up the DPLL and any encoders state that needs to adjust or depend
8539          * on the DPLL.
8540          */
8541         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8542                 ret = intel_crtc_mode_set(&intel_crtc->base,
8543                                           x, y, fb);
8544                 if (ret)
8545                         goto done;
8546         }
8547
8548         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8549         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8550                 dev_priv->display.crtc_enable(&intel_crtc->base);
8551
8552         if (modeset_pipes) {
8553                 /* Store real post-adjustment hardware mode. */
8554                 crtc->hwmode = pipe_config->adjusted_mode;
8555
8556                 /* Calculate and store various constants which
8557                  * are later needed by vblank and swap-completion
8558                  * timestamping. They are derived from true hwmode.
8559                  */
8560                 drm_calc_timestamping_constants(crtc);
8561         }
8562
8563         /* FIXME: add subpixel order */
8564 done:
8565         if (ret && crtc->enabled) {
8566                 crtc->hwmode = *saved_hwmode;
8567                 crtc->mode = *saved_mode;
8568         }
8569
8570 out:
8571         kfree(pipe_config);
8572         kfree(saved_mode);
8573         return ret;
8574 }
8575
8576 int intel_set_mode(struct drm_crtc *crtc,
8577                      struct drm_display_mode *mode,
8578                      int x, int y, struct drm_framebuffer *fb)
8579 {
8580         int ret;
8581
8582         ret = __intel_set_mode(crtc, mode, x, y, fb);
8583
8584         if (ret == 0)
8585                 intel_modeset_check_state(crtc->dev);
8586
8587         return ret;
8588 }
8589
8590 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8591 {
8592         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8593 }
8594
8595 #undef for_each_intel_crtc_masked
8596
8597 static void intel_set_config_free(struct intel_set_config *config)
8598 {
8599         if (!config)
8600                 return;
8601
8602         kfree(config->save_connector_encoders);
8603         kfree(config->save_encoder_crtcs);
8604         kfree(config);
8605 }
8606
8607 static int intel_set_config_save_state(struct drm_device *dev,
8608                                        struct intel_set_config *config)
8609 {
8610         struct drm_encoder *encoder;
8611         struct drm_connector *connector;
8612         int count;
8613
8614         config->save_encoder_crtcs =
8615                 kcalloc(dev->mode_config.num_encoder,
8616                         sizeof(struct drm_crtc *), GFP_KERNEL);
8617         if (!config->save_encoder_crtcs)
8618                 return -ENOMEM;
8619
8620         config->save_connector_encoders =
8621                 kcalloc(dev->mode_config.num_connector,
8622                         sizeof(struct drm_encoder *), GFP_KERNEL);
8623         if (!config->save_connector_encoders)
8624                 return -ENOMEM;
8625
8626         /* Copy data. Note that driver private data is not affected.
8627          * Should anything bad happen only the expected state is
8628          * restored, not the drivers personal bookkeeping.
8629          */
8630         count = 0;
8631         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8632                 config->save_encoder_crtcs[count++] = encoder->crtc;
8633         }
8634
8635         count = 0;
8636         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8637                 config->save_connector_encoders[count++] = connector->encoder;
8638         }
8639
8640         return 0;
8641 }
8642
8643 static void intel_set_config_restore_state(struct drm_device *dev,
8644                                            struct intel_set_config *config)
8645 {
8646         struct intel_encoder *encoder;
8647         struct intel_connector *connector;
8648         int count;
8649
8650         count = 0;
8651         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8652                 encoder->new_crtc =
8653                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8654         }
8655
8656         count = 0;
8657         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8658                 connector->new_encoder =
8659                         to_intel_encoder(config->save_connector_encoders[count++]);
8660         }
8661 }
8662
8663 static bool
8664 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8665                       int num_connectors)
8666 {
8667         int i;
8668
8669         for (i = 0; i < num_connectors; i++)
8670                 if (connectors[i].encoder &&
8671                     connectors[i].encoder->crtc == crtc &&
8672                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8673                         return true;
8674
8675         return false;
8676 }
8677
8678 static void
8679 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8680                                       struct intel_set_config *config)
8681 {
8682
8683         /* We should be able to check here if the fb has the same properties
8684          * and then just flip_or_move it */
8685         if (set->connectors != NULL &&
8686             is_crtc_connector_off(set->crtc, *set->connectors,
8687                                   set->num_connectors)) {
8688                         config->mode_changed = true;
8689         } else if (set->crtc->fb != set->fb) {
8690                 /* If we have no fb then treat it as a full mode set */
8691                 if (set->crtc->fb == NULL) {
8692                         struct intel_crtc *intel_crtc =
8693                                 to_intel_crtc(set->crtc);
8694
8695                         if (intel_crtc->active && i915_fastboot) {
8696                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8697                                 config->fb_changed = true;
8698                         } else {
8699                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8700                                 config->mode_changed = true;
8701                         }
8702                 } else if (set->fb == NULL) {
8703                         config->mode_changed = true;
8704                 } else if (set->fb->pixel_format !=
8705                            set->crtc->fb->pixel_format) {
8706                         config->mode_changed = true;
8707                 } else {
8708                         config->fb_changed = true;
8709                 }
8710         }
8711
8712         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8713                 config->fb_changed = true;
8714
8715         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8716                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8717                 drm_mode_debug_printmodeline(&set->crtc->mode);
8718                 drm_mode_debug_printmodeline(set->mode);
8719                 config->mode_changed = true;
8720         }
8721 }
8722
8723 static int
8724 intel_modeset_stage_output_state(struct drm_device *dev,
8725                                  struct drm_mode_set *set,
8726                                  struct intel_set_config *config)
8727 {
8728         struct drm_crtc *new_crtc;
8729         struct intel_connector *connector;
8730         struct intel_encoder *encoder;
8731         int count, ro;
8732
8733         /* The upper layers ensure that we either disable a crtc or have a list
8734          * of connectors. For paranoia, double-check this. */
8735         WARN_ON(!set->fb && (set->num_connectors != 0));
8736         WARN_ON(set->fb && (set->num_connectors == 0));
8737
8738         count = 0;
8739         list_for_each_entry(connector, &dev->mode_config.connector_list,
8740                             base.head) {
8741                 /* Otherwise traverse passed in connector list and get encoders
8742                  * for them. */
8743                 for (ro = 0; ro < set->num_connectors; ro++) {
8744                         if (set->connectors[ro] == &connector->base) {
8745                                 connector->new_encoder = connector->encoder;
8746                                 break;
8747                         }
8748                 }
8749
8750                 /* If we disable the crtc, disable all its connectors. Also, if
8751                  * the connector is on the changing crtc but not on the new
8752                  * connector list, disable it. */
8753                 if ((!set->fb || ro == set->num_connectors) &&
8754                     connector->base.encoder &&
8755                     connector->base.encoder->crtc == set->crtc) {
8756                         connector->new_encoder = NULL;
8757
8758                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8759                                 connector->base.base.id,
8760                                 drm_get_connector_name(&connector->base));
8761                 }
8762
8763
8764                 if (&connector->new_encoder->base != connector->base.encoder) {
8765                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8766                         config->mode_changed = true;
8767                 }
8768         }
8769         /* connector->new_encoder is now updated for all connectors. */
8770
8771         /* Update crtc of enabled connectors. */
8772         count = 0;
8773         list_for_each_entry(connector, &dev->mode_config.connector_list,
8774                             base.head) {
8775                 if (!connector->new_encoder)
8776                         continue;
8777
8778                 new_crtc = connector->new_encoder->base.crtc;
8779
8780                 for (ro = 0; ro < set->num_connectors; ro++) {
8781                         if (set->connectors[ro] == &connector->base)
8782                                 new_crtc = set->crtc;
8783                 }
8784
8785                 /* Make sure the new CRTC will work with the encoder */
8786                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8787                                            new_crtc)) {
8788                         return -EINVAL;
8789                 }
8790                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8791
8792                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8793                         connector->base.base.id,
8794                         drm_get_connector_name(&connector->base),
8795                         new_crtc->base.id);
8796         }
8797
8798         /* Check for any encoders that needs to be disabled. */
8799         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8800                             base.head) {
8801                 list_for_each_entry(connector,
8802                                     &dev->mode_config.connector_list,
8803                                     base.head) {
8804                         if (connector->new_encoder == encoder) {
8805                                 WARN_ON(!connector->new_encoder->new_crtc);
8806
8807                                 goto next_encoder;
8808                         }
8809                 }
8810                 encoder->new_crtc = NULL;
8811 next_encoder:
8812                 /* Only now check for crtc changes so we don't miss encoders
8813                  * that will be disabled. */
8814                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8815                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8816                         config->mode_changed = true;
8817                 }
8818         }
8819         /* Now we've also updated encoder->new_crtc for all encoders. */
8820
8821         return 0;
8822 }
8823
8824 static int intel_crtc_set_config(struct drm_mode_set *set)
8825 {
8826         struct drm_device *dev;
8827         struct drm_mode_set save_set;
8828         struct intel_set_config *config;
8829         int ret;
8830
8831         BUG_ON(!set);
8832         BUG_ON(!set->crtc);
8833         BUG_ON(!set->crtc->helper_private);
8834
8835         /* Enforce sane interface api - has been abused by the fb helper. */
8836         BUG_ON(!set->mode && set->fb);
8837         BUG_ON(set->fb && set->num_connectors == 0);
8838
8839         if (set->fb) {
8840                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8841                                 set->crtc->base.id, set->fb->base.id,
8842                                 (int)set->num_connectors, set->x, set->y);
8843         } else {
8844                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8845         }
8846
8847         dev = set->crtc->dev;
8848
8849         ret = -ENOMEM;
8850         config = kzalloc(sizeof(*config), GFP_KERNEL);
8851         if (!config)
8852                 goto out_config;
8853
8854         ret = intel_set_config_save_state(dev, config);
8855         if (ret)
8856                 goto out_config;
8857
8858         save_set.crtc = set->crtc;
8859         save_set.mode = &set->crtc->mode;
8860         save_set.x = set->crtc->x;
8861         save_set.y = set->crtc->y;
8862         save_set.fb = set->crtc->fb;
8863
8864         /* Compute whether we need a full modeset, only an fb base update or no
8865          * change at all. In the future we might also check whether only the
8866          * mode changed, e.g. for LVDS where we only change the panel fitter in
8867          * such cases. */
8868         intel_set_config_compute_mode_changes(set, config);
8869
8870         ret = intel_modeset_stage_output_state(dev, set, config);
8871         if (ret)
8872                 goto fail;
8873
8874         if (config->mode_changed) {
8875                 ret = intel_set_mode(set->crtc, set->mode,
8876                                      set->x, set->y, set->fb);
8877         } else if (config->fb_changed) {
8878                 intel_crtc_wait_for_pending_flips(set->crtc);
8879
8880                 ret = intel_pipe_set_base(set->crtc,
8881                                           set->x, set->y, set->fb);
8882         }
8883
8884         if (ret) {
8885                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8886                               set->crtc->base.id, ret);
8887 fail:
8888                 intel_set_config_restore_state(dev, config);
8889
8890                 /* Try to restore the config */
8891                 if (config->mode_changed &&
8892                     intel_set_mode(save_set.crtc, save_set.mode,
8893                                    save_set.x, save_set.y, save_set.fb))
8894                         DRM_ERROR("failed to restore config after modeset failure\n");
8895         }
8896
8897 out_config:
8898         intel_set_config_free(config);
8899         return ret;
8900 }
8901
8902 static const struct drm_crtc_funcs intel_crtc_funcs = {
8903         .cursor_set = intel_crtc_cursor_set,
8904         .cursor_move = intel_crtc_cursor_move,
8905         .gamma_set = intel_crtc_gamma_set,
8906         .set_config = intel_crtc_set_config,
8907         .destroy = intel_crtc_destroy,
8908         .page_flip = intel_crtc_page_flip,
8909 };
8910
8911 static void intel_cpu_pll_init(struct drm_device *dev)
8912 {
8913         if (HAS_DDI(dev))
8914                 intel_ddi_pll_init(dev);
8915 }
8916
8917 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8918                                       struct intel_shared_dpll *pll,
8919                                       struct intel_dpll_hw_state *hw_state)
8920 {
8921         uint32_t val;
8922
8923         val = I915_READ(PCH_DPLL(pll->id));
8924         hw_state->dpll = val;
8925         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8926         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8927
8928         return val & DPLL_VCO_ENABLE;
8929 }
8930
8931 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8932                                   struct intel_shared_dpll *pll)
8933 {
8934         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8935         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8936 }
8937
8938 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8939                                 struct intel_shared_dpll *pll)
8940 {
8941         /* PCH refclock must be enabled first */
8942         assert_pch_refclk_enabled(dev_priv);
8943
8944         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8945
8946         /* Wait for the clocks to stabilize. */
8947         POSTING_READ(PCH_DPLL(pll->id));
8948         udelay(150);
8949
8950         /* The pixel multiplier can only be updated once the
8951          * DPLL is enabled and the clocks are stable.
8952          *
8953          * So write it again.
8954          */
8955         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8956         POSTING_READ(PCH_DPLL(pll->id));
8957         udelay(200);
8958 }
8959
8960 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8961                                  struct intel_shared_dpll *pll)
8962 {
8963         struct drm_device *dev = dev_priv->dev;
8964         struct intel_crtc *crtc;
8965
8966         /* Make sure no transcoder isn't still depending on us. */
8967         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8968                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8969                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8970         }
8971
8972         I915_WRITE(PCH_DPLL(pll->id), 0);
8973         POSTING_READ(PCH_DPLL(pll->id));
8974         udelay(200);
8975 }
8976
8977 static char *ibx_pch_dpll_names[] = {
8978         "PCH DPLL A",
8979         "PCH DPLL B",
8980 };
8981
8982 static void ibx_pch_dpll_init(struct drm_device *dev)
8983 {
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         int i;
8986
8987         dev_priv->num_shared_dpll = 2;
8988
8989         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8990                 dev_priv->shared_dplls[i].id = i;
8991                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8992                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8993                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8994                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8995                 dev_priv->shared_dplls[i].get_hw_state =
8996                         ibx_pch_dpll_get_hw_state;
8997         }
8998 }
8999
9000 static void intel_shared_dpll_init(struct drm_device *dev)
9001 {
9002         struct drm_i915_private *dev_priv = dev->dev_private;
9003
9004         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9005                 ibx_pch_dpll_init(dev);
9006         else
9007                 dev_priv->num_shared_dpll = 0;
9008
9009         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9010         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9011                       dev_priv->num_shared_dpll);
9012 }
9013
9014 static void intel_crtc_init(struct drm_device *dev, int pipe)
9015 {
9016         drm_i915_private_t *dev_priv = dev->dev_private;
9017         struct intel_crtc *intel_crtc;
9018         int i;
9019
9020         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9021         if (intel_crtc == NULL)
9022                 return;
9023
9024         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9025
9026         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9027         for (i = 0; i < 256; i++) {
9028                 intel_crtc->lut_r[i] = i;
9029                 intel_crtc->lut_g[i] = i;
9030                 intel_crtc->lut_b[i] = i;
9031         }
9032
9033         /* Swap pipes & planes for FBC on pre-965 */
9034         intel_crtc->pipe = pipe;
9035         intel_crtc->plane = pipe;
9036         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9037                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9038                 intel_crtc->plane = !pipe;
9039         }
9040
9041         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9042                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9043         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9044         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9045
9046         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9047 }
9048
9049 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9050                                 struct drm_file *file)
9051 {
9052         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9053         struct drm_mode_object *drmmode_obj;
9054         struct intel_crtc *crtc;
9055
9056         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9057                 return -ENODEV;
9058
9059         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9060                         DRM_MODE_OBJECT_CRTC);
9061
9062         if (!drmmode_obj) {
9063                 DRM_ERROR("no such CRTC id\n");
9064                 return -EINVAL;
9065         }
9066
9067         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9068         pipe_from_crtc_id->pipe = crtc->pipe;
9069
9070         return 0;
9071 }
9072
9073 static int intel_encoder_clones(struct intel_encoder *encoder)
9074 {
9075         struct drm_device *dev = encoder->base.dev;
9076         struct intel_encoder *source_encoder;
9077         int index_mask = 0;
9078         int entry = 0;
9079
9080         list_for_each_entry(source_encoder,
9081                             &dev->mode_config.encoder_list, base.head) {
9082
9083                 if (encoder == source_encoder)
9084                         index_mask |= (1 << entry);
9085
9086                 /* Intel hw has only one MUX where enocoders could be cloned. */
9087                 if (encoder->cloneable && source_encoder->cloneable)
9088                         index_mask |= (1 << entry);
9089
9090                 entry++;
9091         }
9092
9093         return index_mask;
9094 }
9095
9096 static bool has_edp_a(struct drm_device *dev)
9097 {
9098         struct drm_i915_private *dev_priv = dev->dev_private;
9099
9100         if (!IS_MOBILE(dev))
9101                 return false;
9102
9103         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9104                 return false;
9105
9106         if (IS_GEN5(dev) &&
9107             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9108                 return false;
9109
9110         return true;
9111 }
9112
9113 static void intel_setup_outputs(struct drm_device *dev)
9114 {
9115         struct drm_i915_private *dev_priv = dev->dev_private;
9116         struct intel_encoder *encoder;
9117         bool dpd_is_edp = false;
9118
9119         intel_lvds_init(dev);
9120
9121         if (!IS_ULT(dev))
9122                 intel_crt_init(dev);
9123
9124         if (HAS_DDI(dev)) {
9125                 int found;
9126
9127                 /* Haswell uses DDI functions to detect digital outputs */
9128                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9129                 /* DDI A only supports eDP */
9130                 if (found)
9131                         intel_ddi_init(dev, PORT_A);
9132
9133                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9134                  * register */
9135                 found = I915_READ(SFUSE_STRAP);
9136
9137                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9138                         intel_ddi_init(dev, PORT_B);
9139                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9140                         intel_ddi_init(dev, PORT_C);
9141                 if (found & SFUSE_STRAP_DDID_DETECTED)
9142                         intel_ddi_init(dev, PORT_D);
9143         } else if (HAS_PCH_SPLIT(dev)) {
9144                 int found;
9145                 dpd_is_edp = intel_dpd_is_edp(dev);
9146
9147                 if (has_edp_a(dev))
9148                         intel_dp_init(dev, DP_A, PORT_A);
9149
9150                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9151                         /* PCH SDVOB multiplex with HDMIB */
9152                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9153                         if (!found)
9154                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9155                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9156                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9157                 }
9158
9159                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9160                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9161
9162                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9163                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9164
9165                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9166                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9167
9168                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9169                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9170         } else if (IS_VALLEYVIEW(dev)) {
9171                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9172                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9173                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9174
9175                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9176                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9177                                         PORT_B);
9178                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9179                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9180                 }
9181         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9182                 bool found = false;
9183
9184                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9185                         DRM_DEBUG_KMS("probing SDVOB\n");
9186                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9187                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9188                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9189                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9190                         }
9191
9192                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9193                                 intel_dp_init(dev, DP_B, PORT_B);
9194                 }
9195
9196                 /* Before G4X SDVOC doesn't have its own detect register */
9197
9198                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9199                         DRM_DEBUG_KMS("probing SDVOC\n");
9200                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9201                 }
9202
9203                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9204
9205                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9206                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9207                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9208                         }
9209                         if (SUPPORTS_INTEGRATED_DP(dev))
9210                                 intel_dp_init(dev, DP_C, PORT_C);
9211                 }
9212
9213                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9214                     (I915_READ(DP_D) & DP_DETECTED))
9215                         intel_dp_init(dev, DP_D, PORT_D);
9216         } else if (IS_GEN2(dev))
9217                 intel_dvo_init(dev);
9218
9219         if (SUPPORTS_TV(dev))
9220                 intel_tv_init(dev);
9221
9222         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9223                 encoder->base.possible_crtcs = encoder->crtc_mask;
9224                 encoder->base.possible_clones =
9225                         intel_encoder_clones(encoder);
9226         }
9227
9228         intel_init_pch_refclk(dev);
9229
9230         drm_helper_move_panel_connectors_to_head(dev);
9231 }
9232
9233 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9234 {
9235         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9236
9237         drm_framebuffer_cleanup(fb);
9238         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9239
9240         kfree(intel_fb);
9241 }
9242
9243 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9244                                                 struct drm_file *file,
9245                                                 unsigned int *handle)
9246 {
9247         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9248         struct drm_i915_gem_object *obj = intel_fb->obj;
9249
9250         return drm_gem_handle_create(file, &obj->base, handle);
9251 }
9252
9253 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9254         .destroy = intel_user_framebuffer_destroy,
9255         .create_handle = intel_user_framebuffer_create_handle,
9256 };
9257
9258 int intel_framebuffer_init(struct drm_device *dev,
9259                            struct intel_framebuffer *intel_fb,
9260                            struct drm_mode_fb_cmd2 *mode_cmd,
9261                            struct drm_i915_gem_object *obj)
9262 {
9263         int pitch_limit;
9264         int ret;
9265
9266         if (obj->tiling_mode == I915_TILING_Y) {
9267                 DRM_DEBUG("hardware does not support tiling Y\n");
9268                 return -EINVAL;
9269         }
9270
9271         if (mode_cmd->pitches[0] & 63) {
9272                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9273                           mode_cmd->pitches[0]);
9274                 return -EINVAL;
9275         }
9276
9277         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9278                 pitch_limit = 32*1024;
9279         } else if (INTEL_INFO(dev)->gen >= 4) {
9280                 if (obj->tiling_mode)
9281                         pitch_limit = 16*1024;
9282                 else
9283                         pitch_limit = 32*1024;
9284         } else if (INTEL_INFO(dev)->gen >= 3) {
9285                 if (obj->tiling_mode)
9286                         pitch_limit = 8*1024;
9287                 else
9288                         pitch_limit = 16*1024;
9289         } else
9290                 /* XXX DSPC is limited to 4k tiled */
9291                 pitch_limit = 8*1024;
9292
9293         if (mode_cmd->pitches[0] > pitch_limit) {
9294                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9295                           obj->tiling_mode ? "tiled" : "linear",
9296                           mode_cmd->pitches[0], pitch_limit);
9297                 return -EINVAL;
9298         }
9299
9300         if (obj->tiling_mode != I915_TILING_NONE &&
9301             mode_cmd->pitches[0] != obj->stride) {
9302                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9303                           mode_cmd->pitches[0], obj->stride);
9304                 return -EINVAL;
9305         }
9306
9307         /* Reject formats not supported by any plane early. */
9308         switch (mode_cmd->pixel_format) {
9309         case DRM_FORMAT_C8:
9310         case DRM_FORMAT_RGB565:
9311         case DRM_FORMAT_XRGB8888:
9312         case DRM_FORMAT_ARGB8888:
9313                 break;
9314         case DRM_FORMAT_XRGB1555:
9315         case DRM_FORMAT_ARGB1555:
9316                 if (INTEL_INFO(dev)->gen > 3) {
9317                         DRM_DEBUG("unsupported pixel format: %s\n",
9318                                   drm_get_format_name(mode_cmd->pixel_format));
9319                         return -EINVAL;
9320                 }
9321                 break;
9322         case DRM_FORMAT_XBGR8888:
9323         case DRM_FORMAT_ABGR8888:
9324         case DRM_FORMAT_XRGB2101010:
9325         case DRM_FORMAT_ARGB2101010:
9326         case DRM_FORMAT_XBGR2101010:
9327         case DRM_FORMAT_ABGR2101010:
9328                 if (INTEL_INFO(dev)->gen < 4) {
9329                         DRM_DEBUG("unsupported pixel format: %s\n",
9330                                   drm_get_format_name(mode_cmd->pixel_format));
9331                         return -EINVAL;
9332                 }
9333                 break;
9334         case DRM_FORMAT_YUYV:
9335         case DRM_FORMAT_UYVY:
9336         case DRM_FORMAT_YVYU:
9337         case DRM_FORMAT_VYUY:
9338                 if (INTEL_INFO(dev)->gen < 5) {
9339                         DRM_DEBUG("unsupported pixel format: %s\n",
9340                                   drm_get_format_name(mode_cmd->pixel_format));
9341                         return -EINVAL;
9342                 }
9343                 break;
9344         default:
9345                 DRM_DEBUG("unsupported pixel format: %s\n",
9346                           drm_get_format_name(mode_cmd->pixel_format));
9347                 return -EINVAL;
9348         }
9349
9350         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9351         if (mode_cmd->offsets[0] != 0)
9352                 return -EINVAL;
9353
9354         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9355         intel_fb->obj = obj;
9356
9357         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9358         if (ret) {
9359                 DRM_ERROR("framebuffer init failed %d\n", ret);
9360                 return ret;
9361         }
9362
9363         return 0;
9364 }
9365
9366 static struct drm_framebuffer *
9367 intel_user_framebuffer_create(struct drm_device *dev,
9368                               struct drm_file *filp,
9369                               struct drm_mode_fb_cmd2 *mode_cmd)
9370 {
9371         struct drm_i915_gem_object *obj;
9372
9373         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9374                                                 mode_cmd->handles[0]));
9375         if (&obj->base == NULL)
9376                 return ERR_PTR(-ENOENT);
9377
9378         return intel_framebuffer_create(dev, mode_cmd, obj);
9379 }
9380
9381 static const struct drm_mode_config_funcs intel_mode_funcs = {
9382         .fb_create = intel_user_framebuffer_create,
9383         .output_poll_changed = intel_fb_output_poll_changed,
9384 };
9385
9386 /* Set up chip specific display functions */
9387 static void intel_init_display(struct drm_device *dev)
9388 {
9389         struct drm_i915_private *dev_priv = dev->dev_private;
9390
9391         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9392                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9393         else if (IS_VALLEYVIEW(dev))
9394                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9395         else if (IS_PINEVIEW(dev))
9396                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9397         else
9398                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9399
9400         if (HAS_DDI(dev)) {
9401                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9402                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9403                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9404                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9405                 dev_priv->display.off = haswell_crtc_off;
9406                 dev_priv->display.update_plane = ironlake_update_plane;
9407         } else if (HAS_PCH_SPLIT(dev)) {
9408                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9409                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9410                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9411                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9412                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9413                 dev_priv->display.off = ironlake_crtc_off;
9414                 dev_priv->display.update_plane = ironlake_update_plane;
9415         } else if (IS_VALLEYVIEW(dev)) {
9416                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9417                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9418                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9419                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9420                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9421                 dev_priv->display.off = i9xx_crtc_off;
9422                 dev_priv->display.update_plane = i9xx_update_plane;
9423         } else {
9424                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9425                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9426                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9427                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9428                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9429                 dev_priv->display.off = i9xx_crtc_off;
9430                 dev_priv->display.update_plane = i9xx_update_plane;
9431         }
9432
9433         /* Returns the core display clock speed */
9434         if (IS_VALLEYVIEW(dev))
9435                 dev_priv->display.get_display_clock_speed =
9436                         valleyview_get_display_clock_speed;
9437         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9438                 dev_priv->display.get_display_clock_speed =
9439                         i945_get_display_clock_speed;
9440         else if (IS_I915G(dev))
9441                 dev_priv->display.get_display_clock_speed =
9442                         i915_get_display_clock_speed;
9443         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9444                 dev_priv->display.get_display_clock_speed =
9445                         i9xx_misc_get_display_clock_speed;
9446         else if (IS_I915GM(dev))
9447                 dev_priv->display.get_display_clock_speed =
9448                         i915gm_get_display_clock_speed;
9449         else if (IS_I865G(dev))
9450                 dev_priv->display.get_display_clock_speed =
9451                         i865_get_display_clock_speed;
9452         else if (IS_I85X(dev))
9453                 dev_priv->display.get_display_clock_speed =
9454                         i855_get_display_clock_speed;
9455         else /* 852, 830 */
9456                 dev_priv->display.get_display_clock_speed =
9457                         i830_get_display_clock_speed;
9458
9459         if (HAS_PCH_SPLIT(dev)) {
9460                 if (IS_GEN5(dev)) {
9461                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9462                         dev_priv->display.write_eld = ironlake_write_eld;
9463                 } else if (IS_GEN6(dev)) {
9464                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9465                         dev_priv->display.write_eld = ironlake_write_eld;
9466                 } else if (IS_IVYBRIDGE(dev)) {
9467                         /* FIXME: detect B0+ stepping and use auto training */
9468                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9469                         dev_priv->display.write_eld = ironlake_write_eld;
9470                         dev_priv->display.modeset_global_resources =
9471                                 ivb_modeset_global_resources;
9472                 } else if (IS_HASWELL(dev)) {
9473                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9474                         dev_priv->display.write_eld = haswell_write_eld;
9475                         dev_priv->display.modeset_global_resources =
9476                                 haswell_modeset_global_resources;
9477                 }
9478         } else if (IS_G4X(dev)) {
9479                 dev_priv->display.write_eld = g4x_write_eld;
9480         }
9481
9482         /* Default just returns -ENODEV to indicate unsupported */
9483         dev_priv->display.queue_flip = intel_default_queue_flip;
9484
9485         switch (INTEL_INFO(dev)->gen) {
9486         case 2:
9487                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9488                 break;
9489
9490         case 3:
9491                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9492                 break;
9493
9494         case 4:
9495         case 5:
9496                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9497                 break;
9498
9499         case 6:
9500                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9501                 break;
9502         case 7:
9503                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9504                 break;
9505         }
9506 }
9507
9508 /*
9509  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9510  * resume, or other times.  This quirk makes sure that's the case for
9511  * affected systems.
9512  */
9513 static void quirk_pipea_force(struct drm_device *dev)
9514 {
9515         struct drm_i915_private *dev_priv = dev->dev_private;
9516
9517         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9518         DRM_INFO("applying pipe a force quirk\n");
9519 }
9520
9521 /*
9522  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9523  */
9524 static void quirk_ssc_force_disable(struct drm_device *dev)
9525 {
9526         struct drm_i915_private *dev_priv = dev->dev_private;
9527         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9528         DRM_INFO("applying lvds SSC disable quirk\n");
9529 }
9530
9531 /*
9532  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9533  * brightness value
9534  */
9535 static void quirk_invert_brightness(struct drm_device *dev)
9536 {
9537         struct drm_i915_private *dev_priv = dev->dev_private;
9538         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9539         DRM_INFO("applying inverted panel brightness quirk\n");
9540 }
9541
9542 struct intel_quirk {
9543         int device;
9544         int subsystem_vendor;
9545         int subsystem_device;
9546         void (*hook)(struct drm_device *dev);
9547 };
9548
9549 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9550 struct intel_dmi_quirk {
9551         void (*hook)(struct drm_device *dev);
9552         const struct dmi_system_id (*dmi_id_list)[];
9553 };
9554
9555 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9556 {
9557         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9558         return 1;
9559 }
9560
9561 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9562         {
9563                 .dmi_id_list = &(const struct dmi_system_id[]) {
9564                         {
9565                                 .callback = intel_dmi_reverse_brightness,
9566                                 .ident = "NCR Corporation",
9567                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9568                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9569                                 },
9570                         },
9571                         { }  /* terminating entry */
9572                 },
9573                 .hook = quirk_invert_brightness,
9574         },
9575 };
9576
9577 static struct intel_quirk intel_quirks[] = {
9578         /* HP Mini needs pipe A force quirk (LP: #322104) */
9579         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9580
9581         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9582         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9583
9584         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9585         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9586
9587         /* 830/845 need to leave pipe A & dpll A up */
9588         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9589         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9590
9591         /* Lenovo U160 cannot use SSC on LVDS */
9592         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9593
9594         /* Sony Vaio Y cannot use SSC on LVDS */
9595         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9596
9597         /* Acer Aspire 5734Z must invert backlight brightness */
9598         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9599
9600         /* Acer/eMachines G725 */
9601         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9602
9603         /* Acer/eMachines e725 */
9604         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9605
9606         /* Acer/Packard Bell NCL20 */
9607         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9608
9609         /* Acer Aspire 4736Z */
9610         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9611 };
9612
9613 static void intel_init_quirks(struct drm_device *dev)
9614 {
9615         struct pci_dev *d = dev->pdev;
9616         int i;
9617
9618         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9619                 struct intel_quirk *q = &intel_quirks[i];
9620
9621                 if (d->device == q->device &&
9622                     (d->subsystem_vendor == q->subsystem_vendor ||
9623                      q->subsystem_vendor == PCI_ANY_ID) &&
9624                     (d->subsystem_device == q->subsystem_device ||
9625                      q->subsystem_device == PCI_ANY_ID))
9626                         q->hook(dev);
9627         }
9628         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9629                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9630                         intel_dmi_quirks[i].hook(dev);
9631         }
9632 }
9633
9634 /* Disable the VGA plane that we never use */
9635 static void i915_disable_vga(struct drm_device *dev)
9636 {
9637         struct drm_i915_private *dev_priv = dev->dev_private;
9638         u8 sr1;
9639         u32 vga_reg = i915_vgacntrl_reg(dev);
9640
9641         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9642         outb(SR01, VGA_SR_INDEX);
9643         sr1 = inb(VGA_SR_DATA);
9644         outb(sr1 | 1<<5, VGA_SR_DATA);
9645         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9646         udelay(300);
9647
9648         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9649         POSTING_READ(vga_reg);
9650 }
9651
9652 void intel_modeset_init_hw(struct drm_device *dev)
9653 {
9654         intel_init_power_well(dev);
9655
9656         intel_prepare_ddi(dev);
9657
9658         intel_init_clock_gating(dev);
9659
9660         mutex_lock(&dev->struct_mutex);
9661         intel_enable_gt_powersave(dev);
9662         mutex_unlock(&dev->struct_mutex);
9663 }
9664
9665 void intel_modeset_suspend_hw(struct drm_device *dev)
9666 {
9667         intel_suspend_hw(dev);
9668 }
9669
9670 void intel_modeset_init(struct drm_device *dev)
9671 {
9672         struct drm_i915_private *dev_priv = dev->dev_private;
9673         int i, j, ret;
9674
9675         drm_mode_config_init(dev);
9676
9677         dev->mode_config.min_width = 0;
9678         dev->mode_config.min_height = 0;
9679
9680         dev->mode_config.preferred_depth = 24;
9681         dev->mode_config.prefer_shadow = 1;
9682
9683         dev->mode_config.funcs = &intel_mode_funcs;
9684
9685         intel_init_quirks(dev);
9686
9687         intel_init_pm(dev);
9688
9689         if (INTEL_INFO(dev)->num_pipes == 0)
9690                 return;
9691
9692         intel_init_display(dev);
9693
9694         if (IS_GEN2(dev)) {
9695                 dev->mode_config.max_width = 2048;
9696                 dev->mode_config.max_height = 2048;
9697         } else if (IS_GEN3(dev)) {
9698                 dev->mode_config.max_width = 4096;
9699                 dev->mode_config.max_height = 4096;
9700         } else {
9701                 dev->mode_config.max_width = 8192;
9702                 dev->mode_config.max_height = 8192;
9703         }
9704         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9705
9706         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9707                       INTEL_INFO(dev)->num_pipes,
9708                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9709
9710         for_each_pipe(i) {
9711                 intel_crtc_init(dev, i);
9712                 for (j = 0; j < dev_priv->num_plane; j++) {
9713                         ret = intel_plane_init(dev, i, j);
9714                         if (ret)
9715                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9716                                               pipe_name(i), sprite_name(i, j), ret);
9717                 }
9718         }
9719
9720         intel_cpu_pll_init(dev);
9721         intel_shared_dpll_init(dev);
9722
9723         /* Just disable it once at startup */
9724         i915_disable_vga(dev);
9725         intel_setup_outputs(dev);
9726
9727         /* Just in case the BIOS is doing something questionable. */
9728         intel_disable_fbc(dev);
9729 }
9730
9731 static void
9732 intel_connector_break_all_links(struct intel_connector *connector)
9733 {
9734         connector->base.dpms = DRM_MODE_DPMS_OFF;
9735         connector->base.encoder = NULL;
9736         connector->encoder->connectors_active = false;
9737         connector->encoder->base.crtc = NULL;
9738 }
9739
9740 static void intel_enable_pipe_a(struct drm_device *dev)
9741 {
9742         struct intel_connector *connector;
9743         struct drm_connector *crt = NULL;
9744         struct intel_load_detect_pipe load_detect_temp;
9745
9746         /* We can't just switch on the pipe A, we need to set things up with a
9747          * proper mode and output configuration. As a gross hack, enable pipe A
9748          * by enabling the load detect pipe once. */
9749         list_for_each_entry(connector,
9750                             &dev->mode_config.connector_list,
9751                             base.head) {
9752                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9753                         crt = &connector->base;
9754                         break;
9755                 }
9756         }
9757
9758         if (!crt)
9759                 return;
9760
9761         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9762                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9763
9764
9765 }
9766
9767 static bool
9768 intel_check_plane_mapping(struct intel_crtc *crtc)
9769 {
9770         struct drm_device *dev = crtc->base.dev;
9771         struct drm_i915_private *dev_priv = dev->dev_private;
9772         u32 reg, val;
9773
9774         if (INTEL_INFO(dev)->num_pipes == 1)
9775                 return true;
9776
9777         reg = DSPCNTR(!crtc->plane);
9778         val = I915_READ(reg);
9779
9780         if ((val & DISPLAY_PLANE_ENABLE) &&
9781             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9782                 return false;
9783
9784         return true;
9785 }
9786
9787 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9788 {
9789         struct drm_device *dev = crtc->base.dev;
9790         struct drm_i915_private *dev_priv = dev->dev_private;
9791         u32 reg;
9792
9793         /* Clear any frame start delays used for debugging left by the BIOS */
9794         reg = PIPECONF(crtc->config.cpu_transcoder);
9795         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9796
9797         /* We need to sanitize the plane -> pipe mapping first because this will
9798          * disable the crtc (and hence change the state) if it is wrong. Note
9799          * that gen4+ has a fixed plane -> pipe mapping.  */
9800         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9801                 struct intel_connector *connector;
9802                 bool plane;
9803
9804                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9805                               crtc->base.base.id);
9806
9807                 /* Pipe has the wrong plane attached and the plane is active.
9808                  * Temporarily change the plane mapping and disable everything
9809                  * ...  */
9810                 plane = crtc->plane;
9811                 crtc->plane = !plane;
9812                 dev_priv->display.crtc_disable(&crtc->base);
9813                 crtc->plane = plane;
9814
9815                 /* ... and break all links. */
9816                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9817                                     base.head) {
9818                         if (connector->encoder->base.crtc != &crtc->base)
9819                                 continue;
9820
9821                         intel_connector_break_all_links(connector);
9822                 }
9823
9824                 WARN_ON(crtc->active);
9825                 crtc->base.enabled = false;
9826         }
9827
9828         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9829             crtc->pipe == PIPE_A && !crtc->active) {
9830                 /* BIOS forgot to enable pipe A, this mostly happens after
9831                  * resume. Force-enable the pipe to fix this, the update_dpms
9832                  * call below we restore the pipe to the right state, but leave
9833                  * the required bits on. */
9834                 intel_enable_pipe_a(dev);
9835         }
9836
9837         /* Adjust the state of the output pipe according to whether we
9838          * have active connectors/encoders. */
9839         intel_crtc_update_dpms(&crtc->base);
9840
9841         if (crtc->active != crtc->base.enabled) {
9842                 struct intel_encoder *encoder;
9843
9844                 /* This can happen either due to bugs in the get_hw_state
9845                  * functions or because the pipe is force-enabled due to the
9846                  * pipe A quirk. */
9847                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9848                               crtc->base.base.id,
9849                               crtc->base.enabled ? "enabled" : "disabled",
9850                               crtc->active ? "enabled" : "disabled");
9851
9852                 crtc->base.enabled = crtc->active;
9853
9854                 /* Because we only establish the connector -> encoder ->
9855                  * crtc links if something is active, this means the
9856                  * crtc is now deactivated. Break the links. connector
9857                  * -> encoder links are only establish when things are
9858                  *  actually up, hence no need to break them. */
9859                 WARN_ON(crtc->active);
9860
9861                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9862                         WARN_ON(encoder->connectors_active);
9863                         encoder->base.crtc = NULL;
9864                 }
9865         }
9866 }
9867
9868 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9869 {
9870         struct intel_connector *connector;
9871         struct drm_device *dev = encoder->base.dev;
9872
9873         /* We need to check both for a crtc link (meaning that the
9874          * encoder is active and trying to read from a pipe) and the
9875          * pipe itself being active. */
9876         bool has_active_crtc = encoder->base.crtc &&
9877                 to_intel_crtc(encoder->base.crtc)->active;
9878
9879         if (encoder->connectors_active && !has_active_crtc) {
9880                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9881                               encoder->base.base.id,
9882                               drm_get_encoder_name(&encoder->base));
9883
9884                 /* Connector is active, but has no active pipe. This is
9885                  * fallout from our resume register restoring. Disable
9886                  * the encoder manually again. */
9887                 if (encoder->base.crtc) {
9888                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9889                                       encoder->base.base.id,
9890                                       drm_get_encoder_name(&encoder->base));
9891                         encoder->disable(encoder);
9892                 }
9893
9894                 /* Inconsistent output/port/pipe state happens presumably due to
9895                  * a bug in one of the get_hw_state functions. Or someplace else
9896                  * in our code, like the register restore mess on resume. Clamp
9897                  * things to off as a safer default. */
9898                 list_for_each_entry(connector,
9899                                     &dev->mode_config.connector_list,
9900                                     base.head) {
9901                         if (connector->encoder != encoder)
9902                                 continue;
9903
9904                         intel_connector_break_all_links(connector);
9905                 }
9906         }
9907         /* Enabled encoders without active connectors will be fixed in
9908          * the crtc fixup. */
9909 }
9910
9911 void i915_redisable_vga(struct drm_device *dev)
9912 {
9913         struct drm_i915_private *dev_priv = dev->dev_private;
9914         u32 vga_reg = i915_vgacntrl_reg(dev);
9915
9916         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9917                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9918                 i915_disable_vga(dev);
9919         }
9920 }
9921
9922 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9923 {
9924         struct drm_i915_private *dev_priv = dev->dev_private;
9925         enum pipe pipe;
9926         struct intel_crtc *crtc;
9927         struct intel_encoder *encoder;
9928         struct intel_connector *connector;
9929         int i;
9930
9931         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9932                             base.head) {
9933                 memset(&crtc->config, 0, sizeof(crtc->config));
9934
9935                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9936                                                                  &crtc->config);
9937
9938                 crtc->base.enabled = crtc->active;
9939
9940                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9941                               crtc->base.base.id,
9942                               crtc->active ? "enabled" : "disabled");
9943         }
9944
9945         /* FIXME: Smash this into the new shared dpll infrastructure. */
9946         if (HAS_DDI(dev))
9947                 intel_ddi_setup_hw_pll_state(dev);
9948
9949         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9950                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9951
9952                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9953                 pll->active = 0;
9954                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9955                                     base.head) {
9956                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9957                                 pll->active++;
9958                 }
9959                 pll->refcount = pll->active;
9960
9961                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9962                               pll->name, pll->refcount);
9963         }
9964
9965         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9966                             base.head) {
9967                 pipe = 0;
9968
9969                 if (encoder->get_hw_state(encoder, &pipe)) {
9970                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9971                         encoder->base.crtc = &crtc->base;
9972                         if (encoder->get_config)
9973                                 encoder->get_config(encoder, &crtc->config);
9974                 } else {
9975                         encoder->base.crtc = NULL;
9976                 }
9977
9978                 encoder->connectors_active = false;
9979                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9980                               encoder->base.base.id,
9981                               drm_get_encoder_name(&encoder->base),
9982                               encoder->base.crtc ? "enabled" : "disabled",
9983                               pipe);
9984         }
9985
9986         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9987                             base.head) {
9988                 if (!crtc->active)
9989                         continue;
9990                 if (dev_priv->display.get_clock)
9991                         dev_priv->display.get_clock(crtc,
9992                                                     &crtc->config);
9993         }
9994
9995         list_for_each_entry(connector, &dev->mode_config.connector_list,
9996                             base.head) {
9997                 if (connector->get_hw_state(connector)) {
9998                         connector->base.dpms = DRM_MODE_DPMS_ON;
9999                         connector->encoder->connectors_active = true;
10000                         connector->base.encoder = &connector->encoder->base;
10001                 } else {
10002                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10003                         connector->base.encoder = NULL;
10004                 }
10005                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10006                               connector->base.base.id,
10007                               drm_get_connector_name(&connector->base),
10008                               connector->base.encoder ? "enabled" : "disabled");
10009         }
10010 }
10011
10012 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10013  * and i915 state tracking structures. */
10014 void intel_modeset_setup_hw_state(struct drm_device *dev,
10015                                   bool force_restore)
10016 {
10017         struct drm_i915_private *dev_priv = dev->dev_private;
10018         enum pipe pipe;
10019         struct drm_plane *plane;
10020         struct intel_crtc *crtc;
10021         struct intel_encoder *encoder;
10022
10023         intel_modeset_readout_hw_state(dev);
10024
10025         /*
10026          * Now that we have the config, copy it to each CRTC struct
10027          * Note that this could go away if we move to using crtc_config
10028          * checking everywhere.
10029          */
10030         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10031                             base.head) {
10032                 if (crtc->active && i915_fastboot) {
10033                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10034
10035                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10036                                       crtc->base.base.id);
10037                         drm_mode_debug_printmodeline(&crtc->base.mode);
10038                 }
10039         }
10040
10041         /* HW state is read out, now we need to sanitize this mess. */
10042         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10043                             base.head) {
10044                 intel_sanitize_encoder(encoder);
10045         }
10046
10047         for_each_pipe(pipe) {
10048                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10049                 intel_sanitize_crtc(crtc);
10050                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10051         }
10052
10053         if (force_restore) {
10054                 /*
10055                  * We need to use raw interfaces for restoring state to avoid
10056                  * checking (bogus) intermediate states.
10057                  */
10058                 for_each_pipe(pipe) {
10059                         struct drm_crtc *crtc =
10060                                 dev_priv->pipe_to_crtc_mapping[pipe];
10061
10062                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10063                                          crtc->fb);
10064                 }
10065                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10066                         intel_plane_restore(plane);
10067
10068                 i915_redisable_vga(dev);
10069         } else {
10070                 intel_modeset_update_staged_output_state(dev);
10071         }
10072
10073         intel_modeset_check_state(dev);
10074
10075         drm_mode_config_reset(dev);
10076 }
10077
10078 void intel_modeset_gem_init(struct drm_device *dev)
10079 {
10080         intel_modeset_init_hw(dev);
10081
10082         intel_setup_overlay(dev);
10083
10084         intel_modeset_setup_hw_state(dev, false);
10085 }
10086
10087 void intel_modeset_cleanup(struct drm_device *dev)
10088 {
10089         struct drm_i915_private *dev_priv = dev->dev_private;
10090         struct drm_crtc *crtc;
10091         struct intel_crtc *intel_crtc;
10092
10093         /*
10094          * Interrupts and polling as the first thing to avoid creating havoc.
10095          * Too much stuff here (turning of rps, connectors, ...) would
10096          * experience fancy races otherwise.
10097          */
10098         drm_irq_uninstall(dev);
10099         cancel_work_sync(&dev_priv->hotplug_work);
10100         /*
10101          * Due to the hpd irq storm handling the hotplug work can re-arm the
10102          * poll handlers. Hence disable polling after hpd handling is shut down.
10103          */
10104         drm_kms_helper_poll_fini(dev);
10105
10106         mutex_lock(&dev->struct_mutex);
10107
10108         intel_unregister_dsm_handler();
10109
10110         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10111                 /* Skip inactive CRTCs */
10112                 if (!crtc->fb)
10113                         continue;
10114
10115                 intel_crtc = to_intel_crtc(crtc);
10116                 intel_increase_pllclock(crtc);
10117         }
10118
10119         intel_disable_fbc(dev);
10120
10121         intel_disable_gt_powersave(dev);
10122
10123         ironlake_teardown_rc6(dev);
10124
10125         mutex_unlock(&dev->struct_mutex);
10126
10127         /* flush any delayed tasks or pending work */
10128         flush_scheduled_work();
10129
10130         /* destroy backlight, if any, before the connectors */
10131         intel_panel_destroy_backlight(dev);
10132
10133         drm_mode_config_cleanup(dev);
10134
10135         intel_cleanup_overlay(dev);
10136 }
10137
10138 /*
10139  * Return which encoder is currently attached for connector.
10140  */
10141 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10142 {
10143         return &intel_attached_encoder(connector)->base;
10144 }
10145
10146 void intel_connector_attach_encoder(struct intel_connector *connector,
10147                                     struct intel_encoder *encoder)
10148 {
10149         connector->encoder = encoder;
10150         drm_mode_connector_attach_encoder(&connector->base,
10151                                           &encoder->base);
10152 }
10153
10154 /*
10155  * set vga decode state - true == enable VGA decode
10156  */
10157 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10158 {
10159         struct drm_i915_private *dev_priv = dev->dev_private;
10160         u16 gmch_ctrl;
10161
10162         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10163         if (state)
10164                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10165         else
10166                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10167         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10168         return 0;
10169 }
10170
10171 struct intel_display_error_state {
10172
10173         u32 power_well_driver;
10174
10175         struct intel_cursor_error_state {
10176                 u32 control;
10177                 u32 position;
10178                 u32 base;
10179                 u32 size;
10180         } cursor[I915_MAX_PIPES];
10181
10182         struct intel_pipe_error_state {
10183                 enum transcoder cpu_transcoder;
10184                 u32 conf;
10185                 u32 source;
10186
10187                 u32 htotal;
10188                 u32 hblank;
10189                 u32 hsync;
10190                 u32 vtotal;
10191                 u32 vblank;
10192                 u32 vsync;
10193         } pipe[I915_MAX_PIPES];
10194
10195         struct intel_plane_error_state {
10196                 u32 control;
10197                 u32 stride;
10198                 u32 size;
10199                 u32 pos;
10200                 u32 addr;
10201                 u32 surface;
10202                 u32 tile_offset;
10203         } plane[I915_MAX_PIPES];
10204 };
10205
10206 struct intel_display_error_state *
10207 intel_display_capture_error_state(struct drm_device *dev)
10208 {
10209         drm_i915_private_t *dev_priv = dev->dev_private;
10210         struct intel_display_error_state *error;
10211         enum transcoder cpu_transcoder;
10212         int i;
10213
10214         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10215         if (error == NULL)
10216                 return NULL;
10217
10218         if (HAS_POWER_WELL(dev))
10219                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10220
10221         for_each_pipe(i) {
10222                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10223                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10224
10225                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10226                         error->cursor[i].control = I915_READ(CURCNTR(i));
10227                         error->cursor[i].position = I915_READ(CURPOS(i));
10228                         error->cursor[i].base = I915_READ(CURBASE(i));
10229                 } else {
10230                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10231                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10232                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10233                 }
10234
10235                 error->plane[i].control = I915_READ(DSPCNTR(i));
10236                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10237                 if (INTEL_INFO(dev)->gen <= 3) {
10238                         error->plane[i].size = I915_READ(DSPSIZE(i));
10239                         error->plane[i].pos = I915_READ(DSPPOS(i));
10240                 }
10241                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10242                         error->plane[i].addr = I915_READ(DSPADDR(i));
10243                 if (INTEL_INFO(dev)->gen >= 4) {
10244                         error->plane[i].surface = I915_READ(DSPSURF(i));
10245                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10246                 }
10247
10248                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10249                 error->pipe[i].source = I915_READ(PIPESRC(i));
10250                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10251                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10252                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10253                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10254                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10255                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10256         }
10257
10258         /* In the code above we read the registers without checking if the power
10259          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10260          * prevent the next I915_WRITE from detecting it and printing an error
10261          * message. */
10262         if (HAS_POWER_WELL(dev))
10263                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10264
10265         return error;
10266 }
10267
10268 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10269
10270 void
10271 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10272                                 struct drm_device *dev,
10273                                 struct intel_display_error_state *error)
10274 {
10275         int i;
10276
10277         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10278         if (HAS_POWER_WELL(dev))
10279                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10280                            error->power_well_driver);
10281         for_each_pipe(i) {
10282                 err_printf(m, "Pipe [%d]:\n", i);
10283                 err_printf(m, "  CPU transcoder: %c\n",
10284                            transcoder_name(error->pipe[i].cpu_transcoder));
10285                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10286                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10287                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10288                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10289                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10290                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10291                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10292                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10293
10294                 err_printf(m, "Plane [%d]:\n", i);
10295                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10296                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10297                 if (INTEL_INFO(dev)->gen <= 3) {
10298                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10299                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10300                 }
10301                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10302                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10303                 if (INTEL_INFO(dev)->gen >= 4) {
10304                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10305                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10306                 }
10307
10308                 err_printf(m, "Cursor [%d]:\n", i);
10309                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10310                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10311                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10312         }
10313 }