drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1099                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1100         else if (IS_845G(dev) || IS_I865G(dev))
1101                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1102         else
1103                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN((val & DISPLAY_PLANE_ENABLE),
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN((val & SP_ENABLE),
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN((val & SPRITE_ENABLE),
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN((val & DVS_ENABLE),
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807
1808         /*
1809          * There's no guarantee the pipe will really start running now. It
1810          * depends on the Gen, the output type and the relative order between
1811          * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812          * necessary.
1813          * TODO: audit the previous gens.
1814          */
1815         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816                 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873
1874 /**
1875  * intel_enable_primary_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1883                                        enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892
1893         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895         intel_crtc->primary_enabled = true;
1896
1897         reg = DSPCNTR(plane);
1898         val = I915_READ(reg);
1899         if (val & DISPLAY_PLANE_ENABLE)
1900                 return;
1901
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908  * intel_disable_primary_plane - disable the primary plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1916                                         enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922
1923         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925         intel_crtc->primary_enabled = false;
1926
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004
2005         i915_gem_object_pin_fence(obj);
2006
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049
2050 int intel_format_to_fourcc(int format)
2051 {
2052         switch (format) {
2053         case DISPPLANE_8BPP:
2054                 return DRM_FORMAT_C8;
2055         case DISPPLANE_BGRX555:
2056                 return DRM_FORMAT_XRGB1555;
2057         case DISPPLANE_BGRX565:
2058                 return DRM_FORMAT_RGB565;
2059         default:
2060         case DISPPLANE_BGRX888:
2061                 return DRM_FORMAT_XRGB8888;
2062         case DISPPLANE_RGBX888:
2063                 return DRM_FORMAT_XBGR8888;
2064         case DISPPLANE_BGRX101010:
2065                 return DRM_FORMAT_XRGB2101010;
2066         case DISPPLANE_RGBX101010:
2067                 return DRM_FORMAT_XBGR2101010;
2068         }
2069 }
2070
2071 static void intel_alloc_plane_obj(struct intel_crtc *crtc,
2072                                   struct intel_plane_config *plane_config)
2073 {
2074         struct drm_device *dev = crtc->base.dev;
2075         struct drm_i915_gem_object *obj = NULL;
2076         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077         u32 base = plane_config->base;
2078
2079         if (!plane_config->fb)
2080                 return;
2081
2082         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083                                                              plane_config->size);
2084         if (!obj)
2085                 return;
2086
2087         if (plane_config->tiled) {
2088                 obj->tiling_mode = I915_TILING_X;
2089                 obj->stride = plane_config->fb->base.pitches[0];
2090         }
2091
2092         mode_cmd.pixel_format = plane_config->fb->base.pixel_format;
2093         mode_cmd.width = plane_config->fb->base.width;
2094         mode_cmd.height = plane_config->fb->base.height;
2095         mode_cmd.pitches[0] = plane_config->fb->base.pitches[0];
2096
2097         mutex_lock(&dev->struct_mutex);
2098
2099         if (intel_framebuffer_init(dev, plane_config->fb, &mode_cmd, obj)) {
2100                 DRM_DEBUG_KMS("intel fb init failed\n");
2101                 goto out_unref_obj;
2102         }
2103
2104         mutex_unlock(&dev->struct_mutex);
2105         DRM_DEBUG_KMS("plane fb obj %p\n", plane_config->fb->obj);
2106         return;
2107
2108 out_unref_obj:
2109         drm_gem_object_unreference(&obj->base);
2110         mutex_unlock(&dev->struct_mutex);
2111
2112 }
2113
2114 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2115                              int x, int y)
2116 {
2117         struct drm_device *dev = crtc->dev;
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2120         struct intel_framebuffer *intel_fb;
2121         struct drm_i915_gem_object *obj;
2122         int plane = intel_crtc->plane;
2123         unsigned long linear_offset;
2124         u32 dspcntr;
2125         u32 reg;
2126
2127         switch (plane) {
2128         case 0:
2129         case 1:
2130                 break;
2131         default:
2132                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2133                 return -EINVAL;
2134         }
2135
2136         intel_fb = to_intel_framebuffer(fb);
2137         obj = intel_fb->obj;
2138
2139         reg = DSPCNTR(plane);
2140         dspcntr = I915_READ(reg);
2141         /* Mask out pixel format bits in case we change it */
2142         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2143         switch (fb->pixel_format) {
2144         case DRM_FORMAT_C8:
2145                 dspcntr |= DISPPLANE_8BPP;
2146                 break;
2147         case DRM_FORMAT_XRGB1555:
2148         case DRM_FORMAT_ARGB1555:
2149                 dspcntr |= DISPPLANE_BGRX555;
2150                 break;
2151         case DRM_FORMAT_RGB565:
2152                 dspcntr |= DISPPLANE_BGRX565;
2153                 break;
2154         case DRM_FORMAT_XRGB8888:
2155         case DRM_FORMAT_ARGB8888:
2156                 dspcntr |= DISPPLANE_BGRX888;
2157                 break;
2158         case DRM_FORMAT_XBGR8888:
2159         case DRM_FORMAT_ABGR8888:
2160                 dspcntr |= DISPPLANE_RGBX888;
2161                 break;
2162         case DRM_FORMAT_XRGB2101010:
2163         case DRM_FORMAT_ARGB2101010:
2164                 dspcntr |= DISPPLANE_BGRX101010;
2165                 break;
2166         case DRM_FORMAT_XBGR2101010:
2167         case DRM_FORMAT_ABGR2101010:
2168                 dspcntr |= DISPPLANE_RGBX101010;
2169                 break;
2170         default:
2171                 BUG();
2172         }
2173
2174         if (INTEL_INFO(dev)->gen >= 4) {
2175                 if (obj->tiling_mode != I915_TILING_NONE)
2176                         dspcntr |= DISPPLANE_TILED;
2177                 else
2178                         dspcntr &= ~DISPPLANE_TILED;
2179         }
2180
2181         if (IS_G4X(dev))
2182                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2183
2184         I915_WRITE(reg, dspcntr);
2185
2186         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2187
2188         if (INTEL_INFO(dev)->gen >= 4) {
2189                 intel_crtc->dspaddr_offset =
2190                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2191                                                        fb->bits_per_pixel / 8,
2192                                                        fb->pitches[0]);
2193                 linear_offset -= intel_crtc->dspaddr_offset;
2194         } else {
2195                 intel_crtc->dspaddr_offset = linear_offset;
2196         }
2197
2198         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2199                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2200                       fb->pitches[0]);
2201         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2202         if (INTEL_INFO(dev)->gen >= 4) {
2203                 I915_WRITE(DSPSURF(plane),
2204                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2205                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2206                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2207         } else
2208                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2209         POSTING_READ(reg);
2210
2211         return 0;
2212 }
2213
2214 static int ironlake_update_plane(struct drm_crtc *crtc,
2215                                  struct drm_framebuffer *fb, int x, int y)
2216 {
2217         struct drm_device *dev = crtc->dev;
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2220         struct intel_framebuffer *intel_fb;
2221         struct drm_i915_gem_object *obj;
2222         int plane = intel_crtc->plane;
2223         unsigned long linear_offset;
2224         u32 dspcntr;
2225         u32 reg;
2226
2227         switch (plane) {
2228         case 0:
2229         case 1:
2230         case 2:
2231                 break;
2232         default:
2233                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2234                 return -EINVAL;
2235         }
2236
2237         intel_fb = to_intel_framebuffer(fb);
2238         obj = intel_fb->obj;
2239
2240         reg = DSPCNTR(plane);
2241         dspcntr = I915_READ(reg);
2242         /* Mask out pixel format bits in case we change it */
2243         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2244         switch (fb->pixel_format) {
2245         case DRM_FORMAT_C8:
2246                 dspcntr |= DISPPLANE_8BPP;
2247                 break;
2248         case DRM_FORMAT_RGB565:
2249                 dspcntr |= DISPPLANE_BGRX565;
2250                 break;
2251         case DRM_FORMAT_XRGB8888:
2252         case DRM_FORMAT_ARGB8888:
2253                 dspcntr |= DISPPLANE_BGRX888;
2254                 break;
2255         case DRM_FORMAT_XBGR8888:
2256         case DRM_FORMAT_ABGR8888:
2257                 dspcntr |= DISPPLANE_RGBX888;
2258                 break;
2259         case DRM_FORMAT_XRGB2101010:
2260         case DRM_FORMAT_ARGB2101010:
2261                 dspcntr |= DISPPLANE_BGRX101010;
2262                 break;
2263         case DRM_FORMAT_XBGR2101010:
2264         case DRM_FORMAT_ABGR2101010:
2265                 dspcntr |= DISPPLANE_RGBX101010;
2266                 break;
2267         default:
2268                 BUG();
2269         }
2270
2271         if (obj->tiling_mode != I915_TILING_NONE)
2272                 dspcntr |= DISPPLANE_TILED;
2273         else
2274                 dspcntr &= ~DISPPLANE_TILED;
2275
2276         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2277                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2278         else
2279                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2280
2281         I915_WRITE(reg, dspcntr);
2282
2283         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2284         intel_crtc->dspaddr_offset =
2285                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2286                                                fb->bits_per_pixel / 8,
2287                                                fb->pitches[0]);
2288         linear_offset -= intel_crtc->dspaddr_offset;
2289
2290         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2291                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2292                       fb->pitches[0]);
2293         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2294         I915_WRITE(DSPSURF(plane),
2295                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2296         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2297                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2298         } else {
2299                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2300                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2301         }
2302         POSTING_READ(reg);
2303
2304         return 0;
2305 }
2306
2307 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2308 static int
2309 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2310                            int x, int y, enum mode_set_atomic state)
2311 {
2312         struct drm_device *dev = crtc->dev;
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314
2315         if (dev_priv->display.disable_fbc)
2316                 dev_priv->display.disable_fbc(dev);
2317         intel_increase_pllclock(crtc);
2318
2319         return dev_priv->display.update_plane(crtc, fb, x, y);
2320 }
2321
2322 void intel_display_handle_reset(struct drm_device *dev)
2323 {
2324         struct drm_i915_private *dev_priv = dev->dev_private;
2325         struct drm_crtc *crtc;
2326
2327         /*
2328          * Flips in the rings have been nuked by the reset,
2329          * so complete all pending flips so that user space
2330          * will get its events and not get stuck.
2331          *
2332          * Also update the base address of all primary
2333          * planes to the the last fb to make sure we're
2334          * showing the correct fb after a reset.
2335          *
2336          * Need to make two loops over the crtcs so that we
2337          * don't try to grab a crtc mutex before the
2338          * pending_flip_queue really got woken up.
2339          */
2340
2341         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2342                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343                 enum plane plane = intel_crtc->plane;
2344
2345                 intel_prepare_page_flip(dev, plane);
2346                 intel_finish_page_flip_plane(dev, plane);
2347         }
2348
2349         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2350                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351
2352                 mutex_lock(&crtc->mutex);
2353                 /*
2354                  * FIXME: Once we have proper support for primary planes (and
2355                  * disabling them without disabling the entire crtc) allow again
2356                  * a NULL crtc->fb.
2357                  */
2358                 if (intel_crtc->active && crtc->fb)
2359                         dev_priv->display.update_plane(crtc, crtc->fb,
2360                                                        crtc->x, crtc->y);
2361                 mutex_unlock(&crtc->mutex);
2362         }
2363 }
2364
2365 static int
2366 intel_finish_fb(struct drm_framebuffer *old_fb)
2367 {
2368         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2369         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2370         bool was_interruptible = dev_priv->mm.interruptible;
2371         int ret;
2372
2373         /* Big Hammer, we also need to ensure that any pending
2374          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2375          * current scanout is retired before unpinning the old
2376          * framebuffer.
2377          *
2378          * This should only fail upon a hung GPU, in which case we
2379          * can safely continue.
2380          */
2381         dev_priv->mm.interruptible = false;
2382         ret = i915_gem_object_finish_gpu(obj);
2383         dev_priv->mm.interruptible = was_interruptible;
2384
2385         return ret;
2386 }
2387
2388 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         unsigned long flags;
2394         bool pending;
2395
2396         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2397             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2398                 return false;
2399
2400         spin_lock_irqsave(&dev->event_lock, flags);
2401         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2402         spin_unlock_irqrestore(&dev->event_lock, flags);
2403
2404         return pending;
2405 }
2406
2407 static int
2408 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2409                     struct drm_framebuffer *fb)
2410 {
2411         struct drm_device *dev = crtc->dev;
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414         struct drm_framebuffer *old_fb;
2415         int ret;
2416
2417         if (intel_crtc_has_pending_flip(crtc)) {
2418                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2419                 return -EBUSY;
2420         }
2421
2422         /* no fb bound */
2423         if (!fb) {
2424                 DRM_ERROR("No FB bound\n");
2425                 return 0;
2426         }
2427
2428         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2429                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2430                           plane_name(intel_crtc->plane),
2431                           INTEL_INFO(dev)->num_pipes);
2432                 return -EINVAL;
2433         }
2434
2435         mutex_lock(&dev->struct_mutex);
2436         ret = intel_pin_and_fence_fb_obj(dev,
2437                                          to_intel_framebuffer(fb)->obj,
2438                                          NULL);
2439         if (ret != 0) {
2440                 mutex_unlock(&dev->struct_mutex);
2441                 DRM_ERROR("pin & fence failed\n");
2442                 return ret;
2443         }
2444
2445         /*
2446          * Update pipe size and adjust fitter if needed: the reason for this is
2447          * that in compute_mode_changes we check the native mode (not the pfit
2448          * mode) to see if we can flip rather than do a full mode set. In the
2449          * fastboot case, we'll flip, but if we don't update the pipesrc and
2450          * pfit state, we'll end up with a big fb scanned out into the wrong
2451          * sized surface.
2452          *
2453          * To fix this properly, we need to hoist the checks up into
2454          * compute_mode_changes (or above), check the actual pfit state and
2455          * whether the platform allows pfit disable with pipe active, and only
2456          * then update the pipesrc and pfit state, even on the flip path.
2457          */
2458         if (i915.fastboot) {
2459                 const struct drm_display_mode *adjusted_mode =
2460                         &intel_crtc->config.adjusted_mode;
2461
2462                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2463                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2464                            (adjusted_mode->crtc_vdisplay - 1));
2465                 if (!intel_crtc->config.pch_pfit.enabled &&
2466                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2467                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2468                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2469                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2470                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2471                 }
2472                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2473                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2474         }
2475
2476         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2477         if (ret) {
2478                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2479                 mutex_unlock(&dev->struct_mutex);
2480                 DRM_ERROR("failed to update base address\n");
2481                 return ret;
2482         }
2483
2484         old_fb = crtc->fb;
2485         crtc->fb = fb;
2486         crtc->x = x;
2487         crtc->y = y;
2488
2489         if (old_fb) {
2490                 if (intel_crtc->active && old_fb != fb)
2491                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2492                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2493         }
2494
2495         intel_update_fbc(dev);
2496         intel_edp_psr_update(dev);
2497         mutex_unlock(&dev->struct_mutex);
2498
2499         return 0;
2500 }
2501
2502 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2503 {
2504         struct drm_device *dev = crtc->dev;
2505         struct drm_i915_private *dev_priv = dev->dev_private;
2506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2507         int pipe = intel_crtc->pipe;
2508         u32 reg, temp;
2509
2510         /* enable normal train */
2511         reg = FDI_TX_CTL(pipe);
2512         temp = I915_READ(reg);
2513         if (IS_IVYBRIDGE(dev)) {
2514                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2515                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2516         } else {
2517                 temp &= ~FDI_LINK_TRAIN_NONE;
2518                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2519         }
2520         I915_WRITE(reg, temp);
2521
2522         reg = FDI_RX_CTL(pipe);
2523         temp = I915_READ(reg);
2524         if (HAS_PCH_CPT(dev)) {
2525                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2526                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2527         } else {
2528                 temp &= ~FDI_LINK_TRAIN_NONE;
2529                 temp |= FDI_LINK_TRAIN_NONE;
2530         }
2531         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2532
2533         /* wait one idle pattern time */
2534         POSTING_READ(reg);
2535         udelay(1000);
2536
2537         /* IVB wants error correction enabled */
2538         if (IS_IVYBRIDGE(dev))
2539                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2540                            FDI_FE_ERRC_ENABLE);
2541 }
2542
2543 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2544 {
2545         return crtc->base.enabled && crtc->active &&
2546                 crtc->config.has_pch_encoder;
2547 }
2548
2549 static void ivb_modeset_global_resources(struct drm_device *dev)
2550 {
2551         struct drm_i915_private *dev_priv = dev->dev_private;
2552         struct intel_crtc *pipe_B_crtc =
2553                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2554         struct intel_crtc *pipe_C_crtc =
2555                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2556         uint32_t temp;
2557
2558         /*
2559          * When everything is off disable fdi C so that we could enable fdi B
2560          * with all lanes. Note that we don't care about enabled pipes without
2561          * an enabled pch encoder.
2562          */
2563         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2564             !pipe_has_enabled_pch(pipe_C_crtc)) {
2565                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2566                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2567
2568                 temp = I915_READ(SOUTH_CHICKEN1);
2569                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2570                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2571                 I915_WRITE(SOUTH_CHICKEN1, temp);
2572         }
2573 }
2574
2575 /* The FDI link training functions for ILK/Ibexpeak. */
2576 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2577 {
2578         struct drm_device *dev = crtc->dev;
2579         struct drm_i915_private *dev_priv = dev->dev_private;
2580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581         int pipe = intel_crtc->pipe;
2582         int plane = intel_crtc->plane;
2583         u32 reg, temp, tries;
2584
2585         /* FDI needs bits from pipe & plane first */
2586         assert_pipe_enabled(dev_priv, pipe);
2587         assert_plane_enabled(dev_priv, plane);
2588
2589         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2590            for train result */
2591         reg = FDI_RX_IMR(pipe);
2592         temp = I915_READ(reg);
2593         temp &= ~FDI_RX_SYMBOL_LOCK;
2594         temp &= ~FDI_RX_BIT_LOCK;
2595         I915_WRITE(reg, temp);
2596         I915_READ(reg);
2597         udelay(150);
2598
2599         /* enable CPU FDI TX and PCH FDI RX */
2600         reg = FDI_TX_CTL(pipe);
2601         temp = I915_READ(reg);
2602         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2603         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2604         temp &= ~FDI_LINK_TRAIN_NONE;
2605         temp |= FDI_LINK_TRAIN_PATTERN_1;
2606         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2607
2608         reg = FDI_RX_CTL(pipe);
2609         temp = I915_READ(reg);
2610         temp &= ~FDI_LINK_TRAIN_NONE;
2611         temp |= FDI_LINK_TRAIN_PATTERN_1;
2612         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2613
2614         POSTING_READ(reg);
2615         udelay(150);
2616
2617         /* Ironlake workaround, enable clock pointer after FDI enable*/
2618         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2619         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2620                    FDI_RX_PHASE_SYNC_POINTER_EN);
2621
2622         reg = FDI_RX_IIR(pipe);
2623         for (tries = 0; tries < 5; tries++) {
2624                 temp = I915_READ(reg);
2625                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626
2627                 if ((temp & FDI_RX_BIT_LOCK)) {
2628                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2629                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2630                         break;
2631                 }
2632         }
2633         if (tries == 5)
2634                 DRM_ERROR("FDI train 1 fail!\n");
2635
2636         /* Train 2 */
2637         reg = FDI_TX_CTL(pipe);
2638         temp = I915_READ(reg);
2639         temp &= ~FDI_LINK_TRAIN_NONE;
2640         temp |= FDI_LINK_TRAIN_PATTERN_2;
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2;
2647         I915_WRITE(reg, temp);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         reg = FDI_RX_IIR(pipe);
2653         for (tries = 0; tries < 5; tries++) {
2654                 temp = I915_READ(reg);
2655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657                 if (temp & FDI_RX_SYMBOL_LOCK) {
2658                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2659                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2660                         break;
2661                 }
2662         }
2663         if (tries == 5)
2664                 DRM_ERROR("FDI train 2 fail!\n");
2665
2666         DRM_DEBUG_KMS("FDI train done\n");
2667
2668 }
2669
2670 static const int snb_b_fdi_train_param[] = {
2671         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2672         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2673         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2674         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2675 };
2676
2677 /* The FDI link training functions for SNB/Cougarpoint. */
2678 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683         int pipe = intel_crtc->pipe;
2684         u32 reg, temp, i, retry;
2685
2686         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2687            for train result */
2688         reg = FDI_RX_IMR(pipe);
2689         temp = I915_READ(reg);
2690         temp &= ~FDI_RX_SYMBOL_LOCK;
2691         temp &= ~FDI_RX_BIT_LOCK;
2692         I915_WRITE(reg, temp);
2693
2694         POSTING_READ(reg);
2695         udelay(150);
2696
2697         /* enable CPU FDI TX and PCH FDI RX */
2698         reg = FDI_TX_CTL(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2701         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2702         temp &= ~FDI_LINK_TRAIN_NONE;
2703         temp |= FDI_LINK_TRAIN_PATTERN_1;
2704         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2705         /* SNB-B */
2706         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2707         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2708
2709         I915_WRITE(FDI_RX_MISC(pipe),
2710                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2711
2712         reg = FDI_RX_CTL(pipe);
2713         temp = I915_READ(reg);
2714         if (HAS_PCH_CPT(dev)) {
2715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2717         } else {
2718                 temp &= ~FDI_LINK_TRAIN_NONE;
2719                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2720         }
2721         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(150);
2725
2726         for (i = 0; i < 4; i++) {
2727                 reg = FDI_TX_CTL(pipe);
2728                 temp = I915_READ(reg);
2729                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2730                 temp |= snb_b_fdi_train_param[i];
2731                 I915_WRITE(reg, temp);
2732
2733                 POSTING_READ(reg);
2734                 udelay(500);
2735
2736                 for (retry = 0; retry < 5; retry++) {
2737                         reg = FDI_RX_IIR(pipe);
2738                         temp = I915_READ(reg);
2739                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2740                         if (temp & FDI_RX_BIT_LOCK) {
2741                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2742                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2743                                 break;
2744                         }
2745                         udelay(50);
2746                 }
2747                 if (retry < 5)
2748                         break;
2749         }
2750         if (i == 4)
2751                 DRM_ERROR("FDI train 1 fail!\n");
2752
2753         /* Train 2 */
2754         reg = FDI_TX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         temp &= ~FDI_LINK_TRAIN_NONE;
2757         temp |= FDI_LINK_TRAIN_PATTERN_2;
2758         if (IS_GEN6(dev)) {
2759                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2760                 /* SNB-B */
2761                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2762         }
2763         I915_WRITE(reg, temp);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         if (HAS_PCH_CPT(dev)) {
2768                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2770         } else {
2771                 temp &= ~FDI_LINK_TRAIN_NONE;
2772                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2773         }
2774         I915_WRITE(reg, temp);
2775
2776         POSTING_READ(reg);
2777         udelay(150);
2778
2779         for (i = 0; i < 4; i++) {
2780                 reg = FDI_TX_CTL(pipe);
2781                 temp = I915_READ(reg);
2782                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783                 temp |= snb_b_fdi_train_param[i];
2784                 I915_WRITE(reg, temp);
2785
2786                 POSTING_READ(reg);
2787                 udelay(500);
2788
2789                 for (retry = 0; retry < 5; retry++) {
2790                         reg = FDI_RX_IIR(pipe);
2791                         temp = I915_READ(reg);
2792                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2793                         if (temp & FDI_RX_SYMBOL_LOCK) {
2794                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2796                                 break;
2797                         }
2798                         udelay(50);
2799                 }
2800                 if (retry < 5)
2801                         break;
2802         }
2803         if (i == 4)
2804                 DRM_ERROR("FDI train 2 fail!\n");
2805
2806         DRM_DEBUG_KMS("FDI train done.\n");
2807 }
2808
2809 /* Manual link training for Ivy Bridge A0 parts */
2810 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2811 {
2812         struct drm_device *dev = crtc->dev;
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815         int pipe = intel_crtc->pipe;
2816         u32 reg, temp, i, j;
2817
2818         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2819            for train result */
2820         reg = FDI_RX_IMR(pipe);
2821         temp = I915_READ(reg);
2822         temp &= ~FDI_RX_SYMBOL_LOCK;
2823         temp &= ~FDI_RX_BIT_LOCK;
2824         I915_WRITE(reg, temp);
2825
2826         POSTING_READ(reg);
2827         udelay(150);
2828
2829         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2830                       I915_READ(FDI_RX_IIR(pipe)));
2831
2832         /* Try each vswing and preemphasis setting twice before moving on */
2833         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2834                 /* disable first in case we need to retry */
2835                 reg = FDI_TX_CTL(pipe);
2836                 temp = I915_READ(reg);
2837                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2838                 temp &= ~FDI_TX_ENABLE;
2839                 I915_WRITE(reg, temp);
2840
2841                 reg = FDI_RX_CTL(pipe);
2842                 temp = I915_READ(reg);
2843                 temp &= ~FDI_LINK_TRAIN_AUTO;
2844                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2845                 temp &= ~FDI_RX_ENABLE;
2846                 I915_WRITE(reg, temp);
2847
2848                 /* enable CPU FDI TX and PCH FDI RX */
2849                 reg = FDI_TX_CTL(pipe);
2850                 temp = I915_READ(reg);
2851                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2852                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2853                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2854                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2855                 temp |= snb_b_fdi_train_param[j/2];
2856                 temp |= FDI_COMPOSITE_SYNC;
2857                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2858
2859                 I915_WRITE(FDI_RX_MISC(pipe),
2860                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2861
2862                 reg = FDI_RX_CTL(pipe);
2863                 temp = I915_READ(reg);
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2865                 temp |= FDI_COMPOSITE_SYNC;
2866                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2867
2868                 POSTING_READ(reg);
2869                 udelay(1); /* should be 0.5us */
2870
2871                 for (i = 0; i < 4; i++) {
2872                         reg = FDI_RX_IIR(pipe);
2873                         temp = I915_READ(reg);
2874                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2875
2876                         if (temp & FDI_RX_BIT_LOCK ||
2877                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2878                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2879                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2880                                               i);
2881                                 break;
2882                         }
2883                         udelay(1); /* should be 0.5us */
2884                 }
2885                 if (i == 4) {
2886                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2887                         continue;
2888                 }
2889
2890                 /* Train 2 */
2891                 reg = FDI_TX_CTL(pipe);
2892                 temp = I915_READ(reg);
2893                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2894                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2895                 I915_WRITE(reg, temp);
2896
2897                 reg = FDI_RX_CTL(pipe);
2898                 temp = I915_READ(reg);
2899                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2900                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2901                 I915_WRITE(reg, temp);
2902
2903                 POSTING_READ(reg);
2904                 udelay(2); /* should be 1.5us */
2905
2906                 for (i = 0; i < 4; i++) {
2907                         reg = FDI_RX_IIR(pipe);
2908                         temp = I915_READ(reg);
2909                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2910
2911                         if (temp & FDI_RX_SYMBOL_LOCK ||
2912                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2913                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2914                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2915                                               i);
2916                                 goto train_done;
2917                         }
2918                         udelay(2); /* should be 1.5us */
2919                 }
2920                 if (i == 4)
2921                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2922         }
2923
2924 train_done:
2925         DRM_DEBUG_KMS("FDI train done.\n");
2926 }
2927
2928 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2929 {
2930         struct drm_device *dev = intel_crtc->base.dev;
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         int pipe = intel_crtc->pipe;
2933         u32 reg, temp;
2934
2935
2936         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2937         reg = FDI_RX_CTL(pipe);
2938         temp = I915_READ(reg);
2939         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2940         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2941         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2942         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2943
2944         POSTING_READ(reg);
2945         udelay(200);
2946
2947         /* Switch from Rawclk to PCDclk */
2948         temp = I915_READ(reg);
2949         I915_WRITE(reg, temp | FDI_PCDCLK);
2950
2951         POSTING_READ(reg);
2952         udelay(200);
2953
2954         /* Enable CPU FDI TX PLL, always on for Ironlake */
2955         reg = FDI_TX_CTL(pipe);
2956         temp = I915_READ(reg);
2957         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2958                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2959
2960                 POSTING_READ(reg);
2961                 udelay(100);
2962         }
2963 }
2964
2965 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2966 {
2967         struct drm_device *dev = intel_crtc->base.dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int pipe = intel_crtc->pipe;
2970         u32 reg, temp;
2971
2972         /* Switch from PCDclk to Rawclk */
2973         reg = FDI_RX_CTL(pipe);
2974         temp = I915_READ(reg);
2975         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2976
2977         /* Disable CPU FDI TX PLL */
2978         reg = FDI_TX_CTL(pipe);
2979         temp = I915_READ(reg);
2980         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2981
2982         POSTING_READ(reg);
2983         udelay(100);
2984
2985         reg = FDI_RX_CTL(pipe);
2986         temp = I915_READ(reg);
2987         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2988
2989         /* Wait for the clocks to turn off. */
2990         POSTING_READ(reg);
2991         udelay(100);
2992 }
2993
2994 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2995 {
2996         struct drm_device *dev = crtc->dev;
2997         struct drm_i915_private *dev_priv = dev->dev_private;
2998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2999         int pipe = intel_crtc->pipe;
3000         u32 reg, temp;
3001
3002         /* disable CPU FDI tx and PCH FDI rx */
3003         reg = FDI_TX_CTL(pipe);
3004         temp = I915_READ(reg);
3005         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3006         POSTING_READ(reg);
3007
3008         reg = FDI_RX_CTL(pipe);
3009         temp = I915_READ(reg);
3010         temp &= ~(0x7 << 16);
3011         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3012         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3013
3014         POSTING_READ(reg);
3015         udelay(100);
3016
3017         /* Ironlake workaround, disable clock pointer after downing FDI */
3018         if (HAS_PCH_IBX(dev)) {
3019                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3020         }
3021
3022         /* still set train pattern 1 */
3023         reg = FDI_TX_CTL(pipe);
3024         temp = I915_READ(reg);
3025         temp &= ~FDI_LINK_TRAIN_NONE;
3026         temp |= FDI_LINK_TRAIN_PATTERN_1;
3027         I915_WRITE(reg, temp);
3028
3029         reg = FDI_RX_CTL(pipe);
3030         temp = I915_READ(reg);
3031         if (HAS_PCH_CPT(dev)) {
3032                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3033                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3034         } else {
3035                 temp &= ~FDI_LINK_TRAIN_NONE;
3036                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3037         }
3038         /* BPC in FDI rx is consistent with that in PIPECONF */
3039         temp &= ~(0x07 << 16);
3040         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3041         I915_WRITE(reg, temp);
3042
3043         POSTING_READ(reg);
3044         udelay(100);
3045 }
3046
3047 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3048 {
3049         struct intel_crtc *crtc;
3050
3051         /* Note that we don't need to be called with mode_config.lock here
3052          * as our list of CRTC objects is static for the lifetime of the
3053          * device and so cannot disappear as we iterate. Similarly, we can
3054          * happily treat the predicates as racy, atomic checks as userspace
3055          * cannot claim and pin a new fb without at least acquring the
3056          * struct_mutex and so serialising with us.
3057          */
3058         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3059                 if (atomic_read(&crtc->unpin_work_count) == 0)
3060                         continue;
3061
3062                 if (crtc->unpin_work)
3063                         intel_wait_for_vblank(dev, crtc->pipe);
3064
3065                 return true;
3066         }
3067
3068         return false;
3069 }
3070
3071 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075
3076         if (crtc->fb == NULL)
3077                 return;
3078
3079         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3080
3081         wait_event(dev_priv->pending_flip_queue,
3082                    !intel_crtc_has_pending_flip(crtc));
3083
3084         mutex_lock(&dev->struct_mutex);
3085         intel_finish_fb(crtc->fb);
3086         mutex_unlock(&dev->struct_mutex);
3087 }
3088
3089 /* Program iCLKIP clock to the desired frequency */
3090 static void lpt_program_iclkip(struct drm_crtc *crtc)
3091 {
3092         struct drm_device *dev = crtc->dev;
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3095         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3096         u32 temp;
3097
3098         mutex_lock(&dev_priv->dpio_lock);
3099
3100         /* It is necessary to ungate the pixclk gate prior to programming
3101          * the divisors, and gate it back when it is done.
3102          */
3103         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3104
3105         /* Disable SSCCTL */
3106         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3107                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3108                                 SBI_SSCCTL_DISABLE,
3109                         SBI_ICLK);
3110
3111         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3112         if (clock == 20000) {
3113                 auxdiv = 1;
3114                 divsel = 0x41;
3115                 phaseinc = 0x20;
3116         } else {
3117                 /* The iCLK virtual clock root frequency is in MHz,
3118                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3119                  * divisors, it is necessary to divide one by another, so we
3120                  * convert the virtual clock precision to KHz here for higher
3121                  * precision.
3122                  */
3123                 u32 iclk_virtual_root_freq = 172800 * 1000;
3124                 u32 iclk_pi_range = 64;
3125                 u32 desired_divisor, msb_divisor_value, pi_value;
3126
3127                 desired_divisor = (iclk_virtual_root_freq / clock);
3128                 msb_divisor_value = desired_divisor / iclk_pi_range;
3129                 pi_value = desired_divisor % iclk_pi_range;
3130
3131                 auxdiv = 0;
3132                 divsel = msb_divisor_value - 2;
3133                 phaseinc = pi_value;
3134         }
3135
3136         /* This should not happen with any sane values */
3137         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3138                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3139         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3140                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3141
3142         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3143                         clock,
3144                         auxdiv,
3145                         divsel,
3146                         phasedir,
3147                         phaseinc);
3148
3149         /* Program SSCDIVINTPHASE6 */
3150         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3151         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3152         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3153         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3154         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3155         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3156         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3157         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3158
3159         /* Program SSCAUXDIV */
3160         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3161         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3162         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3163         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3164
3165         /* Enable modulator and associated divider */
3166         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3167         temp &= ~SBI_SSCCTL_DISABLE;
3168         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3169
3170         /* Wait for initialization time */
3171         udelay(24);
3172
3173         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3174
3175         mutex_unlock(&dev_priv->dpio_lock);
3176 }
3177
3178 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3179                                                 enum pipe pch_transcoder)
3180 {
3181         struct drm_device *dev = crtc->base.dev;
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3184
3185         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3186                    I915_READ(HTOTAL(cpu_transcoder)));
3187         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3188                    I915_READ(HBLANK(cpu_transcoder)));
3189         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3190                    I915_READ(HSYNC(cpu_transcoder)));
3191
3192         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3193                    I915_READ(VTOTAL(cpu_transcoder)));
3194         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3195                    I915_READ(VBLANK(cpu_transcoder)));
3196         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3197                    I915_READ(VSYNC(cpu_transcoder)));
3198         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3199                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3200 }
3201
3202 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3203 {
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         uint32_t temp;
3206
3207         temp = I915_READ(SOUTH_CHICKEN1);
3208         if (temp & FDI_BC_BIFURCATION_SELECT)
3209                 return;
3210
3211         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3212         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3213
3214         temp |= FDI_BC_BIFURCATION_SELECT;
3215         DRM_DEBUG_KMS("enabling fdi C rx\n");
3216         I915_WRITE(SOUTH_CHICKEN1, temp);
3217         POSTING_READ(SOUTH_CHICKEN1);
3218 }
3219
3220 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3221 {
3222         struct drm_device *dev = intel_crtc->base.dev;
3223         struct drm_i915_private *dev_priv = dev->dev_private;
3224
3225         switch (intel_crtc->pipe) {
3226         case PIPE_A:
3227                 break;
3228         case PIPE_B:
3229                 if (intel_crtc->config.fdi_lanes > 2)
3230                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3231                 else
3232                         cpt_enable_fdi_bc_bifurcation(dev);
3233
3234                 break;
3235         case PIPE_C:
3236                 cpt_enable_fdi_bc_bifurcation(dev);
3237
3238                 break;
3239         default:
3240                 BUG();
3241         }
3242 }
3243
3244 /*
3245  * Enable PCH resources required for PCH ports:
3246  *   - PCH PLLs
3247  *   - FDI training & RX/TX
3248  *   - update transcoder timings
3249  *   - DP transcoding bits
3250  *   - transcoder
3251  */
3252 static void ironlake_pch_enable(struct drm_crtc *crtc)
3253 {
3254         struct drm_device *dev = crtc->dev;
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3257         int pipe = intel_crtc->pipe;
3258         u32 reg, temp;
3259
3260         assert_pch_transcoder_disabled(dev_priv, pipe);
3261
3262         if (IS_IVYBRIDGE(dev))
3263                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3264
3265         /* Write the TU size bits before fdi link training, so that error
3266          * detection works. */
3267         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3268                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3269
3270         /* For PCH output, training FDI link */
3271         dev_priv->display.fdi_link_train(crtc);
3272
3273         /* We need to program the right clock selection before writing the pixel
3274          * mutliplier into the DPLL. */
3275         if (HAS_PCH_CPT(dev)) {
3276                 u32 sel;
3277
3278                 temp = I915_READ(PCH_DPLL_SEL);
3279                 temp |= TRANS_DPLL_ENABLE(pipe);
3280                 sel = TRANS_DPLLB_SEL(pipe);
3281                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3282                         temp |= sel;
3283                 else
3284                         temp &= ~sel;
3285                 I915_WRITE(PCH_DPLL_SEL, temp);
3286         }
3287
3288         /* XXX: pch pll's can be enabled any time before we enable the PCH
3289          * transcoder, and we actually should do this to not upset any PCH
3290          * transcoder that already use the clock when we share it.
3291          *
3292          * Note that enable_shared_dpll tries to do the right thing, but
3293          * get_shared_dpll unconditionally resets the pll - we need that to have
3294          * the right LVDS enable sequence. */
3295         ironlake_enable_shared_dpll(intel_crtc);
3296
3297         /* set transcoder timing, panel must allow it */
3298         assert_panel_unlocked(dev_priv, pipe);
3299         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3300
3301         intel_fdi_normal_train(crtc);
3302
3303         /* For PCH DP, enable TRANS_DP_CTL */
3304         if (HAS_PCH_CPT(dev) &&
3305             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3306              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3307                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3308                 reg = TRANS_DP_CTL(pipe);
3309                 temp = I915_READ(reg);
3310                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3311                           TRANS_DP_SYNC_MASK |
3312                           TRANS_DP_BPC_MASK);
3313                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3314                          TRANS_DP_ENH_FRAMING);
3315                 temp |= bpc << 9; /* same format but at 11:9 */
3316
3317                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3318                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3319                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3320                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3321
3322                 switch (intel_trans_dp_port_sel(crtc)) {
3323                 case PCH_DP_B:
3324                         temp |= TRANS_DP_PORT_SEL_B;
3325                         break;
3326                 case PCH_DP_C:
3327                         temp |= TRANS_DP_PORT_SEL_C;
3328                         break;
3329                 case PCH_DP_D:
3330                         temp |= TRANS_DP_PORT_SEL_D;
3331                         break;
3332                 default:
3333                         BUG();
3334                 }
3335
3336                 I915_WRITE(reg, temp);
3337         }
3338
3339         ironlake_enable_pch_transcoder(dev_priv, pipe);
3340 }
3341
3342 static void lpt_pch_enable(struct drm_crtc *crtc)
3343 {
3344         struct drm_device *dev = crtc->dev;
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3348
3349         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3350
3351         lpt_program_iclkip(crtc);
3352
3353         /* Set transcoder timing. */
3354         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3355
3356         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3357 }
3358
3359 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3360 {
3361         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3362
3363         if (pll == NULL)
3364                 return;
3365
3366         if (pll->refcount == 0) {
3367                 WARN(1, "bad %s refcount\n", pll->name);
3368                 return;
3369         }
3370
3371         if (--pll->refcount == 0) {
3372                 WARN_ON(pll->on);
3373                 WARN_ON(pll->active);
3374         }
3375
3376         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3377 }
3378
3379 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3380 {
3381         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3382         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3383         enum intel_dpll_id i;
3384
3385         if (pll) {
3386                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3387                               crtc->base.base.id, pll->name);
3388                 intel_put_shared_dpll(crtc);
3389         }
3390
3391         if (HAS_PCH_IBX(dev_priv->dev)) {
3392                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3393                 i = (enum intel_dpll_id) crtc->pipe;
3394                 pll = &dev_priv->shared_dplls[i];
3395
3396                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3397                               crtc->base.base.id, pll->name);
3398
3399                 goto found;
3400         }
3401
3402         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3403                 pll = &dev_priv->shared_dplls[i];
3404
3405                 /* Only want to check enabled timings first */
3406                 if (pll->refcount == 0)
3407                         continue;
3408
3409                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3410                            sizeof(pll->hw_state)) == 0) {
3411                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3412                                       crtc->base.base.id,
3413                                       pll->name, pll->refcount, pll->active);
3414
3415                         goto found;
3416                 }
3417         }
3418
3419         /* Ok no matching timings, maybe there's a free one? */
3420         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3421                 pll = &dev_priv->shared_dplls[i];
3422                 if (pll->refcount == 0) {
3423                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3424                                       crtc->base.base.id, pll->name);
3425                         goto found;
3426                 }
3427         }
3428
3429         return NULL;
3430
3431 found:
3432         crtc->config.shared_dpll = i;
3433         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3434                          pipe_name(crtc->pipe));
3435
3436         if (pll->active == 0) {
3437                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3438                        sizeof(pll->hw_state));
3439
3440                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3441                 WARN_ON(pll->on);
3442                 assert_shared_dpll_disabled(dev_priv, pll);
3443
3444                 pll->mode_set(dev_priv, pll);
3445         }
3446         pll->refcount++;
3447
3448         return pll;
3449 }
3450
3451 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3452 {
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         int dslreg = PIPEDSL(pipe);
3455         u32 temp;
3456
3457         temp = I915_READ(dslreg);
3458         udelay(500);
3459         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3460                 if (wait_for(I915_READ(dslreg) != temp, 5))
3461                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3462         }
3463 }
3464
3465 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3466 {
3467         struct drm_device *dev = crtc->base.dev;
3468         struct drm_i915_private *dev_priv = dev->dev_private;
3469         int pipe = crtc->pipe;
3470
3471         if (crtc->config.pch_pfit.enabled) {
3472                 /* Force use of hard-coded filter coefficients
3473                  * as some pre-programmed values are broken,
3474                  * e.g. x201.
3475                  */
3476                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3477                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3478                                                  PF_PIPE_SEL_IVB(pipe));
3479                 else
3480                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3481                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3482                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3483         }
3484 }
3485
3486 static void intel_enable_planes(struct drm_crtc *crtc)
3487 {
3488         struct drm_device *dev = crtc->dev;
3489         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3490         struct intel_plane *intel_plane;
3491
3492         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3493                 if (intel_plane->pipe == pipe)
3494                         intel_plane_restore(&intel_plane->base);
3495 }
3496
3497 static void intel_disable_planes(struct drm_crtc *crtc)
3498 {
3499         struct drm_device *dev = crtc->dev;
3500         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3501         struct intel_plane *intel_plane;
3502
3503         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3504                 if (intel_plane->pipe == pipe)
3505                         intel_plane_disable(&intel_plane->base);
3506 }
3507
3508 void hsw_enable_ips(struct intel_crtc *crtc)
3509 {
3510         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3511
3512         if (!crtc->config.ips_enabled)
3513                 return;
3514
3515         /* We can only enable IPS after we enable a plane and wait for a vblank.
3516          * We guarantee that the plane is enabled by calling intel_enable_ips
3517          * only after intel_enable_plane. And intel_enable_plane already waits
3518          * for a vblank, so all we need to do here is to enable the IPS bit. */
3519         assert_plane_enabled(dev_priv, crtc->plane);
3520         if (IS_BROADWELL(crtc->base.dev)) {
3521                 mutex_lock(&dev_priv->rps.hw_lock);
3522                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3523                 mutex_unlock(&dev_priv->rps.hw_lock);
3524                 /* Quoting Art Runyan: "its not safe to expect any particular
3525                  * value in IPS_CTL bit 31 after enabling IPS through the
3526                  * mailbox." Moreover, the mailbox may return a bogus state,
3527                  * so we need to just enable it and continue on.
3528                  */
3529         } else {
3530                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3531                 /* The bit only becomes 1 in the next vblank, so this wait here
3532                  * is essentially intel_wait_for_vblank. If we don't have this
3533                  * and don't wait for vblanks until the end of crtc_enable, then
3534                  * the HW state readout code will complain that the expected
3535                  * IPS_CTL value is not the one we read. */
3536                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3537                         DRM_ERROR("Timed out waiting for IPS enable\n");
3538         }
3539 }
3540
3541 void hsw_disable_ips(struct intel_crtc *crtc)
3542 {
3543         struct drm_device *dev = crtc->base.dev;
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545
3546         if (!crtc->config.ips_enabled)
3547                 return;
3548
3549         assert_plane_enabled(dev_priv, crtc->plane);
3550         if (IS_BROADWELL(crtc->base.dev)) {
3551                 mutex_lock(&dev_priv->rps.hw_lock);
3552                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3553                 mutex_unlock(&dev_priv->rps.hw_lock);
3554         } else {
3555                 I915_WRITE(IPS_CTL, 0);
3556                 POSTING_READ(IPS_CTL);
3557         }
3558
3559         /* We need to wait for a vblank before we can disable the plane. */
3560         intel_wait_for_vblank(dev, crtc->pipe);
3561 }
3562
3563 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3564 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3565 {
3566         struct drm_device *dev = crtc->dev;
3567         struct drm_i915_private *dev_priv = dev->dev_private;
3568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569         enum pipe pipe = intel_crtc->pipe;
3570         int palreg = PALETTE(pipe);
3571         int i;
3572         bool reenable_ips = false;
3573
3574         /* The clocks have to be on to load the palette. */
3575         if (!crtc->enabled || !intel_crtc->active)
3576                 return;
3577
3578         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3579                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3580                         assert_dsi_pll_enabled(dev_priv);
3581                 else
3582                         assert_pll_enabled(dev_priv, pipe);
3583         }
3584
3585         /* use legacy palette for Ironlake */
3586         if (HAS_PCH_SPLIT(dev))
3587                 palreg = LGC_PALETTE(pipe);
3588
3589         /* Workaround : Do not read or write the pipe palette/gamma data while
3590          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3591          */
3592         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3593             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3594              GAMMA_MODE_MODE_SPLIT)) {
3595                 hsw_disable_ips(intel_crtc);
3596                 reenable_ips = true;
3597         }
3598
3599         for (i = 0; i < 256; i++) {
3600                 I915_WRITE(palreg + 4 * i,
3601                            (intel_crtc->lut_r[i] << 16) |
3602                            (intel_crtc->lut_g[i] << 8) |
3603                            intel_crtc->lut_b[i]);
3604         }
3605
3606         if (reenable_ips)
3607                 hsw_enable_ips(intel_crtc);
3608 }
3609
3610 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3611 {
3612         struct drm_device *dev = crtc->dev;
3613         struct drm_i915_private *dev_priv = dev->dev_private;
3614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615         struct intel_encoder *encoder;
3616         int pipe = intel_crtc->pipe;
3617         int plane = intel_crtc->plane;
3618
3619         WARN_ON(!crtc->enabled);
3620
3621         if (intel_crtc->active)
3622                 return;
3623
3624         intel_crtc->active = true;
3625
3626         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3627         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3628
3629         for_each_encoder_on_crtc(dev, crtc, encoder)
3630                 if (encoder->pre_enable)
3631                         encoder->pre_enable(encoder);
3632
3633         if (intel_crtc->config.has_pch_encoder) {
3634                 /* Note: FDI PLL enabling _must_ be done before we enable the
3635                  * cpu pipes, hence this is separate from all the other fdi/pch
3636                  * enabling. */
3637                 ironlake_fdi_pll_enable(intel_crtc);
3638         } else {
3639                 assert_fdi_tx_disabled(dev_priv, pipe);
3640                 assert_fdi_rx_disabled(dev_priv, pipe);
3641         }
3642
3643         ironlake_pfit_enable(intel_crtc);
3644
3645         /*
3646          * On ILK+ LUT must be loaded before the pipe is running but with
3647          * clocks enabled
3648          */
3649         intel_crtc_load_lut(crtc);
3650
3651         intel_update_watermarks(crtc);
3652         intel_enable_pipe(intel_crtc);
3653         intel_enable_primary_plane(dev_priv, plane, pipe);
3654         intel_enable_planes(crtc);
3655         intel_crtc_update_cursor(crtc, true);
3656
3657         if (intel_crtc->config.has_pch_encoder)
3658                 ironlake_pch_enable(crtc);
3659
3660         mutex_lock(&dev->struct_mutex);
3661         intel_update_fbc(dev);
3662         mutex_unlock(&dev->struct_mutex);
3663
3664         for_each_encoder_on_crtc(dev, crtc, encoder)
3665                 encoder->enable(encoder);
3666
3667         if (HAS_PCH_CPT(dev))
3668                 cpt_verify_modeset(dev, intel_crtc->pipe);
3669
3670         /*
3671          * There seems to be a race in PCH platform hw (at least on some
3672          * outputs) where an enabled pipe still completes any pageflip right
3673          * away (as if the pipe is off) instead of waiting for vblank. As soon
3674          * as the first vblank happend, everything works as expected. Hence just
3675          * wait for one vblank before returning to avoid strange things
3676          * happening.
3677          */
3678         intel_wait_for_vblank(dev, intel_crtc->pipe);
3679 }
3680
3681 /* IPS only exists on ULT machines and is tied to pipe A. */
3682 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3683 {
3684         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3685 }
3686
3687 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3688 {
3689         struct drm_device *dev = crtc->dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692         int pipe = intel_crtc->pipe;
3693         int plane = intel_crtc->plane;
3694
3695         intel_enable_primary_plane(dev_priv, plane, pipe);
3696         intel_enable_planes(crtc);
3697         intel_crtc_update_cursor(crtc, true);
3698
3699         hsw_enable_ips(intel_crtc);
3700
3701         mutex_lock(&dev->struct_mutex);
3702         intel_update_fbc(dev);
3703         mutex_unlock(&dev->struct_mutex);
3704 }
3705
3706 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3711         int pipe = intel_crtc->pipe;
3712         int plane = intel_crtc->plane;
3713
3714         intel_crtc_wait_for_pending_flips(crtc);
3715         drm_vblank_off(dev, pipe);
3716
3717         /* FBC must be disabled before disabling the plane on HSW. */
3718         if (dev_priv->fbc.plane == plane)
3719                 intel_disable_fbc(dev);
3720
3721         hsw_disable_ips(intel_crtc);
3722
3723         intel_crtc_update_cursor(crtc, false);
3724         intel_disable_planes(crtc);
3725         intel_disable_primary_plane(dev_priv, plane, pipe);
3726 }
3727
3728 /*
3729  * This implements the workaround described in the "notes" section of the mode
3730  * set sequence documentation. When going from no pipes or single pipe to
3731  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3732  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3733  */
3734 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->base.dev;
3737         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3738
3739         /* We want to get the other_active_crtc only if there's only 1 other
3740          * active crtc. */
3741         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3742                 if (!crtc_it->active || crtc_it == crtc)
3743                         continue;
3744
3745                 if (other_active_crtc)
3746                         return;
3747
3748                 other_active_crtc = crtc_it;
3749         }
3750         if (!other_active_crtc)
3751                 return;
3752
3753         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3754         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3755 }
3756
3757 static void haswell_crtc_enable(struct drm_crtc *crtc)
3758 {
3759         struct drm_device *dev = crtc->dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762         struct intel_encoder *encoder;
3763         int pipe = intel_crtc->pipe;
3764
3765         WARN_ON(!crtc->enabled);
3766
3767         if (intel_crtc->active)
3768                 return;
3769
3770         intel_crtc->active = true;
3771
3772         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3773         if (intel_crtc->config.has_pch_encoder)
3774                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3775
3776         if (intel_crtc->config.has_pch_encoder)
3777                 dev_priv->display.fdi_link_train(crtc);
3778
3779         for_each_encoder_on_crtc(dev, crtc, encoder)
3780                 if (encoder->pre_enable)
3781                         encoder->pre_enable(encoder);
3782
3783         intel_ddi_enable_pipe_clock(intel_crtc);
3784
3785         ironlake_pfit_enable(intel_crtc);
3786
3787         /*
3788          * On ILK+ LUT must be loaded before the pipe is running but with
3789          * clocks enabled
3790          */
3791         intel_crtc_load_lut(crtc);
3792
3793         intel_ddi_set_pipe_settings(crtc);
3794         intel_ddi_enable_transcoder_func(crtc);
3795
3796         intel_update_watermarks(crtc);
3797         intel_enable_pipe(intel_crtc);
3798
3799         if (intel_crtc->config.has_pch_encoder)
3800                 lpt_pch_enable(crtc);
3801
3802         for_each_encoder_on_crtc(dev, crtc, encoder) {
3803                 encoder->enable(encoder);
3804                 intel_opregion_notify_encoder(encoder, true);
3805         }
3806
3807         /* If we change the relative order between pipe/planes enabling, we need
3808          * to change the workaround. */
3809         haswell_mode_set_planes_workaround(intel_crtc);
3810         haswell_crtc_enable_planes(crtc);
3811 }
3812
3813 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->base.dev;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         int pipe = crtc->pipe;
3818
3819         /* To avoid upsetting the power well on haswell only disable the pfit if
3820          * it's in use. The hw state code will make sure we get this right. */
3821         if (crtc->config.pch_pfit.enabled) {
3822                 I915_WRITE(PF_CTL(pipe), 0);
3823                 I915_WRITE(PF_WIN_POS(pipe), 0);
3824                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3825         }
3826 }
3827
3828 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3829 {
3830         struct drm_device *dev = crtc->dev;
3831         struct drm_i915_private *dev_priv = dev->dev_private;
3832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833         struct intel_encoder *encoder;
3834         int pipe = intel_crtc->pipe;
3835         int plane = intel_crtc->plane;
3836         u32 reg, temp;
3837
3838
3839         if (!intel_crtc->active)
3840                 return;
3841
3842         for_each_encoder_on_crtc(dev, crtc, encoder)
3843                 encoder->disable(encoder);
3844
3845         intel_crtc_wait_for_pending_flips(crtc);
3846         drm_vblank_off(dev, pipe);
3847
3848         if (dev_priv->fbc.plane == plane)
3849                 intel_disable_fbc(dev);
3850
3851         intel_crtc_update_cursor(crtc, false);
3852         intel_disable_planes(crtc);
3853         intel_disable_primary_plane(dev_priv, plane, pipe);
3854
3855         if (intel_crtc->config.has_pch_encoder)
3856                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3857
3858         intel_disable_pipe(dev_priv, pipe);
3859
3860         ironlake_pfit_disable(intel_crtc);
3861
3862         for_each_encoder_on_crtc(dev, crtc, encoder)
3863                 if (encoder->post_disable)
3864                         encoder->post_disable(encoder);
3865
3866         if (intel_crtc->config.has_pch_encoder) {
3867                 ironlake_fdi_disable(crtc);
3868
3869                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3870                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3871
3872                 if (HAS_PCH_CPT(dev)) {
3873                         /* disable TRANS_DP_CTL */
3874                         reg = TRANS_DP_CTL(pipe);
3875                         temp = I915_READ(reg);
3876                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3877                                   TRANS_DP_PORT_SEL_MASK);
3878                         temp |= TRANS_DP_PORT_SEL_NONE;
3879                         I915_WRITE(reg, temp);
3880
3881                         /* disable DPLL_SEL */
3882                         temp = I915_READ(PCH_DPLL_SEL);
3883                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3884                         I915_WRITE(PCH_DPLL_SEL, temp);
3885                 }
3886
3887                 /* disable PCH DPLL */
3888                 intel_disable_shared_dpll(intel_crtc);
3889
3890                 ironlake_fdi_pll_disable(intel_crtc);
3891         }
3892
3893         intel_crtc->active = false;
3894         intel_update_watermarks(crtc);
3895
3896         mutex_lock(&dev->struct_mutex);
3897         intel_update_fbc(dev);
3898         mutex_unlock(&dev->struct_mutex);
3899 }
3900
3901 static void haswell_crtc_disable(struct drm_crtc *crtc)
3902 {
3903         struct drm_device *dev = crtc->dev;
3904         struct drm_i915_private *dev_priv = dev->dev_private;
3905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3906         struct intel_encoder *encoder;
3907         int pipe = intel_crtc->pipe;
3908         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3909
3910         if (!intel_crtc->active)
3911                 return;
3912
3913         haswell_crtc_disable_planes(crtc);
3914
3915         for_each_encoder_on_crtc(dev, crtc, encoder) {
3916                 intel_opregion_notify_encoder(encoder, false);
3917                 encoder->disable(encoder);
3918         }
3919
3920         if (intel_crtc->config.has_pch_encoder)
3921                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3922         intel_disable_pipe(dev_priv, pipe);
3923
3924         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3925
3926         ironlake_pfit_disable(intel_crtc);
3927
3928         intel_ddi_disable_pipe_clock(intel_crtc);
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->post_disable)
3932                         encoder->post_disable(encoder);
3933
3934         if (intel_crtc->config.has_pch_encoder) {
3935                 lpt_disable_pch_transcoder(dev_priv);
3936                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3937                 intel_ddi_fdi_disable(crtc);
3938         }
3939
3940         intel_crtc->active = false;
3941         intel_update_watermarks(crtc);
3942
3943         mutex_lock(&dev->struct_mutex);
3944         intel_update_fbc(dev);
3945         mutex_unlock(&dev->struct_mutex);
3946 }
3947
3948 static void ironlake_crtc_off(struct drm_crtc *crtc)
3949 {
3950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3951         intel_put_shared_dpll(intel_crtc);
3952 }
3953
3954 static void haswell_crtc_off(struct drm_crtc *crtc)
3955 {
3956         intel_ddi_put_crtc_pll(crtc);
3957 }
3958
3959 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3960 {
3961         if (!enable && intel_crtc->overlay) {
3962                 struct drm_device *dev = intel_crtc->base.dev;
3963                 struct drm_i915_private *dev_priv = dev->dev_private;
3964
3965                 mutex_lock(&dev->struct_mutex);
3966                 dev_priv->mm.interruptible = false;
3967                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3968                 dev_priv->mm.interruptible = true;
3969                 mutex_unlock(&dev->struct_mutex);
3970         }
3971
3972         /* Let userspace switch the overlay on again. In most cases userspace
3973          * has to recompute where to put it anyway.
3974          */
3975 }
3976
3977 /**
3978  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3979  * cursor plane briefly if not already running after enabling the display
3980  * plane.
3981  * This workaround avoids occasional blank screens when self refresh is
3982  * enabled.
3983  */
3984 static void
3985 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3986 {
3987         u32 cntl = I915_READ(CURCNTR(pipe));
3988
3989         if ((cntl & CURSOR_MODE) == 0) {
3990                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3991
3992                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3993                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3994                 intel_wait_for_vblank(dev_priv->dev, pipe);
3995                 I915_WRITE(CURCNTR(pipe), cntl);
3996                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3997                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3998         }
3999 }
4000
4001 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4002 {
4003         struct drm_device *dev = crtc->base.dev;
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         struct intel_crtc_config *pipe_config = &crtc->config;
4006
4007         if (!crtc->config.gmch_pfit.control)
4008                 return;
4009
4010         /*
4011          * The panel fitter should only be adjusted whilst the pipe is disabled,
4012          * according to register description and PRM.
4013          */
4014         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4015         assert_pipe_disabled(dev_priv, crtc->pipe);
4016
4017         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4018         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4019
4020         /* Border color in case we don't scale up to the full screen. Black by
4021          * default, change to something else for debugging. */
4022         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4023 }
4024
4025 #define for_each_power_domain(domain, mask)                             \
4026         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4027                 if ((1 << (domain)) & (mask))
4028
4029 enum intel_display_power_domain
4030 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4031 {
4032         struct drm_device *dev = intel_encoder->base.dev;
4033         struct intel_digital_port *intel_dig_port;
4034
4035         switch (intel_encoder->type) {
4036         case INTEL_OUTPUT_UNKNOWN:
4037                 /* Only DDI platforms should ever use this output type */
4038                 WARN_ON_ONCE(!HAS_DDI(dev));
4039         case INTEL_OUTPUT_DISPLAYPORT:
4040         case INTEL_OUTPUT_HDMI:
4041         case INTEL_OUTPUT_EDP:
4042                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4043                 switch (intel_dig_port->port) {
4044                 case PORT_A:
4045                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4046                 case PORT_B:
4047                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4048                 case PORT_C:
4049                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4050                 case PORT_D:
4051                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4052                 default:
4053                         WARN_ON_ONCE(1);
4054                         return POWER_DOMAIN_PORT_OTHER;
4055                 }
4056         case INTEL_OUTPUT_ANALOG:
4057                 return POWER_DOMAIN_PORT_CRT;
4058         case INTEL_OUTPUT_DSI:
4059                 return POWER_DOMAIN_PORT_DSI;
4060         default:
4061                 return POWER_DOMAIN_PORT_OTHER;
4062         }
4063 }
4064
4065 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4066 {
4067         struct drm_device *dev = crtc->dev;
4068         struct intel_encoder *intel_encoder;
4069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4070         enum pipe pipe = intel_crtc->pipe;
4071         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4072         unsigned long mask;
4073         enum transcoder transcoder;
4074
4075         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4076
4077         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4078         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4079         if (pfit_enabled)
4080                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4081
4082         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4083                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4084
4085         return mask;
4086 }
4087
4088 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4089                                   bool enable)
4090 {
4091         if (dev_priv->power_domains.init_power_on == enable)
4092                 return;
4093
4094         if (enable)
4095                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4096         else
4097                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4098
4099         dev_priv->power_domains.init_power_on = enable;
4100 }
4101
4102 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4103 {
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4106         struct intel_crtc *crtc;
4107
4108         /*
4109          * First get all needed power domains, then put all unneeded, to avoid
4110          * any unnecessary toggling of the power wells.
4111          */
4112         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4113                 enum intel_display_power_domain domain;
4114
4115                 if (!crtc->base.enabled)
4116                         continue;
4117
4118                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4119
4120                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4121                         intel_display_power_get(dev_priv, domain);
4122         }
4123
4124         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4125                 enum intel_display_power_domain domain;
4126
4127                 for_each_power_domain(domain, crtc->enabled_power_domains)
4128                         intel_display_power_put(dev_priv, domain);
4129
4130                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4131         }
4132
4133         intel_display_set_init_power(dev_priv, false);
4134 }
4135
4136 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4137 {
4138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4139
4140         /* Obtain SKU information */
4141         mutex_lock(&dev_priv->dpio_lock);
4142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4143                 CCK_FUSE_HPLL_FREQ_MASK;
4144         mutex_unlock(&dev_priv->dpio_lock);
4145
4146         return vco_freq[hpll_freq];
4147 }
4148
4149 /* Adjust CDclk dividers to allow high res or save power if possible */
4150 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4151 {
4152         struct drm_i915_private *dev_priv = dev->dev_private;
4153         u32 val, cmd;
4154
4155         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4156                 cmd = 2;
4157         else if (cdclk == 266)
4158                 cmd = 1;
4159         else
4160                 cmd = 0;
4161
4162         mutex_lock(&dev_priv->rps.hw_lock);
4163         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4164         val &= ~DSPFREQGUAR_MASK;
4165         val |= (cmd << DSPFREQGUAR_SHIFT);
4166         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4167         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4168                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4169                      50)) {
4170                 DRM_ERROR("timed out waiting for CDclk change\n");
4171         }
4172         mutex_unlock(&dev_priv->rps.hw_lock);
4173
4174         if (cdclk == 400) {
4175                 u32 divider, vco;
4176
4177                 vco = valleyview_get_vco(dev_priv);
4178                 divider = ((vco << 1) / cdclk) - 1;
4179
4180                 mutex_lock(&dev_priv->dpio_lock);
4181                 /* adjust cdclk divider */
4182                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4183                 val &= ~0xf;
4184                 val |= divider;
4185                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4186                 mutex_unlock(&dev_priv->dpio_lock);
4187         }
4188
4189         mutex_lock(&dev_priv->dpio_lock);
4190         /* adjust self-refresh exit latency value */
4191         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4192         val &= ~0x7f;
4193
4194         /*
4195          * For high bandwidth configs, we set a higher latency in the bunit
4196          * so that the core display fetch happens in time to avoid underruns.
4197          */
4198         if (cdclk == 400)
4199                 val |= 4500 / 250; /* 4.5 usec */
4200         else
4201                 val |= 3000 / 250; /* 3.0 usec */
4202         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4203         mutex_unlock(&dev_priv->dpio_lock);
4204
4205         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4206         intel_i2c_reset(dev);
4207 }
4208
4209 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4210 {
4211         int cur_cdclk, vco;
4212         int divider;
4213
4214         vco = valleyview_get_vco(dev_priv);
4215
4216         mutex_lock(&dev_priv->dpio_lock);
4217         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4218         mutex_unlock(&dev_priv->dpio_lock);
4219
4220         divider &= 0xf;
4221
4222         cur_cdclk = (vco << 1) / (divider + 1);
4223
4224         return cur_cdclk;
4225 }
4226
4227 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4228                                  int max_pixclk)
4229 {
4230         int cur_cdclk;
4231
4232         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4233
4234         /*
4235          * Really only a few cases to deal with, as only 4 CDclks are supported:
4236          *   200MHz
4237          *   267MHz
4238          *   320MHz
4239          *   400MHz
4240          * So we check to see whether we're above 90% of the lower bin and
4241          * adjust if needed.
4242          */
4243         if (max_pixclk > 288000) {
4244                 return 400;
4245         } else if (max_pixclk > 240000) {
4246                 return 320;
4247         } else
4248                 return 266;
4249         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4250 }
4251
4252 /* compute the max pixel clock for new configuration */
4253 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4254 {
4255         struct drm_device *dev = dev_priv->dev;
4256         struct intel_crtc *intel_crtc;
4257         int max_pixclk = 0;
4258
4259         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4260                             base.head) {
4261                 if (intel_crtc->new_enabled)
4262                         max_pixclk = max(max_pixclk,
4263                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4264         }
4265
4266         return max_pixclk;
4267 }
4268
4269 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4270                                             unsigned *prepare_pipes)
4271 {
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         struct intel_crtc *intel_crtc;
4274         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4275         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4276
4277         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4278                 return;
4279
4280         /* disable/enable all currently active pipes while we change cdclk */
4281         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4282                             base.head)
4283                 if (intel_crtc->base.enabled)
4284                         *prepare_pipes |= (1 << intel_crtc->pipe);
4285 }
4286
4287 static void valleyview_modeset_global_resources(struct drm_device *dev)
4288 {
4289         struct drm_i915_private *dev_priv = dev->dev_private;
4290         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4291         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4292         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4293
4294         if (req_cdclk != cur_cdclk)
4295                 valleyview_set_cdclk(dev, req_cdclk);
4296         modeset_update_crtc_power_domains(dev);
4297 }
4298
4299 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4300 {
4301         struct drm_device *dev = crtc->dev;
4302         struct drm_i915_private *dev_priv = dev->dev_private;
4303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304         struct intel_encoder *encoder;
4305         int pipe = intel_crtc->pipe;
4306         int plane = intel_crtc->plane;
4307         bool is_dsi;
4308
4309         WARN_ON(!crtc->enabled);
4310
4311         if (intel_crtc->active)
4312                 return;
4313
4314         intel_crtc->active = true;
4315
4316         for_each_encoder_on_crtc(dev, crtc, encoder)
4317                 if (encoder->pre_pll_enable)
4318                         encoder->pre_pll_enable(encoder);
4319
4320         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4321
4322         if (!is_dsi)
4323                 vlv_enable_pll(intel_crtc);
4324
4325         for_each_encoder_on_crtc(dev, crtc, encoder)
4326                 if (encoder->pre_enable)
4327                         encoder->pre_enable(encoder);
4328
4329         i9xx_pfit_enable(intel_crtc);
4330
4331         intel_crtc_load_lut(crtc);
4332
4333         intel_update_watermarks(crtc);
4334         intel_enable_pipe(intel_crtc);
4335         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4336         intel_enable_primary_plane(dev_priv, plane, pipe);
4337         intel_enable_planes(crtc);
4338         intel_crtc_update_cursor(crtc, true);
4339
4340         intel_update_fbc(dev);
4341
4342         for_each_encoder_on_crtc(dev, crtc, encoder)
4343                 encoder->enable(encoder);
4344 }
4345
4346 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4347 {
4348         struct drm_device *dev = crtc->dev;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351         struct intel_encoder *encoder;
4352         int pipe = intel_crtc->pipe;
4353         int plane = intel_crtc->plane;
4354
4355         WARN_ON(!crtc->enabled);
4356
4357         if (intel_crtc->active)
4358                 return;
4359
4360         intel_crtc->active = true;
4361
4362         for_each_encoder_on_crtc(dev, crtc, encoder)
4363                 if (encoder->pre_enable)
4364                         encoder->pre_enable(encoder);
4365
4366         i9xx_enable_pll(intel_crtc);
4367
4368         i9xx_pfit_enable(intel_crtc);
4369
4370         intel_crtc_load_lut(crtc);
4371
4372         intel_update_watermarks(crtc);
4373         intel_enable_pipe(intel_crtc);
4374         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4375         intel_enable_primary_plane(dev_priv, plane, pipe);
4376         intel_enable_planes(crtc);
4377         /* The fixup needs to happen before cursor is enabled */
4378         if (IS_G4X(dev))
4379                 g4x_fixup_plane(dev_priv, pipe);
4380         intel_crtc_update_cursor(crtc, true);
4381
4382         /* Give the overlay scaler a chance to enable if it's on this pipe */
4383         intel_crtc_dpms_overlay(intel_crtc, true);
4384
4385         intel_update_fbc(dev);
4386
4387         for_each_encoder_on_crtc(dev, crtc, encoder)
4388                 encoder->enable(encoder);
4389 }
4390
4391 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4392 {
4393         struct drm_device *dev = crtc->base.dev;
4394         struct drm_i915_private *dev_priv = dev->dev_private;
4395
4396         if (!crtc->config.gmch_pfit.control)
4397                 return;
4398
4399         assert_pipe_disabled(dev_priv, crtc->pipe);
4400
4401         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4402                          I915_READ(PFIT_CONTROL));
4403         I915_WRITE(PFIT_CONTROL, 0);
4404 }
4405
4406 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4407 {
4408         struct drm_device *dev = crtc->dev;
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411         struct intel_encoder *encoder;
4412         int pipe = intel_crtc->pipe;
4413         int plane = intel_crtc->plane;
4414
4415         if (!intel_crtc->active)
4416                 return;
4417
4418         for_each_encoder_on_crtc(dev, crtc, encoder)
4419                 encoder->disable(encoder);
4420
4421         /* Give the overlay scaler a chance to disable if it's on this pipe */
4422         intel_crtc_wait_for_pending_flips(crtc);
4423         drm_vblank_off(dev, pipe);
4424
4425         if (dev_priv->fbc.plane == plane)
4426                 intel_disable_fbc(dev);
4427
4428         intel_crtc_dpms_overlay(intel_crtc, false);
4429         intel_crtc_update_cursor(crtc, false);
4430         intel_disable_planes(crtc);
4431         intel_disable_primary_plane(dev_priv, plane, pipe);
4432
4433         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4434         intel_disable_pipe(dev_priv, pipe);
4435
4436         i9xx_pfit_disable(intel_crtc);
4437
4438         for_each_encoder_on_crtc(dev, crtc, encoder)
4439                 if (encoder->post_disable)
4440                         encoder->post_disable(encoder);
4441
4442         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4443                 vlv_disable_pll(dev_priv, pipe);
4444         else if (!IS_VALLEYVIEW(dev))
4445                 i9xx_disable_pll(dev_priv, pipe);
4446
4447         intel_crtc->active = false;
4448         intel_update_watermarks(crtc);
4449
4450         intel_update_fbc(dev);
4451 }
4452
4453 static void i9xx_crtc_off(struct drm_crtc *crtc)
4454 {
4455 }
4456
4457 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4458                                     bool enabled)
4459 {
4460         struct drm_device *dev = crtc->dev;
4461         struct drm_i915_master_private *master_priv;
4462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463         int pipe = intel_crtc->pipe;
4464
4465         if (!dev->primary->master)
4466                 return;
4467
4468         master_priv = dev->primary->master->driver_priv;
4469         if (!master_priv->sarea_priv)
4470                 return;
4471
4472         switch (pipe) {
4473         case 0:
4474                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4475                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4476                 break;
4477         case 1:
4478                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4479                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4480                 break;
4481         default:
4482                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4483                 break;
4484         }
4485 }
4486
4487 /**
4488  * Sets the power management mode of the pipe and plane.
4489  */
4490 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4491 {
4492         struct drm_device *dev = crtc->dev;
4493         struct drm_i915_private *dev_priv = dev->dev_private;
4494         struct intel_encoder *intel_encoder;
4495         bool enable = false;
4496
4497         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4498                 enable |= intel_encoder->connectors_active;
4499
4500         if (enable)
4501                 dev_priv->display.crtc_enable(crtc);
4502         else
4503                 dev_priv->display.crtc_disable(crtc);
4504
4505         intel_crtc_update_sarea(crtc, enable);
4506 }
4507
4508 static void intel_crtc_disable(struct drm_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->dev;
4511         struct drm_connector *connector;
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514
4515         /* crtc should still be enabled when we disable it. */
4516         WARN_ON(!crtc->enabled);
4517
4518         dev_priv->display.crtc_disable(crtc);
4519         intel_crtc->eld_vld = false;
4520         intel_crtc_update_sarea(crtc, false);
4521         dev_priv->display.off(crtc);
4522
4523         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4524         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4525         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4526
4527         if (crtc->fb) {
4528                 mutex_lock(&dev->struct_mutex);
4529                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4530                 mutex_unlock(&dev->struct_mutex);
4531                 crtc->fb = NULL;
4532         }
4533
4534         /* Update computed state. */
4535         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4536                 if (!connector->encoder || !connector->encoder->crtc)
4537                         continue;
4538
4539                 if (connector->encoder->crtc != crtc)
4540                         continue;
4541
4542                 connector->dpms = DRM_MODE_DPMS_OFF;
4543                 to_intel_encoder(connector->encoder)->connectors_active = false;
4544         }
4545 }
4546
4547 void intel_encoder_destroy(struct drm_encoder *encoder)
4548 {
4549         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4550
4551         drm_encoder_cleanup(encoder);
4552         kfree(intel_encoder);
4553 }
4554
4555 /* Simple dpms helper for encoders with just one connector, no cloning and only
4556  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4557  * state of the entire output pipe. */
4558 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4559 {
4560         if (mode == DRM_MODE_DPMS_ON) {
4561                 encoder->connectors_active = true;
4562
4563                 intel_crtc_update_dpms(encoder->base.crtc);
4564         } else {
4565                 encoder->connectors_active = false;
4566
4567                 intel_crtc_update_dpms(encoder->base.crtc);
4568         }
4569 }
4570
4571 /* Cross check the actual hw state with our own modeset state tracking (and it's
4572  * internal consistency). */
4573 static void intel_connector_check_state(struct intel_connector *connector)
4574 {
4575         if (connector->get_hw_state(connector)) {
4576                 struct intel_encoder *encoder = connector->encoder;
4577                 struct drm_crtc *crtc;
4578                 bool encoder_enabled;
4579                 enum pipe pipe;
4580
4581                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4582                               connector->base.base.id,
4583                               drm_get_connector_name(&connector->base));
4584
4585                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4586                      "wrong connector dpms state\n");
4587                 WARN(connector->base.encoder != &encoder->base,
4588                      "active connector not linked to encoder\n");
4589                 WARN(!encoder->connectors_active,
4590                      "encoder->connectors_active not set\n");
4591
4592                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4593                 WARN(!encoder_enabled, "encoder not enabled\n");
4594                 if (WARN_ON(!encoder->base.crtc))
4595                         return;
4596
4597                 crtc = encoder->base.crtc;
4598
4599                 WARN(!crtc->enabled, "crtc not enabled\n");
4600                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4601                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4602                      "encoder active on the wrong pipe\n");
4603         }
4604 }
4605
4606 /* Even simpler default implementation, if there's really no special case to
4607  * consider. */
4608 void intel_connector_dpms(struct drm_connector *connector, int mode)
4609 {
4610         /* All the simple cases only support two dpms states. */
4611         if (mode != DRM_MODE_DPMS_ON)
4612                 mode = DRM_MODE_DPMS_OFF;
4613
4614         if (mode == connector->dpms)
4615                 return;
4616
4617         connector->dpms = mode;
4618
4619         /* Only need to change hw state when actually enabled */
4620         if (connector->encoder)
4621                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4622
4623         intel_modeset_check_state(connector->dev);
4624 }
4625
4626 /* Simple connector->get_hw_state implementation for encoders that support only
4627  * one connector and no cloning and hence the encoder state determines the state
4628  * of the connector. */
4629 bool intel_connector_get_hw_state(struct intel_connector *connector)
4630 {
4631         enum pipe pipe = 0;
4632         struct intel_encoder *encoder = connector->encoder;
4633
4634         return encoder->get_hw_state(encoder, &pipe);
4635 }
4636
4637 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4638                                      struct intel_crtc_config *pipe_config)
4639 {
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         struct intel_crtc *pipe_B_crtc =
4642                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4643
4644         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4645                       pipe_name(pipe), pipe_config->fdi_lanes);
4646         if (pipe_config->fdi_lanes > 4) {
4647                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4648                               pipe_name(pipe), pipe_config->fdi_lanes);
4649                 return false;
4650         }
4651
4652         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4653                 if (pipe_config->fdi_lanes > 2) {
4654                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4655                                       pipe_config->fdi_lanes);
4656                         return false;
4657                 } else {
4658                         return true;
4659                 }
4660         }
4661
4662         if (INTEL_INFO(dev)->num_pipes == 2)
4663                 return true;
4664
4665         /* Ivybridge 3 pipe is really complicated */
4666         switch (pipe) {
4667         case PIPE_A:
4668                 return true;
4669         case PIPE_B:
4670                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4671                     pipe_config->fdi_lanes > 2) {
4672                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4673                                       pipe_name(pipe), pipe_config->fdi_lanes);
4674                         return false;
4675                 }
4676                 return true;
4677         case PIPE_C:
4678                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4679                     pipe_B_crtc->config.fdi_lanes <= 2) {
4680                         if (pipe_config->fdi_lanes > 2) {
4681                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4682                                               pipe_name(pipe), pipe_config->fdi_lanes);
4683                                 return false;
4684                         }
4685                 } else {
4686                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4687                         return false;
4688                 }
4689                 return true;
4690         default:
4691                 BUG();
4692         }
4693 }
4694
4695 #define RETRY 1
4696 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4697                                        struct intel_crtc_config *pipe_config)
4698 {
4699         struct drm_device *dev = intel_crtc->base.dev;
4700         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4701         int lane, link_bw, fdi_dotclock;
4702         bool setup_ok, needs_recompute = false;
4703
4704 retry:
4705         /* FDI is a binary signal running at ~2.7GHz, encoding
4706          * each output octet as 10 bits. The actual frequency
4707          * is stored as a divider into a 100MHz clock, and the
4708          * mode pixel clock is stored in units of 1KHz.
4709          * Hence the bw of each lane in terms of the mode signal
4710          * is:
4711          */
4712         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4713
4714         fdi_dotclock = adjusted_mode->crtc_clock;
4715
4716         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4717                                            pipe_config->pipe_bpp);
4718
4719         pipe_config->fdi_lanes = lane;
4720
4721         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4722                                link_bw, &pipe_config->fdi_m_n);
4723
4724         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4725                                             intel_crtc->pipe, pipe_config);
4726         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4727                 pipe_config->pipe_bpp -= 2*3;
4728                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4729                               pipe_config->pipe_bpp);
4730                 needs_recompute = true;
4731                 pipe_config->bw_constrained = true;
4732
4733                 goto retry;
4734         }
4735
4736         if (needs_recompute)
4737                 return RETRY;
4738
4739         return setup_ok ? 0 : -EINVAL;
4740 }
4741
4742 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4743                                    struct intel_crtc_config *pipe_config)
4744 {
4745         pipe_config->ips_enabled = i915.enable_ips &&
4746                                    hsw_crtc_supports_ips(crtc) &&
4747                                    pipe_config->pipe_bpp <= 24;
4748 }
4749
4750 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4751                                      struct intel_crtc_config *pipe_config)
4752 {
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4755
4756         /* FIXME should check pixel clock limits on all platforms */
4757         if (INTEL_INFO(dev)->gen < 4) {
4758                 struct drm_i915_private *dev_priv = dev->dev_private;
4759                 int clock_limit =
4760                         dev_priv->display.get_display_clock_speed(dev);
4761
4762                 /*
4763                  * Enable pixel doubling when the dot clock
4764                  * is > 90% of the (display) core speed.
4765                  *
4766                  * GDG double wide on either pipe,
4767                  * otherwise pipe A only.
4768                  */
4769                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4770                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4771                         clock_limit *= 2;
4772                         pipe_config->double_wide = true;
4773                 }
4774
4775                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4776                         return -EINVAL;
4777         }
4778
4779         /*
4780          * Pipe horizontal size must be even in:
4781          * - DVO ganged mode
4782          * - LVDS dual channel mode
4783          * - Double wide pipe
4784          */
4785         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4786              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4787                 pipe_config->pipe_src_w &= ~1;
4788
4789         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4790          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4791          */
4792         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4793                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4794                 return -EINVAL;
4795
4796         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4797                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4798         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4799                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4800                  * for lvds. */
4801                 pipe_config->pipe_bpp = 8*3;
4802         }
4803
4804         if (HAS_IPS(dev))
4805                 hsw_compute_ips_config(crtc, pipe_config);
4806
4807         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4808          * clock survives for now. */
4809         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4810                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4811
4812         if (pipe_config->has_pch_encoder)
4813                 return ironlake_fdi_compute_config(crtc, pipe_config);
4814
4815         return 0;
4816 }
4817
4818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4819 {
4820         return 400000; /* FIXME */
4821 }
4822
4823 static int i945_get_display_clock_speed(struct drm_device *dev)
4824 {
4825         return 400000;
4826 }
4827
4828 static int i915_get_display_clock_speed(struct drm_device *dev)
4829 {
4830         return 333000;
4831 }
4832
4833 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4834 {
4835         return 200000;
4836 }
4837
4838 static int pnv_get_display_clock_speed(struct drm_device *dev)
4839 {
4840         u16 gcfgc = 0;
4841
4842         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4843
4844         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4845         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4846                 return 267000;
4847         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4848                 return 333000;
4849         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4850                 return 444000;
4851         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4852                 return 200000;
4853         default:
4854                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4855         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4856                 return 133000;
4857         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4858                 return 167000;
4859         }
4860 }
4861
4862 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4863 {
4864         u16 gcfgc = 0;
4865
4866         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4867
4868         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4869                 return 133000;
4870         else {
4871                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4872                 case GC_DISPLAY_CLOCK_333_MHZ:
4873                         return 333000;
4874                 default:
4875                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4876                         return 190000;
4877                 }
4878         }
4879 }
4880
4881 static int i865_get_display_clock_speed(struct drm_device *dev)
4882 {
4883         return 266000;
4884 }
4885
4886 static int i855_get_display_clock_speed(struct drm_device *dev)
4887 {
4888         u16 hpllcc = 0;
4889         /* Assume that the hardware is in the high speed state.  This
4890          * should be the default.
4891          */
4892         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4893         case GC_CLOCK_133_200:
4894         case GC_CLOCK_100_200:
4895                 return 200000;
4896         case GC_CLOCK_166_250:
4897                 return 250000;
4898         case GC_CLOCK_100_133:
4899                 return 133000;
4900         }
4901
4902         /* Shouldn't happen */
4903         return 0;
4904 }
4905
4906 static int i830_get_display_clock_speed(struct drm_device *dev)
4907 {
4908         return 133000;
4909 }
4910
4911 static void
4912 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4913 {
4914         while (*num > DATA_LINK_M_N_MASK ||
4915                *den > DATA_LINK_M_N_MASK) {
4916                 *num >>= 1;
4917                 *den >>= 1;
4918         }
4919 }
4920
4921 static void compute_m_n(unsigned int m, unsigned int n,
4922                         uint32_t *ret_m, uint32_t *ret_n)
4923 {
4924         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4925         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4926         intel_reduce_m_n_ratio(ret_m, ret_n);
4927 }
4928
4929 void
4930 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4931                        int pixel_clock, int link_clock,
4932                        struct intel_link_m_n *m_n)
4933 {
4934         m_n->tu = 64;
4935
4936         compute_m_n(bits_per_pixel * pixel_clock,
4937                     link_clock * nlanes * 8,
4938                     &m_n->gmch_m, &m_n->gmch_n);
4939
4940         compute_m_n(pixel_clock, link_clock,
4941                     &m_n->link_m, &m_n->link_n);
4942 }
4943
4944 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4945 {
4946         if (i915.panel_use_ssc >= 0)
4947                 return i915.panel_use_ssc != 0;
4948         return dev_priv->vbt.lvds_use_ssc
4949                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4950 }
4951
4952 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4953 {
4954         struct drm_device *dev = crtc->dev;
4955         struct drm_i915_private *dev_priv = dev->dev_private;
4956         int refclk;
4957
4958         if (IS_VALLEYVIEW(dev)) {
4959                 refclk = 100000;
4960         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4961             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4962                 refclk = dev_priv->vbt.lvds_ssc_freq;
4963                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4964         } else if (!IS_GEN2(dev)) {
4965                 refclk = 96000;
4966         } else {
4967                 refclk = 48000;
4968         }
4969
4970         return refclk;
4971 }
4972
4973 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4974 {
4975         return (1 << dpll->n) << 16 | dpll->m2;
4976 }
4977
4978 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4979 {
4980         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4981 }
4982
4983 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4984                                      intel_clock_t *reduced_clock)
4985 {
4986         struct drm_device *dev = crtc->base.dev;
4987         struct drm_i915_private *dev_priv = dev->dev_private;
4988         int pipe = crtc->pipe;
4989         u32 fp, fp2 = 0;
4990
4991         if (IS_PINEVIEW(dev)) {
4992                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4993                 if (reduced_clock)
4994                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4995         } else {
4996                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4997                 if (reduced_clock)
4998                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4999         }
5000
5001         I915_WRITE(FP0(pipe), fp);
5002         crtc->config.dpll_hw_state.fp0 = fp;
5003
5004         crtc->lowfreq_avail = false;
5005         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5006             reduced_clock && i915.powersave) {
5007                 I915_WRITE(FP1(pipe), fp2);
5008                 crtc->config.dpll_hw_state.fp1 = fp2;
5009                 crtc->lowfreq_avail = true;
5010         } else {
5011                 I915_WRITE(FP1(pipe), fp);
5012                 crtc->config.dpll_hw_state.fp1 = fp;
5013         }
5014 }
5015
5016 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5017                 pipe)
5018 {
5019         u32 reg_val;
5020
5021         /*
5022          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5023          * and set it to a reasonable value instead.
5024          */
5025         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5026         reg_val &= 0xffffff00;
5027         reg_val |= 0x00000030;
5028         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5029
5030         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5031         reg_val &= 0x8cffffff;
5032         reg_val = 0x8c000000;
5033         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5034
5035         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5036         reg_val &= 0xffffff00;
5037         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5038
5039         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5040         reg_val &= 0x00ffffff;
5041         reg_val |= 0xb0000000;
5042         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5043 }
5044
5045 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5046                                          struct intel_link_m_n *m_n)
5047 {
5048         struct drm_device *dev = crtc->base.dev;
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050         int pipe = crtc->pipe;
5051
5052         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5053         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5054         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5055         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5056 }
5057
5058 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5059                                          struct intel_link_m_n *m_n)
5060 {
5061         struct drm_device *dev = crtc->base.dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         int pipe = crtc->pipe;
5064         enum transcoder transcoder = crtc->config.cpu_transcoder;
5065
5066         if (INTEL_INFO(dev)->gen >= 5) {
5067                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5068                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5069                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5070                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5071         } else {
5072                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5073                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5074                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5075                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5076         }
5077 }
5078
5079 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5080 {
5081         if (crtc->config.has_pch_encoder)
5082                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5083         else
5084                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5085 }
5086
5087 static void vlv_update_pll(struct intel_crtc *crtc)
5088 {
5089         struct drm_device *dev = crtc->base.dev;
5090         struct drm_i915_private *dev_priv = dev->dev_private;
5091         int pipe = crtc->pipe;
5092         u32 dpll, mdiv;
5093         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5094         u32 coreclk, reg_val, dpll_md;
5095
5096         mutex_lock(&dev_priv->dpio_lock);
5097
5098         bestn = crtc->config.dpll.n;
5099         bestm1 = crtc->config.dpll.m1;
5100         bestm2 = crtc->config.dpll.m2;
5101         bestp1 = crtc->config.dpll.p1;
5102         bestp2 = crtc->config.dpll.p2;
5103
5104         /* See eDP HDMI DPIO driver vbios notes doc */
5105
5106         /* PLL B needs special handling */
5107         if (pipe)
5108                 vlv_pllb_recal_opamp(dev_priv, pipe);
5109
5110         /* Set up Tx target for periodic Rcomp update */
5111         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5112
5113         /* Disable target IRef on PLL */
5114         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5115         reg_val &= 0x00ffffff;
5116         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5117
5118         /* Disable fast lock */
5119         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5120
5121         /* Set idtafcrecal before PLL is enabled */
5122         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5123         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5124         mdiv |= ((bestn << DPIO_N_SHIFT));
5125         mdiv |= (1 << DPIO_K_SHIFT);
5126
5127         /*
5128          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5129          * but we don't support that).
5130          * Note: don't use the DAC post divider as it seems unstable.
5131          */
5132         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5133         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5134
5135         mdiv |= DPIO_ENABLE_CALIBRATION;
5136         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5137
5138         /* Set HBR and RBR LPF coefficients */
5139         if (crtc->config.port_clock == 162000 ||
5140             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5141             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5142                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5143                                  0x009f0003);
5144         else
5145                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5146                                  0x00d0000f);
5147
5148         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5149             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5150                 /* Use SSC source */
5151                 if (!pipe)
5152                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5153                                          0x0df40000);
5154                 else
5155                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5156                                          0x0df70000);
5157         } else { /* HDMI or VGA */
5158                 /* Use bend source */
5159                 if (!pipe)
5160                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5161                                          0x0df70000);
5162                 else
5163                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5164                                          0x0df40000);
5165         }
5166
5167         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5168         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5169         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5170             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5171                 coreclk |= 0x01000000;
5172         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5173
5174         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5175
5176         /*
5177          * Enable DPIO clock input. We should never disable the reference
5178          * clock for pipe B, since VGA hotplug / manual detection depends
5179          * on it.
5180          */
5181         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5182                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5183         /* We should never disable this, set it here for state tracking */
5184         if (pipe == PIPE_B)
5185                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5186         dpll |= DPLL_VCO_ENABLE;
5187         crtc->config.dpll_hw_state.dpll = dpll;
5188
5189         dpll_md = (crtc->config.pixel_multiplier - 1)
5190                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5191         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5192
5193         if (crtc->config.has_dp_encoder)
5194                 intel_dp_set_m_n(crtc);
5195
5196         mutex_unlock(&dev_priv->dpio_lock);
5197 }
5198
5199 static void i9xx_update_pll(struct intel_crtc *crtc,
5200                             intel_clock_t *reduced_clock,
5201                             int num_connectors)
5202 {
5203         struct drm_device *dev = crtc->base.dev;
5204         struct drm_i915_private *dev_priv = dev->dev_private;
5205         u32 dpll;
5206         bool is_sdvo;
5207         struct dpll *clock = &crtc->config.dpll;
5208
5209         i9xx_update_pll_dividers(crtc, reduced_clock);
5210
5211         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5212                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5213
5214         dpll = DPLL_VGA_MODE_DIS;
5215
5216         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5217                 dpll |= DPLLB_MODE_LVDS;
5218         else
5219                 dpll |= DPLLB_MODE_DAC_SERIAL;
5220
5221         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5222                 dpll |= (crtc->config.pixel_multiplier - 1)
5223                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5224         }
5225
5226         if (is_sdvo)
5227                 dpll |= DPLL_SDVO_HIGH_SPEED;
5228
5229         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5230                 dpll |= DPLL_SDVO_HIGH_SPEED;
5231
5232         /* compute bitmask from p1 value */
5233         if (IS_PINEVIEW(dev))
5234                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5235         else {
5236                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5237                 if (IS_G4X(dev) && reduced_clock)
5238                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5239         }
5240         switch (clock->p2) {
5241         case 5:
5242                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5243                 break;
5244         case 7:
5245                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5246                 break;
5247         case 10:
5248                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5249                 break;
5250         case 14:
5251                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5252                 break;
5253         }
5254         if (INTEL_INFO(dev)->gen >= 4)
5255                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5256
5257         if (crtc->config.sdvo_tv_clock)
5258                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5259         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5260                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5261                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5262         else
5263                 dpll |= PLL_REF_INPUT_DREFCLK;
5264
5265         dpll |= DPLL_VCO_ENABLE;
5266         crtc->config.dpll_hw_state.dpll = dpll;
5267
5268         if (INTEL_INFO(dev)->gen >= 4) {
5269                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5270                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5271                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5272         }
5273
5274         if (crtc->config.has_dp_encoder)
5275                 intel_dp_set_m_n(crtc);
5276 }
5277
5278 static void i8xx_update_pll(struct intel_crtc *crtc,
5279                             intel_clock_t *reduced_clock,
5280                             int num_connectors)
5281 {
5282         struct drm_device *dev = crtc->base.dev;
5283         struct drm_i915_private *dev_priv = dev->dev_private;
5284         u32 dpll;
5285         struct dpll *clock = &crtc->config.dpll;
5286
5287         i9xx_update_pll_dividers(crtc, reduced_clock);
5288
5289         dpll = DPLL_VGA_MODE_DIS;
5290
5291         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5292                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5293         } else {
5294                 if (clock->p1 == 2)
5295                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5296                 else
5297                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5298                 if (clock->p2 == 4)
5299                         dpll |= PLL_P2_DIVIDE_BY_4;
5300         }
5301
5302         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5303                 dpll |= DPLL_DVO_2X_MODE;
5304
5305         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5306                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5307                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5308         else
5309                 dpll |= PLL_REF_INPUT_DREFCLK;
5310
5311         dpll |= DPLL_VCO_ENABLE;
5312         crtc->config.dpll_hw_state.dpll = dpll;
5313 }
5314
5315 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5316 {
5317         struct drm_device *dev = intel_crtc->base.dev;
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319         enum pipe pipe = intel_crtc->pipe;
5320         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5321         struct drm_display_mode *adjusted_mode =
5322                 &intel_crtc->config.adjusted_mode;
5323         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5324
5325         /* We need to be careful not to changed the adjusted mode, for otherwise
5326          * the hw state checker will get angry at the mismatch. */
5327         crtc_vtotal = adjusted_mode->crtc_vtotal;
5328         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5329
5330         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5331                 /* the chip adds 2 halflines automatically */
5332                 crtc_vtotal -= 1;
5333                 crtc_vblank_end -= 1;
5334                 vsyncshift = adjusted_mode->crtc_hsync_start
5335                              - adjusted_mode->crtc_htotal / 2;
5336         } else {
5337                 vsyncshift = 0;
5338         }
5339
5340         if (INTEL_INFO(dev)->gen > 3)
5341                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5342
5343         I915_WRITE(HTOTAL(cpu_transcoder),
5344                    (adjusted_mode->crtc_hdisplay - 1) |
5345                    ((adjusted_mode->crtc_htotal - 1) << 16));
5346         I915_WRITE(HBLANK(cpu_transcoder),
5347                    (adjusted_mode->crtc_hblank_start - 1) |
5348                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5349         I915_WRITE(HSYNC(cpu_transcoder),
5350                    (adjusted_mode->crtc_hsync_start - 1) |
5351                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5352
5353         I915_WRITE(VTOTAL(cpu_transcoder),
5354                    (adjusted_mode->crtc_vdisplay - 1) |
5355                    ((crtc_vtotal - 1) << 16));
5356         I915_WRITE(VBLANK(cpu_transcoder),
5357                    (adjusted_mode->crtc_vblank_start - 1) |
5358                    ((crtc_vblank_end - 1) << 16));
5359         I915_WRITE(VSYNC(cpu_transcoder),
5360                    (adjusted_mode->crtc_vsync_start - 1) |
5361                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5362
5363         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5364          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5365          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5366          * bits. */
5367         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5368             (pipe == PIPE_B || pipe == PIPE_C))
5369                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5370
5371         /* pipesrc controls the size that is scaled from, which should
5372          * always be the user's requested size.
5373          */
5374         I915_WRITE(PIPESRC(pipe),
5375                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5376                    (intel_crtc->config.pipe_src_h - 1));
5377 }
5378
5379 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5380                                    struct intel_crtc_config *pipe_config)
5381 {
5382         struct drm_device *dev = crtc->base.dev;
5383         struct drm_i915_private *dev_priv = dev->dev_private;
5384         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5385         uint32_t tmp;
5386
5387         tmp = I915_READ(HTOTAL(cpu_transcoder));
5388         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5389         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5390         tmp = I915_READ(HBLANK(cpu_transcoder));
5391         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5392         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5393         tmp = I915_READ(HSYNC(cpu_transcoder));
5394         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5395         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5396
5397         tmp = I915_READ(VTOTAL(cpu_transcoder));
5398         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5399         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5400         tmp = I915_READ(VBLANK(cpu_transcoder));
5401         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5402         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5403         tmp = I915_READ(VSYNC(cpu_transcoder));
5404         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5405         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5406
5407         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5408                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5409                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5410                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5411         }
5412
5413         tmp = I915_READ(PIPESRC(crtc->pipe));
5414         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5415         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5416
5417         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5418         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5419 }
5420
5421 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5422                                  struct intel_crtc_config *pipe_config)
5423 {
5424         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5425         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5426         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5427         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5428
5429         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5430         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5431         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5432         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5433
5434         mode->flags = pipe_config->adjusted_mode.flags;
5435
5436         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5437         mode->flags |= pipe_config->adjusted_mode.flags;
5438 }
5439
5440 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5441 {
5442         struct drm_device *dev = intel_crtc->base.dev;
5443         struct drm_i915_private *dev_priv = dev->dev_private;
5444         uint32_t pipeconf;
5445
5446         pipeconf = 0;
5447
5448         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5449             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5450                 pipeconf |= PIPECONF_ENABLE;
5451
5452         if (intel_crtc->config.double_wide)
5453                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5454
5455         /* only g4x and later have fancy bpc/dither controls */
5456         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5457                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5458                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5459                         pipeconf |= PIPECONF_DITHER_EN |
5460                                     PIPECONF_DITHER_TYPE_SP;
5461
5462                 switch (intel_crtc->config.pipe_bpp) {
5463                 case 18:
5464                         pipeconf |= PIPECONF_6BPC;
5465                         break;
5466                 case 24:
5467                         pipeconf |= PIPECONF_8BPC;
5468                         break;
5469                 case 30:
5470                         pipeconf |= PIPECONF_10BPC;
5471                         break;
5472                 default:
5473                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5474                         BUG();
5475                 }
5476         }
5477
5478         if (HAS_PIPE_CXSR(dev)) {
5479                 if (intel_crtc->lowfreq_avail) {
5480                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5481                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5482                 } else {
5483                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5484                 }
5485         }
5486
5487         if (!IS_GEN2(dev) &&
5488             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5489                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5490         else
5491                 pipeconf |= PIPECONF_PROGRESSIVE;
5492
5493         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5494                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5495
5496         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5497         POSTING_READ(PIPECONF(intel_crtc->pipe));
5498 }
5499
5500 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5501                               int x, int y,
5502                               struct drm_framebuffer *fb)
5503 {
5504         struct drm_device *dev = crtc->dev;
5505         struct drm_i915_private *dev_priv = dev->dev_private;
5506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507         int pipe = intel_crtc->pipe;
5508         int plane = intel_crtc->plane;
5509         int refclk, num_connectors = 0;
5510         intel_clock_t clock, reduced_clock;
5511         u32 dspcntr;
5512         bool ok, has_reduced_clock = false;
5513         bool is_lvds = false, is_dsi = false;
5514         struct intel_encoder *encoder;
5515         const intel_limit_t *limit;
5516         int ret;
5517
5518         for_each_encoder_on_crtc(dev, crtc, encoder) {
5519                 switch (encoder->type) {
5520                 case INTEL_OUTPUT_LVDS:
5521                         is_lvds = true;
5522                         break;
5523                 case INTEL_OUTPUT_DSI:
5524                         is_dsi = true;
5525                         break;
5526                 }
5527
5528                 num_connectors++;
5529         }
5530
5531         if (is_dsi)
5532                 goto skip_dpll;
5533
5534         if (!intel_crtc->config.clock_set) {
5535                 refclk = i9xx_get_refclk(crtc, num_connectors);
5536
5537                 /*
5538                  * Returns a set of divisors for the desired target clock with
5539                  * the given refclk, or FALSE.  The returned values represent
5540                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5541                  * 2) / p1 / p2.
5542                  */
5543                 limit = intel_limit(crtc, refclk);
5544                 ok = dev_priv->display.find_dpll(limit, crtc,
5545                                                  intel_crtc->config.port_clock,
5546                                                  refclk, NULL, &clock);
5547                 if (!ok) {
5548                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5549                         return -EINVAL;
5550                 }
5551
5552                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5553                         /*
5554                          * Ensure we match the reduced clock's P to the target
5555                          * clock.  If the clocks don't match, we can't switch
5556                          * the display clock by using the FP0/FP1. In such case
5557                          * we will disable the LVDS downclock feature.
5558                          */
5559                         has_reduced_clock =
5560                                 dev_priv->display.find_dpll(limit, crtc,
5561                                                             dev_priv->lvds_downclock,
5562                                                             refclk, &clock,
5563                                                             &reduced_clock);
5564                 }
5565                 /* Compat-code for transition, will disappear. */
5566                 intel_crtc->config.dpll.n = clock.n;
5567                 intel_crtc->config.dpll.m1 = clock.m1;
5568                 intel_crtc->config.dpll.m2 = clock.m2;
5569                 intel_crtc->config.dpll.p1 = clock.p1;
5570                 intel_crtc->config.dpll.p2 = clock.p2;
5571         }
5572
5573         if (IS_GEN2(dev)) {
5574                 i8xx_update_pll(intel_crtc,
5575                                 has_reduced_clock ? &reduced_clock : NULL,
5576                                 num_connectors);
5577         } else if (IS_VALLEYVIEW(dev)) {
5578                 vlv_update_pll(intel_crtc);
5579         } else {
5580                 i9xx_update_pll(intel_crtc,
5581                                 has_reduced_clock ? &reduced_clock : NULL,
5582                                 num_connectors);
5583         }
5584
5585 skip_dpll:
5586         /* Set up the display plane register */
5587         dspcntr = DISPPLANE_GAMMA_ENABLE;
5588
5589         if (!IS_VALLEYVIEW(dev)) {
5590                 if (pipe == 0)
5591                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5592                 else
5593                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5594         }
5595
5596         intel_set_pipe_timings(intel_crtc);
5597
5598         /* pipesrc and dspsize control the size that is scaled from,
5599          * which should always be the user's requested size.
5600          */
5601         I915_WRITE(DSPSIZE(plane),
5602                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5603                    (intel_crtc->config.pipe_src_w - 1));
5604         I915_WRITE(DSPPOS(plane), 0);
5605
5606         i9xx_set_pipeconf(intel_crtc);
5607
5608         I915_WRITE(DSPCNTR(plane), dspcntr);
5609         POSTING_READ(DSPCNTR(plane));
5610
5611         ret = intel_pipe_set_base(crtc, x, y, fb);
5612
5613         return ret;
5614 }
5615
5616 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5617                                  struct intel_crtc_config *pipe_config)
5618 {
5619         struct drm_device *dev = crtc->base.dev;
5620         struct drm_i915_private *dev_priv = dev->dev_private;
5621         uint32_t tmp;
5622
5623         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5624                 return;
5625
5626         tmp = I915_READ(PFIT_CONTROL);
5627         if (!(tmp & PFIT_ENABLE))
5628                 return;
5629
5630         /* Check whether the pfit is attached to our pipe. */
5631         if (INTEL_INFO(dev)->gen < 4) {
5632                 if (crtc->pipe != PIPE_B)
5633                         return;
5634         } else {
5635                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5636                         return;
5637         }
5638
5639         pipe_config->gmch_pfit.control = tmp;
5640         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5641         if (INTEL_INFO(dev)->gen < 5)
5642                 pipe_config->gmch_pfit.lvds_border_bits =
5643                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5644 }
5645
5646 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5647                                struct intel_crtc_config *pipe_config)
5648 {
5649         struct drm_device *dev = crtc->base.dev;
5650         struct drm_i915_private *dev_priv = dev->dev_private;
5651         int pipe = pipe_config->cpu_transcoder;
5652         intel_clock_t clock;
5653         u32 mdiv;
5654         int refclk = 100000;
5655
5656         mutex_lock(&dev_priv->dpio_lock);
5657         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5658         mutex_unlock(&dev_priv->dpio_lock);
5659
5660         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5661         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5662         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5663         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5664         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5665
5666         vlv_clock(refclk, &clock);
5667
5668         /* clock.dot is the fast clock */
5669         pipe_config->port_clock = clock.dot / 5;
5670 }
5671
5672 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5673                                   struct intel_plane_config *plane_config)
5674 {
5675         struct drm_device *dev = crtc->base.dev;
5676         struct drm_i915_private *dev_priv = dev->dev_private;
5677         u32 val, base, offset;
5678         int pipe = crtc->pipe, plane = crtc->plane;
5679         int fourcc, pixel_format;
5680         int aligned_height;
5681
5682         plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL);
5683         if (!plane_config->fb) {
5684                 DRM_DEBUG_KMS("failed to alloc fb\n");
5685                 return;
5686         }
5687
5688         val = I915_READ(DSPCNTR(plane));
5689
5690         if (INTEL_INFO(dev)->gen >= 4)
5691                 if (val & DISPPLANE_TILED)
5692                         plane_config->tiled = true;
5693
5694         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5695         fourcc = intel_format_to_fourcc(pixel_format);
5696         plane_config->fb->base.pixel_format = fourcc;
5697         plane_config->fb->base.bits_per_pixel =
5698                 drm_format_plane_cpp(fourcc, 0) * 8;
5699
5700         if (INTEL_INFO(dev)->gen >= 4) {
5701                 if (plane_config->tiled)
5702                         offset = I915_READ(DSPTILEOFF(plane));
5703                 else
5704                         offset = I915_READ(DSPLINOFF(plane));
5705                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5706         } else {
5707                 base = I915_READ(DSPADDR(plane));
5708         }
5709         plane_config->base = base;
5710
5711         val = I915_READ(PIPESRC(pipe));
5712         plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1;
5713         plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1;
5714
5715         val = I915_READ(DSPSTRIDE(pipe));
5716         plane_config->fb->base.pitches[0] = val & 0xffffff80;
5717
5718         aligned_height = intel_align_height(dev, plane_config->fb->base.height,
5719                                             plane_config->tiled);
5720
5721         plane_config->size = ALIGN(plane_config->fb->base.pitches[0] *
5722                                    aligned_height, PAGE_SIZE);
5723
5724         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5725                       pipe, plane, plane_config->fb->base.width,
5726                       plane_config->fb->base.height,
5727                       plane_config->fb->base.bits_per_pixel, base,
5728                       plane_config->fb->base.pitches[0],
5729                       plane_config->size);
5730
5731 }
5732
5733 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5734                                  struct intel_crtc_config *pipe_config)
5735 {
5736         struct drm_device *dev = crtc->base.dev;
5737         struct drm_i915_private *dev_priv = dev->dev_private;
5738         uint32_t tmp;
5739
5740         if (!intel_display_power_enabled(dev_priv,
5741                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5742                 return false;
5743
5744         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5745         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5746
5747         tmp = I915_READ(PIPECONF(crtc->pipe));
5748         if (!(tmp & PIPECONF_ENABLE))
5749                 return false;
5750
5751         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5752                 switch (tmp & PIPECONF_BPC_MASK) {
5753                 case PIPECONF_6BPC:
5754                         pipe_config->pipe_bpp = 18;
5755                         break;
5756                 case PIPECONF_8BPC:
5757                         pipe_config->pipe_bpp = 24;
5758                         break;
5759                 case PIPECONF_10BPC:
5760                         pipe_config->pipe_bpp = 30;
5761                         break;
5762                 default:
5763                         break;
5764                 }
5765         }
5766
5767         if (INTEL_INFO(dev)->gen < 4)
5768                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5769
5770         intel_get_pipe_timings(crtc, pipe_config);
5771
5772         i9xx_get_pfit_config(crtc, pipe_config);
5773
5774         if (INTEL_INFO(dev)->gen >= 4) {
5775                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5776                 pipe_config->pixel_multiplier =
5777                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5778                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5779                 pipe_config->dpll_hw_state.dpll_md = tmp;
5780         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5781                 tmp = I915_READ(DPLL(crtc->pipe));
5782                 pipe_config->pixel_multiplier =
5783                         ((tmp & SDVO_MULTIPLIER_MASK)
5784                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5785         } else {
5786                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5787                  * port and will be fixed up in the encoder->get_config
5788                  * function. */
5789                 pipe_config->pixel_multiplier = 1;
5790         }
5791         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5792         if (!IS_VALLEYVIEW(dev)) {
5793                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5794                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5795         } else {
5796                 /* Mask out read-only status bits. */
5797                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5798                                                      DPLL_PORTC_READY_MASK |
5799                                                      DPLL_PORTB_READY_MASK);
5800         }
5801
5802         if (IS_VALLEYVIEW(dev))
5803                 vlv_crtc_clock_get(crtc, pipe_config);
5804         else
5805                 i9xx_crtc_clock_get(crtc, pipe_config);
5806
5807         return true;
5808 }
5809
5810 static void ironlake_init_pch_refclk(struct drm_device *dev)
5811 {
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         struct drm_mode_config *mode_config = &dev->mode_config;
5814         struct intel_encoder *encoder;
5815         u32 val, final;
5816         bool has_lvds = false;
5817         bool has_cpu_edp = false;
5818         bool has_panel = false;
5819         bool has_ck505 = false;
5820         bool can_ssc = false;
5821
5822         /* We need to take the global config into account */
5823         list_for_each_entry(encoder, &mode_config->encoder_list,
5824                             base.head) {
5825                 switch (encoder->type) {
5826                 case INTEL_OUTPUT_LVDS:
5827                         has_panel = true;
5828                         has_lvds = true;
5829                         break;
5830                 case INTEL_OUTPUT_EDP:
5831                         has_panel = true;
5832                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5833                                 has_cpu_edp = true;
5834                         break;
5835                 }
5836         }
5837
5838         if (HAS_PCH_IBX(dev)) {
5839                 has_ck505 = dev_priv->vbt.display_clock_mode;
5840                 can_ssc = has_ck505;
5841         } else {
5842                 has_ck505 = false;
5843                 can_ssc = true;
5844         }
5845
5846         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5847                       has_panel, has_lvds, has_ck505);
5848
5849         /* Ironlake: try to setup display ref clock before DPLL
5850          * enabling. This is only under driver's control after
5851          * PCH B stepping, previous chipset stepping should be
5852          * ignoring this setting.
5853          */
5854         val = I915_READ(PCH_DREF_CONTROL);
5855
5856         /* As we must carefully and slowly disable/enable each source in turn,
5857          * compute the final state we want first and check if we need to
5858          * make any changes at all.
5859          */
5860         final = val;
5861         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5862         if (has_ck505)
5863                 final |= DREF_NONSPREAD_CK505_ENABLE;
5864         else
5865                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5866
5867         final &= ~DREF_SSC_SOURCE_MASK;
5868         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5869         final &= ~DREF_SSC1_ENABLE;
5870
5871         if (has_panel) {
5872                 final |= DREF_SSC_SOURCE_ENABLE;
5873
5874                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5875                         final |= DREF_SSC1_ENABLE;
5876
5877                 if (has_cpu_edp) {
5878                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5879                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5880                         else
5881                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5882                 } else
5883                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5884         } else {
5885                 final |= DREF_SSC_SOURCE_DISABLE;
5886                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5887         }
5888
5889         if (final == val)
5890                 return;
5891
5892         /* Always enable nonspread source */
5893         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5894
5895         if (has_ck505)
5896                 val |= DREF_NONSPREAD_CK505_ENABLE;
5897         else
5898                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5899
5900         if (has_panel) {
5901                 val &= ~DREF_SSC_SOURCE_MASK;
5902                 val |= DREF_SSC_SOURCE_ENABLE;
5903
5904                 /* SSC must be turned on before enabling the CPU output  */
5905                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5906                         DRM_DEBUG_KMS("Using SSC on panel\n");
5907                         val |= DREF_SSC1_ENABLE;
5908                 } else
5909                         val &= ~DREF_SSC1_ENABLE;
5910
5911                 /* Get SSC going before enabling the outputs */
5912                 I915_WRITE(PCH_DREF_CONTROL, val);
5913                 POSTING_READ(PCH_DREF_CONTROL);
5914                 udelay(200);
5915
5916                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5917
5918                 /* Enable CPU source on CPU attached eDP */
5919                 if (has_cpu_edp) {
5920                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5921                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5922                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5923                         }
5924                         else
5925                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5926                 } else
5927                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5928
5929                 I915_WRITE(PCH_DREF_CONTROL, val);
5930                 POSTING_READ(PCH_DREF_CONTROL);
5931                 udelay(200);
5932         } else {
5933                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5934
5935                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5936
5937                 /* Turn off CPU output */
5938                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5939
5940                 I915_WRITE(PCH_DREF_CONTROL, val);
5941                 POSTING_READ(PCH_DREF_CONTROL);
5942                 udelay(200);
5943
5944                 /* Turn off the SSC source */
5945                 val &= ~DREF_SSC_SOURCE_MASK;
5946                 val |= DREF_SSC_SOURCE_DISABLE;
5947
5948                 /* Turn off SSC1 */
5949                 val &= ~DREF_SSC1_ENABLE;
5950
5951                 I915_WRITE(PCH_DREF_CONTROL, val);
5952                 POSTING_READ(PCH_DREF_CONTROL);
5953                 udelay(200);
5954         }
5955
5956         BUG_ON(val != final);
5957 }
5958
5959 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5960 {
5961         uint32_t tmp;
5962
5963         tmp = I915_READ(SOUTH_CHICKEN2);
5964         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5965         I915_WRITE(SOUTH_CHICKEN2, tmp);
5966
5967         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5968                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5969                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5970
5971         tmp = I915_READ(SOUTH_CHICKEN2);
5972         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5973         I915_WRITE(SOUTH_CHICKEN2, tmp);
5974
5975         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5976                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5977                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5978 }
5979
5980 /* WaMPhyProgramming:hsw */
5981 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5982 {
5983         uint32_t tmp;
5984
5985         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5986         tmp &= ~(0xFF << 24);
5987         tmp |= (0x12 << 24);
5988         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5989
5990         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5991         tmp |= (1 << 11);
5992         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5993
5994         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5995         tmp |= (1 << 11);
5996         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5997
5998         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5999         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6000         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6001
6002         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6003         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6004         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6005
6006         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6007         tmp &= ~(7 << 13);
6008         tmp |= (5 << 13);
6009         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6010
6011         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6012         tmp &= ~(7 << 13);
6013         tmp |= (5 << 13);
6014         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6015
6016         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6017         tmp &= ~0xFF;
6018         tmp |= 0x1C;
6019         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6020
6021         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6022         tmp &= ~0xFF;
6023         tmp |= 0x1C;
6024         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6025
6026         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6027         tmp &= ~(0xFF << 16);
6028         tmp |= (0x1C << 16);
6029         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6030
6031         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6032         tmp &= ~(0xFF << 16);
6033         tmp |= (0x1C << 16);
6034         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6035
6036         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6037         tmp |= (1 << 27);
6038         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6039
6040         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6041         tmp |= (1 << 27);
6042         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6043
6044         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6045         tmp &= ~(0xF << 28);
6046         tmp |= (4 << 28);
6047         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6048
6049         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6050         tmp &= ~(0xF << 28);
6051         tmp |= (4 << 28);
6052         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6053 }
6054
6055 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6056  * Programming" based on the parameters passed:
6057  * - Sequence to enable CLKOUT_DP
6058  * - Sequence to enable CLKOUT_DP without spread
6059  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6060  */
6061 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6062                                  bool with_fdi)
6063 {
6064         struct drm_i915_private *dev_priv = dev->dev_private;
6065         uint32_t reg, tmp;
6066
6067         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6068                 with_spread = true;
6069         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6070                  with_fdi, "LP PCH doesn't have FDI\n"))
6071                 with_fdi = false;
6072
6073         mutex_lock(&dev_priv->dpio_lock);
6074
6075         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6076         tmp &= ~SBI_SSCCTL_DISABLE;
6077         tmp |= SBI_SSCCTL_PATHALT;
6078         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6079
6080         udelay(24);
6081
6082         if (with_spread) {
6083                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6084                 tmp &= ~SBI_SSCCTL_PATHALT;
6085                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6086
6087                 if (with_fdi) {
6088                         lpt_reset_fdi_mphy(dev_priv);
6089                         lpt_program_fdi_mphy(dev_priv);
6090                 }
6091         }
6092
6093         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6094                SBI_GEN0 : SBI_DBUFF0;
6095         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6096         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6097         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6098
6099         mutex_unlock(&dev_priv->dpio_lock);
6100 }
6101
6102 /* Sequence to disable CLKOUT_DP */
6103 static void lpt_disable_clkout_dp(struct drm_device *dev)
6104 {
6105         struct drm_i915_private *dev_priv = dev->dev_private;
6106         uint32_t reg, tmp;
6107
6108         mutex_lock(&dev_priv->dpio_lock);
6109
6110         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6111                SBI_GEN0 : SBI_DBUFF0;
6112         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6113         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6114         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6115
6116         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6117         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6118                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6119                         tmp |= SBI_SSCCTL_PATHALT;
6120                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6121                         udelay(32);
6122                 }
6123                 tmp |= SBI_SSCCTL_DISABLE;
6124                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6125         }
6126
6127         mutex_unlock(&dev_priv->dpio_lock);
6128 }
6129
6130 static void lpt_init_pch_refclk(struct drm_device *dev)
6131 {
6132         struct drm_mode_config *mode_config = &dev->mode_config;
6133         struct intel_encoder *encoder;
6134         bool has_vga = false;
6135
6136         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6137                 switch (encoder->type) {
6138                 case INTEL_OUTPUT_ANALOG:
6139                         has_vga = true;
6140                         break;
6141                 }
6142         }
6143
6144         if (has_vga)
6145                 lpt_enable_clkout_dp(dev, true, true);
6146         else
6147                 lpt_disable_clkout_dp(dev);
6148 }
6149
6150 /*
6151  * Initialize reference clocks when the driver loads
6152  */
6153 void intel_init_pch_refclk(struct drm_device *dev)
6154 {
6155         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6156                 ironlake_init_pch_refclk(dev);
6157         else if (HAS_PCH_LPT(dev))
6158                 lpt_init_pch_refclk(dev);
6159 }
6160
6161 static int ironlake_get_refclk(struct drm_crtc *crtc)
6162 {
6163         struct drm_device *dev = crtc->dev;
6164         struct drm_i915_private *dev_priv = dev->dev_private;
6165         struct intel_encoder *encoder;
6166         int num_connectors = 0;
6167         bool is_lvds = false;
6168
6169         for_each_encoder_on_crtc(dev, crtc, encoder) {
6170                 switch (encoder->type) {
6171                 case INTEL_OUTPUT_LVDS:
6172                         is_lvds = true;
6173                         break;
6174                 }
6175                 num_connectors++;
6176         }
6177
6178         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6179                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6180                               dev_priv->vbt.lvds_ssc_freq);
6181                 return dev_priv->vbt.lvds_ssc_freq;
6182         }
6183
6184         return 120000;
6185 }
6186
6187 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6188 {
6189         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191         int pipe = intel_crtc->pipe;
6192         uint32_t val;
6193
6194         val = 0;
6195
6196         switch (intel_crtc->config.pipe_bpp) {
6197         case 18:
6198                 val |= PIPECONF_6BPC;
6199                 break;
6200         case 24:
6201                 val |= PIPECONF_8BPC;
6202                 break;
6203         case 30:
6204                 val |= PIPECONF_10BPC;
6205                 break;
6206         case 36:
6207                 val |= PIPECONF_12BPC;
6208                 break;
6209         default:
6210                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6211                 BUG();
6212         }
6213
6214         if (intel_crtc->config.dither)
6215                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6216
6217         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6218                 val |= PIPECONF_INTERLACED_ILK;
6219         else
6220                 val |= PIPECONF_PROGRESSIVE;
6221
6222         if (intel_crtc->config.limited_color_range)
6223                 val |= PIPECONF_COLOR_RANGE_SELECT;
6224
6225         I915_WRITE(PIPECONF(pipe), val);
6226         POSTING_READ(PIPECONF(pipe));
6227 }
6228
6229 /*
6230  * Set up the pipe CSC unit.
6231  *
6232  * Currently only full range RGB to limited range RGB conversion
6233  * is supported, but eventually this should handle various
6234  * RGB<->YCbCr scenarios as well.
6235  */
6236 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6237 {
6238         struct drm_device *dev = crtc->dev;
6239         struct drm_i915_private *dev_priv = dev->dev_private;
6240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6241         int pipe = intel_crtc->pipe;
6242         uint16_t coeff = 0x7800; /* 1.0 */
6243
6244         /*
6245          * TODO: Check what kind of values actually come out of the pipe
6246          * with these coeff/postoff values and adjust to get the best
6247          * accuracy. Perhaps we even need to take the bpc value into
6248          * consideration.
6249          */
6250
6251         if (intel_crtc->config.limited_color_range)
6252                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6253
6254         /*
6255          * GY/GU and RY/RU should be the other way around according
6256          * to BSpec, but reality doesn't agree. Just set them up in
6257          * a way that results in the correct picture.
6258          */
6259         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6260         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6261
6262         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6263         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6264
6265         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6266         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6267
6268         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6269         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6270         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6271
6272         if (INTEL_INFO(dev)->gen > 6) {
6273                 uint16_t postoff = 0;
6274
6275                 if (intel_crtc->config.limited_color_range)
6276                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6277
6278                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6279                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6280                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6281
6282                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6283         } else {
6284                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6285
6286                 if (intel_crtc->config.limited_color_range)
6287                         mode |= CSC_BLACK_SCREEN_OFFSET;
6288
6289                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6290         }
6291 }
6292
6293 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6294 {
6295         struct drm_device *dev = crtc->dev;
6296         struct drm_i915_private *dev_priv = dev->dev_private;
6297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298         enum pipe pipe = intel_crtc->pipe;
6299         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6300         uint32_t val;
6301
6302         val = 0;
6303
6304         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6305                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6306
6307         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6308                 val |= PIPECONF_INTERLACED_ILK;
6309         else
6310                 val |= PIPECONF_PROGRESSIVE;
6311
6312         I915_WRITE(PIPECONF(cpu_transcoder), val);
6313         POSTING_READ(PIPECONF(cpu_transcoder));
6314
6315         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6316         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6317
6318         if (IS_BROADWELL(dev)) {
6319                 val = 0;
6320
6321                 switch (intel_crtc->config.pipe_bpp) {
6322                 case 18:
6323                         val |= PIPEMISC_DITHER_6_BPC;
6324                         break;
6325                 case 24:
6326                         val |= PIPEMISC_DITHER_8_BPC;
6327                         break;
6328                 case 30:
6329                         val |= PIPEMISC_DITHER_10_BPC;
6330                         break;
6331                 case 36:
6332                         val |= PIPEMISC_DITHER_12_BPC;
6333                         break;
6334                 default:
6335                         /* Case prevented by pipe_config_set_bpp. */
6336                         BUG();
6337                 }
6338
6339                 if (intel_crtc->config.dither)
6340                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6341
6342                 I915_WRITE(PIPEMISC(pipe), val);
6343         }
6344 }
6345
6346 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6347                                     intel_clock_t *clock,
6348                                     bool *has_reduced_clock,
6349                                     intel_clock_t *reduced_clock)
6350 {
6351         struct drm_device *dev = crtc->dev;
6352         struct drm_i915_private *dev_priv = dev->dev_private;
6353         struct intel_encoder *intel_encoder;
6354         int refclk;
6355         const intel_limit_t *limit;
6356         bool ret, is_lvds = false;
6357
6358         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6359                 switch (intel_encoder->type) {
6360                 case INTEL_OUTPUT_LVDS:
6361                         is_lvds = true;
6362                         break;
6363                 }
6364         }
6365
6366         refclk = ironlake_get_refclk(crtc);
6367
6368         /*
6369          * Returns a set of divisors for the desired target clock with the given
6370          * refclk, or FALSE.  The returned values represent the clock equation:
6371          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6372          */
6373         limit = intel_limit(crtc, refclk);
6374         ret = dev_priv->display.find_dpll(limit, crtc,
6375                                           to_intel_crtc(crtc)->config.port_clock,
6376                                           refclk, NULL, clock);
6377         if (!ret)
6378                 return false;
6379
6380         if (is_lvds && dev_priv->lvds_downclock_avail) {
6381                 /*
6382                  * Ensure we match the reduced clock's P to the target clock.
6383                  * If the clocks don't match, we can't switch the display clock
6384                  * by using the FP0/FP1. In such case we will disable the LVDS
6385                  * downclock feature.
6386                 */
6387                 *has_reduced_clock =
6388                         dev_priv->display.find_dpll(limit, crtc,
6389                                                     dev_priv->lvds_downclock,
6390                                                     refclk, clock,
6391                                                     reduced_clock);
6392         }
6393
6394         return true;
6395 }
6396
6397 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6398 {
6399         /*
6400          * Account for spread spectrum to avoid
6401          * oversubscribing the link. Max center spread
6402          * is 2.5%; use 5% for safety's sake.
6403          */
6404         u32 bps = target_clock * bpp * 21 / 20;
6405         return DIV_ROUND_UP(bps, link_bw * 8);
6406 }
6407
6408 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6409 {
6410         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6411 }
6412
6413 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6414                                       u32 *fp,
6415                                       intel_clock_t *reduced_clock, u32 *fp2)
6416 {
6417         struct drm_crtc *crtc = &intel_crtc->base;
6418         struct drm_device *dev = crtc->dev;
6419         struct drm_i915_private *dev_priv = dev->dev_private;
6420         struct intel_encoder *intel_encoder;
6421         uint32_t dpll;
6422         int factor, num_connectors = 0;
6423         bool is_lvds = false, is_sdvo = false;
6424
6425         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6426                 switch (intel_encoder->type) {
6427                 case INTEL_OUTPUT_LVDS:
6428                         is_lvds = true;
6429                         break;
6430                 case INTEL_OUTPUT_SDVO:
6431                 case INTEL_OUTPUT_HDMI:
6432                         is_sdvo = true;
6433                         break;
6434                 }
6435
6436                 num_connectors++;
6437         }
6438
6439         /* Enable autotuning of the PLL clock (if permissible) */
6440         factor = 21;
6441         if (is_lvds) {
6442                 if ((intel_panel_use_ssc(dev_priv) &&
6443                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6444                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6445                         factor = 25;
6446         } else if (intel_crtc->config.sdvo_tv_clock)
6447                 factor = 20;
6448
6449         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6450                 *fp |= FP_CB_TUNE;
6451
6452         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6453                 *fp2 |= FP_CB_TUNE;
6454
6455         dpll = 0;
6456
6457         if (is_lvds)
6458                 dpll |= DPLLB_MODE_LVDS;
6459         else
6460                 dpll |= DPLLB_MODE_DAC_SERIAL;
6461
6462         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6463                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6464
6465         if (is_sdvo)
6466                 dpll |= DPLL_SDVO_HIGH_SPEED;
6467         if (intel_crtc->config.has_dp_encoder)
6468                 dpll |= DPLL_SDVO_HIGH_SPEED;
6469
6470         /* compute bitmask from p1 value */
6471         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6472         /* also FPA1 */
6473         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6474
6475         switch (intel_crtc->config.dpll.p2) {
6476         case 5:
6477                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6478                 break;
6479         case 7:
6480                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6481                 break;
6482         case 10:
6483                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6484                 break;
6485         case 14:
6486                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6487                 break;
6488         }
6489
6490         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6491                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6492         else
6493                 dpll |= PLL_REF_INPUT_DREFCLK;
6494
6495         return dpll | DPLL_VCO_ENABLE;
6496 }
6497
6498 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6499                                   int x, int y,
6500                                   struct drm_framebuffer *fb)
6501 {
6502         struct drm_device *dev = crtc->dev;
6503         struct drm_i915_private *dev_priv = dev->dev_private;
6504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6505         int pipe = intel_crtc->pipe;
6506         int plane = intel_crtc->plane;
6507         int num_connectors = 0;
6508         intel_clock_t clock, reduced_clock;
6509         u32 dpll = 0, fp = 0, fp2 = 0;
6510         bool ok, has_reduced_clock = false;
6511         bool is_lvds = false;
6512         struct intel_encoder *encoder;
6513         struct intel_shared_dpll *pll;
6514         int ret;
6515
6516         for_each_encoder_on_crtc(dev, crtc, encoder) {
6517                 switch (encoder->type) {
6518                 case INTEL_OUTPUT_LVDS:
6519                         is_lvds = true;
6520                         break;
6521                 }
6522
6523                 num_connectors++;
6524         }
6525
6526         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6527              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6528
6529         ok = ironlake_compute_clocks(crtc, &clock,
6530                                      &has_reduced_clock, &reduced_clock);
6531         if (!ok && !intel_crtc->config.clock_set) {
6532                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6533                 return -EINVAL;
6534         }
6535         /* Compat-code for transition, will disappear. */
6536         if (!intel_crtc->config.clock_set) {
6537                 intel_crtc->config.dpll.n = clock.n;
6538                 intel_crtc->config.dpll.m1 = clock.m1;
6539                 intel_crtc->config.dpll.m2 = clock.m2;
6540                 intel_crtc->config.dpll.p1 = clock.p1;
6541                 intel_crtc->config.dpll.p2 = clock.p2;
6542         }
6543
6544         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6545         if (intel_crtc->config.has_pch_encoder) {
6546                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6547                 if (has_reduced_clock)
6548                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6549
6550                 dpll = ironlake_compute_dpll(intel_crtc,
6551                                              &fp, &reduced_clock,
6552                                              has_reduced_clock ? &fp2 : NULL);
6553
6554                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6555                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6556                 if (has_reduced_clock)
6557                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6558                 else
6559                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6560
6561                 pll = intel_get_shared_dpll(intel_crtc);
6562                 if (pll == NULL) {
6563                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6564                                          pipe_name(pipe));
6565                         return -EINVAL;
6566                 }
6567         } else
6568                 intel_put_shared_dpll(intel_crtc);
6569
6570         if (intel_crtc->config.has_dp_encoder)
6571                 intel_dp_set_m_n(intel_crtc);
6572
6573         if (is_lvds && has_reduced_clock && i915.powersave)
6574                 intel_crtc->lowfreq_avail = true;
6575         else
6576                 intel_crtc->lowfreq_avail = false;
6577
6578         intel_set_pipe_timings(intel_crtc);
6579
6580         if (intel_crtc->config.has_pch_encoder) {
6581                 intel_cpu_transcoder_set_m_n(intel_crtc,
6582                                              &intel_crtc->config.fdi_m_n);
6583         }
6584
6585         ironlake_set_pipeconf(crtc);
6586
6587         /* Set up the display plane register */
6588         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6589         POSTING_READ(DSPCNTR(plane));
6590
6591         ret = intel_pipe_set_base(crtc, x, y, fb);
6592
6593         return ret;
6594 }
6595
6596 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6597                                          struct intel_link_m_n *m_n)
6598 {
6599         struct drm_device *dev = crtc->base.dev;
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         enum pipe pipe = crtc->pipe;
6602
6603         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6604         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6605         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6606                 & ~TU_SIZE_MASK;
6607         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6608         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6609                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6610 }
6611
6612 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6613                                          enum transcoder transcoder,
6614                                          struct intel_link_m_n *m_n)
6615 {
6616         struct drm_device *dev = crtc->base.dev;
6617         struct drm_i915_private *dev_priv = dev->dev_private;
6618         enum pipe pipe = crtc->pipe;
6619
6620         if (INTEL_INFO(dev)->gen >= 5) {
6621                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6622                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6623                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6624                         & ~TU_SIZE_MASK;
6625                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6626                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6627                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6628         } else {
6629                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6630                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6631                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6632                         & ~TU_SIZE_MASK;
6633                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6634                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6635                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6636         }
6637 }
6638
6639 void intel_dp_get_m_n(struct intel_crtc *crtc,
6640                       struct intel_crtc_config *pipe_config)
6641 {
6642         if (crtc->config.has_pch_encoder)
6643                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6644         else
6645                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6646                                              &pipe_config->dp_m_n);
6647 }
6648
6649 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6650                                         struct intel_crtc_config *pipe_config)
6651 {
6652         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6653                                      &pipe_config->fdi_m_n);
6654 }
6655
6656 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6657                                      struct intel_crtc_config *pipe_config)
6658 {
6659         struct drm_device *dev = crtc->base.dev;
6660         struct drm_i915_private *dev_priv = dev->dev_private;
6661         uint32_t tmp;
6662
6663         tmp = I915_READ(PF_CTL(crtc->pipe));
6664
6665         if (tmp & PF_ENABLE) {
6666                 pipe_config->pch_pfit.enabled = true;
6667                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6668                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6669
6670                 /* We currently do not free assignements of panel fitters on
6671                  * ivb/hsw (since we don't use the higher upscaling modes which
6672                  * differentiates them) so just WARN about this case for now. */
6673                 if (IS_GEN7(dev)) {
6674                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6675                                 PF_PIPE_SEL_IVB(crtc->pipe));
6676                 }
6677         }
6678 }
6679
6680 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6681                                      struct intel_crtc_config *pipe_config)
6682 {
6683         struct drm_device *dev = crtc->base.dev;
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         uint32_t tmp;
6686
6687         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6688         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6689
6690         tmp = I915_READ(PIPECONF(crtc->pipe));
6691         if (!(tmp & PIPECONF_ENABLE))
6692                 return false;
6693
6694         switch (tmp & PIPECONF_BPC_MASK) {
6695         case PIPECONF_6BPC:
6696                 pipe_config->pipe_bpp = 18;
6697                 break;
6698         case PIPECONF_8BPC:
6699                 pipe_config->pipe_bpp = 24;
6700                 break;
6701         case PIPECONF_10BPC:
6702                 pipe_config->pipe_bpp = 30;
6703                 break;
6704         case PIPECONF_12BPC:
6705                 pipe_config->pipe_bpp = 36;
6706                 break;
6707         default:
6708                 break;
6709         }
6710
6711         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6712                 struct intel_shared_dpll *pll;
6713
6714                 pipe_config->has_pch_encoder = true;
6715
6716                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6717                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6718                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6719
6720                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6721
6722                 if (HAS_PCH_IBX(dev_priv->dev)) {
6723                         pipe_config->shared_dpll =
6724                                 (enum intel_dpll_id) crtc->pipe;
6725                 } else {
6726                         tmp = I915_READ(PCH_DPLL_SEL);
6727                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6728                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6729                         else
6730                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6731                 }
6732
6733                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6734
6735                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6736                                            &pipe_config->dpll_hw_state));
6737
6738                 tmp = pipe_config->dpll_hw_state.dpll;
6739                 pipe_config->pixel_multiplier =
6740                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6741                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6742
6743                 ironlake_pch_clock_get(crtc, pipe_config);
6744         } else {
6745                 pipe_config->pixel_multiplier = 1;
6746         }
6747
6748         intel_get_pipe_timings(crtc, pipe_config);
6749
6750         ironlake_get_pfit_config(crtc, pipe_config);
6751
6752         return true;
6753 }
6754
6755 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6756 {
6757         struct drm_device *dev = dev_priv->dev;
6758         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6759         struct intel_crtc *crtc;
6760         unsigned long irqflags;
6761         uint32_t val;
6762
6763         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6764                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6765                      pipe_name(crtc->pipe));
6766
6767         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6768         WARN(plls->spll_refcount, "SPLL enabled\n");
6769         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6770         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6771         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6772         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6773              "CPU PWM1 enabled\n");
6774         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6775              "CPU PWM2 enabled\n");
6776         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6777              "PCH PWM1 enabled\n");
6778         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6779              "Utility pin enabled\n");
6780         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6781
6782         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6783         val = I915_READ(DEIMR);
6784         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6785              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6786         val = I915_READ(SDEIMR);
6787         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6788              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6789         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6790 }
6791
6792 /*
6793  * This function implements pieces of two sequences from BSpec:
6794  * - Sequence for display software to disable LCPLL
6795  * - Sequence for display software to allow package C8+
6796  * The steps implemented here are just the steps that actually touch the LCPLL
6797  * register. Callers should take care of disabling all the display engine
6798  * functions, doing the mode unset, fixing interrupts, etc.
6799  */
6800 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6801                               bool switch_to_fclk, bool allow_power_down)
6802 {
6803         uint32_t val;
6804
6805         assert_can_disable_lcpll(dev_priv);
6806
6807         val = I915_READ(LCPLL_CTL);
6808
6809         if (switch_to_fclk) {
6810                 val |= LCPLL_CD_SOURCE_FCLK;
6811                 I915_WRITE(LCPLL_CTL, val);
6812
6813                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6814                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6815                         DRM_ERROR("Switching to FCLK failed\n");
6816
6817                 val = I915_READ(LCPLL_CTL);
6818         }
6819
6820         val |= LCPLL_PLL_DISABLE;
6821         I915_WRITE(LCPLL_CTL, val);
6822         POSTING_READ(LCPLL_CTL);
6823
6824         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6825                 DRM_ERROR("LCPLL still locked\n");
6826
6827         val = I915_READ(D_COMP);
6828         val |= D_COMP_COMP_DISABLE;
6829         mutex_lock(&dev_priv->rps.hw_lock);
6830         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6831                 DRM_ERROR("Failed to disable D_COMP\n");
6832         mutex_unlock(&dev_priv->rps.hw_lock);
6833         POSTING_READ(D_COMP);
6834         ndelay(100);
6835
6836         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6837                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6838
6839         if (allow_power_down) {
6840                 val = I915_READ(LCPLL_CTL);
6841                 val |= LCPLL_POWER_DOWN_ALLOW;
6842                 I915_WRITE(LCPLL_CTL, val);
6843                 POSTING_READ(LCPLL_CTL);
6844         }
6845 }
6846
6847 /*
6848  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6849  * source.
6850  */
6851 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6852 {
6853         uint32_t val;
6854
6855         val = I915_READ(LCPLL_CTL);
6856
6857         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6858                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6859                 return;
6860
6861         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6862          * we'll hang the machine! */
6863         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6864
6865         if (val & LCPLL_POWER_DOWN_ALLOW) {
6866                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6867                 I915_WRITE(LCPLL_CTL, val);
6868                 POSTING_READ(LCPLL_CTL);
6869         }
6870
6871         val = I915_READ(D_COMP);
6872         val |= D_COMP_COMP_FORCE;
6873         val &= ~D_COMP_COMP_DISABLE;
6874         mutex_lock(&dev_priv->rps.hw_lock);
6875         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6876                 DRM_ERROR("Failed to enable D_COMP\n");
6877         mutex_unlock(&dev_priv->rps.hw_lock);
6878         POSTING_READ(D_COMP);
6879
6880         val = I915_READ(LCPLL_CTL);
6881         val &= ~LCPLL_PLL_DISABLE;
6882         I915_WRITE(LCPLL_CTL, val);
6883
6884         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6885                 DRM_ERROR("LCPLL not locked yet\n");
6886
6887         if (val & LCPLL_CD_SOURCE_FCLK) {
6888                 val = I915_READ(LCPLL_CTL);
6889                 val &= ~LCPLL_CD_SOURCE_FCLK;
6890                 I915_WRITE(LCPLL_CTL, val);
6891
6892                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6893                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6894                         DRM_ERROR("Switching back to LCPLL failed\n");
6895         }
6896
6897         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6898 }
6899
6900 void hsw_enable_pc8_work(struct work_struct *__work)
6901 {
6902         struct drm_i915_private *dev_priv =
6903                 container_of(to_delayed_work(__work), struct drm_i915_private,
6904                              pc8.enable_work);
6905         struct drm_device *dev = dev_priv->dev;
6906         uint32_t val;
6907
6908         WARN_ON(!HAS_PC8(dev));
6909
6910         if (dev_priv->pc8.enabled)
6911                 return;
6912
6913         DRM_DEBUG_KMS("Enabling package C8+\n");
6914
6915         dev_priv->pc8.enabled = true;
6916
6917         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6918                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6919                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6920                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6921         }
6922
6923         lpt_disable_clkout_dp(dev);
6924         hsw_pc8_disable_interrupts(dev);
6925         hsw_disable_lcpll(dev_priv, true, true);
6926
6927         intel_runtime_pm_put(dev_priv);
6928 }
6929
6930 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6931 {
6932         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6933         WARN(dev_priv->pc8.disable_count < 1,
6934              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6935
6936         dev_priv->pc8.disable_count--;
6937         if (dev_priv->pc8.disable_count != 0)
6938                 return;
6939
6940         schedule_delayed_work(&dev_priv->pc8.enable_work,
6941                               msecs_to_jiffies(i915.pc8_timeout));
6942 }
6943
6944 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6945 {
6946         struct drm_device *dev = dev_priv->dev;
6947         uint32_t val;
6948
6949         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6950         WARN(dev_priv->pc8.disable_count < 0,
6951              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6952
6953         dev_priv->pc8.disable_count++;
6954         if (dev_priv->pc8.disable_count != 1)
6955                 return;
6956
6957         WARN_ON(!HAS_PC8(dev));
6958
6959         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6960         if (!dev_priv->pc8.enabled)
6961                 return;
6962
6963         DRM_DEBUG_KMS("Disabling package C8+\n");
6964
6965         intel_runtime_pm_get(dev_priv);
6966
6967         hsw_restore_lcpll(dev_priv);
6968         hsw_pc8_restore_interrupts(dev);
6969         lpt_init_pch_refclk(dev);
6970
6971         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6972                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6973                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6974                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6975         }
6976
6977         intel_prepare_ddi(dev);
6978         i915_gem_init_swizzling(dev);
6979         mutex_lock(&dev_priv->rps.hw_lock);
6980         gen6_update_ring_freq(dev);
6981         mutex_unlock(&dev_priv->rps.hw_lock);
6982         dev_priv->pc8.enabled = false;
6983 }
6984
6985 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6986 {
6987         if (!HAS_PC8(dev_priv->dev))
6988                 return;
6989
6990         mutex_lock(&dev_priv->pc8.lock);
6991         __hsw_enable_package_c8(dev_priv);
6992         mutex_unlock(&dev_priv->pc8.lock);
6993 }
6994
6995 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6996 {
6997         if (!HAS_PC8(dev_priv->dev))
6998                 return;
6999
7000         mutex_lock(&dev_priv->pc8.lock);
7001         __hsw_disable_package_c8(dev_priv);
7002         mutex_unlock(&dev_priv->pc8.lock);
7003 }
7004
7005 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
7006 {
7007         struct drm_device *dev = dev_priv->dev;
7008         struct intel_crtc *crtc;
7009         uint32_t val;
7010
7011         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
7012                 if (crtc->base.enabled)
7013                         return false;
7014
7015         /* This case is still possible since we have the i915.disable_power_well
7016          * parameter and also the KVMr or something else might be requesting the
7017          * power well. */
7018         val = I915_READ(HSW_PWR_WELL_DRIVER);
7019         if (val != 0) {
7020                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
7021                 return false;
7022         }
7023
7024         return true;
7025 }
7026
7027 /* Since we're called from modeset_global_resources there's no way to
7028  * symmetrically increase and decrease the refcount, so we use
7029  * dev_priv->pc8.requirements_met to track whether we already have the refcount
7030  * or not.
7031  */
7032 static void hsw_update_package_c8(struct drm_device *dev)
7033 {
7034         struct drm_i915_private *dev_priv = dev->dev_private;
7035         bool allow;
7036
7037         if (!HAS_PC8(dev_priv->dev))
7038                 return;
7039
7040         if (!i915.enable_pc8)
7041                 return;
7042
7043         mutex_lock(&dev_priv->pc8.lock);
7044
7045         allow = hsw_can_enable_package_c8(dev_priv);
7046
7047         if (allow == dev_priv->pc8.requirements_met)
7048                 goto done;
7049
7050         dev_priv->pc8.requirements_met = allow;
7051
7052         if (allow)
7053                 __hsw_enable_package_c8(dev_priv);
7054         else
7055                 __hsw_disable_package_c8(dev_priv);
7056
7057 done:
7058         mutex_unlock(&dev_priv->pc8.lock);
7059 }
7060
7061 static void haswell_modeset_global_resources(struct drm_device *dev)
7062 {
7063         modeset_update_crtc_power_domains(dev);
7064         hsw_update_package_c8(dev);
7065 }
7066
7067 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7068                                  int x, int y,
7069                                  struct drm_framebuffer *fb)
7070 {
7071         struct drm_device *dev = crtc->dev;
7072         struct drm_i915_private *dev_priv = dev->dev_private;
7073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7074         int plane = intel_crtc->plane;
7075         int ret;
7076
7077         if (!intel_ddi_pll_select(intel_crtc))
7078                 return -EINVAL;
7079         intel_ddi_pll_enable(intel_crtc);
7080
7081         if (intel_crtc->config.has_dp_encoder)
7082                 intel_dp_set_m_n(intel_crtc);
7083
7084         intel_crtc->lowfreq_avail = false;
7085
7086         intel_set_pipe_timings(intel_crtc);
7087
7088         if (intel_crtc->config.has_pch_encoder) {
7089                 intel_cpu_transcoder_set_m_n(intel_crtc,
7090                                              &intel_crtc->config.fdi_m_n);
7091         }
7092
7093         haswell_set_pipeconf(crtc);
7094
7095         intel_set_pipe_csc(crtc);
7096
7097         /* Set up the display plane register */
7098         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7099         POSTING_READ(DSPCNTR(plane));
7100
7101         ret = intel_pipe_set_base(crtc, x, y, fb);
7102
7103         return ret;
7104 }
7105
7106 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7107                                     struct intel_crtc_config *pipe_config)
7108 {
7109         struct drm_device *dev = crtc->base.dev;
7110         struct drm_i915_private *dev_priv = dev->dev_private;
7111         enum intel_display_power_domain pfit_domain;
7112         uint32_t tmp;
7113
7114         if (!intel_display_power_enabled(dev_priv,
7115                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7116                 return false;
7117
7118         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7119         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7120
7121         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7122         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7123                 enum pipe trans_edp_pipe;
7124                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7125                 default:
7126                         WARN(1, "unknown pipe linked to edp transcoder\n");
7127                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7128                 case TRANS_DDI_EDP_INPUT_A_ON:
7129                         trans_edp_pipe = PIPE_A;
7130                         break;
7131                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7132                         trans_edp_pipe = PIPE_B;
7133                         break;
7134                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7135                         trans_edp_pipe = PIPE_C;
7136                         break;
7137                 }
7138
7139                 if (trans_edp_pipe == crtc->pipe)
7140                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7141         }
7142
7143         if (!intel_display_power_enabled(dev_priv,
7144                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7145                 return false;
7146
7147         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7148         if (!(tmp & PIPECONF_ENABLE))
7149                 return false;
7150
7151         /*
7152          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7153          * DDI E. So just check whether this pipe is wired to DDI E and whether
7154          * the PCH transcoder is on.
7155          */
7156         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7157         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7158             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7159                 pipe_config->has_pch_encoder = true;
7160
7161                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7162                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7163                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7164
7165                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7166         }
7167
7168         intel_get_pipe_timings(crtc, pipe_config);
7169
7170         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7171         if (intel_display_power_enabled(dev_priv, pfit_domain))
7172                 ironlake_get_pfit_config(crtc, pipe_config);
7173
7174         if (IS_HASWELL(dev))
7175                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7176                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7177
7178         pipe_config->pixel_multiplier = 1;
7179
7180         return true;
7181 }
7182
7183 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7184                                int x, int y,
7185                                struct drm_framebuffer *fb)
7186 {
7187         struct drm_device *dev = crtc->dev;
7188         struct drm_i915_private *dev_priv = dev->dev_private;
7189         struct intel_encoder *encoder;
7190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7191         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7192         int pipe = intel_crtc->pipe;
7193         int ret;
7194
7195         drm_vblank_pre_modeset(dev, pipe);
7196
7197         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7198
7199         drm_vblank_post_modeset(dev, pipe);
7200
7201         if (ret != 0)
7202                 return ret;
7203
7204         for_each_encoder_on_crtc(dev, crtc, encoder) {
7205                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7206                         encoder->base.base.id,
7207                         drm_get_encoder_name(&encoder->base),
7208                         mode->base.id, mode->name);
7209                 encoder->mode_set(encoder);
7210         }
7211
7212         return 0;
7213 }
7214
7215 static struct {
7216         int clock;
7217         u32 config;
7218 } hdmi_audio_clock[] = {
7219         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7220         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7221         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7222         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7223         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7224         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7225         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7226         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7227         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7228         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7229 };
7230
7231 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7232 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7233 {
7234         int i;
7235
7236         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7237                 if (mode->clock == hdmi_audio_clock[i].clock)
7238                         break;
7239         }
7240
7241         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7242                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7243                 i = 1;
7244         }
7245
7246         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7247                       hdmi_audio_clock[i].clock,
7248                       hdmi_audio_clock[i].config);
7249
7250         return hdmi_audio_clock[i].config;
7251 }
7252
7253 static bool intel_eld_uptodate(struct drm_connector *connector,
7254                                int reg_eldv, uint32_t bits_eldv,
7255                                int reg_elda, uint32_t bits_elda,
7256                                int reg_edid)
7257 {
7258         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7259         uint8_t *eld = connector->eld;
7260         uint32_t i;
7261
7262         i = I915_READ(reg_eldv);
7263         i &= bits_eldv;
7264
7265         if (!eld[0])
7266                 return !i;
7267
7268         if (!i)
7269                 return false;
7270
7271         i = I915_READ(reg_elda);
7272         i &= ~bits_elda;
7273         I915_WRITE(reg_elda, i);
7274
7275         for (i = 0; i < eld[2]; i++)
7276                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7277                         return false;
7278
7279         return true;
7280 }
7281
7282 static void g4x_write_eld(struct drm_connector *connector,
7283                           struct drm_crtc *crtc,
7284                           struct drm_display_mode *mode)
7285 {
7286         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7287         uint8_t *eld = connector->eld;
7288         uint32_t eldv;
7289         uint32_t len;
7290         uint32_t i;
7291
7292         i = I915_READ(G4X_AUD_VID_DID);
7293
7294         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7295                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7296         else
7297                 eldv = G4X_ELDV_DEVCTG;
7298
7299         if (intel_eld_uptodate(connector,
7300                                G4X_AUD_CNTL_ST, eldv,
7301                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7302                                G4X_HDMIW_HDMIEDID))
7303                 return;
7304
7305         i = I915_READ(G4X_AUD_CNTL_ST);
7306         i &= ~(eldv | G4X_ELD_ADDR);
7307         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7308         I915_WRITE(G4X_AUD_CNTL_ST, i);
7309
7310         if (!eld[0])
7311                 return;
7312
7313         len = min_t(uint8_t, eld[2], len);
7314         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7315         for (i = 0; i < len; i++)
7316                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7317
7318         i = I915_READ(G4X_AUD_CNTL_ST);
7319         i |= eldv;
7320         I915_WRITE(G4X_AUD_CNTL_ST, i);
7321 }
7322
7323 static void haswell_write_eld(struct drm_connector *connector,
7324                               struct drm_crtc *crtc,
7325                               struct drm_display_mode *mode)
7326 {
7327         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7328         uint8_t *eld = connector->eld;
7329         struct drm_device *dev = crtc->dev;
7330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7331         uint32_t eldv;
7332         uint32_t i;
7333         int len;
7334         int pipe = to_intel_crtc(crtc)->pipe;
7335         int tmp;
7336
7337         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7338         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7339         int aud_config = HSW_AUD_CFG(pipe);
7340         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7341
7342
7343         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7344
7345         /* Audio output enable */
7346         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7347         tmp = I915_READ(aud_cntrl_st2);
7348         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7349         I915_WRITE(aud_cntrl_st2, tmp);
7350
7351         /* Wait for 1 vertical blank */
7352         intel_wait_for_vblank(dev, pipe);
7353
7354         /* Set ELD valid state */
7355         tmp = I915_READ(aud_cntrl_st2);
7356         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7357         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7358         I915_WRITE(aud_cntrl_st2, tmp);
7359         tmp = I915_READ(aud_cntrl_st2);
7360         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7361
7362         /* Enable HDMI mode */
7363         tmp = I915_READ(aud_config);
7364         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7365         /* clear N_programing_enable and N_value_index */
7366         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7367         I915_WRITE(aud_config, tmp);
7368
7369         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7370
7371         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7372         intel_crtc->eld_vld = true;
7373
7374         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7375                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7376                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7377                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7378         } else {
7379                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7380         }
7381
7382         if (intel_eld_uptodate(connector,
7383                                aud_cntrl_st2, eldv,
7384                                aud_cntl_st, IBX_ELD_ADDRESS,
7385                                hdmiw_hdmiedid))
7386                 return;
7387
7388         i = I915_READ(aud_cntrl_st2);
7389         i &= ~eldv;
7390         I915_WRITE(aud_cntrl_st2, i);
7391
7392         if (!eld[0])
7393                 return;
7394
7395         i = I915_READ(aud_cntl_st);
7396         i &= ~IBX_ELD_ADDRESS;
7397         I915_WRITE(aud_cntl_st, i);
7398         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7399         DRM_DEBUG_DRIVER("port num:%d\n", i);
7400
7401         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7402         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7403         for (i = 0; i < len; i++)
7404                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7405
7406         i = I915_READ(aud_cntrl_st2);
7407         i |= eldv;
7408         I915_WRITE(aud_cntrl_st2, i);
7409
7410 }
7411
7412 static void ironlake_write_eld(struct drm_connector *connector,
7413                                struct drm_crtc *crtc,
7414                                struct drm_display_mode *mode)
7415 {
7416         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7417         uint8_t *eld = connector->eld;
7418         uint32_t eldv;
7419         uint32_t i;
7420         int len;
7421         int hdmiw_hdmiedid;
7422         int aud_config;
7423         int aud_cntl_st;
7424         int aud_cntrl_st2;
7425         int pipe = to_intel_crtc(crtc)->pipe;
7426
7427         if (HAS_PCH_IBX(connector->dev)) {
7428                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7429                 aud_config = IBX_AUD_CFG(pipe);
7430                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7431                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7432         } else if (IS_VALLEYVIEW(connector->dev)) {
7433                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7434                 aud_config = VLV_AUD_CFG(pipe);
7435                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7436                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7437         } else {
7438                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7439                 aud_config = CPT_AUD_CFG(pipe);
7440                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7441                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7442         }
7443
7444         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7445
7446         if (IS_VALLEYVIEW(connector->dev))  {
7447                 struct intel_encoder *intel_encoder;
7448                 struct intel_digital_port *intel_dig_port;
7449
7450                 intel_encoder = intel_attached_encoder(connector);
7451                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7452                 i = intel_dig_port->port;
7453         } else {
7454                 i = I915_READ(aud_cntl_st);
7455                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7456                 /* DIP_Port_Select, 0x1 = PortB */
7457         }
7458
7459         if (!i) {
7460                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7461                 /* operate blindly on all ports */
7462                 eldv = IBX_ELD_VALIDB;
7463                 eldv |= IBX_ELD_VALIDB << 4;
7464                 eldv |= IBX_ELD_VALIDB << 8;
7465         } else {
7466                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7467                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7468         }
7469
7470         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7471                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7472                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7473                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7474         } else {
7475                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7476         }
7477
7478         if (intel_eld_uptodate(connector,
7479                                aud_cntrl_st2, eldv,
7480                                aud_cntl_st, IBX_ELD_ADDRESS,
7481                                hdmiw_hdmiedid))
7482                 return;
7483
7484         i = I915_READ(aud_cntrl_st2);
7485         i &= ~eldv;
7486         I915_WRITE(aud_cntrl_st2, i);
7487
7488         if (!eld[0])
7489                 return;
7490
7491         i = I915_READ(aud_cntl_st);
7492         i &= ~IBX_ELD_ADDRESS;
7493         I915_WRITE(aud_cntl_st, i);
7494
7495         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7496         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7497         for (i = 0; i < len; i++)
7498                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7499
7500         i = I915_READ(aud_cntrl_st2);
7501         i |= eldv;
7502         I915_WRITE(aud_cntrl_st2, i);
7503 }
7504
7505 void intel_write_eld(struct drm_encoder *encoder,
7506                      struct drm_display_mode *mode)
7507 {
7508         struct drm_crtc *crtc = encoder->crtc;
7509         struct drm_connector *connector;
7510         struct drm_device *dev = encoder->dev;
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512
7513         connector = drm_select_eld(encoder, mode);
7514         if (!connector)
7515                 return;
7516
7517         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7518                          connector->base.id,
7519                          drm_get_connector_name(connector),
7520                          connector->encoder->base.id,
7521                          drm_get_encoder_name(connector->encoder));
7522
7523         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7524
7525         if (dev_priv->display.write_eld)
7526                 dev_priv->display.write_eld(connector, crtc, mode);
7527 }
7528
7529 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7530 {
7531         struct drm_device *dev = crtc->dev;
7532         struct drm_i915_private *dev_priv = dev->dev_private;
7533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7534         bool visible = base != 0;
7535         u32 cntl;
7536
7537         if (intel_crtc->cursor_visible == visible)
7538                 return;
7539
7540         cntl = I915_READ(_CURACNTR);
7541         if (visible) {
7542                 /* On these chipsets we can only modify the base whilst
7543                  * the cursor is disabled.
7544                  */
7545                 I915_WRITE(_CURABASE, base);
7546
7547                 cntl &= ~(CURSOR_FORMAT_MASK);
7548                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7549                 cntl |= CURSOR_ENABLE |
7550                         CURSOR_GAMMA_ENABLE |
7551                         CURSOR_FORMAT_ARGB;
7552         } else
7553                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7554         I915_WRITE(_CURACNTR, cntl);
7555
7556         intel_crtc->cursor_visible = visible;
7557 }
7558
7559 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7560 {
7561         struct drm_device *dev = crtc->dev;
7562         struct drm_i915_private *dev_priv = dev->dev_private;
7563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564         int pipe = intel_crtc->pipe;
7565         bool visible = base != 0;
7566
7567         if (intel_crtc->cursor_visible != visible) {
7568                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7569                 if (base) {
7570                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7571                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7572                         cntl |= pipe << 28; /* Connect to correct pipe */
7573                 } else {
7574                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7575                         cntl |= CURSOR_MODE_DISABLE;
7576                 }
7577                 I915_WRITE(CURCNTR(pipe), cntl);
7578
7579                 intel_crtc->cursor_visible = visible;
7580         }
7581         /* and commit changes on next vblank */
7582         POSTING_READ(CURCNTR(pipe));
7583         I915_WRITE(CURBASE(pipe), base);
7584         POSTING_READ(CURBASE(pipe));
7585 }
7586
7587 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7588 {
7589         struct drm_device *dev = crtc->dev;
7590         struct drm_i915_private *dev_priv = dev->dev_private;
7591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7592         int pipe = intel_crtc->pipe;
7593         bool visible = base != 0;
7594
7595         if (intel_crtc->cursor_visible != visible) {
7596                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7597                 if (base) {
7598                         cntl &= ~CURSOR_MODE;
7599                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7600                 } else {
7601                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7602                         cntl |= CURSOR_MODE_DISABLE;
7603                 }
7604                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7605                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7606                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7607                 }
7608                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7609
7610                 intel_crtc->cursor_visible = visible;
7611         }
7612         /* and commit changes on next vblank */
7613         POSTING_READ(CURCNTR_IVB(pipe));
7614         I915_WRITE(CURBASE_IVB(pipe), base);
7615         POSTING_READ(CURBASE_IVB(pipe));
7616 }
7617
7618 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7619 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7620                                      bool on)
7621 {
7622         struct drm_device *dev = crtc->dev;
7623         struct drm_i915_private *dev_priv = dev->dev_private;
7624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7625         int pipe = intel_crtc->pipe;
7626         int x = intel_crtc->cursor_x;
7627         int y = intel_crtc->cursor_y;
7628         u32 base = 0, pos = 0;
7629         bool visible;
7630
7631         if (on)
7632                 base = intel_crtc->cursor_addr;
7633
7634         if (x >= intel_crtc->config.pipe_src_w)
7635                 base = 0;
7636
7637         if (y >= intel_crtc->config.pipe_src_h)
7638                 base = 0;
7639
7640         if (x < 0) {
7641                 if (x + intel_crtc->cursor_width <= 0)
7642                         base = 0;
7643
7644                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7645                 x = -x;
7646         }
7647         pos |= x << CURSOR_X_SHIFT;
7648
7649         if (y < 0) {
7650                 if (y + intel_crtc->cursor_height <= 0)
7651                         base = 0;
7652
7653                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7654                 y = -y;
7655         }
7656         pos |= y << CURSOR_Y_SHIFT;
7657
7658         visible = base != 0;
7659         if (!visible && !intel_crtc->cursor_visible)
7660                 return;
7661
7662         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7663                 I915_WRITE(CURPOS_IVB(pipe), pos);
7664                 ivb_update_cursor(crtc, base);
7665         } else {
7666                 I915_WRITE(CURPOS(pipe), pos);
7667                 if (IS_845G(dev) || IS_I865G(dev))
7668                         i845_update_cursor(crtc, base);
7669                 else
7670                         i9xx_update_cursor(crtc, base);
7671         }
7672 }
7673
7674 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7675                                  struct drm_file *file,
7676                                  uint32_t handle,
7677                                  uint32_t width, uint32_t height)
7678 {
7679         struct drm_device *dev = crtc->dev;
7680         struct drm_i915_private *dev_priv = dev->dev_private;
7681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7682         struct drm_i915_gem_object *obj;
7683         uint32_t addr;
7684         int ret;
7685
7686         /* if we want to turn off the cursor ignore width and height */
7687         if (!handle) {
7688                 DRM_DEBUG_KMS("cursor off\n");
7689                 addr = 0;
7690                 obj = NULL;
7691                 mutex_lock(&dev->struct_mutex);
7692                 goto finish;
7693         }
7694
7695         /* Currently we only support 64x64 cursors */
7696         if (width != 64 || height != 64) {
7697                 DRM_ERROR("we currently only support 64x64 cursors\n");
7698                 return -EINVAL;
7699         }
7700
7701         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7702         if (&obj->base == NULL)
7703                 return -ENOENT;
7704
7705         if (obj->base.size < width * height * 4) {
7706                 DRM_DEBUG_KMS("buffer is to small\n");
7707                 ret = -ENOMEM;
7708                 goto fail;
7709         }
7710
7711         /* we only need to pin inside GTT if cursor is non-phy */
7712         mutex_lock(&dev->struct_mutex);
7713         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7714                 unsigned alignment;
7715
7716                 if (obj->tiling_mode) {
7717                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7718                         ret = -EINVAL;
7719                         goto fail_locked;
7720                 }
7721
7722                 /* Note that the w/a also requires 2 PTE of padding following
7723                  * the bo. We currently fill all unused PTE with the shadow
7724                  * page and so we should always have valid PTE following the
7725                  * cursor preventing the VT-d warning.
7726                  */
7727                 alignment = 0;
7728                 if (need_vtd_wa(dev))
7729                         alignment = 64*1024;
7730
7731                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7732                 if (ret) {
7733                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7734                         goto fail_locked;
7735                 }
7736
7737                 ret = i915_gem_object_put_fence(obj);
7738                 if (ret) {
7739                         DRM_DEBUG_KMS("failed to release fence for cursor");
7740                         goto fail_unpin;
7741                 }
7742
7743                 addr = i915_gem_obj_ggtt_offset(obj);
7744         } else {
7745                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7746                 ret = i915_gem_attach_phys_object(dev, obj,
7747                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7748                                                   align);
7749                 if (ret) {
7750                         DRM_DEBUG_KMS("failed to attach phys object\n");
7751                         goto fail_locked;
7752                 }
7753                 addr = obj->phys_obj->handle->busaddr;
7754         }
7755
7756         if (IS_GEN2(dev))
7757                 I915_WRITE(CURSIZE, (height << 12) | width);
7758
7759  finish:
7760         if (intel_crtc->cursor_bo) {
7761                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7762                         if (intel_crtc->cursor_bo != obj)
7763                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7764                 } else
7765                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7766                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7767         }
7768
7769         mutex_unlock(&dev->struct_mutex);
7770
7771         intel_crtc->cursor_addr = addr;
7772         intel_crtc->cursor_bo = obj;
7773         intel_crtc->cursor_width = width;
7774         intel_crtc->cursor_height = height;
7775
7776         if (intel_crtc->active)
7777                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7778
7779         return 0;
7780 fail_unpin:
7781         i915_gem_object_unpin_from_display_plane(obj);
7782 fail_locked:
7783         mutex_unlock(&dev->struct_mutex);
7784 fail:
7785         drm_gem_object_unreference_unlocked(&obj->base);
7786         return ret;
7787 }
7788
7789 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7790 {
7791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7792
7793         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7794         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7795
7796         if (intel_crtc->active)
7797                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7798
7799         return 0;
7800 }
7801
7802 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7803                                  u16 *blue, uint32_t start, uint32_t size)
7804 {
7805         int end = (start + size > 256) ? 256 : start + size, i;
7806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7807
7808         for (i = start; i < end; i++) {
7809                 intel_crtc->lut_r[i] = red[i] >> 8;
7810                 intel_crtc->lut_g[i] = green[i] >> 8;
7811                 intel_crtc->lut_b[i] = blue[i] >> 8;
7812         }
7813
7814         intel_crtc_load_lut(crtc);
7815 }
7816
7817 /* VESA 640x480x72Hz mode to set on the pipe */
7818 static struct drm_display_mode load_detect_mode = {
7819         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7820                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7821 };
7822
7823 struct drm_framebuffer *
7824 __intel_framebuffer_create(struct drm_device *dev,
7825                            struct drm_mode_fb_cmd2 *mode_cmd,
7826                            struct drm_i915_gem_object *obj)
7827 {
7828         struct intel_framebuffer *intel_fb;
7829         int ret;
7830
7831         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7832         if (!intel_fb) {
7833                 drm_gem_object_unreference_unlocked(&obj->base);
7834                 return ERR_PTR(-ENOMEM);
7835         }
7836
7837         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7838         if (ret)
7839                 goto err;
7840
7841         return &intel_fb->base;
7842 err:
7843         drm_gem_object_unreference_unlocked(&obj->base);
7844         kfree(intel_fb);
7845
7846         return ERR_PTR(ret);
7847 }
7848
7849 static struct drm_framebuffer *
7850 intel_framebuffer_create(struct drm_device *dev,
7851                          struct drm_mode_fb_cmd2 *mode_cmd,
7852                          struct drm_i915_gem_object *obj)
7853 {
7854         struct drm_framebuffer *fb;
7855         int ret;
7856
7857         ret = i915_mutex_lock_interruptible(dev);
7858         if (ret)
7859                 return ERR_PTR(ret);
7860         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7861         mutex_unlock(&dev->struct_mutex);
7862
7863         return fb;
7864 }
7865
7866 static u32
7867 intel_framebuffer_pitch_for_width(int width, int bpp)
7868 {
7869         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7870         return ALIGN(pitch, 64);
7871 }
7872
7873 static u32
7874 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7875 {
7876         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7877         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7878 }
7879
7880 static struct drm_framebuffer *
7881 intel_framebuffer_create_for_mode(struct drm_device *dev,
7882                                   struct drm_display_mode *mode,
7883                                   int depth, int bpp)
7884 {
7885         struct drm_i915_gem_object *obj;
7886         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7887
7888         obj = i915_gem_alloc_object(dev,
7889                                     intel_framebuffer_size_for_mode(mode, bpp));
7890         if (obj == NULL)
7891                 return ERR_PTR(-ENOMEM);
7892
7893         mode_cmd.width = mode->hdisplay;
7894         mode_cmd.height = mode->vdisplay;
7895         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7896                                                                 bpp);
7897         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7898
7899         return intel_framebuffer_create(dev, &mode_cmd, obj);
7900 }
7901
7902 static struct drm_framebuffer *
7903 mode_fits_in_fbdev(struct drm_device *dev,
7904                    struct drm_display_mode *mode)
7905 {
7906 #ifdef CONFIG_DRM_I915_FBDEV
7907         struct drm_i915_private *dev_priv = dev->dev_private;
7908         struct drm_i915_gem_object *obj;
7909         struct drm_framebuffer *fb;
7910
7911         if (!dev_priv->fbdev)
7912                 return NULL;
7913
7914         if (!dev_priv->fbdev->fb)
7915                 return NULL;
7916
7917         obj = dev_priv->fbdev->fb->obj;
7918         BUG_ON(!obj);
7919
7920         fb = &dev_priv->fbdev->fb->base;
7921         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7922                                                                fb->bits_per_pixel))
7923                 return NULL;
7924
7925         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7926                 return NULL;
7927
7928         return fb;
7929 #else
7930         return NULL;
7931 #endif
7932 }
7933
7934 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7935                                 struct drm_display_mode *mode,
7936                                 struct intel_load_detect_pipe *old)
7937 {
7938         struct intel_crtc *intel_crtc;
7939         struct intel_encoder *intel_encoder =
7940                 intel_attached_encoder(connector);
7941         struct drm_crtc *possible_crtc;
7942         struct drm_encoder *encoder = &intel_encoder->base;
7943         struct drm_crtc *crtc = NULL;
7944         struct drm_device *dev = encoder->dev;
7945         struct drm_framebuffer *fb;
7946         int i = -1;
7947
7948         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7949                       connector->base.id, drm_get_connector_name(connector),
7950                       encoder->base.id, drm_get_encoder_name(encoder));
7951
7952         /*
7953          * Algorithm gets a little messy:
7954          *
7955          *   - if the connector already has an assigned crtc, use it (but make
7956          *     sure it's on first)
7957          *
7958          *   - try to find the first unused crtc that can drive this connector,
7959          *     and use that if we find one
7960          */
7961
7962         /* See if we already have a CRTC for this connector */
7963         if (encoder->crtc) {
7964                 crtc = encoder->crtc;
7965
7966                 mutex_lock(&crtc->mutex);
7967
7968                 old->dpms_mode = connector->dpms;
7969                 old->load_detect_temp = false;
7970
7971                 /* Make sure the crtc and connector are running */
7972                 if (connector->dpms != DRM_MODE_DPMS_ON)
7973                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7974
7975                 return true;
7976         }
7977
7978         /* Find an unused one (if possible) */
7979         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7980                 i++;
7981                 if (!(encoder->possible_crtcs & (1 << i)))
7982                         continue;
7983                 if (!possible_crtc->enabled) {
7984                         crtc = possible_crtc;
7985                         break;
7986                 }
7987         }
7988
7989         /*
7990          * If we didn't find an unused CRTC, don't use any.
7991          */
7992         if (!crtc) {
7993                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7994                 return false;
7995         }
7996
7997         mutex_lock(&crtc->mutex);
7998         intel_encoder->new_crtc = to_intel_crtc(crtc);
7999         to_intel_connector(connector)->new_encoder = intel_encoder;
8000
8001         intel_crtc = to_intel_crtc(crtc);
8002         intel_crtc->new_enabled = true;
8003         intel_crtc->new_config = &intel_crtc->config;
8004         old->dpms_mode = connector->dpms;
8005         old->load_detect_temp = true;
8006         old->release_fb = NULL;
8007
8008         if (!mode)
8009                 mode = &load_detect_mode;
8010
8011         /* We need a framebuffer large enough to accommodate all accesses
8012          * that the plane may generate whilst we perform load detection.
8013          * We can not rely on the fbcon either being present (we get called
8014          * during its initialisation to detect all boot displays, or it may
8015          * not even exist) or that it is large enough to satisfy the
8016          * requested mode.
8017          */
8018         fb = mode_fits_in_fbdev(dev, mode);
8019         if (fb == NULL) {
8020                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8021                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8022                 old->release_fb = fb;
8023         } else
8024                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8025         if (IS_ERR(fb)) {
8026                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8027                 goto fail;
8028         }
8029
8030         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8031                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8032                 if (old->release_fb)
8033                         old->release_fb->funcs->destroy(old->release_fb);
8034                 goto fail;
8035         }
8036
8037         /* let the connector get through one full cycle before testing */
8038         intel_wait_for_vblank(dev, intel_crtc->pipe);
8039         return true;
8040
8041  fail:
8042         intel_crtc->new_enabled = crtc->enabled;
8043         if (intel_crtc->new_enabled)
8044                 intel_crtc->new_config = &intel_crtc->config;
8045         else
8046                 intel_crtc->new_config = NULL;
8047         mutex_unlock(&crtc->mutex);
8048         return false;
8049 }
8050
8051 void intel_release_load_detect_pipe(struct drm_connector *connector,
8052                                     struct intel_load_detect_pipe *old)
8053 {
8054         struct intel_encoder *intel_encoder =
8055                 intel_attached_encoder(connector);
8056         struct drm_encoder *encoder = &intel_encoder->base;
8057         struct drm_crtc *crtc = encoder->crtc;
8058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8059
8060         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8061                       connector->base.id, drm_get_connector_name(connector),
8062                       encoder->base.id, drm_get_encoder_name(encoder));
8063
8064         if (old->load_detect_temp) {
8065                 to_intel_connector(connector)->new_encoder = NULL;
8066                 intel_encoder->new_crtc = NULL;
8067                 intel_crtc->new_enabled = false;
8068                 intel_crtc->new_config = NULL;
8069                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8070
8071                 if (old->release_fb) {
8072                         drm_framebuffer_unregister_private(old->release_fb);
8073                         drm_framebuffer_unreference(old->release_fb);
8074                 }
8075
8076                 mutex_unlock(&crtc->mutex);
8077                 return;
8078         }
8079
8080         /* Switch crtc and encoder back off if necessary */
8081         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8082                 connector->funcs->dpms(connector, old->dpms_mode);
8083
8084         mutex_unlock(&crtc->mutex);
8085 }
8086
8087 static int i9xx_pll_refclk(struct drm_device *dev,
8088                            const struct intel_crtc_config *pipe_config)
8089 {
8090         struct drm_i915_private *dev_priv = dev->dev_private;
8091         u32 dpll = pipe_config->dpll_hw_state.dpll;
8092
8093         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8094                 return dev_priv->vbt.lvds_ssc_freq;
8095         else if (HAS_PCH_SPLIT(dev))
8096                 return 120000;
8097         else if (!IS_GEN2(dev))
8098                 return 96000;
8099         else
8100                 return 48000;
8101 }
8102
8103 /* Returns the clock of the currently programmed mode of the given pipe. */
8104 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8105                                 struct intel_crtc_config *pipe_config)
8106 {
8107         struct drm_device *dev = crtc->base.dev;
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         int pipe = pipe_config->cpu_transcoder;
8110         u32 dpll = pipe_config->dpll_hw_state.dpll;
8111         u32 fp;
8112         intel_clock_t clock;
8113         int refclk = i9xx_pll_refclk(dev, pipe_config);
8114
8115         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8116                 fp = pipe_config->dpll_hw_state.fp0;
8117         else
8118                 fp = pipe_config->dpll_hw_state.fp1;
8119
8120         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8121         if (IS_PINEVIEW(dev)) {
8122                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8123                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8124         } else {
8125                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8126                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8127         }
8128
8129         if (!IS_GEN2(dev)) {
8130                 if (IS_PINEVIEW(dev))
8131                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8132                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8133                 else
8134                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8135                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8136
8137                 switch (dpll & DPLL_MODE_MASK) {
8138                 case DPLLB_MODE_DAC_SERIAL:
8139                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8140                                 5 : 10;
8141                         break;
8142                 case DPLLB_MODE_LVDS:
8143                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8144                                 7 : 14;
8145                         break;
8146                 default:
8147                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8148                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8149                         return;
8150                 }
8151
8152                 if (IS_PINEVIEW(dev))
8153                         pineview_clock(refclk, &clock);
8154                 else
8155                         i9xx_clock(refclk, &clock);
8156         } else {
8157                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8158                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8159
8160                 if (is_lvds) {
8161                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8162                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8163
8164                         if (lvds & LVDS_CLKB_POWER_UP)
8165                                 clock.p2 = 7;
8166                         else
8167                                 clock.p2 = 14;
8168                 } else {
8169                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8170                                 clock.p1 = 2;
8171                         else {
8172                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8173                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8174                         }
8175                         if (dpll & PLL_P2_DIVIDE_BY_4)
8176                                 clock.p2 = 4;
8177                         else
8178                                 clock.p2 = 2;
8179                 }
8180
8181                 i9xx_clock(refclk, &clock);
8182         }
8183
8184         /*
8185          * This value includes pixel_multiplier. We will use
8186          * port_clock to compute adjusted_mode.crtc_clock in the
8187          * encoder's get_config() function.
8188          */
8189         pipe_config->port_clock = clock.dot;
8190 }
8191
8192 int intel_dotclock_calculate(int link_freq,
8193                              const struct intel_link_m_n *m_n)
8194 {
8195         /*
8196          * The calculation for the data clock is:
8197          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8198          * But we want to avoid losing precison if possible, so:
8199          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8200          *
8201          * and the link clock is simpler:
8202          * link_clock = (m * link_clock) / n
8203          */
8204
8205         if (!m_n->link_n)
8206                 return 0;
8207
8208         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8209 }
8210
8211 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8212                                    struct intel_crtc_config *pipe_config)
8213 {
8214         struct drm_device *dev = crtc->base.dev;
8215
8216         /* read out port_clock from the DPLL */
8217         i9xx_crtc_clock_get(crtc, pipe_config);
8218
8219         /*
8220          * This value does not include pixel_multiplier.
8221          * We will check that port_clock and adjusted_mode.crtc_clock
8222          * agree once we know their relationship in the encoder's
8223          * get_config() function.
8224          */
8225         pipe_config->adjusted_mode.crtc_clock =
8226                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8227                                          &pipe_config->fdi_m_n);
8228 }
8229
8230 /** Returns the currently programmed mode of the given pipe. */
8231 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8232                                              struct drm_crtc *crtc)
8233 {
8234         struct drm_i915_private *dev_priv = dev->dev_private;
8235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8236         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8237         struct drm_display_mode *mode;
8238         struct intel_crtc_config pipe_config;
8239         int htot = I915_READ(HTOTAL(cpu_transcoder));
8240         int hsync = I915_READ(HSYNC(cpu_transcoder));
8241         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8242         int vsync = I915_READ(VSYNC(cpu_transcoder));
8243         enum pipe pipe = intel_crtc->pipe;
8244
8245         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8246         if (!mode)
8247                 return NULL;
8248
8249         /*
8250          * Construct a pipe_config sufficient for getting the clock info
8251          * back out of crtc_clock_get.
8252          *
8253          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8254          * to use a real value here instead.
8255          */
8256         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8257         pipe_config.pixel_multiplier = 1;
8258         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8259         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8260         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8261         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8262
8263         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8264         mode->hdisplay = (htot & 0xffff) + 1;
8265         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8266         mode->hsync_start = (hsync & 0xffff) + 1;
8267         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8268         mode->vdisplay = (vtot & 0xffff) + 1;
8269         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8270         mode->vsync_start = (vsync & 0xffff) + 1;
8271         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8272
8273         drm_mode_set_name(mode);
8274
8275         return mode;
8276 }
8277
8278 static void intel_increase_pllclock(struct drm_crtc *crtc)
8279 {
8280         struct drm_device *dev = crtc->dev;
8281         drm_i915_private_t *dev_priv = dev->dev_private;
8282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8283         int pipe = intel_crtc->pipe;
8284         int dpll_reg = DPLL(pipe);
8285         int dpll;
8286
8287         if (HAS_PCH_SPLIT(dev))
8288                 return;
8289
8290         if (!dev_priv->lvds_downclock_avail)
8291                 return;
8292
8293         dpll = I915_READ(dpll_reg);
8294         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8295                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8296
8297                 assert_panel_unlocked(dev_priv, pipe);
8298
8299                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8300                 I915_WRITE(dpll_reg, dpll);
8301                 intel_wait_for_vblank(dev, pipe);
8302
8303                 dpll = I915_READ(dpll_reg);
8304                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8305                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8306         }
8307 }
8308
8309 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8310 {
8311         struct drm_device *dev = crtc->dev;
8312         drm_i915_private_t *dev_priv = dev->dev_private;
8313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8314
8315         if (HAS_PCH_SPLIT(dev))
8316                 return;
8317
8318         if (!dev_priv->lvds_downclock_avail)
8319                 return;
8320
8321         /*
8322          * Since this is called by a timer, we should never get here in
8323          * the manual case.
8324          */
8325         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8326                 int pipe = intel_crtc->pipe;
8327                 int dpll_reg = DPLL(pipe);
8328                 int dpll;
8329
8330                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8331
8332                 assert_panel_unlocked(dev_priv, pipe);
8333
8334                 dpll = I915_READ(dpll_reg);
8335                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8336                 I915_WRITE(dpll_reg, dpll);
8337                 intel_wait_for_vblank(dev, pipe);
8338                 dpll = I915_READ(dpll_reg);
8339                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8340                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8341         }
8342
8343 }
8344
8345 void intel_mark_busy(struct drm_device *dev)
8346 {
8347         struct drm_i915_private *dev_priv = dev->dev_private;
8348
8349         if (dev_priv->mm.busy)
8350                 return;
8351
8352         hsw_disable_package_c8(dev_priv);
8353         i915_update_gfx_val(dev_priv);
8354         dev_priv->mm.busy = true;
8355 }
8356
8357 void intel_mark_idle(struct drm_device *dev)
8358 {
8359         struct drm_i915_private *dev_priv = dev->dev_private;
8360         struct drm_crtc *crtc;
8361
8362         if (!dev_priv->mm.busy)
8363                 return;
8364
8365         dev_priv->mm.busy = false;
8366
8367         if (!i915.powersave)
8368                 goto out;
8369
8370         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8371                 if (!crtc->fb)
8372                         continue;
8373
8374                 intel_decrease_pllclock(crtc);
8375         }
8376
8377         if (INTEL_INFO(dev)->gen >= 6)
8378                 gen6_rps_idle(dev->dev_private);
8379
8380 out:
8381         hsw_enable_package_c8(dev_priv);
8382 }
8383
8384 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8385                         struct intel_ring_buffer *ring)
8386 {
8387         struct drm_device *dev = obj->base.dev;
8388         struct drm_crtc *crtc;
8389
8390         if (!i915.powersave)
8391                 return;
8392
8393         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8394                 if (!crtc->fb)
8395                         continue;
8396
8397                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8398                         continue;
8399
8400                 intel_increase_pllclock(crtc);
8401                 if (ring && intel_fbc_enabled(dev))
8402                         ring->fbc_dirty = true;
8403         }
8404 }
8405
8406 static void intel_crtc_destroy(struct drm_crtc *crtc)
8407 {
8408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8409         struct drm_device *dev = crtc->dev;
8410         struct intel_unpin_work *work;
8411         unsigned long flags;
8412
8413         spin_lock_irqsave(&dev->event_lock, flags);
8414         work = intel_crtc->unpin_work;
8415         intel_crtc->unpin_work = NULL;
8416         spin_unlock_irqrestore(&dev->event_lock, flags);
8417
8418         if (work) {
8419                 cancel_work_sync(&work->work);
8420                 kfree(work);
8421         }
8422
8423         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8424
8425         drm_crtc_cleanup(crtc);
8426
8427         kfree(intel_crtc);
8428 }
8429
8430 static void intel_unpin_work_fn(struct work_struct *__work)
8431 {
8432         struct intel_unpin_work *work =
8433                 container_of(__work, struct intel_unpin_work, work);
8434         struct drm_device *dev = work->crtc->dev;
8435
8436         mutex_lock(&dev->struct_mutex);
8437         intel_unpin_fb_obj(work->old_fb_obj);
8438         drm_gem_object_unreference(&work->pending_flip_obj->base);
8439         drm_gem_object_unreference(&work->old_fb_obj->base);
8440
8441         intel_update_fbc(dev);
8442         mutex_unlock(&dev->struct_mutex);
8443
8444         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8445         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8446
8447         kfree(work);
8448 }
8449
8450 static void do_intel_finish_page_flip(struct drm_device *dev,
8451                                       struct drm_crtc *crtc)
8452 {
8453         drm_i915_private_t *dev_priv = dev->dev_private;
8454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8455         struct intel_unpin_work *work;
8456         unsigned long flags;
8457
8458         /* Ignore early vblank irqs */
8459         if (intel_crtc == NULL)
8460                 return;
8461
8462         spin_lock_irqsave(&dev->event_lock, flags);
8463         work = intel_crtc->unpin_work;
8464
8465         /* Ensure we don't miss a work->pending update ... */
8466         smp_rmb();
8467
8468         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8469                 spin_unlock_irqrestore(&dev->event_lock, flags);
8470                 return;
8471         }
8472
8473         /* and that the unpin work is consistent wrt ->pending. */
8474         smp_rmb();
8475
8476         intel_crtc->unpin_work = NULL;
8477
8478         if (work->event)
8479                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8480
8481         drm_vblank_put(dev, intel_crtc->pipe);
8482
8483         spin_unlock_irqrestore(&dev->event_lock, flags);
8484
8485         wake_up_all(&dev_priv->pending_flip_queue);
8486
8487         queue_work(dev_priv->wq, &work->work);
8488
8489         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8490 }
8491
8492 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8493 {
8494         drm_i915_private_t *dev_priv = dev->dev_private;
8495         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8496
8497         do_intel_finish_page_flip(dev, crtc);
8498 }
8499
8500 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8501 {
8502         drm_i915_private_t *dev_priv = dev->dev_private;
8503         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8504
8505         do_intel_finish_page_flip(dev, crtc);
8506 }
8507
8508 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8509 {
8510         drm_i915_private_t *dev_priv = dev->dev_private;
8511         struct intel_crtc *intel_crtc =
8512                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8513         unsigned long flags;
8514
8515         /* NB: An MMIO update of the plane base pointer will also
8516          * generate a page-flip completion irq, i.e. every modeset
8517          * is also accompanied by a spurious intel_prepare_page_flip().
8518          */
8519         spin_lock_irqsave(&dev->event_lock, flags);
8520         if (intel_crtc->unpin_work)
8521                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8522         spin_unlock_irqrestore(&dev->event_lock, flags);
8523 }
8524
8525 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8526 {
8527         /* Ensure that the work item is consistent when activating it ... */
8528         smp_wmb();
8529         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8530         /* and that it is marked active as soon as the irq could fire. */
8531         smp_wmb();
8532 }
8533
8534 static int intel_gen2_queue_flip(struct drm_device *dev,
8535                                  struct drm_crtc *crtc,
8536                                  struct drm_framebuffer *fb,
8537                                  struct drm_i915_gem_object *obj,
8538                                  uint32_t flags)
8539 {
8540         struct drm_i915_private *dev_priv = dev->dev_private;
8541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8542         u32 flip_mask;
8543         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8544         int ret;
8545
8546         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8547         if (ret)
8548                 goto err;
8549
8550         ret = intel_ring_begin(ring, 6);
8551         if (ret)
8552                 goto err_unpin;
8553
8554         /* Can't queue multiple flips, so wait for the previous
8555          * one to finish before executing the next.
8556          */
8557         if (intel_crtc->plane)
8558                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8559         else
8560                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8561         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8562         intel_ring_emit(ring, MI_NOOP);
8563         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8564                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8565         intel_ring_emit(ring, fb->pitches[0]);
8566         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8567         intel_ring_emit(ring, 0); /* aux display base address, unused */
8568
8569         intel_mark_page_flip_active(intel_crtc);
8570         __intel_ring_advance(ring);
8571         return 0;
8572
8573 err_unpin:
8574         intel_unpin_fb_obj(obj);
8575 err:
8576         return ret;
8577 }
8578
8579 static int intel_gen3_queue_flip(struct drm_device *dev,
8580                                  struct drm_crtc *crtc,
8581                                  struct drm_framebuffer *fb,
8582                                  struct drm_i915_gem_object *obj,
8583                                  uint32_t flags)
8584 {
8585         struct drm_i915_private *dev_priv = dev->dev_private;
8586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8587         u32 flip_mask;
8588         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8589         int ret;
8590
8591         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8592         if (ret)
8593                 goto err;
8594
8595         ret = intel_ring_begin(ring, 6);
8596         if (ret)
8597                 goto err_unpin;
8598
8599         if (intel_crtc->plane)
8600                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8601         else
8602                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8603         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8604         intel_ring_emit(ring, MI_NOOP);
8605         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8606                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8607         intel_ring_emit(ring, fb->pitches[0]);
8608         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8609         intel_ring_emit(ring, MI_NOOP);
8610
8611         intel_mark_page_flip_active(intel_crtc);
8612         __intel_ring_advance(ring);
8613         return 0;
8614
8615 err_unpin:
8616         intel_unpin_fb_obj(obj);
8617 err:
8618         return ret;
8619 }
8620
8621 static int intel_gen4_queue_flip(struct drm_device *dev,
8622                                  struct drm_crtc *crtc,
8623                                  struct drm_framebuffer *fb,
8624                                  struct drm_i915_gem_object *obj,
8625                                  uint32_t flags)
8626 {
8627         struct drm_i915_private *dev_priv = dev->dev_private;
8628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629         uint32_t pf, pipesrc;
8630         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8631         int ret;
8632
8633         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8634         if (ret)
8635                 goto err;
8636
8637         ret = intel_ring_begin(ring, 4);
8638         if (ret)
8639                 goto err_unpin;
8640
8641         /* i965+ uses the linear or tiled offsets from the
8642          * Display Registers (which do not change across a page-flip)
8643          * so we need only reprogram the base address.
8644          */
8645         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8646                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8647         intel_ring_emit(ring, fb->pitches[0]);
8648         intel_ring_emit(ring,
8649                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8650                         obj->tiling_mode);
8651
8652         /* XXX Enabling the panel-fitter across page-flip is so far
8653          * untested on non-native modes, so ignore it for now.
8654          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8655          */
8656         pf = 0;
8657         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8658         intel_ring_emit(ring, pf | pipesrc);
8659
8660         intel_mark_page_flip_active(intel_crtc);
8661         __intel_ring_advance(ring);
8662         return 0;
8663
8664 err_unpin:
8665         intel_unpin_fb_obj(obj);
8666 err:
8667         return ret;
8668 }
8669
8670 static int intel_gen6_queue_flip(struct drm_device *dev,
8671                                  struct drm_crtc *crtc,
8672                                  struct drm_framebuffer *fb,
8673                                  struct drm_i915_gem_object *obj,
8674                                  uint32_t flags)
8675 {
8676         struct drm_i915_private *dev_priv = dev->dev_private;
8677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8678         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8679         uint32_t pf, pipesrc;
8680         int ret;
8681
8682         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8683         if (ret)
8684                 goto err;
8685
8686         ret = intel_ring_begin(ring, 4);
8687         if (ret)
8688                 goto err_unpin;
8689
8690         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8691                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8692         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8693         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8694
8695         /* Contrary to the suggestions in the documentation,
8696          * "Enable Panel Fitter" does not seem to be required when page
8697          * flipping with a non-native mode, and worse causes a normal
8698          * modeset to fail.
8699          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8700          */
8701         pf = 0;
8702         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8703         intel_ring_emit(ring, pf | pipesrc);
8704
8705         intel_mark_page_flip_active(intel_crtc);
8706         __intel_ring_advance(ring);
8707         return 0;
8708
8709 err_unpin:
8710         intel_unpin_fb_obj(obj);
8711 err:
8712         return ret;
8713 }
8714
8715 static int intel_gen7_queue_flip(struct drm_device *dev,
8716                                  struct drm_crtc *crtc,
8717                                  struct drm_framebuffer *fb,
8718                                  struct drm_i915_gem_object *obj,
8719                                  uint32_t flags)
8720 {
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8723         struct intel_ring_buffer *ring;
8724         uint32_t plane_bit = 0;
8725         int len, ret;
8726
8727         ring = obj->ring;
8728         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8729                 ring = &dev_priv->ring[BCS];
8730
8731         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8732         if (ret)
8733                 goto err;
8734
8735         switch(intel_crtc->plane) {
8736         case PLANE_A:
8737                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8738                 break;
8739         case PLANE_B:
8740                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8741                 break;
8742         case PLANE_C:
8743                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8744                 break;
8745         default:
8746                 WARN_ONCE(1, "unknown plane in flip command\n");
8747                 ret = -ENODEV;
8748                 goto err_unpin;
8749         }
8750
8751         len = 4;
8752         if (ring->id == RCS)
8753                 len += 6;
8754
8755         ret = intel_ring_begin(ring, len);
8756         if (ret)
8757                 goto err_unpin;
8758
8759         /* Unmask the flip-done completion message. Note that the bspec says that
8760          * we should do this for both the BCS and RCS, and that we must not unmask
8761          * more than one flip event at any time (or ensure that one flip message
8762          * can be sent by waiting for flip-done prior to queueing new flips).
8763          * Experimentation says that BCS works despite DERRMR masking all
8764          * flip-done completion events and that unmasking all planes at once
8765          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8766          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8767          */
8768         if (ring->id == RCS) {
8769                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8770                 intel_ring_emit(ring, DERRMR);
8771                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8772                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8773                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8774                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8775                                 MI_SRM_LRM_GLOBAL_GTT);
8776                 intel_ring_emit(ring, DERRMR);
8777                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8778         }
8779
8780         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8781         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8782         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8783         intel_ring_emit(ring, (MI_NOOP));
8784
8785         intel_mark_page_flip_active(intel_crtc);
8786         __intel_ring_advance(ring);
8787         return 0;
8788
8789 err_unpin:
8790         intel_unpin_fb_obj(obj);
8791 err:
8792         return ret;
8793 }
8794
8795 static int intel_default_queue_flip(struct drm_device *dev,
8796                                     struct drm_crtc *crtc,
8797                                     struct drm_framebuffer *fb,
8798                                     struct drm_i915_gem_object *obj,
8799                                     uint32_t flags)
8800 {
8801         return -ENODEV;
8802 }
8803
8804 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8805                                 struct drm_framebuffer *fb,
8806                                 struct drm_pending_vblank_event *event,
8807                                 uint32_t page_flip_flags)
8808 {
8809         struct drm_device *dev = crtc->dev;
8810         struct drm_i915_private *dev_priv = dev->dev_private;
8811         struct drm_framebuffer *old_fb = crtc->fb;
8812         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8814         struct intel_unpin_work *work;
8815         unsigned long flags;
8816         int ret;
8817
8818         /* Can't change pixel format via MI display flips. */
8819         if (fb->pixel_format != crtc->fb->pixel_format)
8820                 return -EINVAL;
8821
8822         /*
8823          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8824          * Note that pitch changes could also affect these register.
8825          */
8826         if (INTEL_INFO(dev)->gen > 3 &&
8827             (fb->offsets[0] != crtc->fb->offsets[0] ||
8828              fb->pitches[0] != crtc->fb->pitches[0]))
8829                 return -EINVAL;
8830
8831         if (i915_terminally_wedged(&dev_priv->gpu_error))
8832                 goto out_hang;
8833
8834         work = kzalloc(sizeof(*work), GFP_KERNEL);
8835         if (work == NULL)
8836                 return -ENOMEM;
8837
8838         work->event = event;
8839         work->crtc = crtc;
8840         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8841         INIT_WORK(&work->work, intel_unpin_work_fn);
8842
8843         ret = drm_vblank_get(dev, intel_crtc->pipe);
8844         if (ret)
8845                 goto free_work;
8846
8847         /* We borrow the event spin lock for protecting unpin_work */
8848         spin_lock_irqsave(&dev->event_lock, flags);
8849         if (intel_crtc->unpin_work) {
8850                 spin_unlock_irqrestore(&dev->event_lock, flags);
8851                 kfree(work);
8852                 drm_vblank_put(dev, intel_crtc->pipe);
8853
8854                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8855                 return -EBUSY;
8856         }
8857         intel_crtc->unpin_work = work;
8858         spin_unlock_irqrestore(&dev->event_lock, flags);
8859
8860         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8861                 flush_workqueue(dev_priv->wq);
8862
8863         ret = i915_mutex_lock_interruptible(dev);
8864         if (ret)
8865                 goto cleanup;
8866
8867         /* Reference the objects for the scheduled work. */
8868         drm_gem_object_reference(&work->old_fb_obj->base);
8869         drm_gem_object_reference(&obj->base);
8870
8871         crtc->fb = fb;
8872
8873         work->pending_flip_obj = obj;
8874
8875         work->enable_stall_check = true;
8876
8877         atomic_inc(&intel_crtc->unpin_work_count);
8878         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8879
8880         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8881         if (ret)
8882                 goto cleanup_pending;
8883
8884         intel_disable_fbc(dev);
8885         intel_mark_fb_busy(obj, NULL);
8886         mutex_unlock(&dev->struct_mutex);
8887
8888         trace_i915_flip_request(intel_crtc->plane, obj);
8889
8890         return 0;
8891
8892 cleanup_pending:
8893         atomic_dec(&intel_crtc->unpin_work_count);
8894         crtc->fb = old_fb;
8895         drm_gem_object_unreference(&work->old_fb_obj->base);
8896         drm_gem_object_unreference(&obj->base);
8897         mutex_unlock(&dev->struct_mutex);
8898
8899 cleanup:
8900         spin_lock_irqsave(&dev->event_lock, flags);
8901         intel_crtc->unpin_work = NULL;
8902         spin_unlock_irqrestore(&dev->event_lock, flags);
8903
8904         drm_vblank_put(dev, intel_crtc->pipe);
8905 free_work:
8906         kfree(work);
8907
8908         if (ret == -EIO) {
8909 out_hang:
8910                 intel_crtc_wait_for_pending_flips(crtc);
8911                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8912                 if (ret == 0 && event)
8913                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8914         }
8915         return ret;
8916 }
8917
8918 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8919         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8920         .load_lut = intel_crtc_load_lut,
8921 };
8922
8923 /**
8924  * intel_modeset_update_staged_output_state
8925  *
8926  * Updates the staged output configuration state, e.g. after we've read out the
8927  * current hw state.
8928  */
8929 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8930 {
8931         struct intel_crtc *crtc;
8932         struct intel_encoder *encoder;
8933         struct intel_connector *connector;
8934
8935         list_for_each_entry(connector, &dev->mode_config.connector_list,
8936                             base.head) {
8937                 connector->new_encoder =
8938                         to_intel_encoder(connector->base.encoder);
8939         }
8940
8941         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8942                             base.head) {
8943                 encoder->new_crtc =
8944                         to_intel_crtc(encoder->base.crtc);
8945         }
8946
8947         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8948                             base.head) {
8949                 crtc->new_enabled = crtc->base.enabled;
8950
8951                 if (crtc->new_enabled)
8952                         crtc->new_config = &crtc->config;
8953                 else
8954                         crtc->new_config = NULL;
8955         }
8956 }
8957
8958 /**
8959  * intel_modeset_commit_output_state
8960  *
8961  * This function copies the stage display pipe configuration to the real one.
8962  */
8963 static void intel_modeset_commit_output_state(struct drm_device *dev)
8964 {
8965         struct intel_crtc *crtc;
8966         struct intel_encoder *encoder;
8967         struct intel_connector *connector;
8968
8969         list_for_each_entry(connector, &dev->mode_config.connector_list,
8970                             base.head) {
8971                 connector->base.encoder = &connector->new_encoder->base;
8972         }
8973
8974         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8975                             base.head) {
8976                 encoder->base.crtc = &encoder->new_crtc->base;
8977         }
8978
8979         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8980                             base.head) {
8981                 crtc->base.enabled = crtc->new_enabled;
8982         }
8983 }
8984
8985 static void
8986 connected_sink_compute_bpp(struct intel_connector * connector,
8987                            struct intel_crtc_config *pipe_config)
8988 {
8989         int bpp = pipe_config->pipe_bpp;
8990
8991         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8992                 connector->base.base.id,
8993                 drm_get_connector_name(&connector->base));
8994
8995         /* Don't use an invalid EDID bpc value */
8996         if (connector->base.display_info.bpc &&
8997             connector->base.display_info.bpc * 3 < bpp) {
8998                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8999                               bpp, connector->base.display_info.bpc*3);
9000                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9001         }
9002
9003         /* Clamp bpp to 8 on screens without EDID 1.4 */
9004         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9005                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9006                               bpp);
9007                 pipe_config->pipe_bpp = 24;
9008         }
9009 }
9010
9011 static int
9012 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9013                           struct drm_framebuffer *fb,
9014                           struct intel_crtc_config *pipe_config)
9015 {
9016         struct drm_device *dev = crtc->base.dev;
9017         struct intel_connector *connector;
9018         int bpp;
9019
9020         switch (fb->pixel_format) {
9021         case DRM_FORMAT_C8:
9022                 bpp = 8*3; /* since we go through a colormap */
9023                 break;
9024         case DRM_FORMAT_XRGB1555:
9025         case DRM_FORMAT_ARGB1555:
9026                 /* checked in intel_framebuffer_init already */
9027                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9028                         return -EINVAL;
9029         case DRM_FORMAT_RGB565:
9030                 bpp = 6*3; /* min is 18bpp */
9031                 break;
9032         case DRM_FORMAT_XBGR8888:
9033         case DRM_FORMAT_ABGR8888:
9034                 /* checked in intel_framebuffer_init already */
9035                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9036                         return -EINVAL;
9037         case DRM_FORMAT_XRGB8888:
9038         case DRM_FORMAT_ARGB8888:
9039                 bpp = 8*3;
9040                 break;
9041         case DRM_FORMAT_XRGB2101010:
9042         case DRM_FORMAT_ARGB2101010:
9043         case DRM_FORMAT_XBGR2101010:
9044         case DRM_FORMAT_ABGR2101010:
9045                 /* checked in intel_framebuffer_init already */
9046                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9047                         return -EINVAL;
9048                 bpp = 10*3;
9049                 break;
9050         /* TODO: gen4+ supports 16 bpc floating point, too. */
9051         default:
9052                 DRM_DEBUG_KMS("unsupported depth\n");
9053                 return -EINVAL;
9054         }
9055
9056         pipe_config->pipe_bpp = bpp;
9057
9058         /* Clamp display bpp to EDID value */
9059         list_for_each_entry(connector, &dev->mode_config.connector_list,
9060                             base.head) {
9061                 if (!connector->new_encoder ||
9062                     connector->new_encoder->new_crtc != crtc)
9063                         continue;
9064
9065                 connected_sink_compute_bpp(connector, pipe_config);
9066         }
9067
9068         return bpp;
9069 }
9070
9071 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9072 {
9073         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9074                         "type: 0x%x flags: 0x%x\n",
9075                 mode->crtc_clock,
9076                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9077                 mode->crtc_hsync_end, mode->crtc_htotal,
9078                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9079                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9080 }
9081
9082 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9083                                    struct intel_crtc_config *pipe_config,
9084                                    const char *context)
9085 {
9086         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9087                       context, pipe_name(crtc->pipe));
9088
9089         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9090         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9091                       pipe_config->pipe_bpp, pipe_config->dither);
9092         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9093                       pipe_config->has_pch_encoder,
9094                       pipe_config->fdi_lanes,
9095                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9096                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9097                       pipe_config->fdi_m_n.tu);
9098         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9099                       pipe_config->has_dp_encoder,
9100                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9101                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9102                       pipe_config->dp_m_n.tu);
9103         DRM_DEBUG_KMS("requested mode:\n");
9104         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9105         DRM_DEBUG_KMS("adjusted mode:\n");
9106         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9107         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9108         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9109         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9110                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9111         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9112                       pipe_config->gmch_pfit.control,
9113                       pipe_config->gmch_pfit.pgm_ratios,
9114                       pipe_config->gmch_pfit.lvds_border_bits);
9115         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9116                       pipe_config->pch_pfit.pos,
9117                       pipe_config->pch_pfit.size,
9118                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9119         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9120         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9121 }
9122
9123 static bool check_encoder_cloning(struct drm_crtc *crtc)
9124 {
9125         int num_encoders = 0;
9126         bool uncloneable_encoders = false;
9127         struct intel_encoder *encoder;
9128
9129         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
9130                             base.head) {
9131                 if (&encoder->new_crtc->base != crtc)
9132                         continue;
9133
9134                 num_encoders++;
9135                 if (!encoder->cloneable)
9136                         uncloneable_encoders = true;
9137         }
9138
9139         return !(num_encoders > 1 && uncloneable_encoders);
9140 }
9141
9142 static struct intel_crtc_config *
9143 intel_modeset_pipe_config(struct drm_crtc *crtc,
9144                           struct drm_framebuffer *fb,
9145                           struct drm_display_mode *mode)
9146 {
9147         struct drm_device *dev = crtc->dev;
9148         struct intel_encoder *encoder;
9149         struct intel_crtc_config *pipe_config;
9150         int plane_bpp, ret = -EINVAL;
9151         bool retry = true;
9152
9153         if (!check_encoder_cloning(crtc)) {
9154                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9155                 return ERR_PTR(-EINVAL);
9156         }
9157
9158         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9159         if (!pipe_config)
9160                 return ERR_PTR(-ENOMEM);
9161
9162         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9163         drm_mode_copy(&pipe_config->requested_mode, mode);
9164
9165         pipe_config->cpu_transcoder =
9166                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9167         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9168
9169         /*
9170          * Sanitize sync polarity flags based on requested ones. If neither
9171          * positive or negative polarity is requested, treat this as meaning
9172          * negative polarity.
9173          */
9174         if (!(pipe_config->adjusted_mode.flags &
9175               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9176                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9177
9178         if (!(pipe_config->adjusted_mode.flags &
9179               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9180                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9181
9182         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9183          * plane pixel format and any sink constraints into account. Returns the
9184          * source plane bpp so that dithering can be selected on mismatches
9185          * after encoders and crtc also have had their say. */
9186         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9187                                               fb, pipe_config);
9188         if (plane_bpp < 0)
9189                 goto fail;
9190
9191         /*
9192          * Determine the real pipe dimensions. Note that stereo modes can
9193          * increase the actual pipe size due to the frame doubling and
9194          * insertion of additional space for blanks between the frame. This
9195          * is stored in the crtc timings. We use the requested mode to do this
9196          * computation to clearly distinguish it from the adjusted mode, which
9197          * can be changed by the connectors in the below retry loop.
9198          */
9199         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9200         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9201         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9202
9203 encoder_retry:
9204         /* Ensure the port clock defaults are reset when retrying. */
9205         pipe_config->port_clock = 0;
9206         pipe_config->pixel_multiplier = 1;
9207
9208         /* Fill in default crtc timings, allow encoders to overwrite them. */
9209         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9210
9211         /* Pass our mode to the connectors and the CRTC to give them a chance to
9212          * adjust it according to limitations or connector properties, and also
9213          * a chance to reject the mode entirely.
9214          */
9215         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9216                             base.head) {
9217
9218                 if (&encoder->new_crtc->base != crtc)
9219                         continue;
9220
9221                 if (!(encoder->compute_config(encoder, pipe_config))) {
9222                         DRM_DEBUG_KMS("Encoder config failure\n");
9223                         goto fail;
9224                 }
9225         }
9226
9227         /* Set default port clock if not overwritten by the encoder. Needs to be
9228          * done afterwards in case the encoder adjusts the mode. */
9229         if (!pipe_config->port_clock)
9230                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9231                         * pipe_config->pixel_multiplier;
9232
9233         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9234         if (ret < 0) {
9235                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9236                 goto fail;
9237         }
9238
9239         if (ret == RETRY) {
9240                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9241                         ret = -EINVAL;
9242                         goto fail;
9243                 }
9244
9245                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9246                 retry = false;
9247                 goto encoder_retry;
9248         }
9249
9250         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9251         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9252                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9253
9254         return pipe_config;
9255 fail:
9256         kfree(pipe_config);
9257         return ERR_PTR(ret);
9258 }
9259
9260 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9261  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9262 static void
9263 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9264                              unsigned *prepare_pipes, unsigned *disable_pipes)
9265 {
9266         struct intel_crtc *intel_crtc;
9267         struct drm_device *dev = crtc->dev;
9268         struct intel_encoder *encoder;
9269         struct intel_connector *connector;
9270         struct drm_crtc *tmp_crtc;
9271
9272         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9273
9274         /* Check which crtcs have changed outputs connected to them, these need
9275          * to be part of the prepare_pipes mask. We don't (yet) support global
9276          * modeset across multiple crtcs, so modeset_pipes will only have one
9277          * bit set at most. */
9278         list_for_each_entry(connector, &dev->mode_config.connector_list,
9279                             base.head) {
9280                 if (connector->base.encoder == &connector->new_encoder->base)
9281                         continue;
9282
9283                 if (connector->base.encoder) {
9284                         tmp_crtc = connector->base.encoder->crtc;
9285
9286                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9287                 }
9288
9289                 if (connector->new_encoder)
9290                         *prepare_pipes |=
9291                                 1 << connector->new_encoder->new_crtc->pipe;
9292         }
9293
9294         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9295                             base.head) {
9296                 if (encoder->base.crtc == &encoder->new_crtc->base)
9297                         continue;
9298
9299                 if (encoder->base.crtc) {
9300                         tmp_crtc = encoder->base.crtc;
9301
9302                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9303                 }
9304
9305                 if (encoder->new_crtc)
9306                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9307         }
9308
9309         /* Check for pipes that will be enabled/disabled ... */
9310         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9311                             base.head) {
9312                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9313                         continue;
9314
9315                 if (!intel_crtc->new_enabled)
9316                         *disable_pipes |= 1 << intel_crtc->pipe;
9317                 else
9318                         *prepare_pipes |= 1 << intel_crtc->pipe;
9319         }
9320
9321
9322         /* set_mode is also used to update properties on life display pipes. */
9323         intel_crtc = to_intel_crtc(crtc);
9324         if (intel_crtc->new_enabled)
9325                 *prepare_pipes |= 1 << intel_crtc->pipe;
9326
9327         /*
9328          * For simplicity do a full modeset on any pipe where the output routing
9329          * changed. We could be more clever, but that would require us to be
9330          * more careful with calling the relevant encoder->mode_set functions.
9331          */
9332         if (*prepare_pipes)
9333                 *modeset_pipes = *prepare_pipes;
9334
9335         /* ... and mask these out. */
9336         *modeset_pipes &= ~(*disable_pipes);
9337         *prepare_pipes &= ~(*disable_pipes);
9338
9339         /*
9340          * HACK: We don't (yet) fully support global modesets. intel_set_config
9341          * obies this rule, but the modeset restore mode of
9342          * intel_modeset_setup_hw_state does not.
9343          */
9344         *modeset_pipes &= 1 << intel_crtc->pipe;
9345         *prepare_pipes &= 1 << intel_crtc->pipe;
9346
9347         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9348                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9349 }
9350
9351 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9352 {
9353         struct drm_encoder *encoder;
9354         struct drm_device *dev = crtc->dev;
9355
9356         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9357                 if (encoder->crtc == crtc)
9358                         return true;
9359
9360         return false;
9361 }
9362
9363 static void
9364 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9365 {
9366         struct intel_encoder *intel_encoder;
9367         struct intel_crtc *intel_crtc;
9368         struct drm_connector *connector;
9369
9370         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9371                             base.head) {
9372                 if (!intel_encoder->base.crtc)
9373                         continue;
9374
9375                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9376
9377                 if (prepare_pipes & (1 << intel_crtc->pipe))
9378                         intel_encoder->connectors_active = false;
9379         }
9380
9381         intel_modeset_commit_output_state(dev);
9382
9383         /* Double check state. */
9384         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9385                             base.head) {
9386                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9387                 WARN_ON(intel_crtc->new_config &&
9388                         intel_crtc->new_config != &intel_crtc->config);
9389                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9390         }
9391
9392         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9393                 if (!connector->encoder || !connector->encoder->crtc)
9394                         continue;
9395
9396                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9397
9398                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9399                         struct drm_property *dpms_property =
9400                                 dev->mode_config.dpms_property;
9401
9402                         connector->dpms = DRM_MODE_DPMS_ON;
9403                         drm_object_property_set_value(&connector->base,
9404                                                          dpms_property,
9405                                                          DRM_MODE_DPMS_ON);
9406
9407                         intel_encoder = to_intel_encoder(connector->encoder);
9408                         intel_encoder->connectors_active = true;
9409                 }
9410         }
9411
9412 }
9413
9414 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9415 {
9416         int diff;
9417
9418         if (clock1 == clock2)
9419                 return true;
9420
9421         if (!clock1 || !clock2)
9422                 return false;
9423
9424         diff = abs(clock1 - clock2);
9425
9426         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9427                 return true;
9428
9429         return false;
9430 }
9431
9432 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9433         list_for_each_entry((intel_crtc), \
9434                             &(dev)->mode_config.crtc_list, \
9435                             base.head) \
9436                 if (mask & (1 <<(intel_crtc)->pipe))
9437
9438 static bool
9439 intel_pipe_config_compare(struct drm_device *dev,
9440                           struct intel_crtc_config *current_config,
9441                           struct intel_crtc_config *pipe_config)
9442 {
9443 #define PIPE_CONF_CHECK_X(name) \
9444         if (current_config->name != pipe_config->name) { \
9445                 DRM_ERROR("mismatch in " #name " " \
9446                           "(expected 0x%08x, found 0x%08x)\n", \
9447                           current_config->name, \
9448                           pipe_config->name); \
9449                 return false; \
9450         }
9451
9452 #define PIPE_CONF_CHECK_I(name) \
9453         if (current_config->name != pipe_config->name) { \
9454                 DRM_ERROR("mismatch in " #name " " \
9455                           "(expected %i, found %i)\n", \
9456                           current_config->name, \
9457                           pipe_config->name); \
9458                 return false; \
9459         }
9460
9461 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9462         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9463                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9464                           "(expected %i, found %i)\n", \
9465                           current_config->name & (mask), \
9466                           pipe_config->name & (mask)); \
9467                 return false; \
9468         }
9469
9470 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9471         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9472                 DRM_ERROR("mismatch in " #name " " \
9473                           "(expected %i, found %i)\n", \
9474                           current_config->name, \
9475                           pipe_config->name); \
9476                 return false; \
9477         }
9478
9479 #define PIPE_CONF_QUIRK(quirk)  \
9480         ((current_config->quirks | pipe_config->quirks) & (quirk))
9481
9482         PIPE_CONF_CHECK_I(cpu_transcoder);
9483
9484         PIPE_CONF_CHECK_I(has_pch_encoder);
9485         PIPE_CONF_CHECK_I(fdi_lanes);
9486         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9487         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9488         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9489         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9490         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9491
9492         PIPE_CONF_CHECK_I(has_dp_encoder);
9493         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9494         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9495         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9496         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9497         PIPE_CONF_CHECK_I(dp_m_n.tu);
9498
9499         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9500         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9501         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9502         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9503         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9504         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9505
9506         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9507         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9508         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9509         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9510         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9511         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9512
9513         PIPE_CONF_CHECK_I(pixel_multiplier);
9514
9515         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9516                               DRM_MODE_FLAG_INTERLACE);
9517
9518         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9519                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9520                                       DRM_MODE_FLAG_PHSYNC);
9521                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9522                                       DRM_MODE_FLAG_NHSYNC);
9523                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9524                                       DRM_MODE_FLAG_PVSYNC);
9525                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9526                                       DRM_MODE_FLAG_NVSYNC);
9527         }
9528
9529         PIPE_CONF_CHECK_I(pipe_src_w);
9530         PIPE_CONF_CHECK_I(pipe_src_h);
9531
9532         PIPE_CONF_CHECK_I(gmch_pfit.control);
9533         /* pfit ratios are autocomputed by the hw on gen4+ */
9534         if (INTEL_INFO(dev)->gen < 4)
9535                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9536         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9537         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9538         if (current_config->pch_pfit.enabled) {
9539                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9540                 PIPE_CONF_CHECK_I(pch_pfit.size);
9541         }
9542
9543         /* BDW+ don't expose a synchronous way to read the state */
9544         if (IS_HASWELL(dev))
9545                 PIPE_CONF_CHECK_I(ips_enabled);
9546
9547         PIPE_CONF_CHECK_I(double_wide);
9548
9549         PIPE_CONF_CHECK_I(shared_dpll);
9550         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9551         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9552         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9553         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9554
9555         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9556                 PIPE_CONF_CHECK_I(pipe_bpp);
9557
9558         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9559         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9560
9561 #undef PIPE_CONF_CHECK_X
9562 #undef PIPE_CONF_CHECK_I
9563 #undef PIPE_CONF_CHECK_FLAGS
9564 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9565 #undef PIPE_CONF_QUIRK
9566
9567         return true;
9568 }
9569
9570 static void
9571 check_connector_state(struct drm_device *dev)
9572 {
9573         struct intel_connector *connector;
9574
9575         list_for_each_entry(connector, &dev->mode_config.connector_list,
9576                             base.head) {
9577                 /* This also checks the encoder/connector hw state with the
9578                  * ->get_hw_state callbacks. */
9579                 intel_connector_check_state(connector);
9580
9581                 WARN(&connector->new_encoder->base != connector->base.encoder,
9582                      "connector's staged encoder doesn't match current encoder\n");
9583         }
9584 }
9585
9586 static void
9587 check_encoder_state(struct drm_device *dev)
9588 {
9589         struct intel_encoder *encoder;
9590         struct intel_connector *connector;
9591
9592         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9593                             base.head) {
9594                 bool enabled = false;
9595                 bool active = false;
9596                 enum pipe pipe, tracked_pipe;
9597
9598                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9599                               encoder->base.base.id,
9600                               drm_get_encoder_name(&encoder->base));
9601
9602                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9603                      "encoder's stage crtc doesn't match current crtc\n");
9604                 WARN(encoder->connectors_active && !encoder->base.crtc,
9605                      "encoder's active_connectors set, but no crtc\n");
9606
9607                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9608                                     base.head) {
9609                         if (connector->base.encoder != &encoder->base)
9610                                 continue;
9611                         enabled = true;
9612                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9613                                 active = true;
9614                 }
9615                 WARN(!!encoder->base.crtc != enabled,
9616                      "encoder's enabled state mismatch "
9617                      "(expected %i, found %i)\n",
9618                      !!encoder->base.crtc, enabled);
9619                 WARN(active && !encoder->base.crtc,
9620                      "active encoder with no crtc\n");
9621
9622                 WARN(encoder->connectors_active != active,
9623                      "encoder's computed active state doesn't match tracked active state "
9624                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9625
9626                 active = encoder->get_hw_state(encoder, &pipe);
9627                 WARN(active != encoder->connectors_active,
9628                      "encoder's hw state doesn't match sw tracking "
9629                      "(expected %i, found %i)\n",
9630                      encoder->connectors_active, active);
9631
9632                 if (!encoder->base.crtc)
9633                         continue;
9634
9635                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9636                 WARN(active && pipe != tracked_pipe,
9637                      "active encoder's pipe doesn't match"
9638                      "(expected %i, found %i)\n",
9639                      tracked_pipe, pipe);
9640
9641         }
9642 }
9643
9644 static void
9645 check_crtc_state(struct drm_device *dev)
9646 {
9647         drm_i915_private_t *dev_priv = dev->dev_private;
9648         struct intel_crtc *crtc;
9649         struct intel_encoder *encoder;
9650         struct intel_crtc_config pipe_config;
9651
9652         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9653                             base.head) {
9654                 bool enabled = false;
9655                 bool active = false;
9656
9657                 memset(&pipe_config, 0, sizeof(pipe_config));
9658
9659                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9660                               crtc->base.base.id);
9661
9662                 WARN(crtc->active && !crtc->base.enabled,
9663                      "active crtc, but not enabled in sw tracking\n");
9664
9665                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9666                                     base.head) {
9667                         if (encoder->base.crtc != &crtc->base)
9668                                 continue;
9669                         enabled = true;
9670                         if (encoder->connectors_active)
9671                                 active = true;
9672                 }
9673
9674                 WARN(active != crtc->active,
9675                      "crtc's computed active state doesn't match tracked active state "
9676                      "(expected %i, found %i)\n", active, crtc->active);
9677                 WARN(enabled != crtc->base.enabled,
9678                      "crtc's computed enabled state doesn't match tracked enabled state "
9679                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9680
9681                 active = dev_priv->display.get_pipe_config(crtc,
9682                                                            &pipe_config);
9683
9684                 /* hw state is inconsistent with the pipe A quirk */
9685                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9686                         active = crtc->active;
9687
9688                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9689                                     base.head) {
9690                         enum pipe pipe;
9691                         if (encoder->base.crtc != &crtc->base)
9692                                 continue;
9693                         if (encoder->get_hw_state(encoder, &pipe))
9694                                 encoder->get_config(encoder, &pipe_config);
9695                 }
9696
9697                 WARN(crtc->active != active,
9698                      "crtc active state doesn't match with hw state "
9699                      "(expected %i, found %i)\n", crtc->active, active);
9700
9701                 if (active &&
9702                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9703                         WARN(1, "pipe state doesn't match!\n");
9704                         intel_dump_pipe_config(crtc, &pipe_config,
9705                                                "[hw state]");
9706                         intel_dump_pipe_config(crtc, &crtc->config,
9707                                                "[sw state]");
9708                 }
9709         }
9710 }
9711
9712 static void
9713 check_shared_dpll_state(struct drm_device *dev)
9714 {
9715         drm_i915_private_t *dev_priv = dev->dev_private;
9716         struct intel_crtc *crtc;
9717         struct intel_dpll_hw_state dpll_hw_state;
9718         int i;
9719
9720         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9721                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9722                 int enabled_crtcs = 0, active_crtcs = 0;
9723                 bool active;
9724
9725                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9726
9727                 DRM_DEBUG_KMS("%s\n", pll->name);
9728
9729                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9730
9731                 WARN(pll->active > pll->refcount,
9732                      "more active pll users than references: %i vs %i\n",
9733                      pll->active, pll->refcount);
9734                 WARN(pll->active && !pll->on,
9735                      "pll in active use but not on in sw tracking\n");
9736                 WARN(pll->on && !pll->active,
9737                      "pll in on but not on in use in sw tracking\n");
9738                 WARN(pll->on != active,
9739                      "pll on state mismatch (expected %i, found %i)\n",
9740                      pll->on, active);
9741
9742                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9743                                     base.head) {
9744                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9745                                 enabled_crtcs++;
9746                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9747                                 active_crtcs++;
9748                 }
9749                 WARN(pll->active != active_crtcs,
9750                      "pll active crtcs mismatch (expected %i, found %i)\n",
9751                      pll->active, active_crtcs);
9752                 WARN(pll->refcount != enabled_crtcs,
9753                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9754                      pll->refcount, enabled_crtcs);
9755
9756                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9757                                        sizeof(dpll_hw_state)),
9758                      "pll hw state mismatch\n");
9759         }
9760 }
9761
9762 void
9763 intel_modeset_check_state(struct drm_device *dev)
9764 {
9765         check_connector_state(dev);
9766         check_encoder_state(dev);
9767         check_crtc_state(dev);
9768         check_shared_dpll_state(dev);
9769 }
9770
9771 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9772                                      int dotclock)
9773 {
9774         /*
9775          * FDI already provided one idea for the dotclock.
9776          * Yell if the encoder disagrees.
9777          */
9778         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9779              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9780              pipe_config->adjusted_mode.crtc_clock, dotclock);
9781 }
9782
9783 static int __intel_set_mode(struct drm_crtc *crtc,
9784                             struct drm_display_mode *mode,
9785                             int x, int y, struct drm_framebuffer *fb)
9786 {
9787         struct drm_device *dev = crtc->dev;
9788         drm_i915_private_t *dev_priv = dev->dev_private;
9789         struct drm_display_mode *saved_mode;
9790         struct intel_crtc_config *pipe_config = NULL;
9791         struct intel_crtc *intel_crtc;
9792         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9793         int ret = 0;
9794
9795         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9796         if (!saved_mode)
9797                 return -ENOMEM;
9798
9799         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9800                                      &prepare_pipes, &disable_pipes);
9801
9802         *saved_mode = crtc->mode;
9803
9804         /* Hack: Because we don't (yet) support global modeset on multiple
9805          * crtcs, we don't keep track of the new mode for more than one crtc.
9806          * Hence simply check whether any bit is set in modeset_pipes in all the
9807          * pieces of code that are not yet converted to deal with mutliple crtcs
9808          * changing their mode at the same time. */
9809         if (modeset_pipes) {
9810                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9811                 if (IS_ERR(pipe_config)) {
9812                         ret = PTR_ERR(pipe_config);
9813                         pipe_config = NULL;
9814
9815                         goto out;
9816                 }
9817                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9818                                        "[modeset]");
9819                 to_intel_crtc(crtc)->new_config = pipe_config;
9820         }
9821
9822         /*
9823          * See if the config requires any additional preparation, e.g.
9824          * to adjust global state with pipes off.  We need to do this
9825          * here so we can get the modeset_pipe updated config for the new
9826          * mode set on this crtc.  For other crtcs we need to use the
9827          * adjusted_mode bits in the crtc directly.
9828          */
9829         if (IS_VALLEYVIEW(dev)) {
9830                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9831
9832                 /* may have added more to prepare_pipes than we should */
9833                 prepare_pipes &= ~disable_pipes;
9834         }
9835
9836         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9837                 intel_crtc_disable(&intel_crtc->base);
9838
9839         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9840                 if (intel_crtc->base.enabled)
9841                         dev_priv->display.crtc_disable(&intel_crtc->base);
9842         }
9843
9844         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9845          * to set it here already despite that we pass it down the callchain.
9846          */
9847         if (modeset_pipes) {
9848                 crtc->mode = *mode;
9849                 /* mode_set/enable/disable functions rely on a correct pipe
9850                  * config. */
9851                 to_intel_crtc(crtc)->config = *pipe_config;
9852                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9853
9854                 /*
9855                  * Calculate and store various constants which
9856                  * are later needed by vblank and swap-completion
9857                  * timestamping. They are derived from true hwmode.
9858                  */
9859                 drm_calc_timestamping_constants(crtc,
9860                                                 &pipe_config->adjusted_mode);
9861         }
9862
9863         /* Only after disabling all output pipelines that will be changed can we
9864          * update the the output configuration. */
9865         intel_modeset_update_state(dev, prepare_pipes);
9866
9867         if (dev_priv->display.modeset_global_resources)
9868                 dev_priv->display.modeset_global_resources(dev);
9869
9870         /* Set up the DPLL and any encoders state that needs to adjust or depend
9871          * on the DPLL.
9872          */
9873         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9874                 ret = intel_crtc_mode_set(&intel_crtc->base,
9875                                           x, y, fb);
9876                 if (ret)
9877                         goto done;
9878         }
9879
9880         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9881         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9882                 dev_priv->display.crtc_enable(&intel_crtc->base);
9883
9884         /* FIXME: add subpixel order */
9885 done:
9886         if (ret && crtc->enabled)
9887                 crtc->mode = *saved_mode;
9888
9889 out:
9890         kfree(pipe_config);
9891         kfree(saved_mode);
9892         return ret;
9893 }
9894
9895 static int intel_set_mode(struct drm_crtc *crtc,
9896                           struct drm_display_mode *mode,
9897                           int x, int y, struct drm_framebuffer *fb)
9898 {
9899         int ret;
9900
9901         ret = __intel_set_mode(crtc, mode, x, y, fb);
9902
9903         if (ret == 0)
9904                 intel_modeset_check_state(crtc->dev);
9905
9906         return ret;
9907 }
9908
9909 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9910 {
9911         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9912 }
9913
9914 #undef for_each_intel_crtc_masked
9915
9916 static void intel_set_config_free(struct intel_set_config *config)
9917 {
9918         if (!config)
9919                 return;
9920
9921         kfree(config->save_connector_encoders);
9922         kfree(config->save_encoder_crtcs);
9923         kfree(config->save_crtc_enabled);
9924         kfree(config);
9925 }
9926
9927 static int intel_set_config_save_state(struct drm_device *dev,
9928                                        struct intel_set_config *config)
9929 {
9930         struct drm_crtc *crtc;
9931         struct drm_encoder *encoder;
9932         struct drm_connector *connector;
9933         int count;
9934
9935         config->save_crtc_enabled =
9936                 kcalloc(dev->mode_config.num_crtc,
9937                         sizeof(bool), GFP_KERNEL);
9938         if (!config->save_crtc_enabled)
9939                 return -ENOMEM;
9940
9941         config->save_encoder_crtcs =
9942                 kcalloc(dev->mode_config.num_encoder,
9943                         sizeof(struct drm_crtc *), GFP_KERNEL);
9944         if (!config->save_encoder_crtcs)
9945                 return -ENOMEM;
9946
9947         config->save_connector_encoders =
9948                 kcalloc(dev->mode_config.num_connector,
9949                         sizeof(struct drm_encoder *), GFP_KERNEL);
9950         if (!config->save_connector_encoders)
9951                 return -ENOMEM;
9952
9953         /* Copy data. Note that driver private data is not affected.
9954          * Should anything bad happen only the expected state is
9955          * restored, not the drivers personal bookkeeping.
9956          */
9957         count = 0;
9958         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9959                 config->save_crtc_enabled[count++] = crtc->enabled;
9960         }
9961
9962         count = 0;
9963         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9964                 config->save_encoder_crtcs[count++] = encoder->crtc;
9965         }
9966
9967         count = 0;
9968         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9969                 config->save_connector_encoders[count++] = connector->encoder;
9970         }
9971
9972         return 0;
9973 }
9974
9975 static void intel_set_config_restore_state(struct drm_device *dev,
9976                                            struct intel_set_config *config)
9977 {
9978         struct intel_crtc *crtc;
9979         struct intel_encoder *encoder;
9980         struct intel_connector *connector;
9981         int count;
9982
9983         count = 0;
9984         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9985                 crtc->new_enabled = config->save_crtc_enabled[count++];
9986
9987                 if (crtc->new_enabled)
9988                         crtc->new_config = &crtc->config;
9989                 else
9990                         crtc->new_config = NULL;
9991         }
9992
9993         count = 0;
9994         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9995                 encoder->new_crtc =
9996                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9997         }
9998
9999         count = 0;
10000         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10001                 connector->new_encoder =
10002                         to_intel_encoder(config->save_connector_encoders[count++]);
10003         }
10004 }
10005
10006 static bool
10007 is_crtc_connector_off(struct drm_mode_set *set)
10008 {
10009         int i;
10010
10011         if (set->num_connectors == 0)
10012                 return false;
10013
10014         if (WARN_ON(set->connectors == NULL))
10015                 return false;
10016
10017         for (i = 0; i < set->num_connectors; i++)
10018                 if (set->connectors[i]->encoder &&
10019                     set->connectors[i]->encoder->crtc == set->crtc &&
10020                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10021                         return true;
10022
10023         return false;
10024 }
10025
10026 static void
10027 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10028                                       struct intel_set_config *config)
10029 {
10030
10031         /* We should be able to check here if the fb has the same properties
10032          * and then just flip_or_move it */
10033         if (is_crtc_connector_off(set)) {
10034                 config->mode_changed = true;
10035         } else if (set->crtc->fb != set->fb) {
10036                 /* If we have no fb then treat it as a full mode set */
10037                 if (set->crtc->fb == NULL) {
10038                         struct intel_crtc *intel_crtc =
10039                                 to_intel_crtc(set->crtc);
10040
10041                         if (intel_crtc->active && i915.fastboot) {
10042                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10043                                 config->fb_changed = true;
10044                         } else {
10045                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10046                                 config->mode_changed = true;
10047                         }
10048                 } else if (set->fb == NULL) {
10049                         config->mode_changed = true;
10050                 } else if (set->fb->pixel_format !=
10051                            set->crtc->fb->pixel_format) {
10052                         config->mode_changed = true;
10053                 } else {
10054                         config->fb_changed = true;
10055                 }
10056         }
10057
10058         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10059                 config->fb_changed = true;
10060
10061         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10062                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10063                 drm_mode_debug_printmodeline(&set->crtc->mode);
10064                 drm_mode_debug_printmodeline(set->mode);
10065                 config->mode_changed = true;
10066         }
10067
10068         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10069                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10070 }
10071
10072 static int
10073 intel_modeset_stage_output_state(struct drm_device *dev,
10074                                  struct drm_mode_set *set,
10075                                  struct intel_set_config *config)
10076 {
10077         struct intel_connector *connector;
10078         struct intel_encoder *encoder;
10079         struct intel_crtc *crtc;
10080         int ro;
10081
10082         /* The upper layers ensure that we either disable a crtc or have a list
10083          * of connectors. For paranoia, double-check this. */
10084         WARN_ON(!set->fb && (set->num_connectors != 0));
10085         WARN_ON(set->fb && (set->num_connectors == 0));
10086
10087         list_for_each_entry(connector, &dev->mode_config.connector_list,
10088                             base.head) {
10089                 /* Otherwise traverse passed in connector list and get encoders
10090                  * for them. */
10091                 for (ro = 0; ro < set->num_connectors; ro++) {
10092                         if (set->connectors[ro] == &connector->base) {
10093                                 connector->new_encoder = connector->encoder;
10094                                 break;
10095                         }
10096                 }
10097
10098                 /* If we disable the crtc, disable all its connectors. Also, if
10099                  * the connector is on the changing crtc but not on the new
10100                  * connector list, disable it. */
10101                 if ((!set->fb || ro == set->num_connectors) &&
10102                     connector->base.encoder &&
10103                     connector->base.encoder->crtc == set->crtc) {
10104                         connector->new_encoder = NULL;
10105
10106                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10107                                 connector->base.base.id,
10108                                 drm_get_connector_name(&connector->base));
10109                 }
10110
10111
10112                 if (&connector->new_encoder->base != connector->base.encoder) {
10113                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10114                         config->mode_changed = true;
10115                 }
10116         }
10117         /* connector->new_encoder is now updated for all connectors. */
10118
10119         /* Update crtc of enabled connectors. */
10120         list_for_each_entry(connector, &dev->mode_config.connector_list,
10121                             base.head) {
10122                 struct drm_crtc *new_crtc;
10123
10124                 if (!connector->new_encoder)
10125                         continue;
10126
10127                 new_crtc = connector->new_encoder->base.crtc;
10128
10129                 for (ro = 0; ro < set->num_connectors; ro++) {
10130                         if (set->connectors[ro] == &connector->base)
10131                                 new_crtc = set->crtc;
10132                 }
10133
10134                 /* Make sure the new CRTC will work with the encoder */
10135                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10136                                          new_crtc)) {
10137                         return -EINVAL;
10138                 }
10139                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10140
10141                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10142                         connector->base.base.id,
10143                         drm_get_connector_name(&connector->base),
10144                         new_crtc->base.id);
10145         }
10146
10147         /* Check for any encoders that needs to be disabled. */
10148         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10149                             base.head) {
10150                 int num_connectors = 0;
10151                 list_for_each_entry(connector,
10152                                     &dev->mode_config.connector_list,
10153                                     base.head) {
10154                         if (connector->new_encoder == encoder) {
10155                                 WARN_ON(!connector->new_encoder->new_crtc);
10156                                 num_connectors++;
10157                         }
10158                 }
10159
10160                 if (num_connectors == 0)
10161                         encoder->new_crtc = NULL;
10162                 else if (num_connectors > 1)
10163                         return -EINVAL;
10164
10165                 /* Only now check for crtc changes so we don't miss encoders
10166                  * that will be disabled. */
10167                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10168                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10169                         config->mode_changed = true;
10170                 }
10171         }
10172         /* Now we've also updated encoder->new_crtc for all encoders. */
10173
10174         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10175                             base.head) {
10176                 crtc->new_enabled = false;
10177
10178                 list_for_each_entry(encoder,
10179                                     &dev->mode_config.encoder_list,
10180                                     base.head) {
10181                         if (encoder->new_crtc == crtc) {
10182                                 crtc->new_enabled = true;
10183                                 break;
10184                         }
10185                 }
10186
10187                 if (crtc->new_enabled != crtc->base.enabled) {
10188                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10189                                       crtc->new_enabled ? "en" : "dis");
10190                         config->mode_changed = true;
10191                 }
10192
10193                 if (crtc->new_enabled)
10194                         crtc->new_config = &crtc->config;
10195                 else
10196                         crtc->new_config = NULL;
10197         }
10198
10199         return 0;
10200 }
10201
10202 static void disable_crtc_nofb(struct intel_crtc *crtc)
10203 {
10204         struct drm_device *dev = crtc->base.dev;
10205         struct intel_encoder *encoder;
10206         struct intel_connector *connector;
10207
10208         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10209                       pipe_name(crtc->pipe));
10210
10211         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10212                 if (connector->new_encoder &&
10213                     connector->new_encoder->new_crtc == crtc)
10214                         connector->new_encoder = NULL;
10215         }
10216
10217         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10218                 if (encoder->new_crtc == crtc)
10219                         encoder->new_crtc = NULL;
10220         }
10221
10222         crtc->new_enabled = false;
10223         crtc->new_config = NULL;
10224 }
10225
10226 static int intel_crtc_set_config(struct drm_mode_set *set)
10227 {
10228         struct drm_device *dev;
10229         struct drm_mode_set save_set;
10230         struct intel_set_config *config;
10231         int ret;
10232
10233         BUG_ON(!set);
10234         BUG_ON(!set->crtc);
10235         BUG_ON(!set->crtc->helper_private);
10236
10237         /* Enforce sane interface api - has been abused by the fb helper. */
10238         BUG_ON(!set->mode && set->fb);
10239         BUG_ON(set->fb && set->num_connectors == 0);
10240
10241         if (set->fb) {
10242                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10243                                 set->crtc->base.id, set->fb->base.id,
10244                                 (int)set->num_connectors, set->x, set->y);
10245         } else {
10246                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10247         }
10248
10249         dev = set->crtc->dev;
10250
10251         ret = -ENOMEM;
10252         config = kzalloc(sizeof(*config), GFP_KERNEL);
10253         if (!config)
10254                 goto out_config;
10255
10256         ret = intel_set_config_save_state(dev, config);
10257         if (ret)
10258                 goto out_config;
10259
10260         save_set.crtc = set->crtc;
10261         save_set.mode = &set->crtc->mode;
10262         save_set.x = set->crtc->x;
10263         save_set.y = set->crtc->y;
10264         save_set.fb = set->crtc->fb;
10265
10266         /* Compute whether we need a full modeset, only an fb base update or no
10267          * change at all. In the future we might also check whether only the
10268          * mode changed, e.g. for LVDS where we only change the panel fitter in
10269          * such cases. */
10270         intel_set_config_compute_mode_changes(set, config);
10271
10272         ret = intel_modeset_stage_output_state(dev, set, config);
10273         if (ret)
10274                 goto fail;
10275
10276         if (config->mode_changed) {
10277                 ret = intel_set_mode(set->crtc, set->mode,
10278                                      set->x, set->y, set->fb);
10279         } else if (config->fb_changed) {
10280                 intel_crtc_wait_for_pending_flips(set->crtc);
10281
10282                 ret = intel_pipe_set_base(set->crtc,
10283                                           set->x, set->y, set->fb);
10284                 /*
10285                  * In the fastboot case this may be our only check of the
10286                  * state after boot.  It would be better to only do it on
10287                  * the first update, but we don't have a nice way of doing that
10288                  * (and really, set_config isn't used much for high freq page
10289                  * flipping, so increasing its cost here shouldn't be a big
10290                  * deal).
10291                  */
10292                 if (i915.fastboot && ret == 0)
10293                         intel_modeset_check_state(set->crtc->dev);
10294         }
10295
10296         if (ret) {
10297                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10298                               set->crtc->base.id, ret);
10299 fail:
10300                 intel_set_config_restore_state(dev, config);
10301
10302                 /*
10303                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10304                  * force the pipe off to avoid oopsing in the modeset code
10305                  * due to fb==NULL. This should only happen during boot since
10306                  * we don't yet reconstruct the FB from the hardware state.
10307                  */
10308                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10309                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10310
10311                 /* Try to restore the config */
10312                 if (config->mode_changed &&
10313                     intel_set_mode(save_set.crtc, save_set.mode,
10314                                    save_set.x, save_set.y, save_set.fb))
10315                         DRM_ERROR("failed to restore config after modeset failure\n");
10316         }
10317
10318 out_config:
10319         intel_set_config_free(config);
10320         return ret;
10321 }
10322
10323 static const struct drm_crtc_funcs intel_crtc_funcs = {
10324         .cursor_set = intel_crtc_cursor_set,
10325         .cursor_move = intel_crtc_cursor_move,
10326         .gamma_set = intel_crtc_gamma_set,
10327         .set_config = intel_crtc_set_config,
10328         .destroy = intel_crtc_destroy,
10329         .page_flip = intel_crtc_page_flip,
10330 };
10331
10332 static void intel_cpu_pll_init(struct drm_device *dev)
10333 {
10334         if (HAS_DDI(dev))
10335                 intel_ddi_pll_init(dev);
10336 }
10337
10338 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10339                                       struct intel_shared_dpll *pll,
10340                                       struct intel_dpll_hw_state *hw_state)
10341 {
10342         uint32_t val;
10343
10344         val = I915_READ(PCH_DPLL(pll->id));
10345         hw_state->dpll = val;
10346         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10347         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10348
10349         return val & DPLL_VCO_ENABLE;
10350 }
10351
10352 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10353                                   struct intel_shared_dpll *pll)
10354 {
10355         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10356         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10357 }
10358
10359 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10360                                 struct intel_shared_dpll *pll)
10361 {
10362         /* PCH refclock must be enabled first */
10363         ibx_assert_pch_refclk_enabled(dev_priv);
10364
10365         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10366
10367         /* Wait for the clocks to stabilize. */
10368         POSTING_READ(PCH_DPLL(pll->id));
10369         udelay(150);
10370
10371         /* The pixel multiplier can only be updated once the
10372          * DPLL is enabled and the clocks are stable.
10373          *
10374          * So write it again.
10375          */
10376         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10377         POSTING_READ(PCH_DPLL(pll->id));
10378         udelay(200);
10379 }
10380
10381 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10382                                  struct intel_shared_dpll *pll)
10383 {
10384         struct drm_device *dev = dev_priv->dev;
10385         struct intel_crtc *crtc;
10386
10387         /* Make sure no transcoder isn't still depending on us. */
10388         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10389                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10390                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10391         }
10392
10393         I915_WRITE(PCH_DPLL(pll->id), 0);
10394         POSTING_READ(PCH_DPLL(pll->id));
10395         udelay(200);
10396 }
10397
10398 static char *ibx_pch_dpll_names[] = {
10399         "PCH DPLL A",
10400         "PCH DPLL B",
10401 };
10402
10403 static void ibx_pch_dpll_init(struct drm_device *dev)
10404 {
10405         struct drm_i915_private *dev_priv = dev->dev_private;
10406         int i;
10407
10408         dev_priv->num_shared_dpll = 2;
10409
10410         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10411                 dev_priv->shared_dplls[i].id = i;
10412                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10413                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10414                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10415                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10416                 dev_priv->shared_dplls[i].get_hw_state =
10417                         ibx_pch_dpll_get_hw_state;
10418         }
10419 }
10420
10421 static void intel_shared_dpll_init(struct drm_device *dev)
10422 {
10423         struct drm_i915_private *dev_priv = dev->dev_private;
10424
10425         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10426                 ibx_pch_dpll_init(dev);
10427         else
10428                 dev_priv->num_shared_dpll = 0;
10429
10430         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10431 }
10432
10433 static void intel_crtc_init(struct drm_device *dev, int pipe)
10434 {
10435         drm_i915_private_t *dev_priv = dev->dev_private;
10436         struct intel_crtc *intel_crtc;
10437         int i;
10438
10439         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10440         if (intel_crtc == NULL)
10441                 return;
10442
10443         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10444
10445         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10446         for (i = 0; i < 256; i++) {
10447                 intel_crtc->lut_r[i] = i;
10448                 intel_crtc->lut_g[i] = i;
10449                 intel_crtc->lut_b[i] = i;
10450         }
10451
10452         /*
10453          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10454          * is hooked to plane B. Hence we want plane A feeding pipe B.
10455          */
10456         intel_crtc->pipe = pipe;
10457         intel_crtc->plane = pipe;
10458         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10459                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10460                 intel_crtc->plane = !pipe;
10461         }
10462
10463         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10464                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10465         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10466         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10467
10468         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10469 }
10470
10471 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10472 {
10473         struct drm_encoder *encoder = connector->base.encoder;
10474
10475         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10476
10477         if (!encoder)
10478                 return INVALID_PIPE;
10479
10480         return to_intel_crtc(encoder->crtc)->pipe;
10481 }
10482
10483 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10484                                 struct drm_file *file)
10485 {
10486         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10487         struct drm_mode_object *drmmode_obj;
10488         struct intel_crtc *crtc;
10489
10490         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10491                 return -ENODEV;
10492
10493         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10494                         DRM_MODE_OBJECT_CRTC);
10495
10496         if (!drmmode_obj) {
10497                 DRM_ERROR("no such CRTC id\n");
10498                 return -ENOENT;
10499         }
10500
10501         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10502         pipe_from_crtc_id->pipe = crtc->pipe;
10503
10504         return 0;
10505 }
10506
10507 static int intel_encoder_clones(struct intel_encoder *encoder)
10508 {
10509         struct drm_device *dev = encoder->base.dev;
10510         struct intel_encoder *source_encoder;
10511         int index_mask = 0;
10512         int entry = 0;
10513
10514         list_for_each_entry(source_encoder,
10515                             &dev->mode_config.encoder_list, base.head) {
10516
10517                 if (encoder == source_encoder)
10518                         index_mask |= (1 << entry);
10519
10520                 /* Intel hw has only one MUX where enocoders could be cloned. */
10521                 if (encoder->cloneable && source_encoder->cloneable)
10522                         index_mask |= (1 << entry);
10523
10524                 entry++;
10525         }
10526
10527         return index_mask;
10528 }
10529
10530 static bool has_edp_a(struct drm_device *dev)
10531 {
10532         struct drm_i915_private *dev_priv = dev->dev_private;
10533
10534         if (!IS_MOBILE(dev))
10535                 return false;
10536
10537         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10538                 return false;
10539
10540         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10541                 return false;
10542
10543         return true;
10544 }
10545
10546 const char *intel_output_name(int output)
10547 {
10548         static const char *names[] = {
10549                 [INTEL_OUTPUT_UNUSED] = "Unused",
10550                 [INTEL_OUTPUT_ANALOG] = "Analog",
10551                 [INTEL_OUTPUT_DVO] = "DVO",
10552                 [INTEL_OUTPUT_SDVO] = "SDVO",
10553                 [INTEL_OUTPUT_LVDS] = "LVDS",
10554                 [INTEL_OUTPUT_TVOUT] = "TV",
10555                 [INTEL_OUTPUT_HDMI] = "HDMI",
10556                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10557                 [INTEL_OUTPUT_EDP] = "eDP",
10558                 [INTEL_OUTPUT_DSI] = "DSI",
10559                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10560         };
10561
10562         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10563                 return "Invalid";
10564
10565         return names[output];
10566 }
10567
10568 static void intel_setup_outputs(struct drm_device *dev)
10569 {
10570         struct drm_i915_private *dev_priv = dev->dev_private;
10571         struct intel_encoder *encoder;
10572         bool dpd_is_edp = false;
10573
10574         intel_lvds_init(dev);
10575
10576         if (!IS_ULT(dev))
10577                 intel_crt_init(dev);
10578
10579         if (HAS_DDI(dev)) {
10580                 int found;
10581
10582                 /* Haswell uses DDI functions to detect digital outputs */
10583                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10584                 /* DDI A only supports eDP */
10585                 if (found)
10586                         intel_ddi_init(dev, PORT_A);
10587
10588                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10589                  * register */
10590                 found = I915_READ(SFUSE_STRAP);
10591
10592                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10593                         intel_ddi_init(dev, PORT_B);
10594                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10595                         intel_ddi_init(dev, PORT_C);
10596                 if (found & SFUSE_STRAP_DDID_DETECTED)
10597                         intel_ddi_init(dev, PORT_D);
10598         } else if (HAS_PCH_SPLIT(dev)) {
10599                 int found;
10600                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10601
10602                 if (has_edp_a(dev))
10603                         intel_dp_init(dev, DP_A, PORT_A);
10604
10605                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10606                         /* PCH SDVOB multiplex with HDMIB */
10607                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10608                         if (!found)
10609                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10610                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10611                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10612                 }
10613
10614                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10615                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10616
10617                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10618                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10619
10620                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10621                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10622
10623                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10624                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10625         } else if (IS_VALLEYVIEW(dev)) {
10626                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10627                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10628                                         PORT_B);
10629                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10630                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10631                 }
10632
10633                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10634                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10635                                         PORT_C);
10636                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10637                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10638                 }
10639
10640                 intel_dsi_init(dev);
10641         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10642                 bool found = false;
10643
10644                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10645                         DRM_DEBUG_KMS("probing SDVOB\n");
10646                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10647                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10648                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10649                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10650                         }
10651
10652                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10653                                 intel_dp_init(dev, DP_B, PORT_B);
10654                 }
10655
10656                 /* Before G4X SDVOC doesn't have its own detect register */
10657
10658                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10659                         DRM_DEBUG_KMS("probing SDVOC\n");
10660                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10661                 }
10662
10663                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10664
10665                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10666                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10667                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10668                         }
10669                         if (SUPPORTS_INTEGRATED_DP(dev))
10670                                 intel_dp_init(dev, DP_C, PORT_C);
10671                 }
10672
10673                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10674                     (I915_READ(DP_D) & DP_DETECTED))
10675                         intel_dp_init(dev, DP_D, PORT_D);
10676         } else if (IS_GEN2(dev))
10677                 intel_dvo_init(dev);
10678
10679         if (SUPPORTS_TV(dev))
10680                 intel_tv_init(dev);
10681
10682         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10683                 encoder->base.possible_crtcs = encoder->crtc_mask;
10684                 encoder->base.possible_clones =
10685                         intel_encoder_clones(encoder);
10686         }
10687
10688         intel_init_pch_refclk(dev);
10689
10690         drm_helper_move_panel_connectors_to_head(dev);
10691 }
10692
10693 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10694 {
10695         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10696
10697         drm_framebuffer_cleanup(fb);
10698         WARN_ON(!intel_fb->obj->framebuffer_references--);
10699         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10700         kfree(intel_fb);
10701 }
10702
10703 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10704                                                 struct drm_file *file,
10705                                                 unsigned int *handle)
10706 {
10707         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10708         struct drm_i915_gem_object *obj = intel_fb->obj;
10709
10710         return drm_gem_handle_create(file, &obj->base, handle);
10711 }
10712
10713 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10714         .destroy = intel_user_framebuffer_destroy,
10715         .create_handle = intel_user_framebuffer_create_handle,
10716 };
10717
10718 static int intel_framebuffer_init(struct drm_device *dev,
10719                                   struct intel_framebuffer *intel_fb,
10720                                   struct drm_mode_fb_cmd2 *mode_cmd,
10721                                   struct drm_i915_gem_object *obj)
10722 {
10723         int aligned_height;
10724         int pitch_limit;
10725         int ret;
10726
10727         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10728
10729         if (obj->tiling_mode == I915_TILING_Y) {
10730                 DRM_DEBUG("hardware does not support tiling Y\n");
10731                 return -EINVAL;
10732         }
10733
10734         if (mode_cmd->pitches[0] & 63) {
10735                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10736                           mode_cmd->pitches[0]);
10737                 return -EINVAL;
10738         }
10739
10740         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10741                 pitch_limit = 32*1024;
10742         } else if (INTEL_INFO(dev)->gen >= 4) {
10743                 if (obj->tiling_mode)
10744                         pitch_limit = 16*1024;
10745                 else
10746                         pitch_limit = 32*1024;
10747         } else if (INTEL_INFO(dev)->gen >= 3) {
10748                 if (obj->tiling_mode)
10749                         pitch_limit = 8*1024;
10750                 else
10751                         pitch_limit = 16*1024;
10752         } else
10753                 /* XXX DSPC is limited to 4k tiled */
10754                 pitch_limit = 8*1024;
10755
10756         if (mode_cmd->pitches[0] > pitch_limit) {
10757                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10758                           obj->tiling_mode ? "tiled" : "linear",
10759                           mode_cmd->pitches[0], pitch_limit);
10760                 return -EINVAL;
10761         }
10762
10763         if (obj->tiling_mode != I915_TILING_NONE &&
10764             mode_cmd->pitches[0] != obj->stride) {
10765                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10766                           mode_cmd->pitches[0], obj->stride);
10767                 return -EINVAL;
10768         }
10769
10770         /* Reject formats not supported by any plane early. */
10771         switch (mode_cmd->pixel_format) {
10772         case DRM_FORMAT_C8:
10773         case DRM_FORMAT_RGB565:
10774         case DRM_FORMAT_XRGB8888:
10775         case DRM_FORMAT_ARGB8888:
10776                 break;
10777         case DRM_FORMAT_XRGB1555:
10778         case DRM_FORMAT_ARGB1555:
10779                 if (INTEL_INFO(dev)->gen > 3) {
10780                         DRM_DEBUG("unsupported pixel format: %s\n",
10781                                   drm_get_format_name(mode_cmd->pixel_format));
10782                         return -EINVAL;
10783                 }
10784                 break;
10785         case DRM_FORMAT_XBGR8888:
10786         case DRM_FORMAT_ABGR8888:
10787         case DRM_FORMAT_XRGB2101010:
10788         case DRM_FORMAT_ARGB2101010:
10789         case DRM_FORMAT_XBGR2101010:
10790         case DRM_FORMAT_ABGR2101010:
10791                 if (INTEL_INFO(dev)->gen < 4) {
10792                         DRM_DEBUG("unsupported pixel format: %s\n",
10793                                   drm_get_format_name(mode_cmd->pixel_format));
10794                         return -EINVAL;
10795                 }
10796                 break;
10797         case DRM_FORMAT_YUYV:
10798         case DRM_FORMAT_UYVY:
10799         case DRM_FORMAT_YVYU:
10800         case DRM_FORMAT_VYUY:
10801                 if (INTEL_INFO(dev)->gen < 5) {
10802                         DRM_DEBUG("unsupported pixel format: %s\n",
10803                                   drm_get_format_name(mode_cmd->pixel_format));
10804                         return -EINVAL;
10805                 }
10806                 break;
10807         default:
10808                 DRM_DEBUG("unsupported pixel format: %s\n",
10809                           drm_get_format_name(mode_cmd->pixel_format));
10810                 return -EINVAL;
10811         }
10812
10813         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10814         if (mode_cmd->offsets[0] != 0)
10815                 return -EINVAL;
10816
10817         aligned_height = intel_align_height(dev, mode_cmd->height,
10818                                             obj->tiling_mode);
10819         /* FIXME drm helper for size checks (especially planar formats)? */
10820         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10821                 return -EINVAL;
10822
10823         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10824         intel_fb->obj = obj;
10825         intel_fb->obj->framebuffer_references++;
10826
10827         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10828         if (ret) {
10829                 DRM_ERROR("framebuffer init failed %d\n", ret);
10830                 return ret;
10831         }
10832
10833         return 0;
10834 }
10835
10836 static struct drm_framebuffer *
10837 intel_user_framebuffer_create(struct drm_device *dev,
10838                               struct drm_file *filp,
10839                               struct drm_mode_fb_cmd2 *mode_cmd)
10840 {
10841         struct drm_i915_gem_object *obj;
10842
10843         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10844                                                 mode_cmd->handles[0]));
10845         if (&obj->base == NULL)
10846                 return ERR_PTR(-ENOENT);
10847
10848         return intel_framebuffer_create(dev, mode_cmd, obj);
10849 }
10850
10851 #ifndef CONFIG_DRM_I915_FBDEV
10852 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10853 {
10854 }
10855 #endif
10856
10857 static const struct drm_mode_config_funcs intel_mode_funcs = {
10858         .fb_create = intel_user_framebuffer_create,
10859         .output_poll_changed = intel_fbdev_output_poll_changed,
10860 };
10861
10862 /* Set up chip specific display functions */
10863 static void intel_init_display(struct drm_device *dev)
10864 {
10865         struct drm_i915_private *dev_priv = dev->dev_private;
10866
10867         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10868                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10869         else if (IS_VALLEYVIEW(dev))
10870                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10871         else if (IS_PINEVIEW(dev))
10872                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10873         else
10874                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10875
10876         if (HAS_DDI(dev)) {
10877                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10878                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10879                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10880                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10881                 dev_priv->display.off = haswell_crtc_off;
10882                 dev_priv->display.update_plane = ironlake_update_plane;
10883         } else if (HAS_PCH_SPLIT(dev)) {
10884                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10885                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10886                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10887                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10888                 dev_priv->display.off = ironlake_crtc_off;
10889                 dev_priv->display.update_plane = ironlake_update_plane;
10890         } else if (IS_VALLEYVIEW(dev)) {
10891                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10892                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10893                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10894                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10895                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10896                 dev_priv->display.off = i9xx_crtc_off;
10897                 dev_priv->display.update_plane = i9xx_update_plane;
10898         } else {
10899                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10900                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10901                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10902                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10903                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10904                 dev_priv->display.off = i9xx_crtc_off;
10905                 dev_priv->display.update_plane = i9xx_update_plane;
10906         }
10907
10908         /* Returns the core display clock speed */
10909         if (IS_VALLEYVIEW(dev))
10910                 dev_priv->display.get_display_clock_speed =
10911                         valleyview_get_display_clock_speed;
10912         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10913                 dev_priv->display.get_display_clock_speed =
10914                         i945_get_display_clock_speed;
10915         else if (IS_I915G(dev))
10916                 dev_priv->display.get_display_clock_speed =
10917                         i915_get_display_clock_speed;
10918         else if (IS_I945GM(dev) || IS_845G(dev))
10919                 dev_priv->display.get_display_clock_speed =
10920                         i9xx_misc_get_display_clock_speed;
10921         else if (IS_PINEVIEW(dev))
10922                 dev_priv->display.get_display_clock_speed =
10923                         pnv_get_display_clock_speed;
10924         else if (IS_I915GM(dev))
10925                 dev_priv->display.get_display_clock_speed =
10926                         i915gm_get_display_clock_speed;
10927         else if (IS_I865G(dev))
10928                 dev_priv->display.get_display_clock_speed =
10929                         i865_get_display_clock_speed;
10930         else if (IS_I85X(dev))
10931                 dev_priv->display.get_display_clock_speed =
10932                         i855_get_display_clock_speed;
10933         else /* 852, 830 */
10934                 dev_priv->display.get_display_clock_speed =
10935                         i830_get_display_clock_speed;
10936
10937         if (HAS_PCH_SPLIT(dev)) {
10938                 if (IS_GEN5(dev)) {
10939                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10940                         dev_priv->display.write_eld = ironlake_write_eld;
10941                 } else if (IS_GEN6(dev)) {
10942                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10943                         dev_priv->display.write_eld = ironlake_write_eld;
10944                 } else if (IS_IVYBRIDGE(dev)) {
10945                         /* FIXME: detect B0+ stepping and use auto training */
10946                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10947                         dev_priv->display.write_eld = ironlake_write_eld;
10948                         dev_priv->display.modeset_global_resources =
10949                                 ivb_modeset_global_resources;
10950                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10951                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10952                         dev_priv->display.write_eld = haswell_write_eld;
10953                         dev_priv->display.modeset_global_resources =
10954                                 haswell_modeset_global_resources;
10955                 }
10956         } else if (IS_G4X(dev)) {
10957                 dev_priv->display.write_eld = g4x_write_eld;
10958         } else if (IS_VALLEYVIEW(dev)) {
10959                 dev_priv->display.modeset_global_resources =
10960                         valleyview_modeset_global_resources;
10961                 dev_priv->display.write_eld = ironlake_write_eld;
10962         }
10963
10964         /* Default just returns -ENODEV to indicate unsupported */
10965         dev_priv->display.queue_flip = intel_default_queue_flip;
10966
10967         switch (INTEL_INFO(dev)->gen) {
10968         case 2:
10969                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10970                 break;
10971
10972         case 3:
10973                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10974                 break;
10975
10976         case 4:
10977         case 5:
10978                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10979                 break;
10980
10981         case 6:
10982                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10983                 break;
10984         case 7:
10985         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10986                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10987                 break;
10988         }
10989
10990         intel_panel_init_backlight_funcs(dev);
10991 }
10992
10993 /*
10994  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10995  * resume, or other times.  This quirk makes sure that's the case for
10996  * affected systems.
10997  */
10998 static void quirk_pipea_force(struct drm_device *dev)
10999 {
11000         struct drm_i915_private *dev_priv = dev->dev_private;
11001
11002         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11003         DRM_INFO("applying pipe a force quirk\n");
11004 }
11005
11006 /*
11007  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11008  */
11009 static void quirk_ssc_force_disable(struct drm_device *dev)
11010 {
11011         struct drm_i915_private *dev_priv = dev->dev_private;
11012         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11013         DRM_INFO("applying lvds SSC disable quirk\n");
11014 }
11015
11016 /*
11017  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11018  * brightness value
11019  */
11020 static void quirk_invert_brightness(struct drm_device *dev)
11021 {
11022         struct drm_i915_private *dev_priv = dev->dev_private;
11023         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11024         DRM_INFO("applying inverted panel brightness quirk\n");
11025 }
11026
11027 struct intel_quirk {
11028         int device;
11029         int subsystem_vendor;
11030         int subsystem_device;
11031         void (*hook)(struct drm_device *dev);
11032 };
11033
11034 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11035 struct intel_dmi_quirk {
11036         void (*hook)(struct drm_device *dev);
11037         const struct dmi_system_id (*dmi_id_list)[];
11038 };
11039
11040 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11041 {
11042         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11043         return 1;
11044 }
11045
11046 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11047         {
11048                 .dmi_id_list = &(const struct dmi_system_id[]) {
11049                         {
11050                                 .callback = intel_dmi_reverse_brightness,
11051                                 .ident = "NCR Corporation",
11052                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11053                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11054                                 },
11055                         },
11056                         { }  /* terminating entry */
11057                 },
11058                 .hook = quirk_invert_brightness,
11059         },
11060 };
11061
11062 static struct intel_quirk intel_quirks[] = {
11063         /* HP Mini needs pipe A force quirk (LP: #322104) */
11064         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11065
11066         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11067         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11068
11069         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11070         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11071
11072         /* 830 needs to leave pipe A & dpll A up */
11073         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11074
11075         /* Lenovo U160 cannot use SSC on LVDS */
11076         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11077
11078         /* Sony Vaio Y cannot use SSC on LVDS */
11079         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11080
11081         /* Acer Aspire 5734Z must invert backlight brightness */
11082         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11083
11084         /* Acer/eMachines G725 */
11085         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11086
11087         /* Acer/eMachines e725 */
11088         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11089
11090         /* Acer/Packard Bell NCL20 */
11091         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11092
11093         /* Acer Aspire 4736Z */
11094         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11095
11096         /* Acer Aspire 5336 */
11097         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11098 };
11099
11100 static void intel_init_quirks(struct drm_device *dev)
11101 {
11102         struct pci_dev *d = dev->pdev;
11103         int i;
11104
11105         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11106                 struct intel_quirk *q = &intel_quirks[i];
11107
11108                 if (d->device == q->device &&
11109                     (d->subsystem_vendor == q->subsystem_vendor ||
11110                      q->subsystem_vendor == PCI_ANY_ID) &&
11111                     (d->subsystem_device == q->subsystem_device ||
11112                      q->subsystem_device == PCI_ANY_ID))
11113                         q->hook(dev);
11114         }
11115         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11116                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11117                         intel_dmi_quirks[i].hook(dev);
11118         }
11119 }
11120
11121 /* Disable the VGA plane that we never use */
11122 static void i915_disable_vga(struct drm_device *dev)
11123 {
11124         struct drm_i915_private *dev_priv = dev->dev_private;
11125         u8 sr1;
11126         u32 vga_reg = i915_vgacntrl_reg(dev);
11127
11128         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11129         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11130         outb(SR01, VGA_SR_INDEX);
11131         sr1 = inb(VGA_SR_DATA);
11132         outb(sr1 | 1<<5, VGA_SR_DATA);
11133         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11134         udelay(300);
11135
11136         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11137         POSTING_READ(vga_reg);
11138 }
11139
11140 void intel_modeset_init_hw(struct drm_device *dev)
11141 {
11142         intel_prepare_ddi(dev);
11143
11144         intel_init_clock_gating(dev);
11145
11146         intel_reset_dpio(dev);
11147
11148         mutex_lock(&dev->struct_mutex);
11149         intel_enable_gt_powersave(dev);
11150         mutex_unlock(&dev->struct_mutex);
11151 }
11152
11153 void intel_modeset_suspend_hw(struct drm_device *dev)
11154 {
11155         intel_suspend_hw(dev);
11156 }
11157
11158 void intel_modeset_init(struct drm_device *dev)
11159 {
11160         struct drm_i915_private *dev_priv = dev->dev_private;
11161         int sprite, ret;
11162         enum pipe pipe;
11163         struct intel_crtc *crtc;
11164
11165         drm_mode_config_init(dev);
11166
11167         dev->mode_config.min_width = 0;
11168         dev->mode_config.min_height = 0;
11169
11170         dev->mode_config.preferred_depth = 24;
11171         dev->mode_config.prefer_shadow = 1;
11172
11173         dev->mode_config.funcs = &intel_mode_funcs;
11174
11175         intel_init_quirks(dev);
11176
11177         intel_init_pm(dev);
11178
11179         if (INTEL_INFO(dev)->num_pipes == 0)
11180                 return;
11181
11182         intel_init_display(dev);
11183
11184         if (IS_GEN2(dev)) {
11185                 dev->mode_config.max_width = 2048;
11186                 dev->mode_config.max_height = 2048;
11187         } else if (IS_GEN3(dev)) {
11188                 dev->mode_config.max_width = 4096;
11189                 dev->mode_config.max_height = 4096;
11190         } else {
11191                 dev->mode_config.max_width = 8192;
11192                 dev->mode_config.max_height = 8192;
11193         }
11194         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11195
11196         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11197                       INTEL_INFO(dev)->num_pipes,
11198                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11199
11200         for_each_pipe(pipe) {
11201                 intel_crtc_init(dev, pipe);
11202                 for_each_sprite(pipe, sprite) {
11203                         ret = intel_plane_init(dev, pipe, sprite);
11204                         if (ret)
11205                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11206                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11207                 }
11208         }
11209
11210         intel_init_dpio(dev);
11211         intel_reset_dpio(dev);
11212
11213         intel_cpu_pll_init(dev);
11214         intel_shared_dpll_init(dev);
11215
11216         /* Just disable it once at startup */
11217         i915_disable_vga(dev);
11218         intel_setup_outputs(dev);
11219
11220         /* Just in case the BIOS is doing something questionable. */
11221         intel_disable_fbc(dev);
11222
11223         mutex_lock(&dev->mode_config.mutex);
11224         intel_modeset_setup_hw_state(dev, false);
11225         mutex_unlock(&dev->mode_config.mutex);
11226
11227         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11228                             base.head) {
11229                 if (!crtc->active)
11230                         continue;
11231
11232 #if IS_ENABLED(CONFIG_FB)
11233                 /*
11234                  * We don't have a good way of freeing the buffer w/o the FB
11235                  * layer owning it...
11236                  * Note that reserving the BIOS fb up front prevents us
11237                  * from stuffing other stolen allocations like the ring
11238                  * on top.  This prevents some ugliness at boot time, and
11239                  * can even allow for smooth boot transitions if the BIOS
11240                  * fb is large enough for the active pipe configuration.
11241                  */
11242                 if (dev_priv->display.get_plane_config) {
11243                         dev_priv->display.get_plane_config(crtc,
11244                                                            &crtc->plane_config);
11245                         /*
11246                          * If the fb is shared between multiple heads, we'll
11247                          * just get the first one.
11248                          */
11249                         intel_alloc_plane_obj(crtc, &crtc->plane_config);
11250                 }
11251 #endif
11252         }
11253 }
11254
11255 static void
11256 intel_connector_break_all_links(struct intel_connector *connector)
11257 {
11258         connector->base.dpms = DRM_MODE_DPMS_OFF;
11259         connector->base.encoder = NULL;
11260         connector->encoder->connectors_active = false;
11261         connector->encoder->base.crtc = NULL;
11262 }
11263
11264 static void intel_enable_pipe_a(struct drm_device *dev)
11265 {
11266         struct intel_connector *connector;
11267         struct drm_connector *crt = NULL;
11268         struct intel_load_detect_pipe load_detect_temp;
11269
11270         /* We can't just switch on the pipe A, we need to set things up with a
11271          * proper mode and output configuration. As a gross hack, enable pipe A
11272          * by enabling the load detect pipe once. */
11273         list_for_each_entry(connector,
11274                             &dev->mode_config.connector_list,
11275                             base.head) {
11276                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11277                         crt = &connector->base;
11278                         break;
11279                 }
11280         }
11281
11282         if (!crt)
11283                 return;
11284
11285         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11286                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11287
11288
11289 }
11290
11291 static bool
11292 intel_check_plane_mapping(struct intel_crtc *crtc)
11293 {
11294         struct drm_device *dev = crtc->base.dev;
11295         struct drm_i915_private *dev_priv = dev->dev_private;
11296         u32 reg, val;
11297
11298         if (INTEL_INFO(dev)->num_pipes == 1)
11299                 return true;
11300
11301         reg = DSPCNTR(!crtc->plane);
11302         val = I915_READ(reg);
11303
11304         if ((val & DISPLAY_PLANE_ENABLE) &&
11305             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11306                 return false;
11307
11308         return true;
11309 }
11310
11311 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11312 {
11313         struct drm_device *dev = crtc->base.dev;
11314         struct drm_i915_private *dev_priv = dev->dev_private;
11315         u32 reg;
11316
11317         /* Clear any frame start delays used for debugging left by the BIOS */
11318         reg = PIPECONF(crtc->config.cpu_transcoder);
11319         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11320
11321         /* We need to sanitize the plane -> pipe mapping first because this will
11322          * disable the crtc (and hence change the state) if it is wrong. Note
11323          * that gen4+ has a fixed plane -> pipe mapping.  */
11324         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11325                 struct intel_connector *connector;
11326                 bool plane;
11327
11328                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11329                               crtc->base.base.id);
11330
11331                 /* Pipe has the wrong plane attached and the plane is active.
11332                  * Temporarily change the plane mapping and disable everything
11333                  * ...  */
11334                 plane = crtc->plane;
11335                 crtc->plane = !plane;
11336                 dev_priv->display.crtc_disable(&crtc->base);
11337                 crtc->plane = plane;
11338
11339                 /* ... and break all links. */
11340                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11341                                     base.head) {
11342                         if (connector->encoder->base.crtc != &crtc->base)
11343                                 continue;
11344
11345                         intel_connector_break_all_links(connector);
11346                 }
11347
11348                 WARN_ON(crtc->active);
11349                 crtc->base.enabled = false;
11350         }
11351
11352         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11353             crtc->pipe == PIPE_A && !crtc->active) {
11354                 /* BIOS forgot to enable pipe A, this mostly happens after
11355                  * resume. Force-enable the pipe to fix this, the update_dpms
11356                  * call below we restore the pipe to the right state, but leave
11357                  * the required bits on. */
11358                 intel_enable_pipe_a(dev);
11359         }
11360
11361         /* Adjust the state of the output pipe according to whether we
11362          * have active connectors/encoders. */
11363         intel_crtc_update_dpms(&crtc->base);
11364
11365         if (crtc->active != crtc->base.enabled) {
11366                 struct intel_encoder *encoder;
11367
11368                 /* This can happen either due to bugs in the get_hw_state
11369                  * functions or because the pipe is force-enabled due to the
11370                  * pipe A quirk. */
11371                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11372                               crtc->base.base.id,
11373                               crtc->base.enabled ? "enabled" : "disabled",
11374                               crtc->active ? "enabled" : "disabled");
11375
11376                 crtc->base.enabled = crtc->active;
11377
11378                 /* Because we only establish the connector -> encoder ->
11379                  * crtc links if something is active, this means the
11380                  * crtc is now deactivated. Break the links. connector
11381                  * -> encoder links are only establish when things are
11382                  *  actually up, hence no need to break them. */
11383                 WARN_ON(crtc->active);
11384
11385                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11386                         WARN_ON(encoder->connectors_active);
11387                         encoder->base.crtc = NULL;
11388                 }
11389         }
11390 }
11391
11392 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11393 {
11394         struct intel_connector *connector;
11395         struct drm_device *dev = encoder->base.dev;
11396
11397         /* We need to check both for a crtc link (meaning that the
11398          * encoder is active and trying to read from a pipe) and the
11399          * pipe itself being active. */
11400         bool has_active_crtc = encoder->base.crtc &&
11401                 to_intel_crtc(encoder->base.crtc)->active;
11402
11403         if (encoder->connectors_active && !has_active_crtc) {
11404                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11405                               encoder->base.base.id,
11406                               drm_get_encoder_name(&encoder->base));
11407
11408                 /* Connector is active, but has no active pipe. This is
11409                  * fallout from our resume register restoring. Disable
11410                  * the encoder manually again. */
11411                 if (encoder->base.crtc) {
11412                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11413                                       encoder->base.base.id,
11414                                       drm_get_encoder_name(&encoder->base));
11415                         encoder->disable(encoder);
11416                 }
11417
11418                 /* Inconsistent output/port/pipe state happens presumably due to
11419                  * a bug in one of the get_hw_state functions. Or someplace else
11420                  * in our code, like the register restore mess on resume. Clamp
11421                  * things to off as a safer default. */
11422                 list_for_each_entry(connector,
11423                                     &dev->mode_config.connector_list,
11424                                     base.head) {
11425                         if (connector->encoder != encoder)
11426                                 continue;
11427
11428                         intel_connector_break_all_links(connector);
11429                 }
11430         }
11431         /* Enabled encoders without active connectors will be fixed in
11432          * the crtc fixup. */
11433 }
11434
11435 void i915_redisable_vga_power_on(struct drm_device *dev)
11436 {
11437         struct drm_i915_private *dev_priv = dev->dev_private;
11438         u32 vga_reg = i915_vgacntrl_reg(dev);
11439
11440         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11441                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11442                 i915_disable_vga(dev);
11443         }
11444 }
11445
11446 void i915_redisable_vga(struct drm_device *dev)
11447 {
11448         struct drm_i915_private *dev_priv = dev->dev_private;
11449
11450         /* This function can be called both from intel_modeset_setup_hw_state or
11451          * at a very early point in our resume sequence, where the power well
11452          * structures are not yet restored. Since this function is at a very
11453          * paranoid "someone might have enabled VGA while we were not looking"
11454          * level, just check if the power well is enabled instead of trying to
11455          * follow the "don't touch the power well if we don't need it" policy
11456          * the rest of the driver uses. */
11457         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11458                 return;
11459
11460         i915_redisable_vga_power_on(dev);
11461 }
11462
11463 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11464 {
11465         struct drm_i915_private *dev_priv = dev->dev_private;
11466         enum pipe pipe;
11467         struct intel_crtc *crtc;
11468         struct intel_encoder *encoder;
11469         struct intel_connector *connector;
11470         int i;
11471
11472         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11473                             base.head) {
11474                 memset(&crtc->config, 0, sizeof(crtc->config));
11475
11476                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11477                                                                  &crtc->config);
11478
11479                 crtc->base.enabled = crtc->active;
11480                 crtc->primary_enabled = crtc->active;
11481
11482                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11483                               crtc->base.base.id,
11484                               crtc->active ? "enabled" : "disabled");
11485         }
11486
11487         /* FIXME: Smash this into the new shared dpll infrastructure. */
11488         if (HAS_DDI(dev))
11489                 intel_ddi_setup_hw_pll_state(dev);
11490
11491         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11492                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11493
11494                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11495                 pll->active = 0;
11496                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11497                                     base.head) {
11498                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11499                                 pll->active++;
11500                 }
11501                 pll->refcount = pll->active;
11502
11503                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11504                               pll->name, pll->refcount, pll->on);
11505         }
11506
11507         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11508                             base.head) {
11509                 pipe = 0;
11510
11511                 if (encoder->get_hw_state(encoder, &pipe)) {
11512                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11513                         encoder->base.crtc = &crtc->base;
11514                         encoder->get_config(encoder, &crtc->config);
11515                 } else {
11516                         encoder->base.crtc = NULL;
11517                 }
11518
11519                 encoder->connectors_active = false;
11520                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11521                               encoder->base.base.id,
11522                               drm_get_encoder_name(&encoder->base),
11523                               encoder->base.crtc ? "enabled" : "disabled",
11524                               pipe_name(pipe));
11525         }
11526
11527         list_for_each_entry(connector, &dev->mode_config.connector_list,
11528                             base.head) {
11529                 if (connector->get_hw_state(connector)) {
11530                         connector->base.dpms = DRM_MODE_DPMS_ON;
11531                         connector->encoder->connectors_active = true;
11532                         connector->base.encoder = &connector->encoder->base;
11533                 } else {
11534                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11535                         connector->base.encoder = NULL;
11536                 }
11537                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11538                               connector->base.base.id,
11539                               drm_get_connector_name(&connector->base),
11540                               connector->base.encoder ? "enabled" : "disabled");
11541         }
11542 }
11543
11544 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11545  * and i915 state tracking structures. */
11546 void intel_modeset_setup_hw_state(struct drm_device *dev,
11547                                   bool force_restore)
11548 {
11549         struct drm_i915_private *dev_priv = dev->dev_private;
11550         enum pipe pipe;
11551         struct intel_crtc *crtc;
11552         struct intel_encoder *encoder;
11553         int i;
11554
11555         intel_modeset_readout_hw_state(dev);
11556
11557         /*
11558          * Now that we have the config, copy it to each CRTC struct
11559          * Note that this could go away if we move to using crtc_config
11560          * checking everywhere.
11561          */
11562         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11563                             base.head) {
11564                 if (crtc->active && i915.fastboot) {
11565                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11566                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11567                                       crtc->base.base.id);
11568                         drm_mode_debug_printmodeline(&crtc->base.mode);
11569                 }
11570         }
11571
11572         /* HW state is read out, now we need to sanitize this mess. */
11573         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11574                             base.head) {
11575                 intel_sanitize_encoder(encoder);
11576         }
11577
11578         for_each_pipe(pipe) {
11579                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11580                 intel_sanitize_crtc(crtc);
11581                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11582         }
11583
11584         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11585                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11586
11587                 if (!pll->on || pll->active)
11588                         continue;
11589
11590                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11591
11592                 pll->disable(dev_priv, pll);
11593                 pll->on = false;
11594         }
11595
11596         if (HAS_PCH_SPLIT(dev))
11597                 ilk_wm_get_hw_state(dev);
11598
11599         if (force_restore) {
11600                 i915_redisable_vga(dev);
11601
11602                 /*
11603                  * We need to use raw interfaces for restoring state to avoid
11604                  * checking (bogus) intermediate states.
11605                  */
11606                 for_each_pipe(pipe) {
11607                         struct drm_crtc *crtc =
11608                                 dev_priv->pipe_to_crtc_mapping[pipe];
11609
11610                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11611                                          crtc->fb);
11612                 }
11613         } else {
11614                 intel_modeset_update_staged_output_state(dev);
11615         }
11616
11617         intel_modeset_check_state(dev);
11618 }
11619
11620 void intel_modeset_gem_init(struct drm_device *dev)
11621 {
11622         intel_modeset_init_hw(dev);
11623
11624         intel_setup_overlay(dev);
11625 }
11626
11627 void intel_connector_unregister(struct intel_connector *intel_connector)
11628 {
11629         struct drm_connector *connector = &intel_connector->base;
11630
11631         intel_panel_destroy_backlight(connector);
11632         drm_sysfs_connector_remove(connector);
11633 }
11634
11635 void intel_modeset_cleanup(struct drm_device *dev)
11636 {
11637         struct drm_i915_private *dev_priv = dev->dev_private;
11638         struct drm_crtc *crtc;
11639         struct drm_connector *connector;
11640
11641         /*
11642          * Interrupts and polling as the first thing to avoid creating havoc.
11643          * Too much stuff here (turning of rps, connectors, ...) would
11644          * experience fancy races otherwise.
11645          */
11646         drm_irq_uninstall(dev);
11647         cancel_work_sync(&dev_priv->hotplug_work);
11648         /*
11649          * Due to the hpd irq storm handling the hotplug work can re-arm the
11650          * poll handlers. Hence disable polling after hpd handling is shut down.
11651          */
11652         drm_kms_helper_poll_fini(dev);
11653
11654         mutex_lock(&dev->struct_mutex);
11655
11656         intel_unregister_dsm_handler();
11657
11658         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11659                 /* Skip inactive CRTCs */
11660                 if (!crtc->fb)
11661                         continue;
11662
11663                 intel_increase_pllclock(crtc);
11664         }
11665
11666         intel_disable_fbc(dev);
11667
11668         intel_disable_gt_powersave(dev);
11669
11670         ironlake_teardown_rc6(dev);
11671
11672         mutex_unlock(&dev->struct_mutex);
11673
11674         /* flush any delayed tasks or pending work */
11675         flush_scheduled_work();
11676
11677         /* destroy the backlight and sysfs files before encoders/connectors */
11678         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11679                 struct intel_connector *intel_connector;
11680
11681                 intel_connector = to_intel_connector(connector);
11682                 intel_connector->unregister(intel_connector);
11683         }
11684
11685         drm_mode_config_cleanup(dev);
11686
11687         intel_cleanup_overlay(dev);
11688 }
11689
11690 /*
11691  * Return which encoder is currently attached for connector.
11692  */
11693 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11694 {
11695         return &intel_attached_encoder(connector)->base;
11696 }
11697
11698 void intel_connector_attach_encoder(struct intel_connector *connector,
11699                                     struct intel_encoder *encoder)
11700 {
11701         connector->encoder = encoder;
11702         drm_mode_connector_attach_encoder(&connector->base,
11703                                           &encoder->base);
11704 }
11705
11706 /*
11707  * set vga decode state - true == enable VGA decode
11708  */
11709 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11710 {
11711         struct drm_i915_private *dev_priv = dev->dev_private;
11712         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11713         u16 gmch_ctrl;
11714
11715         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11716                 DRM_ERROR("failed to read control word\n");
11717                 return -EIO;
11718         }
11719
11720         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11721                 return 0;
11722
11723         if (state)
11724                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11725         else
11726                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11727
11728         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11729                 DRM_ERROR("failed to write control word\n");
11730                 return -EIO;
11731         }
11732
11733         return 0;
11734 }
11735
11736 struct intel_display_error_state {
11737
11738         u32 power_well_driver;
11739
11740         int num_transcoders;
11741
11742         struct intel_cursor_error_state {
11743                 u32 control;
11744                 u32 position;
11745                 u32 base;
11746                 u32 size;
11747         } cursor[I915_MAX_PIPES];
11748
11749         struct intel_pipe_error_state {
11750                 bool power_domain_on;
11751                 u32 source;
11752         } pipe[I915_MAX_PIPES];
11753
11754         struct intel_plane_error_state {
11755                 u32 control;
11756                 u32 stride;
11757                 u32 size;
11758                 u32 pos;
11759                 u32 addr;
11760                 u32 surface;
11761                 u32 tile_offset;
11762         } plane[I915_MAX_PIPES];
11763
11764         struct intel_transcoder_error_state {
11765                 bool power_domain_on;
11766                 enum transcoder cpu_transcoder;
11767
11768                 u32 conf;
11769
11770                 u32 htotal;
11771                 u32 hblank;
11772                 u32 hsync;
11773                 u32 vtotal;
11774                 u32 vblank;
11775                 u32 vsync;
11776         } transcoder[4];
11777 };
11778
11779 struct intel_display_error_state *
11780 intel_display_capture_error_state(struct drm_device *dev)
11781 {
11782         drm_i915_private_t *dev_priv = dev->dev_private;
11783         struct intel_display_error_state *error;
11784         int transcoders[] = {
11785                 TRANSCODER_A,
11786                 TRANSCODER_B,
11787                 TRANSCODER_C,
11788                 TRANSCODER_EDP,
11789         };
11790         int i;
11791
11792         if (INTEL_INFO(dev)->num_pipes == 0)
11793                 return NULL;
11794
11795         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11796         if (error == NULL)
11797                 return NULL;
11798
11799         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11800                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11801
11802         for_each_pipe(i) {
11803                 error->pipe[i].power_domain_on =
11804                         intel_display_power_enabled_sw(dev_priv,
11805                                                        POWER_DOMAIN_PIPE(i));
11806                 if (!error->pipe[i].power_domain_on)
11807                         continue;
11808
11809                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11810                         error->cursor[i].control = I915_READ(CURCNTR(i));
11811                         error->cursor[i].position = I915_READ(CURPOS(i));
11812                         error->cursor[i].base = I915_READ(CURBASE(i));
11813                 } else {
11814                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11815                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11816                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11817                 }
11818
11819                 error->plane[i].control = I915_READ(DSPCNTR(i));
11820                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11821                 if (INTEL_INFO(dev)->gen <= 3) {
11822                         error->plane[i].size = I915_READ(DSPSIZE(i));
11823                         error->plane[i].pos = I915_READ(DSPPOS(i));
11824                 }
11825                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11826                         error->plane[i].addr = I915_READ(DSPADDR(i));
11827                 if (INTEL_INFO(dev)->gen >= 4) {
11828                         error->plane[i].surface = I915_READ(DSPSURF(i));
11829                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11830                 }
11831
11832                 error->pipe[i].source = I915_READ(PIPESRC(i));
11833         }
11834
11835         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11836         if (HAS_DDI(dev_priv->dev))
11837                 error->num_transcoders++; /* Account for eDP. */
11838
11839         for (i = 0; i < error->num_transcoders; i++) {
11840                 enum transcoder cpu_transcoder = transcoders[i];
11841
11842                 error->transcoder[i].power_domain_on =
11843                         intel_display_power_enabled_sw(dev_priv,
11844                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11845                 if (!error->transcoder[i].power_domain_on)
11846                         continue;
11847
11848                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11849
11850                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11851                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11852                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11853                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11854                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11855                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11856                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11857         }
11858
11859         return error;
11860 }
11861
11862 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11863
11864 void
11865 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11866                                 struct drm_device *dev,
11867                                 struct intel_display_error_state *error)
11868 {
11869         int i;
11870
11871         if (!error)
11872                 return;
11873
11874         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11875         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11876                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11877                            error->power_well_driver);
11878         for_each_pipe(i) {
11879                 err_printf(m, "Pipe [%d]:\n", i);
11880                 err_printf(m, "  Power: %s\n",
11881                            error->pipe[i].power_domain_on ? "on" : "off");
11882                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11883
11884                 err_printf(m, "Plane [%d]:\n", i);
11885                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11886                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11887                 if (INTEL_INFO(dev)->gen <= 3) {
11888                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11889                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11890                 }
11891                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11892                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11893                 if (INTEL_INFO(dev)->gen >= 4) {
11894                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11895                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11896                 }
11897
11898                 err_printf(m, "Cursor [%d]:\n", i);
11899                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11900                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11901                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11902         }
11903
11904         for (i = 0; i < error->num_transcoders; i++) {
11905                 err_printf(m, "CPU transcoder: %c\n",
11906                            transcoder_name(error->transcoder[i].cpu_transcoder));
11907                 err_printf(m, "  Power: %s\n",
11908                            error->transcoder[i].power_domain_on ? "on" : "off");
11909                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11910                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11911                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11912                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11913                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11914                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11915                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11916         }
11917 }