2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54 static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
68 typedef struct intel_limit intel_limit_t;
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_pch_rawclk(struct drm_device *dev)
77 struct drm_i915_private *dev_priv = dev->dev_private;
79 WARN_ON(!HAS_PCH_SPLIT(dev));
81 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
84 static inline u32 /* units of 100MHz */
85 intel_fdi_link_freq(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
94 static const intel_limit_t intel_limits_i8xx_dac = {
95 .dot = { .min = 25000, .max = 350000 },
96 .vco = { .min = 908000, .max = 1512000 },
97 .n = { .min = 2, .max = 16 },
98 .m = { .min = 96, .max = 140 },
99 .m1 = { .min = 18, .max = 26 },
100 .m2 = { .min = 6, .max = 16 },
101 .p = { .min = 4, .max = 128 },
102 .p1 = { .min = 2, .max = 33 },
103 .p2 = { .dot_limit = 165000,
104 .p2_slow = 4, .p2_fast = 2 },
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 908000, .max = 1512000 },
110 .n = { .min = 2, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 4 },
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 908000, .max = 1512000 },
123 .n = { .min = 2, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134 .dot = { .min = 20000, .max = 400000 },
135 .vco = { .min = 1400000, .max = 2800000 },
136 .n = { .min = 1, .max = 6 },
137 .m = { .min = 70, .max = 120 },
138 .m1 = { .min = 8, .max = 18 },
139 .m2 = { .min = 3, .max = 7 },
140 .p = { .min = 5, .max = 80 },
141 .p1 = { .min = 1, .max = 8 },
142 .p2 = { .dot_limit = 200000,
143 .p2_slow = 10, .p2_fast = 5 },
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 7, .max = 98 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 112000,
156 .p2_slow = 14, .p2_fast = 7 },
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161 .dot = { .min = 25000, .max = 270000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 17, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 10, .max = 30 },
168 .p1 = { .min = 1, .max = 3},
169 .p2 = { .dot_limit = 270000,
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176 .dot = { .min = 22000, .max = 400000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 16, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 5, .max = 80 },
183 .p1 = { .min = 1, .max = 8},
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 10, .p2_fast = 5 },
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189 .dot = { .min = 20000, .max = 115000 },
190 .vco = { .min = 1750000, .max = 3500000 },
191 .n = { .min = 1, .max = 3 },
192 .m = { .min = 104, .max = 138 },
193 .m1 = { .min = 17, .max = 23 },
194 .m2 = { .min = 5, .max = 11 },
195 .p = { .min = 28, .max = 112 },
196 .p1 = { .min = 2, .max = 8 },
197 .p2 = { .dot_limit = 0,
198 .p2_slow = 14, .p2_fast = 14
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203 .dot = { .min = 80000, .max = 224000 },
204 .vco = { .min = 1750000, .max = 3500000 },
205 .n = { .min = 1, .max = 3 },
206 .m = { .min = 104, .max = 138 },
207 .m1 = { .min = 17, .max = 23 },
208 .m2 = { .min = 5, .max = 11 },
209 .p = { .min = 14, .max = 42 },
210 .p1 = { .min = 2, .max = 6 },
211 .p2 = { .dot_limit = 0,
212 .p2_slow = 7, .p2_fast = 7
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217 .dot = { .min = 20000, .max = 400000},
218 .vco = { .min = 1700000, .max = 3500000 },
219 /* Pineview's Ncounter is a ring counter */
220 .n = { .min = 3, .max = 6 },
221 .m = { .min = 2, .max = 256 },
222 /* Pineview only has one combined m divider, which we treat as m2. */
223 .m1 = { .min = 0, .max = 0 },
224 .m2 = { .min = 0, .max = 254 },
225 .p = { .min = 5, .max = 80 },
226 .p1 = { .min = 1, .max = 8 },
227 .p2 = { .dot_limit = 200000,
228 .p2_slow = 10, .p2_fast = 5 },
231 static const intel_limit_t intel_limits_pineview_lvds = {
232 .dot = { .min = 20000, .max = 400000 },
233 .vco = { .min = 1700000, .max = 3500000 },
234 .n = { .min = 3, .max = 6 },
235 .m = { .min = 2, .max = 256 },
236 .m1 = { .min = 0, .max = 0 },
237 .m2 = { .min = 0, .max = 254 },
238 .p = { .min = 7, .max = 112 },
239 .p1 = { .min = 1, .max = 8 },
240 .p2 = { .dot_limit = 112000,
241 .p2_slow = 14, .p2_fast = 14 },
244 /* Ironlake / Sandybridge
246 * We calculate clock using (register_value + 2) for N/M1/M2, so here
247 * the range value for them is (actual_value - 2).
249 static const intel_limit_t intel_limits_ironlake_dac = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 1760000, .max = 3510000 },
252 .n = { .min = 1, .max = 5 },
253 .m = { .min = 79, .max = 127 },
254 .m1 = { .min = 12, .max = 22 },
255 .m2 = { .min = 5, .max = 9 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 225000,
259 .p2_slow = 10, .p2_fast = 5 },
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 1760000, .max = 3510000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 79, .max = 118 },
267 .m1 = { .min = 12, .max = 22 },
268 .m2 = { .min = 5, .max = 9 },
269 .p = { .min = 28, .max = 112 },
270 .p1 = { .min = 2, .max = 8 },
271 .p2 = { .dot_limit = 225000,
272 .p2_slow = 14, .p2_fast = 14 },
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 14, .max = 56 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 7, .p2_fast = 7 },
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 2 },
293 .m = { .min = 79, .max = 126 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 126 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 42 },
310 .p1 = { .min = 2, .max = 6 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
315 static const intel_limit_t intel_limits_vlv = {
317 * These are the data rate limits (measured in fast clocks)
318 * since those are the strictest limits we have. The fast
319 * clock and actual rate limits are more relaxed, so checking
320 * them would make no difference.
322 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m1 = { .min = 2, .max = 3 },
326 .m2 = { .min = 11, .max = 156 },
327 .p1 = { .min = 2, .max = 3 },
328 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
331 static void vlv_clock(int refclk, intel_clock_t *clock)
333 clock->m = clock->m1 * clock->m2;
334 clock->p = clock->p1 * clock->p2;
335 if (WARN_ON(clock->n == 0 || clock->p == 0))
337 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
342 * Returns whether any output on the specified pipe is of the specified type
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
346 struct drm_device *dev = crtc->dev;
347 struct intel_encoder *encoder;
349 for_each_encoder_on_crtc(dev, crtc, encoder)
350 if (encoder->type == type)
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 struct drm_device *dev = crtc->dev;
360 const intel_limit_t *limit;
362 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363 if (intel_is_dual_link_lvds(dev)) {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_dual_lvds_100m;
367 limit = &intel_limits_ironlake_dual_lvds;
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_single_lvds_100m;
372 limit = &intel_limits_ironlake_single_lvds;
375 limit = &intel_limits_ironlake_dac;
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
382 struct drm_device *dev = crtc->dev;
383 const intel_limit_t *limit;
385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386 if (intel_is_dual_link_lvds(dev))
387 limit = &intel_limits_g4x_dual_channel_lvds;
389 limit = &intel_limits_g4x_single_channel_lvds;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392 limit = &intel_limits_g4x_hdmi;
393 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394 limit = &intel_limits_g4x_sdvo;
395 } else /* The option is for other outputs */
396 limit = &intel_limits_i9xx_sdvo;
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
403 struct drm_device *dev = crtc->dev;
404 const intel_limit_t *limit;
406 if (HAS_PCH_SPLIT(dev))
407 limit = intel_ironlake_limit(crtc, refclk);
408 else if (IS_G4X(dev)) {
409 limit = intel_g4x_limit(crtc);
410 } else if (IS_PINEVIEW(dev)) {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_pineview_lvds;
414 limit = &intel_limits_pineview_sdvo;
415 } else if (IS_VALLEYVIEW(dev)) {
416 limit = &intel_limits_vlv;
417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
421 limit = &intel_limits_i9xx_sdvo;
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424 limit = &intel_limits_i8xx_lvds;
425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426 limit = &intel_limits_i8xx_dvo;
428 limit = &intel_limits_i8xx_dac;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 if (WARN_ON(clock->n == 0 || clock->p == 0))
440 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
446 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
451 clock->m = i9xx_dpll_compute_m(clock);
452 clock->p = clock->p1 * clock->p2;
453 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
455 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
459 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
469 if (clock->n < limit->n.min || limit->n.max < clock->n)
470 INTELPllInvalid("n out of range\n");
471 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
472 INTELPllInvalid("p1 out of range\n");
473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
474 INTELPllInvalid("m2 out of range\n");
475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
476 INTELPllInvalid("m1 out of range\n");
478 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479 if (clock->m1 <= clock->m2)
480 INTELPllInvalid("m1 <= m2\n");
482 if (!IS_VALLEYVIEW(dev)) {
483 if (clock->p < limit->p.min || limit->p.max < clock->p)
484 INTELPllInvalid("p out of range\n");
485 if (clock->m < limit->m.min || limit->m.max < clock->m)
486 INTELPllInvalid("m out of range\n");
489 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490 INTELPllInvalid("vco out of range\n");
491 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492 * connector, etc., rather than just a single range.
494 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495 INTELPllInvalid("dot out of range\n");
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502 int target, int refclk, intel_clock_t *match_clock,
503 intel_clock_t *best_clock)
505 struct drm_device *dev = crtc->dev;
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
511 * For LVDS just rely on its current settings for dual-channel.
512 * We haven't figured out how to reliably set up different
513 * single/dual channel state, if we even can.
515 if (intel_is_dual_link_lvds(dev))
516 clock.p2 = limit->p2.p2_fast;
518 clock.p2 = limit->p2.p2_slow;
520 if (target < limit->p2.dot_limit)
521 clock.p2 = limit->p2.p2_slow;
523 clock.p2 = limit->p2.p2_fast;
526 memset(best_clock, 0, sizeof(*best_clock));
528 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
530 for (clock.m2 = limit->m2.min;
531 clock.m2 <= limit->m2.max; clock.m2++) {
532 if (clock.m2 >= clock.m1)
534 for (clock.n = limit->n.min;
535 clock.n <= limit->n.max; clock.n++) {
536 for (clock.p1 = limit->p1.min;
537 clock.p1 <= limit->p1.max; clock.p1++) {
540 i9xx_clock(refclk, &clock);
541 if (!intel_PLL_is_valid(dev, limit,
545 clock.p != match_clock->p)
548 this_err = abs(clock.dot - target);
549 if (this_err < err) {
558 return (err != target);
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563 int target, int refclk, intel_clock_t *match_clock,
564 intel_clock_t *best_clock)
566 struct drm_device *dev = crtc->dev;
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
572 * For LVDS just rely on its current settings for dual-channel.
573 * We haven't figured out how to reliably set up different
574 * single/dual channel state, if we even can.
576 if (intel_is_dual_link_lvds(dev))
577 clock.p2 = limit->p2.p2_fast;
579 clock.p2 = limit->p2.p2_slow;
581 if (target < limit->p2.dot_limit)
582 clock.p2 = limit->p2.p2_slow;
584 clock.p2 = limit->p2.p2_fast;
587 memset(best_clock, 0, sizeof(*best_clock));
589 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
591 for (clock.m2 = limit->m2.min;
592 clock.m2 <= limit->m2.max; clock.m2++) {
593 for (clock.n = limit->n.min;
594 clock.n <= limit->n.max; clock.n++) {
595 for (clock.p1 = limit->p1.min;
596 clock.p1 <= limit->p1.max; clock.p1++) {
599 pineview_clock(refclk, &clock);
600 if (!intel_PLL_is_valid(dev, limit,
604 clock.p != match_clock->p)
607 this_err = abs(clock.dot - target);
608 if (this_err < err) {
617 return (err != target);
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622 int target, int refclk, intel_clock_t *match_clock,
623 intel_clock_t *best_clock)
625 struct drm_device *dev = crtc->dev;
629 /* approximately equals target * 0.00585 */
630 int err_most = (target >> 8) + (target >> 9);
633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634 if (intel_is_dual_link_lvds(dev))
635 clock.p2 = limit->p2.p2_fast;
637 clock.p2 = limit->p2.p2_slow;
639 if (target < limit->p2.dot_limit)
640 clock.p2 = limit->p2.p2_slow;
642 clock.p2 = limit->p2.p2_fast;
645 memset(best_clock, 0, sizeof(*best_clock));
646 max_n = limit->n.max;
647 /* based on hardware requirement, prefer smaller n to precision */
648 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649 /* based on hardware requirement, prefere larger m1,m2 */
650 for (clock.m1 = limit->m1.max;
651 clock.m1 >= limit->m1.min; clock.m1--) {
652 for (clock.m2 = limit->m2.max;
653 clock.m2 >= limit->m2.min; clock.m2--) {
654 for (clock.p1 = limit->p1.max;
655 clock.p1 >= limit->p1.min; clock.p1--) {
658 i9xx_clock(refclk, &clock);
659 if (!intel_PLL_is_valid(dev, limit,
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
682 struct drm_device *dev = crtc->dev;
684 unsigned int bestppm = 1000000;
685 /* min update 19.2 MHz */
686 int max_n = min(limit->n.max, refclk / 19200);
689 target *= 5; /* fast clock */
691 memset(best_clock, 0, sizeof(*best_clock));
693 /* based on hardware requirement, prefer smaller n to precision */
694 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698 clock.p = clock.p1 * clock.p2;
699 /* based on hardware requirement, prefer bigger m1,m2 values */
700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701 unsigned int ppm, diff;
703 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
706 vlv_clock(refclk, &clock);
708 if (!intel_PLL_is_valid(dev, limit,
712 diff = abs(clock.dot - target);
713 ppm = div_u64(1000000ULL * diff, target);
715 if (ppm < 100 && clock.p > best_clock->p) {
721 if (bestppm >= 10 && ppm < bestppm - 10) {
734 bool intel_crtc_active(struct drm_crtc *crtc)
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738 /* Be paranoid as we can arrive here with only partial
739 * state retrieved from the hardware during setup.
741 * We can ditch the adjusted_mode.crtc_clock check as soon
742 * as Haswell has gained clock readout/fastboot support.
744 * We can ditch the crtc->primary->fb check as soon as we can
745 * properly reconstruct framebuffers.
747 return intel_crtc->active && crtc->primary->fb &&
748 intel_crtc->config.adjusted_mode.crtc_clock;
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757 return intel_crtc->config.cpu_transcoder;
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
765 frame = I915_READ(frame_reg);
767 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768 WARN(1, "vblank wait timed out\n");
772 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @pipe: pipe to wait for
776 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 int pipestat_reg = PIPESTAT(pipe);
784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 g4x_wait_for_vblank(dev, pipe);
789 /* Clear existing vblank status. Note this will clear any other
790 * sticky status fields as well.
792 * This races with i915_driver_irq_handler() with the result
793 * that either function could miss a vblank event. Here it is not
794 * fatal, as we will either wait upon the next vblank interrupt or
795 * timeout. Generally speaking intel_wait_for_vblank() is only
796 * called during modeset at which time the GPU should be idle and
797 * should *not* be performing page flips and thus not waiting on
799 * Currently, the result of us stealing a vblank from the irq
800 * handler is that a single frame will be skipped during swapbuffers.
802 I915_WRITE(pipestat_reg,
803 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805 /* Wait for vblank interrupt bit to set */
806 if (wait_for(I915_READ(pipestat_reg) &
807 PIPE_VBLANK_INTERRUPT_STATUS,
809 DRM_DEBUG_KMS("vblank wait timed out\n");
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 reg = PIPEDSL(pipe);
820 line_mask = DSL_LINEMASK_GEN2;
822 line_mask = DSL_LINEMASK_GEN3;
824 line1 = I915_READ(reg) & line_mask;
826 line2 = I915_READ(reg) & line_mask;
828 return line1 == line2;
832 * intel_wait_for_pipe_off - wait for pipe to turn off
834 * @pipe: pipe to wait for
836 * After disabling a pipe, we can't wait for vblank in the usual way,
837 * spinning on the vblank interrupt status bit, since we won't actually
838 * see an interrupt when the pipe is disabled.
841 * wait for the pipe register state bit to turn off
844 * wait for the display line value to settle (it usually
845 * ends up stopping at the start of the next frame).
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 if (INTEL_INFO(dev)->gen >= 4) {
855 int reg = PIPECONF(cpu_transcoder);
857 /* Wait for the Pipe State to go off */
858 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
860 WARN(1, "pipe_off wait timed out\n");
862 /* Wait for the display line to settle */
863 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864 WARN(1, "pipe_off wait timed out\n");
869 * ibx_digital_port_connected - is the specified port connected?
870 * @dev_priv: i915 private structure
871 * @port: the port to test
873 * Returns true if @port is connected, false otherwise.
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876 struct intel_digital_port *port)
880 if (HAS_PCH_IBX(dev_priv->dev)) {
883 bit = SDE_PORTB_HOTPLUG;
886 bit = SDE_PORTC_HOTPLUG;
889 bit = SDE_PORTD_HOTPLUG;
897 bit = SDE_PORTB_HOTPLUG_CPT;
900 bit = SDE_PORTC_HOTPLUG_CPT;
903 bit = SDE_PORTD_HOTPLUG_CPT;
910 return I915_READ(SDEISR) & bit;
913 static const char *state_string(bool enabled)
915 return enabled ? "on" : "off";
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool state)
927 val = I915_READ(reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PLL state assertion failure (expected %s, current %s)\n",
931 state_string(state), state_string(cur_state));
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
940 mutex_lock(&dev_priv->dpio_lock);
941 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942 mutex_unlock(&dev_priv->dpio_lock);
944 cur_state = val & DSI_PLL_VCO_EN;
945 WARN(cur_state != state,
946 "DSI PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
957 if (crtc->config.shared_dpll < 0)
960 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965 struct intel_shared_dpll *pll,
969 struct intel_dpll_hw_state hw_state;
971 if (HAS_PCH_LPT(dev_priv->dev)) {
972 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
977 "asserting DPLL %s with no DPLL\n", state_string(state)))
980 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981 WARN(cur_state != state,
982 "%s assertion failure (expected %s, current %s)\n",
983 pll->name, state_string(state), state_string(cur_state));
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987 enum pipe pipe, bool state)
992 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
995 if (HAS_DDI(dev_priv->dev)) {
996 /* DDI does not have a specific FDI_TX register */
997 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998 val = I915_READ(reg);
999 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 cur_state = !!(val & FDI_TX_ENABLE);
1005 WARN(cur_state != state,
1006 "FDI TX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1019 reg = FDI_RX_CTL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & FDI_RX_ENABLE);
1022 WARN(cur_state != state,
1023 "FDI RX state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1035 /* ILK FDI PLL is always enabled */
1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040 if (HAS_DDI(dev_priv->dev))
1043 reg = FDI_TX_CTL(pipe);
1044 val = I915_READ(reg);
1045 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1055 reg = FDI_RX_CTL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058 WARN(cur_state != state,
1059 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 int pp_reg, lvds_reg;
1068 enum pipe panel_pipe = PIPE_A;
1071 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072 pp_reg = PCH_PP_CONTROL;
1073 lvds_reg = PCH_LVDS;
1075 pp_reg = PP_CONTROL;
1079 val = I915_READ(pp_reg);
1080 if (!(val & PANEL_POWER_ON) ||
1081 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085 panel_pipe = PIPE_B;
1087 WARN(panel_pipe == pipe && locked,
1088 "panel assertion failure, pipe %c regs locked\n",
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1095 struct drm_device *dev = dev_priv->dev;
1098 if (IS_845G(dev) || IS_I865G(dev))
1099 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1103 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1105 WARN(cur_state != state,
1106 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107 pipe_name(pipe), state_string(state), state_string(cur_state));
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1121 /* if we need the pipe A quirk it must be always on */
1122 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1125 if (!intel_display_power_enabled(dev_priv,
1126 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1129 reg = PIPECONF(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & PIPECONF_ENABLE);
1134 WARN(cur_state != state,
1135 "pipe %c assertion failure (expected %s, current %s)\n",
1136 pipe_name(pipe), state_string(state), state_string(cur_state));
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140 enum plane plane, bool state)
1146 reg = DSPCNTR(plane);
1147 val = I915_READ(reg);
1148 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149 WARN(cur_state != state,
1150 "plane %c assertion failure (expected %s, current %s)\n",
1151 plane_name(plane), state_string(state), state_string(cur_state));
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1160 struct drm_device *dev = dev_priv->dev;
1165 /* Primary planes are fixed to pipes on gen4+ */
1166 if (INTEL_INFO(dev)->gen >= 4) {
1167 reg = DSPCNTR(pipe);
1168 val = I915_READ(reg);
1169 WARN(val & DISPLAY_PLANE_ENABLE,
1170 "plane %c assertion failure, should be disabled but not\n",
1175 /* Need to check both planes against the pipe */
1178 val = I915_READ(reg);
1179 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180 DISPPLANE_SEL_PIPE_SHIFT;
1181 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183 plane_name(i), pipe_name(pipe));
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1190 struct drm_device *dev = dev_priv->dev;
1194 if (IS_VALLEYVIEW(dev)) {
1195 for_each_sprite(pipe, sprite) {
1196 reg = SPCNTR(pipe, sprite);
1197 val = I915_READ(reg);
1198 WARN(val & SP_ENABLE,
1199 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200 sprite_name(pipe, sprite), pipe_name(pipe));
1202 } else if (INTEL_INFO(dev)->gen >= 7) {
1204 val = I915_READ(reg);
1205 WARN(val & SPRITE_ENABLE,
1206 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207 plane_name(pipe), pipe_name(pipe));
1208 } else if (INTEL_INFO(dev)->gen >= 5) {
1209 reg = DVSCNTR(pipe);
1210 val = I915_READ(reg);
1211 WARN(val & DVS_ENABLE,
1212 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213 plane_name(pipe), pipe_name(pipe));
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1222 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void intel_init_dpio(struct drm_device *dev)
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1367 if (!IS_VALLEYVIEW(dev))
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1373 static void intel_reset_dpio(struct drm_device *dev)
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1377 if (!IS_VALLEYVIEW(dev))
1381 * Enable the CRI clock source so we can get at the display and the
1382 * reference clock for VGA hotplug / manual detection.
1384 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385 DPLL_REFA_CLK_ENABLE_VLV |
1386 DPLL_INTEGRATED_CRI_CLK_VLV);
1389 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1391 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392 * b. The other bits such as sfr settings / modesel may all be set
1395 * This should only be done on init and resume from S3 with both
1396 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1398 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1410 /* No really, not for ILK+ */
1411 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1417 I915_WRITE(reg, dpll);
1421 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1424 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425 POSTING_READ(DPLL_MD(crtc->pipe));
1427 /* We do this three times for luck */
1428 I915_WRITE(reg, dpll);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1433 udelay(150); /* wait for warmup */
1434 I915_WRITE(reg, dpll);
1436 udelay(150); /* wait for warmup */
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1441 struct drm_device *dev = crtc->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int reg = DPLL(crtc->pipe);
1444 u32 dpll = crtc->config.dpll_hw_state.dpll;
1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1448 /* No really, not for ILK+ */
1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev) && !IS_I830(dev))
1453 assert_panel_unlocked(dev_priv, crtc->pipe);
1455 I915_WRITE(reg, dpll);
1457 /* Wait for the clocks to stabilize. */
1461 if (INTEL_INFO(dev)->gen >= 4) {
1462 I915_WRITE(DPLL_MD(crtc->pipe),
1463 crtc->config.dpll_hw_state.dpll_md);
1465 /* The pixel multiplier can only be updated once the
1466 * DPLL is enabled and the clocks are stable.
1468 * So write it again.
1470 I915_WRITE(reg, dpll);
1473 /* We do this three times for luck */
1474 I915_WRITE(reg, dpll);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, dpll);
1482 udelay(150); /* wait for warmup */
1486 * i9xx_disable_pll - disable a PLL
1487 * @dev_priv: i915 private structure
1488 * @pipe: pipe PLL to disable
1490 * Disable the PLL for @pipe, making sure the pipe is off first.
1492 * Note! This is for pre-ILK only.
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1496 /* Don't disable pipe A or pipe A PLLs if needed */
1497 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1500 /* Make sure the pipe isn't still relying on us */
1501 assert_pipe_disabled(dev_priv, pipe);
1503 I915_WRITE(DPLL(pipe), 0);
1504 POSTING_READ(DPLL(pipe));
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1511 /* Make sure the pipe isn't still relying on us */
1512 assert_pipe_disabled(dev_priv, pipe);
1515 * Leave integrated clock source and reference clock enabled for pipe B.
1516 * The latter is needed for VGA hotplug / manual detection.
1519 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520 I915_WRITE(DPLL(pipe), val);
1521 POSTING_READ(DPLL(pipe));
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525 struct intel_digital_port *dport)
1529 switch (dport->port) {
1531 port_mask = DPLL_PORTB_READY_MASK;
1534 port_mask = DPLL_PORTC_READY_MASK;
1540 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542 port_name(dport->port), I915_READ(DPLL(0)));
1546 * ironlake_enable_shared_dpll - enable PCH PLL
1547 * @dev_priv: i915 private structure
1548 * @pipe: pipe PLL to enable
1550 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551 * drives the transcoder clock.
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1559 /* PCH PLLs only available on ILK, SNB and IVB */
1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1561 if (WARN_ON(pll == NULL))
1564 if (WARN_ON(pll->refcount == 0))
1567 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568 pll->name, pll->active, pll->on,
1569 crtc->base.base.id);
1571 if (pll->active++) {
1573 assert_shared_dpll_enabled(dev_priv, pll);
1578 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579 pll->enable(dev_priv, pll);
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1589 /* PCH only available on ILK+ */
1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1591 if (WARN_ON(pll == NULL))
1594 if (WARN_ON(pll->refcount == 0))
1597 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598 pll->name, pll->active, pll->on,
1599 crtc->base.base.id);
1601 if (WARN_ON(pll->active == 0)) {
1602 assert_shared_dpll_disabled(dev_priv, pll);
1606 assert_shared_dpll_enabled(dev_priv, pll);
1611 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612 pll->disable(dev_priv, pll);
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1619 struct drm_device *dev = dev_priv->dev;
1620 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622 uint32_t reg, val, pipeconf_val;
1624 /* PCH only available on ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1627 /* Make sure PCH DPLL is enabled */
1628 assert_shared_dpll_enabled(dev_priv,
1629 intel_crtc_to_shared_dpll(intel_crtc));
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1635 if (HAS_PCH_CPT(dev)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1648 if (HAS_PCH_IBX(dev_priv->dev)) {
1650 * make the BPC in transcoder be consistent with
1651 * that in pipeconf reg.
1653 val &= ~PIPECONF_BPC_MASK;
1654 val |= pipeconf_val & PIPECONF_BPC_MASK;
1657 val &= ~TRANS_INTERLACE_MASK;
1658 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659 if (HAS_PCH_IBX(dev_priv->dev) &&
1660 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661 val |= TRANS_LEGACY_INTERLACED_ILK;
1663 val |= TRANS_INTERLACED;
1665 val |= TRANS_PROGRESSIVE;
1667 I915_WRITE(reg, val | TRANS_ENABLE);
1668 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673 enum transcoder cpu_transcoder)
1675 u32 val, pipeconf_val;
1677 /* PCH only available on ILK+ */
1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1684 /* Workaround: set timing override bit. */
1685 val = I915_READ(_TRANSA_CHICKEN2);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(_TRANSA_CHICKEN2, val);
1690 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1692 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693 PIPECONF_INTERLACED_ILK)
1694 val |= TRANS_INTERLACED;
1696 val |= TRANS_PROGRESSIVE;
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700 DRM_ERROR("Failed to enable PCH transcoder\n");
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1706 struct drm_device *dev = dev_priv->dev;
1709 /* FDI relies on the transcoder */
1710 assert_fdi_tx_disabled(dev_priv, pipe);
1711 assert_fdi_rx_disabled(dev_priv, pipe);
1713 /* Ports must be off as well */
1714 assert_pch_ports_disabled(dev_priv, pipe);
1716 reg = PCH_TRANSCONF(pipe);
1717 val = I915_READ(reg);
1718 val &= ~TRANS_ENABLE;
1719 I915_WRITE(reg, val);
1720 /* wait for PCH transcoder off, transcoder state */
1721 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1724 if (!HAS_PCH_IBX(dev)) {
1725 /* Workaround: Clear the timing override chicken bit again. */
1726 reg = TRANS_CHICKEN2(pipe);
1727 val = I915_READ(reg);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(reg, val);
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1737 val = I915_READ(LPT_TRANSCONF);
1738 val &= ~TRANS_ENABLE;
1739 I915_WRITE(LPT_TRANSCONF, val);
1740 /* wait for PCH transcoder off, transcoder state */
1741 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742 DRM_ERROR("Failed to disable PCH transcoder\n");
1744 /* Workaround: clear timing override bit. */
1745 val = I915_READ(_TRANSA_CHICKEN2);
1746 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747 I915_WRITE(_TRANSA_CHICKEN2, val);
1751 * intel_enable_pipe - enable a pipe, asserting requirements
1752 * @crtc: crtc responsible for the pipe
1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 enum pipe pch_transcoder;
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1775 pch_transcoder = pipe;
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv);
1786 assert_pll_enabled(dev_priv, pipe);
1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1794 /* FIXME: assert CPU port conditions for SNB+ */
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1810 * intel_disable_pipe - disable a pipe, asserting requirements
1811 * @dev_priv: i915 private structure
1812 * @pipe: pipe to disable
1814 * Disable @pipe, making sure that various hardware specific requirements
1815 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1817 * @pipe should be %PIPE_A or %PIPE_B.
1819 * Will wait until the pipe has shut down before returning.
1821 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1824 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1830 * Make sure planes won't keep trying to pump pixels to us,
1831 * or we might hang the display.
1833 assert_planes_disabled(dev_priv, pipe);
1834 assert_cursor_disabled(dev_priv, pipe);
1835 assert_sprites_disabled(dev_priv, pipe);
1837 /* Don't disable pipe A or pipe A PLLs if needed */
1838 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1841 reg = PIPECONF(cpu_transcoder);
1842 val = I915_READ(reg);
1843 if ((val & PIPECONF_ENABLE) == 0)
1846 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1847 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1851 * Plane regs are double buffered, going from enabled->disabled needs a
1852 * trigger in order to latch. The display address reg provides this.
1854 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1857 struct drm_device *dev = dev_priv->dev;
1858 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1860 I915_WRITE(reg, I915_READ(reg));
1865 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1866 * @dev_priv: i915 private structure
1867 * @plane: plane to enable
1868 * @pipe: pipe being fed
1870 * Enable @plane on @pipe, making sure that @pipe is running first.
1872 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1873 enum plane plane, enum pipe pipe)
1875 struct intel_crtc *intel_crtc =
1876 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1880 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1881 assert_pipe_enabled(dev_priv, pipe);
1883 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1885 intel_crtc->primary_enabled = true;
1887 reg = DSPCNTR(plane);
1888 val = I915_READ(reg);
1889 if (val & DISPLAY_PLANE_ENABLE)
1892 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1893 intel_flush_primary_plane(dev_priv, plane);
1894 intel_wait_for_vblank(dev_priv->dev, pipe);
1898 * intel_disable_primary_hw_plane - disable the primary hardware plane
1899 * @dev_priv: i915 private structure
1900 * @plane: plane to disable
1901 * @pipe: pipe consuming the data
1903 * Disable @plane; should be an independent operation.
1905 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1906 enum plane plane, enum pipe pipe)
1908 struct intel_crtc *intel_crtc =
1909 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1913 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1915 intel_crtc->primary_enabled = false;
1917 reg = DSPCNTR(plane);
1918 val = I915_READ(reg);
1919 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1922 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1923 intel_flush_primary_plane(dev_priv, plane);
1924 intel_wait_for_vblank(dev_priv->dev, pipe);
1927 static bool need_vtd_wa(struct drm_device *dev)
1929 #ifdef CONFIG_INTEL_IOMMU
1930 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1936 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1940 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1941 return ALIGN(height, tile_height);
1945 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1946 struct drm_i915_gem_object *obj,
1947 struct intel_ring_buffer *pipelined)
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1953 switch (obj->tiling_mode) {
1954 case I915_TILING_NONE:
1955 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1956 alignment = 128 * 1024;
1957 else if (INTEL_INFO(dev)->gen >= 4)
1958 alignment = 4 * 1024;
1960 alignment = 64 * 1024;
1963 /* pin() will align the object as required by fence */
1967 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1973 /* Note that the w/a also requires 64 PTE of padding following the
1974 * bo. We currently fill all unused PTE with the shadow page and so
1975 * we should always have valid PTE following the scanout preventing
1978 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1979 alignment = 256 * 1024;
1981 dev_priv->mm.interruptible = false;
1982 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1984 goto err_interruptible;
1986 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1987 * fence, whereas 965+ only requires a fence if using
1988 * framebuffer compression. For simplicity, we always install
1989 * a fence as the cost is not that onerous.
1991 ret = i915_gem_object_get_fence(obj);
1995 i915_gem_object_pin_fence(obj);
1997 dev_priv->mm.interruptible = true;
2001 i915_gem_object_unpin_from_display_plane(obj);
2003 dev_priv->mm.interruptible = true;
2007 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009 i915_gem_object_unpin_fence(obj);
2010 i915_gem_object_unpin_from_display_plane(obj);
2013 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2014 * is assumed to be a power-of-two. */
2015 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2016 unsigned int tiling_mode,
2020 if (tiling_mode != I915_TILING_NONE) {
2021 unsigned int tile_rows, tiles;
2026 tiles = *x / (512/cpp);
2029 return tile_rows * pitch * 8 + tiles * 4096;
2031 unsigned int offset;
2033 offset = *y * pitch + *x * cpp;
2035 *x = (offset & 4095) / cpp;
2036 return offset & -4096;
2040 int intel_format_to_fourcc(int format)
2043 case DISPPLANE_8BPP:
2044 return DRM_FORMAT_C8;
2045 case DISPPLANE_BGRX555:
2046 return DRM_FORMAT_XRGB1555;
2047 case DISPPLANE_BGRX565:
2048 return DRM_FORMAT_RGB565;
2050 case DISPPLANE_BGRX888:
2051 return DRM_FORMAT_XRGB8888;
2052 case DISPPLANE_RGBX888:
2053 return DRM_FORMAT_XBGR8888;
2054 case DISPPLANE_BGRX101010:
2055 return DRM_FORMAT_XRGB2101010;
2056 case DISPPLANE_RGBX101010:
2057 return DRM_FORMAT_XBGR2101010;
2061 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2062 struct intel_plane_config *plane_config)
2064 struct drm_device *dev = crtc->base.dev;
2065 struct drm_i915_gem_object *obj = NULL;
2066 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2067 u32 base = plane_config->base;
2069 if (plane_config->size == 0)
2072 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2073 plane_config->size);
2077 if (plane_config->tiled) {
2078 obj->tiling_mode = I915_TILING_X;
2079 obj->stride = crtc->base.primary->fb->pitches[0];
2082 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2083 mode_cmd.width = crtc->base.primary->fb->width;
2084 mode_cmd.height = crtc->base.primary->fb->height;
2085 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2087 mutex_lock(&dev->struct_mutex);
2089 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2091 DRM_DEBUG_KMS("intel fb init failed\n");
2095 mutex_unlock(&dev->struct_mutex);
2097 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2101 drm_gem_object_unreference(&obj->base);
2102 mutex_unlock(&dev->struct_mutex);
2106 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2107 struct intel_plane_config *plane_config)
2109 struct drm_device *dev = intel_crtc->base.dev;
2111 struct intel_crtc *i;
2112 struct intel_framebuffer *fb;
2114 if (!intel_crtc->base.primary->fb)
2117 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2120 kfree(intel_crtc->base.primary->fb);
2121 intel_crtc->base.primary->fb = NULL;
2124 * Failed to alloc the obj, check to see if we should share
2125 * an fb with another CRTC instead
2127 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2128 i = to_intel_crtc(c);
2130 if (c == &intel_crtc->base)
2133 if (!i->active || !c->primary->fb)
2136 fb = to_intel_framebuffer(c->primary->fb);
2137 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2138 drm_framebuffer_reference(c->primary->fb);
2139 intel_crtc->base.primary->fb = c->primary->fb;
2145 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2146 struct drm_framebuffer *fb,
2149 struct drm_device *dev = crtc->dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2152 struct intel_framebuffer *intel_fb;
2153 struct drm_i915_gem_object *obj;
2154 int plane = intel_crtc->plane;
2155 unsigned long linear_offset;
2159 intel_fb = to_intel_framebuffer(fb);
2160 obj = intel_fb->obj;
2162 reg = DSPCNTR(plane);
2163 dspcntr = I915_READ(reg);
2164 /* Mask out pixel format bits in case we change it */
2165 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2166 switch (fb->pixel_format) {
2168 dspcntr |= DISPPLANE_8BPP;
2170 case DRM_FORMAT_XRGB1555:
2171 case DRM_FORMAT_ARGB1555:
2172 dspcntr |= DISPPLANE_BGRX555;
2174 case DRM_FORMAT_RGB565:
2175 dspcntr |= DISPPLANE_BGRX565;
2177 case DRM_FORMAT_XRGB8888:
2178 case DRM_FORMAT_ARGB8888:
2179 dspcntr |= DISPPLANE_BGRX888;
2181 case DRM_FORMAT_XBGR8888:
2182 case DRM_FORMAT_ABGR8888:
2183 dspcntr |= DISPPLANE_RGBX888;
2185 case DRM_FORMAT_XRGB2101010:
2186 case DRM_FORMAT_ARGB2101010:
2187 dspcntr |= DISPPLANE_BGRX101010;
2189 case DRM_FORMAT_XBGR2101010:
2190 case DRM_FORMAT_ABGR2101010:
2191 dspcntr |= DISPPLANE_RGBX101010;
2197 if (INTEL_INFO(dev)->gen >= 4) {
2198 if (obj->tiling_mode != I915_TILING_NONE)
2199 dspcntr |= DISPPLANE_TILED;
2201 dspcntr &= ~DISPPLANE_TILED;
2205 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2207 I915_WRITE(reg, dspcntr);
2209 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2211 if (INTEL_INFO(dev)->gen >= 4) {
2212 intel_crtc->dspaddr_offset =
2213 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2214 fb->bits_per_pixel / 8,
2216 linear_offset -= intel_crtc->dspaddr_offset;
2218 intel_crtc->dspaddr_offset = linear_offset;
2221 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2222 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2224 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2225 if (INTEL_INFO(dev)->gen >= 4) {
2226 I915_WRITE(DSPSURF(plane),
2227 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2228 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229 I915_WRITE(DSPLINOFF(plane), linear_offset);
2231 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2237 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2238 struct drm_framebuffer *fb,
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244 struct intel_framebuffer *intel_fb;
2245 struct drm_i915_gem_object *obj;
2246 int plane = intel_crtc->plane;
2247 unsigned long linear_offset;
2251 intel_fb = to_intel_framebuffer(fb);
2252 obj = intel_fb->obj;
2254 reg = DSPCNTR(plane);
2255 dspcntr = I915_READ(reg);
2256 /* Mask out pixel format bits in case we change it */
2257 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2258 switch (fb->pixel_format) {
2260 dspcntr |= DISPPLANE_8BPP;
2262 case DRM_FORMAT_RGB565:
2263 dspcntr |= DISPPLANE_BGRX565;
2265 case DRM_FORMAT_XRGB8888:
2266 case DRM_FORMAT_ARGB8888:
2267 dspcntr |= DISPPLANE_BGRX888;
2269 case DRM_FORMAT_XBGR8888:
2270 case DRM_FORMAT_ABGR8888:
2271 dspcntr |= DISPPLANE_RGBX888;
2273 case DRM_FORMAT_XRGB2101010:
2274 case DRM_FORMAT_ARGB2101010:
2275 dspcntr |= DISPPLANE_BGRX101010;
2277 case DRM_FORMAT_XBGR2101010:
2278 case DRM_FORMAT_ABGR2101010:
2279 dspcntr |= DISPPLANE_RGBX101010;
2285 if (obj->tiling_mode != I915_TILING_NONE)
2286 dspcntr |= DISPPLANE_TILED;
2288 dspcntr &= ~DISPPLANE_TILED;
2290 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2291 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2293 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2295 I915_WRITE(reg, dspcntr);
2297 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2298 intel_crtc->dspaddr_offset =
2299 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2300 fb->bits_per_pixel / 8,
2302 linear_offset -= intel_crtc->dspaddr_offset;
2304 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2305 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2307 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2308 I915_WRITE(DSPSURF(plane),
2309 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2310 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2311 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2313 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2314 I915_WRITE(DSPLINOFF(plane), linear_offset);
2321 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2323 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2324 int x, int y, enum mode_set_atomic state)
2326 struct drm_device *dev = crtc->dev;
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2329 if (dev_priv->display.disable_fbc)
2330 dev_priv->display.disable_fbc(dev);
2331 intel_increase_pllclock(crtc);
2333 return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2336 void intel_display_handle_reset(struct drm_device *dev)
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_crtc *crtc;
2342 * Flips in the rings have been nuked by the reset,
2343 * so complete all pending flips so that user space
2344 * will get its events and not get stuck.
2346 * Also update the base address of all primary
2347 * planes to the the last fb to make sure we're
2348 * showing the correct fb after a reset.
2350 * Need to make two loops over the crtcs so that we
2351 * don't try to grab a crtc mutex before the
2352 * pending_flip_queue really got woken up.
2355 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357 enum plane plane = intel_crtc->plane;
2359 intel_prepare_page_flip(dev, plane);
2360 intel_finish_page_flip_plane(dev, plane);
2363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 mutex_lock(&crtc->mutex);
2368 * FIXME: Once we have proper support for primary planes (and
2369 * disabling them without disabling the entire crtc) allow again
2370 * a NULL crtc->primary->fb.
2372 if (intel_crtc->active && crtc->primary->fb)
2373 dev_priv->display.update_primary_plane(crtc,
2377 mutex_unlock(&crtc->mutex);
2382 intel_finish_fb(struct drm_framebuffer *old_fb)
2384 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2385 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2386 bool was_interruptible = dev_priv->mm.interruptible;
2389 /* Big Hammer, we also need to ensure that any pending
2390 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2391 * current scanout is retired before unpinning the old
2394 * This should only fail upon a hung GPU, in which case we
2395 * can safely continue.
2397 dev_priv->mm.interruptible = false;
2398 ret = i915_gem_object_finish_gpu(obj);
2399 dev_priv->mm.interruptible = was_interruptible;
2404 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 unsigned long flags;
2412 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2413 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2416 spin_lock_irqsave(&dev->event_lock, flags);
2417 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2418 spin_unlock_irqrestore(&dev->event_lock, flags);
2424 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2425 struct drm_framebuffer *fb)
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 struct drm_framebuffer *old_fb;
2433 if (intel_crtc_has_pending_flip(crtc)) {
2434 DRM_ERROR("pipe is still busy with an old pageflip\n");
2440 DRM_ERROR("No FB bound\n");
2444 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2445 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2446 plane_name(intel_crtc->plane),
2447 INTEL_INFO(dev)->num_pipes);
2451 mutex_lock(&dev->struct_mutex);
2452 ret = intel_pin_and_fence_fb_obj(dev,
2453 to_intel_framebuffer(fb)->obj,
2455 mutex_unlock(&dev->struct_mutex);
2457 DRM_ERROR("pin & fence failed\n");
2462 * Update pipe size and adjust fitter if needed: the reason for this is
2463 * that in compute_mode_changes we check the native mode (not the pfit
2464 * mode) to see if we can flip rather than do a full mode set. In the
2465 * fastboot case, we'll flip, but if we don't update the pipesrc and
2466 * pfit state, we'll end up with a big fb scanned out into the wrong
2469 * To fix this properly, we need to hoist the checks up into
2470 * compute_mode_changes (or above), check the actual pfit state and
2471 * whether the platform allows pfit disable with pipe active, and only
2472 * then update the pipesrc and pfit state, even on the flip path.
2474 if (i915.fastboot) {
2475 const struct drm_display_mode *adjusted_mode =
2476 &intel_crtc->config.adjusted_mode;
2478 I915_WRITE(PIPESRC(intel_crtc->pipe),
2479 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2480 (adjusted_mode->crtc_vdisplay - 1));
2481 if (!intel_crtc->config.pch_pfit.enabled &&
2482 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2483 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2484 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2485 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2486 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2488 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2489 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2492 ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2494 mutex_lock(&dev->struct_mutex);
2495 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2496 mutex_unlock(&dev->struct_mutex);
2497 DRM_ERROR("failed to update base address\n");
2501 old_fb = crtc->primary->fb;
2502 crtc->primary->fb = fb;
2507 if (intel_crtc->active && old_fb != fb)
2508 intel_wait_for_vblank(dev, intel_crtc->pipe);
2509 mutex_lock(&dev->struct_mutex);
2510 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2511 mutex_unlock(&dev->struct_mutex);
2514 mutex_lock(&dev->struct_mutex);
2515 intel_update_fbc(dev);
2516 intel_edp_psr_update(dev);
2517 mutex_unlock(&dev->struct_mutex);
2522 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2524 struct drm_device *dev = crtc->dev;
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2527 int pipe = intel_crtc->pipe;
2530 /* enable normal train */
2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
2533 if (IS_IVYBRIDGE(dev)) {
2534 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2535 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2540 I915_WRITE(reg, temp);
2542 reg = FDI_RX_CTL(pipe);
2543 temp = I915_READ(reg);
2544 if (HAS_PCH_CPT(dev)) {
2545 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2546 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2548 temp &= ~FDI_LINK_TRAIN_NONE;
2549 temp |= FDI_LINK_TRAIN_NONE;
2551 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2553 /* wait one idle pattern time */
2557 /* IVB wants error correction enabled */
2558 if (IS_IVYBRIDGE(dev))
2559 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2560 FDI_FE_ERRC_ENABLE);
2563 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2565 return crtc->base.enabled && crtc->active &&
2566 crtc->config.has_pch_encoder;
2569 static void ivb_modeset_global_resources(struct drm_device *dev)
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *pipe_B_crtc =
2573 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2574 struct intel_crtc *pipe_C_crtc =
2575 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2579 * When everything is off disable fdi C so that we could enable fdi B
2580 * with all lanes. Note that we don't care about enabled pipes without
2581 * an enabled pch encoder.
2583 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2584 !pipe_has_enabled_pch(pipe_C_crtc)) {
2585 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2586 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2588 temp = I915_READ(SOUTH_CHICKEN1);
2589 temp &= ~FDI_BC_BIFURCATION_SELECT;
2590 DRM_DEBUG_KMS("disabling fdi C rx\n");
2591 I915_WRITE(SOUTH_CHICKEN1, temp);
2595 /* The FDI link training functions for ILK/Ibexpeak. */
2596 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
2602 u32 reg, temp, tries;
2604 /* FDI needs bits from pipe first */
2605 assert_pipe_enabled(dev_priv, pipe);
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2617 /* enable CPU FDI TX and PCH FDI RX */
2618 reg = FDI_TX_CTL(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2621 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_1;
2624 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2626 reg = FDI_RX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE;
2629 temp |= FDI_LINK_TRAIN_PATTERN_1;
2630 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635 /* Ironlake workaround, enable clock pointer after FDI enable*/
2636 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2637 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2638 FDI_RX_PHASE_SYNC_POINTER_EN);
2640 reg = FDI_RX_IIR(pipe);
2641 for (tries = 0; tries < 5; tries++) {
2642 temp = I915_READ(reg);
2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2645 if ((temp & FDI_RX_BIT_LOCK)) {
2646 DRM_DEBUG_KMS("FDI train 1 done.\n");
2647 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2652 DRM_ERROR("FDI train 1 fail!\n");
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_LINK_TRAIN_NONE;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2;
2659 I915_WRITE(reg, temp);
2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_NONE;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2;
2665 I915_WRITE(reg, temp);
2670 reg = FDI_RX_IIR(pipe);
2671 for (tries = 0; tries < 5; tries++) {
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675 if (temp & FDI_RX_SYMBOL_LOCK) {
2676 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2677 DRM_DEBUG_KMS("FDI train 2 done.\n");
2682 DRM_ERROR("FDI train 2 fail!\n");
2684 DRM_DEBUG_KMS("FDI train done\n");
2688 static const int snb_b_fdi_train_param[] = {
2689 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2690 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2691 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2692 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2695 /* The FDI link training functions for SNB/Cougarpoint. */
2696 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2698 struct drm_device *dev = crtc->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2701 int pipe = intel_crtc->pipe;
2702 u32 reg, temp, i, retry;
2704 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2706 reg = FDI_RX_IMR(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_RX_SYMBOL_LOCK;
2709 temp &= ~FDI_RX_BIT_LOCK;
2710 I915_WRITE(reg, temp);
2715 /* enable CPU FDI TX and PCH FDI RX */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2719 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720 temp &= ~FDI_LINK_TRAIN_NONE;
2721 temp |= FDI_LINK_TRAIN_PATTERN_1;
2722 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2725 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2727 I915_WRITE(FDI_RX_MISC(pipe),
2728 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 if (HAS_PCH_CPT(dev)) {
2733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2736 temp &= ~FDI_LINK_TRAIN_NONE;
2737 temp |= FDI_LINK_TRAIN_PATTERN_1;
2739 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2744 for (i = 0; i < 4; i++) {
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2748 temp |= snb_b_fdi_train_param[i];
2749 I915_WRITE(reg, temp);
2754 for (retry = 0; retry < 5; retry++) {
2755 reg = FDI_RX_IIR(pipe);
2756 temp = I915_READ(reg);
2757 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758 if (temp & FDI_RX_BIT_LOCK) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done.\n");
2769 DRM_ERROR("FDI train 1 fail!\n");
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2;
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2781 I915_WRITE(reg, temp);
2783 reg = FDI_RX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if (HAS_PCH_CPT(dev)) {
2786 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2787 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2789 temp &= ~FDI_LINK_TRAIN_NONE;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2;
2792 I915_WRITE(reg, temp);
2797 for (i = 0; i < 4; i++) {
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2801 temp |= snb_b_fdi_train_param[i];
2802 I915_WRITE(reg, temp);
2807 for (retry = 0; retry < 5; retry++) {
2808 reg = FDI_RX_IIR(pipe);
2809 temp = I915_READ(reg);
2810 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811 if (temp & FDI_RX_SYMBOL_LOCK) {
2812 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2813 DRM_DEBUG_KMS("FDI train 2 done.\n");
2822 DRM_ERROR("FDI train 2 fail!\n");
2824 DRM_DEBUG_KMS("FDI train done.\n");
2827 /* Manual link training for Ivy Bridge A0 parts */
2828 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2830 struct drm_device *dev = crtc->dev;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2833 int pipe = intel_crtc->pipe;
2834 u32 reg, temp, i, j;
2836 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2838 reg = FDI_RX_IMR(pipe);
2839 temp = I915_READ(reg);
2840 temp &= ~FDI_RX_SYMBOL_LOCK;
2841 temp &= ~FDI_RX_BIT_LOCK;
2842 I915_WRITE(reg, temp);
2847 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2848 I915_READ(FDI_RX_IIR(pipe)));
2850 /* Try each vswing and preemphasis setting twice before moving on */
2851 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2852 /* disable first in case we need to retry */
2853 reg = FDI_TX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2856 temp &= ~FDI_TX_ENABLE;
2857 I915_WRITE(reg, temp);
2859 reg = FDI_RX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_LINK_TRAIN_AUTO;
2862 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2863 temp &= ~FDI_RX_ENABLE;
2864 I915_WRITE(reg, temp);
2866 /* enable CPU FDI TX and PCH FDI RX */
2867 reg = FDI_TX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2870 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2871 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2872 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2873 temp |= snb_b_fdi_train_param[j/2];
2874 temp |= FDI_COMPOSITE_SYNC;
2875 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2877 I915_WRITE(FDI_RX_MISC(pipe),
2878 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2880 reg = FDI_RX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2883 temp |= FDI_COMPOSITE_SYNC;
2884 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2887 udelay(1); /* should be 0.5us */
2889 for (i = 0; i < 4; i++) {
2890 reg = FDI_RX_IIR(pipe);
2891 temp = I915_READ(reg);
2892 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2894 if (temp & FDI_RX_BIT_LOCK ||
2895 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2896 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2897 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2901 udelay(1); /* should be 0.5us */
2904 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2909 reg = FDI_TX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2912 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2913 I915_WRITE(reg, temp);
2915 reg = FDI_RX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2918 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2919 I915_WRITE(reg, temp);
2922 udelay(2); /* should be 1.5us */
2924 for (i = 0; i < 4; i++) {
2925 reg = FDI_RX_IIR(pipe);
2926 temp = I915_READ(reg);
2927 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2929 if (temp & FDI_RX_SYMBOL_LOCK ||
2930 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2931 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2932 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2936 udelay(2); /* should be 1.5us */
2939 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2943 DRM_DEBUG_KMS("FDI train done.\n");
2946 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2948 struct drm_device *dev = intel_crtc->base.dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 int pipe = intel_crtc->pipe;
2954 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
2957 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2958 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2959 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2965 /* Switch from Rawclk to PCDclk */
2966 temp = I915_READ(reg);
2967 I915_WRITE(reg, temp | FDI_PCDCLK);
2972 /* Enable CPU FDI TX PLL, always on for Ironlake */
2973 reg = FDI_TX_CTL(pipe);
2974 temp = I915_READ(reg);
2975 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2976 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2983 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2985 struct drm_device *dev = intel_crtc->base.dev;
2986 struct drm_i915_private *dev_priv = dev->dev_private;
2987 int pipe = intel_crtc->pipe;
2990 /* Switch from PCDclk to Rawclk */
2991 reg = FDI_RX_CTL(pipe);
2992 temp = I915_READ(reg);
2993 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2995 /* Disable CPU FDI TX PLL */
2996 reg = FDI_TX_CTL(pipe);
2997 temp = I915_READ(reg);
2998 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3003 reg = FDI_RX_CTL(pipe);
3004 temp = I915_READ(reg);
3005 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3007 /* Wait for the clocks to turn off. */
3012 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3014 struct drm_device *dev = crtc->dev;
3015 struct drm_i915_private *dev_priv = dev->dev_private;
3016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3017 int pipe = intel_crtc->pipe;
3020 /* disable CPU FDI tx and PCH FDI rx */
3021 reg = FDI_TX_CTL(pipe);
3022 temp = I915_READ(reg);
3023 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3026 reg = FDI_RX_CTL(pipe);
3027 temp = I915_READ(reg);
3028 temp &= ~(0x7 << 16);
3029 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3030 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3035 /* Ironlake workaround, disable clock pointer after downing FDI */
3036 if (HAS_PCH_IBX(dev)) {
3037 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3040 /* still set train pattern 1 */
3041 reg = FDI_TX_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~FDI_LINK_TRAIN_NONE;
3044 temp |= FDI_LINK_TRAIN_PATTERN_1;
3045 I915_WRITE(reg, temp);
3047 reg = FDI_RX_CTL(pipe);
3048 temp = I915_READ(reg);
3049 if (HAS_PCH_CPT(dev)) {
3050 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3053 temp &= ~FDI_LINK_TRAIN_NONE;
3054 temp |= FDI_LINK_TRAIN_PATTERN_1;
3056 /* BPC in FDI rx is consistent with that in PIPECONF */
3057 temp &= ~(0x07 << 16);
3058 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3059 I915_WRITE(reg, temp);
3065 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3067 struct intel_crtc *crtc;
3069 /* Note that we don't need to be called with mode_config.lock here
3070 * as our list of CRTC objects is static for the lifetime of the
3071 * device and so cannot disappear as we iterate. Similarly, we can
3072 * happily treat the predicates as racy, atomic checks as userspace
3073 * cannot claim and pin a new fb without at least acquring the
3074 * struct_mutex and so serialising with us.
3076 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3077 if (atomic_read(&crtc->unpin_work_count) == 0)
3080 if (crtc->unpin_work)
3081 intel_wait_for_vblank(dev, crtc->pipe);
3089 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3091 struct drm_device *dev = crtc->dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3094 if (crtc->primary->fb == NULL)
3097 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3099 wait_event(dev_priv->pending_flip_queue,
3100 !intel_crtc_has_pending_flip(crtc));
3102 mutex_lock(&dev->struct_mutex);
3103 intel_finish_fb(crtc->primary->fb);
3104 mutex_unlock(&dev->struct_mutex);
3107 /* Program iCLKIP clock to the desired frequency */
3108 static void lpt_program_iclkip(struct drm_crtc *crtc)
3110 struct drm_device *dev = crtc->dev;
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3113 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3116 mutex_lock(&dev_priv->dpio_lock);
3118 /* It is necessary to ungate the pixclk gate prior to programming
3119 * the divisors, and gate it back when it is done.
3121 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3123 /* Disable SSCCTL */
3124 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3125 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3129 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3130 if (clock == 20000) {
3135 /* The iCLK virtual clock root frequency is in MHz,
3136 * but the adjusted_mode->crtc_clock in in KHz. To get the
3137 * divisors, it is necessary to divide one by another, so we
3138 * convert the virtual clock precision to KHz here for higher
3141 u32 iclk_virtual_root_freq = 172800 * 1000;
3142 u32 iclk_pi_range = 64;
3143 u32 desired_divisor, msb_divisor_value, pi_value;
3145 desired_divisor = (iclk_virtual_root_freq / clock);
3146 msb_divisor_value = desired_divisor / iclk_pi_range;
3147 pi_value = desired_divisor % iclk_pi_range;
3150 divsel = msb_divisor_value - 2;
3151 phaseinc = pi_value;
3154 /* This should not happen with any sane values */
3155 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3156 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3157 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3158 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3160 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3167 /* Program SSCDIVINTPHASE6 */
3168 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3169 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3170 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3171 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3172 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3173 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3174 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3175 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3177 /* Program SSCAUXDIV */
3178 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3179 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3180 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3181 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3183 /* Enable modulator and associated divider */
3184 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3185 temp &= ~SBI_SSCCTL_DISABLE;
3186 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3188 /* Wait for initialization time */
3191 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3193 mutex_unlock(&dev_priv->dpio_lock);
3196 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3197 enum pipe pch_transcoder)
3199 struct drm_device *dev = crtc->base.dev;
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3203 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3204 I915_READ(HTOTAL(cpu_transcoder)));
3205 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3206 I915_READ(HBLANK(cpu_transcoder)));
3207 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3208 I915_READ(HSYNC(cpu_transcoder)));
3210 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3211 I915_READ(VTOTAL(cpu_transcoder)));
3212 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3213 I915_READ(VBLANK(cpu_transcoder)));
3214 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3215 I915_READ(VSYNC(cpu_transcoder)));
3216 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3217 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3220 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3225 temp = I915_READ(SOUTH_CHICKEN1);
3226 if (temp & FDI_BC_BIFURCATION_SELECT)
3229 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3230 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3232 temp |= FDI_BC_BIFURCATION_SELECT;
3233 DRM_DEBUG_KMS("enabling fdi C rx\n");
3234 I915_WRITE(SOUTH_CHICKEN1, temp);
3235 POSTING_READ(SOUTH_CHICKEN1);
3238 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3240 struct drm_device *dev = intel_crtc->base.dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3243 switch (intel_crtc->pipe) {
3247 if (intel_crtc->config.fdi_lanes > 2)
3248 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3250 cpt_enable_fdi_bc_bifurcation(dev);
3254 cpt_enable_fdi_bc_bifurcation(dev);
3263 * Enable PCH resources required for PCH ports:
3265 * - FDI training & RX/TX
3266 * - update transcoder timings
3267 * - DP transcoding bits
3270 static void ironlake_pch_enable(struct drm_crtc *crtc)
3272 struct drm_device *dev = crtc->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275 int pipe = intel_crtc->pipe;
3278 assert_pch_transcoder_disabled(dev_priv, pipe);
3280 if (IS_IVYBRIDGE(dev))
3281 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3283 /* Write the TU size bits before fdi link training, so that error
3284 * detection works. */
3285 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3286 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3288 /* For PCH output, training FDI link */
3289 dev_priv->display.fdi_link_train(crtc);
3291 /* We need to program the right clock selection before writing the pixel
3292 * mutliplier into the DPLL. */
3293 if (HAS_PCH_CPT(dev)) {
3296 temp = I915_READ(PCH_DPLL_SEL);
3297 temp |= TRANS_DPLL_ENABLE(pipe);
3298 sel = TRANS_DPLLB_SEL(pipe);
3299 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3303 I915_WRITE(PCH_DPLL_SEL, temp);
3306 /* XXX: pch pll's can be enabled any time before we enable the PCH
3307 * transcoder, and we actually should do this to not upset any PCH
3308 * transcoder that already use the clock when we share it.
3310 * Note that enable_shared_dpll tries to do the right thing, but
3311 * get_shared_dpll unconditionally resets the pll - we need that to have
3312 * the right LVDS enable sequence. */
3313 ironlake_enable_shared_dpll(intel_crtc);
3315 /* set transcoder timing, panel must allow it */
3316 assert_panel_unlocked(dev_priv, pipe);
3317 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3319 intel_fdi_normal_train(crtc);
3321 /* For PCH DP, enable TRANS_DP_CTL */
3322 if (HAS_PCH_CPT(dev) &&
3323 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3324 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3325 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3326 reg = TRANS_DP_CTL(pipe);
3327 temp = I915_READ(reg);
3328 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3329 TRANS_DP_SYNC_MASK |
3331 temp |= (TRANS_DP_OUTPUT_ENABLE |
3332 TRANS_DP_ENH_FRAMING);
3333 temp |= bpc << 9; /* same format but at 11:9 */
3335 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3336 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3337 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3338 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3340 switch (intel_trans_dp_port_sel(crtc)) {
3342 temp |= TRANS_DP_PORT_SEL_B;
3345 temp |= TRANS_DP_PORT_SEL_C;
3348 temp |= TRANS_DP_PORT_SEL_D;
3354 I915_WRITE(reg, temp);
3357 ironlake_enable_pch_transcoder(dev_priv, pipe);
3360 static void lpt_pch_enable(struct drm_crtc *crtc)
3362 struct drm_device *dev = crtc->dev;
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3367 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3369 lpt_program_iclkip(crtc);
3371 /* Set transcoder timing. */
3372 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3374 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3377 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3379 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3384 if (pll->refcount == 0) {
3385 WARN(1, "bad %s refcount\n", pll->name);
3389 if (--pll->refcount == 0) {
3391 WARN_ON(pll->active);
3394 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3397 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3401 enum intel_dpll_id i;
3404 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3405 crtc->base.base.id, pll->name);
3406 intel_put_shared_dpll(crtc);
3409 if (HAS_PCH_IBX(dev_priv->dev)) {
3410 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3411 i = (enum intel_dpll_id) crtc->pipe;
3412 pll = &dev_priv->shared_dplls[i];
3414 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3415 crtc->base.base.id, pll->name);
3420 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3421 pll = &dev_priv->shared_dplls[i];
3423 /* Only want to check enabled timings first */
3424 if (pll->refcount == 0)
3427 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3428 sizeof(pll->hw_state)) == 0) {
3429 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3431 pll->name, pll->refcount, pll->active);
3437 /* Ok no matching timings, maybe there's a free one? */
3438 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3439 pll = &dev_priv->shared_dplls[i];
3440 if (pll->refcount == 0) {
3441 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3442 crtc->base.base.id, pll->name);
3450 crtc->config.shared_dpll = i;
3451 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3452 pipe_name(crtc->pipe));
3454 if (pll->active == 0) {
3455 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3456 sizeof(pll->hw_state));
3458 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3460 assert_shared_dpll_disabled(dev_priv, pll);
3462 pll->mode_set(dev_priv, pll);
3469 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472 int dslreg = PIPEDSL(pipe);
3475 temp = I915_READ(dslreg);
3477 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3478 if (wait_for(I915_READ(dslreg) != temp, 5))
3479 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3483 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3485 struct drm_device *dev = crtc->base.dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 int pipe = crtc->pipe;
3489 if (crtc->config.pch_pfit.enabled) {
3490 /* Force use of hard-coded filter coefficients
3491 * as some pre-programmed values are broken,
3494 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3495 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3496 PF_PIPE_SEL_IVB(pipe));
3498 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3499 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3500 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3504 static void intel_enable_planes(struct drm_crtc *crtc)
3506 struct drm_device *dev = crtc->dev;
3507 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3508 struct drm_plane *plane;
3509 struct intel_plane *intel_plane;
3511 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3512 intel_plane = to_intel_plane(plane);
3513 if (intel_plane->pipe == pipe)
3514 intel_plane_restore(&intel_plane->base);
3518 static void intel_disable_planes(struct drm_crtc *crtc)
3520 struct drm_device *dev = crtc->dev;
3521 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3522 struct drm_plane *plane;
3523 struct intel_plane *intel_plane;
3525 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3526 intel_plane = to_intel_plane(plane);
3527 if (intel_plane->pipe == pipe)
3528 intel_plane_disable(&intel_plane->base);
3532 void hsw_enable_ips(struct intel_crtc *crtc)
3534 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3536 if (!crtc->config.ips_enabled)
3539 /* We can only enable IPS after we enable a plane and wait for a vblank.
3540 * We guarantee that the plane is enabled by calling intel_enable_ips
3541 * only after intel_enable_plane. And intel_enable_plane already waits
3542 * for a vblank, so all we need to do here is to enable the IPS bit. */
3543 assert_plane_enabled(dev_priv, crtc->plane);
3544 if (IS_BROADWELL(crtc->base.dev)) {
3545 mutex_lock(&dev_priv->rps.hw_lock);
3546 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3547 mutex_unlock(&dev_priv->rps.hw_lock);
3548 /* Quoting Art Runyan: "its not safe to expect any particular
3549 * value in IPS_CTL bit 31 after enabling IPS through the
3550 * mailbox." Moreover, the mailbox may return a bogus state,
3551 * so we need to just enable it and continue on.
3554 I915_WRITE(IPS_CTL, IPS_ENABLE);
3555 /* The bit only becomes 1 in the next vblank, so this wait here
3556 * is essentially intel_wait_for_vblank. If we don't have this
3557 * and don't wait for vblanks until the end of crtc_enable, then
3558 * the HW state readout code will complain that the expected
3559 * IPS_CTL value is not the one we read. */
3560 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3561 DRM_ERROR("Timed out waiting for IPS enable\n");
3565 void hsw_disable_ips(struct intel_crtc *crtc)
3567 struct drm_device *dev = crtc->base.dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3570 if (!crtc->config.ips_enabled)
3573 assert_plane_enabled(dev_priv, crtc->plane);
3574 if (IS_BROADWELL(dev)) {
3575 mutex_lock(&dev_priv->rps.hw_lock);
3576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3577 mutex_unlock(&dev_priv->rps.hw_lock);
3578 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3579 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3580 DRM_ERROR("Timed out waiting for IPS disable\n");
3582 I915_WRITE(IPS_CTL, 0);
3583 POSTING_READ(IPS_CTL);
3586 /* We need to wait for a vblank before we can disable the plane. */
3587 intel_wait_for_vblank(dev, crtc->pipe);
3590 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3591 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3593 struct drm_device *dev = crtc->dev;
3594 struct drm_i915_private *dev_priv = dev->dev_private;
3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596 enum pipe pipe = intel_crtc->pipe;
3597 int palreg = PALETTE(pipe);
3599 bool reenable_ips = false;
3601 /* The clocks have to be on to load the palette. */
3602 if (!crtc->enabled || !intel_crtc->active)
3605 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3606 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3607 assert_dsi_pll_enabled(dev_priv);
3609 assert_pll_enabled(dev_priv, pipe);
3612 /* use legacy palette for Ironlake */
3613 if (HAS_PCH_SPLIT(dev))
3614 palreg = LGC_PALETTE(pipe);
3616 /* Workaround : Do not read or write the pipe palette/gamma data while
3617 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3619 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3620 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3621 GAMMA_MODE_MODE_SPLIT)) {
3622 hsw_disable_ips(intel_crtc);
3623 reenable_ips = true;
3626 for (i = 0; i < 256; i++) {
3627 I915_WRITE(palreg + 4 * i,
3628 (intel_crtc->lut_r[i] << 16) |
3629 (intel_crtc->lut_g[i] << 8) |
3630 intel_crtc->lut_b[i]);
3634 hsw_enable_ips(intel_crtc);
3637 static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3642 int pipe = intel_crtc->pipe;
3643 int plane = intel_crtc->plane;
3645 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3646 intel_enable_planes(crtc);
3647 intel_crtc_update_cursor(crtc, true);
3649 hsw_enable_ips(intel_crtc);
3651 mutex_lock(&dev->struct_mutex);
3652 intel_update_fbc(dev);
3653 mutex_unlock(&dev->struct_mutex);
3656 static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
3658 struct drm_device *dev = crtc->dev;
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3661 int pipe = intel_crtc->pipe;
3662 int plane = intel_crtc->plane;
3664 intel_crtc_wait_for_pending_flips(crtc);
3665 drm_vblank_off(dev, pipe);
3667 if (dev_priv->fbc.plane == plane)
3668 intel_disable_fbc(dev);
3670 hsw_disable_ips(intel_crtc);
3672 intel_crtc_update_cursor(crtc, false);
3673 intel_disable_planes(crtc);
3674 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3677 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3679 struct drm_device *dev = crtc->dev;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3682 struct intel_encoder *encoder;
3683 int pipe = intel_crtc->pipe;
3685 WARN_ON(!crtc->enabled);
3687 if (intel_crtc->active)
3690 intel_crtc->active = true;
3692 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3693 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3695 for_each_encoder_on_crtc(dev, crtc, encoder)
3696 if (encoder->pre_enable)
3697 encoder->pre_enable(encoder);
3699 if (intel_crtc->config.has_pch_encoder) {
3700 /* Note: FDI PLL enabling _must_ be done before we enable the
3701 * cpu pipes, hence this is separate from all the other fdi/pch
3703 ironlake_fdi_pll_enable(intel_crtc);
3705 assert_fdi_tx_disabled(dev_priv, pipe);
3706 assert_fdi_rx_disabled(dev_priv, pipe);
3709 ironlake_pfit_enable(intel_crtc);
3712 * On ILK+ LUT must be loaded before the pipe is running but with
3715 intel_crtc_load_lut(crtc);
3717 intel_update_watermarks(crtc);
3718 intel_enable_pipe(intel_crtc);
3720 if (intel_crtc->config.has_pch_encoder)
3721 ironlake_pch_enable(crtc);
3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder);
3726 if (HAS_PCH_CPT(dev))
3727 cpt_verify_modeset(dev, intel_crtc->pipe);
3729 ilk_crtc_enable_planes(crtc);
3732 * There seems to be a race in PCH platform hw (at least on some
3733 * outputs) where an enabled pipe still completes any pageflip right
3734 * away (as if the pipe is off) instead of waiting for vblank. As soon
3735 * as the first vblank happend, everything works as expected. Hence just
3736 * wait for one vblank before returning to avoid strange things
3739 intel_wait_for_vblank(dev, intel_crtc->pipe);
3742 /* IPS only exists on ULT machines and is tied to pipe A. */
3743 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3745 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3749 * This implements the workaround described in the "notes" section of the mode
3750 * set sequence documentation. When going from no pipes or single pipe to
3751 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3752 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3754 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3756 struct drm_device *dev = crtc->base.dev;
3757 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3759 /* We want to get the other_active_crtc only if there's only 1 other
3761 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3762 if (!crtc_it->active || crtc_it == crtc)
3765 if (other_active_crtc)
3768 other_active_crtc = crtc_it;
3770 if (!other_active_crtc)
3773 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3774 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3777 static void haswell_crtc_enable(struct drm_crtc *crtc)
3779 struct drm_device *dev = crtc->dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782 struct intel_encoder *encoder;
3783 int pipe = intel_crtc->pipe;
3785 WARN_ON(!crtc->enabled);
3787 if (intel_crtc->active)
3790 intel_crtc->active = true;
3792 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3793 if (intel_crtc->config.has_pch_encoder)
3794 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3796 if (intel_crtc->config.has_pch_encoder)
3797 dev_priv->display.fdi_link_train(crtc);
3799 for_each_encoder_on_crtc(dev, crtc, encoder)
3800 if (encoder->pre_enable)
3801 encoder->pre_enable(encoder);
3803 intel_ddi_enable_pipe_clock(intel_crtc);
3805 ironlake_pfit_enable(intel_crtc);
3808 * On ILK+ LUT must be loaded before the pipe is running but with
3811 intel_crtc_load_lut(crtc);
3813 intel_ddi_set_pipe_settings(crtc);
3814 intel_ddi_enable_transcoder_func(crtc);
3816 intel_update_watermarks(crtc);
3817 intel_enable_pipe(intel_crtc);
3819 if (intel_crtc->config.has_pch_encoder)
3820 lpt_pch_enable(crtc);
3822 for_each_encoder_on_crtc(dev, crtc, encoder) {
3823 encoder->enable(encoder);
3824 intel_opregion_notify_encoder(encoder, true);
3827 /* If we change the relative order between pipe/planes enabling, we need
3828 * to change the workaround. */
3829 haswell_mode_set_planes_workaround(intel_crtc);
3830 ilk_crtc_enable_planes(crtc);
3833 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3835 struct drm_device *dev = crtc->base.dev;
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 int pipe = crtc->pipe;
3839 /* To avoid upsetting the power well on haswell only disable the pfit if
3840 * it's in use. The hw state code will make sure we get this right. */
3841 if (crtc->config.pch_pfit.enabled) {
3842 I915_WRITE(PF_CTL(pipe), 0);
3843 I915_WRITE(PF_WIN_POS(pipe), 0);
3844 I915_WRITE(PF_WIN_SZ(pipe), 0);
3848 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3850 struct drm_device *dev = crtc->dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3853 struct intel_encoder *encoder;
3854 int pipe = intel_crtc->pipe;
3857 if (!intel_crtc->active)
3860 ilk_crtc_disable_planes(crtc);
3862 for_each_encoder_on_crtc(dev, crtc, encoder)
3863 encoder->disable(encoder);
3865 if (intel_crtc->config.has_pch_encoder)
3866 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3868 intel_disable_pipe(dev_priv, pipe);
3870 ironlake_pfit_disable(intel_crtc);
3872 for_each_encoder_on_crtc(dev, crtc, encoder)
3873 if (encoder->post_disable)
3874 encoder->post_disable(encoder);
3876 if (intel_crtc->config.has_pch_encoder) {
3877 ironlake_fdi_disable(crtc);
3879 ironlake_disable_pch_transcoder(dev_priv, pipe);
3880 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3882 if (HAS_PCH_CPT(dev)) {
3883 /* disable TRANS_DP_CTL */
3884 reg = TRANS_DP_CTL(pipe);
3885 temp = I915_READ(reg);
3886 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3887 TRANS_DP_PORT_SEL_MASK);
3888 temp |= TRANS_DP_PORT_SEL_NONE;
3889 I915_WRITE(reg, temp);
3891 /* disable DPLL_SEL */
3892 temp = I915_READ(PCH_DPLL_SEL);
3893 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3894 I915_WRITE(PCH_DPLL_SEL, temp);
3897 /* disable PCH DPLL */
3898 intel_disable_shared_dpll(intel_crtc);
3900 ironlake_fdi_pll_disable(intel_crtc);
3903 intel_crtc->active = false;
3904 intel_update_watermarks(crtc);
3906 mutex_lock(&dev->struct_mutex);
3907 intel_update_fbc(dev);
3908 mutex_unlock(&dev->struct_mutex);
3911 static void haswell_crtc_disable(struct drm_crtc *crtc)
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916 struct intel_encoder *encoder;
3917 int pipe = intel_crtc->pipe;
3918 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3920 if (!intel_crtc->active)
3923 ilk_crtc_disable_planes(crtc);
3925 for_each_encoder_on_crtc(dev, crtc, encoder) {
3926 intel_opregion_notify_encoder(encoder, false);
3927 encoder->disable(encoder);
3930 if (intel_crtc->config.has_pch_encoder)
3931 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3932 intel_disable_pipe(dev_priv, pipe);
3934 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3936 ironlake_pfit_disable(intel_crtc);
3938 intel_ddi_disable_pipe_clock(intel_crtc);
3940 for_each_encoder_on_crtc(dev, crtc, encoder)
3941 if (encoder->post_disable)
3942 encoder->post_disable(encoder);
3944 if (intel_crtc->config.has_pch_encoder) {
3945 lpt_disable_pch_transcoder(dev_priv);
3946 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3947 intel_ddi_fdi_disable(crtc);
3950 intel_crtc->active = false;
3951 intel_update_watermarks(crtc);
3953 mutex_lock(&dev->struct_mutex);
3954 intel_update_fbc(dev);
3955 mutex_unlock(&dev->struct_mutex);
3958 static void ironlake_crtc_off(struct drm_crtc *crtc)
3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961 intel_put_shared_dpll(intel_crtc);
3964 static void haswell_crtc_off(struct drm_crtc *crtc)
3966 intel_ddi_put_crtc_pll(crtc);
3969 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3971 if (!enable && intel_crtc->overlay) {
3972 struct drm_device *dev = intel_crtc->base.dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3975 mutex_lock(&dev->struct_mutex);
3976 dev_priv->mm.interruptible = false;
3977 (void) intel_overlay_switch_off(intel_crtc->overlay);
3978 dev_priv->mm.interruptible = true;
3979 mutex_unlock(&dev->struct_mutex);
3982 /* Let userspace switch the overlay on again. In most cases userspace
3983 * has to recompute where to put it anyway.
3988 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3989 * cursor plane briefly if not already running after enabling the display
3991 * This workaround avoids occasional blank screens when self refresh is
3995 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3997 u32 cntl = I915_READ(CURCNTR(pipe));
3999 if ((cntl & CURSOR_MODE) == 0) {
4000 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4002 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4003 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4004 intel_wait_for_vblank(dev_priv->dev, pipe);
4005 I915_WRITE(CURCNTR(pipe), cntl);
4006 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4007 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4011 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4013 struct drm_device *dev = crtc->base.dev;
4014 struct drm_i915_private *dev_priv = dev->dev_private;
4015 struct intel_crtc_config *pipe_config = &crtc->config;
4017 if (!crtc->config.gmch_pfit.control)
4021 * The panel fitter should only be adjusted whilst the pipe is disabled,
4022 * according to register description and PRM.
4024 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4025 assert_pipe_disabled(dev_priv, crtc->pipe);
4027 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4028 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4030 /* Border color in case we don't scale up to the full screen. Black by
4031 * default, change to something else for debugging. */
4032 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4035 #define for_each_power_domain(domain, mask) \
4036 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4037 if ((1 << (domain)) & (mask))
4039 enum intel_display_power_domain
4040 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4042 struct drm_device *dev = intel_encoder->base.dev;
4043 struct intel_digital_port *intel_dig_port;
4045 switch (intel_encoder->type) {
4046 case INTEL_OUTPUT_UNKNOWN:
4047 /* Only DDI platforms should ever use this output type */
4048 WARN_ON_ONCE(!HAS_DDI(dev));
4049 case INTEL_OUTPUT_DISPLAYPORT:
4050 case INTEL_OUTPUT_HDMI:
4051 case INTEL_OUTPUT_EDP:
4052 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4053 switch (intel_dig_port->port) {
4055 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4057 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4059 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4061 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4064 return POWER_DOMAIN_PORT_OTHER;
4066 case INTEL_OUTPUT_ANALOG:
4067 return POWER_DOMAIN_PORT_CRT;
4068 case INTEL_OUTPUT_DSI:
4069 return POWER_DOMAIN_PORT_DSI;
4071 return POWER_DOMAIN_PORT_OTHER;
4075 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4077 struct drm_device *dev = crtc->dev;
4078 struct intel_encoder *intel_encoder;
4079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4080 enum pipe pipe = intel_crtc->pipe;
4081 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4083 enum transcoder transcoder;
4085 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4087 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4088 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4090 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4092 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4093 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4098 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4101 if (dev_priv->power_domains.init_power_on == enable)
4105 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4107 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4109 dev_priv->power_domains.init_power_on = enable;
4112 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4114 struct drm_i915_private *dev_priv = dev->dev_private;
4115 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4116 struct intel_crtc *crtc;
4119 * First get all needed power domains, then put all unneeded, to avoid
4120 * any unnecessary toggling of the power wells.
4122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4123 enum intel_display_power_domain domain;
4125 if (!crtc->base.enabled)
4128 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4130 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4131 intel_display_power_get(dev_priv, domain);
4134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4135 enum intel_display_power_domain domain;
4137 for_each_power_domain(domain, crtc->enabled_power_domains)
4138 intel_display_power_put(dev_priv, domain);
4140 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4143 intel_display_set_init_power(dev_priv, false);
4146 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4148 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4150 /* Obtain SKU information */
4151 mutex_lock(&dev_priv->dpio_lock);
4152 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4153 CCK_FUSE_HPLL_FREQ_MASK;
4154 mutex_unlock(&dev_priv->dpio_lock);
4156 return vco_freq[hpll_freq];
4159 /* Adjust CDclk dividers to allow high res or save power if possible */
4160 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4165 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4166 dev_priv->vlv_cdclk_freq = cdclk;
4168 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4170 else if (cdclk == 266)
4175 mutex_lock(&dev_priv->rps.hw_lock);
4176 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4177 val &= ~DSPFREQGUAR_MASK;
4178 val |= (cmd << DSPFREQGUAR_SHIFT);
4179 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4180 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4181 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4183 DRM_ERROR("timed out waiting for CDclk change\n");
4185 mutex_unlock(&dev_priv->rps.hw_lock);
4190 vco = valleyview_get_vco(dev_priv);
4191 divider = ((vco << 1) / cdclk) - 1;
4193 mutex_lock(&dev_priv->dpio_lock);
4194 /* adjust cdclk divider */
4195 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4198 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4199 mutex_unlock(&dev_priv->dpio_lock);
4202 mutex_lock(&dev_priv->dpio_lock);
4203 /* adjust self-refresh exit latency value */
4204 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4208 * For high bandwidth configs, we set a higher latency in the bunit
4209 * so that the core display fetch happens in time to avoid underruns.
4212 val |= 4500 / 250; /* 4.5 usec */
4214 val |= 3000 / 250; /* 3.0 usec */
4215 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4216 mutex_unlock(&dev_priv->dpio_lock);
4218 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4219 intel_i2c_reset(dev);
4222 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4227 vco = valleyview_get_vco(dev_priv);
4229 mutex_lock(&dev_priv->dpio_lock);
4230 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4231 mutex_unlock(&dev_priv->dpio_lock);
4235 cur_cdclk = (vco << 1) / (divider + 1);
4240 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4244 * Really only a few cases to deal with, as only 4 CDclks are supported:
4249 * So we check to see whether we're above 90% of the lower bin and
4252 if (max_pixclk > 288000) {
4254 } else if (max_pixclk > 240000) {
4258 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4261 /* compute the max pixel clock for new configuration */
4262 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4264 struct drm_device *dev = dev_priv->dev;
4265 struct intel_crtc *intel_crtc;
4268 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4270 if (intel_crtc->new_enabled)
4271 max_pixclk = max(max_pixclk,
4272 intel_crtc->new_config->adjusted_mode.crtc_clock);
4278 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4279 unsigned *prepare_pipes)
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct intel_crtc *intel_crtc;
4283 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4285 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4286 dev_priv->vlv_cdclk_freq)
4289 /* disable/enable all currently active pipes while we change cdclk */
4290 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4292 if (intel_crtc->base.enabled)
4293 *prepare_pipes |= (1 << intel_crtc->pipe);
4296 static void valleyview_modeset_global_resources(struct drm_device *dev)
4298 struct drm_i915_private *dev_priv = dev->dev_private;
4299 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4300 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4302 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4303 valleyview_set_cdclk(dev, req_cdclk);
4304 modeset_update_crtc_power_domains(dev);
4307 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4309 struct drm_device *dev = crtc->dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4312 struct intel_encoder *encoder;
4313 int pipe = intel_crtc->pipe;
4314 int plane = intel_crtc->plane;
4317 WARN_ON(!crtc->enabled);
4319 if (intel_crtc->active)
4322 intel_crtc->active = true;
4324 for_each_encoder_on_crtc(dev, crtc, encoder)
4325 if (encoder->pre_pll_enable)
4326 encoder->pre_pll_enable(encoder);
4328 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4331 vlv_enable_pll(intel_crtc);
4333 for_each_encoder_on_crtc(dev, crtc, encoder)
4334 if (encoder->pre_enable)
4335 encoder->pre_enable(encoder);
4337 i9xx_pfit_enable(intel_crtc);
4339 intel_crtc_load_lut(crtc);
4341 intel_update_watermarks(crtc);
4342 intel_enable_pipe(intel_crtc);
4343 intel_wait_for_vblank(dev_priv->dev, pipe);
4344 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4346 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4347 intel_enable_planes(crtc);
4348 intel_crtc_update_cursor(crtc, true);
4350 intel_update_fbc(dev);
4352 for_each_encoder_on_crtc(dev, crtc, encoder)
4353 encoder->enable(encoder);
4356 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4358 struct drm_device *dev = crtc->dev;
4359 struct drm_i915_private *dev_priv = dev->dev_private;
4360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361 struct intel_encoder *encoder;
4362 int pipe = intel_crtc->pipe;
4363 int plane = intel_crtc->plane;
4365 WARN_ON(!crtc->enabled);
4367 if (intel_crtc->active)
4370 intel_crtc->active = true;
4372 for_each_encoder_on_crtc(dev, crtc, encoder)
4373 if (encoder->pre_enable)
4374 encoder->pre_enable(encoder);
4376 i9xx_enable_pll(intel_crtc);
4378 i9xx_pfit_enable(intel_crtc);
4380 intel_crtc_load_lut(crtc);
4382 intel_update_watermarks(crtc);
4383 intel_enable_pipe(intel_crtc);
4384 intel_wait_for_vblank(dev_priv->dev, pipe);
4385 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4387 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4388 intel_enable_planes(crtc);
4389 /* The fixup needs to happen before cursor is enabled */
4391 g4x_fixup_plane(dev_priv, pipe);
4392 intel_crtc_update_cursor(crtc, true);
4394 /* Give the overlay scaler a chance to enable if it's on this pipe */
4395 intel_crtc_dpms_overlay(intel_crtc, true);
4397 intel_update_fbc(dev);
4399 for_each_encoder_on_crtc(dev, crtc, encoder)
4400 encoder->enable(encoder);
4403 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4405 struct drm_device *dev = crtc->base.dev;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4408 if (!crtc->config.gmch_pfit.control)
4411 assert_pipe_disabled(dev_priv, crtc->pipe);
4413 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4414 I915_READ(PFIT_CONTROL));
4415 I915_WRITE(PFIT_CONTROL, 0);
4418 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4420 struct drm_device *dev = crtc->dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423 struct intel_encoder *encoder;
4424 int pipe = intel_crtc->pipe;
4425 int plane = intel_crtc->plane;
4427 if (!intel_crtc->active)
4430 for_each_encoder_on_crtc(dev, crtc, encoder)
4431 encoder->disable(encoder);
4433 /* Give the overlay scaler a chance to disable if it's on this pipe */
4434 intel_crtc_wait_for_pending_flips(crtc);
4435 drm_vblank_off(dev, pipe);
4437 if (dev_priv->fbc.plane == plane)
4438 intel_disable_fbc(dev);
4440 intel_crtc_dpms_overlay(intel_crtc, false);
4441 intel_crtc_update_cursor(crtc, false);
4442 intel_disable_planes(crtc);
4443 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4445 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4446 intel_disable_pipe(dev_priv, pipe);
4448 i9xx_pfit_disable(intel_crtc);
4450 for_each_encoder_on_crtc(dev, crtc, encoder)
4451 if (encoder->post_disable)
4452 encoder->post_disable(encoder);
4454 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4455 vlv_disable_pll(dev_priv, pipe);
4456 else if (!IS_VALLEYVIEW(dev))
4457 i9xx_disable_pll(dev_priv, pipe);
4459 intel_crtc->active = false;
4460 intel_update_watermarks(crtc);
4462 intel_update_fbc(dev);
4465 static void i9xx_crtc_off(struct drm_crtc *crtc)
4469 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4472 struct drm_device *dev = crtc->dev;
4473 struct drm_i915_master_private *master_priv;
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475 int pipe = intel_crtc->pipe;
4477 if (!dev->primary->master)
4480 master_priv = dev->primary->master->driver_priv;
4481 if (!master_priv->sarea_priv)
4486 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4487 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4490 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4491 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4494 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4500 * Sets the power management mode of the pipe and plane.
4502 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4504 struct drm_device *dev = crtc->dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 struct intel_encoder *intel_encoder;
4507 bool enable = false;
4509 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4510 enable |= intel_encoder->connectors_active;
4513 dev_priv->display.crtc_enable(crtc);
4515 dev_priv->display.crtc_disable(crtc);
4517 intel_crtc_update_sarea(crtc, enable);
4520 static void intel_crtc_disable(struct drm_crtc *crtc)
4522 struct drm_device *dev = crtc->dev;
4523 struct drm_connector *connector;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527 /* crtc should still be enabled when we disable it. */
4528 WARN_ON(!crtc->enabled);
4530 dev_priv->display.crtc_disable(crtc);
4531 intel_crtc->eld_vld = false;
4532 intel_crtc_update_sarea(crtc, false);
4533 dev_priv->display.off(crtc);
4535 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4536 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4537 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4539 if (crtc->primary->fb) {
4540 mutex_lock(&dev->struct_mutex);
4541 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4542 mutex_unlock(&dev->struct_mutex);
4543 crtc->primary->fb = NULL;
4546 /* Update computed state. */
4547 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4548 if (!connector->encoder || !connector->encoder->crtc)
4551 if (connector->encoder->crtc != crtc)
4554 connector->dpms = DRM_MODE_DPMS_OFF;
4555 to_intel_encoder(connector->encoder)->connectors_active = false;
4559 void intel_encoder_destroy(struct drm_encoder *encoder)
4561 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4563 drm_encoder_cleanup(encoder);
4564 kfree(intel_encoder);
4567 /* Simple dpms helper for encoders with just one connector, no cloning and only
4568 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4569 * state of the entire output pipe. */
4570 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4572 if (mode == DRM_MODE_DPMS_ON) {
4573 encoder->connectors_active = true;
4575 intel_crtc_update_dpms(encoder->base.crtc);
4577 encoder->connectors_active = false;
4579 intel_crtc_update_dpms(encoder->base.crtc);
4583 /* Cross check the actual hw state with our own modeset state tracking (and it's
4584 * internal consistency). */
4585 static void intel_connector_check_state(struct intel_connector *connector)
4587 if (connector->get_hw_state(connector)) {
4588 struct intel_encoder *encoder = connector->encoder;
4589 struct drm_crtc *crtc;
4590 bool encoder_enabled;
4593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4594 connector->base.base.id,
4595 drm_get_connector_name(&connector->base));
4597 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4598 "wrong connector dpms state\n");
4599 WARN(connector->base.encoder != &encoder->base,
4600 "active connector not linked to encoder\n");
4601 WARN(!encoder->connectors_active,
4602 "encoder->connectors_active not set\n");
4604 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4605 WARN(!encoder_enabled, "encoder not enabled\n");
4606 if (WARN_ON(!encoder->base.crtc))
4609 crtc = encoder->base.crtc;
4611 WARN(!crtc->enabled, "crtc not enabled\n");
4612 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4613 WARN(pipe != to_intel_crtc(crtc)->pipe,
4614 "encoder active on the wrong pipe\n");
4618 /* Even simpler default implementation, if there's really no special case to
4620 void intel_connector_dpms(struct drm_connector *connector, int mode)
4622 /* All the simple cases only support two dpms states. */
4623 if (mode != DRM_MODE_DPMS_ON)
4624 mode = DRM_MODE_DPMS_OFF;
4626 if (mode == connector->dpms)
4629 connector->dpms = mode;
4631 /* Only need to change hw state when actually enabled */
4632 if (connector->encoder)
4633 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4635 intel_modeset_check_state(connector->dev);
4638 /* Simple connector->get_hw_state implementation for encoders that support only
4639 * one connector and no cloning and hence the encoder state determines the state
4640 * of the connector. */
4641 bool intel_connector_get_hw_state(struct intel_connector *connector)
4644 struct intel_encoder *encoder = connector->encoder;
4646 return encoder->get_hw_state(encoder, &pipe);
4649 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4650 struct intel_crtc_config *pipe_config)
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_crtc *pipe_B_crtc =
4654 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4656 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4657 pipe_name(pipe), pipe_config->fdi_lanes);
4658 if (pipe_config->fdi_lanes > 4) {
4659 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4660 pipe_name(pipe), pipe_config->fdi_lanes);
4664 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4665 if (pipe_config->fdi_lanes > 2) {
4666 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4667 pipe_config->fdi_lanes);
4674 if (INTEL_INFO(dev)->num_pipes == 2)
4677 /* Ivybridge 3 pipe is really complicated */
4682 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4683 pipe_config->fdi_lanes > 2) {
4684 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4685 pipe_name(pipe), pipe_config->fdi_lanes);
4690 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4691 pipe_B_crtc->config.fdi_lanes <= 2) {
4692 if (pipe_config->fdi_lanes > 2) {
4693 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4694 pipe_name(pipe), pipe_config->fdi_lanes);
4698 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4708 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4709 struct intel_crtc_config *pipe_config)
4711 struct drm_device *dev = intel_crtc->base.dev;
4712 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4713 int lane, link_bw, fdi_dotclock;
4714 bool setup_ok, needs_recompute = false;
4717 /* FDI is a binary signal running at ~2.7GHz, encoding
4718 * each output octet as 10 bits. The actual frequency
4719 * is stored as a divider into a 100MHz clock, and the
4720 * mode pixel clock is stored in units of 1KHz.
4721 * Hence the bw of each lane in terms of the mode signal
4724 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4726 fdi_dotclock = adjusted_mode->crtc_clock;
4728 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4729 pipe_config->pipe_bpp);
4731 pipe_config->fdi_lanes = lane;
4733 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4734 link_bw, &pipe_config->fdi_m_n);
4736 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4737 intel_crtc->pipe, pipe_config);
4738 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4739 pipe_config->pipe_bpp -= 2*3;
4740 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4741 pipe_config->pipe_bpp);
4742 needs_recompute = true;
4743 pipe_config->bw_constrained = true;
4748 if (needs_recompute)
4751 return setup_ok ? 0 : -EINVAL;
4754 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4755 struct intel_crtc_config *pipe_config)
4757 pipe_config->ips_enabled = i915.enable_ips &&
4758 hsw_crtc_supports_ips(crtc) &&
4759 pipe_config->pipe_bpp <= 24;
4762 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4763 struct intel_crtc_config *pipe_config)
4765 struct drm_device *dev = crtc->base.dev;
4766 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4768 /* FIXME should check pixel clock limits on all platforms */
4769 if (INTEL_INFO(dev)->gen < 4) {
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4772 dev_priv->display.get_display_clock_speed(dev);
4775 * Enable pixel doubling when the dot clock
4776 * is > 90% of the (display) core speed.
4778 * GDG double wide on either pipe,
4779 * otherwise pipe A only.
4781 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4782 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4784 pipe_config->double_wide = true;
4787 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4792 * Pipe horizontal size must be even in:
4794 * - LVDS dual channel mode
4795 * - Double wide pipe
4797 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4798 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4799 pipe_config->pipe_src_w &= ~1;
4801 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4802 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4804 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4805 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4808 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4809 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4810 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4811 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4813 pipe_config->pipe_bpp = 8*3;
4817 hsw_compute_ips_config(crtc, pipe_config);
4819 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4820 * clock survives for now. */
4821 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4822 pipe_config->shared_dpll = crtc->config.shared_dpll;
4824 if (pipe_config->has_pch_encoder)
4825 return ironlake_fdi_compute_config(crtc, pipe_config);
4830 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4832 return 400000; /* FIXME */
4835 static int i945_get_display_clock_speed(struct drm_device *dev)
4840 static int i915_get_display_clock_speed(struct drm_device *dev)
4845 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4850 static int pnv_get_display_clock_speed(struct drm_device *dev)
4854 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4856 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4857 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4859 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4861 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4863 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4866 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4867 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4869 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4874 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4878 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4880 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4883 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4884 case GC_DISPLAY_CLOCK_333_MHZ:
4887 case GC_DISPLAY_CLOCK_190_200_MHZ:
4893 static int i865_get_display_clock_speed(struct drm_device *dev)
4898 static int i855_get_display_clock_speed(struct drm_device *dev)
4901 /* Assume that the hardware is in the high speed state. This
4902 * should be the default.
4904 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4905 case GC_CLOCK_133_200:
4906 case GC_CLOCK_100_200:
4908 case GC_CLOCK_166_250:
4910 case GC_CLOCK_100_133:
4914 /* Shouldn't happen */
4918 static int i830_get_display_clock_speed(struct drm_device *dev)
4924 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4926 while (*num > DATA_LINK_M_N_MASK ||
4927 *den > DATA_LINK_M_N_MASK) {
4933 static void compute_m_n(unsigned int m, unsigned int n,
4934 uint32_t *ret_m, uint32_t *ret_n)
4936 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4937 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4938 intel_reduce_m_n_ratio(ret_m, ret_n);
4942 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4943 int pixel_clock, int link_clock,
4944 struct intel_link_m_n *m_n)
4948 compute_m_n(bits_per_pixel * pixel_clock,
4949 link_clock * nlanes * 8,
4950 &m_n->gmch_m, &m_n->gmch_n);
4952 compute_m_n(pixel_clock, link_clock,
4953 &m_n->link_m, &m_n->link_n);
4956 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4958 if (i915.panel_use_ssc >= 0)
4959 return i915.panel_use_ssc != 0;
4960 return dev_priv->vbt.lvds_use_ssc
4961 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4964 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4970 if (IS_VALLEYVIEW(dev)) {
4972 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4973 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4974 refclk = dev_priv->vbt.lvds_ssc_freq;
4975 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4976 } else if (!IS_GEN2(dev)) {
4985 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4987 return (1 << dpll->n) << 16 | dpll->m2;
4990 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4992 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4995 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4996 intel_clock_t *reduced_clock)
4998 struct drm_device *dev = crtc->base.dev;
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5000 int pipe = crtc->pipe;
5003 if (IS_PINEVIEW(dev)) {
5004 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5006 fp2 = pnv_dpll_compute_fp(reduced_clock);
5008 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5010 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5013 I915_WRITE(FP0(pipe), fp);
5014 crtc->config.dpll_hw_state.fp0 = fp;
5016 crtc->lowfreq_avail = false;
5017 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5018 reduced_clock && i915.powersave) {
5019 I915_WRITE(FP1(pipe), fp2);
5020 crtc->config.dpll_hw_state.fp1 = fp2;
5021 crtc->lowfreq_avail = true;
5023 I915_WRITE(FP1(pipe), fp);
5024 crtc->config.dpll_hw_state.fp1 = fp;
5028 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5034 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5035 * and set it to a reasonable value instead.
5037 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5038 reg_val &= 0xffffff00;
5039 reg_val |= 0x00000030;
5040 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5042 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5043 reg_val &= 0x8cffffff;
5044 reg_val = 0x8c000000;
5045 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5047 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5048 reg_val &= 0xffffff00;
5049 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5051 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5052 reg_val &= 0x00ffffff;
5053 reg_val |= 0xb0000000;
5054 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5057 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5058 struct intel_link_m_n *m_n)
5060 struct drm_device *dev = crtc->base.dev;
5061 struct drm_i915_private *dev_priv = dev->dev_private;
5062 int pipe = crtc->pipe;
5064 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5065 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5066 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5067 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5070 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5071 struct intel_link_m_n *m_n)
5073 struct drm_device *dev = crtc->base.dev;
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 int pipe = crtc->pipe;
5076 enum transcoder transcoder = crtc->config.cpu_transcoder;
5078 if (INTEL_INFO(dev)->gen >= 5) {
5079 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5080 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5081 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5082 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5084 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5085 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5086 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5087 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5091 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5093 if (crtc->config.has_pch_encoder)
5094 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5096 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5099 static void vlv_update_pll(struct intel_crtc *crtc)
5101 struct drm_device *dev = crtc->base.dev;
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 int pipe = crtc->pipe;
5105 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5106 u32 coreclk, reg_val, dpll_md;
5108 mutex_lock(&dev_priv->dpio_lock);
5110 bestn = crtc->config.dpll.n;
5111 bestm1 = crtc->config.dpll.m1;
5112 bestm2 = crtc->config.dpll.m2;
5113 bestp1 = crtc->config.dpll.p1;
5114 bestp2 = crtc->config.dpll.p2;
5116 /* See eDP HDMI DPIO driver vbios notes doc */
5118 /* PLL B needs special handling */
5120 vlv_pllb_recal_opamp(dev_priv, pipe);
5122 /* Set up Tx target for periodic Rcomp update */
5123 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5125 /* Disable target IRef on PLL */
5126 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5127 reg_val &= 0x00ffffff;
5128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5130 /* Disable fast lock */
5131 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5133 /* Set idtafcrecal before PLL is enabled */
5134 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5135 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5136 mdiv |= ((bestn << DPIO_N_SHIFT));
5137 mdiv |= (1 << DPIO_K_SHIFT);
5140 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5141 * but we don't support that).
5142 * Note: don't use the DAC post divider as it seems unstable.
5144 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5145 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5147 mdiv |= DPIO_ENABLE_CALIBRATION;
5148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5150 /* Set HBR and RBR LPF coefficients */
5151 if (crtc->config.port_clock == 162000 ||
5152 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5153 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5160 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5161 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5162 /* Use SSC source */
5164 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5167 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5169 } else { /* HDMI or VGA */
5170 /* Use bend source */
5172 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5175 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5179 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5180 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5181 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5182 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5183 coreclk |= 0x01000000;
5184 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5186 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5189 * Enable DPIO clock input. We should never disable the reference
5190 * clock for pipe B, since VGA hotplug / manual detection depends
5193 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5194 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5195 /* We should never disable this, set it here for state tracking */
5197 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5198 dpll |= DPLL_VCO_ENABLE;
5199 crtc->config.dpll_hw_state.dpll = dpll;
5201 dpll_md = (crtc->config.pixel_multiplier - 1)
5202 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5203 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5205 mutex_unlock(&dev_priv->dpio_lock);
5208 static void i9xx_update_pll(struct intel_crtc *crtc,
5209 intel_clock_t *reduced_clock,
5212 struct drm_device *dev = crtc->base.dev;
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5216 struct dpll *clock = &crtc->config.dpll;
5218 i9xx_update_pll_dividers(crtc, reduced_clock);
5220 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5221 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5223 dpll = DPLL_VGA_MODE_DIS;
5225 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5226 dpll |= DPLLB_MODE_LVDS;
5228 dpll |= DPLLB_MODE_DAC_SERIAL;
5230 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5231 dpll |= (crtc->config.pixel_multiplier - 1)
5232 << SDVO_MULTIPLIER_SHIFT_HIRES;
5236 dpll |= DPLL_SDVO_HIGH_SPEED;
5238 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5239 dpll |= DPLL_SDVO_HIGH_SPEED;
5241 /* compute bitmask from p1 value */
5242 if (IS_PINEVIEW(dev))
5243 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5245 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5246 if (IS_G4X(dev) && reduced_clock)
5247 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5249 switch (clock->p2) {
5251 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5254 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5257 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5260 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5263 if (INTEL_INFO(dev)->gen >= 4)
5264 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5266 if (crtc->config.sdvo_tv_clock)
5267 dpll |= PLL_REF_INPUT_TVCLKINBC;
5268 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5269 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5270 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5272 dpll |= PLL_REF_INPUT_DREFCLK;
5274 dpll |= DPLL_VCO_ENABLE;
5275 crtc->config.dpll_hw_state.dpll = dpll;
5277 if (INTEL_INFO(dev)->gen >= 4) {
5278 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5279 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5280 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5284 static void i8xx_update_pll(struct intel_crtc *crtc,
5285 intel_clock_t *reduced_clock,
5288 struct drm_device *dev = crtc->base.dev;
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5291 struct dpll *clock = &crtc->config.dpll;
5293 i9xx_update_pll_dividers(crtc, reduced_clock);
5295 dpll = DPLL_VGA_MODE_DIS;
5297 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5298 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5301 dpll |= PLL_P1_DIVIDE_BY_TWO;
5303 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5305 dpll |= PLL_P2_DIVIDE_BY_4;
5308 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5309 dpll |= DPLL_DVO_2X_MODE;
5311 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5312 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5313 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5315 dpll |= PLL_REF_INPUT_DREFCLK;
5317 dpll |= DPLL_VCO_ENABLE;
5318 crtc->config.dpll_hw_state.dpll = dpll;
5321 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5323 struct drm_device *dev = intel_crtc->base.dev;
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 enum pipe pipe = intel_crtc->pipe;
5326 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5327 struct drm_display_mode *adjusted_mode =
5328 &intel_crtc->config.adjusted_mode;
5329 uint32_t crtc_vtotal, crtc_vblank_end;
5332 /* We need to be careful not to changed the adjusted mode, for otherwise
5333 * the hw state checker will get angry at the mismatch. */
5334 crtc_vtotal = adjusted_mode->crtc_vtotal;
5335 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5337 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5338 /* the chip adds 2 halflines automatically */
5340 crtc_vblank_end -= 1;
5342 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5343 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5345 vsyncshift = adjusted_mode->crtc_hsync_start -
5346 adjusted_mode->crtc_htotal / 2;
5348 vsyncshift += adjusted_mode->crtc_htotal;
5351 if (INTEL_INFO(dev)->gen > 3)
5352 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5354 I915_WRITE(HTOTAL(cpu_transcoder),
5355 (adjusted_mode->crtc_hdisplay - 1) |
5356 ((adjusted_mode->crtc_htotal - 1) << 16));
5357 I915_WRITE(HBLANK(cpu_transcoder),
5358 (adjusted_mode->crtc_hblank_start - 1) |
5359 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5360 I915_WRITE(HSYNC(cpu_transcoder),
5361 (adjusted_mode->crtc_hsync_start - 1) |
5362 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5364 I915_WRITE(VTOTAL(cpu_transcoder),
5365 (adjusted_mode->crtc_vdisplay - 1) |
5366 ((crtc_vtotal - 1) << 16));
5367 I915_WRITE(VBLANK(cpu_transcoder),
5368 (adjusted_mode->crtc_vblank_start - 1) |
5369 ((crtc_vblank_end - 1) << 16));
5370 I915_WRITE(VSYNC(cpu_transcoder),
5371 (adjusted_mode->crtc_vsync_start - 1) |
5372 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5374 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5375 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5376 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5378 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5379 (pipe == PIPE_B || pipe == PIPE_C))
5380 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5382 /* pipesrc controls the size that is scaled from, which should
5383 * always be the user's requested size.
5385 I915_WRITE(PIPESRC(pipe),
5386 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5387 (intel_crtc->config.pipe_src_h - 1));
5390 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5391 struct intel_crtc_config *pipe_config)
5393 struct drm_device *dev = crtc->base.dev;
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5398 tmp = I915_READ(HTOTAL(cpu_transcoder));
5399 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5400 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5401 tmp = I915_READ(HBLANK(cpu_transcoder));
5402 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5403 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5404 tmp = I915_READ(HSYNC(cpu_transcoder));
5405 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5406 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5408 tmp = I915_READ(VTOTAL(cpu_transcoder));
5409 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5410 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5411 tmp = I915_READ(VBLANK(cpu_transcoder));
5412 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5413 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5414 tmp = I915_READ(VSYNC(cpu_transcoder));
5415 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5416 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5418 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5419 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5420 pipe_config->adjusted_mode.crtc_vtotal += 1;
5421 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5424 tmp = I915_READ(PIPESRC(crtc->pipe));
5425 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5426 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5428 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5429 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5432 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5433 struct intel_crtc_config *pipe_config)
5435 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5436 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5437 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5438 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5440 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5441 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5442 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5443 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5445 mode->flags = pipe_config->adjusted_mode.flags;
5447 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5448 mode->flags |= pipe_config->adjusted_mode.flags;
5451 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5453 struct drm_device *dev = intel_crtc->base.dev;
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5459 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5460 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5461 pipeconf |= PIPECONF_ENABLE;
5463 if (intel_crtc->config.double_wide)
5464 pipeconf |= PIPECONF_DOUBLE_WIDE;
5466 /* only g4x and later have fancy bpc/dither controls */
5467 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5468 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5469 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5470 pipeconf |= PIPECONF_DITHER_EN |
5471 PIPECONF_DITHER_TYPE_SP;
5473 switch (intel_crtc->config.pipe_bpp) {
5475 pipeconf |= PIPECONF_6BPC;
5478 pipeconf |= PIPECONF_8BPC;
5481 pipeconf |= PIPECONF_10BPC;
5484 /* Case prevented by intel_choose_pipe_bpp_dither. */
5489 if (HAS_PIPE_CXSR(dev)) {
5490 if (intel_crtc->lowfreq_avail) {
5491 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5492 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5494 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5498 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5499 if (INTEL_INFO(dev)->gen < 4 ||
5500 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5501 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5503 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5505 pipeconf |= PIPECONF_PROGRESSIVE;
5507 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5508 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5510 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5511 POSTING_READ(PIPECONF(intel_crtc->pipe));
5514 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5516 struct drm_framebuffer *fb)
5518 struct drm_device *dev = crtc->dev;
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5521 int pipe = intel_crtc->pipe;
5522 int plane = intel_crtc->plane;
5523 int refclk, num_connectors = 0;
5524 intel_clock_t clock, reduced_clock;
5526 bool ok, has_reduced_clock = false;
5527 bool is_lvds = false, is_dsi = false;
5528 struct intel_encoder *encoder;
5529 const intel_limit_t *limit;
5532 for_each_encoder_on_crtc(dev, crtc, encoder) {
5533 switch (encoder->type) {
5534 case INTEL_OUTPUT_LVDS:
5537 case INTEL_OUTPUT_DSI:
5548 if (!intel_crtc->config.clock_set) {
5549 refclk = i9xx_get_refclk(crtc, num_connectors);
5552 * Returns a set of divisors for the desired target clock with
5553 * the given refclk, or FALSE. The returned values represent
5554 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5557 limit = intel_limit(crtc, refclk);
5558 ok = dev_priv->display.find_dpll(limit, crtc,
5559 intel_crtc->config.port_clock,
5560 refclk, NULL, &clock);
5562 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5566 if (is_lvds && dev_priv->lvds_downclock_avail) {
5568 * Ensure we match the reduced clock's P to the target
5569 * clock. If the clocks don't match, we can't switch
5570 * the display clock by using the FP0/FP1. In such case
5571 * we will disable the LVDS downclock feature.
5574 dev_priv->display.find_dpll(limit, crtc,
5575 dev_priv->lvds_downclock,
5579 /* Compat-code for transition, will disappear. */
5580 intel_crtc->config.dpll.n = clock.n;
5581 intel_crtc->config.dpll.m1 = clock.m1;
5582 intel_crtc->config.dpll.m2 = clock.m2;
5583 intel_crtc->config.dpll.p1 = clock.p1;
5584 intel_crtc->config.dpll.p2 = clock.p2;
5588 i8xx_update_pll(intel_crtc,
5589 has_reduced_clock ? &reduced_clock : NULL,
5591 } else if (IS_VALLEYVIEW(dev)) {
5592 vlv_update_pll(intel_crtc);
5594 i9xx_update_pll(intel_crtc,
5595 has_reduced_clock ? &reduced_clock : NULL,
5600 /* Set up the display plane register */
5601 dspcntr = DISPPLANE_GAMMA_ENABLE;
5603 if (!IS_VALLEYVIEW(dev)) {
5605 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5607 dspcntr |= DISPPLANE_SEL_PIPE_B;
5610 if (intel_crtc->config.has_dp_encoder)
5611 intel_dp_set_m_n(intel_crtc);
5613 intel_set_pipe_timings(intel_crtc);
5615 /* pipesrc and dspsize control the size that is scaled from,
5616 * which should always be the user's requested size.
5618 I915_WRITE(DSPSIZE(plane),
5619 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5620 (intel_crtc->config.pipe_src_w - 1));
5621 I915_WRITE(DSPPOS(plane), 0);
5623 i9xx_set_pipeconf(intel_crtc);
5625 I915_WRITE(DSPCNTR(plane), dspcntr);
5626 POSTING_READ(DSPCNTR(plane));
5628 ret = intel_pipe_set_base(crtc, x, y, fb);
5633 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5634 struct intel_crtc_config *pipe_config)
5636 struct drm_device *dev = crtc->base.dev;
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5640 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5643 tmp = I915_READ(PFIT_CONTROL);
5644 if (!(tmp & PFIT_ENABLE))
5647 /* Check whether the pfit is attached to our pipe. */
5648 if (INTEL_INFO(dev)->gen < 4) {
5649 if (crtc->pipe != PIPE_B)
5652 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5656 pipe_config->gmch_pfit.control = tmp;
5657 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5658 if (INTEL_INFO(dev)->gen < 5)
5659 pipe_config->gmch_pfit.lvds_border_bits =
5660 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5663 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5664 struct intel_crtc_config *pipe_config)
5666 struct drm_device *dev = crtc->base.dev;
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 int pipe = pipe_config->cpu_transcoder;
5669 intel_clock_t clock;
5671 int refclk = 100000;
5673 mutex_lock(&dev_priv->dpio_lock);
5674 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5675 mutex_unlock(&dev_priv->dpio_lock);
5677 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5678 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5679 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5680 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5681 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5683 vlv_clock(refclk, &clock);
5685 /* clock.dot is the fast clock */
5686 pipe_config->port_clock = clock.dot / 5;
5689 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5690 struct intel_plane_config *plane_config)
5692 struct drm_device *dev = crtc->base.dev;
5693 struct drm_i915_private *dev_priv = dev->dev_private;
5694 u32 val, base, offset;
5695 int pipe = crtc->pipe, plane = crtc->plane;
5696 int fourcc, pixel_format;
5699 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5700 if (!crtc->base.primary->fb) {
5701 DRM_DEBUG_KMS("failed to alloc fb\n");
5705 val = I915_READ(DSPCNTR(plane));
5707 if (INTEL_INFO(dev)->gen >= 4)
5708 if (val & DISPPLANE_TILED)
5709 plane_config->tiled = true;
5711 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5712 fourcc = intel_format_to_fourcc(pixel_format);
5713 crtc->base.primary->fb->pixel_format = fourcc;
5714 crtc->base.primary->fb->bits_per_pixel =
5715 drm_format_plane_cpp(fourcc, 0) * 8;
5717 if (INTEL_INFO(dev)->gen >= 4) {
5718 if (plane_config->tiled)
5719 offset = I915_READ(DSPTILEOFF(plane));
5721 offset = I915_READ(DSPLINOFF(plane));
5722 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5724 base = I915_READ(DSPADDR(plane));
5726 plane_config->base = base;
5728 val = I915_READ(PIPESRC(pipe));
5729 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5730 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5732 val = I915_READ(DSPSTRIDE(pipe));
5733 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5735 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5736 plane_config->tiled);
5738 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5739 aligned_height, PAGE_SIZE);
5741 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5742 pipe, plane, crtc->base.primary->fb->width,
5743 crtc->base.primary->fb->height,
5744 crtc->base.primary->fb->bits_per_pixel, base,
5745 crtc->base.primary->fb->pitches[0],
5746 plane_config->size);
5750 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5751 struct intel_crtc_config *pipe_config)
5753 struct drm_device *dev = crtc->base.dev;
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5757 if (!intel_display_power_enabled(dev_priv,
5758 POWER_DOMAIN_PIPE(crtc->pipe)))
5761 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5762 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5764 tmp = I915_READ(PIPECONF(crtc->pipe));
5765 if (!(tmp & PIPECONF_ENABLE))
5768 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5769 switch (tmp & PIPECONF_BPC_MASK) {
5771 pipe_config->pipe_bpp = 18;
5774 pipe_config->pipe_bpp = 24;
5776 case PIPECONF_10BPC:
5777 pipe_config->pipe_bpp = 30;
5784 if (INTEL_INFO(dev)->gen < 4)
5785 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5787 intel_get_pipe_timings(crtc, pipe_config);
5789 i9xx_get_pfit_config(crtc, pipe_config);
5791 if (INTEL_INFO(dev)->gen >= 4) {
5792 tmp = I915_READ(DPLL_MD(crtc->pipe));
5793 pipe_config->pixel_multiplier =
5794 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5795 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5796 pipe_config->dpll_hw_state.dpll_md = tmp;
5797 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5798 tmp = I915_READ(DPLL(crtc->pipe));
5799 pipe_config->pixel_multiplier =
5800 ((tmp & SDVO_MULTIPLIER_MASK)
5801 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5803 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5804 * port and will be fixed up in the encoder->get_config
5806 pipe_config->pixel_multiplier = 1;
5808 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5809 if (!IS_VALLEYVIEW(dev)) {
5810 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5811 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5813 /* Mask out read-only status bits. */
5814 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5815 DPLL_PORTC_READY_MASK |
5816 DPLL_PORTB_READY_MASK);
5819 if (IS_VALLEYVIEW(dev))
5820 vlv_crtc_clock_get(crtc, pipe_config);
5822 i9xx_crtc_clock_get(crtc, pipe_config);
5827 static void ironlake_init_pch_refclk(struct drm_device *dev)
5829 struct drm_i915_private *dev_priv = dev->dev_private;
5830 struct drm_mode_config *mode_config = &dev->mode_config;
5831 struct intel_encoder *encoder;
5833 bool has_lvds = false;
5834 bool has_cpu_edp = false;
5835 bool has_panel = false;
5836 bool has_ck505 = false;
5837 bool can_ssc = false;
5839 /* We need to take the global config into account */
5840 list_for_each_entry(encoder, &mode_config->encoder_list,
5842 switch (encoder->type) {
5843 case INTEL_OUTPUT_LVDS:
5847 case INTEL_OUTPUT_EDP:
5849 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5855 if (HAS_PCH_IBX(dev)) {
5856 has_ck505 = dev_priv->vbt.display_clock_mode;
5857 can_ssc = has_ck505;
5863 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5864 has_panel, has_lvds, has_ck505);
5866 /* Ironlake: try to setup display ref clock before DPLL
5867 * enabling. This is only under driver's control after
5868 * PCH B stepping, previous chipset stepping should be
5869 * ignoring this setting.
5871 val = I915_READ(PCH_DREF_CONTROL);
5873 /* As we must carefully and slowly disable/enable each source in turn,
5874 * compute the final state we want first and check if we need to
5875 * make any changes at all.
5878 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5880 final |= DREF_NONSPREAD_CK505_ENABLE;
5882 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5884 final &= ~DREF_SSC_SOURCE_MASK;
5885 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5886 final &= ~DREF_SSC1_ENABLE;
5889 final |= DREF_SSC_SOURCE_ENABLE;
5891 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5892 final |= DREF_SSC1_ENABLE;
5895 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5896 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5898 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5900 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5902 final |= DREF_SSC_SOURCE_DISABLE;
5903 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5909 /* Always enable nonspread source */
5910 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5913 val |= DREF_NONSPREAD_CK505_ENABLE;
5915 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5918 val &= ~DREF_SSC_SOURCE_MASK;
5919 val |= DREF_SSC_SOURCE_ENABLE;
5921 /* SSC must be turned on before enabling the CPU output */
5922 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5923 DRM_DEBUG_KMS("Using SSC on panel\n");
5924 val |= DREF_SSC1_ENABLE;
5926 val &= ~DREF_SSC1_ENABLE;
5928 /* Get SSC going before enabling the outputs */
5929 I915_WRITE(PCH_DREF_CONTROL, val);
5930 POSTING_READ(PCH_DREF_CONTROL);
5933 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5935 /* Enable CPU source on CPU attached eDP */
5937 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5938 DRM_DEBUG_KMS("Using SSC on eDP\n");
5939 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5942 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5944 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5946 I915_WRITE(PCH_DREF_CONTROL, val);
5947 POSTING_READ(PCH_DREF_CONTROL);
5950 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5952 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5954 /* Turn off CPU output */
5955 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5957 I915_WRITE(PCH_DREF_CONTROL, val);
5958 POSTING_READ(PCH_DREF_CONTROL);
5961 /* Turn off the SSC source */
5962 val &= ~DREF_SSC_SOURCE_MASK;
5963 val |= DREF_SSC_SOURCE_DISABLE;
5966 val &= ~DREF_SSC1_ENABLE;
5968 I915_WRITE(PCH_DREF_CONTROL, val);
5969 POSTING_READ(PCH_DREF_CONTROL);
5973 BUG_ON(val != final);
5976 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5980 tmp = I915_READ(SOUTH_CHICKEN2);
5981 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5982 I915_WRITE(SOUTH_CHICKEN2, tmp);
5984 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5985 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5986 DRM_ERROR("FDI mPHY reset assert timeout\n");
5988 tmp = I915_READ(SOUTH_CHICKEN2);
5989 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5990 I915_WRITE(SOUTH_CHICKEN2, tmp);
5992 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5993 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5994 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5997 /* WaMPhyProgramming:hsw */
5998 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6002 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6003 tmp &= ~(0xFF << 24);
6004 tmp |= (0x12 << 24);
6005 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6007 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6009 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6011 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6013 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6015 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6016 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6017 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6019 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6020 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6021 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6023 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6026 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6028 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6031 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6033 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6036 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6038 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6041 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6043 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6044 tmp &= ~(0xFF << 16);
6045 tmp |= (0x1C << 16);
6046 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6048 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6049 tmp &= ~(0xFF << 16);
6050 tmp |= (0x1C << 16);
6051 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6053 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6055 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6057 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6059 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6061 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6062 tmp &= ~(0xF << 28);
6064 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6066 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6067 tmp &= ~(0xF << 28);
6069 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6072 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6073 * Programming" based on the parameters passed:
6074 * - Sequence to enable CLKOUT_DP
6075 * - Sequence to enable CLKOUT_DP without spread
6076 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6078 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6084 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6086 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6087 with_fdi, "LP PCH doesn't have FDI\n"))
6090 mutex_lock(&dev_priv->dpio_lock);
6092 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6093 tmp &= ~SBI_SSCCTL_DISABLE;
6094 tmp |= SBI_SSCCTL_PATHALT;
6095 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6100 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6101 tmp &= ~SBI_SSCCTL_PATHALT;
6102 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6105 lpt_reset_fdi_mphy(dev_priv);
6106 lpt_program_fdi_mphy(dev_priv);
6110 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6111 SBI_GEN0 : SBI_DBUFF0;
6112 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6113 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6114 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6116 mutex_unlock(&dev_priv->dpio_lock);
6119 /* Sequence to disable CLKOUT_DP */
6120 static void lpt_disable_clkout_dp(struct drm_device *dev)
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6125 mutex_lock(&dev_priv->dpio_lock);
6127 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6128 SBI_GEN0 : SBI_DBUFF0;
6129 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6130 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6131 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6133 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6134 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6135 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6136 tmp |= SBI_SSCCTL_PATHALT;
6137 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6140 tmp |= SBI_SSCCTL_DISABLE;
6141 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6144 mutex_unlock(&dev_priv->dpio_lock);
6147 static void lpt_init_pch_refclk(struct drm_device *dev)
6149 struct drm_mode_config *mode_config = &dev->mode_config;
6150 struct intel_encoder *encoder;
6151 bool has_vga = false;
6153 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6154 switch (encoder->type) {
6155 case INTEL_OUTPUT_ANALOG:
6162 lpt_enable_clkout_dp(dev, true, true);
6164 lpt_disable_clkout_dp(dev);
6168 * Initialize reference clocks when the driver loads
6170 void intel_init_pch_refclk(struct drm_device *dev)
6172 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6173 ironlake_init_pch_refclk(dev);
6174 else if (HAS_PCH_LPT(dev))
6175 lpt_init_pch_refclk(dev);
6178 static int ironlake_get_refclk(struct drm_crtc *crtc)
6180 struct drm_device *dev = crtc->dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182 struct intel_encoder *encoder;
6183 int num_connectors = 0;
6184 bool is_lvds = false;
6186 for_each_encoder_on_crtc(dev, crtc, encoder) {
6187 switch (encoder->type) {
6188 case INTEL_OUTPUT_LVDS:
6195 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6196 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6197 dev_priv->vbt.lvds_ssc_freq);
6198 return dev_priv->vbt.lvds_ssc_freq;
6204 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6206 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 int pipe = intel_crtc->pipe;
6213 switch (intel_crtc->config.pipe_bpp) {
6215 val |= PIPECONF_6BPC;
6218 val |= PIPECONF_8BPC;
6221 val |= PIPECONF_10BPC;
6224 val |= PIPECONF_12BPC;
6227 /* Case prevented by intel_choose_pipe_bpp_dither. */
6231 if (intel_crtc->config.dither)
6232 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6234 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6235 val |= PIPECONF_INTERLACED_ILK;
6237 val |= PIPECONF_PROGRESSIVE;
6239 if (intel_crtc->config.limited_color_range)
6240 val |= PIPECONF_COLOR_RANGE_SELECT;
6242 I915_WRITE(PIPECONF(pipe), val);
6243 POSTING_READ(PIPECONF(pipe));
6247 * Set up the pipe CSC unit.
6249 * Currently only full range RGB to limited range RGB conversion
6250 * is supported, but eventually this should handle various
6251 * RGB<->YCbCr scenarios as well.
6253 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6255 struct drm_device *dev = crtc->dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6258 int pipe = intel_crtc->pipe;
6259 uint16_t coeff = 0x7800; /* 1.0 */
6262 * TODO: Check what kind of values actually come out of the pipe
6263 * with these coeff/postoff values and adjust to get the best
6264 * accuracy. Perhaps we even need to take the bpc value into
6268 if (intel_crtc->config.limited_color_range)
6269 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6272 * GY/GU and RY/RU should be the other way around according
6273 * to BSpec, but reality doesn't agree. Just set them up in
6274 * a way that results in the correct picture.
6276 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6277 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6279 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6280 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6282 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6283 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6285 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6286 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6287 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6289 if (INTEL_INFO(dev)->gen > 6) {
6290 uint16_t postoff = 0;
6292 if (intel_crtc->config.limited_color_range)
6293 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6295 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6296 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6297 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6299 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6301 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6303 if (intel_crtc->config.limited_color_range)
6304 mode |= CSC_BLACK_SCREEN_OFFSET;
6306 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6310 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6312 struct drm_device *dev = crtc->dev;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315 enum pipe pipe = intel_crtc->pipe;
6316 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6321 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6322 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6324 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6325 val |= PIPECONF_INTERLACED_ILK;
6327 val |= PIPECONF_PROGRESSIVE;
6329 I915_WRITE(PIPECONF(cpu_transcoder), val);
6330 POSTING_READ(PIPECONF(cpu_transcoder));
6332 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6333 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6335 if (IS_BROADWELL(dev)) {
6338 switch (intel_crtc->config.pipe_bpp) {
6340 val |= PIPEMISC_DITHER_6_BPC;
6343 val |= PIPEMISC_DITHER_8_BPC;
6346 val |= PIPEMISC_DITHER_10_BPC;
6349 val |= PIPEMISC_DITHER_12_BPC;
6352 /* Case prevented by pipe_config_set_bpp. */
6356 if (intel_crtc->config.dither)
6357 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6359 I915_WRITE(PIPEMISC(pipe), val);
6363 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6364 intel_clock_t *clock,
6365 bool *has_reduced_clock,
6366 intel_clock_t *reduced_clock)
6368 struct drm_device *dev = crtc->dev;
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_encoder *intel_encoder;
6372 const intel_limit_t *limit;
6373 bool ret, is_lvds = false;
6375 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6376 switch (intel_encoder->type) {
6377 case INTEL_OUTPUT_LVDS:
6383 refclk = ironlake_get_refclk(crtc);
6386 * Returns a set of divisors for the desired target clock with the given
6387 * refclk, or FALSE. The returned values represent the clock equation:
6388 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6390 limit = intel_limit(crtc, refclk);
6391 ret = dev_priv->display.find_dpll(limit, crtc,
6392 to_intel_crtc(crtc)->config.port_clock,
6393 refclk, NULL, clock);
6397 if (is_lvds && dev_priv->lvds_downclock_avail) {
6399 * Ensure we match the reduced clock's P to the target clock.
6400 * If the clocks don't match, we can't switch the display clock
6401 * by using the FP0/FP1. In such case we will disable the LVDS
6402 * downclock feature.
6404 *has_reduced_clock =
6405 dev_priv->display.find_dpll(limit, crtc,
6406 dev_priv->lvds_downclock,
6414 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6417 * Account for spread spectrum to avoid
6418 * oversubscribing the link. Max center spread
6419 * is 2.5%; use 5% for safety's sake.
6421 u32 bps = target_clock * bpp * 21 / 20;
6422 return DIV_ROUND_UP(bps, link_bw * 8);
6425 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6427 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6430 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6432 intel_clock_t *reduced_clock, u32 *fp2)
6434 struct drm_crtc *crtc = &intel_crtc->base;
6435 struct drm_device *dev = crtc->dev;
6436 struct drm_i915_private *dev_priv = dev->dev_private;
6437 struct intel_encoder *intel_encoder;
6439 int factor, num_connectors = 0;
6440 bool is_lvds = false, is_sdvo = false;
6442 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6443 switch (intel_encoder->type) {
6444 case INTEL_OUTPUT_LVDS:
6447 case INTEL_OUTPUT_SDVO:
6448 case INTEL_OUTPUT_HDMI:
6456 /* Enable autotuning of the PLL clock (if permissible) */
6459 if ((intel_panel_use_ssc(dev_priv) &&
6460 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6461 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6463 } else if (intel_crtc->config.sdvo_tv_clock)
6466 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6469 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6475 dpll |= DPLLB_MODE_LVDS;
6477 dpll |= DPLLB_MODE_DAC_SERIAL;
6479 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6480 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6483 dpll |= DPLL_SDVO_HIGH_SPEED;
6484 if (intel_crtc->config.has_dp_encoder)
6485 dpll |= DPLL_SDVO_HIGH_SPEED;
6487 /* compute bitmask from p1 value */
6488 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6490 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6492 switch (intel_crtc->config.dpll.p2) {
6494 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6497 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6500 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6503 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6507 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6508 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6510 dpll |= PLL_REF_INPUT_DREFCLK;
6512 return dpll | DPLL_VCO_ENABLE;
6515 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6517 struct drm_framebuffer *fb)
6519 struct drm_device *dev = crtc->dev;
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6522 int pipe = intel_crtc->pipe;
6523 int plane = intel_crtc->plane;
6524 int num_connectors = 0;
6525 intel_clock_t clock, reduced_clock;
6526 u32 dpll = 0, fp = 0, fp2 = 0;
6527 bool ok, has_reduced_clock = false;
6528 bool is_lvds = false;
6529 struct intel_encoder *encoder;
6530 struct intel_shared_dpll *pll;
6533 for_each_encoder_on_crtc(dev, crtc, encoder) {
6534 switch (encoder->type) {
6535 case INTEL_OUTPUT_LVDS:
6543 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6544 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6546 ok = ironlake_compute_clocks(crtc, &clock,
6547 &has_reduced_clock, &reduced_clock);
6548 if (!ok && !intel_crtc->config.clock_set) {
6549 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6552 /* Compat-code for transition, will disappear. */
6553 if (!intel_crtc->config.clock_set) {
6554 intel_crtc->config.dpll.n = clock.n;
6555 intel_crtc->config.dpll.m1 = clock.m1;
6556 intel_crtc->config.dpll.m2 = clock.m2;
6557 intel_crtc->config.dpll.p1 = clock.p1;
6558 intel_crtc->config.dpll.p2 = clock.p2;
6561 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6562 if (intel_crtc->config.has_pch_encoder) {
6563 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6564 if (has_reduced_clock)
6565 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6567 dpll = ironlake_compute_dpll(intel_crtc,
6568 &fp, &reduced_clock,
6569 has_reduced_clock ? &fp2 : NULL);
6571 intel_crtc->config.dpll_hw_state.dpll = dpll;
6572 intel_crtc->config.dpll_hw_state.fp0 = fp;
6573 if (has_reduced_clock)
6574 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6576 intel_crtc->config.dpll_hw_state.fp1 = fp;
6578 pll = intel_get_shared_dpll(intel_crtc);
6580 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6585 intel_put_shared_dpll(intel_crtc);
6587 if (intel_crtc->config.has_dp_encoder)
6588 intel_dp_set_m_n(intel_crtc);
6590 if (is_lvds && has_reduced_clock && i915.powersave)
6591 intel_crtc->lowfreq_avail = true;
6593 intel_crtc->lowfreq_avail = false;
6595 intel_set_pipe_timings(intel_crtc);
6597 if (intel_crtc->config.has_pch_encoder) {
6598 intel_cpu_transcoder_set_m_n(intel_crtc,
6599 &intel_crtc->config.fdi_m_n);
6602 ironlake_set_pipeconf(crtc);
6604 /* Set up the display plane register */
6605 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6606 POSTING_READ(DSPCNTR(plane));
6608 ret = intel_pipe_set_base(crtc, x, y, fb);
6613 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6614 struct intel_link_m_n *m_n)
6616 struct drm_device *dev = crtc->base.dev;
6617 struct drm_i915_private *dev_priv = dev->dev_private;
6618 enum pipe pipe = crtc->pipe;
6620 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6621 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6622 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6624 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6625 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6626 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6629 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6630 enum transcoder transcoder,
6631 struct intel_link_m_n *m_n)
6633 struct drm_device *dev = crtc->base.dev;
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635 enum pipe pipe = crtc->pipe;
6637 if (INTEL_INFO(dev)->gen >= 5) {
6638 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6639 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6640 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6642 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6643 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6644 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6646 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6647 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6648 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6650 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6651 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6652 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6656 void intel_dp_get_m_n(struct intel_crtc *crtc,
6657 struct intel_crtc_config *pipe_config)
6659 if (crtc->config.has_pch_encoder)
6660 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6662 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6663 &pipe_config->dp_m_n);
6666 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6667 struct intel_crtc_config *pipe_config)
6669 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6670 &pipe_config->fdi_m_n);
6673 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6674 struct intel_crtc_config *pipe_config)
6676 struct drm_device *dev = crtc->base.dev;
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6680 tmp = I915_READ(PF_CTL(crtc->pipe));
6682 if (tmp & PF_ENABLE) {
6683 pipe_config->pch_pfit.enabled = true;
6684 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6685 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6687 /* We currently do not free assignements of panel fitters on
6688 * ivb/hsw (since we don't use the higher upscaling modes which
6689 * differentiates them) so just WARN about this case for now. */
6691 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6692 PF_PIPE_SEL_IVB(crtc->pipe));
6697 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6698 struct intel_plane_config *plane_config)
6700 struct drm_device *dev = crtc->base.dev;
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 u32 val, base, offset;
6703 int pipe = crtc->pipe, plane = crtc->plane;
6704 int fourcc, pixel_format;
6707 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6708 if (!crtc->base.primary->fb) {
6709 DRM_DEBUG_KMS("failed to alloc fb\n");
6713 val = I915_READ(DSPCNTR(plane));
6715 if (INTEL_INFO(dev)->gen >= 4)
6716 if (val & DISPPLANE_TILED)
6717 plane_config->tiled = true;
6719 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6720 fourcc = intel_format_to_fourcc(pixel_format);
6721 crtc->base.primary->fb->pixel_format = fourcc;
6722 crtc->base.primary->fb->bits_per_pixel =
6723 drm_format_plane_cpp(fourcc, 0) * 8;
6725 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6726 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6727 offset = I915_READ(DSPOFFSET(plane));
6729 if (plane_config->tiled)
6730 offset = I915_READ(DSPTILEOFF(plane));
6732 offset = I915_READ(DSPLINOFF(plane));
6734 plane_config->base = base;
6736 val = I915_READ(PIPESRC(pipe));
6737 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6738 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6740 val = I915_READ(DSPSTRIDE(pipe));
6741 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6743 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6744 plane_config->tiled);
6746 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6747 aligned_height, PAGE_SIZE);
6749 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6750 pipe, plane, crtc->base.primary->fb->width,
6751 crtc->base.primary->fb->height,
6752 crtc->base.primary->fb->bits_per_pixel, base,
6753 crtc->base.primary->fb->pitches[0],
6754 plane_config->size);
6757 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6758 struct intel_crtc_config *pipe_config)
6760 struct drm_device *dev = crtc->base.dev;
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6764 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6765 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6767 tmp = I915_READ(PIPECONF(crtc->pipe));
6768 if (!(tmp & PIPECONF_ENABLE))
6771 switch (tmp & PIPECONF_BPC_MASK) {
6773 pipe_config->pipe_bpp = 18;
6776 pipe_config->pipe_bpp = 24;
6778 case PIPECONF_10BPC:
6779 pipe_config->pipe_bpp = 30;
6781 case PIPECONF_12BPC:
6782 pipe_config->pipe_bpp = 36;
6788 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6789 struct intel_shared_dpll *pll;
6791 pipe_config->has_pch_encoder = true;
6793 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6794 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6795 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6797 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6799 if (HAS_PCH_IBX(dev_priv->dev)) {
6800 pipe_config->shared_dpll =
6801 (enum intel_dpll_id) crtc->pipe;
6803 tmp = I915_READ(PCH_DPLL_SEL);
6804 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6805 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6807 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6810 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6812 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6813 &pipe_config->dpll_hw_state));
6815 tmp = pipe_config->dpll_hw_state.dpll;
6816 pipe_config->pixel_multiplier =
6817 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6818 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6820 ironlake_pch_clock_get(crtc, pipe_config);
6822 pipe_config->pixel_multiplier = 1;
6825 intel_get_pipe_timings(crtc, pipe_config);
6827 ironlake_get_pfit_config(crtc, pipe_config);
6832 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6834 struct drm_device *dev = dev_priv->dev;
6835 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6836 struct intel_crtc *crtc;
6838 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6839 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6840 pipe_name(crtc->pipe));
6842 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6843 WARN(plls->spll_refcount, "SPLL enabled\n");
6844 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6845 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6846 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6847 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6848 "CPU PWM1 enabled\n");
6849 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6850 "CPU PWM2 enabled\n");
6851 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6852 "PCH PWM1 enabled\n");
6853 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6854 "Utility pin enabled\n");
6855 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6858 * In theory we can still leave IRQs enabled, as long as only the HPD
6859 * interrupts remain enabled. We used to check for that, but since it's
6860 * gen-specific and since we only disable LCPLL after we fully disable
6861 * the interrupts, the check below should be enough.
6863 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6866 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6868 struct drm_device *dev = dev_priv->dev;
6870 if (IS_HASWELL(dev)) {
6871 mutex_lock(&dev_priv->rps.hw_lock);
6872 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6874 DRM_ERROR("Failed to disable D_COMP\n");
6875 mutex_unlock(&dev_priv->rps.hw_lock);
6877 I915_WRITE(D_COMP, val);
6879 POSTING_READ(D_COMP);
6883 * This function implements pieces of two sequences from BSpec:
6884 * - Sequence for display software to disable LCPLL
6885 * - Sequence for display software to allow package C8+
6886 * The steps implemented here are just the steps that actually touch the LCPLL
6887 * register. Callers should take care of disabling all the display engine
6888 * functions, doing the mode unset, fixing interrupts, etc.
6890 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6891 bool switch_to_fclk, bool allow_power_down)
6895 assert_can_disable_lcpll(dev_priv);
6897 val = I915_READ(LCPLL_CTL);
6899 if (switch_to_fclk) {
6900 val |= LCPLL_CD_SOURCE_FCLK;
6901 I915_WRITE(LCPLL_CTL, val);
6903 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6904 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6905 DRM_ERROR("Switching to FCLK failed\n");
6907 val = I915_READ(LCPLL_CTL);
6910 val |= LCPLL_PLL_DISABLE;
6911 I915_WRITE(LCPLL_CTL, val);
6912 POSTING_READ(LCPLL_CTL);
6914 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6915 DRM_ERROR("LCPLL still locked\n");
6917 val = I915_READ(D_COMP);
6918 val |= D_COMP_COMP_DISABLE;
6919 hsw_write_dcomp(dev_priv, val);
6922 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6923 DRM_ERROR("D_COMP RCOMP still in progress\n");
6925 if (allow_power_down) {
6926 val = I915_READ(LCPLL_CTL);
6927 val |= LCPLL_POWER_DOWN_ALLOW;
6928 I915_WRITE(LCPLL_CTL, val);
6929 POSTING_READ(LCPLL_CTL);
6934 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6937 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6940 unsigned long irqflags;
6942 val = I915_READ(LCPLL_CTL);
6944 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6945 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6949 * Make sure we're not on PC8 state before disabling PC8, otherwise
6950 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6952 * The other problem is that hsw_restore_lcpll() is called as part of
6953 * the runtime PM resume sequence, so we can't just call
6954 * gen6_gt_force_wake_get() because that function calls
6955 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6956 * while we are on the resume sequence. So to solve this problem we have
6957 * to call special forcewake code that doesn't touch runtime PM and
6958 * doesn't enable the forcewake delayed work.
6960 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6961 if (dev_priv->uncore.forcewake_count++ == 0)
6962 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6963 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6965 if (val & LCPLL_POWER_DOWN_ALLOW) {
6966 val &= ~LCPLL_POWER_DOWN_ALLOW;
6967 I915_WRITE(LCPLL_CTL, val);
6968 POSTING_READ(LCPLL_CTL);
6971 val = I915_READ(D_COMP);
6972 val |= D_COMP_COMP_FORCE;
6973 val &= ~D_COMP_COMP_DISABLE;
6974 hsw_write_dcomp(dev_priv, val);
6976 val = I915_READ(LCPLL_CTL);
6977 val &= ~LCPLL_PLL_DISABLE;
6978 I915_WRITE(LCPLL_CTL, val);
6980 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6981 DRM_ERROR("LCPLL not locked yet\n");
6983 if (val & LCPLL_CD_SOURCE_FCLK) {
6984 val = I915_READ(LCPLL_CTL);
6985 val &= ~LCPLL_CD_SOURCE_FCLK;
6986 I915_WRITE(LCPLL_CTL, val);
6988 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6989 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6990 DRM_ERROR("Switching back to LCPLL failed\n");
6993 /* See the big comment above. */
6994 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6995 if (--dev_priv->uncore.forcewake_count == 0)
6996 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6997 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7001 * Package states C8 and deeper are really deep PC states that can only be
7002 * reached when all the devices on the system allow it, so even if the graphics
7003 * device allows PC8+, it doesn't mean the system will actually get to these
7004 * states. Our driver only allows PC8+ when going into runtime PM.
7006 * The requirements for PC8+ are that all the outputs are disabled, the power
7007 * well is disabled and most interrupts are disabled, and these are also
7008 * requirements for runtime PM. When these conditions are met, we manually do
7009 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7010 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7013 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7014 * the state of some registers, so when we come back from PC8+ we need to
7015 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7016 * need to take care of the registers kept by RC6. Notice that this happens even
7017 * if we don't put the device in PCI D3 state (which is what currently happens
7018 * because of the runtime PM support).
7020 * For more, read "Display Sequences for Package C8" on the hardware
7023 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7025 struct drm_device *dev = dev_priv->dev;
7028 DRM_DEBUG_KMS("Enabling package C8+\n");
7030 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7031 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7032 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7033 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7036 lpt_disable_clkout_dp(dev);
7037 hsw_disable_lcpll(dev_priv, true, true);
7040 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7042 struct drm_device *dev = dev_priv->dev;
7045 DRM_DEBUG_KMS("Disabling package C8+\n");
7047 hsw_restore_lcpll(dev_priv);
7048 lpt_init_pch_refclk(dev);
7050 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7051 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7052 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7053 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7056 intel_prepare_ddi(dev);
7059 static void snb_modeset_global_resources(struct drm_device *dev)
7061 modeset_update_crtc_power_domains(dev);
7064 static void haswell_modeset_global_resources(struct drm_device *dev)
7066 modeset_update_crtc_power_domains(dev);
7069 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7071 struct drm_framebuffer *fb)
7073 struct drm_device *dev = crtc->dev;
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076 int plane = intel_crtc->plane;
7079 if (!intel_ddi_pll_select(intel_crtc))
7081 intel_ddi_pll_enable(intel_crtc);
7083 if (intel_crtc->config.has_dp_encoder)
7084 intel_dp_set_m_n(intel_crtc);
7086 intel_crtc->lowfreq_avail = false;
7088 intel_set_pipe_timings(intel_crtc);
7090 if (intel_crtc->config.has_pch_encoder) {
7091 intel_cpu_transcoder_set_m_n(intel_crtc,
7092 &intel_crtc->config.fdi_m_n);
7095 haswell_set_pipeconf(crtc);
7097 intel_set_pipe_csc(crtc);
7099 /* Set up the display plane register */
7100 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7101 POSTING_READ(DSPCNTR(plane));
7103 ret = intel_pipe_set_base(crtc, x, y, fb);
7108 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7109 struct intel_crtc_config *pipe_config)
7111 struct drm_device *dev = crtc->base.dev;
7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 enum intel_display_power_domain pfit_domain;
7116 if (!intel_display_power_enabled(dev_priv,
7117 POWER_DOMAIN_PIPE(crtc->pipe)))
7120 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7121 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7123 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7124 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7125 enum pipe trans_edp_pipe;
7126 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7128 WARN(1, "unknown pipe linked to edp transcoder\n");
7129 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7130 case TRANS_DDI_EDP_INPUT_A_ON:
7131 trans_edp_pipe = PIPE_A;
7133 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7134 trans_edp_pipe = PIPE_B;
7136 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7137 trans_edp_pipe = PIPE_C;
7141 if (trans_edp_pipe == crtc->pipe)
7142 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7145 if (!intel_display_power_enabled(dev_priv,
7146 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7149 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7150 if (!(tmp & PIPECONF_ENABLE))
7154 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7155 * DDI E. So just check whether this pipe is wired to DDI E and whether
7156 * the PCH transcoder is on.
7158 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7159 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7160 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7161 pipe_config->has_pch_encoder = true;
7163 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7164 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7165 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7167 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7170 intel_get_pipe_timings(crtc, pipe_config);
7172 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7173 if (intel_display_power_enabled(dev_priv, pfit_domain))
7174 ironlake_get_pfit_config(crtc, pipe_config);
7176 if (IS_HASWELL(dev))
7177 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7178 (I915_READ(IPS_CTL) & IPS_ENABLE);
7180 pipe_config->pixel_multiplier = 1;
7185 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7187 struct drm_framebuffer *fb)
7189 struct drm_device *dev = crtc->dev;
7190 struct drm_i915_private *dev_priv = dev->dev_private;
7191 struct intel_encoder *encoder;
7192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7194 int pipe = intel_crtc->pipe;
7197 drm_vblank_pre_modeset(dev, pipe);
7199 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7201 drm_vblank_post_modeset(dev, pipe);
7206 for_each_encoder_on_crtc(dev, crtc, encoder) {
7207 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7208 encoder->base.base.id,
7209 drm_get_encoder_name(&encoder->base),
7210 mode->base.id, mode->name);
7211 encoder->mode_set(encoder);
7220 } hdmi_audio_clock[] = {
7221 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7222 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7223 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7224 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7225 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7226 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7227 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7228 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7229 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7230 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7233 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7234 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7238 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7239 if (mode->clock == hdmi_audio_clock[i].clock)
7243 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7244 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7248 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7249 hdmi_audio_clock[i].clock,
7250 hdmi_audio_clock[i].config);
7252 return hdmi_audio_clock[i].config;
7255 static bool intel_eld_uptodate(struct drm_connector *connector,
7256 int reg_eldv, uint32_t bits_eldv,
7257 int reg_elda, uint32_t bits_elda,
7260 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7261 uint8_t *eld = connector->eld;
7264 i = I915_READ(reg_eldv);
7273 i = I915_READ(reg_elda);
7275 I915_WRITE(reg_elda, i);
7277 for (i = 0; i < eld[2]; i++)
7278 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7284 static void g4x_write_eld(struct drm_connector *connector,
7285 struct drm_crtc *crtc,
7286 struct drm_display_mode *mode)
7288 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7289 uint8_t *eld = connector->eld;
7294 i = I915_READ(G4X_AUD_VID_DID);
7296 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7297 eldv = G4X_ELDV_DEVCL_DEVBLC;
7299 eldv = G4X_ELDV_DEVCTG;
7301 if (intel_eld_uptodate(connector,
7302 G4X_AUD_CNTL_ST, eldv,
7303 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7304 G4X_HDMIW_HDMIEDID))
7307 i = I915_READ(G4X_AUD_CNTL_ST);
7308 i &= ~(eldv | G4X_ELD_ADDR);
7309 len = (i >> 9) & 0x1f; /* ELD buffer size */
7310 I915_WRITE(G4X_AUD_CNTL_ST, i);
7315 len = min_t(uint8_t, eld[2], len);
7316 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7317 for (i = 0; i < len; i++)
7318 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7320 i = I915_READ(G4X_AUD_CNTL_ST);
7322 I915_WRITE(G4X_AUD_CNTL_ST, i);
7325 static void haswell_write_eld(struct drm_connector *connector,
7326 struct drm_crtc *crtc,
7327 struct drm_display_mode *mode)
7329 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7330 uint8_t *eld = connector->eld;
7331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7335 int pipe = to_intel_crtc(crtc)->pipe;
7338 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7339 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7340 int aud_config = HSW_AUD_CFG(pipe);
7341 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7343 /* Audio output enable */
7344 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7345 tmp = I915_READ(aud_cntrl_st2);
7346 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7347 I915_WRITE(aud_cntrl_st2, tmp);
7348 POSTING_READ(aud_cntrl_st2);
7350 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7352 /* Set ELD valid state */
7353 tmp = I915_READ(aud_cntrl_st2);
7354 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7355 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7356 I915_WRITE(aud_cntrl_st2, tmp);
7357 tmp = I915_READ(aud_cntrl_st2);
7358 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7360 /* Enable HDMI mode */
7361 tmp = I915_READ(aud_config);
7362 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7363 /* clear N_programing_enable and N_value_index */
7364 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7365 I915_WRITE(aud_config, tmp);
7367 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7369 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7370 intel_crtc->eld_vld = true;
7372 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7373 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7374 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7375 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7377 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7380 if (intel_eld_uptodate(connector,
7381 aud_cntrl_st2, eldv,
7382 aud_cntl_st, IBX_ELD_ADDRESS,
7386 i = I915_READ(aud_cntrl_st2);
7388 I915_WRITE(aud_cntrl_st2, i);
7393 i = I915_READ(aud_cntl_st);
7394 i &= ~IBX_ELD_ADDRESS;
7395 I915_WRITE(aud_cntl_st, i);
7396 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7397 DRM_DEBUG_DRIVER("port num:%d\n", i);
7399 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7400 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7401 for (i = 0; i < len; i++)
7402 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7404 i = I915_READ(aud_cntrl_st2);
7406 I915_WRITE(aud_cntrl_st2, i);
7410 static void ironlake_write_eld(struct drm_connector *connector,
7411 struct drm_crtc *crtc,
7412 struct drm_display_mode *mode)
7414 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7415 uint8_t *eld = connector->eld;
7423 int pipe = to_intel_crtc(crtc)->pipe;
7425 if (HAS_PCH_IBX(connector->dev)) {
7426 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7427 aud_config = IBX_AUD_CFG(pipe);
7428 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7429 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7430 } else if (IS_VALLEYVIEW(connector->dev)) {
7431 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7432 aud_config = VLV_AUD_CFG(pipe);
7433 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7434 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7436 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7437 aud_config = CPT_AUD_CFG(pipe);
7438 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7439 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7442 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7444 if (IS_VALLEYVIEW(connector->dev)) {
7445 struct intel_encoder *intel_encoder;
7446 struct intel_digital_port *intel_dig_port;
7448 intel_encoder = intel_attached_encoder(connector);
7449 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7450 i = intel_dig_port->port;
7452 i = I915_READ(aud_cntl_st);
7453 i = (i >> 29) & DIP_PORT_SEL_MASK;
7454 /* DIP_Port_Select, 0x1 = PortB */
7458 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7459 /* operate blindly on all ports */
7460 eldv = IBX_ELD_VALIDB;
7461 eldv |= IBX_ELD_VALIDB << 4;
7462 eldv |= IBX_ELD_VALIDB << 8;
7464 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7465 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7468 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7469 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7470 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7471 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7473 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7476 if (intel_eld_uptodate(connector,
7477 aud_cntrl_st2, eldv,
7478 aud_cntl_st, IBX_ELD_ADDRESS,
7482 i = I915_READ(aud_cntrl_st2);
7484 I915_WRITE(aud_cntrl_st2, i);
7489 i = I915_READ(aud_cntl_st);
7490 i &= ~IBX_ELD_ADDRESS;
7491 I915_WRITE(aud_cntl_st, i);
7493 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7494 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7495 for (i = 0; i < len; i++)
7496 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7498 i = I915_READ(aud_cntrl_st2);
7500 I915_WRITE(aud_cntrl_st2, i);
7503 void intel_write_eld(struct drm_encoder *encoder,
7504 struct drm_display_mode *mode)
7506 struct drm_crtc *crtc = encoder->crtc;
7507 struct drm_connector *connector;
7508 struct drm_device *dev = encoder->dev;
7509 struct drm_i915_private *dev_priv = dev->dev_private;
7511 connector = drm_select_eld(encoder, mode);
7515 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7517 drm_get_connector_name(connector),
7518 connector->encoder->base.id,
7519 drm_get_encoder_name(connector->encoder));
7521 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7523 if (dev_priv->display.write_eld)
7524 dev_priv->display.write_eld(connector, crtc, mode);
7527 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7529 struct drm_device *dev = crtc->dev;
7530 struct drm_i915_private *dev_priv = dev->dev_private;
7531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7532 bool visible = base != 0;
7535 if (intel_crtc->cursor_visible == visible)
7538 cntl = I915_READ(_CURACNTR);
7540 /* On these chipsets we can only modify the base whilst
7541 * the cursor is disabled.
7543 I915_WRITE(_CURABASE, base);
7545 cntl &= ~(CURSOR_FORMAT_MASK);
7546 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7547 cntl |= CURSOR_ENABLE |
7548 CURSOR_GAMMA_ENABLE |
7551 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7552 I915_WRITE(_CURACNTR, cntl);
7554 intel_crtc->cursor_visible = visible;
7557 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7559 struct drm_device *dev = crtc->dev;
7560 struct drm_i915_private *dev_priv = dev->dev_private;
7561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7562 int pipe = intel_crtc->pipe;
7563 bool visible = base != 0;
7565 if (intel_crtc->cursor_visible != visible) {
7566 int16_t width = intel_crtc->cursor_width;
7567 uint32_t cntl = I915_READ(CURCNTR(pipe));
7569 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7570 cntl |= MCURSOR_GAMMA_ENABLE;
7574 cntl |= CURSOR_MODE_64_ARGB_AX;
7577 cntl |= CURSOR_MODE_128_ARGB_AX;
7580 cntl |= CURSOR_MODE_256_ARGB_AX;
7586 cntl |= pipe << 28; /* Connect to correct pipe */
7588 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7589 cntl |= CURSOR_MODE_DISABLE;
7591 I915_WRITE(CURCNTR(pipe), cntl);
7593 intel_crtc->cursor_visible = visible;
7595 /* and commit changes on next vblank */
7596 POSTING_READ(CURCNTR(pipe));
7597 I915_WRITE(CURBASE(pipe), base);
7598 POSTING_READ(CURBASE(pipe));
7601 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7603 struct drm_device *dev = crtc->dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7606 int pipe = intel_crtc->pipe;
7607 bool visible = base != 0;
7609 if (intel_crtc->cursor_visible != visible) {
7610 int16_t width = intel_crtc->cursor_width;
7611 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7613 cntl &= ~CURSOR_MODE;
7614 cntl |= MCURSOR_GAMMA_ENABLE;
7617 cntl |= CURSOR_MODE_64_ARGB_AX;
7620 cntl |= CURSOR_MODE_128_ARGB_AX;
7623 cntl |= CURSOR_MODE_256_ARGB_AX;
7630 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7631 cntl |= CURSOR_MODE_DISABLE;
7633 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7634 cntl |= CURSOR_PIPE_CSC_ENABLE;
7635 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7637 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7639 intel_crtc->cursor_visible = visible;
7641 /* and commit changes on next vblank */
7642 POSTING_READ(CURCNTR_IVB(pipe));
7643 I915_WRITE(CURBASE_IVB(pipe), base);
7644 POSTING_READ(CURBASE_IVB(pipe));
7647 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7648 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7651 struct drm_device *dev = crtc->dev;
7652 struct drm_i915_private *dev_priv = dev->dev_private;
7653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7654 int pipe = intel_crtc->pipe;
7655 int x = intel_crtc->cursor_x;
7656 int y = intel_crtc->cursor_y;
7657 u32 base = 0, pos = 0;
7661 base = intel_crtc->cursor_addr;
7663 if (x >= intel_crtc->config.pipe_src_w)
7666 if (y >= intel_crtc->config.pipe_src_h)
7670 if (x + intel_crtc->cursor_width <= 0)
7673 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7676 pos |= x << CURSOR_X_SHIFT;
7679 if (y + intel_crtc->cursor_height <= 0)
7682 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7685 pos |= y << CURSOR_Y_SHIFT;
7687 visible = base != 0;
7688 if (!visible && !intel_crtc->cursor_visible)
7691 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7692 I915_WRITE(CURPOS_IVB(pipe), pos);
7693 ivb_update_cursor(crtc, base);
7695 I915_WRITE(CURPOS(pipe), pos);
7696 if (IS_845G(dev) || IS_I865G(dev))
7697 i845_update_cursor(crtc, base);
7699 i9xx_update_cursor(crtc, base);
7703 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7704 struct drm_file *file,
7706 uint32_t width, uint32_t height)
7708 struct drm_device *dev = crtc->dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7711 struct drm_i915_gem_object *obj;
7716 /* if we want to turn off the cursor ignore width and height */
7718 DRM_DEBUG_KMS("cursor off\n");
7721 mutex_lock(&dev->struct_mutex);
7725 /* Check for which cursor types we support */
7726 if (!((width == 64 && height == 64) ||
7727 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7728 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7729 DRM_DEBUG("Cursor dimension not supported\n");
7733 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7734 if (&obj->base == NULL)
7737 if (obj->base.size < width * height * 4) {
7738 DRM_DEBUG_KMS("buffer is to small\n");
7743 /* we only need to pin inside GTT if cursor is non-phy */
7744 mutex_lock(&dev->struct_mutex);
7745 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7748 if (obj->tiling_mode) {
7749 DRM_DEBUG_KMS("cursor cannot be tiled\n");
7754 /* Note that the w/a also requires 2 PTE of padding following
7755 * the bo. We currently fill all unused PTE with the shadow
7756 * page and so we should always have valid PTE following the
7757 * cursor preventing the VT-d warning.
7760 if (need_vtd_wa(dev))
7761 alignment = 64*1024;
7763 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7765 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7769 ret = i915_gem_object_put_fence(obj);
7771 DRM_DEBUG_KMS("failed to release fence for cursor");
7775 addr = i915_gem_obj_ggtt_offset(obj);
7777 int align = IS_I830(dev) ? 16 * 1024 : 256;
7778 ret = i915_gem_attach_phys_object(dev, obj,
7779 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7782 DRM_DEBUG_KMS("failed to attach phys object\n");
7785 addr = obj->phys_obj->handle->busaddr;
7789 I915_WRITE(CURSIZE, (height << 12) | width);
7792 if (intel_crtc->cursor_bo) {
7793 if (INTEL_INFO(dev)->cursor_needs_physical) {
7794 if (intel_crtc->cursor_bo != obj)
7795 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7797 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7798 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7801 mutex_unlock(&dev->struct_mutex);
7803 old_width = intel_crtc->cursor_width;
7805 intel_crtc->cursor_addr = addr;
7806 intel_crtc->cursor_bo = obj;
7807 intel_crtc->cursor_width = width;
7808 intel_crtc->cursor_height = height;
7810 if (intel_crtc->active) {
7811 if (old_width != width)
7812 intel_update_watermarks(crtc);
7813 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7818 i915_gem_object_unpin_from_display_plane(obj);
7820 mutex_unlock(&dev->struct_mutex);
7822 drm_gem_object_unreference_unlocked(&obj->base);
7826 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7830 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7831 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7833 if (intel_crtc->active)
7834 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7839 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7840 u16 *blue, uint32_t start, uint32_t size)
7842 int end = (start + size > 256) ? 256 : start + size, i;
7843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7845 for (i = start; i < end; i++) {
7846 intel_crtc->lut_r[i] = red[i] >> 8;
7847 intel_crtc->lut_g[i] = green[i] >> 8;
7848 intel_crtc->lut_b[i] = blue[i] >> 8;
7851 intel_crtc_load_lut(crtc);
7854 /* VESA 640x480x72Hz mode to set on the pipe */
7855 static struct drm_display_mode load_detect_mode = {
7856 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7857 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7860 struct drm_framebuffer *
7861 __intel_framebuffer_create(struct drm_device *dev,
7862 struct drm_mode_fb_cmd2 *mode_cmd,
7863 struct drm_i915_gem_object *obj)
7865 struct intel_framebuffer *intel_fb;
7868 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7870 drm_gem_object_unreference_unlocked(&obj->base);
7871 return ERR_PTR(-ENOMEM);
7874 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7878 return &intel_fb->base;
7880 drm_gem_object_unreference_unlocked(&obj->base);
7883 return ERR_PTR(ret);
7886 static struct drm_framebuffer *
7887 intel_framebuffer_create(struct drm_device *dev,
7888 struct drm_mode_fb_cmd2 *mode_cmd,
7889 struct drm_i915_gem_object *obj)
7891 struct drm_framebuffer *fb;
7894 ret = i915_mutex_lock_interruptible(dev);
7896 return ERR_PTR(ret);
7897 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7898 mutex_unlock(&dev->struct_mutex);
7904 intel_framebuffer_pitch_for_width(int width, int bpp)
7906 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7907 return ALIGN(pitch, 64);
7911 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7913 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7914 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7917 static struct drm_framebuffer *
7918 intel_framebuffer_create_for_mode(struct drm_device *dev,
7919 struct drm_display_mode *mode,
7922 struct drm_i915_gem_object *obj;
7923 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7925 obj = i915_gem_alloc_object(dev,
7926 intel_framebuffer_size_for_mode(mode, bpp));
7928 return ERR_PTR(-ENOMEM);
7930 mode_cmd.width = mode->hdisplay;
7931 mode_cmd.height = mode->vdisplay;
7932 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7934 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7936 return intel_framebuffer_create(dev, &mode_cmd, obj);
7939 static struct drm_framebuffer *
7940 mode_fits_in_fbdev(struct drm_device *dev,
7941 struct drm_display_mode *mode)
7943 #ifdef CONFIG_DRM_I915_FBDEV
7944 struct drm_i915_private *dev_priv = dev->dev_private;
7945 struct drm_i915_gem_object *obj;
7946 struct drm_framebuffer *fb;
7948 if (!dev_priv->fbdev)
7951 if (!dev_priv->fbdev->fb)
7954 obj = dev_priv->fbdev->fb->obj;
7957 fb = &dev_priv->fbdev->fb->base;
7958 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7959 fb->bits_per_pixel))
7962 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7971 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7972 struct drm_display_mode *mode,
7973 struct intel_load_detect_pipe *old)
7975 struct intel_crtc *intel_crtc;
7976 struct intel_encoder *intel_encoder =
7977 intel_attached_encoder(connector);
7978 struct drm_crtc *possible_crtc;
7979 struct drm_encoder *encoder = &intel_encoder->base;
7980 struct drm_crtc *crtc = NULL;
7981 struct drm_device *dev = encoder->dev;
7982 struct drm_framebuffer *fb;
7985 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7986 connector->base.id, drm_get_connector_name(connector),
7987 encoder->base.id, drm_get_encoder_name(encoder));
7990 * Algorithm gets a little messy:
7992 * - if the connector already has an assigned crtc, use it (but make
7993 * sure it's on first)
7995 * - try to find the first unused crtc that can drive this connector,
7996 * and use that if we find one
7999 /* See if we already have a CRTC for this connector */
8000 if (encoder->crtc) {
8001 crtc = encoder->crtc;
8003 mutex_lock(&crtc->mutex);
8005 old->dpms_mode = connector->dpms;
8006 old->load_detect_temp = false;
8008 /* Make sure the crtc and connector are running */
8009 if (connector->dpms != DRM_MODE_DPMS_ON)
8010 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8015 /* Find an unused one (if possible) */
8016 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8018 if (!(encoder->possible_crtcs & (1 << i)))
8020 if (!possible_crtc->enabled) {
8021 crtc = possible_crtc;
8027 * If we didn't find an unused CRTC, don't use any.
8030 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8034 mutex_lock(&crtc->mutex);
8035 intel_encoder->new_crtc = to_intel_crtc(crtc);
8036 to_intel_connector(connector)->new_encoder = intel_encoder;
8038 intel_crtc = to_intel_crtc(crtc);
8039 intel_crtc->new_enabled = true;
8040 intel_crtc->new_config = &intel_crtc->config;
8041 old->dpms_mode = connector->dpms;
8042 old->load_detect_temp = true;
8043 old->release_fb = NULL;
8046 mode = &load_detect_mode;
8048 /* We need a framebuffer large enough to accommodate all accesses
8049 * that the plane may generate whilst we perform load detection.
8050 * We can not rely on the fbcon either being present (we get called
8051 * during its initialisation to detect all boot displays, or it may
8052 * not even exist) or that it is large enough to satisfy the
8055 fb = mode_fits_in_fbdev(dev, mode);
8057 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8058 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8059 old->release_fb = fb;
8061 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8063 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8067 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8068 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8069 if (old->release_fb)
8070 old->release_fb->funcs->destroy(old->release_fb);
8074 /* let the connector get through one full cycle before testing */
8075 intel_wait_for_vblank(dev, intel_crtc->pipe);
8079 intel_crtc->new_enabled = crtc->enabled;
8080 if (intel_crtc->new_enabled)
8081 intel_crtc->new_config = &intel_crtc->config;
8083 intel_crtc->new_config = NULL;
8084 mutex_unlock(&crtc->mutex);
8088 void intel_release_load_detect_pipe(struct drm_connector *connector,
8089 struct intel_load_detect_pipe *old)
8091 struct intel_encoder *intel_encoder =
8092 intel_attached_encoder(connector);
8093 struct drm_encoder *encoder = &intel_encoder->base;
8094 struct drm_crtc *crtc = encoder->crtc;
8095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8097 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8098 connector->base.id, drm_get_connector_name(connector),
8099 encoder->base.id, drm_get_encoder_name(encoder));
8101 if (old->load_detect_temp) {
8102 to_intel_connector(connector)->new_encoder = NULL;
8103 intel_encoder->new_crtc = NULL;
8104 intel_crtc->new_enabled = false;
8105 intel_crtc->new_config = NULL;
8106 intel_set_mode(crtc, NULL, 0, 0, NULL);
8108 if (old->release_fb) {
8109 drm_framebuffer_unregister_private(old->release_fb);
8110 drm_framebuffer_unreference(old->release_fb);
8113 mutex_unlock(&crtc->mutex);
8117 /* Switch crtc and encoder back off if necessary */
8118 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8119 connector->funcs->dpms(connector, old->dpms_mode);
8121 mutex_unlock(&crtc->mutex);
8124 static int i9xx_pll_refclk(struct drm_device *dev,
8125 const struct intel_crtc_config *pipe_config)
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8128 u32 dpll = pipe_config->dpll_hw_state.dpll;
8130 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8131 return dev_priv->vbt.lvds_ssc_freq;
8132 else if (HAS_PCH_SPLIT(dev))
8134 else if (!IS_GEN2(dev))
8140 /* Returns the clock of the currently programmed mode of the given pipe. */
8141 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8142 struct intel_crtc_config *pipe_config)
8144 struct drm_device *dev = crtc->base.dev;
8145 struct drm_i915_private *dev_priv = dev->dev_private;
8146 int pipe = pipe_config->cpu_transcoder;
8147 u32 dpll = pipe_config->dpll_hw_state.dpll;
8149 intel_clock_t clock;
8150 int refclk = i9xx_pll_refclk(dev, pipe_config);
8152 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8153 fp = pipe_config->dpll_hw_state.fp0;
8155 fp = pipe_config->dpll_hw_state.fp1;
8157 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8158 if (IS_PINEVIEW(dev)) {
8159 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8160 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8162 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8163 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8166 if (!IS_GEN2(dev)) {
8167 if (IS_PINEVIEW(dev))
8168 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8169 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8171 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8172 DPLL_FPA01_P1_POST_DIV_SHIFT);
8174 switch (dpll & DPLL_MODE_MASK) {
8175 case DPLLB_MODE_DAC_SERIAL:
8176 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8179 case DPLLB_MODE_LVDS:
8180 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8184 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8185 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8189 if (IS_PINEVIEW(dev))
8190 pineview_clock(refclk, &clock);
8192 i9xx_clock(refclk, &clock);
8194 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8195 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8198 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8199 DPLL_FPA01_P1_POST_DIV_SHIFT);
8201 if (lvds & LVDS_CLKB_POWER_UP)
8206 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8209 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8210 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8212 if (dpll & PLL_P2_DIVIDE_BY_4)
8218 i9xx_clock(refclk, &clock);
8222 * This value includes pixel_multiplier. We will use
8223 * port_clock to compute adjusted_mode.crtc_clock in the
8224 * encoder's get_config() function.
8226 pipe_config->port_clock = clock.dot;
8229 int intel_dotclock_calculate(int link_freq,
8230 const struct intel_link_m_n *m_n)
8233 * The calculation for the data clock is:
8234 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8235 * But we want to avoid losing precison if possible, so:
8236 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8238 * and the link clock is simpler:
8239 * link_clock = (m * link_clock) / n
8245 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8248 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8249 struct intel_crtc_config *pipe_config)
8251 struct drm_device *dev = crtc->base.dev;
8253 /* read out port_clock from the DPLL */
8254 i9xx_crtc_clock_get(crtc, pipe_config);
8257 * This value does not include pixel_multiplier.
8258 * We will check that port_clock and adjusted_mode.crtc_clock
8259 * agree once we know their relationship in the encoder's
8260 * get_config() function.
8262 pipe_config->adjusted_mode.crtc_clock =
8263 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8264 &pipe_config->fdi_m_n);
8267 /** Returns the currently programmed mode of the given pipe. */
8268 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8269 struct drm_crtc *crtc)
8271 struct drm_i915_private *dev_priv = dev->dev_private;
8272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8273 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8274 struct drm_display_mode *mode;
8275 struct intel_crtc_config pipe_config;
8276 int htot = I915_READ(HTOTAL(cpu_transcoder));
8277 int hsync = I915_READ(HSYNC(cpu_transcoder));
8278 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8279 int vsync = I915_READ(VSYNC(cpu_transcoder));
8280 enum pipe pipe = intel_crtc->pipe;
8282 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8287 * Construct a pipe_config sufficient for getting the clock info
8288 * back out of crtc_clock_get.
8290 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8291 * to use a real value here instead.
8293 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8294 pipe_config.pixel_multiplier = 1;
8295 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8296 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8297 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8298 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8300 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8301 mode->hdisplay = (htot & 0xffff) + 1;
8302 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8303 mode->hsync_start = (hsync & 0xffff) + 1;
8304 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8305 mode->vdisplay = (vtot & 0xffff) + 1;
8306 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8307 mode->vsync_start = (vsync & 0xffff) + 1;
8308 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8310 drm_mode_set_name(mode);
8315 static void intel_increase_pllclock(struct drm_crtc *crtc)
8317 struct drm_device *dev = crtc->dev;
8318 struct drm_i915_private *dev_priv = dev->dev_private;
8319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8320 int pipe = intel_crtc->pipe;
8321 int dpll_reg = DPLL(pipe);
8324 if (HAS_PCH_SPLIT(dev))
8327 if (!dev_priv->lvds_downclock_avail)
8330 dpll = I915_READ(dpll_reg);
8331 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8332 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8334 assert_panel_unlocked(dev_priv, pipe);
8336 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8337 I915_WRITE(dpll_reg, dpll);
8338 intel_wait_for_vblank(dev, pipe);
8340 dpll = I915_READ(dpll_reg);
8341 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8342 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8346 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8348 struct drm_device *dev = crtc->dev;
8349 struct drm_i915_private *dev_priv = dev->dev_private;
8350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8352 if (HAS_PCH_SPLIT(dev))
8355 if (!dev_priv->lvds_downclock_avail)
8359 * Since this is called by a timer, we should never get here in
8362 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8363 int pipe = intel_crtc->pipe;
8364 int dpll_reg = DPLL(pipe);
8367 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8369 assert_panel_unlocked(dev_priv, pipe);
8371 dpll = I915_READ(dpll_reg);
8372 dpll |= DISPLAY_RATE_SELECT_FPA1;
8373 I915_WRITE(dpll_reg, dpll);
8374 intel_wait_for_vblank(dev, pipe);
8375 dpll = I915_READ(dpll_reg);
8376 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8377 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8382 void intel_mark_busy(struct drm_device *dev)
8384 struct drm_i915_private *dev_priv = dev->dev_private;
8386 if (dev_priv->mm.busy)
8389 intel_runtime_pm_get(dev_priv);
8390 i915_update_gfx_val(dev_priv);
8391 dev_priv->mm.busy = true;
8394 void intel_mark_idle(struct drm_device *dev)
8396 struct drm_i915_private *dev_priv = dev->dev_private;
8397 struct drm_crtc *crtc;
8399 if (!dev_priv->mm.busy)
8402 dev_priv->mm.busy = false;
8404 if (!i915.powersave)
8407 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8408 if (!crtc->primary->fb)
8411 intel_decrease_pllclock(crtc);
8414 if (INTEL_INFO(dev)->gen >= 6)
8415 gen6_rps_idle(dev->dev_private);
8418 intel_runtime_pm_put(dev_priv);
8421 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8422 struct intel_ring_buffer *ring)
8424 struct drm_device *dev = obj->base.dev;
8425 struct drm_crtc *crtc;
8427 if (!i915.powersave)
8430 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8431 if (!crtc->primary->fb)
8434 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8437 intel_increase_pllclock(crtc);
8438 if (ring && intel_fbc_enabled(dev))
8439 ring->fbc_dirty = true;
8443 static void intel_crtc_destroy(struct drm_crtc *crtc)
8445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8446 struct drm_device *dev = crtc->dev;
8447 struct intel_unpin_work *work;
8448 unsigned long flags;
8450 spin_lock_irqsave(&dev->event_lock, flags);
8451 work = intel_crtc->unpin_work;
8452 intel_crtc->unpin_work = NULL;
8453 spin_unlock_irqrestore(&dev->event_lock, flags);
8456 cancel_work_sync(&work->work);
8460 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8462 drm_crtc_cleanup(crtc);
8467 static void intel_unpin_work_fn(struct work_struct *__work)
8469 struct intel_unpin_work *work =
8470 container_of(__work, struct intel_unpin_work, work);
8471 struct drm_device *dev = work->crtc->dev;
8473 mutex_lock(&dev->struct_mutex);
8474 intel_unpin_fb_obj(work->old_fb_obj);
8475 drm_gem_object_unreference(&work->pending_flip_obj->base);
8476 drm_gem_object_unreference(&work->old_fb_obj->base);
8478 intel_update_fbc(dev);
8479 mutex_unlock(&dev->struct_mutex);
8481 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8482 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8487 static void do_intel_finish_page_flip(struct drm_device *dev,
8488 struct drm_crtc *crtc)
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8492 struct intel_unpin_work *work;
8493 unsigned long flags;
8495 /* Ignore early vblank irqs */
8496 if (intel_crtc == NULL)
8499 spin_lock_irqsave(&dev->event_lock, flags);
8500 work = intel_crtc->unpin_work;
8502 /* Ensure we don't miss a work->pending update ... */
8505 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8506 spin_unlock_irqrestore(&dev->event_lock, flags);
8510 /* and that the unpin work is consistent wrt ->pending. */
8513 intel_crtc->unpin_work = NULL;
8516 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8518 drm_vblank_put(dev, intel_crtc->pipe);
8520 spin_unlock_irqrestore(&dev->event_lock, flags);
8522 wake_up_all(&dev_priv->pending_flip_queue);
8524 queue_work(dev_priv->wq, &work->work);
8526 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8529 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8534 do_intel_finish_page_flip(dev, crtc);
8537 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8539 struct drm_i915_private *dev_priv = dev->dev_private;
8540 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8542 do_intel_finish_page_flip(dev, crtc);
8545 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8548 struct intel_crtc *intel_crtc =
8549 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8550 unsigned long flags;
8552 /* NB: An MMIO update of the plane base pointer will also
8553 * generate a page-flip completion irq, i.e. every modeset
8554 * is also accompanied by a spurious intel_prepare_page_flip().
8556 spin_lock_irqsave(&dev->event_lock, flags);
8557 if (intel_crtc->unpin_work)
8558 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8559 spin_unlock_irqrestore(&dev->event_lock, flags);
8562 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8564 /* Ensure that the work item is consistent when activating it ... */
8566 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8567 /* and that it is marked active as soon as the irq could fire. */
8571 static int intel_gen2_queue_flip(struct drm_device *dev,
8572 struct drm_crtc *crtc,
8573 struct drm_framebuffer *fb,
8574 struct drm_i915_gem_object *obj,
8577 struct drm_i915_private *dev_priv = dev->dev_private;
8578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8580 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8583 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8587 ret = intel_ring_begin(ring, 6);
8591 /* Can't queue multiple flips, so wait for the previous
8592 * one to finish before executing the next.
8594 if (intel_crtc->plane)
8595 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8597 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8598 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8599 intel_ring_emit(ring, MI_NOOP);
8600 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8601 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8602 intel_ring_emit(ring, fb->pitches[0]);
8603 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8604 intel_ring_emit(ring, 0); /* aux display base address, unused */
8606 intel_mark_page_flip_active(intel_crtc);
8607 __intel_ring_advance(ring);
8611 intel_unpin_fb_obj(obj);
8616 static int intel_gen3_queue_flip(struct drm_device *dev,
8617 struct drm_crtc *crtc,
8618 struct drm_framebuffer *fb,
8619 struct drm_i915_gem_object *obj,
8622 struct drm_i915_private *dev_priv = dev->dev_private;
8623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8628 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8632 ret = intel_ring_begin(ring, 6);
8636 if (intel_crtc->plane)
8637 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8639 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8640 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8641 intel_ring_emit(ring, MI_NOOP);
8642 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8643 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8644 intel_ring_emit(ring, fb->pitches[0]);
8645 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8646 intel_ring_emit(ring, MI_NOOP);
8648 intel_mark_page_flip_active(intel_crtc);
8649 __intel_ring_advance(ring);
8653 intel_unpin_fb_obj(obj);
8658 static int intel_gen4_queue_flip(struct drm_device *dev,
8659 struct drm_crtc *crtc,
8660 struct drm_framebuffer *fb,
8661 struct drm_i915_gem_object *obj,
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666 uint32_t pf, pipesrc;
8667 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8670 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8674 ret = intel_ring_begin(ring, 4);
8678 /* i965+ uses the linear or tiled offsets from the
8679 * Display Registers (which do not change across a page-flip)
8680 * so we need only reprogram the base address.
8682 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8683 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8684 intel_ring_emit(ring, fb->pitches[0]);
8685 intel_ring_emit(ring,
8686 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8689 /* XXX Enabling the panel-fitter across page-flip is so far
8690 * untested on non-native modes, so ignore it for now.
8691 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8694 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8695 intel_ring_emit(ring, pf | pipesrc);
8697 intel_mark_page_flip_active(intel_crtc);
8698 __intel_ring_advance(ring);
8702 intel_unpin_fb_obj(obj);
8707 static int intel_gen6_queue_flip(struct drm_device *dev,
8708 struct drm_crtc *crtc,
8709 struct drm_framebuffer *fb,
8710 struct drm_i915_gem_object *obj,
8713 struct drm_i915_private *dev_priv = dev->dev_private;
8714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8715 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8716 uint32_t pf, pipesrc;
8719 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8723 ret = intel_ring_begin(ring, 4);
8727 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8728 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8729 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8730 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8732 /* Contrary to the suggestions in the documentation,
8733 * "Enable Panel Fitter" does not seem to be required when page
8734 * flipping with a non-native mode, and worse causes a normal
8736 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8739 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8740 intel_ring_emit(ring, pf | pipesrc);
8742 intel_mark_page_flip_active(intel_crtc);
8743 __intel_ring_advance(ring);
8747 intel_unpin_fb_obj(obj);
8752 static int intel_gen7_queue_flip(struct drm_device *dev,
8753 struct drm_crtc *crtc,
8754 struct drm_framebuffer *fb,
8755 struct drm_i915_gem_object *obj,
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8760 struct intel_ring_buffer *ring;
8761 uint32_t plane_bit = 0;
8765 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8766 ring = &dev_priv->ring[BCS];
8768 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8772 switch(intel_crtc->plane) {
8774 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8777 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8780 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8783 WARN_ONCE(1, "unknown plane in flip command\n");
8789 if (ring->id == RCS) {
8792 * On Gen 8, SRM is now taking an extra dword to accommodate
8793 * 48bits addresses, and we need a NOOP for the batch size to
8801 * BSpec MI_DISPLAY_FLIP for IVB:
8802 * "The full packet must be contained within the same cache line."
8804 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8805 * cacheline, if we ever start emitting more commands before
8806 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8807 * then do the cacheline alignment, and finally emit the
8810 ret = intel_ring_cacheline_align(ring);
8814 ret = intel_ring_begin(ring, len);
8818 /* Unmask the flip-done completion message. Note that the bspec says that
8819 * we should do this for both the BCS and RCS, and that we must not unmask
8820 * more than one flip event at any time (or ensure that one flip message
8821 * can be sent by waiting for flip-done prior to queueing new flips).
8822 * Experimentation says that BCS works despite DERRMR masking all
8823 * flip-done completion events and that unmasking all planes at once
8824 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8825 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8827 if (ring->id == RCS) {
8828 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8829 intel_ring_emit(ring, DERRMR);
8830 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8831 DERRMR_PIPEB_PRI_FLIP_DONE |
8832 DERRMR_PIPEC_PRI_FLIP_DONE));
8834 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8835 MI_SRM_LRM_GLOBAL_GTT);
8837 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8838 MI_SRM_LRM_GLOBAL_GTT);
8839 intel_ring_emit(ring, DERRMR);
8840 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8842 intel_ring_emit(ring, 0);
8843 intel_ring_emit(ring, MI_NOOP);
8847 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8848 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8849 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8850 intel_ring_emit(ring, (MI_NOOP));
8852 intel_mark_page_flip_active(intel_crtc);
8853 __intel_ring_advance(ring);
8857 intel_unpin_fb_obj(obj);
8862 static int intel_default_queue_flip(struct drm_device *dev,
8863 struct drm_crtc *crtc,
8864 struct drm_framebuffer *fb,
8865 struct drm_i915_gem_object *obj,
8871 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8872 struct drm_framebuffer *fb,
8873 struct drm_pending_vblank_event *event,
8874 uint32_t page_flip_flags)
8876 struct drm_device *dev = crtc->dev;
8877 struct drm_i915_private *dev_priv = dev->dev_private;
8878 struct drm_framebuffer *old_fb = crtc->primary->fb;
8879 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8881 struct intel_unpin_work *work;
8882 unsigned long flags;
8885 /* Can't change pixel format via MI display flips. */
8886 if (fb->pixel_format != crtc->primary->fb->pixel_format)
8890 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8891 * Note that pitch changes could also affect these register.
8893 if (INTEL_INFO(dev)->gen > 3 &&
8894 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8895 fb->pitches[0] != crtc->primary->fb->pitches[0]))
8898 if (i915_terminally_wedged(&dev_priv->gpu_error))
8901 work = kzalloc(sizeof(*work), GFP_KERNEL);
8905 work->event = event;
8907 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8908 INIT_WORK(&work->work, intel_unpin_work_fn);
8910 ret = drm_vblank_get(dev, intel_crtc->pipe);
8914 /* We borrow the event spin lock for protecting unpin_work */
8915 spin_lock_irqsave(&dev->event_lock, flags);
8916 if (intel_crtc->unpin_work) {
8917 spin_unlock_irqrestore(&dev->event_lock, flags);
8919 drm_vblank_put(dev, intel_crtc->pipe);
8921 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8924 intel_crtc->unpin_work = work;
8925 spin_unlock_irqrestore(&dev->event_lock, flags);
8927 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8928 flush_workqueue(dev_priv->wq);
8930 ret = i915_mutex_lock_interruptible(dev);
8934 /* Reference the objects for the scheduled work. */
8935 drm_gem_object_reference(&work->old_fb_obj->base);
8936 drm_gem_object_reference(&obj->base);
8938 crtc->primary->fb = fb;
8940 work->pending_flip_obj = obj;
8942 work->enable_stall_check = true;
8944 atomic_inc(&intel_crtc->unpin_work_count);
8945 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8947 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8949 goto cleanup_pending;
8951 intel_disable_fbc(dev);
8952 intel_mark_fb_busy(obj, NULL);
8953 mutex_unlock(&dev->struct_mutex);
8955 trace_i915_flip_request(intel_crtc->plane, obj);
8960 atomic_dec(&intel_crtc->unpin_work_count);
8961 crtc->primary->fb = old_fb;
8962 drm_gem_object_unreference(&work->old_fb_obj->base);
8963 drm_gem_object_unreference(&obj->base);
8964 mutex_unlock(&dev->struct_mutex);
8967 spin_lock_irqsave(&dev->event_lock, flags);
8968 intel_crtc->unpin_work = NULL;
8969 spin_unlock_irqrestore(&dev->event_lock, flags);
8971 drm_vblank_put(dev, intel_crtc->pipe);
8977 intel_crtc_wait_for_pending_flips(crtc);
8978 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8979 if (ret == 0 && event)
8980 drm_send_vblank_event(dev, intel_crtc->pipe, event);
8985 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8986 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8987 .load_lut = intel_crtc_load_lut,
8991 * intel_modeset_update_staged_output_state
8993 * Updates the staged output configuration state, e.g. after we've read out the
8996 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8998 struct intel_crtc *crtc;
8999 struct intel_encoder *encoder;
9000 struct intel_connector *connector;
9002 list_for_each_entry(connector, &dev->mode_config.connector_list,
9004 connector->new_encoder =
9005 to_intel_encoder(connector->base.encoder);
9008 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9011 to_intel_crtc(encoder->base.crtc);
9014 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9016 crtc->new_enabled = crtc->base.enabled;
9018 if (crtc->new_enabled)
9019 crtc->new_config = &crtc->config;
9021 crtc->new_config = NULL;
9026 * intel_modeset_commit_output_state
9028 * This function copies the stage display pipe configuration to the real one.
9030 static void intel_modeset_commit_output_state(struct drm_device *dev)
9032 struct intel_crtc *crtc;
9033 struct intel_encoder *encoder;
9034 struct intel_connector *connector;
9036 list_for_each_entry(connector, &dev->mode_config.connector_list,
9038 connector->base.encoder = &connector->new_encoder->base;
9041 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9043 encoder->base.crtc = &encoder->new_crtc->base;
9046 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9048 crtc->base.enabled = crtc->new_enabled;
9053 connected_sink_compute_bpp(struct intel_connector * connector,
9054 struct intel_crtc_config *pipe_config)
9056 int bpp = pipe_config->pipe_bpp;
9058 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9059 connector->base.base.id,
9060 drm_get_connector_name(&connector->base));
9062 /* Don't use an invalid EDID bpc value */
9063 if (connector->base.display_info.bpc &&
9064 connector->base.display_info.bpc * 3 < bpp) {
9065 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9066 bpp, connector->base.display_info.bpc*3);
9067 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9070 /* Clamp bpp to 8 on screens without EDID 1.4 */
9071 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9072 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9074 pipe_config->pipe_bpp = 24;
9079 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9080 struct drm_framebuffer *fb,
9081 struct intel_crtc_config *pipe_config)
9083 struct drm_device *dev = crtc->base.dev;
9084 struct intel_connector *connector;
9087 switch (fb->pixel_format) {
9089 bpp = 8*3; /* since we go through a colormap */
9091 case DRM_FORMAT_XRGB1555:
9092 case DRM_FORMAT_ARGB1555:
9093 /* checked in intel_framebuffer_init already */
9094 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9096 case DRM_FORMAT_RGB565:
9097 bpp = 6*3; /* min is 18bpp */
9099 case DRM_FORMAT_XBGR8888:
9100 case DRM_FORMAT_ABGR8888:
9101 /* checked in intel_framebuffer_init already */
9102 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9104 case DRM_FORMAT_XRGB8888:
9105 case DRM_FORMAT_ARGB8888:
9108 case DRM_FORMAT_XRGB2101010:
9109 case DRM_FORMAT_ARGB2101010:
9110 case DRM_FORMAT_XBGR2101010:
9111 case DRM_FORMAT_ABGR2101010:
9112 /* checked in intel_framebuffer_init already */
9113 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9117 /* TODO: gen4+ supports 16 bpc floating point, too. */
9119 DRM_DEBUG_KMS("unsupported depth\n");
9123 pipe_config->pipe_bpp = bpp;
9125 /* Clamp display bpp to EDID value */
9126 list_for_each_entry(connector, &dev->mode_config.connector_list,
9128 if (!connector->new_encoder ||
9129 connector->new_encoder->new_crtc != crtc)
9132 connected_sink_compute_bpp(connector, pipe_config);
9138 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9140 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9141 "type: 0x%x flags: 0x%x\n",
9143 mode->crtc_hdisplay, mode->crtc_hsync_start,
9144 mode->crtc_hsync_end, mode->crtc_htotal,
9145 mode->crtc_vdisplay, mode->crtc_vsync_start,
9146 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9149 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9150 struct intel_crtc_config *pipe_config,
9151 const char *context)
9153 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9154 context, pipe_name(crtc->pipe));
9156 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9157 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9158 pipe_config->pipe_bpp, pipe_config->dither);
9159 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9160 pipe_config->has_pch_encoder,
9161 pipe_config->fdi_lanes,
9162 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9163 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9164 pipe_config->fdi_m_n.tu);
9165 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9166 pipe_config->has_dp_encoder,
9167 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9168 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9169 pipe_config->dp_m_n.tu);
9170 DRM_DEBUG_KMS("requested mode:\n");
9171 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9172 DRM_DEBUG_KMS("adjusted mode:\n");
9173 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9174 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9175 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9176 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9177 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9178 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9179 pipe_config->gmch_pfit.control,
9180 pipe_config->gmch_pfit.pgm_ratios,
9181 pipe_config->gmch_pfit.lvds_border_bits);
9182 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9183 pipe_config->pch_pfit.pos,
9184 pipe_config->pch_pfit.size,
9185 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9186 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9187 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9190 static bool encoders_cloneable(const struct intel_encoder *a,
9191 const struct intel_encoder *b)
9193 /* masks could be asymmetric, so check both ways */
9194 return a == b || (a->cloneable & (1 << b->type) &&
9195 b->cloneable & (1 << a->type));
9198 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9199 struct intel_encoder *encoder)
9201 struct drm_device *dev = crtc->base.dev;
9202 struct intel_encoder *source_encoder;
9204 list_for_each_entry(source_encoder,
9205 &dev->mode_config.encoder_list, base.head) {
9206 if (source_encoder->new_crtc != crtc)
9209 if (!encoders_cloneable(encoder, source_encoder))
9216 static bool check_encoder_cloning(struct intel_crtc *crtc)
9218 struct drm_device *dev = crtc->base.dev;
9219 struct intel_encoder *encoder;
9221 list_for_each_entry(encoder,
9222 &dev->mode_config.encoder_list, base.head) {
9223 if (encoder->new_crtc != crtc)
9226 if (!check_single_encoder_cloning(crtc, encoder))
9233 static struct intel_crtc_config *
9234 intel_modeset_pipe_config(struct drm_crtc *crtc,
9235 struct drm_framebuffer *fb,
9236 struct drm_display_mode *mode)
9238 struct drm_device *dev = crtc->dev;
9239 struct intel_encoder *encoder;
9240 struct intel_crtc_config *pipe_config;
9241 int plane_bpp, ret = -EINVAL;
9244 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9245 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9246 return ERR_PTR(-EINVAL);
9249 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9251 return ERR_PTR(-ENOMEM);
9253 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9254 drm_mode_copy(&pipe_config->requested_mode, mode);
9256 pipe_config->cpu_transcoder =
9257 (enum transcoder) to_intel_crtc(crtc)->pipe;
9258 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9261 * Sanitize sync polarity flags based on requested ones. If neither
9262 * positive or negative polarity is requested, treat this as meaning
9263 * negative polarity.
9265 if (!(pipe_config->adjusted_mode.flags &
9266 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9267 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9269 if (!(pipe_config->adjusted_mode.flags &
9270 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9271 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9273 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9274 * plane pixel format and any sink constraints into account. Returns the
9275 * source plane bpp so that dithering can be selected on mismatches
9276 * after encoders and crtc also have had their say. */
9277 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9283 * Determine the real pipe dimensions. Note that stereo modes can
9284 * increase the actual pipe size due to the frame doubling and
9285 * insertion of additional space for blanks between the frame. This
9286 * is stored in the crtc timings. We use the requested mode to do this
9287 * computation to clearly distinguish it from the adjusted mode, which
9288 * can be changed by the connectors in the below retry loop.
9290 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9291 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9292 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9295 /* Ensure the port clock defaults are reset when retrying. */
9296 pipe_config->port_clock = 0;
9297 pipe_config->pixel_multiplier = 1;
9299 /* Fill in default crtc timings, allow encoders to overwrite them. */
9300 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9302 /* Pass our mode to the connectors and the CRTC to give them a chance to
9303 * adjust it according to limitations or connector properties, and also
9304 * a chance to reject the mode entirely.
9306 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9309 if (&encoder->new_crtc->base != crtc)
9312 if (!(encoder->compute_config(encoder, pipe_config))) {
9313 DRM_DEBUG_KMS("Encoder config failure\n");
9318 /* Set default port clock if not overwritten by the encoder. Needs to be
9319 * done afterwards in case the encoder adjusts the mode. */
9320 if (!pipe_config->port_clock)
9321 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9322 * pipe_config->pixel_multiplier;
9324 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9326 DRM_DEBUG_KMS("CRTC fixup failed\n");
9331 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9336 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9341 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9342 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9343 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9348 return ERR_PTR(ret);
9351 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9352 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9354 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9355 unsigned *prepare_pipes, unsigned *disable_pipes)
9357 struct intel_crtc *intel_crtc;
9358 struct drm_device *dev = crtc->dev;
9359 struct intel_encoder *encoder;
9360 struct intel_connector *connector;
9361 struct drm_crtc *tmp_crtc;
9363 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9365 /* Check which crtcs have changed outputs connected to them, these need
9366 * to be part of the prepare_pipes mask. We don't (yet) support global
9367 * modeset across multiple crtcs, so modeset_pipes will only have one
9368 * bit set at most. */
9369 list_for_each_entry(connector, &dev->mode_config.connector_list,
9371 if (connector->base.encoder == &connector->new_encoder->base)
9374 if (connector->base.encoder) {
9375 tmp_crtc = connector->base.encoder->crtc;
9377 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9380 if (connector->new_encoder)
9382 1 << connector->new_encoder->new_crtc->pipe;
9385 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9387 if (encoder->base.crtc == &encoder->new_crtc->base)
9390 if (encoder->base.crtc) {
9391 tmp_crtc = encoder->base.crtc;
9393 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9396 if (encoder->new_crtc)
9397 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9400 /* Check for pipes that will be enabled/disabled ... */
9401 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9403 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9406 if (!intel_crtc->new_enabled)
9407 *disable_pipes |= 1 << intel_crtc->pipe;
9409 *prepare_pipes |= 1 << intel_crtc->pipe;
9413 /* set_mode is also used to update properties on life display pipes. */
9414 intel_crtc = to_intel_crtc(crtc);
9415 if (intel_crtc->new_enabled)
9416 *prepare_pipes |= 1 << intel_crtc->pipe;
9419 * For simplicity do a full modeset on any pipe where the output routing
9420 * changed. We could be more clever, but that would require us to be
9421 * more careful with calling the relevant encoder->mode_set functions.
9424 *modeset_pipes = *prepare_pipes;
9426 /* ... and mask these out. */
9427 *modeset_pipes &= ~(*disable_pipes);
9428 *prepare_pipes &= ~(*disable_pipes);
9431 * HACK: We don't (yet) fully support global modesets. intel_set_config
9432 * obies this rule, but the modeset restore mode of
9433 * intel_modeset_setup_hw_state does not.
9435 *modeset_pipes &= 1 << intel_crtc->pipe;
9436 *prepare_pipes &= 1 << intel_crtc->pipe;
9438 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9439 *modeset_pipes, *prepare_pipes, *disable_pipes);
9442 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9444 struct drm_encoder *encoder;
9445 struct drm_device *dev = crtc->dev;
9447 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9448 if (encoder->crtc == crtc)
9455 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9457 struct intel_encoder *intel_encoder;
9458 struct intel_crtc *intel_crtc;
9459 struct drm_connector *connector;
9461 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9463 if (!intel_encoder->base.crtc)
9466 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9468 if (prepare_pipes & (1 << intel_crtc->pipe))
9469 intel_encoder->connectors_active = false;
9472 intel_modeset_commit_output_state(dev);
9474 /* Double check state. */
9475 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9477 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9478 WARN_ON(intel_crtc->new_config &&
9479 intel_crtc->new_config != &intel_crtc->config);
9480 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9483 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9484 if (!connector->encoder || !connector->encoder->crtc)
9487 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9489 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9490 struct drm_property *dpms_property =
9491 dev->mode_config.dpms_property;
9493 connector->dpms = DRM_MODE_DPMS_ON;
9494 drm_object_property_set_value(&connector->base,
9498 intel_encoder = to_intel_encoder(connector->encoder);
9499 intel_encoder->connectors_active = true;
9505 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9509 if (clock1 == clock2)
9512 if (!clock1 || !clock2)
9515 diff = abs(clock1 - clock2);
9517 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9523 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9524 list_for_each_entry((intel_crtc), \
9525 &(dev)->mode_config.crtc_list, \
9527 if (mask & (1 <<(intel_crtc)->pipe))
9530 intel_pipe_config_compare(struct drm_device *dev,
9531 struct intel_crtc_config *current_config,
9532 struct intel_crtc_config *pipe_config)
9534 #define PIPE_CONF_CHECK_X(name) \
9535 if (current_config->name != pipe_config->name) { \
9536 DRM_ERROR("mismatch in " #name " " \
9537 "(expected 0x%08x, found 0x%08x)\n", \
9538 current_config->name, \
9539 pipe_config->name); \
9543 #define PIPE_CONF_CHECK_I(name) \
9544 if (current_config->name != pipe_config->name) { \
9545 DRM_ERROR("mismatch in " #name " " \
9546 "(expected %i, found %i)\n", \
9547 current_config->name, \
9548 pipe_config->name); \
9552 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9553 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9554 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9555 "(expected %i, found %i)\n", \
9556 current_config->name & (mask), \
9557 pipe_config->name & (mask)); \
9561 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9562 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9563 DRM_ERROR("mismatch in " #name " " \
9564 "(expected %i, found %i)\n", \
9565 current_config->name, \
9566 pipe_config->name); \
9570 #define PIPE_CONF_QUIRK(quirk) \
9571 ((current_config->quirks | pipe_config->quirks) & (quirk))
9573 PIPE_CONF_CHECK_I(cpu_transcoder);
9575 PIPE_CONF_CHECK_I(has_pch_encoder);
9576 PIPE_CONF_CHECK_I(fdi_lanes);
9577 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9578 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9579 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9580 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9581 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9583 PIPE_CONF_CHECK_I(has_dp_encoder);
9584 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9585 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9586 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9587 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9588 PIPE_CONF_CHECK_I(dp_m_n.tu);
9590 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9591 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9592 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9593 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9594 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9595 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9597 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9598 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9602 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9604 PIPE_CONF_CHECK_I(pixel_multiplier);
9606 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9607 DRM_MODE_FLAG_INTERLACE);
9609 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9610 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9611 DRM_MODE_FLAG_PHSYNC);
9612 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9613 DRM_MODE_FLAG_NHSYNC);
9614 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9615 DRM_MODE_FLAG_PVSYNC);
9616 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9617 DRM_MODE_FLAG_NVSYNC);
9620 PIPE_CONF_CHECK_I(pipe_src_w);
9621 PIPE_CONF_CHECK_I(pipe_src_h);
9624 * FIXME: BIOS likes to set up a cloned config with lvds+external
9625 * screen. Since we don't yet re-compute the pipe config when moving
9626 * just the lvds port away to another pipe the sw tracking won't match.
9628 * Proper atomic modesets with recomputed global state will fix this.
9629 * Until then just don't check gmch state for inherited modes.
9631 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9632 PIPE_CONF_CHECK_I(gmch_pfit.control);
9633 /* pfit ratios are autocomputed by the hw on gen4+ */
9634 if (INTEL_INFO(dev)->gen < 4)
9635 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9636 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9639 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9640 if (current_config->pch_pfit.enabled) {
9641 PIPE_CONF_CHECK_I(pch_pfit.pos);
9642 PIPE_CONF_CHECK_I(pch_pfit.size);
9645 /* BDW+ don't expose a synchronous way to read the state */
9646 if (IS_HASWELL(dev))
9647 PIPE_CONF_CHECK_I(ips_enabled);
9649 PIPE_CONF_CHECK_I(double_wide);
9651 PIPE_CONF_CHECK_I(shared_dpll);
9652 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9653 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9654 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9655 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9657 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9658 PIPE_CONF_CHECK_I(pipe_bpp);
9660 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9661 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9663 #undef PIPE_CONF_CHECK_X
9664 #undef PIPE_CONF_CHECK_I
9665 #undef PIPE_CONF_CHECK_FLAGS
9666 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9667 #undef PIPE_CONF_QUIRK
9673 check_connector_state(struct drm_device *dev)
9675 struct intel_connector *connector;
9677 list_for_each_entry(connector, &dev->mode_config.connector_list,
9679 /* This also checks the encoder/connector hw state with the
9680 * ->get_hw_state callbacks. */
9681 intel_connector_check_state(connector);
9683 WARN(&connector->new_encoder->base != connector->base.encoder,
9684 "connector's staged encoder doesn't match current encoder\n");
9689 check_encoder_state(struct drm_device *dev)
9691 struct intel_encoder *encoder;
9692 struct intel_connector *connector;
9694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9696 bool enabled = false;
9697 bool active = false;
9698 enum pipe pipe, tracked_pipe;
9700 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9701 encoder->base.base.id,
9702 drm_get_encoder_name(&encoder->base));
9704 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9705 "encoder's stage crtc doesn't match current crtc\n");
9706 WARN(encoder->connectors_active && !encoder->base.crtc,
9707 "encoder's active_connectors set, but no crtc\n");
9709 list_for_each_entry(connector, &dev->mode_config.connector_list,
9711 if (connector->base.encoder != &encoder->base)
9714 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9717 WARN(!!encoder->base.crtc != enabled,
9718 "encoder's enabled state mismatch "
9719 "(expected %i, found %i)\n",
9720 !!encoder->base.crtc, enabled);
9721 WARN(active && !encoder->base.crtc,
9722 "active encoder with no crtc\n");
9724 WARN(encoder->connectors_active != active,
9725 "encoder's computed active state doesn't match tracked active state "
9726 "(expected %i, found %i)\n", active, encoder->connectors_active);
9728 active = encoder->get_hw_state(encoder, &pipe);
9729 WARN(active != encoder->connectors_active,
9730 "encoder's hw state doesn't match sw tracking "
9731 "(expected %i, found %i)\n",
9732 encoder->connectors_active, active);
9734 if (!encoder->base.crtc)
9737 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9738 WARN(active && pipe != tracked_pipe,
9739 "active encoder's pipe doesn't match"
9740 "(expected %i, found %i)\n",
9741 tracked_pipe, pipe);
9747 check_crtc_state(struct drm_device *dev)
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 struct intel_crtc *crtc;
9751 struct intel_encoder *encoder;
9752 struct intel_crtc_config pipe_config;
9754 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9756 bool enabled = false;
9757 bool active = false;
9759 memset(&pipe_config, 0, sizeof(pipe_config));
9761 DRM_DEBUG_KMS("[CRTC:%d]\n",
9762 crtc->base.base.id);
9764 WARN(crtc->active && !crtc->base.enabled,
9765 "active crtc, but not enabled in sw tracking\n");
9767 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9769 if (encoder->base.crtc != &crtc->base)
9772 if (encoder->connectors_active)
9776 WARN(active != crtc->active,
9777 "crtc's computed active state doesn't match tracked active state "
9778 "(expected %i, found %i)\n", active, crtc->active);
9779 WARN(enabled != crtc->base.enabled,
9780 "crtc's computed enabled state doesn't match tracked enabled state "
9781 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9783 active = dev_priv->display.get_pipe_config(crtc,
9786 /* hw state is inconsistent with the pipe A quirk */
9787 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9788 active = crtc->active;
9790 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9793 if (encoder->base.crtc != &crtc->base)
9795 if (encoder->get_hw_state(encoder, &pipe))
9796 encoder->get_config(encoder, &pipe_config);
9799 WARN(crtc->active != active,
9800 "crtc active state doesn't match with hw state "
9801 "(expected %i, found %i)\n", crtc->active, active);
9804 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9805 WARN(1, "pipe state doesn't match!\n");
9806 intel_dump_pipe_config(crtc, &pipe_config,
9808 intel_dump_pipe_config(crtc, &crtc->config,
9815 check_shared_dpll_state(struct drm_device *dev)
9817 struct drm_i915_private *dev_priv = dev->dev_private;
9818 struct intel_crtc *crtc;
9819 struct intel_dpll_hw_state dpll_hw_state;
9822 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9823 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9824 int enabled_crtcs = 0, active_crtcs = 0;
9827 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9829 DRM_DEBUG_KMS("%s\n", pll->name);
9831 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9833 WARN(pll->active > pll->refcount,
9834 "more active pll users than references: %i vs %i\n",
9835 pll->active, pll->refcount);
9836 WARN(pll->active && !pll->on,
9837 "pll in active use but not on in sw tracking\n");
9838 WARN(pll->on && !pll->active,
9839 "pll in on but not on in use in sw tracking\n");
9840 WARN(pll->on != active,
9841 "pll on state mismatch (expected %i, found %i)\n",
9844 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9846 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9848 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9851 WARN(pll->active != active_crtcs,
9852 "pll active crtcs mismatch (expected %i, found %i)\n",
9853 pll->active, active_crtcs);
9854 WARN(pll->refcount != enabled_crtcs,
9855 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9856 pll->refcount, enabled_crtcs);
9858 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9859 sizeof(dpll_hw_state)),
9860 "pll hw state mismatch\n");
9865 intel_modeset_check_state(struct drm_device *dev)
9867 check_connector_state(dev);
9868 check_encoder_state(dev);
9869 check_crtc_state(dev);
9870 check_shared_dpll_state(dev);
9873 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9877 * FDI already provided one idea for the dotclock.
9878 * Yell if the encoder disagrees.
9880 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9881 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9882 pipe_config->adjusted_mode.crtc_clock, dotclock);
9885 static int __intel_set_mode(struct drm_crtc *crtc,
9886 struct drm_display_mode *mode,
9887 int x, int y, struct drm_framebuffer *fb)
9889 struct drm_device *dev = crtc->dev;
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 struct drm_display_mode *saved_mode;
9892 struct intel_crtc_config *pipe_config = NULL;
9893 struct intel_crtc *intel_crtc;
9894 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9897 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9901 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9902 &prepare_pipes, &disable_pipes);
9904 *saved_mode = crtc->mode;
9906 /* Hack: Because we don't (yet) support global modeset on multiple
9907 * crtcs, we don't keep track of the new mode for more than one crtc.
9908 * Hence simply check whether any bit is set in modeset_pipes in all the
9909 * pieces of code that are not yet converted to deal with mutliple crtcs
9910 * changing their mode at the same time. */
9911 if (modeset_pipes) {
9912 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9913 if (IS_ERR(pipe_config)) {
9914 ret = PTR_ERR(pipe_config);
9919 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9921 to_intel_crtc(crtc)->new_config = pipe_config;
9925 * See if the config requires any additional preparation, e.g.
9926 * to adjust global state with pipes off. We need to do this
9927 * here so we can get the modeset_pipe updated config for the new
9928 * mode set on this crtc. For other crtcs we need to use the
9929 * adjusted_mode bits in the crtc directly.
9931 if (IS_VALLEYVIEW(dev)) {
9932 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9934 /* may have added more to prepare_pipes than we should */
9935 prepare_pipes &= ~disable_pipes;
9938 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9939 intel_crtc_disable(&intel_crtc->base);
9941 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9942 if (intel_crtc->base.enabled)
9943 dev_priv->display.crtc_disable(&intel_crtc->base);
9946 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9947 * to set it here already despite that we pass it down the callchain.
9949 if (modeset_pipes) {
9951 /* mode_set/enable/disable functions rely on a correct pipe
9953 to_intel_crtc(crtc)->config = *pipe_config;
9954 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9957 * Calculate and store various constants which
9958 * are later needed by vblank and swap-completion
9959 * timestamping. They are derived from true hwmode.
9961 drm_calc_timestamping_constants(crtc,
9962 &pipe_config->adjusted_mode);
9965 /* Only after disabling all output pipelines that will be changed can we
9966 * update the the output configuration. */
9967 intel_modeset_update_state(dev, prepare_pipes);
9969 if (dev_priv->display.modeset_global_resources)
9970 dev_priv->display.modeset_global_resources(dev);
9972 /* Set up the DPLL and any encoders state that needs to adjust or depend
9975 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9976 ret = intel_crtc_mode_set(&intel_crtc->base,
9982 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9983 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9984 dev_priv->display.crtc_enable(&intel_crtc->base);
9986 /* FIXME: add subpixel order */
9988 if (ret && crtc->enabled)
9989 crtc->mode = *saved_mode;
9997 static int intel_set_mode(struct drm_crtc *crtc,
9998 struct drm_display_mode *mode,
9999 int x, int y, struct drm_framebuffer *fb)
10003 ret = __intel_set_mode(crtc, mode, x, y, fb);
10006 intel_modeset_check_state(crtc->dev);
10011 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10013 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10016 #undef for_each_intel_crtc_masked
10018 static void intel_set_config_free(struct intel_set_config *config)
10023 kfree(config->save_connector_encoders);
10024 kfree(config->save_encoder_crtcs);
10025 kfree(config->save_crtc_enabled);
10029 static int intel_set_config_save_state(struct drm_device *dev,
10030 struct intel_set_config *config)
10032 struct drm_crtc *crtc;
10033 struct drm_encoder *encoder;
10034 struct drm_connector *connector;
10037 config->save_crtc_enabled =
10038 kcalloc(dev->mode_config.num_crtc,
10039 sizeof(bool), GFP_KERNEL);
10040 if (!config->save_crtc_enabled)
10043 config->save_encoder_crtcs =
10044 kcalloc(dev->mode_config.num_encoder,
10045 sizeof(struct drm_crtc *), GFP_KERNEL);
10046 if (!config->save_encoder_crtcs)
10049 config->save_connector_encoders =
10050 kcalloc(dev->mode_config.num_connector,
10051 sizeof(struct drm_encoder *), GFP_KERNEL);
10052 if (!config->save_connector_encoders)
10055 /* Copy data. Note that driver private data is not affected.
10056 * Should anything bad happen only the expected state is
10057 * restored, not the drivers personal bookkeeping.
10060 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10061 config->save_crtc_enabled[count++] = crtc->enabled;
10065 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10066 config->save_encoder_crtcs[count++] = encoder->crtc;
10070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10071 config->save_connector_encoders[count++] = connector->encoder;
10077 static void intel_set_config_restore_state(struct drm_device *dev,
10078 struct intel_set_config *config)
10080 struct intel_crtc *crtc;
10081 struct intel_encoder *encoder;
10082 struct intel_connector *connector;
10086 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10087 crtc->new_enabled = config->save_crtc_enabled[count++];
10089 if (crtc->new_enabled)
10090 crtc->new_config = &crtc->config;
10092 crtc->new_config = NULL;
10096 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10097 encoder->new_crtc =
10098 to_intel_crtc(config->save_encoder_crtcs[count++]);
10102 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10103 connector->new_encoder =
10104 to_intel_encoder(config->save_connector_encoders[count++]);
10109 is_crtc_connector_off(struct drm_mode_set *set)
10113 if (set->num_connectors == 0)
10116 if (WARN_ON(set->connectors == NULL))
10119 for (i = 0; i < set->num_connectors; i++)
10120 if (set->connectors[i]->encoder &&
10121 set->connectors[i]->encoder->crtc == set->crtc &&
10122 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10129 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10130 struct intel_set_config *config)
10133 /* We should be able to check here if the fb has the same properties
10134 * and then just flip_or_move it */
10135 if (is_crtc_connector_off(set)) {
10136 config->mode_changed = true;
10137 } else if (set->crtc->primary->fb != set->fb) {
10138 /* If we have no fb then treat it as a full mode set */
10139 if (set->crtc->primary->fb == NULL) {
10140 struct intel_crtc *intel_crtc =
10141 to_intel_crtc(set->crtc);
10143 if (intel_crtc->active && i915.fastboot) {
10144 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10145 config->fb_changed = true;
10147 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10148 config->mode_changed = true;
10150 } else if (set->fb == NULL) {
10151 config->mode_changed = true;
10152 } else if (set->fb->pixel_format !=
10153 set->crtc->primary->fb->pixel_format) {
10154 config->mode_changed = true;
10156 config->fb_changed = true;
10160 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10161 config->fb_changed = true;
10163 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10164 DRM_DEBUG_KMS("modes are different, full mode set\n");
10165 drm_mode_debug_printmodeline(&set->crtc->mode);
10166 drm_mode_debug_printmodeline(set->mode);
10167 config->mode_changed = true;
10170 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10171 set->crtc->base.id, config->mode_changed, config->fb_changed);
10175 intel_modeset_stage_output_state(struct drm_device *dev,
10176 struct drm_mode_set *set,
10177 struct intel_set_config *config)
10179 struct intel_connector *connector;
10180 struct intel_encoder *encoder;
10181 struct intel_crtc *crtc;
10184 /* The upper layers ensure that we either disable a crtc or have a list
10185 * of connectors. For paranoia, double-check this. */
10186 WARN_ON(!set->fb && (set->num_connectors != 0));
10187 WARN_ON(set->fb && (set->num_connectors == 0));
10189 list_for_each_entry(connector, &dev->mode_config.connector_list,
10191 /* Otherwise traverse passed in connector list and get encoders
10193 for (ro = 0; ro < set->num_connectors; ro++) {
10194 if (set->connectors[ro] == &connector->base) {
10195 connector->new_encoder = connector->encoder;
10200 /* If we disable the crtc, disable all its connectors. Also, if
10201 * the connector is on the changing crtc but not on the new
10202 * connector list, disable it. */
10203 if ((!set->fb || ro == set->num_connectors) &&
10204 connector->base.encoder &&
10205 connector->base.encoder->crtc == set->crtc) {
10206 connector->new_encoder = NULL;
10208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10209 connector->base.base.id,
10210 drm_get_connector_name(&connector->base));
10214 if (&connector->new_encoder->base != connector->base.encoder) {
10215 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10216 config->mode_changed = true;
10219 /* connector->new_encoder is now updated for all connectors. */
10221 /* Update crtc of enabled connectors. */
10222 list_for_each_entry(connector, &dev->mode_config.connector_list,
10224 struct drm_crtc *new_crtc;
10226 if (!connector->new_encoder)
10229 new_crtc = connector->new_encoder->base.crtc;
10231 for (ro = 0; ro < set->num_connectors; ro++) {
10232 if (set->connectors[ro] == &connector->base)
10233 new_crtc = set->crtc;
10236 /* Make sure the new CRTC will work with the encoder */
10237 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10241 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10243 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10244 connector->base.base.id,
10245 drm_get_connector_name(&connector->base),
10246 new_crtc->base.id);
10249 /* Check for any encoders that needs to be disabled. */
10250 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10252 int num_connectors = 0;
10253 list_for_each_entry(connector,
10254 &dev->mode_config.connector_list,
10256 if (connector->new_encoder == encoder) {
10257 WARN_ON(!connector->new_encoder->new_crtc);
10262 if (num_connectors == 0)
10263 encoder->new_crtc = NULL;
10264 else if (num_connectors > 1)
10267 /* Only now check for crtc changes so we don't miss encoders
10268 * that will be disabled. */
10269 if (&encoder->new_crtc->base != encoder->base.crtc) {
10270 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10271 config->mode_changed = true;
10274 /* Now we've also updated encoder->new_crtc for all encoders. */
10276 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10278 crtc->new_enabled = false;
10280 list_for_each_entry(encoder,
10281 &dev->mode_config.encoder_list,
10283 if (encoder->new_crtc == crtc) {
10284 crtc->new_enabled = true;
10289 if (crtc->new_enabled != crtc->base.enabled) {
10290 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10291 crtc->new_enabled ? "en" : "dis");
10292 config->mode_changed = true;
10295 if (crtc->new_enabled)
10296 crtc->new_config = &crtc->config;
10298 crtc->new_config = NULL;
10304 static void disable_crtc_nofb(struct intel_crtc *crtc)
10306 struct drm_device *dev = crtc->base.dev;
10307 struct intel_encoder *encoder;
10308 struct intel_connector *connector;
10310 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10311 pipe_name(crtc->pipe));
10313 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10314 if (connector->new_encoder &&
10315 connector->new_encoder->new_crtc == crtc)
10316 connector->new_encoder = NULL;
10319 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10320 if (encoder->new_crtc == crtc)
10321 encoder->new_crtc = NULL;
10324 crtc->new_enabled = false;
10325 crtc->new_config = NULL;
10328 static int intel_crtc_set_config(struct drm_mode_set *set)
10330 struct drm_device *dev;
10331 struct drm_mode_set save_set;
10332 struct intel_set_config *config;
10336 BUG_ON(!set->crtc);
10337 BUG_ON(!set->crtc->helper_private);
10339 /* Enforce sane interface api - has been abused by the fb helper. */
10340 BUG_ON(!set->mode && set->fb);
10341 BUG_ON(set->fb && set->num_connectors == 0);
10344 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10345 set->crtc->base.id, set->fb->base.id,
10346 (int)set->num_connectors, set->x, set->y);
10348 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10351 dev = set->crtc->dev;
10354 config = kzalloc(sizeof(*config), GFP_KERNEL);
10358 ret = intel_set_config_save_state(dev, config);
10362 save_set.crtc = set->crtc;
10363 save_set.mode = &set->crtc->mode;
10364 save_set.x = set->crtc->x;
10365 save_set.y = set->crtc->y;
10366 save_set.fb = set->crtc->primary->fb;
10368 /* Compute whether we need a full modeset, only an fb base update or no
10369 * change at all. In the future we might also check whether only the
10370 * mode changed, e.g. for LVDS where we only change the panel fitter in
10372 intel_set_config_compute_mode_changes(set, config);
10374 ret = intel_modeset_stage_output_state(dev, set, config);
10378 if (config->mode_changed) {
10379 ret = intel_set_mode(set->crtc, set->mode,
10380 set->x, set->y, set->fb);
10381 } else if (config->fb_changed) {
10382 intel_crtc_wait_for_pending_flips(set->crtc);
10384 ret = intel_pipe_set_base(set->crtc,
10385 set->x, set->y, set->fb);
10387 * In the fastboot case this may be our only check of the
10388 * state after boot. It would be better to only do it on
10389 * the first update, but we don't have a nice way of doing that
10390 * (and really, set_config isn't used much for high freq page
10391 * flipping, so increasing its cost here shouldn't be a big
10394 if (i915.fastboot && ret == 0)
10395 intel_modeset_check_state(set->crtc->dev);
10399 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10400 set->crtc->base.id, ret);
10402 intel_set_config_restore_state(dev, config);
10405 * HACK: if the pipe was on, but we didn't have a framebuffer,
10406 * force the pipe off to avoid oopsing in the modeset code
10407 * due to fb==NULL. This should only happen during boot since
10408 * we don't yet reconstruct the FB from the hardware state.
10410 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10411 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10413 /* Try to restore the config */
10414 if (config->mode_changed &&
10415 intel_set_mode(save_set.crtc, save_set.mode,
10416 save_set.x, save_set.y, save_set.fb))
10417 DRM_ERROR("failed to restore config after modeset failure\n");
10421 intel_set_config_free(config);
10425 static const struct drm_crtc_funcs intel_crtc_funcs = {
10426 .cursor_set = intel_crtc_cursor_set,
10427 .cursor_move = intel_crtc_cursor_move,
10428 .gamma_set = intel_crtc_gamma_set,
10429 .set_config = intel_crtc_set_config,
10430 .destroy = intel_crtc_destroy,
10431 .page_flip = intel_crtc_page_flip,
10434 static void intel_cpu_pll_init(struct drm_device *dev)
10437 intel_ddi_pll_init(dev);
10440 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10441 struct intel_shared_dpll *pll,
10442 struct intel_dpll_hw_state *hw_state)
10446 val = I915_READ(PCH_DPLL(pll->id));
10447 hw_state->dpll = val;
10448 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10449 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10451 return val & DPLL_VCO_ENABLE;
10454 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10455 struct intel_shared_dpll *pll)
10457 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10458 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10461 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10462 struct intel_shared_dpll *pll)
10464 /* PCH refclock must be enabled first */
10465 ibx_assert_pch_refclk_enabled(dev_priv);
10467 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10469 /* Wait for the clocks to stabilize. */
10470 POSTING_READ(PCH_DPLL(pll->id));
10473 /* The pixel multiplier can only be updated once the
10474 * DPLL is enabled and the clocks are stable.
10476 * So write it again.
10478 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10479 POSTING_READ(PCH_DPLL(pll->id));
10483 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10484 struct intel_shared_dpll *pll)
10486 struct drm_device *dev = dev_priv->dev;
10487 struct intel_crtc *crtc;
10489 /* Make sure no transcoder isn't still depending on us. */
10490 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10491 if (intel_crtc_to_shared_dpll(crtc) == pll)
10492 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10495 I915_WRITE(PCH_DPLL(pll->id), 0);
10496 POSTING_READ(PCH_DPLL(pll->id));
10500 static char *ibx_pch_dpll_names[] = {
10505 static void ibx_pch_dpll_init(struct drm_device *dev)
10507 struct drm_i915_private *dev_priv = dev->dev_private;
10510 dev_priv->num_shared_dpll = 2;
10512 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10513 dev_priv->shared_dplls[i].id = i;
10514 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10515 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10516 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10517 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10518 dev_priv->shared_dplls[i].get_hw_state =
10519 ibx_pch_dpll_get_hw_state;
10523 static void intel_shared_dpll_init(struct drm_device *dev)
10525 struct drm_i915_private *dev_priv = dev->dev_private;
10527 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10528 ibx_pch_dpll_init(dev);
10530 dev_priv->num_shared_dpll = 0;
10532 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10535 static void intel_crtc_init(struct drm_device *dev, int pipe)
10537 struct drm_i915_private *dev_priv = dev->dev_private;
10538 struct intel_crtc *intel_crtc;
10541 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10542 if (intel_crtc == NULL)
10545 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10547 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10548 for (i = 0; i < 256; i++) {
10549 intel_crtc->lut_r[i] = i;
10550 intel_crtc->lut_g[i] = i;
10551 intel_crtc->lut_b[i] = i;
10555 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10556 * is hooked to plane B. Hence we want plane A feeding pipe B.
10558 intel_crtc->pipe = pipe;
10559 intel_crtc->plane = pipe;
10560 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10561 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10562 intel_crtc->plane = !pipe;
10565 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10566 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10567 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10568 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10570 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10573 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10575 struct drm_encoder *encoder = connector->base.encoder;
10577 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10580 return INVALID_PIPE;
10582 return to_intel_crtc(encoder->crtc)->pipe;
10585 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10586 struct drm_file *file)
10588 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10589 struct drm_mode_object *drmmode_obj;
10590 struct intel_crtc *crtc;
10592 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10595 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10596 DRM_MODE_OBJECT_CRTC);
10598 if (!drmmode_obj) {
10599 DRM_ERROR("no such CRTC id\n");
10603 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10604 pipe_from_crtc_id->pipe = crtc->pipe;
10609 static int intel_encoder_clones(struct intel_encoder *encoder)
10611 struct drm_device *dev = encoder->base.dev;
10612 struct intel_encoder *source_encoder;
10613 int index_mask = 0;
10616 list_for_each_entry(source_encoder,
10617 &dev->mode_config.encoder_list, base.head) {
10618 if (encoders_cloneable(encoder, source_encoder))
10619 index_mask |= (1 << entry);
10627 static bool has_edp_a(struct drm_device *dev)
10629 struct drm_i915_private *dev_priv = dev->dev_private;
10631 if (!IS_MOBILE(dev))
10634 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10637 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10643 const char *intel_output_name(int output)
10645 static const char *names[] = {
10646 [INTEL_OUTPUT_UNUSED] = "Unused",
10647 [INTEL_OUTPUT_ANALOG] = "Analog",
10648 [INTEL_OUTPUT_DVO] = "DVO",
10649 [INTEL_OUTPUT_SDVO] = "SDVO",
10650 [INTEL_OUTPUT_LVDS] = "LVDS",
10651 [INTEL_OUTPUT_TVOUT] = "TV",
10652 [INTEL_OUTPUT_HDMI] = "HDMI",
10653 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10654 [INTEL_OUTPUT_EDP] = "eDP",
10655 [INTEL_OUTPUT_DSI] = "DSI",
10656 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10659 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10662 return names[output];
10665 static void intel_setup_outputs(struct drm_device *dev)
10667 struct drm_i915_private *dev_priv = dev->dev_private;
10668 struct intel_encoder *encoder;
10669 bool dpd_is_edp = false;
10671 intel_lvds_init(dev);
10674 intel_crt_init(dev);
10676 if (HAS_DDI(dev)) {
10679 /* Haswell uses DDI functions to detect digital outputs */
10680 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10681 /* DDI A only supports eDP */
10683 intel_ddi_init(dev, PORT_A);
10685 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10687 found = I915_READ(SFUSE_STRAP);
10689 if (found & SFUSE_STRAP_DDIB_DETECTED)
10690 intel_ddi_init(dev, PORT_B);
10691 if (found & SFUSE_STRAP_DDIC_DETECTED)
10692 intel_ddi_init(dev, PORT_C);
10693 if (found & SFUSE_STRAP_DDID_DETECTED)
10694 intel_ddi_init(dev, PORT_D);
10695 } else if (HAS_PCH_SPLIT(dev)) {
10697 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10699 if (has_edp_a(dev))
10700 intel_dp_init(dev, DP_A, PORT_A);
10702 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10703 /* PCH SDVOB multiplex with HDMIB */
10704 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10706 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10707 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10708 intel_dp_init(dev, PCH_DP_B, PORT_B);
10711 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10712 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10714 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10715 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10717 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10718 intel_dp_init(dev, PCH_DP_C, PORT_C);
10720 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10721 intel_dp_init(dev, PCH_DP_D, PORT_D);
10722 } else if (IS_VALLEYVIEW(dev)) {
10723 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10724 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10726 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10727 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10730 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10731 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10733 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10734 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10737 intel_dsi_init(dev);
10738 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10739 bool found = false;
10741 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10742 DRM_DEBUG_KMS("probing SDVOB\n");
10743 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10744 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10745 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10746 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10749 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10750 intel_dp_init(dev, DP_B, PORT_B);
10753 /* Before G4X SDVOC doesn't have its own detect register */
10755 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10756 DRM_DEBUG_KMS("probing SDVOC\n");
10757 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10760 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10762 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10763 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10764 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10766 if (SUPPORTS_INTEGRATED_DP(dev))
10767 intel_dp_init(dev, DP_C, PORT_C);
10770 if (SUPPORTS_INTEGRATED_DP(dev) &&
10771 (I915_READ(DP_D) & DP_DETECTED))
10772 intel_dp_init(dev, DP_D, PORT_D);
10773 } else if (IS_GEN2(dev))
10774 intel_dvo_init(dev);
10776 if (SUPPORTS_TV(dev))
10777 intel_tv_init(dev);
10779 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10780 encoder->base.possible_crtcs = encoder->crtc_mask;
10781 encoder->base.possible_clones =
10782 intel_encoder_clones(encoder);
10785 intel_init_pch_refclk(dev);
10787 drm_helper_move_panel_connectors_to_head(dev);
10790 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10792 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10794 drm_framebuffer_cleanup(fb);
10795 WARN_ON(!intel_fb->obj->framebuffer_references--);
10796 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10800 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10801 struct drm_file *file,
10802 unsigned int *handle)
10804 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10805 struct drm_i915_gem_object *obj = intel_fb->obj;
10807 return drm_gem_handle_create(file, &obj->base, handle);
10810 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10811 .destroy = intel_user_framebuffer_destroy,
10812 .create_handle = intel_user_framebuffer_create_handle,
10815 static int intel_framebuffer_init(struct drm_device *dev,
10816 struct intel_framebuffer *intel_fb,
10817 struct drm_mode_fb_cmd2 *mode_cmd,
10818 struct drm_i915_gem_object *obj)
10820 int aligned_height;
10824 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10826 if (obj->tiling_mode == I915_TILING_Y) {
10827 DRM_DEBUG("hardware does not support tiling Y\n");
10831 if (mode_cmd->pitches[0] & 63) {
10832 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10833 mode_cmd->pitches[0]);
10837 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10838 pitch_limit = 32*1024;
10839 } else if (INTEL_INFO(dev)->gen >= 4) {
10840 if (obj->tiling_mode)
10841 pitch_limit = 16*1024;
10843 pitch_limit = 32*1024;
10844 } else if (INTEL_INFO(dev)->gen >= 3) {
10845 if (obj->tiling_mode)
10846 pitch_limit = 8*1024;
10848 pitch_limit = 16*1024;
10850 /* XXX DSPC is limited to 4k tiled */
10851 pitch_limit = 8*1024;
10853 if (mode_cmd->pitches[0] > pitch_limit) {
10854 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10855 obj->tiling_mode ? "tiled" : "linear",
10856 mode_cmd->pitches[0], pitch_limit);
10860 if (obj->tiling_mode != I915_TILING_NONE &&
10861 mode_cmd->pitches[0] != obj->stride) {
10862 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10863 mode_cmd->pitches[0], obj->stride);
10867 /* Reject formats not supported by any plane early. */
10868 switch (mode_cmd->pixel_format) {
10869 case DRM_FORMAT_C8:
10870 case DRM_FORMAT_RGB565:
10871 case DRM_FORMAT_XRGB8888:
10872 case DRM_FORMAT_ARGB8888:
10874 case DRM_FORMAT_XRGB1555:
10875 case DRM_FORMAT_ARGB1555:
10876 if (INTEL_INFO(dev)->gen > 3) {
10877 DRM_DEBUG("unsupported pixel format: %s\n",
10878 drm_get_format_name(mode_cmd->pixel_format));
10882 case DRM_FORMAT_XBGR8888:
10883 case DRM_FORMAT_ABGR8888:
10884 case DRM_FORMAT_XRGB2101010:
10885 case DRM_FORMAT_ARGB2101010:
10886 case DRM_FORMAT_XBGR2101010:
10887 case DRM_FORMAT_ABGR2101010:
10888 if (INTEL_INFO(dev)->gen < 4) {
10889 DRM_DEBUG("unsupported pixel format: %s\n",
10890 drm_get_format_name(mode_cmd->pixel_format));
10894 case DRM_FORMAT_YUYV:
10895 case DRM_FORMAT_UYVY:
10896 case DRM_FORMAT_YVYU:
10897 case DRM_FORMAT_VYUY:
10898 if (INTEL_INFO(dev)->gen < 5) {
10899 DRM_DEBUG("unsupported pixel format: %s\n",
10900 drm_get_format_name(mode_cmd->pixel_format));
10905 DRM_DEBUG("unsupported pixel format: %s\n",
10906 drm_get_format_name(mode_cmd->pixel_format));
10910 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10911 if (mode_cmd->offsets[0] != 0)
10914 aligned_height = intel_align_height(dev, mode_cmd->height,
10916 /* FIXME drm helper for size checks (especially planar formats)? */
10917 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10920 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10921 intel_fb->obj = obj;
10922 intel_fb->obj->framebuffer_references++;
10924 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10926 DRM_ERROR("framebuffer init failed %d\n", ret);
10933 static struct drm_framebuffer *
10934 intel_user_framebuffer_create(struct drm_device *dev,
10935 struct drm_file *filp,
10936 struct drm_mode_fb_cmd2 *mode_cmd)
10938 struct drm_i915_gem_object *obj;
10940 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10941 mode_cmd->handles[0]));
10942 if (&obj->base == NULL)
10943 return ERR_PTR(-ENOENT);
10945 return intel_framebuffer_create(dev, mode_cmd, obj);
10948 #ifndef CONFIG_DRM_I915_FBDEV
10949 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10954 static const struct drm_mode_config_funcs intel_mode_funcs = {
10955 .fb_create = intel_user_framebuffer_create,
10956 .output_poll_changed = intel_fbdev_output_poll_changed,
10959 /* Set up chip specific display functions */
10960 static void intel_init_display(struct drm_device *dev)
10962 struct drm_i915_private *dev_priv = dev->dev_private;
10964 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10965 dev_priv->display.find_dpll = g4x_find_best_dpll;
10966 else if (IS_VALLEYVIEW(dev))
10967 dev_priv->display.find_dpll = vlv_find_best_dpll;
10968 else if (IS_PINEVIEW(dev))
10969 dev_priv->display.find_dpll = pnv_find_best_dpll;
10971 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10973 if (HAS_DDI(dev)) {
10974 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10975 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10976 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10977 dev_priv->display.crtc_enable = haswell_crtc_enable;
10978 dev_priv->display.crtc_disable = haswell_crtc_disable;
10979 dev_priv->display.off = haswell_crtc_off;
10980 dev_priv->display.update_primary_plane =
10981 ironlake_update_primary_plane;
10982 } else if (HAS_PCH_SPLIT(dev)) {
10983 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10984 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10985 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10986 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10987 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10988 dev_priv->display.off = ironlake_crtc_off;
10989 dev_priv->display.update_primary_plane =
10990 ironlake_update_primary_plane;
10991 } else if (IS_VALLEYVIEW(dev)) {
10992 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10993 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10994 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10995 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10996 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10997 dev_priv->display.off = i9xx_crtc_off;
10998 dev_priv->display.update_primary_plane =
10999 i9xx_update_primary_plane;
11001 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11002 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11003 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11004 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11005 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11006 dev_priv->display.off = i9xx_crtc_off;
11007 dev_priv->display.update_primary_plane =
11008 i9xx_update_primary_plane;
11011 /* Returns the core display clock speed */
11012 if (IS_VALLEYVIEW(dev))
11013 dev_priv->display.get_display_clock_speed =
11014 valleyview_get_display_clock_speed;
11015 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11016 dev_priv->display.get_display_clock_speed =
11017 i945_get_display_clock_speed;
11018 else if (IS_I915G(dev))
11019 dev_priv->display.get_display_clock_speed =
11020 i915_get_display_clock_speed;
11021 else if (IS_I945GM(dev) || IS_845G(dev))
11022 dev_priv->display.get_display_clock_speed =
11023 i9xx_misc_get_display_clock_speed;
11024 else if (IS_PINEVIEW(dev))
11025 dev_priv->display.get_display_clock_speed =
11026 pnv_get_display_clock_speed;
11027 else if (IS_I915GM(dev))
11028 dev_priv->display.get_display_clock_speed =
11029 i915gm_get_display_clock_speed;
11030 else if (IS_I865G(dev))
11031 dev_priv->display.get_display_clock_speed =
11032 i865_get_display_clock_speed;
11033 else if (IS_I85X(dev))
11034 dev_priv->display.get_display_clock_speed =
11035 i855_get_display_clock_speed;
11036 else /* 852, 830 */
11037 dev_priv->display.get_display_clock_speed =
11038 i830_get_display_clock_speed;
11040 if (HAS_PCH_SPLIT(dev)) {
11041 if (IS_GEN5(dev)) {
11042 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11043 dev_priv->display.write_eld = ironlake_write_eld;
11044 } else if (IS_GEN6(dev)) {
11045 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11046 dev_priv->display.write_eld = ironlake_write_eld;
11047 dev_priv->display.modeset_global_resources =
11048 snb_modeset_global_resources;
11049 } else if (IS_IVYBRIDGE(dev)) {
11050 /* FIXME: detect B0+ stepping and use auto training */
11051 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11052 dev_priv->display.write_eld = ironlake_write_eld;
11053 dev_priv->display.modeset_global_resources =
11054 ivb_modeset_global_resources;
11055 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11056 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11057 dev_priv->display.write_eld = haswell_write_eld;
11058 dev_priv->display.modeset_global_resources =
11059 haswell_modeset_global_resources;
11061 } else if (IS_G4X(dev)) {
11062 dev_priv->display.write_eld = g4x_write_eld;
11063 } else if (IS_VALLEYVIEW(dev)) {
11064 dev_priv->display.modeset_global_resources =
11065 valleyview_modeset_global_resources;
11066 dev_priv->display.write_eld = ironlake_write_eld;
11069 /* Default just returns -ENODEV to indicate unsupported */
11070 dev_priv->display.queue_flip = intel_default_queue_flip;
11072 switch (INTEL_INFO(dev)->gen) {
11074 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11078 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11083 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11087 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11090 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11091 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11095 intel_panel_init_backlight_funcs(dev);
11099 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11100 * resume, or other times. This quirk makes sure that's the case for
11101 * affected systems.
11103 static void quirk_pipea_force(struct drm_device *dev)
11105 struct drm_i915_private *dev_priv = dev->dev_private;
11107 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11108 DRM_INFO("applying pipe a force quirk\n");
11112 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11114 static void quirk_ssc_force_disable(struct drm_device *dev)
11116 struct drm_i915_private *dev_priv = dev->dev_private;
11117 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11118 DRM_INFO("applying lvds SSC disable quirk\n");
11122 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11125 static void quirk_invert_brightness(struct drm_device *dev)
11127 struct drm_i915_private *dev_priv = dev->dev_private;
11128 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11129 DRM_INFO("applying inverted panel brightness quirk\n");
11132 struct intel_quirk {
11134 int subsystem_vendor;
11135 int subsystem_device;
11136 void (*hook)(struct drm_device *dev);
11139 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11140 struct intel_dmi_quirk {
11141 void (*hook)(struct drm_device *dev);
11142 const struct dmi_system_id (*dmi_id_list)[];
11145 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11147 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11151 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11153 .dmi_id_list = &(const struct dmi_system_id[]) {
11155 .callback = intel_dmi_reverse_brightness,
11156 .ident = "NCR Corporation",
11157 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11158 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11161 { } /* terminating entry */
11163 .hook = quirk_invert_brightness,
11167 static struct intel_quirk intel_quirks[] = {
11168 /* HP Mini needs pipe A force quirk (LP: #322104) */
11169 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11171 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11172 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11174 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11175 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11177 /* 830 needs to leave pipe A & dpll A up */
11178 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11180 /* Lenovo U160 cannot use SSC on LVDS */
11181 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11183 /* Sony Vaio Y cannot use SSC on LVDS */
11184 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11186 /* Acer Aspire 5734Z must invert backlight brightness */
11187 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11189 /* Acer/eMachines G725 */
11190 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11192 /* Acer/eMachines e725 */
11193 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11195 /* Acer/Packard Bell NCL20 */
11196 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11198 /* Acer Aspire 4736Z */
11199 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11201 /* Acer Aspire 5336 */
11202 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11205 static void intel_init_quirks(struct drm_device *dev)
11207 struct pci_dev *d = dev->pdev;
11210 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11211 struct intel_quirk *q = &intel_quirks[i];
11213 if (d->device == q->device &&
11214 (d->subsystem_vendor == q->subsystem_vendor ||
11215 q->subsystem_vendor == PCI_ANY_ID) &&
11216 (d->subsystem_device == q->subsystem_device ||
11217 q->subsystem_device == PCI_ANY_ID))
11220 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11221 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11222 intel_dmi_quirks[i].hook(dev);
11226 /* Disable the VGA plane that we never use */
11227 static void i915_disable_vga(struct drm_device *dev)
11229 struct drm_i915_private *dev_priv = dev->dev_private;
11231 u32 vga_reg = i915_vgacntrl_reg(dev);
11233 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11234 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11235 outb(SR01, VGA_SR_INDEX);
11236 sr1 = inb(VGA_SR_DATA);
11237 outb(sr1 | 1<<5, VGA_SR_DATA);
11238 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11241 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11242 POSTING_READ(vga_reg);
11245 void intel_modeset_init_hw(struct drm_device *dev)
11247 intel_prepare_ddi(dev);
11249 intel_init_clock_gating(dev);
11251 intel_reset_dpio(dev);
11253 intel_enable_gt_powersave(dev);
11256 void intel_modeset_suspend_hw(struct drm_device *dev)
11258 intel_suspend_hw(dev);
11261 void intel_modeset_init(struct drm_device *dev)
11263 struct drm_i915_private *dev_priv = dev->dev_private;
11266 struct intel_crtc *crtc;
11268 drm_mode_config_init(dev);
11270 dev->mode_config.min_width = 0;
11271 dev->mode_config.min_height = 0;
11273 dev->mode_config.preferred_depth = 24;
11274 dev->mode_config.prefer_shadow = 1;
11276 dev->mode_config.funcs = &intel_mode_funcs;
11278 intel_init_quirks(dev);
11280 intel_init_pm(dev);
11282 if (INTEL_INFO(dev)->num_pipes == 0)
11285 intel_init_display(dev);
11287 if (IS_GEN2(dev)) {
11288 dev->mode_config.max_width = 2048;
11289 dev->mode_config.max_height = 2048;
11290 } else if (IS_GEN3(dev)) {
11291 dev->mode_config.max_width = 4096;
11292 dev->mode_config.max_height = 4096;
11294 dev->mode_config.max_width = 8192;
11295 dev->mode_config.max_height = 8192;
11298 if (IS_GEN2(dev)) {
11299 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11300 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11302 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11303 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11306 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11308 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11309 INTEL_INFO(dev)->num_pipes,
11310 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11312 for_each_pipe(pipe) {
11313 intel_crtc_init(dev, pipe);
11314 for_each_sprite(pipe, sprite) {
11315 ret = intel_plane_init(dev, pipe, sprite);
11317 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11318 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11322 intel_init_dpio(dev);
11323 intel_reset_dpio(dev);
11325 intel_cpu_pll_init(dev);
11326 intel_shared_dpll_init(dev);
11328 /* Just disable it once at startup */
11329 i915_disable_vga(dev);
11330 intel_setup_outputs(dev);
11332 /* Just in case the BIOS is doing something questionable. */
11333 intel_disable_fbc(dev);
11335 mutex_lock(&dev->mode_config.mutex);
11336 intel_modeset_setup_hw_state(dev, false);
11337 mutex_unlock(&dev->mode_config.mutex);
11339 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11345 * Note that reserving the BIOS fb up front prevents us
11346 * from stuffing other stolen allocations like the ring
11347 * on top. This prevents some ugliness at boot time, and
11348 * can even allow for smooth boot transitions if the BIOS
11349 * fb is large enough for the active pipe configuration.
11351 if (dev_priv->display.get_plane_config) {
11352 dev_priv->display.get_plane_config(crtc,
11353 &crtc->plane_config);
11355 * If the fb is shared between multiple heads, we'll
11356 * just get the first one.
11358 intel_find_plane_obj(crtc, &crtc->plane_config);
11364 intel_connector_break_all_links(struct intel_connector *connector)
11366 connector->base.dpms = DRM_MODE_DPMS_OFF;
11367 connector->base.encoder = NULL;
11368 connector->encoder->connectors_active = false;
11369 connector->encoder->base.crtc = NULL;
11372 static void intel_enable_pipe_a(struct drm_device *dev)
11374 struct intel_connector *connector;
11375 struct drm_connector *crt = NULL;
11376 struct intel_load_detect_pipe load_detect_temp;
11378 /* We can't just switch on the pipe A, we need to set things up with a
11379 * proper mode and output configuration. As a gross hack, enable pipe A
11380 * by enabling the load detect pipe once. */
11381 list_for_each_entry(connector,
11382 &dev->mode_config.connector_list,
11384 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11385 crt = &connector->base;
11393 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11394 intel_release_load_detect_pipe(crt, &load_detect_temp);
11400 intel_check_plane_mapping(struct intel_crtc *crtc)
11402 struct drm_device *dev = crtc->base.dev;
11403 struct drm_i915_private *dev_priv = dev->dev_private;
11406 if (INTEL_INFO(dev)->num_pipes == 1)
11409 reg = DSPCNTR(!crtc->plane);
11410 val = I915_READ(reg);
11412 if ((val & DISPLAY_PLANE_ENABLE) &&
11413 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11419 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11421 struct drm_device *dev = crtc->base.dev;
11422 struct drm_i915_private *dev_priv = dev->dev_private;
11425 /* Clear any frame start delays used for debugging left by the BIOS */
11426 reg = PIPECONF(crtc->config.cpu_transcoder);
11427 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11429 /* We need to sanitize the plane -> pipe mapping first because this will
11430 * disable the crtc (and hence change the state) if it is wrong. Note
11431 * that gen4+ has a fixed plane -> pipe mapping. */
11432 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11433 struct intel_connector *connector;
11436 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11437 crtc->base.base.id);
11439 /* Pipe has the wrong plane attached and the plane is active.
11440 * Temporarily change the plane mapping and disable everything
11442 plane = crtc->plane;
11443 crtc->plane = !plane;
11444 dev_priv->display.crtc_disable(&crtc->base);
11445 crtc->plane = plane;
11447 /* ... and break all links. */
11448 list_for_each_entry(connector, &dev->mode_config.connector_list,
11450 if (connector->encoder->base.crtc != &crtc->base)
11453 intel_connector_break_all_links(connector);
11456 WARN_ON(crtc->active);
11457 crtc->base.enabled = false;
11460 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11461 crtc->pipe == PIPE_A && !crtc->active) {
11462 /* BIOS forgot to enable pipe A, this mostly happens after
11463 * resume. Force-enable the pipe to fix this, the update_dpms
11464 * call below we restore the pipe to the right state, but leave
11465 * the required bits on. */
11466 intel_enable_pipe_a(dev);
11469 /* Adjust the state of the output pipe according to whether we
11470 * have active connectors/encoders. */
11471 intel_crtc_update_dpms(&crtc->base);
11473 if (crtc->active != crtc->base.enabled) {
11474 struct intel_encoder *encoder;
11476 /* This can happen either due to bugs in the get_hw_state
11477 * functions or because the pipe is force-enabled due to the
11479 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11480 crtc->base.base.id,
11481 crtc->base.enabled ? "enabled" : "disabled",
11482 crtc->active ? "enabled" : "disabled");
11484 crtc->base.enabled = crtc->active;
11486 /* Because we only establish the connector -> encoder ->
11487 * crtc links if something is active, this means the
11488 * crtc is now deactivated. Break the links. connector
11489 * -> encoder links are only establish when things are
11490 * actually up, hence no need to break them. */
11491 WARN_ON(crtc->active);
11493 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11494 WARN_ON(encoder->connectors_active);
11495 encoder->base.crtc = NULL;
11498 if (crtc->active) {
11500 * We start out with underrun reporting disabled to avoid races.
11501 * For correct bookkeeping mark this on active crtcs.
11503 * No protection against concurrent access is required - at
11504 * worst a fifo underrun happens which also sets this to false.
11506 crtc->cpu_fifo_underrun_disabled = true;
11507 crtc->pch_fifo_underrun_disabled = true;
11511 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11513 struct intel_connector *connector;
11514 struct drm_device *dev = encoder->base.dev;
11516 /* We need to check both for a crtc link (meaning that the
11517 * encoder is active and trying to read from a pipe) and the
11518 * pipe itself being active. */
11519 bool has_active_crtc = encoder->base.crtc &&
11520 to_intel_crtc(encoder->base.crtc)->active;
11522 if (encoder->connectors_active && !has_active_crtc) {
11523 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11524 encoder->base.base.id,
11525 drm_get_encoder_name(&encoder->base));
11527 /* Connector is active, but has no active pipe. This is
11528 * fallout from our resume register restoring. Disable
11529 * the encoder manually again. */
11530 if (encoder->base.crtc) {
11531 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11532 encoder->base.base.id,
11533 drm_get_encoder_name(&encoder->base));
11534 encoder->disable(encoder);
11537 /* Inconsistent output/port/pipe state happens presumably due to
11538 * a bug in one of the get_hw_state functions. Or someplace else
11539 * in our code, like the register restore mess on resume. Clamp
11540 * things to off as a safer default. */
11541 list_for_each_entry(connector,
11542 &dev->mode_config.connector_list,
11544 if (connector->encoder != encoder)
11547 intel_connector_break_all_links(connector);
11550 /* Enabled encoders without active connectors will be fixed in
11551 * the crtc fixup. */
11554 void i915_redisable_vga_power_on(struct drm_device *dev)
11556 struct drm_i915_private *dev_priv = dev->dev_private;
11557 u32 vga_reg = i915_vgacntrl_reg(dev);
11559 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11560 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11561 i915_disable_vga(dev);
11565 void i915_redisable_vga(struct drm_device *dev)
11567 struct drm_i915_private *dev_priv = dev->dev_private;
11569 /* This function can be called both from intel_modeset_setup_hw_state or
11570 * at a very early point in our resume sequence, where the power well
11571 * structures are not yet restored. Since this function is at a very
11572 * paranoid "someone might have enabled VGA while we were not looking"
11573 * level, just check if the power well is enabled instead of trying to
11574 * follow the "don't touch the power well if we don't need it" policy
11575 * the rest of the driver uses. */
11576 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11579 i915_redisable_vga_power_on(dev);
11582 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11584 struct drm_i915_private *dev_priv = dev->dev_private;
11586 struct intel_crtc *crtc;
11587 struct intel_encoder *encoder;
11588 struct intel_connector *connector;
11591 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11593 memset(&crtc->config, 0, sizeof(crtc->config));
11595 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11597 crtc->active = dev_priv->display.get_pipe_config(crtc,
11600 crtc->base.enabled = crtc->active;
11601 crtc->primary_enabled = crtc->active;
11603 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11604 crtc->base.base.id,
11605 crtc->active ? "enabled" : "disabled");
11608 /* FIXME: Smash this into the new shared dpll infrastructure. */
11610 intel_ddi_setup_hw_pll_state(dev);
11612 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11613 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11615 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11617 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11619 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11622 pll->refcount = pll->active;
11624 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11625 pll->name, pll->refcount, pll->on);
11628 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11632 if (encoder->get_hw_state(encoder, &pipe)) {
11633 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11634 encoder->base.crtc = &crtc->base;
11635 encoder->get_config(encoder, &crtc->config);
11637 encoder->base.crtc = NULL;
11640 encoder->connectors_active = false;
11641 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11642 encoder->base.base.id,
11643 drm_get_encoder_name(&encoder->base),
11644 encoder->base.crtc ? "enabled" : "disabled",
11648 list_for_each_entry(connector, &dev->mode_config.connector_list,
11650 if (connector->get_hw_state(connector)) {
11651 connector->base.dpms = DRM_MODE_DPMS_ON;
11652 connector->encoder->connectors_active = true;
11653 connector->base.encoder = &connector->encoder->base;
11655 connector->base.dpms = DRM_MODE_DPMS_OFF;
11656 connector->base.encoder = NULL;
11658 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11659 connector->base.base.id,
11660 drm_get_connector_name(&connector->base),
11661 connector->base.encoder ? "enabled" : "disabled");
11665 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11666 * and i915 state tracking structures. */
11667 void intel_modeset_setup_hw_state(struct drm_device *dev,
11668 bool force_restore)
11670 struct drm_i915_private *dev_priv = dev->dev_private;
11672 struct intel_crtc *crtc;
11673 struct intel_encoder *encoder;
11676 intel_modeset_readout_hw_state(dev);
11679 * Now that we have the config, copy it to each CRTC struct
11680 * Note that this could go away if we move to using crtc_config
11681 * checking everywhere.
11683 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11685 if (crtc->active && i915.fastboot) {
11686 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11687 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11688 crtc->base.base.id);
11689 drm_mode_debug_printmodeline(&crtc->base.mode);
11693 /* HW state is read out, now we need to sanitize this mess. */
11694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11696 intel_sanitize_encoder(encoder);
11699 for_each_pipe(pipe) {
11700 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11701 intel_sanitize_crtc(crtc);
11702 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11705 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11706 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11708 if (!pll->on || pll->active)
11711 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11713 pll->disable(dev_priv, pll);
11717 if (HAS_PCH_SPLIT(dev))
11718 ilk_wm_get_hw_state(dev);
11720 if (force_restore) {
11721 i915_redisable_vga(dev);
11724 * We need to use raw interfaces for restoring state to avoid
11725 * checking (bogus) intermediate states.
11727 for_each_pipe(pipe) {
11728 struct drm_crtc *crtc =
11729 dev_priv->pipe_to_crtc_mapping[pipe];
11731 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11732 crtc->primary->fb);
11735 intel_modeset_update_staged_output_state(dev);
11738 intel_modeset_check_state(dev);
11741 void intel_modeset_gem_init(struct drm_device *dev)
11743 struct drm_crtc *c;
11744 struct intel_framebuffer *fb;
11746 mutex_lock(&dev->struct_mutex);
11747 intel_init_gt_powersave(dev);
11748 mutex_unlock(&dev->struct_mutex);
11750 intel_modeset_init_hw(dev);
11752 intel_setup_overlay(dev);
11755 * Make sure any fbs we allocated at startup are properly
11756 * pinned & fenced. When we do the allocation it's too early
11759 mutex_lock(&dev->struct_mutex);
11760 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11761 if (!c->primary->fb)
11764 fb = to_intel_framebuffer(c->primary->fb);
11765 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11766 DRM_ERROR("failed to pin boot fb on pipe %d\n",
11767 to_intel_crtc(c)->pipe);
11768 drm_framebuffer_unreference(c->primary->fb);
11769 c->primary->fb = NULL;
11772 mutex_unlock(&dev->struct_mutex);
11775 void intel_connector_unregister(struct intel_connector *intel_connector)
11777 struct drm_connector *connector = &intel_connector->base;
11779 intel_panel_destroy_backlight(connector);
11780 drm_sysfs_connector_remove(connector);
11783 void intel_modeset_cleanup(struct drm_device *dev)
11785 struct drm_i915_private *dev_priv = dev->dev_private;
11786 struct drm_crtc *crtc;
11787 struct drm_connector *connector;
11790 * Interrupts and polling as the first thing to avoid creating havoc.
11791 * Too much stuff here (turning of rps, connectors, ...) would
11792 * experience fancy races otherwise.
11794 drm_irq_uninstall(dev);
11795 cancel_work_sync(&dev_priv->hotplug_work);
11797 * Due to the hpd irq storm handling the hotplug work can re-arm the
11798 * poll handlers. Hence disable polling after hpd handling is shut down.
11800 drm_kms_helper_poll_fini(dev);
11802 mutex_lock(&dev->struct_mutex);
11804 intel_unregister_dsm_handler();
11806 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11807 /* Skip inactive CRTCs */
11808 if (!crtc->primary->fb)
11811 intel_increase_pllclock(crtc);
11814 intel_disable_fbc(dev);
11816 intel_disable_gt_powersave(dev);
11818 ironlake_teardown_rc6(dev);
11820 mutex_unlock(&dev->struct_mutex);
11822 /* flush any delayed tasks or pending work */
11823 flush_scheduled_work();
11825 /* destroy the backlight and sysfs files before encoders/connectors */
11826 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11827 struct intel_connector *intel_connector;
11829 intel_connector = to_intel_connector(connector);
11830 intel_connector->unregister(intel_connector);
11833 drm_mode_config_cleanup(dev);
11835 intel_cleanup_overlay(dev);
11837 mutex_lock(&dev->struct_mutex);
11838 intel_cleanup_gt_powersave(dev);
11839 mutex_unlock(&dev->struct_mutex);
11843 * Return which encoder is currently attached for connector.
11845 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11847 return &intel_attached_encoder(connector)->base;
11850 void intel_connector_attach_encoder(struct intel_connector *connector,
11851 struct intel_encoder *encoder)
11853 connector->encoder = encoder;
11854 drm_mode_connector_attach_encoder(&connector->base,
11859 * set vga decode state - true == enable VGA decode
11861 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11863 struct drm_i915_private *dev_priv = dev->dev_private;
11864 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11867 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11868 DRM_ERROR("failed to read control word\n");
11872 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11876 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11878 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11880 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11881 DRM_ERROR("failed to write control word\n");
11888 struct intel_display_error_state {
11890 u32 power_well_driver;
11892 int num_transcoders;
11894 struct intel_cursor_error_state {
11899 } cursor[I915_MAX_PIPES];
11901 struct intel_pipe_error_state {
11902 bool power_domain_on;
11905 } pipe[I915_MAX_PIPES];
11907 struct intel_plane_error_state {
11915 } plane[I915_MAX_PIPES];
11917 struct intel_transcoder_error_state {
11918 bool power_domain_on;
11919 enum transcoder cpu_transcoder;
11932 struct intel_display_error_state *
11933 intel_display_capture_error_state(struct drm_device *dev)
11935 struct drm_i915_private *dev_priv = dev->dev_private;
11936 struct intel_display_error_state *error;
11937 int transcoders[] = {
11945 if (INTEL_INFO(dev)->num_pipes == 0)
11948 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11952 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11953 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11956 error->pipe[i].power_domain_on =
11957 intel_display_power_enabled_sw(dev_priv,
11958 POWER_DOMAIN_PIPE(i));
11959 if (!error->pipe[i].power_domain_on)
11962 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11963 error->cursor[i].control = I915_READ(CURCNTR(i));
11964 error->cursor[i].position = I915_READ(CURPOS(i));
11965 error->cursor[i].base = I915_READ(CURBASE(i));
11967 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11968 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11969 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11972 error->plane[i].control = I915_READ(DSPCNTR(i));
11973 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11974 if (INTEL_INFO(dev)->gen <= 3) {
11975 error->plane[i].size = I915_READ(DSPSIZE(i));
11976 error->plane[i].pos = I915_READ(DSPPOS(i));
11978 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11979 error->plane[i].addr = I915_READ(DSPADDR(i));
11980 if (INTEL_INFO(dev)->gen >= 4) {
11981 error->plane[i].surface = I915_READ(DSPSURF(i));
11982 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11985 error->pipe[i].source = I915_READ(PIPESRC(i));
11987 if (!HAS_PCH_SPLIT(dev))
11988 error->pipe[i].stat = I915_READ(PIPESTAT(i));
11991 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11992 if (HAS_DDI(dev_priv->dev))
11993 error->num_transcoders++; /* Account for eDP. */
11995 for (i = 0; i < error->num_transcoders; i++) {
11996 enum transcoder cpu_transcoder = transcoders[i];
11998 error->transcoder[i].power_domain_on =
11999 intel_display_power_enabled_sw(dev_priv,
12000 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12001 if (!error->transcoder[i].power_domain_on)
12004 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12006 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12007 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12008 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12009 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12010 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12011 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12012 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12018 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12021 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12022 struct drm_device *dev,
12023 struct intel_display_error_state *error)
12030 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12031 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12032 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12033 error->power_well_driver);
12035 err_printf(m, "Pipe [%d]:\n", i);
12036 err_printf(m, " Power: %s\n",
12037 error->pipe[i].power_domain_on ? "on" : "off");
12038 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12039 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12041 err_printf(m, "Plane [%d]:\n", i);
12042 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12043 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12044 if (INTEL_INFO(dev)->gen <= 3) {
12045 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12046 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12048 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12049 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12050 if (INTEL_INFO(dev)->gen >= 4) {
12051 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12052 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12055 err_printf(m, "Cursor [%d]:\n", i);
12056 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12057 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12058 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12061 for (i = 0; i < error->num_transcoders; i++) {
12062 err_printf(m, "CPU transcoder: %c\n",
12063 transcoder_name(error->transcoder[i].cpu_transcoder));
12064 err_printf(m, " Power: %s\n",
12065 error->transcoder[i].power_domain_on ? "on" : "off");
12066 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12067 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12068 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12069 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12070 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12071 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12072 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);