drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198                            struct drm_i915_gem_object *obj,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         u32 alignment;
2203         int ret;
2204
2205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207         switch (obj->tiling_mode) {
2208         case I915_TILING_NONE:
2209                 if (INTEL_INFO(dev)->gen >= 9)
2210                         alignment = 256 * 1024;
2211                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212                         alignment = 128 * 1024;
2213                 else if (INTEL_INFO(dev)->gen >= 4)
2214                         alignment = 4 * 1024;
2215                 else
2216                         alignment = 64 * 1024;
2217                 break;
2218         case I915_TILING_X:
2219                 if (INTEL_INFO(dev)->gen >= 9)
2220                         alignment = 256 * 1024;
2221                 else {
2222                         /* pin() will align the object as required by fence */
2223                         alignment = 0;
2224                 }
2225                 break;
2226         case I915_TILING_Y:
2227                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228                 return -EINVAL;
2229         default:
2230                 BUG();
2231         }
2232
2233         /* Note that the w/a also requires 64 PTE of padding following the
2234          * bo. We currently fill all unused PTE with the shadow page and so
2235          * we should always have valid PTE following the scanout preventing
2236          * the VT-d warning.
2237          */
2238         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239                 alignment = 256 * 1024;
2240
2241         /*
2242          * Global gtt pte registers are special registers which actually forward
2243          * writes to a chunk of system memory. Which means that there is no risk
2244          * that the register values disappear as soon as we call
2245          * intel_runtime_pm_put(), so it is correct to wrap only the
2246          * pin/unpin/fence and not more.
2247          */
2248         intel_runtime_pm_get(dev_priv);
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         intel_runtime_pm_put(dev_priv);
2268         return 0;
2269
2270 err_unpin:
2271         i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282         i915_gem_object_unpin_fence(obj);
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287  * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289                                              unsigned int tiling_mode,
2290                                              unsigned int cpp,
2291                                              unsigned int pitch)
2292 {
2293         if (tiling_mode != I915_TILING_NONE) {
2294                 unsigned int tile_rows, tiles;
2295
2296                 tile_rows = *y / 8;
2297                 *y %= 8;
2298
2299                 tiles = *x / (512/cpp);
2300                 *x %= 512/cpp;
2301
2302                 return tile_rows * pitch * 8 + tiles * 4096;
2303         } else {
2304                 unsigned int offset;
2305
2306                 offset = *y * pitch + *x * cpp;
2307                 *y = 0;
2308                 *x = (offset & 4095) / cpp;
2309                 return offset & -4096;
2310         }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315         switch (format) {
2316         case DISPPLANE_8BPP:
2317                 return DRM_FORMAT_C8;
2318         case DISPPLANE_BGRX555:
2319                 return DRM_FORMAT_XRGB1555;
2320         case DISPPLANE_BGRX565:
2321                 return DRM_FORMAT_RGB565;
2322         default:
2323         case DISPPLANE_BGRX888:
2324                 return DRM_FORMAT_XRGB8888;
2325         case DISPPLANE_RGBX888:
2326                 return DRM_FORMAT_XBGR8888;
2327         case DISPPLANE_BGRX101010:
2328                 return DRM_FORMAT_XRGB2101010;
2329         case DISPPLANE_RGBX101010:
2330                 return DRM_FORMAT_XBGR2101010;
2331         }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335                                   struct intel_plane_config *plane_config)
2336 {
2337         struct drm_device *dev = crtc->base.dev;
2338         struct drm_i915_gem_object *obj = NULL;
2339         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340         u32 base = plane_config->base;
2341
2342         if (plane_config->size == 0)
2343                 return false;
2344
2345         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346                                                              plane_config->size);
2347         if (!obj)
2348                 return false;
2349
2350         if (plane_config->tiled) {
2351                 obj->tiling_mode = I915_TILING_X;
2352                 obj->stride = crtc->base.primary->fb->pitches[0];
2353         }
2354
2355         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356         mode_cmd.width = crtc->base.primary->fb->width;
2357         mode_cmd.height = crtc->base.primary->fb->height;
2358         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360         mutex_lock(&dev->struct_mutex);
2361
2362         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363                                    &mode_cmd, obj)) {
2364                 DRM_DEBUG_KMS("intel fb init failed\n");
2365                 goto out_unref_obj;
2366         }
2367
2368         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369         mutex_unlock(&dev->struct_mutex);
2370
2371         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372         return true;
2373
2374 out_unref_obj:
2375         drm_gem_object_unreference(&obj->base);
2376         mutex_unlock(&dev->struct_mutex);
2377         return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381                                  struct intel_plane_config *plane_config)
2382 {
2383         struct drm_device *dev = intel_crtc->base.dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_crtc *c;
2386         struct intel_crtc *i;
2387         struct drm_i915_gem_object *obj;
2388
2389         if (!intel_crtc->base.primary->fb)
2390                 return;
2391
2392         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393                 return;
2394
2395         kfree(intel_crtc->base.primary->fb);
2396         intel_crtc->base.primary->fb = NULL;
2397
2398         /*
2399          * Failed to alloc the obj, check to see if we should share
2400          * an fb with another CRTC instead
2401          */
2402         for_each_crtc(dev, c) {
2403                 i = to_intel_crtc(c);
2404
2405                 if (c == &intel_crtc->base)
2406                         continue;
2407
2408                 if (!i->active)
2409                         continue;
2410
2411                 obj = intel_fb_obj(c->primary->fb);
2412                 if (obj == NULL)
2413                         continue;
2414
2415                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416                         if (obj->tiling_mode != I915_TILING_NONE)
2417                                 dev_priv->preserve_bios_swizzle = true;
2418
2419                         drm_framebuffer_reference(c->primary->fb);
2420                         intel_crtc->base.primary->fb = c->primary->fb;
2421                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2422                         break;
2423                 }
2424         }
2425 }
2426
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428                                       struct drm_framebuffer *fb,
2429                                       int x, int y)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg = DSPCNTR(plane);
2439         int pixel_size;
2440
2441         if (!intel_crtc->primary_enabled) {
2442                 I915_WRITE(reg, 0);
2443                 if (INTEL_INFO(dev)->gen >= 4)
2444                         I915_WRITE(DSPSURF(plane), 0);
2445                 else
2446                         I915_WRITE(DSPADDR(plane), 0);
2447                 POSTING_READ(reg);
2448                 return;
2449         }
2450
2451         obj = intel_fb_obj(fb);
2452         if (WARN_ON(obj == NULL))
2453                 return;
2454
2455         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
2457         dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
2459         dspcntr |= DISPLAY_PLANE_ENABLE;
2460
2461         if (INTEL_INFO(dev)->gen < 4) {
2462                 if (intel_crtc->pipe == PIPE_B)
2463                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465                 /* pipesrc and dspsize control the size that is scaled from,
2466                  * which should always be the user's requested size.
2467                  */
2468                 I915_WRITE(DSPSIZE(plane),
2469                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470                            (intel_crtc->config.pipe_src_w - 1));
2471                 I915_WRITE(DSPPOS(plane), 0);
2472         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473                 I915_WRITE(PRIMSIZE(plane),
2474                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475                            (intel_crtc->config.pipe_src_w - 1));
2476                 I915_WRITE(PRIMPOS(plane), 0);
2477                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2478         }
2479
2480         switch (fb->pixel_format) {
2481         case DRM_FORMAT_C8:
2482                 dspcntr |= DISPPLANE_8BPP;
2483                 break;
2484         case DRM_FORMAT_XRGB1555:
2485         case DRM_FORMAT_ARGB1555:
2486                 dspcntr |= DISPPLANE_BGRX555;
2487                 break;
2488         case DRM_FORMAT_RGB565:
2489                 dspcntr |= DISPPLANE_BGRX565;
2490                 break;
2491         case DRM_FORMAT_XRGB8888:
2492         case DRM_FORMAT_ARGB8888:
2493                 dspcntr |= DISPPLANE_BGRX888;
2494                 break;
2495         case DRM_FORMAT_XBGR8888:
2496         case DRM_FORMAT_ABGR8888:
2497                 dspcntr |= DISPPLANE_RGBX888;
2498                 break;
2499         case DRM_FORMAT_XRGB2101010:
2500         case DRM_FORMAT_ARGB2101010:
2501                 dspcntr |= DISPPLANE_BGRX101010;
2502                 break;
2503         case DRM_FORMAT_XBGR2101010:
2504         case DRM_FORMAT_ABGR2101010:
2505                 dspcntr |= DISPPLANE_RGBX101010;
2506                 break;
2507         default:
2508                 BUG();
2509         }
2510
2511         if (INTEL_INFO(dev)->gen >= 4 &&
2512             obj->tiling_mode != I915_TILING_NONE)
2513                 dspcntr |= DISPPLANE_TILED;
2514
2515         if (IS_G4X(dev))
2516                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
2518         linear_offset = y * fb->pitches[0] + x * pixel_size;
2519
2520         if (INTEL_INFO(dev)->gen >= 4) {
2521                 intel_crtc->dspaddr_offset =
2522                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2523                                                        pixel_size,
2524                                                        fb->pitches[0]);
2525                 linear_offset -= intel_crtc->dspaddr_offset;
2526         } else {
2527                 intel_crtc->dspaddr_offset = linear_offset;
2528         }
2529
2530         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531                 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533                 x += (intel_crtc->config.pipe_src_w - 1);
2534                 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536                 /* Finding the last pixel of the last line of the display
2537                 data and adding to linear_offset*/
2538                 linear_offset +=
2539                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541         }
2542
2543         I915_WRITE(reg, dspcntr);
2544
2545         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547                       fb->pitches[0]);
2548         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549         if (INTEL_INFO(dev)->gen >= 4) {
2550                 I915_WRITE(DSPSURF(plane),
2551                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2554         } else
2555                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2556         POSTING_READ(reg);
2557 }
2558
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560                                           struct drm_framebuffer *fb,
2561                                           int x, int y)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         struct drm_i915_gem_object *obj;
2567         int plane = intel_crtc->plane;
2568         unsigned long linear_offset;
2569         u32 dspcntr;
2570         u32 reg = DSPCNTR(plane);
2571         int pixel_size;
2572
2573         if (!intel_crtc->primary_enabled) {
2574                 I915_WRITE(reg, 0);
2575                 I915_WRITE(DSPSURF(plane), 0);
2576                 POSTING_READ(reg);
2577                 return;
2578         }
2579
2580         obj = intel_fb_obj(fb);
2581         if (WARN_ON(obj == NULL))
2582                 return;
2583
2584         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
2586         dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
2588         dspcntr |= DISPLAY_PLANE_ENABLE;
2589
2590         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
2593         switch (fb->pixel_format) {
2594         case DRM_FORMAT_C8:
2595                 dspcntr |= DISPPLANE_8BPP;
2596                 break;
2597         case DRM_FORMAT_RGB565:
2598                 dspcntr |= DISPPLANE_BGRX565;
2599                 break;
2600         case DRM_FORMAT_XRGB8888:
2601         case DRM_FORMAT_ARGB8888:
2602                 dspcntr |= DISPPLANE_BGRX888;
2603                 break;
2604         case DRM_FORMAT_XBGR8888:
2605         case DRM_FORMAT_ABGR8888:
2606                 dspcntr |= DISPPLANE_RGBX888;
2607                 break;
2608         case DRM_FORMAT_XRGB2101010:
2609         case DRM_FORMAT_ARGB2101010:
2610                 dspcntr |= DISPPLANE_BGRX101010;
2611                 break;
2612         case DRM_FORMAT_XBGR2101010:
2613         case DRM_FORMAT_ABGR2101010:
2614                 dspcntr |= DISPPLANE_RGBX101010;
2615                 break;
2616         default:
2617                 BUG();
2618         }
2619
2620         if (obj->tiling_mode != I915_TILING_NONE)
2621                 dspcntr |= DISPPLANE_TILED;
2622
2623         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2625
2626         linear_offset = y * fb->pitches[0] + x * pixel_size;
2627         intel_crtc->dspaddr_offset =
2628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629                                                pixel_size,
2630                                                fb->pitches[0]);
2631         linear_offset -= intel_crtc->dspaddr_offset;
2632         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633                 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636                         x += (intel_crtc->config.pipe_src_w - 1);
2637                         y += (intel_crtc->config.pipe_src_h - 1);
2638
2639                         /* Finding the last pixel of the last line of the display
2640                         data and adding to linear_offset*/
2641                         linear_offset +=
2642                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644                 }
2645         }
2646
2647         I915_WRITE(reg, dspcntr);
2648
2649         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651                       fb->pitches[0]);
2652         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653         I915_WRITE(DSPSURF(plane),
2654                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657         } else {
2658                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660         }
2661         POSTING_READ(reg);
2662 }
2663
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665                                          struct drm_framebuffer *fb,
2666                                          int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct intel_framebuffer *intel_fb;
2672         struct drm_i915_gem_object *obj;
2673         int pipe = intel_crtc->pipe;
2674         u32 plane_ctl, stride;
2675
2676         if (!intel_crtc->primary_enabled) {
2677                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679                 POSTING_READ(PLANE_CTL(pipe, 0));
2680                 return;
2681         }
2682
2683         plane_ctl = PLANE_CTL_ENABLE |
2684                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2685                     PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687         switch (fb->pixel_format) {
2688         case DRM_FORMAT_RGB565:
2689                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690                 break;
2691         case DRM_FORMAT_XRGB8888:
2692                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693                 break;
2694         case DRM_FORMAT_XBGR8888:
2695                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697                 break;
2698         case DRM_FORMAT_XRGB2101010:
2699                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700                 break;
2701         case DRM_FORMAT_XBGR2101010:
2702                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704                 break;
2705         default:
2706                 BUG();
2707         }
2708
2709         intel_fb = to_intel_framebuffer(fb);
2710         obj = intel_fb->obj;
2711
2712         /*
2713          * The stride is either expressed as a multiple of 64 bytes chunks for
2714          * linear buffers or in number of tiles for tiled buffers.
2715          */
2716         switch (obj->tiling_mode) {
2717         case I915_TILING_NONE:
2718                 stride = fb->pitches[0] >> 6;
2719                 break;
2720         case I915_TILING_X:
2721                 plane_ctl |= PLANE_CTL_TILED_X;
2722                 stride = fb->pitches[0] >> 9;
2723                 break;
2724         default:
2725                 BUG();
2726         }
2727
2728         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730                 plane_ctl |= PLANE_CTL_ROTATE_180;
2731
2732         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735                       i915_gem_obj_ggtt_offset(obj),
2736                       x, y, fb->width, fb->height,
2737                       fb->pitches[0]);
2738
2739         I915_WRITE(PLANE_POS(pipe, 0), 0);
2740         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741         I915_WRITE(PLANE_SIZE(pipe, 0),
2742                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2743                    (intel_crtc->config.pipe_src_w - 1));
2744         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747         POSTING_READ(PLANE_SURF(pipe, 0));
2748 }
2749
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2751 static int
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753                            int x, int y, enum mode_set_atomic state)
2754 {
2755         struct drm_device *dev = crtc->dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757
2758         if (dev_priv->display.disable_fbc)
2759                 dev_priv->display.disable_fbc(dev);
2760
2761         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763         return 0;
2764 }
2765
2766 void intel_display_handle_reset(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct drm_crtc *crtc;
2770
2771         /*
2772          * Flips in the rings have been nuked by the reset,
2773          * so complete all pending flips so that user space
2774          * will get its events and not get stuck.
2775          *
2776          * Also update the base address of all primary
2777          * planes to the the last fb to make sure we're
2778          * showing the correct fb after a reset.
2779          *
2780          * Need to make two loops over the crtcs so that we
2781          * don't try to grab a crtc mutex before the
2782          * pending_flip_queue really got woken up.
2783          */
2784
2785         for_each_crtc(dev, crtc) {
2786                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787                 enum plane plane = intel_crtc->plane;
2788
2789                 intel_prepare_page_flip(dev, plane);
2790                 intel_finish_page_flip_plane(dev, plane);
2791         }
2792
2793         for_each_crtc(dev, crtc) {
2794                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
2796                 drm_modeset_lock(&crtc->mutex, NULL);
2797                 /*
2798                  * FIXME: Once we have proper support for primary planes (and
2799                  * disabling them without disabling the entire crtc) allow again
2800                  * a NULL crtc->primary->fb.
2801                  */
2802                 if (intel_crtc->active && crtc->primary->fb)
2803                         dev_priv->display.update_primary_plane(crtc,
2804                                                                crtc->primary->fb,
2805                                                                crtc->x,
2806                                                                crtc->y);
2807                 drm_modeset_unlock(&crtc->mutex);
2808         }
2809 }
2810
2811 static int
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2813 {
2814         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816         bool was_interruptible = dev_priv->mm.interruptible;
2817         int ret;
2818
2819         /* Big Hammer, we also need to ensure that any pending
2820          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821          * current scanout is retired before unpinning the old
2822          * framebuffer.
2823          *
2824          * This should only fail upon a hung GPU, in which case we
2825          * can safely continue.
2826          */
2827         dev_priv->mm.interruptible = false;
2828         ret = i915_gem_object_finish_gpu(obj);
2829         dev_priv->mm.interruptible = was_interruptible;
2830
2831         return ret;
2832 }
2833
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irq(&dev->event_lock);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irq(&dev->event_lock);
2848
2849         return pending;
2850 }
2851
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->base.dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         const struct drm_display_mode *adjusted_mode;
2857
2858         if (!i915.fastboot)
2859                 return;
2860
2861         /*
2862          * Update pipe size and adjust fitter if needed: the reason for this is
2863          * that in compute_mode_changes we check the native mode (not the pfit
2864          * mode) to see if we can flip rather than do a full mode set. In the
2865          * fastboot case, we'll flip, but if we don't update the pipesrc and
2866          * pfit state, we'll end up with a big fb scanned out into the wrong
2867          * sized surface.
2868          *
2869          * To fix this properly, we need to hoist the checks up into
2870          * compute_mode_changes (or above), check the actual pfit state and
2871          * whether the platform allows pfit disable with pipe active, and only
2872          * then update the pipesrc and pfit state, even on the flip path.
2873          */
2874
2875         adjusted_mode = &crtc->config.adjusted_mode;
2876
2877         I915_WRITE(PIPESRC(crtc->pipe),
2878                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879                    (adjusted_mode->crtc_vdisplay - 1));
2880         if (!crtc->config.pch_pfit.enabled &&
2881             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886         }
2887         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889 }
2890
2891 static int
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893                     struct drm_framebuffer *fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         enum pipe pipe = intel_crtc->pipe;
2899         struct drm_framebuffer *old_fb = crtc->primary->fb;
2900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2902         int ret;
2903
2904         if (intel_crtc_has_pending_flip(crtc)) {
2905                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906                 return -EBUSY;
2907         }
2908
2909         /* no fb bound */
2910         if (!fb) {
2911                 DRM_ERROR("No FB bound\n");
2912                 return 0;
2913         }
2914
2915         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917                           plane_name(intel_crtc->plane),
2918                           INTEL_INFO(dev)->num_pipes);
2919                 return -EINVAL;
2920         }
2921
2922         mutex_lock(&dev->struct_mutex);
2923         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924         if (ret == 0)
2925                 i915_gem_track_fb(old_obj, obj,
2926                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2927         mutex_unlock(&dev->struct_mutex);
2928         if (ret != 0) {
2929                 DRM_ERROR("pin & fence failed\n");
2930                 return ret;
2931         }
2932
2933         intel_update_pipe_size(intel_crtc);
2934
2935         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2936
2937         if (intel_crtc->active)
2938                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
2940         crtc->primary->fb = fb;
2941         crtc->x = x;
2942         crtc->y = y;
2943
2944         if (old_fb) {
2945                 if (intel_crtc->active && old_fb != fb)
2946                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2947                 mutex_lock(&dev->struct_mutex);
2948                 intel_unpin_fb_obj(old_obj);
2949                 mutex_unlock(&dev->struct_mutex);
2950         }
2951
2952         mutex_lock(&dev->struct_mutex);
2953         intel_update_fbc(dev);
2954         mutex_unlock(&dev->struct_mutex);
2955
2956         return 0;
2957 }
2958
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         int pipe = intel_crtc->pipe;
2965         u32 reg, temp;
2966
2967         /* enable normal train */
2968         reg = FDI_TX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (IS_IVYBRIDGE(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2976         }
2977         I915_WRITE(reg, temp);
2978
2979         reg = FDI_RX_CTL(pipe);
2980         temp = I915_READ(reg);
2981         if (HAS_PCH_CPT(dev)) {
2982                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984         } else {
2985                 temp &= ~FDI_LINK_TRAIN_NONE;
2986                 temp |= FDI_LINK_TRAIN_NONE;
2987         }
2988         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990         /* wait one idle pattern time */
2991         POSTING_READ(reg);
2992         udelay(1000);
2993
2994         /* IVB wants error correction enabled */
2995         if (IS_IVYBRIDGE(dev))
2996                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997                            FDI_FE_ERRC_ENABLE);
2998 }
2999
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3001 {
3002         return crtc->base.enabled && crtc->active &&
3003                 crtc->config.has_pch_encoder;
3004 }
3005
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *pipe_B_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011         struct intel_crtc *pipe_C_crtc =
3012                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013         uint32_t temp;
3014
3015         /*
3016          * When everything is off disable fdi C so that we could enable fdi B
3017          * with all lanes. Note that we don't care about enabled pipes without
3018          * an enabled pch encoder.
3019          */
3020         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021             !pipe_has_enabled_pch(pipe_C_crtc)) {
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025                 temp = I915_READ(SOUTH_CHICKEN1);
3026                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028                 I915_WRITE(SOUTH_CHICKEN1, temp);
3029         }
3030 }
3031
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp, tries;
3040
3041         /* FDI needs bits from pipe first */
3042         assert_pipe_enabled(dev_priv, pipe);
3043
3044         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045            for train result */
3046         reg = FDI_RX_IMR(pipe);
3047         temp = I915_READ(reg);
3048         temp &= ~FDI_RX_SYMBOL_LOCK;
3049         temp &= ~FDI_RX_BIT_LOCK;
3050         I915_WRITE(reg, temp);
3051         I915_READ(reg);
3052         udelay(150);
3053
3054         /* enable CPU FDI TX and PCH FDI RX */
3055         reg = FDI_TX_CTL(pipe);
3056         temp = I915_READ(reg);
3057         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059         temp &= ~FDI_LINK_TRAIN_NONE;
3060         temp |= FDI_LINK_TRAIN_PATTERN_1;
3061         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3062
3063         reg = FDI_RX_CTL(pipe);
3064         temp = I915_READ(reg);
3065         temp &= ~FDI_LINK_TRAIN_NONE;
3066         temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069         POSTING_READ(reg);
3070         udelay(150);
3071
3072         /* Ironlake workaround, enable clock pointer after FDI enable*/
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075                    FDI_RX_PHASE_SYNC_POINTER_EN);
3076
3077         reg = FDI_RX_IIR(pipe);
3078         for (tries = 0; tries < 5; tries++) {
3079                 temp = I915_READ(reg);
3080                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                 if ((temp & FDI_RX_BIT_LOCK)) {
3083                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3084                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                         break;
3086                 }
3087         }
3088         if (tries == 5)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         I915_WRITE(reg, temp);
3097
3098         reg = FDI_RX_CTL(pipe);
3099         temp = I915_READ(reg);
3100         temp &= ~FDI_LINK_TRAIN_NONE;
3101         temp |= FDI_LINK_TRAIN_PATTERN_2;
3102         I915_WRITE(reg, temp);
3103
3104         POSTING_READ(reg);
3105         udelay(150);
3106
3107         reg = FDI_RX_IIR(pipe);
3108         for (tries = 0; tries < 5; tries++) {
3109                 temp = I915_READ(reg);
3110                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112                 if (temp & FDI_RX_SYMBOL_LOCK) {
3113                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3115                         break;
3116                 }
3117         }
3118         if (tries == 5)
3119                 DRM_ERROR("FDI train 2 fail!\n");
3120
3121         DRM_DEBUG_KMS("FDI train done\n");
3122
3123 }
3124
3125 static const int snb_b_fdi_train_param[] = {
3126         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130 };
3131
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134 {
3135         struct drm_device *dev = crtc->dev;
3136         struct drm_i915_private *dev_priv = dev->dev_private;
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp, i, retry;
3140
3141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142            for train result */
3143         reg = FDI_RX_IMR(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_RX_SYMBOL_LOCK;
3146         temp &= ~FDI_RX_BIT_LOCK;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         /* enable CPU FDI TX and PCH FDI RX */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_1;
3159         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160         /* SNB-B */
3161         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3163
3164         I915_WRITE(FDI_RX_MISC(pipe),
3165                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
3167         reg = FDI_RX_CTL(pipe);
3168         temp = I915_READ(reg);
3169         if (HAS_PCH_CPT(dev)) {
3170                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172         } else {
3173                 temp &= ~FDI_LINK_TRAIN_NONE;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175         }
3176         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178         POSTING_READ(reg);
3179         udelay(150);
3180
3181         for (i = 0; i < 4; i++) {
3182                 reg = FDI_TX_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185                 temp |= snb_b_fdi_train_param[i];
3186                 I915_WRITE(reg, temp);
3187
3188                 POSTING_READ(reg);
3189                 udelay(500);
3190
3191                 for (retry = 0; retry < 5; retry++) {
3192                         reg = FDI_RX_IIR(pipe);
3193                         temp = I915_READ(reg);
3194                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195                         if (temp & FDI_RX_BIT_LOCK) {
3196                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198                                 break;
3199                         }
3200                         udelay(50);
3201                 }
3202                 if (retry < 5)
3203                         break;
3204         }
3205         if (i == 4)
3206                 DRM_ERROR("FDI train 1 fail!\n");
3207
3208         /* Train 2 */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_LINK_TRAIN_NONE;
3212         temp |= FDI_LINK_TRAIN_PATTERN_2;
3213         if (IS_GEN6(dev)) {
3214                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215                 /* SNB-B */
3216                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217         }
3218         I915_WRITE(reg, temp);
3219
3220         reg = FDI_RX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (HAS_PCH_CPT(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         POSTING_READ(reg);
3232         udelay(150);
3233
3234         for (i = 0; i < 4; i++) {
3235                 reg = FDI_TX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238                 temp |= snb_b_fdi_train_param[i];
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(500);
3243
3244                 for (retry = 0; retry < 5; retry++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248                         if (temp & FDI_RX_SYMBOL_LOCK) {
3249                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251                                 break;
3252                         }
3253                         udelay(50);
3254                 }
3255                 if (retry < 5)
3256                         break;
3257         }
3258         if (i == 4)
3259                 DRM_ERROR("FDI train 2 fail!\n");
3260
3261         DRM_DEBUG_KMS("FDI train done.\n");
3262 }
3263
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp, i, j;
3272
3273         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274            for train result */
3275         reg = FDI_RX_IMR(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_RX_SYMBOL_LOCK;
3278         temp &= ~FDI_RX_BIT_LOCK;
3279         I915_WRITE(reg, temp);
3280
3281         POSTING_READ(reg);
3282         udelay(150);
3283
3284         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285                       I915_READ(FDI_RX_IIR(pipe)));
3286
3287         /* Try each vswing and preemphasis setting twice before moving on */
3288         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289                 /* disable first in case we need to retry */
3290                 reg = FDI_TX_CTL(pipe);
3291                 temp = I915_READ(reg);
3292                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293                 temp &= ~FDI_TX_ENABLE;
3294                 I915_WRITE(reg, temp);
3295
3296                 reg = FDI_RX_CTL(pipe);
3297                 temp = I915_READ(reg);
3298                 temp &= ~FDI_LINK_TRAIN_AUTO;
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp &= ~FDI_RX_ENABLE;
3301                 I915_WRITE(reg, temp);
3302
3303                 /* enable CPU FDI TX and PCH FDI RX */
3304                 reg = FDI_TX_CTL(pipe);
3305                 temp = I915_READ(reg);
3306                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310                 temp |= snb_b_fdi_train_param[j/2];
3311                 temp |= FDI_COMPOSITE_SYNC;
3312                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314                 I915_WRITE(FDI_RX_MISC(pipe),
3315                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317                 reg = FDI_RX_CTL(pipe);
3318                 temp = I915_READ(reg);
3319                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320                 temp |= FDI_COMPOSITE_SYNC;
3321                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323                 POSTING_READ(reg);
3324                 udelay(1); /* should be 0.5us */
3325
3326                 for (i = 0; i < 4; i++) {
3327                         reg = FDI_RX_IIR(pipe);
3328                         temp = I915_READ(reg);
3329                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331                         if (temp & FDI_RX_BIT_LOCK ||
3332                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335                                               i);
3336                                 break;
3337                         }
3338                         udelay(1); /* should be 0.5us */
3339                 }
3340                 if (i == 4) {
3341                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342                         continue;
3343                 }
3344
3345                 /* Train 2 */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356                 I915_WRITE(reg, temp);
3357
3358                 POSTING_READ(reg);
3359                 udelay(2); /* should be 1.5us */
3360
3361                 for (i = 0; i < 4; i++) {
3362                         reg = FDI_RX_IIR(pipe);
3363                         temp = I915_READ(reg);
3364                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3365
3366                         if (temp & FDI_RX_SYMBOL_LOCK ||
3367                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370                                               i);
3371                                 goto train_done;
3372                         }
3373                         udelay(2); /* should be 1.5us */
3374                 }
3375                 if (i == 4)
3376                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3377         }
3378
3379 train_done:
3380         DRM_DEBUG_KMS("FDI train done.\n");
3381 }
3382
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3384 {
3385         struct drm_device *dev = intel_crtc->base.dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         int pipe = intel_crtc->pipe;
3388         u32 reg, temp;
3389
3390
3391         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392         reg = FDI_RX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399         POSTING_READ(reg);
3400         udelay(200);
3401
3402         /* Switch from Rawclk to PCDclk */
3403         temp = I915_READ(reg);
3404         I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406         POSTING_READ(reg);
3407         udelay(200);
3408
3409         /* Enable CPU FDI TX PLL, always on for Ironlake */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3414
3415                 POSTING_READ(reg);
3416                 udelay(100);
3417         }
3418 }
3419
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp;
3426
3427         /* Switch from PCDclk to Rawclk */
3428         reg = FDI_RX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432         /* Disable CPU FDI TX PLL */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444         /* Wait for the clocks to turn off. */
3445         POSTING_READ(reg);
3446         udelay(100);
3447 }
3448
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         /* disable CPU FDI tx and PCH FDI rx */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461         POSTING_READ(reg);
3462
3463         reg = FDI_RX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~(0x7 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471
3472         /* Ironlake workaround, disable clock pointer after downing FDI */
3473         if (HAS_PCH_IBX(dev))
3474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3475
3476         /* still set train pattern 1 */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_LINK_TRAIN_NONE;
3480         temp |= FDI_LINK_TRAIN_PATTERN_1;
3481         I915_WRITE(reg, temp);
3482
3483         reg = FDI_RX_CTL(pipe);
3484         temp = I915_READ(reg);
3485         if (HAS_PCH_CPT(dev)) {
3486                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488         } else {
3489                 temp &= ~FDI_LINK_TRAIN_NONE;
3490                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491         }
3492         /* BPC in FDI rx is consistent with that in PIPECONF */
3493         temp &= ~(0x07 << 16);
3494         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495         I915_WRITE(reg, temp);
3496
3497         POSTING_READ(reg);
3498         udelay(100);
3499 }
3500
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502 {
3503         struct intel_crtc *crtc;
3504
3505         /* Note that we don't need to be called with mode_config.lock here
3506          * as our list of CRTC objects is static for the lifetime of the
3507          * device and so cannot disappear as we iterate. Similarly, we can
3508          * happily treat the predicates as racy, atomic checks as userspace
3509          * cannot claim and pin a new fb without at least acquring the
3510          * struct_mutex and so serialising with us.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (atomic_read(&crtc->unpin_work_count) == 0)
3514                         continue;
3515
3516                 if (crtc->unpin_work)
3517                         intel_wait_for_vblank(dev, crtc->pipe);
3518
3519                 return true;
3520         }
3521
3522         return false;
3523 }
3524
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3526 {
3527         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528         struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530         /* ensure that the unpin work is consistent wrt ->pending. */
3531         smp_rmb();
3532         intel_crtc->unpin_work = NULL;
3533
3534         if (work->event)
3535                 drm_send_vblank_event(intel_crtc->base.dev,
3536                                       intel_crtc->pipe,
3537                                       work->event);
3538
3539         drm_crtc_vblank_put(&intel_crtc->base);
3540
3541         wake_up_all(&dev_priv->pending_flip_queue);
3542         queue_work(dev_priv->wq, &work->work);
3543
3544         trace_i915_flip_complete(intel_crtc->plane,
3545                                  work->pending_flip_obj);
3546 }
3547
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555                                        !intel_crtc_has_pending_flip(crtc),
3556                                        60*HZ) == 0)) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558
3559                 spin_lock_irq(&dev->event_lock);
3560                 if (intel_crtc->unpin_work) {
3561                         WARN_ONCE(1, "Removing stuck page flip\n");
3562                         page_flip_completed(intel_crtc);
3563                 }
3564                 spin_unlock_irq(&dev->event_lock);
3565         }
3566
3567         if (crtc->primary->fb) {
3568                 mutex_lock(&dev->struct_mutex);
3569                 intel_finish_fb(crtc->primary->fb);
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572 }
3573
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581         u32 temp;
3582
3583         mutex_lock(&dev_priv->dpio_lock);
3584
3585         /* It is necessary to ungate the pixclk gate prior to programming
3586          * the divisors, and gate it back when it is done.
3587          */
3588         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590         /* Disable SSCCTL */
3591         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593                                 SBI_SSCCTL_DISABLE,
3594                         SBI_ICLK);
3595
3596         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597         if (clock == 20000) {
3598                 auxdiv = 1;
3599                 divsel = 0x41;
3600                 phaseinc = 0x20;
3601         } else {
3602                 /* The iCLK virtual clock root frequency is in MHz,
3603                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3604                  * divisors, it is necessary to divide one by another, so we
3605                  * convert the virtual clock precision to KHz here for higher
3606                  * precision.
3607                  */
3608                 u32 iclk_virtual_root_freq = 172800 * 1000;
3609                 u32 iclk_pi_range = 64;
3610                 u32 desired_divisor, msb_divisor_value, pi_value;
3611
3612                 desired_divisor = (iclk_virtual_root_freq / clock);
3613                 msb_divisor_value = desired_divisor / iclk_pi_range;
3614                 pi_value = desired_divisor % iclk_pi_range;
3615
3616                 auxdiv = 0;
3617                 divsel = msb_divisor_value - 2;
3618                 phaseinc = pi_value;
3619         }
3620
3621         /* This should not happen with any sane values */
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3628                         clock,
3629                         auxdiv,
3630                         divsel,
3631                         phasedir,
3632                         phaseinc);
3633
3634         /* Program SSCDIVINTPHASE6 */
3635         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3643
3644         /* Program SSCAUXDIV */
3645         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3649
3650         /* Enable modulator and associated divider */
3651         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652         temp &= ~SBI_SSCCTL_DISABLE;
3653         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3654
3655         /* Wait for initialization time */
3656         udelay(24);
3657
3658         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3659
3660         mutex_unlock(&dev_priv->dpio_lock);
3661 }
3662
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664                                                 enum pipe pch_transcoder)
3665 {
3666         struct drm_device *dev = crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671                    I915_READ(HTOTAL(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673                    I915_READ(HBLANK(cpu_transcoder)));
3674         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675                    I915_READ(HSYNC(cpu_transcoder)));
3676
3677         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678                    I915_READ(VTOTAL(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680                    I915_READ(VBLANK(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682                    I915_READ(VSYNC(cpu_transcoder)));
3683         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685 }
3686
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         uint32_t temp;
3691
3692         temp = I915_READ(SOUTH_CHICKEN1);
3693         if (temp & FDI_BC_BIFURCATION_SELECT)
3694                 return;
3695
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699         temp |= FDI_BC_BIFURCATION_SELECT;
3700         DRM_DEBUG_KMS("enabling fdi C rx\n");
3701         I915_WRITE(SOUTH_CHICKEN1, temp);
3702         POSTING_READ(SOUTH_CHICKEN1);
3703 }
3704
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706 {
3707         struct drm_device *dev = intel_crtc->base.dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         switch (intel_crtc->pipe) {
3711         case PIPE_A:
3712                 break;
3713         case PIPE_B:
3714                 if (intel_crtc->config.fdi_lanes > 2)
3715                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716                 else
3717                         cpt_enable_fdi_bc_bifurcation(dev);
3718
3719                 break;
3720         case PIPE_C:
3721                 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723                 break;
3724         default:
3725                 BUG();
3726         }
3727 }
3728
3729 /*
3730  * Enable PCH resources required for PCH ports:
3731  *   - PCH PLLs
3732  *   - FDI training & RX/TX
3733  *   - update transcoder timings
3734  *   - DP transcoding bits
3735  *   - transcoder
3736  */
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745         assert_pch_transcoder_disabled(dev_priv, pipe);
3746
3747         if (IS_IVYBRIDGE(dev))
3748                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
3750         /* Write the TU size bits before fdi link training, so that error
3751          * detection works. */
3752         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
3755         /* For PCH output, training FDI link */
3756         dev_priv->display.fdi_link_train(crtc);
3757
3758         /* We need to program the right clock selection before writing the pixel
3759          * mutliplier into the DPLL. */
3760         if (HAS_PCH_CPT(dev)) {
3761                 u32 sel;
3762
3763                 temp = I915_READ(PCH_DPLL_SEL);
3764                 temp |= TRANS_DPLL_ENABLE(pipe);
3765                 sel = TRANS_DPLLB_SEL(pipe);
3766                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3767                         temp |= sel;
3768                 else
3769                         temp &= ~sel;
3770                 I915_WRITE(PCH_DPLL_SEL, temp);
3771         }
3772
3773         /* XXX: pch pll's can be enabled any time before we enable the PCH
3774          * transcoder, and we actually should do this to not upset any PCH
3775          * transcoder that already use the clock when we share it.
3776          *
3777          * Note that enable_shared_dpll tries to do the right thing, but
3778          * get_shared_dpll unconditionally resets the pll - we need that to have
3779          * the right LVDS enable sequence. */
3780         intel_enable_shared_dpll(intel_crtc);
3781
3782         /* set transcoder timing, panel must allow it */
3783         assert_panel_unlocked(dev_priv, pipe);
3784         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3785
3786         intel_fdi_normal_train(crtc);
3787
3788         /* For PCH DP, enable TRANS_DP_CTL */
3789         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791                 reg = TRANS_DP_CTL(pipe);
3792                 temp = I915_READ(reg);
3793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794                           TRANS_DP_SYNC_MASK |
3795                           TRANS_DP_BPC_MASK);
3796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797                          TRANS_DP_ENH_FRAMING);
3798                 temp |= bpc << 9; /* same format but at 11:9 */
3799
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3804
3805                 switch (intel_trans_dp_port_sel(crtc)) {
3806                 case PCH_DP_B:
3807                         temp |= TRANS_DP_PORT_SEL_B;
3808                         break;
3809                 case PCH_DP_C:
3810                         temp |= TRANS_DP_PORT_SEL_C;
3811                         break;
3812                 case PCH_DP_D:
3813                         temp |= TRANS_DP_PORT_SEL_D;
3814                         break;
3815                 default:
3816                         BUG();
3817                 }
3818
3819                 I915_WRITE(reg, temp);
3820         }
3821
3822         ironlake_enable_pch_transcoder(dev_priv, pipe);
3823 }
3824
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3833
3834         lpt_program_iclkip(crtc);
3835
3836         /* Set transcoder timing. */
3837         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3838
3839         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3840 }
3841
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3843 {
3844         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3845
3846         if (pll == NULL)
3847                 return;
3848
3849         if (!(pll->crtc_mask & (1 << crtc->pipe))) {
3850                 WARN(1, "bad %s crtc mask\n", pll->name);
3851                 return;
3852         }
3853
3854         pll->crtc_mask &= ~(1 << crtc->pipe);
3855         if (pll->crtc_mask == 0) {
3856                 WARN_ON(pll->on);
3857                 WARN_ON(pll->active);
3858         }
3859
3860         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3861 }
3862
3863 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3864 {
3865         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3866         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3867         enum intel_dpll_id i;
3868
3869         if (pll) {
3870                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3871                               crtc->base.base.id, pll->name);
3872                 intel_put_shared_dpll(crtc);
3873         }
3874
3875         if (HAS_PCH_IBX(dev_priv->dev)) {
3876                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3877                 i = (enum intel_dpll_id) crtc->pipe;
3878                 pll = &dev_priv->shared_dplls[i];
3879
3880                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3881                               crtc->base.base.id, pll->name);
3882
3883                 WARN_ON(pll->crtc_mask);
3884
3885                 goto found;
3886         }
3887
3888         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3889                 pll = &dev_priv->shared_dplls[i];
3890
3891                 /* Only want to check enabled timings first */
3892                 if (pll->crtc_mask == 0)
3893                         continue;
3894
3895                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3896                            sizeof(pll->hw_state)) == 0) {
3897                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s "
3898                                       "(crtc_mask 0x%08x, active %d)\n",
3899                                       crtc->base.base.id, pll->name,
3900                                       pll->crtc_mask, pll->active);
3901
3902                         goto found;
3903                 }
3904         }
3905
3906         /* Ok no matching timings, maybe there's a free one? */
3907         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3908                 pll = &dev_priv->shared_dplls[i];
3909                 if (pll->crtc_mask == 0) {
3910                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3911                                       crtc->base.base.id, pll->name);
3912                         goto found;
3913                 }
3914         }
3915
3916         return NULL;
3917
3918 found:
3919         if (pll->crtc_mask == 0)
3920                 pll->hw_state = crtc->config.dpll_hw_state;
3921
3922         crtc->config.shared_dpll = i;
3923         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3924                          pipe_name(crtc->pipe));
3925
3926         pll->crtc_mask |= 1 << crtc->pipe;
3927
3928         return pll;
3929 }
3930
3931 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3932 {
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         int dslreg = PIPEDSL(pipe);
3935         u32 temp;
3936
3937         temp = I915_READ(dslreg);
3938         udelay(500);
3939         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3940                 if (wait_for(I915_READ(dslreg) != temp, 5))
3941                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3942         }
3943 }
3944
3945 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->base.dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         int pipe = crtc->pipe;
3950
3951         if (crtc->config.pch_pfit.enabled) {
3952                 /* Force use of hard-coded filter coefficients
3953                  * as some pre-programmed values are broken,
3954                  * e.g. x201.
3955                  */
3956                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3957                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3958                                                  PF_PIPE_SEL_IVB(pipe));
3959                 else
3960                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3961                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3962                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3963         }
3964 }
3965
3966 static void intel_enable_planes(struct drm_crtc *crtc)
3967 {
3968         struct drm_device *dev = crtc->dev;
3969         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3970         struct drm_plane *plane;
3971         struct intel_plane *intel_plane;
3972
3973         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3974                 intel_plane = to_intel_plane(plane);
3975                 if (intel_plane->pipe == pipe)
3976                         intel_plane_restore(&intel_plane->base);
3977         }
3978 }
3979
3980 static void intel_disable_planes(struct drm_crtc *crtc)
3981 {
3982         struct drm_device *dev = crtc->dev;
3983         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3984         struct drm_plane *plane;
3985         struct intel_plane *intel_plane;
3986
3987         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3988                 intel_plane = to_intel_plane(plane);
3989                 if (intel_plane->pipe == pipe)
3990                         intel_plane_disable(&intel_plane->base);
3991         }
3992 }
3993
3994 void hsw_enable_ips(struct intel_crtc *crtc)
3995 {
3996         struct drm_device *dev = crtc->base.dev;
3997         struct drm_i915_private *dev_priv = dev->dev_private;
3998
3999         if (!crtc->config.ips_enabled)
4000                 return;
4001
4002         /* We can only enable IPS after we enable a plane and wait for a vblank */
4003         intel_wait_for_vblank(dev, crtc->pipe);
4004
4005         assert_plane_enabled(dev_priv, crtc->plane);
4006         if (IS_BROADWELL(dev)) {
4007                 mutex_lock(&dev_priv->rps.hw_lock);
4008                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4009                 mutex_unlock(&dev_priv->rps.hw_lock);
4010                 /* Quoting Art Runyan: "its not safe to expect any particular
4011                  * value in IPS_CTL bit 31 after enabling IPS through the
4012                  * mailbox." Moreover, the mailbox may return a bogus state,
4013                  * so we need to just enable it and continue on.
4014                  */
4015         } else {
4016                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4017                 /* The bit only becomes 1 in the next vblank, so this wait here
4018                  * is essentially intel_wait_for_vblank. If we don't have this
4019                  * and don't wait for vblanks until the end of crtc_enable, then
4020                  * the HW state readout code will complain that the expected
4021                  * IPS_CTL value is not the one we read. */
4022                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4023                         DRM_ERROR("Timed out waiting for IPS enable\n");
4024         }
4025 }
4026
4027 void hsw_disable_ips(struct intel_crtc *crtc)
4028 {
4029         struct drm_device *dev = crtc->base.dev;
4030         struct drm_i915_private *dev_priv = dev->dev_private;
4031
4032         if (!crtc->config.ips_enabled)
4033                 return;
4034
4035         assert_plane_enabled(dev_priv, crtc->plane);
4036         if (IS_BROADWELL(dev)) {
4037                 mutex_lock(&dev_priv->rps.hw_lock);
4038                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4039                 mutex_unlock(&dev_priv->rps.hw_lock);
4040                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4041                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4042                         DRM_ERROR("Timed out waiting for IPS disable\n");
4043         } else {
4044                 I915_WRITE(IPS_CTL, 0);
4045                 POSTING_READ(IPS_CTL);
4046         }
4047
4048         /* We need to wait for a vblank before we can disable the plane. */
4049         intel_wait_for_vblank(dev, crtc->pipe);
4050 }
4051
4052 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4053 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058         enum pipe pipe = intel_crtc->pipe;
4059         int palreg = PALETTE(pipe);
4060         int i;
4061         bool reenable_ips = false;
4062
4063         /* The clocks have to be on to load the palette. */
4064         if (!crtc->enabled || !intel_crtc->active)
4065                 return;
4066
4067         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4068                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4069                         assert_dsi_pll_enabled(dev_priv);
4070                 else
4071                         assert_pll_enabled(dev_priv, pipe);
4072         }
4073
4074         /* use legacy palette for Ironlake */
4075         if (!HAS_GMCH_DISPLAY(dev))
4076                 palreg = LGC_PALETTE(pipe);
4077
4078         /* Workaround : Do not read or write the pipe palette/gamma data while
4079          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4080          */
4081         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4082             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4083              GAMMA_MODE_MODE_SPLIT)) {
4084                 hsw_disable_ips(intel_crtc);
4085                 reenable_ips = true;
4086         }
4087
4088         for (i = 0; i < 256; i++) {
4089                 I915_WRITE(palreg + 4 * i,
4090                            (intel_crtc->lut_r[i] << 16) |
4091                            (intel_crtc->lut_g[i] << 8) |
4092                            intel_crtc->lut_b[i]);
4093         }
4094
4095         if (reenable_ips)
4096                 hsw_enable_ips(intel_crtc);
4097 }
4098
4099 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4100 {
4101         if (!enable && intel_crtc->overlay) {
4102                 struct drm_device *dev = intel_crtc->base.dev;
4103                 struct drm_i915_private *dev_priv = dev->dev_private;
4104
4105                 mutex_lock(&dev->struct_mutex);
4106                 dev_priv->mm.interruptible = false;
4107                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4108                 dev_priv->mm.interruptible = true;
4109                 mutex_unlock(&dev->struct_mutex);
4110         }
4111
4112         /* Let userspace switch the overlay on again. In most cases userspace
4113          * has to recompute where to put it anyway.
4114          */
4115 }
4116
4117 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4118 {
4119         struct drm_device *dev = crtc->dev;
4120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121         int pipe = intel_crtc->pipe;
4122
4123         intel_enable_primary_hw_plane(crtc->primary, crtc);
4124         intel_enable_planes(crtc);
4125         intel_crtc_update_cursor(crtc, true);
4126         intel_crtc_dpms_overlay(intel_crtc, true);
4127
4128         hsw_enable_ips(intel_crtc);
4129
4130         mutex_lock(&dev->struct_mutex);
4131         intel_update_fbc(dev);
4132         mutex_unlock(&dev->struct_mutex);
4133
4134         /*
4135          * FIXME: Once we grow proper nuclear flip support out of this we need
4136          * to compute the mask of flip planes precisely. For the time being
4137          * consider this a flip from a NULL plane.
4138          */
4139         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4140 }
4141
4142 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4143 {
4144         struct drm_device *dev = crtc->dev;
4145         struct drm_i915_private *dev_priv = dev->dev_private;
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         int pipe = intel_crtc->pipe;
4148         int plane = intel_crtc->plane;
4149
4150         intel_crtc_wait_for_pending_flips(crtc);
4151
4152         if (dev_priv->fbc.plane == plane)
4153                 intel_disable_fbc(dev);
4154
4155         hsw_disable_ips(intel_crtc);
4156
4157         intel_crtc_dpms_overlay(intel_crtc, false);
4158         intel_crtc_update_cursor(crtc, false);
4159         intel_disable_planes(crtc);
4160         intel_disable_primary_hw_plane(crtc->primary, crtc);
4161
4162         /*
4163          * FIXME: Once we grow proper nuclear flip support out of this we need
4164          * to compute the mask of flip planes precisely. For the time being
4165          * consider this a flip to a NULL plane.
4166          */
4167         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4168 }
4169
4170 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175         struct intel_encoder *encoder;
4176         int pipe = intel_crtc->pipe;
4177
4178         WARN_ON(!crtc->enabled);
4179
4180         if (intel_crtc->active)
4181                 return;
4182
4183         if (intel_crtc->config.has_pch_encoder)
4184                 intel_prepare_shared_dpll(intel_crtc);
4185
4186         if (intel_crtc->config.has_dp_encoder)
4187                 intel_dp_set_m_n(intel_crtc);
4188
4189         intel_set_pipe_timings(intel_crtc);
4190
4191         if (intel_crtc->config.has_pch_encoder) {
4192                 intel_cpu_transcoder_set_m_n(intel_crtc,
4193                                      &intel_crtc->config.fdi_m_n, NULL);
4194         }
4195
4196         ironlake_set_pipeconf(crtc);
4197
4198         intel_crtc->active = true;
4199
4200         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4201         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4202
4203         for_each_encoder_on_crtc(dev, crtc, encoder)
4204                 if (encoder->pre_enable)
4205                         encoder->pre_enable(encoder);
4206
4207         if (intel_crtc->config.has_pch_encoder) {
4208                 /* Note: FDI PLL enabling _must_ be done before we enable the
4209                  * cpu pipes, hence this is separate from all the other fdi/pch
4210                  * enabling. */
4211                 ironlake_fdi_pll_enable(intel_crtc);
4212         } else {
4213                 assert_fdi_tx_disabled(dev_priv, pipe);
4214                 assert_fdi_rx_disabled(dev_priv, pipe);
4215         }
4216
4217         ironlake_pfit_enable(intel_crtc);
4218
4219         /*
4220          * On ILK+ LUT must be loaded before the pipe is running but with
4221          * clocks enabled
4222          */
4223         intel_crtc_load_lut(crtc);
4224
4225         intel_update_watermarks(crtc);
4226         intel_enable_pipe(intel_crtc);
4227
4228         if (intel_crtc->config.has_pch_encoder)
4229                 ironlake_pch_enable(crtc);
4230
4231         for_each_encoder_on_crtc(dev, crtc, encoder)
4232                 encoder->enable(encoder);
4233
4234         if (HAS_PCH_CPT(dev))
4235                 cpt_verify_modeset(dev, intel_crtc->pipe);
4236
4237         assert_vblank_disabled(crtc);
4238         drm_crtc_vblank_on(crtc);
4239
4240         intel_crtc_enable_planes(crtc);
4241 }
4242
4243 /* IPS only exists on ULT machines and is tied to pipe A. */
4244 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4245 {
4246         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4247 }
4248
4249 /*
4250  * This implements the workaround described in the "notes" section of the mode
4251  * set sequence documentation. When going from no pipes or single pipe to
4252  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4253  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4254  */
4255 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4256 {
4257         struct drm_device *dev = crtc->base.dev;
4258         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4259
4260         /* We want to get the other_active_crtc only if there's only 1 other
4261          * active crtc. */
4262         for_each_intel_crtc(dev, crtc_it) {
4263                 if (!crtc_it->active || crtc_it == crtc)
4264                         continue;
4265
4266                 if (other_active_crtc)
4267                         return;
4268
4269                 other_active_crtc = crtc_it;
4270         }
4271         if (!other_active_crtc)
4272                 return;
4273
4274         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4275         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4276 }
4277
4278 static void haswell_crtc_enable(struct drm_crtc *crtc)
4279 {
4280         struct drm_device *dev = crtc->dev;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4283         struct intel_encoder *encoder;
4284         int pipe = intel_crtc->pipe;
4285
4286         WARN_ON(!crtc->enabled);
4287
4288         if (intel_crtc->active)
4289                 return;
4290
4291         if (intel_crtc_to_shared_dpll(intel_crtc))
4292                 intel_enable_shared_dpll(intel_crtc);
4293
4294         if (intel_crtc->config.has_dp_encoder)
4295                 intel_dp_set_m_n(intel_crtc);
4296
4297         intel_set_pipe_timings(intel_crtc);
4298
4299         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4300                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4301                            intel_crtc->config.pixel_multiplier - 1);
4302         }
4303
4304         if (intel_crtc->config.has_pch_encoder) {
4305                 intel_cpu_transcoder_set_m_n(intel_crtc,
4306                                      &intel_crtc->config.fdi_m_n, NULL);
4307         }
4308
4309         haswell_set_pipeconf(crtc);
4310
4311         intel_set_pipe_csc(crtc);
4312
4313         intel_crtc->active = true;
4314
4315         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4316         for_each_encoder_on_crtc(dev, crtc, encoder)
4317                 if (encoder->pre_enable)
4318                         encoder->pre_enable(encoder);
4319
4320         if (intel_crtc->config.has_pch_encoder) {
4321                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4322                                                       true);
4323                 dev_priv->display.fdi_link_train(crtc);
4324         }
4325
4326         intel_ddi_enable_pipe_clock(intel_crtc);
4327
4328         ironlake_pfit_enable(intel_crtc);
4329
4330         /*
4331          * On ILK+ LUT must be loaded before the pipe is running but with
4332          * clocks enabled
4333          */
4334         intel_crtc_load_lut(crtc);
4335
4336         intel_ddi_set_pipe_settings(crtc);
4337         intel_ddi_enable_transcoder_func(crtc);
4338
4339         intel_update_watermarks(crtc);
4340         intel_enable_pipe(intel_crtc);
4341
4342         if (intel_crtc->config.has_pch_encoder)
4343                 lpt_pch_enable(crtc);
4344
4345         if (intel_crtc->config.dp_encoder_is_mst)
4346                 intel_ddi_set_vc_payload_alloc(crtc, true);
4347
4348         for_each_encoder_on_crtc(dev, crtc, encoder) {
4349                 encoder->enable(encoder);
4350                 intel_opregion_notify_encoder(encoder, true);
4351         }
4352
4353         assert_vblank_disabled(crtc);
4354         drm_crtc_vblank_on(crtc);
4355
4356         /* If we change the relative order between pipe/planes enabling, we need
4357          * to change the workaround. */
4358         haswell_mode_set_planes_workaround(intel_crtc);
4359         intel_crtc_enable_planes(crtc);
4360 }
4361
4362 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4363 {
4364         struct drm_device *dev = crtc->base.dev;
4365         struct drm_i915_private *dev_priv = dev->dev_private;
4366         int pipe = crtc->pipe;
4367
4368         /* To avoid upsetting the power well on haswell only disable the pfit if
4369          * it's in use. The hw state code will make sure we get this right. */
4370         if (crtc->config.pch_pfit.enabled) {
4371                 I915_WRITE(PF_CTL(pipe), 0);
4372                 I915_WRITE(PF_WIN_POS(pipe), 0);
4373                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4374         }
4375 }
4376
4377 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4378 {
4379         struct drm_device *dev = crtc->dev;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4382         struct intel_encoder *encoder;
4383         int pipe = intel_crtc->pipe;
4384         u32 reg, temp;
4385
4386         if (!intel_crtc->active)
4387                 return;
4388
4389         intel_crtc_disable_planes(crtc);
4390
4391         drm_crtc_vblank_off(crtc);
4392         assert_vblank_disabled(crtc);
4393
4394         for_each_encoder_on_crtc(dev, crtc, encoder)
4395                 encoder->disable(encoder);
4396
4397         if (intel_crtc->config.has_pch_encoder)
4398                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4399
4400         intel_disable_pipe(intel_crtc);
4401
4402         ironlake_pfit_disable(intel_crtc);
4403
4404         for_each_encoder_on_crtc(dev, crtc, encoder)
4405                 if (encoder->post_disable)
4406                         encoder->post_disable(encoder);
4407
4408         if (intel_crtc->config.has_pch_encoder) {
4409                 ironlake_fdi_disable(crtc);
4410
4411                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4412                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4413
4414                 if (HAS_PCH_CPT(dev)) {
4415                         /* disable TRANS_DP_CTL */
4416                         reg = TRANS_DP_CTL(pipe);
4417                         temp = I915_READ(reg);
4418                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4419                                   TRANS_DP_PORT_SEL_MASK);
4420                         temp |= TRANS_DP_PORT_SEL_NONE;
4421                         I915_WRITE(reg, temp);
4422
4423                         /* disable DPLL_SEL */
4424                         temp = I915_READ(PCH_DPLL_SEL);
4425                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4426                         I915_WRITE(PCH_DPLL_SEL, temp);
4427                 }
4428
4429                 /* disable PCH DPLL */
4430                 intel_disable_shared_dpll(intel_crtc);
4431
4432                 ironlake_fdi_pll_disable(intel_crtc);
4433         }
4434
4435         intel_crtc->active = false;
4436         intel_update_watermarks(crtc);
4437
4438         mutex_lock(&dev->struct_mutex);
4439         intel_update_fbc(dev);
4440         mutex_unlock(&dev->struct_mutex);
4441 }
4442
4443 static void haswell_crtc_disable(struct drm_crtc *crtc)
4444 {
4445         struct drm_device *dev = crtc->dev;
4446         struct drm_i915_private *dev_priv = dev->dev_private;
4447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4448         struct intel_encoder *encoder;
4449         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4450
4451         if (!intel_crtc->active)
4452                 return;
4453
4454         intel_crtc_disable_planes(crtc);
4455
4456         drm_crtc_vblank_off(crtc);
4457         assert_vblank_disabled(crtc);
4458
4459         for_each_encoder_on_crtc(dev, crtc, encoder) {
4460                 intel_opregion_notify_encoder(encoder, false);
4461                 encoder->disable(encoder);
4462         }
4463
4464         if (intel_crtc->config.has_pch_encoder)
4465                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4466                                                       false);
4467         intel_disable_pipe(intel_crtc);
4468
4469         if (intel_crtc->config.dp_encoder_is_mst)
4470                 intel_ddi_set_vc_payload_alloc(crtc, false);
4471
4472         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4473
4474         ironlake_pfit_disable(intel_crtc);
4475
4476         intel_ddi_disable_pipe_clock(intel_crtc);
4477
4478         if (intel_crtc->config.has_pch_encoder) {
4479                 lpt_disable_pch_transcoder(dev_priv);
4480                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4481                                                       true);
4482                 intel_ddi_fdi_disable(crtc);
4483         }
4484
4485         for_each_encoder_on_crtc(dev, crtc, encoder)
4486                 if (encoder->post_disable)
4487                         encoder->post_disable(encoder);
4488
4489         intel_crtc->active = false;
4490         intel_update_watermarks(crtc);
4491
4492         mutex_lock(&dev->struct_mutex);
4493         intel_update_fbc(dev);
4494         mutex_unlock(&dev->struct_mutex);
4495
4496         if (intel_crtc_to_shared_dpll(intel_crtc))
4497                 intel_disable_shared_dpll(intel_crtc);
4498 }
4499
4500 static void ironlake_crtc_off(struct drm_crtc *crtc)
4501 {
4502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4503         intel_put_shared_dpll(intel_crtc);
4504 }
4505
4506
4507 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4508 {
4509         struct drm_device *dev = crtc->base.dev;
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         struct intel_crtc_config *pipe_config = &crtc->config;
4512
4513         if (!crtc->config.gmch_pfit.control)
4514                 return;
4515
4516         /*
4517          * The panel fitter should only be adjusted whilst the pipe is disabled,
4518          * according to register description and PRM.
4519          */
4520         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4521         assert_pipe_disabled(dev_priv, crtc->pipe);
4522
4523         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4524         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4525
4526         /* Border color in case we don't scale up to the full screen. Black by
4527          * default, change to something else for debugging. */
4528         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4529 }
4530
4531 static enum intel_display_power_domain port_to_power_domain(enum port port)
4532 {
4533         switch (port) {
4534         case PORT_A:
4535                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4536         case PORT_B:
4537                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4538         case PORT_C:
4539                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4540         case PORT_D:
4541                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4542         default:
4543                 WARN_ON_ONCE(1);
4544                 return POWER_DOMAIN_PORT_OTHER;
4545         }
4546 }
4547
4548 #define for_each_power_domain(domain, mask)                             \
4549         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4550                 if ((1 << (domain)) & (mask))
4551
4552 enum intel_display_power_domain
4553 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4554 {
4555         struct drm_device *dev = intel_encoder->base.dev;
4556         struct intel_digital_port *intel_dig_port;
4557
4558         switch (intel_encoder->type) {
4559         case INTEL_OUTPUT_UNKNOWN:
4560                 /* Only DDI platforms should ever use this output type */
4561                 WARN_ON_ONCE(!HAS_DDI(dev));
4562         case INTEL_OUTPUT_DISPLAYPORT:
4563         case INTEL_OUTPUT_HDMI:
4564         case INTEL_OUTPUT_EDP:
4565                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4566                 return port_to_power_domain(intel_dig_port->port);
4567         case INTEL_OUTPUT_DP_MST:
4568                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4569                 return port_to_power_domain(intel_dig_port->port);
4570         case INTEL_OUTPUT_ANALOG:
4571                 return POWER_DOMAIN_PORT_CRT;
4572         case INTEL_OUTPUT_DSI:
4573                 return POWER_DOMAIN_PORT_DSI;
4574         default:
4575                 return POWER_DOMAIN_PORT_OTHER;
4576         }
4577 }
4578
4579 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4580 {
4581         struct drm_device *dev = crtc->dev;
4582         struct intel_encoder *intel_encoder;
4583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4584         enum pipe pipe = intel_crtc->pipe;
4585         unsigned long mask;
4586         enum transcoder transcoder;
4587
4588         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4589
4590         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4591         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4592         if (intel_crtc->config.pch_pfit.enabled ||
4593             intel_crtc->config.pch_pfit.force_thru)
4594                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4595
4596         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4597                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4598
4599         return mask;
4600 }
4601
4602 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4603 {
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4606         struct intel_crtc *crtc;
4607
4608         /*
4609          * First get all needed power domains, then put all unneeded, to avoid
4610          * any unnecessary toggling of the power wells.
4611          */
4612         for_each_intel_crtc(dev, crtc) {
4613                 enum intel_display_power_domain domain;
4614
4615                 if (!crtc->base.enabled)
4616                         continue;
4617
4618                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4619
4620                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4621                         intel_display_power_get(dev_priv, domain);
4622         }
4623
4624         for_each_intel_crtc(dev, crtc) {
4625                 enum intel_display_power_domain domain;
4626
4627                 for_each_power_domain(domain, crtc->enabled_power_domains)
4628                         intel_display_power_put(dev_priv, domain);
4629
4630                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4631         }
4632
4633         intel_display_set_init_power(dev_priv, false);
4634 }
4635
4636 /* returns HPLL frequency in kHz */
4637 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4638 {
4639         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4640
4641         /* Obtain SKU information */
4642         mutex_lock(&dev_priv->dpio_lock);
4643         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4644                 CCK_FUSE_HPLL_FREQ_MASK;
4645         mutex_unlock(&dev_priv->dpio_lock);
4646
4647         return vco_freq[hpll_freq] * 1000;
4648 }
4649
4650 static void vlv_update_cdclk(struct drm_device *dev)
4651 {
4652         struct drm_i915_private *dev_priv = dev->dev_private;
4653
4654         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4655         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4656                          dev_priv->vlv_cdclk_freq);
4657
4658         /*
4659          * Program the gmbus_freq based on the cdclk frequency.
4660          * BSpec erroneously claims we should aim for 4MHz, but
4661          * in fact 1MHz is the correct frequency.
4662          */
4663         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4664 }
4665
4666 /* Adjust CDclk dividers to allow high res or save power if possible */
4667 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4668 {
4669         struct drm_i915_private *dev_priv = dev->dev_private;
4670         u32 val, cmd;
4671
4672         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4673
4674         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4675                 cmd = 2;
4676         else if (cdclk == 266667)
4677                 cmd = 1;
4678         else
4679                 cmd = 0;
4680
4681         mutex_lock(&dev_priv->rps.hw_lock);
4682         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4683         val &= ~DSPFREQGUAR_MASK;
4684         val |= (cmd << DSPFREQGUAR_SHIFT);
4685         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4686         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4687                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4688                      50)) {
4689                 DRM_ERROR("timed out waiting for CDclk change\n");
4690         }
4691         mutex_unlock(&dev_priv->rps.hw_lock);
4692
4693         if (cdclk == 400000) {
4694                 u32 divider, vco;
4695
4696                 vco = valleyview_get_vco(dev_priv);
4697                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4698
4699                 mutex_lock(&dev_priv->dpio_lock);
4700                 /* adjust cdclk divider */
4701                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4702                 val &= ~DISPLAY_FREQUENCY_VALUES;
4703                 val |= divider;
4704                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4705
4706                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4707                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4708                              50))
4709                         DRM_ERROR("timed out waiting for CDclk change\n");
4710                 mutex_unlock(&dev_priv->dpio_lock);
4711         }
4712
4713         mutex_lock(&dev_priv->dpio_lock);
4714         /* adjust self-refresh exit latency value */
4715         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4716         val &= ~0x7f;
4717
4718         /*
4719          * For high bandwidth configs, we set a higher latency in the bunit
4720          * so that the core display fetch happens in time to avoid underruns.
4721          */
4722         if (cdclk == 400000)
4723                 val |= 4500 / 250; /* 4.5 usec */
4724         else
4725                 val |= 3000 / 250; /* 3.0 usec */
4726         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4727         mutex_unlock(&dev_priv->dpio_lock);
4728
4729         vlv_update_cdclk(dev);
4730 }
4731
4732 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4733 {
4734         struct drm_i915_private *dev_priv = dev->dev_private;
4735         u32 val, cmd;
4736
4737         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4738
4739         switch (cdclk) {
4740         case 400000:
4741                 cmd = 3;
4742                 break;
4743         case 333333:
4744         case 320000:
4745                 cmd = 2;
4746                 break;
4747         case 266667:
4748                 cmd = 1;
4749                 break;
4750         case 200000:
4751                 cmd = 0;
4752                 break;
4753         default:
4754                 WARN_ON(1);
4755                 return;
4756         }
4757
4758         mutex_lock(&dev_priv->rps.hw_lock);
4759         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4760         val &= ~DSPFREQGUAR_MASK_CHV;
4761         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4762         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4763         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4764                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4765                      50)) {
4766                 DRM_ERROR("timed out waiting for CDclk change\n");
4767         }
4768         mutex_unlock(&dev_priv->rps.hw_lock);
4769
4770         vlv_update_cdclk(dev);
4771 }
4772
4773 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4774                                  int max_pixclk)
4775 {
4776         int vco = valleyview_get_vco(dev_priv);
4777         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4778
4779         /* FIXME: Punit isn't quite ready yet */
4780         if (IS_CHERRYVIEW(dev_priv->dev))
4781                 return 400000;
4782
4783         /*
4784          * Really only a few cases to deal with, as only 4 CDclks are supported:
4785          *   200MHz
4786          *   267MHz
4787          *   320/333MHz (depends on HPLL freq)
4788          *   400MHz
4789          * So we check to see whether we're above 90% of the lower bin and
4790          * adjust if needed.
4791          *
4792          * We seem to get an unstable or solid color picture at 200MHz.
4793          * Not sure what's wrong. For now use 200MHz only when all pipes
4794          * are off.
4795          */
4796         if (max_pixclk > freq_320*9/10)
4797                 return 400000;
4798         else if (max_pixclk > 266667*9/10)
4799                 return freq_320;
4800         else if (max_pixclk > 0)
4801                 return 266667;
4802         else
4803                 return 200000;
4804 }
4805
4806 /* compute the max pixel clock for new configuration */
4807 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4808 {
4809         struct drm_device *dev = dev_priv->dev;
4810         struct intel_crtc *intel_crtc;
4811         int max_pixclk = 0;
4812
4813         for_each_intel_crtc(dev, intel_crtc) {
4814                 if (intel_crtc->new_enabled)
4815                         max_pixclk = max(max_pixclk,
4816                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4817         }
4818
4819         return max_pixclk;
4820 }
4821
4822 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4823                                             unsigned *prepare_pipes)
4824 {
4825         struct drm_i915_private *dev_priv = dev->dev_private;
4826         struct intel_crtc *intel_crtc;
4827         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4828
4829         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4830             dev_priv->vlv_cdclk_freq)
4831                 return;
4832
4833         /* disable/enable all currently active pipes while we change cdclk */
4834         for_each_intel_crtc(dev, intel_crtc)
4835                 if (intel_crtc->base.enabled)
4836                         *prepare_pipes |= (1 << intel_crtc->pipe);
4837 }
4838
4839 static void valleyview_modeset_global_resources(struct drm_device *dev)
4840 {
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4843         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4844
4845         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4846                 if (IS_CHERRYVIEW(dev))
4847                         cherryview_set_cdclk(dev, req_cdclk);
4848                 else
4849                         valleyview_set_cdclk(dev, req_cdclk);
4850         }
4851
4852         modeset_update_crtc_power_domains(dev);
4853 }
4854
4855 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4856 {
4857         struct drm_device *dev = crtc->dev;
4858         struct drm_i915_private *dev_priv = to_i915(dev);
4859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860         struct intel_encoder *encoder;
4861         int pipe = intel_crtc->pipe;
4862         bool is_dsi;
4863
4864         WARN_ON(!crtc->enabled);
4865
4866         if (intel_crtc->active)
4867                 return;
4868
4869         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4870
4871         if (!is_dsi) {
4872                 if (IS_CHERRYVIEW(dev))
4873                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4874                 else
4875                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4876         }
4877
4878         if (intel_crtc->config.has_dp_encoder)
4879                 intel_dp_set_m_n(intel_crtc);
4880
4881         intel_set_pipe_timings(intel_crtc);
4882
4883         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4884                 struct drm_i915_private *dev_priv = dev->dev_private;
4885
4886                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4887                 I915_WRITE(CHV_CANVAS(pipe), 0);
4888         }
4889
4890         i9xx_set_pipeconf(intel_crtc);
4891
4892         intel_crtc->active = true;
4893
4894         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4895
4896         for_each_encoder_on_crtc(dev, crtc, encoder)
4897                 if (encoder->pre_pll_enable)
4898                         encoder->pre_pll_enable(encoder);
4899
4900         if (!is_dsi) {
4901                 if (IS_CHERRYVIEW(dev))
4902                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4903                 else
4904                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4905         }
4906
4907         for_each_encoder_on_crtc(dev, crtc, encoder)
4908                 if (encoder->pre_enable)
4909                         encoder->pre_enable(encoder);
4910
4911         i9xx_pfit_enable(intel_crtc);
4912
4913         intel_crtc_load_lut(crtc);
4914
4915         intel_update_watermarks(crtc);
4916         intel_enable_pipe(intel_crtc);
4917
4918         for_each_encoder_on_crtc(dev, crtc, encoder)
4919                 encoder->enable(encoder);
4920
4921         assert_vblank_disabled(crtc);
4922         drm_crtc_vblank_on(crtc);
4923
4924         intel_crtc_enable_planes(crtc);
4925
4926         /* Underruns don't raise interrupts, so check manually. */
4927         i9xx_check_fifo_underruns(dev_priv);
4928 }
4929
4930 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4931 {
4932         struct drm_device *dev = crtc->base.dev;
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934
4935         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4936         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4937 }
4938
4939 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4940 {
4941         struct drm_device *dev = crtc->dev;
4942         struct drm_i915_private *dev_priv = to_i915(dev);
4943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4944         struct intel_encoder *encoder;
4945         int pipe = intel_crtc->pipe;
4946
4947         WARN_ON(!crtc->enabled);
4948
4949         if (intel_crtc->active)
4950                 return;
4951
4952         i9xx_set_pll_dividers(intel_crtc);
4953
4954         if (intel_crtc->config.has_dp_encoder)
4955                 intel_dp_set_m_n(intel_crtc);
4956
4957         intel_set_pipe_timings(intel_crtc);
4958
4959         i9xx_set_pipeconf(intel_crtc);
4960
4961         intel_crtc->active = true;
4962
4963         if (!IS_GEN2(dev))
4964                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4965
4966         for_each_encoder_on_crtc(dev, crtc, encoder)
4967                 if (encoder->pre_enable)
4968                         encoder->pre_enable(encoder);
4969
4970         i9xx_enable_pll(intel_crtc);
4971
4972         i9xx_pfit_enable(intel_crtc);
4973
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_update_watermarks(crtc);
4977         intel_enable_pipe(intel_crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder)
4980                 encoder->enable(encoder);
4981
4982         assert_vblank_disabled(crtc);
4983         drm_crtc_vblank_on(crtc);
4984
4985         intel_crtc_enable_planes(crtc);
4986
4987         /*
4988          * Gen2 reports pipe underruns whenever all planes are disabled.
4989          * So don't enable underrun reporting before at least some planes
4990          * are enabled.
4991          * FIXME: Need to fix the logic to work when we turn off all planes
4992          * but leave the pipe running.
4993          */
4994         if (IS_GEN2(dev))
4995                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4996
4997         /* Underruns don't raise interrupts, so check manually. */
4998         i9xx_check_fifo_underruns(dev_priv);
4999 }
5000
5001 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5002 {
5003         struct drm_device *dev = crtc->base.dev;
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005
5006         if (!crtc->config.gmch_pfit.control)
5007                 return;
5008
5009         assert_pipe_disabled(dev_priv, crtc->pipe);
5010
5011         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5012                          I915_READ(PFIT_CONTROL));
5013         I915_WRITE(PFIT_CONTROL, 0);
5014 }
5015
5016 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5017 {
5018         struct drm_device *dev = crtc->dev;
5019         struct drm_i915_private *dev_priv = dev->dev_private;
5020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021         struct intel_encoder *encoder;
5022         int pipe = intel_crtc->pipe;
5023
5024         if (!intel_crtc->active)
5025                 return;
5026
5027         /*
5028          * Gen2 reports pipe underruns whenever all planes are disabled.
5029          * So diasble underrun reporting before all the planes get disabled.
5030          * FIXME: Need to fix the logic to work when we turn off all planes
5031          * but leave the pipe running.
5032          */
5033         if (IS_GEN2(dev))
5034                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5035
5036         /*
5037          * Vblank time updates from the shadow to live plane control register
5038          * are blocked if the memory self-refresh mode is active at that
5039          * moment. So to make sure the plane gets truly disabled, disable
5040          * first the self-refresh mode. The self-refresh enable bit in turn
5041          * will be checked/applied by the HW only at the next frame start
5042          * event which is after the vblank start event, so we need to have a
5043          * wait-for-vblank between disabling the plane and the pipe.
5044          */
5045         intel_set_memory_cxsr(dev_priv, false);
5046         intel_crtc_disable_planes(crtc);
5047
5048         /*
5049          * On gen2 planes are double buffered but the pipe isn't, so we must
5050          * wait for planes to fully turn off before disabling the pipe.
5051          * We also need to wait on all gmch platforms because of the
5052          * self-refresh mode constraint explained above.
5053          */
5054         intel_wait_for_vblank(dev, pipe);
5055
5056         drm_crtc_vblank_off(crtc);
5057         assert_vblank_disabled(crtc);
5058
5059         for_each_encoder_on_crtc(dev, crtc, encoder)
5060                 encoder->disable(encoder);
5061
5062         intel_disable_pipe(intel_crtc);
5063
5064         i9xx_pfit_disable(intel_crtc);
5065
5066         for_each_encoder_on_crtc(dev, crtc, encoder)
5067                 if (encoder->post_disable)
5068                         encoder->post_disable(encoder);
5069
5070         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5071                 if (IS_CHERRYVIEW(dev))
5072                         chv_disable_pll(dev_priv, pipe);
5073                 else if (IS_VALLEYVIEW(dev))
5074                         vlv_disable_pll(dev_priv, pipe);
5075                 else
5076                         i9xx_disable_pll(intel_crtc);
5077         }
5078
5079         if (!IS_GEN2(dev))
5080                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5081
5082         intel_crtc->active = false;
5083         intel_update_watermarks(crtc);
5084
5085         mutex_lock(&dev->struct_mutex);
5086         intel_update_fbc(dev);
5087         mutex_unlock(&dev->struct_mutex);
5088 }
5089
5090 static void i9xx_crtc_off(struct drm_crtc *crtc)
5091 {
5092 }
5093
5094 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5095                                     bool enabled)
5096 {
5097         struct drm_device *dev = crtc->dev;
5098         struct drm_i915_master_private *master_priv;
5099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5100         int pipe = intel_crtc->pipe;
5101
5102         if (!dev->primary->master)
5103                 return;
5104
5105         master_priv = dev->primary->master->driver_priv;
5106         if (!master_priv->sarea_priv)
5107                 return;
5108
5109         switch (pipe) {
5110         case 0:
5111                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5112                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5113                 break;
5114         case 1:
5115                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5116                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5117                 break;
5118         default:
5119                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5120                 break;
5121         }
5122 }
5123
5124 /* Master function to enable/disable CRTC and corresponding power wells */
5125 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5126 {
5127         struct drm_device *dev = crtc->dev;
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5130         enum intel_display_power_domain domain;
5131         unsigned long domains;
5132
5133         if (enable) {
5134                 if (!intel_crtc->active) {
5135                         domains = get_crtc_power_domains(crtc);
5136                         for_each_power_domain(domain, domains)
5137                                 intel_display_power_get(dev_priv, domain);
5138                         intel_crtc->enabled_power_domains = domains;
5139
5140                         dev_priv->display.crtc_enable(crtc);
5141                 }
5142         } else {
5143                 if (intel_crtc->active) {
5144                         dev_priv->display.crtc_disable(crtc);
5145
5146                         domains = intel_crtc->enabled_power_domains;
5147                         for_each_power_domain(domain, domains)
5148                                 intel_display_power_put(dev_priv, domain);
5149                         intel_crtc->enabled_power_domains = 0;
5150                 }
5151         }
5152 }
5153
5154 /**
5155  * Sets the power management mode of the pipe and plane.
5156  */
5157 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5158 {
5159         struct drm_device *dev = crtc->dev;
5160         struct intel_encoder *intel_encoder;
5161         bool enable = false;
5162
5163         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5164                 enable |= intel_encoder->connectors_active;
5165
5166         intel_crtc_control(crtc, enable);
5167
5168         intel_crtc_update_sarea(crtc, enable);
5169 }
5170
5171 static void intel_crtc_disable(struct drm_crtc *crtc)
5172 {
5173         struct drm_device *dev = crtc->dev;
5174         struct drm_connector *connector;
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5177         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5178
5179         /* crtc should still be enabled when we disable it. */
5180         WARN_ON(!crtc->enabled);
5181
5182         dev_priv->display.crtc_disable(crtc);
5183         intel_crtc_update_sarea(crtc, false);
5184         dev_priv->display.off(crtc);
5185
5186         if (crtc->primary->fb) {
5187                 mutex_lock(&dev->struct_mutex);
5188                 intel_unpin_fb_obj(old_obj);
5189                 i915_gem_track_fb(old_obj, NULL,
5190                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5191                 mutex_unlock(&dev->struct_mutex);
5192                 crtc->primary->fb = NULL;
5193         }
5194
5195         /* Update computed state. */
5196         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5197                 if (!connector->encoder || !connector->encoder->crtc)
5198                         continue;
5199
5200                 if (connector->encoder->crtc != crtc)
5201                         continue;
5202
5203                 connector->dpms = DRM_MODE_DPMS_OFF;
5204                 to_intel_encoder(connector->encoder)->connectors_active = false;
5205         }
5206 }
5207
5208 void intel_encoder_destroy(struct drm_encoder *encoder)
5209 {
5210         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5211
5212         drm_encoder_cleanup(encoder);
5213         kfree(intel_encoder);
5214 }
5215
5216 /* Simple dpms helper for encoders with just one connector, no cloning and only
5217  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5218  * state of the entire output pipe. */
5219 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5220 {
5221         if (mode == DRM_MODE_DPMS_ON) {
5222                 encoder->connectors_active = true;
5223
5224                 intel_crtc_update_dpms(encoder->base.crtc);
5225         } else {
5226                 encoder->connectors_active = false;
5227
5228                 intel_crtc_update_dpms(encoder->base.crtc);
5229         }
5230 }
5231
5232 /* Cross check the actual hw state with our own modeset state tracking (and it's
5233  * internal consistency). */
5234 static void intel_connector_check_state(struct intel_connector *connector)
5235 {
5236         if (connector->get_hw_state(connector)) {
5237                 struct intel_encoder *encoder = connector->encoder;
5238                 struct drm_crtc *crtc;
5239                 bool encoder_enabled;
5240                 enum pipe pipe;
5241
5242                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5243                               connector->base.base.id,
5244                               connector->base.name);
5245
5246                 /* there is no real hw state for MST connectors */
5247                 if (connector->mst_port)
5248                         return;
5249
5250                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5251                      "wrong connector dpms state\n");
5252                 WARN(connector->base.encoder != &encoder->base,
5253                      "active connector not linked to encoder\n");
5254
5255                 if (encoder) {
5256                         WARN(!encoder->connectors_active,
5257                              "encoder->connectors_active not set\n");
5258
5259                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5260                         WARN(!encoder_enabled, "encoder not enabled\n");
5261                         if (WARN_ON(!encoder->base.crtc))
5262                                 return;
5263
5264                         crtc = encoder->base.crtc;
5265
5266                         WARN(!crtc->enabled, "crtc not enabled\n");
5267                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5268                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5269                              "encoder active on the wrong pipe\n");
5270                 }
5271         }
5272 }
5273
5274 /* Even simpler default implementation, if there's really no special case to
5275  * consider. */
5276 void intel_connector_dpms(struct drm_connector *connector, int mode)
5277 {
5278         /* All the simple cases only support two dpms states. */
5279         if (mode != DRM_MODE_DPMS_ON)
5280                 mode = DRM_MODE_DPMS_OFF;
5281
5282         if (mode == connector->dpms)
5283                 return;
5284
5285         connector->dpms = mode;
5286
5287         /* Only need to change hw state when actually enabled */
5288         if (connector->encoder)
5289                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5290
5291         intel_modeset_check_state(connector->dev);
5292 }
5293
5294 /* Simple connector->get_hw_state implementation for encoders that support only
5295  * one connector and no cloning and hence the encoder state determines the state
5296  * of the connector. */
5297 bool intel_connector_get_hw_state(struct intel_connector *connector)
5298 {
5299         enum pipe pipe = 0;
5300         struct intel_encoder *encoder = connector->encoder;
5301
5302         return encoder->get_hw_state(encoder, &pipe);
5303 }
5304
5305 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5306                                      struct intel_crtc_config *pipe_config)
5307 {
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         struct intel_crtc *pipe_B_crtc =
5310                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5311
5312         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5313                       pipe_name(pipe), pipe_config->fdi_lanes);
5314         if (pipe_config->fdi_lanes > 4) {
5315                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5316                               pipe_name(pipe), pipe_config->fdi_lanes);
5317                 return false;
5318         }
5319
5320         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5321                 if (pipe_config->fdi_lanes > 2) {
5322                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5323                                       pipe_config->fdi_lanes);
5324                         return false;
5325                 } else {
5326                         return true;
5327                 }
5328         }
5329
5330         if (INTEL_INFO(dev)->num_pipes == 2)
5331                 return true;
5332
5333         /* Ivybridge 3 pipe is really complicated */
5334         switch (pipe) {
5335         case PIPE_A:
5336                 return true;
5337         case PIPE_B:
5338                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5339                     pipe_config->fdi_lanes > 2) {
5340                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5341                                       pipe_name(pipe), pipe_config->fdi_lanes);
5342                         return false;
5343                 }
5344                 return true;
5345         case PIPE_C:
5346                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5347                     pipe_B_crtc->config.fdi_lanes <= 2) {
5348                         if (pipe_config->fdi_lanes > 2) {
5349                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5350                                               pipe_name(pipe), pipe_config->fdi_lanes);
5351                                 return false;
5352                         }
5353                 } else {
5354                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5355                         return false;
5356                 }
5357                 return true;
5358         default:
5359                 BUG();
5360         }
5361 }
5362
5363 #define RETRY 1
5364 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5365                                        struct intel_crtc_config *pipe_config)
5366 {
5367         struct drm_device *dev = intel_crtc->base.dev;
5368         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5369         int lane, link_bw, fdi_dotclock;
5370         bool setup_ok, needs_recompute = false;
5371
5372 retry:
5373         /* FDI is a binary signal running at ~2.7GHz, encoding
5374          * each output octet as 10 bits. The actual frequency
5375          * is stored as a divider into a 100MHz clock, and the
5376          * mode pixel clock is stored in units of 1KHz.
5377          * Hence the bw of each lane in terms of the mode signal
5378          * is:
5379          */
5380         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5381
5382         fdi_dotclock = adjusted_mode->crtc_clock;
5383
5384         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5385                                            pipe_config->pipe_bpp);
5386
5387         pipe_config->fdi_lanes = lane;
5388
5389         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5390                                link_bw, &pipe_config->fdi_m_n);
5391
5392         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5393                                             intel_crtc->pipe, pipe_config);
5394         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5395                 pipe_config->pipe_bpp -= 2*3;
5396                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5397                               pipe_config->pipe_bpp);
5398                 needs_recompute = true;
5399                 pipe_config->bw_constrained = true;
5400
5401                 goto retry;
5402         }
5403
5404         if (needs_recompute)
5405                 return RETRY;
5406
5407         return setup_ok ? 0 : -EINVAL;
5408 }
5409
5410 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5411                                    struct intel_crtc_config *pipe_config)
5412 {
5413         pipe_config->ips_enabled = i915.enable_ips &&
5414                                    hsw_crtc_supports_ips(crtc) &&
5415                                    pipe_config->pipe_bpp <= 24;
5416 }
5417
5418 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5419                                      struct intel_crtc_config *pipe_config)
5420 {
5421         struct drm_device *dev = crtc->base.dev;
5422         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5423
5424         /* FIXME should check pixel clock limits on all platforms */
5425         if (INTEL_INFO(dev)->gen < 4) {
5426                 struct drm_i915_private *dev_priv = dev->dev_private;
5427                 int clock_limit =
5428                         dev_priv->display.get_display_clock_speed(dev);
5429
5430                 /*
5431                  * Enable pixel doubling when the dot clock
5432                  * is > 90% of the (display) core speed.
5433                  *
5434                  * GDG double wide on either pipe,
5435                  * otherwise pipe A only.
5436                  */
5437                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5438                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5439                         clock_limit *= 2;
5440                         pipe_config->double_wide = true;
5441                 }
5442
5443                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5444                         return -EINVAL;
5445         }
5446
5447         /*
5448          * Pipe horizontal size must be even in:
5449          * - DVO ganged mode
5450          * - LVDS dual channel mode
5451          * - Double wide pipe
5452          */
5453         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5454              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5455                 pipe_config->pipe_src_w &= ~1;
5456
5457         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5458          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5459          */
5460         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5461                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5462                 return -EINVAL;
5463
5464         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5465                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5466         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5467                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5468                  * for lvds. */
5469                 pipe_config->pipe_bpp = 8*3;
5470         }
5471
5472         if (HAS_IPS(dev))
5473                 hsw_compute_ips_config(crtc, pipe_config);
5474
5475         /*
5476          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5477          * old clock survives for now.
5478          */
5479         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5480                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5481
5482         if (pipe_config->has_pch_encoder)
5483                 return ironlake_fdi_compute_config(crtc, pipe_config);
5484
5485         return 0;
5486 }
5487
5488 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5489 {
5490         struct drm_i915_private *dev_priv = dev->dev_private;
5491         int vco = valleyview_get_vco(dev_priv);
5492         u32 val;
5493         int divider;
5494
5495         /* FIXME: Punit isn't quite ready yet */
5496         if (IS_CHERRYVIEW(dev))
5497                 return 400000;
5498
5499         mutex_lock(&dev_priv->dpio_lock);
5500         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5501         mutex_unlock(&dev_priv->dpio_lock);
5502
5503         divider = val & DISPLAY_FREQUENCY_VALUES;
5504
5505         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5506              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5507              "cdclk change in progress\n");
5508
5509         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5510 }
5511
5512 static int i945_get_display_clock_speed(struct drm_device *dev)
5513 {
5514         return 400000;
5515 }
5516
5517 static int i915_get_display_clock_speed(struct drm_device *dev)
5518 {
5519         return 333000;
5520 }
5521
5522 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5523 {
5524         return 200000;
5525 }
5526
5527 static int pnv_get_display_clock_speed(struct drm_device *dev)
5528 {
5529         u16 gcfgc = 0;
5530
5531         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5532
5533         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5534         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5535                 return 267000;
5536         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5537                 return 333000;
5538         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5539                 return 444000;
5540         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5541                 return 200000;
5542         default:
5543                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5544         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5545                 return 133000;
5546         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5547                 return 167000;
5548         }
5549 }
5550
5551 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5552 {
5553         u16 gcfgc = 0;
5554
5555         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5556
5557         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5558                 return 133000;
5559         else {
5560                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5561                 case GC_DISPLAY_CLOCK_333_MHZ:
5562                         return 333000;
5563                 default:
5564                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5565                         return 190000;
5566                 }
5567         }
5568 }
5569
5570 static int i865_get_display_clock_speed(struct drm_device *dev)
5571 {
5572         return 266000;
5573 }
5574
5575 static int i855_get_display_clock_speed(struct drm_device *dev)
5576 {
5577         u16 hpllcc = 0;
5578         /* Assume that the hardware is in the high speed state.  This
5579          * should be the default.
5580          */
5581         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5582         case GC_CLOCK_133_200:
5583         case GC_CLOCK_100_200:
5584                 return 200000;
5585         case GC_CLOCK_166_250:
5586                 return 250000;
5587         case GC_CLOCK_100_133:
5588                 return 133000;
5589         }
5590
5591         /* Shouldn't happen */
5592         return 0;
5593 }
5594
5595 static int i830_get_display_clock_speed(struct drm_device *dev)
5596 {
5597         return 133000;
5598 }
5599
5600 static void
5601 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5602 {
5603         while (*num > DATA_LINK_M_N_MASK ||
5604                *den > DATA_LINK_M_N_MASK) {
5605                 *num >>= 1;
5606                 *den >>= 1;
5607         }
5608 }
5609
5610 static void compute_m_n(unsigned int m, unsigned int n,
5611                         uint32_t *ret_m, uint32_t *ret_n)
5612 {
5613         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5614         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5615         intel_reduce_m_n_ratio(ret_m, ret_n);
5616 }
5617
5618 void
5619 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5620                        int pixel_clock, int link_clock,
5621                        struct intel_link_m_n *m_n)
5622 {
5623         m_n->tu = 64;
5624
5625         compute_m_n(bits_per_pixel * pixel_clock,
5626                     link_clock * nlanes * 8,
5627                     &m_n->gmch_m, &m_n->gmch_n);
5628
5629         compute_m_n(pixel_clock, link_clock,
5630                     &m_n->link_m, &m_n->link_n);
5631 }
5632
5633 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5634 {
5635         if (i915.panel_use_ssc >= 0)
5636                 return i915.panel_use_ssc != 0;
5637         return dev_priv->vbt.lvds_use_ssc
5638                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5639 }
5640
5641 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5642 {
5643         struct drm_device *dev = crtc->base.dev;
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         int refclk;
5646
5647         if (IS_VALLEYVIEW(dev)) {
5648                 refclk = 100000;
5649         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5650             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5651                 refclk = dev_priv->vbt.lvds_ssc_freq;
5652                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5653         } else if (!IS_GEN2(dev)) {
5654                 refclk = 96000;
5655         } else {
5656                 refclk = 48000;
5657         }
5658
5659         return refclk;
5660 }
5661
5662 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5663 {
5664         return (1 << dpll->n) << 16 | dpll->m2;
5665 }
5666
5667 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5668 {
5669         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5670 }
5671
5672 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5673                                      intel_clock_t *reduced_clock)
5674 {
5675         struct drm_device *dev = crtc->base.dev;
5676         u32 fp, fp2 = 0;
5677
5678         if (IS_PINEVIEW(dev)) {
5679                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5680                 if (reduced_clock)
5681                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5682         } else {
5683                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5684                 if (reduced_clock)
5685                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5686         }
5687
5688         crtc->config.dpll_hw_state.fp0 = fp;
5689
5690         crtc->lowfreq_avail = false;
5691         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5692             reduced_clock && i915.powersave) {
5693                 crtc->config.dpll_hw_state.fp1 = fp2;
5694                 crtc->lowfreq_avail = true;
5695         } else {
5696                 crtc->config.dpll_hw_state.fp1 = fp;
5697         }
5698 }
5699
5700 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5701                 pipe)
5702 {
5703         u32 reg_val;
5704
5705         /*
5706          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5707          * and set it to a reasonable value instead.
5708          */
5709         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5710         reg_val &= 0xffffff00;
5711         reg_val |= 0x00000030;
5712         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5713
5714         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5715         reg_val &= 0x8cffffff;
5716         reg_val = 0x8c000000;
5717         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5718
5719         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5720         reg_val &= 0xffffff00;
5721         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5722
5723         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5724         reg_val &= 0x00ffffff;
5725         reg_val |= 0xb0000000;
5726         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5727 }
5728
5729 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5730                                          struct intel_link_m_n *m_n)
5731 {
5732         struct drm_device *dev = crtc->base.dev;
5733         struct drm_i915_private *dev_priv = dev->dev_private;
5734         int pipe = crtc->pipe;
5735
5736         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5737         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5738         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5739         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5740 }
5741
5742 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5743                                          struct intel_link_m_n *m_n,
5744                                          struct intel_link_m_n *m2_n2)
5745 {
5746         struct drm_device *dev = crtc->base.dev;
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         int pipe = crtc->pipe;
5749         enum transcoder transcoder = crtc->config.cpu_transcoder;
5750
5751         if (INTEL_INFO(dev)->gen >= 5) {
5752                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5753                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5754                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5755                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5756                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5757                  * for gen < 8) and if DRRS is supported (to make sure the
5758                  * registers are not unnecessarily accessed).
5759                  */
5760                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5761                         crtc->config.has_drrs) {
5762                         I915_WRITE(PIPE_DATA_M2(transcoder),
5763                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5764                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5765                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5766                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5767                 }
5768         } else {
5769                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5770                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5771                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5772                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5773         }
5774 }
5775
5776 void intel_dp_set_m_n(struct intel_crtc *crtc)
5777 {
5778         if (crtc->config.has_pch_encoder)
5779                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5780         else
5781                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5782                                                    &crtc->config.dp_m2_n2);
5783 }
5784
5785 static void vlv_update_pll(struct intel_crtc *crtc,
5786                            struct intel_crtc_config *pipe_config)
5787 {
5788         u32 dpll, dpll_md;
5789
5790         /*
5791          * Enable DPIO clock input. We should never disable the reference
5792          * clock for pipe B, since VGA hotplug / manual detection depends
5793          * on it.
5794          */
5795         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5796                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5797         /* We should never disable this, set it here for state tracking */
5798         if (crtc->pipe == PIPE_B)
5799                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5800         dpll |= DPLL_VCO_ENABLE;
5801         pipe_config->dpll_hw_state.dpll = dpll;
5802
5803         dpll_md = (pipe_config->pixel_multiplier - 1)
5804                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5805         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5806 }
5807
5808 static void vlv_prepare_pll(struct intel_crtc *crtc,
5809                             const struct intel_crtc_config *pipe_config)
5810 {
5811         struct drm_device *dev = crtc->base.dev;
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         int pipe = crtc->pipe;
5814         u32 mdiv;
5815         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5816         u32 coreclk, reg_val;
5817
5818         mutex_lock(&dev_priv->dpio_lock);
5819
5820         bestn = pipe_config->dpll.n;
5821         bestm1 = pipe_config->dpll.m1;
5822         bestm2 = pipe_config->dpll.m2;
5823         bestp1 = pipe_config->dpll.p1;
5824         bestp2 = pipe_config->dpll.p2;
5825
5826         /* See eDP HDMI DPIO driver vbios notes doc */
5827
5828         /* PLL B needs special handling */
5829         if (pipe == PIPE_B)
5830                 vlv_pllb_recal_opamp(dev_priv, pipe);
5831
5832         /* Set up Tx target for periodic Rcomp update */
5833         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5834
5835         /* Disable target IRef on PLL */
5836         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5837         reg_val &= 0x00ffffff;
5838         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5839
5840         /* Disable fast lock */
5841         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5842
5843         /* Set idtafcrecal before PLL is enabled */
5844         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5845         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5846         mdiv |= ((bestn << DPIO_N_SHIFT));
5847         mdiv |= (1 << DPIO_K_SHIFT);
5848
5849         /*
5850          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5851          * but we don't support that).
5852          * Note: don't use the DAC post divider as it seems unstable.
5853          */
5854         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5855         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5856
5857         mdiv |= DPIO_ENABLE_CALIBRATION;
5858         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5859
5860         /* Set HBR and RBR LPF coefficients */
5861         if (pipe_config->port_clock == 162000 ||
5862             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5863             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5864                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5865                                  0x009f0003);
5866         else
5867                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5868                                  0x00d0000f);
5869
5870         if (crtc->config.has_dp_encoder) {
5871                 /* Use SSC source */
5872                 if (pipe == PIPE_A)
5873                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5874                                          0x0df40000);
5875                 else
5876                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5877                                          0x0df70000);
5878         } else { /* HDMI or VGA */
5879                 /* Use bend source */
5880                 if (pipe == PIPE_A)
5881                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5882                                          0x0df70000);
5883                 else
5884                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5885                                          0x0df40000);
5886         }
5887
5888         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5889         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5890         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5891             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5892                 coreclk |= 0x01000000;
5893         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5894
5895         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5896         mutex_unlock(&dev_priv->dpio_lock);
5897 }
5898
5899 static void chv_update_pll(struct intel_crtc *crtc,
5900                            struct intel_crtc_config *pipe_config)
5901 {
5902         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5903                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5904                 DPLL_VCO_ENABLE;
5905         if (crtc->pipe != PIPE_A)
5906                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5907
5908         pipe_config->dpll_hw_state.dpll_md =
5909                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5910 }
5911
5912 static void chv_prepare_pll(struct intel_crtc *crtc,
5913                             const struct intel_crtc_config *pipe_config)
5914 {
5915         struct drm_device *dev = crtc->base.dev;
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917         int pipe = crtc->pipe;
5918         int dpll_reg = DPLL(crtc->pipe);
5919         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5920         u32 loopfilter, intcoeff;
5921         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5922         int refclk;
5923
5924         bestn = pipe_config->dpll.n;
5925         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5926         bestm1 = pipe_config->dpll.m1;
5927         bestm2 = pipe_config->dpll.m2 >> 22;
5928         bestp1 = pipe_config->dpll.p1;
5929         bestp2 = pipe_config->dpll.p2;
5930
5931         /*
5932          * Enable Refclk and SSC
5933          */
5934         I915_WRITE(dpll_reg,
5935                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5936
5937         mutex_lock(&dev_priv->dpio_lock);
5938
5939         /* p1 and p2 divider */
5940         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5941                         5 << DPIO_CHV_S1_DIV_SHIFT |
5942                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5943                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5944                         1 << DPIO_CHV_K_DIV_SHIFT);
5945
5946         /* Feedback post-divider - m2 */
5947         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5948
5949         /* Feedback refclk divider - n and m1 */
5950         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5951                         DPIO_CHV_M1_DIV_BY_2 |
5952                         1 << DPIO_CHV_N_DIV_SHIFT);
5953
5954         /* M2 fraction division */
5955         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5956
5957         /* M2 fraction division enable */
5958         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5959                        DPIO_CHV_FRAC_DIV_EN |
5960                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5961
5962         /* Loop filter */
5963         refclk = i9xx_get_refclk(crtc, 0);
5964         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5965                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5966         if (refclk == 100000)
5967                 intcoeff = 11;
5968         else if (refclk == 38400)
5969                 intcoeff = 10;
5970         else
5971                 intcoeff = 9;
5972         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5973         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5974
5975         /* AFC Recal */
5976         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5977                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5978                         DPIO_AFC_RECAL);
5979
5980         mutex_unlock(&dev_priv->dpio_lock);
5981 }
5982
5983 /**
5984  * vlv_force_pll_on - forcibly enable just the PLL
5985  * @dev_priv: i915 private structure
5986  * @pipe: pipe PLL to enable
5987  * @dpll: PLL configuration
5988  *
5989  * Enable the PLL for @pipe using the supplied @dpll config. To be used
5990  * in cases where we need the PLL enabled even when @pipe is not going to
5991  * be enabled.
5992  */
5993 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
5994                       const struct dpll *dpll)
5995 {
5996         struct intel_crtc *crtc =
5997                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5998         struct intel_crtc_config pipe_config = {
5999                 .pixel_multiplier = 1,
6000                 .dpll = *dpll,
6001         };
6002
6003         if (IS_CHERRYVIEW(dev)) {
6004                 chv_update_pll(crtc, &pipe_config);
6005                 chv_prepare_pll(crtc, &pipe_config);
6006                 chv_enable_pll(crtc, &pipe_config);
6007         } else {
6008                 vlv_update_pll(crtc, &pipe_config);
6009                 vlv_prepare_pll(crtc, &pipe_config);
6010                 vlv_enable_pll(crtc, &pipe_config);
6011         }
6012 }
6013
6014 /**
6015  * vlv_force_pll_off - forcibly disable just the PLL
6016  * @dev_priv: i915 private structure
6017  * @pipe: pipe PLL to disable
6018  *
6019  * Disable the PLL for @pipe. To be used in cases where we need
6020  * the PLL enabled even when @pipe is not going to be enabled.
6021  */
6022 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6023 {
6024         if (IS_CHERRYVIEW(dev))
6025                 chv_disable_pll(to_i915(dev), pipe);
6026         else
6027                 vlv_disable_pll(to_i915(dev), pipe);
6028 }
6029
6030 static void i9xx_update_pll(struct intel_crtc *crtc,
6031                             intel_clock_t *reduced_clock,
6032                             int num_connectors)
6033 {
6034         struct drm_device *dev = crtc->base.dev;
6035         struct drm_i915_private *dev_priv = dev->dev_private;
6036         u32 dpll;
6037         bool is_sdvo;
6038         struct dpll *clock = &crtc->new_config->dpll;
6039
6040         i9xx_update_pll_dividers(crtc, reduced_clock);
6041
6042         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6043                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6044
6045         dpll = DPLL_VGA_MODE_DIS;
6046
6047         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6048                 dpll |= DPLLB_MODE_LVDS;
6049         else
6050                 dpll |= DPLLB_MODE_DAC_SERIAL;
6051
6052         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6053                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6054                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6055         }
6056
6057         if (is_sdvo)
6058                 dpll |= DPLL_SDVO_HIGH_SPEED;
6059
6060         if (crtc->new_config->has_dp_encoder)
6061                 dpll |= DPLL_SDVO_HIGH_SPEED;
6062
6063         /* compute bitmask from p1 value */
6064         if (IS_PINEVIEW(dev))
6065                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6066         else {
6067                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6068                 if (IS_G4X(dev) && reduced_clock)
6069                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6070         }
6071         switch (clock->p2) {
6072         case 5:
6073                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6074                 break;
6075         case 7:
6076                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6077                 break;
6078         case 10:
6079                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6080                 break;
6081         case 14:
6082                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6083                 break;
6084         }
6085         if (INTEL_INFO(dev)->gen >= 4)
6086                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6087
6088         if (crtc->new_config->sdvo_tv_clock)
6089                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6090         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6091                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6092                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6093         else
6094                 dpll |= PLL_REF_INPUT_DREFCLK;
6095
6096         dpll |= DPLL_VCO_ENABLE;
6097         crtc->new_config->dpll_hw_state.dpll = dpll;
6098
6099         if (INTEL_INFO(dev)->gen >= 4) {
6100                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6101                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6102                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6103         }
6104 }
6105
6106 static void i8xx_update_pll(struct intel_crtc *crtc,
6107                             intel_clock_t *reduced_clock,
6108                             int num_connectors)
6109 {
6110         struct drm_device *dev = crtc->base.dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         u32 dpll;
6113         struct dpll *clock = &crtc->new_config->dpll;
6114
6115         i9xx_update_pll_dividers(crtc, reduced_clock);
6116
6117         dpll = DPLL_VGA_MODE_DIS;
6118
6119         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6120                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6121         } else {
6122                 if (clock->p1 == 2)
6123                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6124                 else
6125                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6126                 if (clock->p2 == 4)
6127                         dpll |= PLL_P2_DIVIDE_BY_4;
6128         }
6129
6130         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6131                 dpll |= DPLL_DVO_2X_MODE;
6132
6133         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6134                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6135                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6136         else
6137                 dpll |= PLL_REF_INPUT_DREFCLK;
6138
6139         dpll |= DPLL_VCO_ENABLE;
6140         crtc->new_config->dpll_hw_state.dpll = dpll;
6141 }
6142
6143 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6144 {
6145         struct drm_device *dev = intel_crtc->base.dev;
6146         struct drm_i915_private *dev_priv = dev->dev_private;
6147         enum pipe pipe = intel_crtc->pipe;
6148         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6149         struct drm_display_mode *adjusted_mode =
6150                 &intel_crtc->config.adjusted_mode;
6151         uint32_t crtc_vtotal, crtc_vblank_end;
6152         int vsyncshift = 0;
6153
6154         /* We need to be careful not to changed the adjusted mode, for otherwise
6155          * the hw state checker will get angry at the mismatch. */
6156         crtc_vtotal = adjusted_mode->crtc_vtotal;
6157         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6158
6159         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6160                 /* the chip adds 2 halflines automatically */
6161                 crtc_vtotal -= 1;
6162                 crtc_vblank_end -= 1;
6163
6164                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6165                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6166                 else
6167                         vsyncshift = adjusted_mode->crtc_hsync_start -
6168                                 adjusted_mode->crtc_htotal / 2;
6169                 if (vsyncshift < 0)
6170                         vsyncshift += adjusted_mode->crtc_htotal;
6171         }
6172
6173         if (INTEL_INFO(dev)->gen > 3)
6174                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6175
6176         I915_WRITE(HTOTAL(cpu_transcoder),
6177                    (adjusted_mode->crtc_hdisplay - 1) |
6178                    ((adjusted_mode->crtc_htotal - 1) << 16));
6179         I915_WRITE(HBLANK(cpu_transcoder),
6180                    (adjusted_mode->crtc_hblank_start - 1) |
6181                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6182         I915_WRITE(HSYNC(cpu_transcoder),
6183                    (adjusted_mode->crtc_hsync_start - 1) |
6184                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6185
6186         I915_WRITE(VTOTAL(cpu_transcoder),
6187                    (adjusted_mode->crtc_vdisplay - 1) |
6188                    ((crtc_vtotal - 1) << 16));
6189         I915_WRITE(VBLANK(cpu_transcoder),
6190                    (adjusted_mode->crtc_vblank_start - 1) |
6191                    ((crtc_vblank_end - 1) << 16));
6192         I915_WRITE(VSYNC(cpu_transcoder),
6193                    (adjusted_mode->crtc_vsync_start - 1) |
6194                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6195
6196         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6197          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6198          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6199          * bits. */
6200         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6201             (pipe == PIPE_B || pipe == PIPE_C))
6202                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6203
6204         /* pipesrc controls the size that is scaled from, which should
6205          * always be the user's requested size.
6206          */
6207         I915_WRITE(PIPESRC(pipe),
6208                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6209                    (intel_crtc->config.pipe_src_h - 1));
6210 }
6211
6212 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6213                                    struct intel_crtc_config *pipe_config)
6214 {
6215         struct drm_device *dev = crtc->base.dev;
6216         struct drm_i915_private *dev_priv = dev->dev_private;
6217         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6218         uint32_t tmp;
6219
6220         tmp = I915_READ(HTOTAL(cpu_transcoder));
6221         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6222         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6223         tmp = I915_READ(HBLANK(cpu_transcoder));
6224         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6225         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6226         tmp = I915_READ(HSYNC(cpu_transcoder));
6227         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6228         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6229
6230         tmp = I915_READ(VTOTAL(cpu_transcoder));
6231         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6232         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6233         tmp = I915_READ(VBLANK(cpu_transcoder));
6234         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6235         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6236         tmp = I915_READ(VSYNC(cpu_transcoder));
6237         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6238         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6239
6240         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6241                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6242                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6243                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6244         }
6245
6246         tmp = I915_READ(PIPESRC(crtc->pipe));
6247         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6248         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6249
6250         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6251         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6252 }
6253
6254 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6255                                  struct intel_crtc_config *pipe_config)
6256 {
6257         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6258         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6259         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6260         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6261
6262         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6263         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6264         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6265         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6266
6267         mode->flags = pipe_config->adjusted_mode.flags;
6268
6269         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6270         mode->flags |= pipe_config->adjusted_mode.flags;
6271 }
6272
6273 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6274 {
6275         struct drm_device *dev = intel_crtc->base.dev;
6276         struct drm_i915_private *dev_priv = dev->dev_private;
6277         uint32_t pipeconf;
6278
6279         pipeconf = 0;
6280
6281         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6282             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6283                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6284
6285         if (intel_crtc->config.double_wide)
6286                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6287
6288         /* only g4x and later have fancy bpc/dither controls */
6289         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6290                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6291                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6292                         pipeconf |= PIPECONF_DITHER_EN |
6293                                     PIPECONF_DITHER_TYPE_SP;
6294
6295                 switch (intel_crtc->config.pipe_bpp) {
6296                 case 18:
6297                         pipeconf |= PIPECONF_6BPC;
6298                         break;
6299                 case 24:
6300                         pipeconf |= PIPECONF_8BPC;
6301                         break;
6302                 case 30:
6303                         pipeconf |= PIPECONF_10BPC;
6304                         break;
6305                 default:
6306                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6307                         BUG();
6308                 }
6309         }
6310
6311         if (HAS_PIPE_CXSR(dev)) {
6312                 if (intel_crtc->lowfreq_avail) {
6313                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6314                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6315                 } else {
6316                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6317                 }
6318         }
6319
6320         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6321                 if (INTEL_INFO(dev)->gen < 4 ||
6322                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6323                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6324                 else
6325                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6326         } else
6327                 pipeconf |= PIPECONF_PROGRESSIVE;
6328
6329         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6330                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6331
6332         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6333         POSTING_READ(PIPECONF(intel_crtc->pipe));
6334 }
6335
6336 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6337                               int x, int y,
6338                               struct drm_framebuffer *fb)
6339 {
6340         struct drm_device *dev = crtc->base.dev;
6341         struct drm_i915_private *dev_priv = dev->dev_private;
6342         int refclk, num_connectors = 0;
6343         intel_clock_t clock, reduced_clock;
6344         bool ok, has_reduced_clock = false;
6345         bool is_lvds = false, is_dsi = false;
6346         struct intel_encoder *encoder;
6347         const intel_limit_t *limit;
6348
6349         for_each_intel_encoder(dev, encoder) {
6350                 if (encoder->new_crtc != crtc)
6351                         continue;
6352
6353                 switch (encoder->type) {
6354                 case INTEL_OUTPUT_LVDS:
6355                         is_lvds = true;
6356                         break;
6357                 case INTEL_OUTPUT_DSI:
6358                         is_dsi = true;
6359                         break;
6360                 default:
6361                         break;
6362                 }
6363
6364                 num_connectors++;
6365         }
6366
6367         if (is_dsi)
6368                 return 0;
6369
6370         if (!crtc->new_config->clock_set) {
6371                 refclk = i9xx_get_refclk(crtc, num_connectors);
6372
6373                 /*
6374                  * Returns a set of divisors for the desired target clock with
6375                  * the given refclk, or FALSE.  The returned values represent
6376                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6377                  * 2) / p1 / p2.
6378                  */
6379                 limit = intel_limit(crtc, refclk);
6380                 ok = dev_priv->display.find_dpll(limit, crtc,
6381                                                  crtc->new_config->port_clock,
6382                                                  refclk, NULL, &clock);
6383                 if (!ok) {
6384                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6385                         return -EINVAL;
6386                 }
6387
6388                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6389                         /*
6390                          * Ensure we match the reduced clock's P to the target
6391                          * clock.  If the clocks don't match, we can't switch
6392                          * the display clock by using the FP0/FP1. In such case
6393                          * we will disable the LVDS downclock feature.
6394                          */
6395                         has_reduced_clock =
6396                                 dev_priv->display.find_dpll(limit, crtc,
6397                                                             dev_priv->lvds_downclock,
6398                                                             refclk, &clock,
6399                                                             &reduced_clock);
6400                 }
6401                 /* Compat-code for transition, will disappear. */
6402                 crtc->new_config->dpll.n = clock.n;
6403                 crtc->new_config->dpll.m1 = clock.m1;
6404                 crtc->new_config->dpll.m2 = clock.m2;
6405                 crtc->new_config->dpll.p1 = clock.p1;
6406                 crtc->new_config->dpll.p2 = clock.p2;
6407         }
6408
6409         if (IS_GEN2(dev)) {
6410                 i8xx_update_pll(crtc,
6411                                 has_reduced_clock ? &reduced_clock : NULL,
6412                                 num_connectors);
6413         } else if (IS_CHERRYVIEW(dev)) {
6414                 chv_update_pll(crtc, crtc->new_config);
6415         } else if (IS_VALLEYVIEW(dev)) {
6416                 vlv_update_pll(crtc, crtc->new_config);
6417         } else {
6418                 i9xx_update_pll(crtc,
6419                                 has_reduced_clock ? &reduced_clock : NULL,
6420                                 num_connectors);
6421         }
6422
6423         return 0;
6424 }
6425
6426 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6427                                  struct intel_crtc_config *pipe_config)
6428 {
6429         struct drm_device *dev = crtc->base.dev;
6430         struct drm_i915_private *dev_priv = dev->dev_private;
6431         uint32_t tmp;
6432
6433         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6434                 return;
6435
6436         tmp = I915_READ(PFIT_CONTROL);
6437         if (!(tmp & PFIT_ENABLE))
6438                 return;
6439
6440         /* Check whether the pfit is attached to our pipe. */
6441         if (INTEL_INFO(dev)->gen < 4) {
6442                 if (crtc->pipe != PIPE_B)
6443                         return;
6444         } else {
6445                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6446                         return;
6447         }
6448
6449         pipe_config->gmch_pfit.control = tmp;
6450         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6451         if (INTEL_INFO(dev)->gen < 5)
6452                 pipe_config->gmch_pfit.lvds_border_bits =
6453                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6454 }
6455
6456 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6457                                struct intel_crtc_config *pipe_config)
6458 {
6459         struct drm_device *dev = crtc->base.dev;
6460         struct drm_i915_private *dev_priv = dev->dev_private;
6461         int pipe = pipe_config->cpu_transcoder;
6462         intel_clock_t clock;
6463         u32 mdiv;
6464         int refclk = 100000;
6465
6466         /* In case of MIPI DPLL will not even be used */
6467         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6468                 return;
6469
6470         mutex_lock(&dev_priv->dpio_lock);
6471         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6472         mutex_unlock(&dev_priv->dpio_lock);
6473
6474         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6475         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6476         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6477         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6478         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6479
6480         vlv_clock(refclk, &clock);
6481
6482         /* clock.dot is the fast clock */
6483         pipe_config->port_clock = clock.dot / 5;
6484 }
6485
6486 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6487                                   struct intel_plane_config *plane_config)
6488 {
6489         struct drm_device *dev = crtc->base.dev;
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         u32 val, base, offset;
6492         int pipe = crtc->pipe, plane = crtc->plane;
6493         int fourcc, pixel_format;
6494         int aligned_height;
6495
6496         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6497         if (!crtc->base.primary->fb) {
6498                 DRM_DEBUG_KMS("failed to alloc fb\n");
6499                 return;
6500         }
6501
6502         val = I915_READ(DSPCNTR(plane));
6503
6504         if (INTEL_INFO(dev)->gen >= 4)
6505                 if (val & DISPPLANE_TILED)
6506                         plane_config->tiled = true;
6507
6508         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6509         fourcc = intel_format_to_fourcc(pixel_format);
6510         crtc->base.primary->fb->pixel_format = fourcc;
6511         crtc->base.primary->fb->bits_per_pixel =
6512                 drm_format_plane_cpp(fourcc, 0) * 8;
6513
6514         if (INTEL_INFO(dev)->gen >= 4) {
6515                 if (plane_config->tiled)
6516                         offset = I915_READ(DSPTILEOFF(plane));
6517                 else
6518                         offset = I915_READ(DSPLINOFF(plane));
6519                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6520         } else {
6521                 base = I915_READ(DSPADDR(plane));
6522         }
6523         plane_config->base = base;
6524
6525         val = I915_READ(PIPESRC(pipe));
6526         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6527         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6528
6529         val = I915_READ(DSPSTRIDE(pipe));
6530         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6531
6532         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6533                                             plane_config->tiled);
6534
6535         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6536                                         aligned_height);
6537
6538         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6539                       pipe, plane, crtc->base.primary->fb->width,
6540                       crtc->base.primary->fb->height,
6541                       crtc->base.primary->fb->bits_per_pixel, base,
6542                       crtc->base.primary->fb->pitches[0],
6543                       plane_config->size);
6544
6545 }
6546
6547 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6548                                struct intel_crtc_config *pipe_config)
6549 {
6550         struct drm_device *dev = crtc->base.dev;
6551         struct drm_i915_private *dev_priv = dev->dev_private;
6552         int pipe = pipe_config->cpu_transcoder;
6553         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6554         intel_clock_t clock;
6555         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6556         int refclk = 100000;
6557
6558         mutex_lock(&dev_priv->dpio_lock);
6559         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6560         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6561         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6562         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6563         mutex_unlock(&dev_priv->dpio_lock);
6564
6565         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6566         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6567         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6568         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6569         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6570
6571         chv_clock(refclk, &clock);
6572
6573         /* clock.dot is the fast clock */
6574         pipe_config->port_clock = clock.dot / 5;
6575 }
6576
6577 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6578                                  struct intel_crtc_config *pipe_config)
6579 {
6580         struct drm_device *dev = crtc->base.dev;
6581         struct drm_i915_private *dev_priv = dev->dev_private;
6582         uint32_t tmp;
6583
6584         if (!intel_display_power_is_enabled(dev_priv,
6585                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6586                 return false;
6587
6588         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6589         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6590
6591         tmp = I915_READ(PIPECONF(crtc->pipe));
6592         if (!(tmp & PIPECONF_ENABLE))
6593                 return false;
6594
6595         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6596                 switch (tmp & PIPECONF_BPC_MASK) {
6597                 case PIPECONF_6BPC:
6598                         pipe_config->pipe_bpp = 18;
6599                         break;
6600                 case PIPECONF_8BPC:
6601                         pipe_config->pipe_bpp = 24;
6602                         break;
6603                 case PIPECONF_10BPC:
6604                         pipe_config->pipe_bpp = 30;
6605                         break;
6606                 default:
6607                         break;
6608                 }
6609         }
6610
6611         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6612                 pipe_config->limited_color_range = true;
6613
6614         if (INTEL_INFO(dev)->gen < 4)
6615                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6616
6617         intel_get_pipe_timings(crtc, pipe_config);
6618
6619         i9xx_get_pfit_config(crtc, pipe_config);
6620
6621         if (INTEL_INFO(dev)->gen >= 4) {
6622                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6623                 pipe_config->pixel_multiplier =
6624                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6625                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6626                 pipe_config->dpll_hw_state.dpll_md = tmp;
6627         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6628                 tmp = I915_READ(DPLL(crtc->pipe));
6629                 pipe_config->pixel_multiplier =
6630                         ((tmp & SDVO_MULTIPLIER_MASK)
6631                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6632         } else {
6633                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6634                  * port and will be fixed up in the encoder->get_config
6635                  * function. */
6636                 pipe_config->pixel_multiplier = 1;
6637         }
6638         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6639         if (!IS_VALLEYVIEW(dev)) {
6640                 /*
6641                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6642                  * on 830. Filter it out here so that we don't
6643                  * report errors due to that.
6644                  */
6645                 if (IS_I830(dev))
6646                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6647
6648                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6649                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6650         } else {
6651                 /* Mask out read-only status bits. */
6652                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6653                                                      DPLL_PORTC_READY_MASK |
6654                                                      DPLL_PORTB_READY_MASK);
6655         }
6656
6657         if (IS_CHERRYVIEW(dev))
6658                 chv_crtc_clock_get(crtc, pipe_config);
6659         else if (IS_VALLEYVIEW(dev))
6660                 vlv_crtc_clock_get(crtc, pipe_config);
6661         else
6662                 i9xx_crtc_clock_get(crtc, pipe_config);
6663
6664         return true;
6665 }
6666
6667 static void ironlake_init_pch_refclk(struct drm_device *dev)
6668 {
6669         struct drm_i915_private *dev_priv = dev->dev_private;
6670         struct intel_encoder *encoder;
6671         u32 val, final;
6672         bool has_lvds = false;
6673         bool has_cpu_edp = false;
6674         bool has_panel = false;
6675         bool has_ck505 = false;
6676         bool can_ssc = false;
6677
6678         /* We need to take the global config into account */
6679         for_each_intel_encoder(dev, encoder) {
6680                 switch (encoder->type) {
6681                 case INTEL_OUTPUT_LVDS:
6682                         has_panel = true;
6683                         has_lvds = true;
6684                         break;
6685                 case INTEL_OUTPUT_EDP:
6686                         has_panel = true;
6687                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6688                                 has_cpu_edp = true;
6689                         break;
6690                 default:
6691                         break;
6692                 }
6693         }
6694
6695         if (HAS_PCH_IBX(dev)) {
6696                 has_ck505 = dev_priv->vbt.display_clock_mode;
6697                 can_ssc = has_ck505;
6698         } else {
6699                 has_ck505 = false;
6700                 can_ssc = true;
6701         }
6702
6703         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6704                       has_panel, has_lvds, has_ck505);
6705
6706         /* Ironlake: try to setup display ref clock before DPLL
6707          * enabling. This is only under driver's control after
6708          * PCH B stepping, previous chipset stepping should be
6709          * ignoring this setting.
6710          */
6711         val = I915_READ(PCH_DREF_CONTROL);
6712
6713         /* As we must carefully and slowly disable/enable each source in turn,
6714          * compute the final state we want first and check if we need to
6715          * make any changes at all.
6716          */
6717         final = val;
6718         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6719         if (has_ck505)
6720                 final |= DREF_NONSPREAD_CK505_ENABLE;
6721         else
6722                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6723
6724         final &= ~DREF_SSC_SOURCE_MASK;
6725         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6726         final &= ~DREF_SSC1_ENABLE;
6727
6728         if (has_panel) {
6729                 final |= DREF_SSC_SOURCE_ENABLE;
6730
6731                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6732                         final |= DREF_SSC1_ENABLE;
6733
6734                 if (has_cpu_edp) {
6735                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6736                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6737                         else
6738                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6739                 } else
6740                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6741         } else {
6742                 final |= DREF_SSC_SOURCE_DISABLE;
6743                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6744         }
6745
6746         if (final == val)
6747                 return;
6748
6749         /* Always enable nonspread source */
6750         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6751
6752         if (has_ck505)
6753                 val |= DREF_NONSPREAD_CK505_ENABLE;
6754         else
6755                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6756
6757         if (has_panel) {
6758                 val &= ~DREF_SSC_SOURCE_MASK;
6759                 val |= DREF_SSC_SOURCE_ENABLE;
6760
6761                 /* SSC must be turned on before enabling the CPU output  */
6762                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6763                         DRM_DEBUG_KMS("Using SSC on panel\n");
6764                         val |= DREF_SSC1_ENABLE;
6765                 } else
6766                         val &= ~DREF_SSC1_ENABLE;
6767
6768                 /* Get SSC going before enabling the outputs */
6769                 I915_WRITE(PCH_DREF_CONTROL, val);
6770                 POSTING_READ(PCH_DREF_CONTROL);
6771                 udelay(200);
6772
6773                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6774
6775                 /* Enable CPU source on CPU attached eDP */
6776                 if (has_cpu_edp) {
6777                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6778                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6779                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6780                         } else
6781                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6782                 } else
6783                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6784
6785                 I915_WRITE(PCH_DREF_CONTROL, val);
6786                 POSTING_READ(PCH_DREF_CONTROL);
6787                 udelay(200);
6788         } else {
6789                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6790
6791                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6792
6793                 /* Turn off CPU output */
6794                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6795
6796                 I915_WRITE(PCH_DREF_CONTROL, val);
6797                 POSTING_READ(PCH_DREF_CONTROL);
6798                 udelay(200);
6799
6800                 /* Turn off the SSC source */
6801                 val &= ~DREF_SSC_SOURCE_MASK;
6802                 val |= DREF_SSC_SOURCE_DISABLE;
6803
6804                 /* Turn off SSC1 */
6805                 val &= ~DREF_SSC1_ENABLE;
6806
6807                 I915_WRITE(PCH_DREF_CONTROL, val);
6808                 POSTING_READ(PCH_DREF_CONTROL);
6809                 udelay(200);
6810         }
6811
6812         BUG_ON(val != final);
6813 }
6814
6815 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6816 {
6817         uint32_t tmp;
6818
6819         tmp = I915_READ(SOUTH_CHICKEN2);
6820         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6821         I915_WRITE(SOUTH_CHICKEN2, tmp);
6822
6823         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6824                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6825                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6826
6827         tmp = I915_READ(SOUTH_CHICKEN2);
6828         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6829         I915_WRITE(SOUTH_CHICKEN2, tmp);
6830
6831         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6832                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6833                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6834 }
6835
6836 /* WaMPhyProgramming:hsw */
6837 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6838 {
6839         uint32_t tmp;
6840
6841         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6842         tmp &= ~(0xFF << 24);
6843         tmp |= (0x12 << 24);
6844         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6845
6846         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6847         tmp |= (1 << 11);
6848         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6849
6850         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6851         tmp |= (1 << 11);
6852         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6853
6854         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6855         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6856         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6857
6858         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6859         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6860         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6861
6862         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6863         tmp &= ~(7 << 13);
6864         tmp |= (5 << 13);
6865         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6866
6867         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6868         tmp &= ~(7 << 13);
6869         tmp |= (5 << 13);
6870         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6871
6872         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6873         tmp &= ~0xFF;
6874         tmp |= 0x1C;
6875         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6876
6877         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6878         tmp &= ~0xFF;
6879         tmp |= 0x1C;
6880         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6881
6882         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6883         tmp &= ~(0xFF << 16);
6884         tmp |= (0x1C << 16);
6885         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6886
6887         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6888         tmp &= ~(0xFF << 16);
6889         tmp |= (0x1C << 16);
6890         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6891
6892         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6893         tmp |= (1 << 27);
6894         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6895
6896         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6897         tmp |= (1 << 27);
6898         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6899
6900         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6901         tmp &= ~(0xF << 28);
6902         tmp |= (4 << 28);
6903         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6904
6905         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6906         tmp &= ~(0xF << 28);
6907         tmp |= (4 << 28);
6908         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6909 }
6910
6911 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6912  * Programming" based on the parameters passed:
6913  * - Sequence to enable CLKOUT_DP
6914  * - Sequence to enable CLKOUT_DP without spread
6915  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6916  */
6917 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6918                                  bool with_fdi)
6919 {
6920         struct drm_i915_private *dev_priv = dev->dev_private;
6921         uint32_t reg, tmp;
6922
6923         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6924                 with_spread = true;
6925         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6926                  with_fdi, "LP PCH doesn't have FDI\n"))
6927                 with_fdi = false;
6928
6929         mutex_lock(&dev_priv->dpio_lock);
6930
6931         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6932         tmp &= ~SBI_SSCCTL_DISABLE;
6933         tmp |= SBI_SSCCTL_PATHALT;
6934         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6935
6936         udelay(24);
6937
6938         if (with_spread) {
6939                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6940                 tmp &= ~SBI_SSCCTL_PATHALT;
6941                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6942
6943                 if (with_fdi) {
6944                         lpt_reset_fdi_mphy(dev_priv);
6945                         lpt_program_fdi_mphy(dev_priv);
6946                 }
6947         }
6948
6949         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6950                SBI_GEN0 : SBI_DBUFF0;
6951         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6952         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6953         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6954
6955         mutex_unlock(&dev_priv->dpio_lock);
6956 }
6957
6958 /* Sequence to disable CLKOUT_DP */
6959 static void lpt_disable_clkout_dp(struct drm_device *dev)
6960 {
6961         struct drm_i915_private *dev_priv = dev->dev_private;
6962         uint32_t reg, tmp;
6963
6964         mutex_lock(&dev_priv->dpio_lock);
6965
6966         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6967                SBI_GEN0 : SBI_DBUFF0;
6968         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6969         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6970         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6971
6972         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6973         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6974                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6975                         tmp |= SBI_SSCCTL_PATHALT;
6976                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6977                         udelay(32);
6978                 }
6979                 tmp |= SBI_SSCCTL_DISABLE;
6980                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6981         }
6982
6983         mutex_unlock(&dev_priv->dpio_lock);
6984 }
6985
6986 static void lpt_init_pch_refclk(struct drm_device *dev)
6987 {
6988         struct intel_encoder *encoder;
6989         bool has_vga = false;
6990
6991         for_each_intel_encoder(dev, encoder) {
6992                 switch (encoder->type) {
6993                 case INTEL_OUTPUT_ANALOG:
6994                         has_vga = true;
6995                         break;
6996                 default:
6997                         break;
6998                 }
6999         }
7000
7001         if (has_vga)
7002                 lpt_enable_clkout_dp(dev, true, true);
7003         else
7004                 lpt_disable_clkout_dp(dev);
7005 }
7006
7007 /*
7008  * Initialize reference clocks when the driver loads
7009  */
7010 void intel_init_pch_refclk(struct drm_device *dev)
7011 {
7012         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7013                 ironlake_init_pch_refclk(dev);
7014         else if (HAS_PCH_LPT(dev))
7015                 lpt_init_pch_refclk(dev);
7016 }
7017
7018 static int ironlake_get_refclk(struct drm_crtc *crtc)
7019 {
7020         struct drm_device *dev = crtc->dev;
7021         struct drm_i915_private *dev_priv = dev->dev_private;
7022         struct intel_encoder *encoder;
7023         int num_connectors = 0;
7024         bool is_lvds = false;
7025
7026         for_each_intel_encoder(dev, encoder) {
7027                 if (encoder->new_crtc != to_intel_crtc(crtc))
7028                         continue;
7029
7030                 switch (encoder->type) {
7031                 case INTEL_OUTPUT_LVDS:
7032                         is_lvds = true;
7033                         break;
7034                 default:
7035                         break;
7036                 }
7037                 num_connectors++;
7038         }
7039
7040         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7041                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7042                               dev_priv->vbt.lvds_ssc_freq);
7043                 return dev_priv->vbt.lvds_ssc_freq;
7044         }
7045
7046         return 120000;
7047 }
7048
7049 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7050 {
7051         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053         int pipe = intel_crtc->pipe;
7054         uint32_t val;
7055
7056         val = 0;
7057
7058         switch (intel_crtc->config.pipe_bpp) {
7059         case 18:
7060                 val |= PIPECONF_6BPC;
7061                 break;
7062         case 24:
7063                 val |= PIPECONF_8BPC;
7064                 break;
7065         case 30:
7066                 val |= PIPECONF_10BPC;
7067                 break;
7068         case 36:
7069                 val |= PIPECONF_12BPC;
7070                 break;
7071         default:
7072                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7073                 BUG();
7074         }
7075
7076         if (intel_crtc->config.dither)
7077                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7078
7079         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7080                 val |= PIPECONF_INTERLACED_ILK;
7081         else
7082                 val |= PIPECONF_PROGRESSIVE;
7083
7084         if (intel_crtc->config.limited_color_range)
7085                 val |= PIPECONF_COLOR_RANGE_SELECT;
7086
7087         I915_WRITE(PIPECONF(pipe), val);
7088         POSTING_READ(PIPECONF(pipe));
7089 }
7090
7091 /*
7092  * Set up the pipe CSC unit.
7093  *
7094  * Currently only full range RGB to limited range RGB conversion
7095  * is supported, but eventually this should handle various
7096  * RGB<->YCbCr scenarios as well.
7097  */
7098 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7099 {
7100         struct drm_device *dev = crtc->dev;
7101         struct drm_i915_private *dev_priv = dev->dev_private;
7102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7103         int pipe = intel_crtc->pipe;
7104         uint16_t coeff = 0x7800; /* 1.0 */
7105
7106         /*
7107          * TODO: Check what kind of values actually come out of the pipe
7108          * with these coeff/postoff values and adjust to get the best
7109          * accuracy. Perhaps we even need to take the bpc value into
7110          * consideration.
7111          */
7112
7113         if (intel_crtc->config.limited_color_range)
7114                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7115
7116         /*
7117          * GY/GU and RY/RU should be the other way around according
7118          * to BSpec, but reality doesn't agree. Just set them up in
7119          * a way that results in the correct picture.
7120          */
7121         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7122         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7123
7124         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7125         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7126
7127         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7128         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7129
7130         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7131         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7132         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7133
7134         if (INTEL_INFO(dev)->gen > 6) {
7135                 uint16_t postoff = 0;
7136
7137                 if (intel_crtc->config.limited_color_range)
7138                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7139
7140                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7141                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7142                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7143
7144                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7145         } else {
7146                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7147
7148                 if (intel_crtc->config.limited_color_range)
7149                         mode |= CSC_BLACK_SCREEN_OFFSET;
7150
7151                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7152         }
7153 }
7154
7155 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7156 {
7157         struct drm_device *dev = crtc->dev;
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7160         enum pipe pipe = intel_crtc->pipe;
7161         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7162         uint32_t val;
7163
7164         val = 0;
7165
7166         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7167                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7168
7169         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7170                 val |= PIPECONF_INTERLACED_ILK;
7171         else
7172                 val |= PIPECONF_PROGRESSIVE;
7173
7174         I915_WRITE(PIPECONF(cpu_transcoder), val);
7175         POSTING_READ(PIPECONF(cpu_transcoder));
7176
7177         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7178         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7179
7180         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7181                 val = 0;
7182
7183                 switch (intel_crtc->config.pipe_bpp) {
7184                 case 18:
7185                         val |= PIPEMISC_DITHER_6_BPC;
7186                         break;
7187                 case 24:
7188                         val |= PIPEMISC_DITHER_8_BPC;
7189                         break;
7190                 case 30:
7191                         val |= PIPEMISC_DITHER_10_BPC;
7192                         break;
7193                 case 36:
7194                         val |= PIPEMISC_DITHER_12_BPC;
7195                         break;
7196                 default:
7197                         /* Case prevented by pipe_config_set_bpp. */
7198                         BUG();
7199                 }
7200
7201                 if (intel_crtc->config.dither)
7202                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7203
7204                 I915_WRITE(PIPEMISC(pipe), val);
7205         }
7206 }
7207
7208 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7209                                     intel_clock_t *clock,
7210                                     bool *has_reduced_clock,
7211                                     intel_clock_t *reduced_clock)
7212 {
7213         struct drm_device *dev = crtc->dev;
7214         struct drm_i915_private *dev_priv = dev->dev_private;
7215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7216         int refclk;
7217         const intel_limit_t *limit;
7218         bool ret, is_lvds = false;
7219
7220         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7221
7222         refclk = ironlake_get_refclk(crtc);
7223
7224         /*
7225          * Returns a set of divisors for the desired target clock with the given
7226          * refclk, or FALSE.  The returned values represent the clock equation:
7227          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7228          */
7229         limit = intel_limit(intel_crtc, refclk);
7230         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7231                                           intel_crtc->new_config->port_clock,
7232                                           refclk, NULL, clock);
7233         if (!ret)
7234                 return false;
7235
7236         if (is_lvds && dev_priv->lvds_downclock_avail) {
7237                 /*
7238                  * Ensure we match the reduced clock's P to the target clock.
7239                  * If the clocks don't match, we can't switch the display clock
7240                  * by using the FP0/FP1. In such case we will disable the LVDS
7241                  * downclock feature.
7242                 */
7243                 *has_reduced_clock =
7244                         dev_priv->display.find_dpll(limit, intel_crtc,
7245                                                     dev_priv->lvds_downclock,
7246                                                     refclk, clock,
7247                                                     reduced_clock);
7248         }
7249
7250         return true;
7251 }
7252
7253 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7254 {
7255         /*
7256          * Account for spread spectrum to avoid
7257          * oversubscribing the link. Max center spread
7258          * is 2.5%; use 5% for safety's sake.
7259          */
7260         u32 bps = target_clock * bpp * 21 / 20;
7261         return DIV_ROUND_UP(bps, link_bw * 8);
7262 }
7263
7264 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7265 {
7266         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7267 }
7268
7269 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7270                                       u32 *fp,
7271                                       intel_clock_t *reduced_clock, u32 *fp2)
7272 {
7273         struct drm_crtc *crtc = &intel_crtc->base;
7274         struct drm_device *dev = crtc->dev;
7275         struct drm_i915_private *dev_priv = dev->dev_private;
7276         struct intel_encoder *intel_encoder;
7277         uint32_t dpll;
7278         int factor, num_connectors = 0;
7279         bool is_lvds = false, is_sdvo = false;
7280
7281         for_each_intel_encoder(dev, intel_encoder) {
7282                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7283                         continue;
7284
7285                 switch (intel_encoder->type) {
7286                 case INTEL_OUTPUT_LVDS:
7287                         is_lvds = true;
7288                         break;
7289                 case INTEL_OUTPUT_SDVO:
7290                 case INTEL_OUTPUT_HDMI:
7291                         is_sdvo = true;
7292                         break;
7293                 default:
7294                         break;
7295                 }
7296
7297                 num_connectors++;
7298         }
7299
7300         /* Enable autotuning of the PLL clock (if permissible) */
7301         factor = 21;
7302         if (is_lvds) {
7303                 if ((intel_panel_use_ssc(dev_priv) &&
7304                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7305                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7306                         factor = 25;
7307         } else if (intel_crtc->new_config->sdvo_tv_clock)
7308                 factor = 20;
7309
7310         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7311                 *fp |= FP_CB_TUNE;
7312
7313         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7314                 *fp2 |= FP_CB_TUNE;
7315
7316         dpll = 0;
7317
7318         if (is_lvds)
7319                 dpll |= DPLLB_MODE_LVDS;
7320         else
7321                 dpll |= DPLLB_MODE_DAC_SERIAL;
7322
7323         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7324                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7325
7326         if (is_sdvo)
7327                 dpll |= DPLL_SDVO_HIGH_SPEED;
7328         if (intel_crtc->new_config->has_dp_encoder)
7329                 dpll |= DPLL_SDVO_HIGH_SPEED;
7330
7331         /* compute bitmask from p1 value */
7332         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7333         /* also FPA1 */
7334         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7335
7336         switch (intel_crtc->new_config->dpll.p2) {
7337         case 5:
7338                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7339                 break;
7340         case 7:
7341                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7342                 break;
7343         case 10:
7344                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7345                 break;
7346         case 14:
7347                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7348                 break;
7349         }
7350
7351         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7352                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7353         else
7354                 dpll |= PLL_REF_INPUT_DREFCLK;
7355
7356         return dpll | DPLL_VCO_ENABLE;
7357 }
7358
7359 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7360                                   int x, int y,
7361                                   struct drm_framebuffer *fb)
7362 {
7363         struct drm_device *dev = crtc->base.dev;
7364         intel_clock_t clock, reduced_clock;
7365         u32 dpll = 0, fp = 0, fp2 = 0;
7366         bool ok, has_reduced_clock = false;
7367         bool is_lvds = false;
7368         struct intel_shared_dpll *pll;
7369
7370         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7371
7372         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7373              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7374
7375         ok = ironlake_compute_clocks(&crtc->base, &clock,
7376                                      &has_reduced_clock, &reduced_clock);
7377         if (!ok && !crtc->new_config->clock_set) {
7378                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7379                 return -EINVAL;
7380         }
7381         /* Compat-code for transition, will disappear. */
7382         if (!crtc->new_config->clock_set) {
7383                 crtc->new_config->dpll.n = clock.n;
7384                 crtc->new_config->dpll.m1 = clock.m1;
7385                 crtc->new_config->dpll.m2 = clock.m2;
7386                 crtc->new_config->dpll.p1 = clock.p1;
7387                 crtc->new_config->dpll.p2 = clock.p2;
7388         }
7389
7390         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7391         if (crtc->new_config->has_pch_encoder) {
7392                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7393                 if (has_reduced_clock)
7394                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7395
7396                 dpll = ironlake_compute_dpll(crtc,
7397                                              &fp, &reduced_clock,
7398                                              has_reduced_clock ? &fp2 : NULL);
7399
7400                 crtc->new_config->dpll_hw_state.dpll = dpll;
7401                 crtc->new_config->dpll_hw_state.fp0 = fp;
7402                 if (has_reduced_clock)
7403                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7404                 else
7405                         crtc->new_config->dpll_hw_state.fp1 = fp;
7406
7407                 pll = intel_get_shared_dpll(crtc);
7408                 if (pll == NULL) {
7409                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7410                                          pipe_name(crtc->pipe));
7411                         return -EINVAL;
7412                 }
7413         } else
7414                 intel_put_shared_dpll(crtc);
7415
7416         if (is_lvds && has_reduced_clock && i915.powersave)
7417                 crtc->lowfreq_avail = true;
7418         else
7419                 crtc->lowfreq_avail = false;
7420
7421         return 0;
7422 }
7423
7424 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7425                                          struct intel_link_m_n *m_n)
7426 {
7427         struct drm_device *dev = crtc->base.dev;
7428         struct drm_i915_private *dev_priv = dev->dev_private;
7429         enum pipe pipe = crtc->pipe;
7430
7431         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7432         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7433         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7434                 & ~TU_SIZE_MASK;
7435         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7436         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7437                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7438 }
7439
7440 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7441                                          enum transcoder transcoder,
7442                                          struct intel_link_m_n *m_n,
7443                                          struct intel_link_m_n *m2_n2)
7444 {
7445         struct drm_device *dev = crtc->base.dev;
7446         struct drm_i915_private *dev_priv = dev->dev_private;
7447         enum pipe pipe = crtc->pipe;
7448
7449         if (INTEL_INFO(dev)->gen >= 5) {
7450                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7451                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7452                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7453                         & ~TU_SIZE_MASK;
7454                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7455                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7456                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7457                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7458                  * gen < 8) and if DRRS is supported (to make sure the
7459                  * registers are not unnecessarily read).
7460                  */
7461                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7462                         crtc->config.has_drrs) {
7463                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7464                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7465                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7466                                         & ~TU_SIZE_MASK;
7467                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7468                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7469                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7470                 }
7471         } else {
7472                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7473                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7474                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7475                         & ~TU_SIZE_MASK;
7476                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7477                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7478                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7479         }
7480 }
7481
7482 void intel_dp_get_m_n(struct intel_crtc *crtc,
7483                       struct intel_crtc_config *pipe_config)
7484 {
7485         if (crtc->config.has_pch_encoder)
7486                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7487         else
7488                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7489                                              &pipe_config->dp_m_n,
7490                                              &pipe_config->dp_m2_n2);
7491 }
7492
7493 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7494                                         struct intel_crtc_config *pipe_config)
7495 {
7496         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7497                                      &pipe_config->fdi_m_n, NULL);
7498 }
7499
7500 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7501                                      struct intel_crtc_config *pipe_config)
7502 {
7503         struct drm_device *dev = crtc->base.dev;
7504         struct drm_i915_private *dev_priv = dev->dev_private;
7505         uint32_t tmp;
7506
7507         tmp = I915_READ(PF_CTL(crtc->pipe));
7508
7509         if (tmp & PF_ENABLE) {
7510                 pipe_config->pch_pfit.enabled = true;
7511                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7512                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7513
7514                 /* We currently do not free assignements of panel fitters on
7515                  * ivb/hsw (since we don't use the higher upscaling modes which
7516                  * differentiates them) so just WARN about this case for now. */
7517                 if (IS_GEN7(dev)) {
7518                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7519                                 PF_PIPE_SEL_IVB(crtc->pipe));
7520                 }
7521         }
7522 }
7523
7524 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7525                                       struct intel_plane_config *plane_config)
7526 {
7527         struct drm_device *dev = crtc->base.dev;
7528         struct drm_i915_private *dev_priv = dev->dev_private;
7529         u32 val, base, offset;
7530         int pipe = crtc->pipe, plane = crtc->plane;
7531         int fourcc, pixel_format;
7532         int aligned_height;
7533
7534         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7535         if (!crtc->base.primary->fb) {
7536                 DRM_DEBUG_KMS("failed to alloc fb\n");
7537                 return;
7538         }
7539
7540         val = I915_READ(DSPCNTR(plane));
7541
7542         if (INTEL_INFO(dev)->gen >= 4)
7543                 if (val & DISPPLANE_TILED)
7544                         plane_config->tiled = true;
7545
7546         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7547         fourcc = intel_format_to_fourcc(pixel_format);
7548         crtc->base.primary->fb->pixel_format = fourcc;
7549         crtc->base.primary->fb->bits_per_pixel =
7550                 drm_format_plane_cpp(fourcc, 0) * 8;
7551
7552         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7553         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7554                 offset = I915_READ(DSPOFFSET(plane));
7555         } else {
7556                 if (plane_config->tiled)
7557                         offset = I915_READ(DSPTILEOFF(plane));
7558                 else
7559                         offset = I915_READ(DSPLINOFF(plane));
7560         }
7561         plane_config->base = base;
7562
7563         val = I915_READ(PIPESRC(pipe));
7564         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7565         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7566
7567         val = I915_READ(DSPSTRIDE(pipe));
7568         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7569
7570         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7571                                             plane_config->tiled);
7572
7573         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7574                                         aligned_height);
7575
7576         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7577                       pipe, plane, crtc->base.primary->fb->width,
7578                       crtc->base.primary->fb->height,
7579                       crtc->base.primary->fb->bits_per_pixel, base,
7580                       crtc->base.primary->fb->pitches[0],
7581                       plane_config->size);
7582 }
7583
7584 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7585                                      struct intel_crtc_config *pipe_config)
7586 {
7587         struct drm_device *dev = crtc->base.dev;
7588         struct drm_i915_private *dev_priv = dev->dev_private;
7589         uint32_t tmp;
7590
7591         if (!intel_display_power_is_enabled(dev_priv,
7592                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7593                 return false;
7594
7595         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7596         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7597
7598         tmp = I915_READ(PIPECONF(crtc->pipe));
7599         if (!(tmp & PIPECONF_ENABLE))
7600                 return false;
7601
7602         switch (tmp & PIPECONF_BPC_MASK) {
7603         case PIPECONF_6BPC:
7604                 pipe_config->pipe_bpp = 18;
7605                 break;
7606         case PIPECONF_8BPC:
7607                 pipe_config->pipe_bpp = 24;
7608                 break;
7609         case PIPECONF_10BPC:
7610                 pipe_config->pipe_bpp = 30;
7611                 break;
7612         case PIPECONF_12BPC:
7613                 pipe_config->pipe_bpp = 36;
7614                 break;
7615         default:
7616                 break;
7617         }
7618
7619         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7620                 pipe_config->limited_color_range = true;
7621
7622         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7623                 struct intel_shared_dpll *pll;
7624
7625                 pipe_config->has_pch_encoder = true;
7626
7627                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7628                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7629                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7630
7631                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7632
7633                 if (HAS_PCH_IBX(dev_priv->dev)) {
7634                         pipe_config->shared_dpll =
7635                                 (enum intel_dpll_id) crtc->pipe;
7636                 } else {
7637                         tmp = I915_READ(PCH_DPLL_SEL);
7638                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7639                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7640                         else
7641                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7642                 }
7643
7644                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7645
7646                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7647                                            &pipe_config->dpll_hw_state));
7648
7649                 tmp = pipe_config->dpll_hw_state.dpll;
7650                 pipe_config->pixel_multiplier =
7651                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7652                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7653
7654                 ironlake_pch_clock_get(crtc, pipe_config);
7655         } else {
7656                 pipe_config->pixel_multiplier = 1;
7657         }
7658
7659         intel_get_pipe_timings(crtc, pipe_config);
7660
7661         ironlake_get_pfit_config(crtc, pipe_config);
7662
7663         return true;
7664 }
7665
7666 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7667 {
7668         struct drm_device *dev = dev_priv->dev;
7669         struct intel_crtc *crtc;
7670
7671         for_each_intel_crtc(dev, crtc)
7672                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7673                      pipe_name(crtc->pipe));
7674
7675         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7676         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7677         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7678         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7679         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7680         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7681              "CPU PWM1 enabled\n");
7682         if (IS_HASWELL(dev))
7683                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7684                      "CPU PWM2 enabled\n");
7685         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7686              "PCH PWM1 enabled\n");
7687         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7688              "Utility pin enabled\n");
7689         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7690
7691         /*
7692          * In theory we can still leave IRQs enabled, as long as only the HPD
7693          * interrupts remain enabled. We used to check for that, but since it's
7694          * gen-specific and since we only disable LCPLL after we fully disable
7695          * the interrupts, the check below should be enough.
7696          */
7697         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7698 }
7699
7700 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7701 {
7702         struct drm_device *dev = dev_priv->dev;
7703
7704         if (IS_HASWELL(dev))
7705                 return I915_READ(D_COMP_HSW);
7706         else
7707                 return I915_READ(D_COMP_BDW);
7708 }
7709
7710 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7711 {
7712         struct drm_device *dev = dev_priv->dev;
7713
7714         if (IS_HASWELL(dev)) {
7715                 mutex_lock(&dev_priv->rps.hw_lock);
7716                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7717                                             val))
7718                         DRM_ERROR("Failed to write to D_COMP\n");
7719                 mutex_unlock(&dev_priv->rps.hw_lock);
7720         } else {
7721                 I915_WRITE(D_COMP_BDW, val);
7722                 POSTING_READ(D_COMP_BDW);
7723         }
7724 }
7725
7726 /*
7727  * This function implements pieces of two sequences from BSpec:
7728  * - Sequence for display software to disable LCPLL
7729  * - Sequence for display software to allow package C8+
7730  * The steps implemented here are just the steps that actually touch the LCPLL
7731  * register. Callers should take care of disabling all the display engine
7732  * functions, doing the mode unset, fixing interrupts, etc.
7733  */
7734 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7735                               bool switch_to_fclk, bool allow_power_down)
7736 {
7737         uint32_t val;
7738
7739         assert_can_disable_lcpll(dev_priv);
7740
7741         val = I915_READ(LCPLL_CTL);
7742
7743         if (switch_to_fclk) {
7744                 val |= LCPLL_CD_SOURCE_FCLK;
7745                 I915_WRITE(LCPLL_CTL, val);
7746
7747                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7748                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7749                         DRM_ERROR("Switching to FCLK failed\n");
7750
7751                 val = I915_READ(LCPLL_CTL);
7752         }
7753
7754         val |= LCPLL_PLL_DISABLE;
7755         I915_WRITE(LCPLL_CTL, val);
7756         POSTING_READ(LCPLL_CTL);
7757
7758         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7759                 DRM_ERROR("LCPLL still locked\n");
7760
7761         val = hsw_read_dcomp(dev_priv);
7762         val |= D_COMP_COMP_DISABLE;
7763         hsw_write_dcomp(dev_priv, val);
7764         ndelay(100);
7765
7766         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7767                      1))
7768                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7769
7770         if (allow_power_down) {
7771                 val = I915_READ(LCPLL_CTL);
7772                 val |= LCPLL_POWER_DOWN_ALLOW;
7773                 I915_WRITE(LCPLL_CTL, val);
7774                 POSTING_READ(LCPLL_CTL);
7775         }
7776 }
7777
7778 /*
7779  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7780  * source.
7781  */
7782 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7783 {
7784         uint32_t val;
7785
7786         val = I915_READ(LCPLL_CTL);
7787
7788         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7789                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7790                 return;
7791
7792         /*
7793          * Make sure we're not on PC8 state before disabling PC8, otherwise
7794          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7795          *
7796          * The other problem is that hsw_restore_lcpll() is called as part of
7797          * the runtime PM resume sequence, so we can't just call
7798          * gen6_gt_force_wake_get() because that function calls
7799          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7800          * while we are on the resume sequence. So to solve this problem we have
7801          * to call special forcewake code that doesn't touch runtime PM and
7802          * doesn't enable the forcewake delayed work.
7803          */
7804         spin_lock_irq(&dev_priv->uncore.lock);
7805         if (dev_priv->uncore.forcewake_count++ == 0)
7806                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7807         spin_unlock_irq(&dev_priv->uncore.lock);
7808
7809         if (val & LCPLL_POWER_DOWN_ALLOW) {
7810                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7811                 I915_WRITE(LCPLL_CTL, val);
7812                 POSTING_READ(LCPLL_CTL);
7813         }
7814
7815         val = hsw_read_dcomp(dev_priv);
7816         val |= D_COMP_COMP_FORCE;
7817         val &= ~D_COMP_COMP_DISABLE;
7818         hsw_write_dcomp(dev_priv, val);
7819
7820         val = I915_READ(LCPLL_CTL);
7821         val &= ~LCPLL_PLL_DISABLE;
7822         I915_WRITE(LCPLL_CTL, val);
7823
7824         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7825                 DRM_ERROR("LCPLL not locked yet\n");
7826
7827         if (val & LCPLL_CD_SOURCE_FCLK) {
7828                 val = I915_READ(LCPLL_CTL);
7829                 val &= ~LCPLL_CD_SOURCE_FCLK;
7830                 I915_WRITE(LCPLL_CTL, val);
7831
7832                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7833                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7834                         DRM_ERROR("Switching back to LCPLL failed\n");
7835         }
7836
7837         /* See the big comment above. */
7838         spin_lock_irq(&dev_priv->uncore.lock);
7839         if (--dev_priv->uncore.forcewake_count == 0)
7840                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7841         spin_unlock_irq(&dev_priv->uncore.lock);
7842 }
7843
7844 /*
7845  * Package states C8 and deeper are really deep PC states that can only be
7846  * reached when all the devices on the system allow it, so even if the graphics
7847  * device allows PC8+, it doesn't mean the system will actually get to these
7848  * states. Our driver only allows PC8+ when going into runtime PM.
7849  *
7850  * The requirements for PC8+ are that all the outputs are disabled, the power
7851  * well is disabled and most interrupts are disabled, and these are also
7852  * requirements for runtime PM. When these conditions are met, we manually do
7853  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7854  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7855  * hang the machine.
7856  *
7857  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7858  * the state of some registers, so when we come back from PC8+ we need to
7859  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7860  * need to take care of the registers kept by RC6. Notice that this happens even
7861  * if we don't put the device in PCI D3 state (which is what currently happens
7862  * because of the runtime PM support).
7863  *
7864  * For more, read "Display Sequences for Package C8" on the hardware
7865  * documentation.
7866  */
7867 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7868 {
7869         struct drm_device *dev = dev_priv->dev;
7870         uint32_t val;
7871
7872         DRM_DEBUG_KMS("Enabling package C8+\n");
7873
7874         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7875                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7876                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7877                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7878         }
7879
7880         lpt_disable_clkout_dp(dev);
7881         hsw_disable_lcpll(dev_priv, true, true);
7882 }
7883
7884 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7885 {
7886         struct drm_device *dev = dev_priv->dev;
7887         uint32_t val;
7888
7889         DRM_DEBUG_KMS("Disabling package C8+\n");
7890
7891         hsw_restore_lcpll(dev_priv);
7892         lpt_init_pch_refclk(dev);
7893
7894         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7895                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7896                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7897                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7898         }
7899
7900         intel_prepare_ddi(dev);
7901 }
7902
7903 static void snb_modeset_global_resources(struct drm_device *dev)
7904 {
7905         modeset_update_crtc_power_domains(dev);
7906 }
7907
7908 static void haswell_modeset_global_resources(struct drm_device *dev)
7909 {
7910         modeset_update_crtc_power_domains(dev);
7911 }
7912
7913 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7914                                  int x, int y,
7915                                  struct drm_framebuffer *fb)
7916 {
7917         if (!intel_ddi_pll_select(crtc))
7918                 return -EINVAL;
7919
7920         crtc->lowfreq_avail = false;
7921
7922         return 0;
7923 }
7924
7925 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7926                                 enum port port,
7927                                 struct intel_crtc_config *pipe_config)
7928 {
7929         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7930
7931         switch (pipe_config->ddi_pll_sel) {
7932         case PORT_CLK_SEL_WRPLL1:
7933                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7934                 break;
7935         case PORT_CLK_SEL_WRPLL2:
7936                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7937                 break;
7938         }
7939 }
7940
7941 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7942                                        struct intel_crtc_config *pipe_config)
7943 {
7944         struct drm_device *dev = crtc->base.dev;
7945         struct drm_i915_private *dev_priv = dev->dev_private;
7946         struct intel_shared_dpll *pll;
7947         enum port port;
7948         uint32_t tmp;
7949
7950         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7951
7952         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7953
7954         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7955
7956         if (pipe_config->shared_dpll >= 0) {
7957                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7958
7959                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7960                                            &pipe_config->dpll_hw_state));
7961         }
7962
7963         /*
7964          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7965          * DDI E. So just check whether this pipe is wired to DDI E and whether
7966          * the PCH transcoder is on.
7967          */
7968         if (INTEL_INFO(dev)->gen < 9 &&
7969             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7970                 pipe_config->has_pch_encoder = true;
7971
7972                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7973                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7974                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7975
7976                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7977         }
7978 }
7979
7980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7981                                     struct intel_crtc_config *pipe_config)
7982 {
7983         struct drm_device *dev = crtc->base.dev;
7984         struct drm_i915_private *dev_priv = dev->dev_private;
7985         enum intel_display_power_domain pfit_domain;
7986         uint32_t tmp;
7987
7988         if (!intel_display_power_is_enabled(dev_priv,
7989                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7990                 return false;
7991
7992         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7993         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7994
7995         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7996         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7997                 enum pipe trans_edp_pipe;
7998                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7999                 default:
8000                         WARN(1, "unknown pipe linked to edp transcoder\n");
8001                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8002                 case TRANS_DDI_EDP_INPUT_A_ON:
8003                         trans_edp_pipe = PIPE_A;
8004                         break;
8005                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8006                         trans_edp_pipe = PIPE_B;
8007                         break;
8008                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8009                         trans_edp_pipe = PIPE_C;
8010                         break;
8011                 }
8012
8013                 if (trans_edp_pipe == crtc->pipe)
8014                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8015         }
8016
8017         if (!intel_display_power_is_enabled(dev_priv,
8018                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8019                 return false;
8020
8021         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8022         if (!(tmp & PIPECONF_ENABLE))
8023                 return false;
8024
8025         haswell_get_ddi_port_state(crtc, pipe_config);
8026
8027         intel_get_pipe_timings(crtc, pipe_config);
8028
8029         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8030         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8031                 ironlake_get_pfit_config(crtc, pipe_config);
8032
8033         if (IS_HASWELL(dev))
8034                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8035                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8036
8037         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8038                 pipe_config->pixel_multiplier =
8039                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8040         } else {
8041                 pipe_config->pixel_multiplier = 1;
8042         }
8043
8044         return true;
8045 }
8046
8047 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8048 {
8049         struct drm_device *dev = crtc->dev;
8050         struct drm_i915_private *dev_priv = dev->dev_private;
8051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8052         uint32_t cntl = 0, size = 0;
8053
8054         if (base) {
8055                 unsigned int width = intel_crtc->cursor_width;
8056                 unsigned int height = intel_crtc->cursor_height;
8057                 unsigned int stride = roundup_pow_of_two(width) * 4;
8058
8059                 switch (stride) {
8060                 default:
8061                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8062                                   width, stride);
8063                         stride = 256;
8064                         /* fallthrough */
8065                 case 256:
8066                 case 512:
8067                 case 1024:
8068                 case 2048:
8069                         break;
8070                 }
8071
8072                 cntl |= CURSOR_ENABLE |
8073                         CURSOR_GAMMA_ENABLE |
8074                         CURSOR_FORMAT_ARGB |
8075                         CURSOR_STRIDE(stride);
8076
8077                 size = (height << 12) | width;
8078         }
8079
8080         if (intel_crtc->cursor_cntl != 0 &&
8081             (intel_crtc->cursor_base != base ||
8082              intel_crtc->cursor_size != size ||
8083              intel_crtc->cursor_cntl != cntl)) {
8084                 /* On these chipsets we can only modify the base/size/stride
8085                  * whilst the cursor is disabled.
8086                  */
8087                 I915_WRITE(_CURACNTR, 0);
8088                 POSTING_READ(_CURACNTR);
8089                 intel_crtc->cursor_cntl = 0;
8090         }
8091
8092         if (intel_crtc->cursor_base != base) {
8093                 I915_WRITE(_CURABASE, base);
8094                 intel_crtc->cursor_base = base;
8095         }
8096
8097         if (intel_crtc->cursor_size != size) {
8098                 I915_WRITE(CURSIZE, size);
8099                 intel_crtc->cursor_size = size;
8100         }
8101
8102         if (intel_crtc->cursor_cntl != cntl) {
8103                 I915_WRITE(_CURACNTR, cntl);
8104                 POSTING_READ(_CURACNTR);
8105                 intel_crtc->cursor_cntl = cntl;
8106         }
8107 }
8108
8109 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8110 {
8111         struct drm_device *dev = crtc->dev;
8112         struct drm_i915_private *dev_priv = dev->dev_private;
8113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8114         int pipe = intel_crtc->pipe;
8115         uint32_t cntl;
8116
8117         cntl = 0;
8118         if (base) {
8119                 cntl = MCURSOR_GAMMA_ENABLE;
8120                 switch (intel_crtc->cursor_width) {
8121                         case 64:
8122                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8123                                 break;
8124                         case 128:
8125                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8126                                 break;
8127                         case 256:
8128                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8129                                 break;
8130                         default:
8131                                 WARN_ON(1);
8132                                 return;
8133                 }
8134                 cntl |= pipe << 28; /* Connect to correct pipe */
8135
8136                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8137                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8138         }
8139
8140         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8141                 cntl |= CURSOR_ROTATE_180;
8142
8143         if (intel_crtc->cursor_cntl != cntl) {
8144                 I915_WRITE(CURCNTR(pipe), cntl);
8145                 POSTING_READ(CURCNTR(pipe));
8146                 intel_crtc->cursor_cntl = cntl;
8147         }
8148
8149         /* and commit changes on next vblank */
8150         I915_WRITE(CURBASE(pipe), base);
8151         POSTING_READ(CURBASE(pipe));
8152
8153         intel_crtc->cursor_base = base;
8154 }
8155
8156 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8157 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8158                                      bool on)
8159 {
8160         struct drm_device *dev = crtc->dev;
8161         struct drm_i915_private *dev_priv = dev->dev_private;
8162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8163         int pipe = intel_crtc->pipe;
8164         int x = crtc->cursor_x;
8165         int y = crtc->cursor_y;
8166         u32 base = 0, pos = 0;
8167
8168         if (on)
8169                 base = intel_crtc->cursor_addr;
8170
8171         if (x >= intel_crtc->config.pipe_src_w)
8172                 base = 0;
8173
8174         if (y >= intel_crtc->config.pipe_src_h)
8175                 base = 0;
8176
8177         if (x < 0) {
8178                 if (x + intel_crtc->cursor_width <= 0)
8179                         base = 0;
8180
8181                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8182                 x = -x;
8183         }
8184         pos |= x << CURSOR_X_SHIFT;
8185
8186         if (y < 0) {
8187                 if (y + intel_crtc->cursor_height <= 0)
8188                         base = 0;
8189
8190                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8191                 y = -y;
8192         }
8193         pos |= y << CURSOR_Y_SHIFT;
8194
8195         if (base == 0 && intel_crtc->cursor_base == 0)
8196                 return;
8197
8198         I915_WRITE(CURPOS(pipe), pos);
8199
8200         /* ILK+ do this automagically */
8201         if (HAS_GMCH_DISPLAY(dev) &&
8202                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8203                 base += (intel_crtc->cursor_height *
8204                         intel_crtc->cursor_width - 1) * 4;
8205         }
8206
8207         if (IS_845G(dev) || IS_I865G(dev))
8208                 i845_update_cursor(crtc, base);
8209         else
8210                 i9xx_update_cursor(crtc, base);
8211 }
8212
8213 static bool cursor_size_ok(struct drm_device *dev,
8214                            uint32_t width, uint32_t height)
8215 {
8216         if (width == 0 || height == 0)
8217                 return false;
8218
8219         /*
8220          * 845g/865g are special in that they are only limited by
8221          * the width of their cursors, the height is arbitrary up to
8222          * the precision of the register. Everything else requires
8223          * square cursors, limited to a few power-of-two sizes.
8224          */
8225         if (IS_845G(dev) || IS_I865G(dev)) {
8226                 if ((width & 63) != 0)
8227                         return false;
8228
8229                 if (width > (IS_845G(dev) ? 64 : 512))
8230                         return false;
8231
8232                 if (height > 1023)
8233                         return false;
8234         } else {
8235                 switch (width | height) {
8236                 case 256:
8237                 case 128:
8238                         if (IS_GEN2(dev))
8239                                 return false;
8240                 case 64:
8241                         break;
8242                 default:
8243                         return false;
8244                 }
8245         }
8246
8247         return true;
8248 }
8249
8250 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8251                                      struct drm_i915_gem_object *obj,
8252                                      uint32_t width, uint32_t height)
8253 {
8254         struct drm_device *dev = crtc->dev;
8255         struct drm_i915_private *dev_priv = dev->dev_private;
8256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8257         enum pipe pipe = intel_crtc->pipe;
8258         unsigned old_width;
8259         uint32_t addr;
8260         int ret;
8261
8262         /* if we want to turn off the cursor ignore width and height */
8263         if (!obj) {
8264                 DRM_DEBUG_KMS("cursor off\n");
8265                 addr = 0;
8266                 mutex_lock(&dev->struct_mutex);
8267                 goto finish;
8268         }
8269
8270         /* we only need to pin inside GTT if cursor is non-phy */
8271         mutex_lock(&dev->struct_mutex);
8272         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8273                 unsigned alignment;
8274
8275                 /*
8276                  * Global gtt pte registers are special registers which actually
8277                  * forward writes to a chunk of system memory. Which means that
8278                  * there is no risk that the register values disappear as soon
8279                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8280                  * only the pin/unpin/fence and not more.
8281                  */
8282                 intel_runtime_pm_get(dev_priv);
8283
8284                 /* Note that the w/a also requires 2 PTE of padding following
8285                  * the bo. We currently fill all unused PTE with the shadow
8286                  * page and so we should always have valid PTE following the
8287                  * cursor preventing the VT-d warning.
8288                  */
8289                 alignment = 0;
8290                 if (need_vtd_wa(dev))
8291                         alignment = 64*1024;
8292
8293                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8294                 if (ret) {
8295                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8296                         intel_runtime_pm_put(dev_priv);
8297                         goto fail_locked;
8298                 }
8299
8300                 ret = i915_gem_object_put_fence(obj);
8301                 if (ret) {
8302                         DRM_DEBUG_KMS("failed to release fence for cursor");
8303                         intel_runtime_pm_put(dev_priv);
8304                         goto fail_unpin;
8305                 }
8306
8307                 addr = i915_gem_obj_ggtt_offset(obj);
8308
8309                 intel_runtime_pm_put(dev_priv);
8310         } else {
8311                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8312                 ret = i915_gem_object_attach_phys(obj, align);
8313                 if (ret) {
8314                         DRM_DEBUG_KMS("failed to attach phys object\n");
8315                         goto fail_locked;
8316                 }
8317                 addr = obj->phys_handle->busaddr;
8318         }
8319
8320  finish:
8321         if (intel_crtc->cursor_bo) {
8322                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8323                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8324         }
8325
8326         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8327                           INTEL_FRONTBUFFER_CURSOR(pipe));
8328         mutex_unlock(&dev->struct_mutex);
8329
8330         old_width = intel_crtc->cursor_width;
8331
8332         intel_crtc->cursor_addr = addr;
8333         intel_crtc->cursor_bo = obj;
8334         intel_crtc->cursor_width = width;
8335         intel_crtc->cursor_height = height;
8336
8337         if (intel_crtc->active) {
8338                 if (old_width != width)
8339                         intel_update_watermarks(crtc);
8340                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8341
8342                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8343         }
8344
8345         return 0;
8346 fail_unpin:
8347         i915_gem_object_unpin_from_display_plane(obj);
8348 fail_locked:
8349         mutex_unlock(&dev->struct_mutex);
8350         return ret;
8351 }
8352
8353 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8354                                  u16 *blue, uint32_t start, uint32_t size)
8355 {
8356         int end = (start + size > 256) ? 256 : start + size, i;
8357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8358
8359         for (i = start; i < end; i++) {
8360                 intel_crtc->lut_r[i] = red[i] >> 8;
8361                 intel_crtc->lut_g[i] = green[i] >> 8;
8362                 intel_crtc->lut_b[i] = blue[i] >> 8;
8363         }
8364
8365         intel_crtc_load_lut(crtc);
8366 }
8367
8368 /* VESA 640x480x72Hz mode to set on the pipe */
8369 static struct drm_display_mode load_detect_mode = {
8370         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8371                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8372 };
8373
8374 struct drm_framebuffer *
8375 __intel_framebuffer_create(struct drm_device *dev,
8376                            struct drm_mode_fb_cmd2 *mode_cmd,
8377                            struct drm_i915_gem_object *obj)
8378 {
8379         struct intel_framebuffer *intel_fb;
8380         int ret;
8381
8382         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8383         if (!intel_fb) {
8384                 drm_gem_object_unreference_unlocked(&obj->base);
8385                 return ERR_PTR(-ENOMEM);
8386         }
8387
8388         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8389         if (ret)
8390                 goto err;
8391
8392         return &intel_fb->base;
8393 err:
8394         drm_gem_object_unreference_unlocked(&obj->base);
8395         kfree(intel_fb);
8396
8397         return ERR_PTR(ret);
8398 }
8399
8400 static struct drm_framebuffer *
8401 intel_framebuffer_create(struct drm_device *dev,
8402                          struct drm_mode_fb_cmd2 *mode_cmd,
8403                          struct drm_i915_gem_object *obj)
8404 {
8405         struct drm_framebuffer *fb;
8406         int ret;
8407
8408         ret = i915_mutex_lock_interruptible(dev);
8409         if (ret)
8410                 return ERR_PTR(ret);
8411         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8412         mutex_unlock(&dev->struct_mutex);
8413
8414         return fb;
8415 }
8416
8417 static u32
8418 intel_framebuffer_pitch_for_width(int width, int bpp)
8419 {
8420         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8421         return ALIGN(pitch, 64);
8422 }
8423
8424 static u32
8425 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8426 {
8427         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8428         return PAGE_ALIGN(pitch * mode->vdisplay);
8429 }
8430
8431 static struct drm_framebuffer *
8432 intel_framebuffer_create_for_mode(struct drm_device *dev,
8433                                   struct drm_display_mode *mode,
8434                                   int depth, int bpp)
8435 {
8436         struct drm_i915_gem_object *obj;
8437         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8438
8439         obj = i915_gem_alloc_object(dev,
8440                                     intel_framebuffer_size_for_mode(mode, bpp));
8441         if (obj == NULL)
8442                 return ERR_PTR(-ENOMEM);
8443
8444         mode_cmd.width = mode->hdisplay;
8445         mode_cmd.height = mode->vdisplay;
8446         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8447                                                                 bpp);
8448         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8449
8450         return intel_framebuffer_create(dev, &mode_cmd, obj);
8451 }
8452
8453 static struct drm_framebuffer *
8454 mode_fits_in_fbdev(struct drm_device *dev,
8455                    struct drm_display_mode *mode)
8456 {
8457 #ifdef CONFIG_DRM_I915_FBDEV
8458         struct drm_i915_private *dev_priv = dev->dev_private;
8459         struct drm_i915_gem_object *obj;
8460         struct drm_framebuffer *fb;
8461
8462         if (!dev_priv->fbdev)
8463                 return NULL;
8464
8465         if (!dev_priv->fbdev->fb)
8466                 return NULL;
8467
8468         obj = dev_priv->fbdev->fb->obj;
8469         BUG_ON(!obj);
8470
8471         fb = &dev_priv->fbdev->fb->base;
8472         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8473                                                                fb->bits_per_pixel))
8474                 return NULL;
8475
8476         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8477                 return NULL;
8478
8479         return fb;
8480 #else
8481         return NULL;
8482 #endif
8483 }
8484
8485 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8486                                 struct drm_display_mode *mode,
8487                                 struct intel_load_detect_pipe *old,
8488                                 struct drm_modeset_acquire_ctx *ctx)
8489 {
8490         struct intel_crtc *intel_crtc;
8491         struct intel_encoder *intel_encoder =
8492                 intel_attached_encoder(connector);
8493         struct drm_crtc *possible_crtc;
8494         struct drm_encoder *encoder = &intel_encoder->base;
8495         struct drm_crtc *crtc = NULL;
8496         struct drm_device *dev = encoder->dev;
8497         struct drm_framebuffer *fb;
8498         struct drm_mode_config *config = &dev->mode_config;
8499         int ret, i = -1;
8500
8501         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8502                       connector->base.id, connector->name,
8503                       encoder->base.id, encoder->name);
8504
8505 retry:
8506         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8507         if (ret)
8508                 goto fail_unlock;
8509
8510         /*
8511          * Algorithm gets a little messy:
8512          *
8513          *   - if the connector already has an assigned crtc, use it (but make
8514          *     sure it's on first)
8515          *
8516          *   - try to find the first unused crtc that can drive this connector,
8517          *     and use that if we find one
8518          */
8519
8520         /* See if we already have a CRTC for this connector */
8521         if (encoder->crtc) {
8522                 crtc = encoder->crtc;
8523
8524                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8525                 if (ret)
8526                         goto fail_unlock;
8527
8528                 old->dpms_mode = connector->dpms;
8529                 old->load_detect_temp = false;
8530
8531                 /* Make sure the crtc and connector are running */
8532                 if (connector->dpms != DRM_MODE_DPMS_ON)
8533                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8534
8535                 return true;
8536         }
8537
8538         /* Find an unused one (if possible) */
8539         for_each_crtc(dev, possible_crtc) {
8540                 i++;
8541                 if (!(encoder->possible_crtcs & (1 << i)))
8542                         continue;
8543                 if (possible_crtc->enabled)
8544                         continue;
8545                 /* This can occur when applying the pipe A quirk on resume. */
8546                 if (to_intel_crtc(possible_crtc)->new_enabled)
8547                         continue;
8548
8549                 crtc = possible_crtc;
8550                 break;
8551         }
8552
8553         /*
8554          * If we didn't find an unused CRTC, don't use any.
8555          */
8556         if (!crtc) {
8557                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8558                 goto fail_unlock;
8559         }
8560
8561         ret = drm_modeset_lock(&crtc->mutex, ctx);
8562         if (ret)
8563                 goto fail_unlock;
8564         intel_encoder->new_crtc = to_intel_crtc(crtc);
8565         to_intel_connector(connector)->new_encoder = intel_encoder;
8566
8567         intel_crtc = to_intel_crtc(crtc);
8568         intel_crtc->new_enabled = true;
8569         intel_crtc->new_config = &intel_crtc->config;
8570         old->dpms_mode = connector->dpms;
8571         old->load_detect_temp = true;
8572         old->release_fb = NULL;
8573
8574         if (!mode)
8575                 mode = &load_detect_mode;
8576
8577         /* We need a framebuffer large enough to accommodate all accesses
8578          * that the plane may generate whilst we perform load detection.
8579          * We can not rely on the fbcon either being present (we get called
8580          * during its initialisation to detect all boot displays, or it may
8581          * not even exist) or that it is large enough to satisfy the
8582          * requested mode.
8583          */
8584         fb = mode_fits_in_fbdev(dev, mode);
8585         if (fb == NULL) {
8586                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8587                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8588                 old->release_fb = fb;
8589         } else
8590                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8591         if (IS_ERR(fb)) {
8592                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8593                 goto fail;
8594         }
8595
8596         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8597                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8598                 if (old->release_fb)
8599                         old->release_fb->funcs->destroy(old->release_fb);
8600                 goto fail;
8601         }
8602
8603         /* let the connector get through one full cycle before testing */
8604         intel_wait_for_vblank(dev, intel_crtc->pipe);
8605         return true;
8606
8607  fail:
8608         intel_crtc->new_enabled = crtc->enabled;
8609         if (intel_crtc->new_enabled)
8610                 intel_crtc->new_config = &intel_crtc->config;
8611         else
8612                 intel_crtc->new_config = NULL;
8613 fail_unlock:
8614         if (ret == -EDEADLK) {
8615                 drm_modeset_backoff(ctx);
8616                 goto retry;
8617         }
8618
8619         return false;
8620 }
8621
8622 void intel_release_load_detect_pipe(struct drm_connector *connector,
8623                                     struct intel_load_detect_pipe *old)
8624 {
8625         struct intel_encoder *intel_encoder =
8626                 intel_attached_encoder(connector);
8627         struct drm_encoder *encoder = &intel_encoder->base;
8628         struct drm_crtc *crtc = encoder->crtc;
8629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8630
8631         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8632                       connector->base.id, connector->name,
8633                       encoder->base.id, encoder->name);
8634
8635         if (old->load_detect_temp) {
8636                 to_intel_connector(connector)->new_encoder = NULL;
8637                 intel_encoder->new_crtc = NULL;
8638                 intel_crtc->new_enabled = false;
8639                 intel_crtc->new_config = NULL;
8640                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8641
8642                 if (old->release_fb) {
8643                         drm_framebuffer_unregister_private(old->release_fb);
8644                         drm_framebuffer_unreference(old->release_fb);
8645                 }
8646
8647                 return;
8648         }
8649
8650         /* Switch crtc and encoder back off if necessary */
8651         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8652                 connector->funcs->dpms(connector, old->dpms_mode);
8653 }
8654
8655 static int i9xx_pll_refclk(struct drm_device *dev,
8656                            const struct intel_crtc_config *pipe_config)
8657 {
8658         struct drm_i915_private *dev_priv = dev->dev_private;
8659         u32 dpll = pipe_config->dpll_hw_state.dpll;
8660
8661         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8662                 return dev_priv->vbt.lvds_ssc_freq;
8663         else if (HAS_PCH_SPLIT(dev))
8664                 return 120000;
8665         else if (!IS_GEN2(dev))
8666                 return 96000;
8667         else
8668                 return 48000;
8669 }
8670
8671 /* Returns the clock of the currently programmed mode of the given pipe. */
8672 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8673                                 struct intel_crtc_config *pipe_config)
8674 {
8675         struct drm_device *dev = crtc->base.dev;
8676         struct drm_i915_private *dev_priv = dev->dev_private;
8677         int pipe = pipe_config->cpu_transcoder;
8678         u32 dpll = pipe_config->dpll_hw_state.dpll;
8679         u32 fp;
8680         intel_clock_t clock;
8681         int refclk = i9xx_pll_refclk(dev, pipe_config);
8682
8683         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8684                 fp = pipe_config->dpll_hw_state.fp0;
8685         else
8686                 fp = pipe_config->dpll_hw_state.fp1;
8687
8688         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8689         if (IS_PINEVIEW(dev)) {
8690                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8691                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8692         } else {
8693                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8694                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8695         }
8696
8697         if (!IS_GEN2(dev)) {
8698                 if (IS_PINEVIEW(dev))
8699                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8700                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8701                 else
8702                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8703                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8704
8705                 switch (dpll & DPLL_MODE_MASK) {
8706                 case DPLLB_MODE_DAC_SERIAL:
8707                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8708                                 5 : 10;
8709                         break;
8710                 case DPLLB_MODE_LVDS:
8711                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8712                                 7 : 14;
8713                         break;
8714                 default:
8715                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8716                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8717                         return;
8718                 }
8719
8720                 if (IS_PINEVIEW(dev))
8721                         pineview_clock(refclk, &clock);
8722                 else
8723                         i9xx_clock(refclk, &clock);
8724         } else {
8725                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8726                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8727
8728                 if (is_lvds) {
8729                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8730                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8731
8732                         if (lvds & LVDS_CLKB_POWER_UP)
8733                                 clock.p2 = 7;
8734                         else
8735                                 clock.p2 = 14;
8736                 } else {
8737                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8738                                 clock.p1 = 2;
8739                         else {
8740                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8741                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8742                         }
8743                         if (dpll & PLL_P2_DIVIDE_BY_4)
8744                                 clock.p2 = 4;
8745                         else
8746                                 clock.p2 = 2;
8747                 }
8748
8749                 i9xx_clock(refclk, &clock);
8750         }
8751
8752         /*
8753          * This value includes pixel_multiplier. We will use
8754          * port_clock to compute adjusted_mode.crtc_clock in the
8755          * encoder's get_config() function.
8756          */
8757         pipe_config->port_clock = clock.dot;
8758 }
8759
8760 int intel_dotclock_calculate(int link_freq,
8761                              const struct intel_link_m_n *m_n)
8762 {
8763         /*
8764          * The calculation for the data clock is:
8765          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8766          * But we want to avoid losing precison if possible, so:
8767          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8768          *
8769          * and the link clock is simpler:
8770          * link_clock = (m * link_clock) / n
8771          */
8772
8773         if (!m_n->link_n)
8774                 return 0;
8775
8776         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8777 }
8778
8779 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8780                                    struct intel_crtc_config *pipe_config)
8781 {
8782         struct drm_device *dev = crtc->base.dev;
8783
8784         /* read out port_clock from the DPLL */
8785         i9xx_crtc_clock_get(crtc, pipe_config);
8786
8787         /*
8788          * This value does not include pixel_multiplier.
8789          * We will check that port_clock and adjusted_mode.crtc_clock
8790          * agree once we know their relationship in the encoder's
8791          * get_config() function.
8792          */
8793         pipe_config->adjusted_mode.crtc_clock =
8794                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8795                                          &pipe_config->fdi_m_n);
8796 }
8797
8798 /** Returns the currently programmed mode of the given pipe. */
8799 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8800                                              struct drm_crtc *crtc)
8801 {
8802         struct drm_i915_private *dev_priv = dev->dev_private;
8803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8804         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8805         struct drm_display_mode *mode;
8806         struct intel_crtc_config pipe_config;
8807         int htot = I915_READ(HTOTAL(cpu_transcoder));
8808         int hsync = I915_READ(HSYNC(cpu_transcoder));
8809         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8810         int vsync = I915_READ(VSYNC(cpu_transcoder));
8811         enum pipe pipe = intel_crtc->pipe;
8812
8813         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8814         if (!mode)
8815                 return NULL;
8816
8817         /*
8818          * Construct a pipe_config sufficient for getting the clock info
8819          * back out of crtc_clock_get.
8820          *
8821          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8822          * to use a real value here instead.
8823          */
8824         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8825         pipe_config.pixel_multiplier = 1;
8826         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8827         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8828         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8829         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8830
8831         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8832         mode->hdisplay = (htot & 0xffff) + 1;
8833         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8834         mode->hsync_start = (hsync & 0xffff) + 1;
8835         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8836         mode->vdisplay = (vtot & 0xffff) + 1;
8837         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8838         mode->vsync_start = (vsync & 0xffff) + 1;
8839         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8840
8841         drm_mode_set_name(mode);
8842
8843         return mode;
8844 }
8845
8846 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8847 {
8848         struct drm_device *dev = crtc->dev;
8849         struct drm_i915_private *dev_priv = dev->dev_private;
8850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8851
8852         if (!HAS_GMCH_DISPLAY(dev))
8853                 return;
8854
8855         if (!dev_priv->lvds_downclock_avail)
8856                 return;
8857
8858         /*
8859          * Since this is called by a timer, we should never get here in
8860          * the manual case.
8861          */
8862         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8863                 int pipe = intel_crtc->pipe;
8864                 int dpll_reg = DPLL(pipe);
8865                 int dpll;
8866
8867                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8868
8869                 assert_panel_unlocked(dev_priv, pipe);
8870
8871                 dpll = I915_READ(dpll_reg);
8872                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8873                 I915_WRITE(dpll_reg, dpll);
8874                 intel_wait_for_vblank(dev, pipe);
8875                 dpll = I915_READ(dpll_reg);
8876                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8877                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8878         }
8879
8880 }
8881
8882 void intel_mark_busy(struct drm_device *dev)
8883 {
8884         struct drm_i915_private *dev_priv = dev->dev_private;
8885
8886         if (dev_priv->mm.busy)
8887                 return;
8888
8889         intel_runtime_pm_get(dev_priv);
8890         i915_update_gfx_val(dev_priv);
8891         dev_priv->mm.busy = true;
8892 }
8893
8894 void intel_mark_idle(struct drm_device *dev)
8895 {
8896         struct drm_i915_private *dev_priv = dev->dev_private;
8897         struct drm_crtc *crtc;
8898
8899         if (!dev_priv->mm.busy)
8900                 return;
8901
8902         dev_priv->mm.busy = false;
8903
8904         if (!i915.powersave)
8905                 goto out;
8906
8907         for_each_crtc(dev, crtc) {
8908                 if (!crtc->primary->fb)
8909                         continue;
8910
8911                 intel_decrease_pllclock(crtc);
8912         }
8913
8914         if (INTEL_INFO(dev)->gen >= 6)
8915                 gen6_rps_idle(dev->dev_private);
8916
8917 out:
8918         intel_runtime_pm_put(dev_priv);
8919 }
8920
8921 static void intel_crtc_destroy(struct drm_crtc *crtc)
8922 {
8923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8924         struct drm_device *dev = crtc->dev;
8925         struct intel_unpin_work *work;
8926
8927         spin_lock_irq(&dev->event_lock);
8928         work = intel_crtc->unpin_work;
8929         intel_crtc->unpin_work = NULL;
8930         spin_unlock_irq(&dev->event_lock);
8931
8932         if (work) {
8933                 cancel_work_sync(&work->work);
8934                 kfree(work);
8935         }
8936
8937         drm_crtc_cleanup(crtc);
8938
8939         kfree(intel_crtc);
8940 }
8941
8942 static void intel_unpin_work_fn(struct work_struct *__work)
8943 {
8944         struct intel_unpin_work *work =
8945                 container_of(__work, struct intel_unpin_work, work);
8946         struct drm_device *dev = work->crtc->dev;
8947         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8948
8949         mutex_lock(&dev->struct_mutex);
8950         intel_unpin_fb_obj(work->old_fb_obj);
8951         drm_gem_object_unreference(&work->pending_flip_obj->base);
8952         drm_gem_object_unreference(&work->old_fb_obj->base);
8953
8954         intel_update_fbc(dev);
8955         mutex_unlock(&dev->struct_mutex);
8956
8957         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8958
8959         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8960         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8961
8962         kfree(work);
8963 }
8964
8965 static void do_intel_finish_page_flip(struct drm_device *dev,
8966                                       struct drm_crtc *crtc)
8967 {
8968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8969         struct intel_unpin_work *work;
8970         unsigned long flags;
8971
8972         /* Ignore early vblank irqs */
8973         if (intel_crtc == NULL)
8974                 return;
8975
8976         /*
8977          * This is called both by irq handlers and the reset code (to complete
8978          * lost pageflips) so needs the full irqsave spinlocks.
8979          */
8980         spin_lock_irqsave(&dev->event_lock, flags);
8981         work = intel_crtc->unpin_work;
8982
8983         /* Ensure we don't miss a work->pending update ... */
8984         smp_rmb();
8985
8986         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8987                 spin_unlock_irqrestore(&dev->event_lock, flags);
8988                 return;
8989         }
8990
8991         page_flip_completed(intel_crtc);
8992
8993         spin_unlock_irqrestore(&dev->event_lock, flags);
8994 }
8995
8996 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8997 {
8998         struct drm_i915_private *dev_priv = dev->dev_private;
8999         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9000
9001         do_intel_finish_page_flip(dev, crtc);
9002 }
9003
9004 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9005 {
9006         struct drm_i915_private *dev_priv = dev->dev_private;
9007         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9008
9009         do_intel_finish_page_flip(dev, crtc);
9010 }
9011
9012 /* Is 'a' after or equal to 'b'? */
9013 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9014 {
9015         return !((a - b) & 0x80000000);
9016 }
9017
9018 static bool page_flip_finished(struct intel_crtc *crtc)
9019 {
9020         struct drm_device *dev = crtc->base.dev;
9021         struct drm_i915_private *dev_priv = dev->dev_private;
9022
9023         /*
9024          * The relevant registers doen't exist on pre-ctg.
9025          * As the flip done interrupt doesn't trigger for mmio
9026          * flips on gmch platforms, a flip count check isn't
9027          * really needed there. But since ctg has the registers,
9028          * include it in the check anyway.
9029          */
9030         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9031                 return true;
9032
9033         /*
9034          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9035          * used the same base address. In that case the mmio flip might
9036          * have completed, but the CS hasn't even executed the flip yet.
9037          *
9038          * A flip count check isn't enough as the CS might have updated
9039          * the base address just after start of vblank, but before we
9040          * managed to process the interrupt. This means we'd complete the
9041          * CS flip too soon.
9042          *
9043          * Combining both checks should get us a good enough result. It may
9044          * still happen that the CS flip has been executed, but has not
9045          * yet actually completed. But in case the base address is the same
9046          * anyway, we don't really care.
9047          */
9048         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9049                 crtc->unpin_work->gtt_offset &&
9050                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9051                                     crtc->unpin_work->flip_count);
9052 }
9053
9054 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9055 {
9056         struct drm_i915_private *dev_priv = dev->dev_private;
9057         struct intel_crtc *intel_crtc =
9058                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9059         unsigned long flags;
9060
9061
9062         /*
9063          * This is called both by irq handlers and the reset code (to complete
9064          * lost pageflips) so needs the full irqsave spinlocks.
9065          *
9066          * NB: An MMIO update of the plane base pointer will also
9067          * generate a page-flip completion irq, i.e. every modeset
9068          * is also accompanied by a spurious intel_prepare_page_flip().
9069          */
9070         spin_lock_irqsave(&dev->event_lock, flags);
9071         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9072                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9073         spin_unlock_irqrestore(&dev->event_lock, flags);
9074 }
9075
9076 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9077 {
9078         /* Ensure that the work item is consistent when activating it ... */
9079         smp_wmb();
9080         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9081         /* and that it is marked active as soon as the irq could fire. */
9082         smp_wmb();
9083 }
9084
9085 static int intel_gen2_queue_flip(struct drm_device *dev,
9086                                  struct drm_crtc *crtc,
9087                                  struct drm_framebuffer *fb,
9088                                  struct drm_i915_gem_object *obj,
9089                                  struct intel_engine_cs *ring,
9090                                  uint32_t flags)
9091 {
9092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9093         u32 flip_mask;
9094         int ret;
9095
9096         ret = intel_ring_begin(ring, 6);
9097         if (ret)
9098                 return ret;
9099
9100         /* Can't queue multiple flips, so wait for the previous
9101          * one to finish before executing the next.
9102          */
9103         if (intel_crtc->plane)
9104                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9105         else
9106                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9107         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9108         intel_ring_emit(ring, MI_NOOP);
9109         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9110                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9111         intel_ring_emit(ring, fb->pitches[0]);
9112         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9113         intel_ring_emit(ring, 0); /* aux display base address, unused */
9114
9115         intel_mark_page_flip_active(intel_crtc);
9116         __intel_ring_advance(ring);
9117         return 0;
9118 }
9119
9120 static int intel_gen3_queue_flip(struct drm_device *dev,
9121                                  struct drm_crtc *crtc,
9122                                  struct drm_framebuffer *fb,
9123                                  struct drm_i915_gem_object *obj,
9124                                  struct intel_engine_cs *ring,
9125                                  uint32_t flags)
9126 {
9127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9128         u32 flip_mask;
9129         int ret;
9130
9131         ret = intel_ring_begin(ring, 6);
9132         if (ret)
9133                 return ret;
9134
9135         if (intel_crtc->plane)
9136                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9137         else
9138                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9139         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9140         intel_ring_emit(ring, MI_NOOP);
9141         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9142                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9143         intel_ring_emit(ring, fb->pitches[0]);
9144         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9145         intel_ring_emit(ring, MI_NOOP);
9146
9147         intel_mark_page_flip_active(intel_crtc);
9148         __intel_ring_advance(ring);
9149         return 0;
9150 }
9151
9152 static int intel_gen4_queue_flip(struct drm_device *dev,
9153                                  struct drm_crtc *crtc,
9154                                  struct drm_framebuffer *fb,
9155                                  struct drm_i915_gem_object *obj,
9156                                  struct intel_engine_cs *ring,
9157                                  uint32_t flags)
9158 {
9159         struct drm_i915_private *dev_priv = dev->dev_private;
9160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9161         uint32_t pf, pipesrc;
9162         int ret;
9163
9164         ret = intel_ring_begin(ring, 4);
9165         if (ret)
9166                 return ret;
9167
9168         /* i965+ uses the linear or tiled offsets from the
9169          * Display Registers (which do not change across a page-flip)
9170          * so we need only reprogram the base address.
9171          */
9172         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9173                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9174         intel_ring_emit(ring, fb->pitches[0]);
9175         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9176                         obj->tiling_mode);
9177
9178         /* XXX Enabling the panel-fitter across page-flip is so far
9179          * untested on non-native modes, so ignore it for now.
9180          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9181          */
9182         pf = 0;
9183         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9184         intel_ring_emit(ring, pf | pipesrc);
9185
9186         intel_mark_page_flip_active(intel_crtc);
9187         __intel_ring_advance(ring);
9188         return 0;
9189 }
9190
9191 static int intel_gen6_queue_flip(struct drm_device *dev,
9192                                  struct drm_crtc *crtc,
9193                                  struct drm_framebuffer *fb,
9194                                  struct drm_i915_gem_object *obj,
9195                                  struct intel_engine_cs *ring,
9196                                  uint32_t flags)
9197 {
9198         struct drm_i915_private *dev_priv = dev->dev_private;
9199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9200         uint32_t pf, pipesrc;
9201         int ret;
9202
9203         ret = intel_ring_begin(ring, 4);
9204         if (ret)
9205                 return ret;
9206
9207         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9208                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9209         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9210         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9211
9212         /* Contrary to the suggestions in the documentation,
9213          * "Enable Panel Fitter" does not seem to be required when page
9214          * flipping with a non-native mode, and worse causes a normal
9215          * modeset to fail.
9216          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9217          */
9218         pf = 0;
9219         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9220         intel_ring_emit(ring, pf | pipesrc);
9221
9222         intel_mark_page_flip_active(intel_crtc);
9223         __intel_ring_advance(ring);
9224         return 0;
9225 }
9226
9227 static int intel_gen7_queue_flip(struct drm_device *dev,
9228                                  struct drm_crtc *crtc,
9229                                  struct drm_framebuffer *fb,
9230                                  struct drm_i915_gem_object *obj,
9231                                  struct intel_engine_cs *ring,
9232                                  uint32_t flags)
9233 {
9234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9235         uint32_t plane_bit = 0;
9236         int len, ret;
9237
9238         switch (intel_crtc->plane) {
9239         case PLANE_A:
9240                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9241                 break;
9242         case PLANE_B:
9243                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9244                 break;
9245         case PLANE_C:
9246                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9247                 break;
9248         default:
9249                 WARN_ONCE(1, "unknown plane in flip command\n");
9250                 return -ENODEV;
9251         }
9252
9253         len = 4;
9254         if (ring->id == RCS) {
9255                 len += 6;
9256                 /*
9257                  * On Gen 8, SRM is now taking an extra dword to accommodate
9258                  * 48bits addresses, and we need a NOOP for the batch size to
9259                  * stay even.
9260                  */
9261                 if (IS_GEN8(dev))
9262                         len += 2;
9263         }
9264
9265         /*
9266          * BSpec MI_DISPLAY_FLIP for IVB:
9267          * "The full packet must be contained within the same cache line."
9268          *
9269          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9270          * cacheline, if we ever start emitting more commands before
9271          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9272          * then do the cacheline alignment, and finally emit the
9273          * MI_DISPLAY_FLIP.
9274          */
9275         ret = intel_ring_cacheline_align(ring);
9276         if (ret)
9277                 return ret;
9278
9279         ret = intel_ring_begin(ring, len);
9280         if (ret)
9281                 return ret;
9282
9283         /* Unmask the flip-done completion message. Note that the bspec says that
9284          * we should do this for both the BCS and RCS, and that we must not unmask
9285          * more than one flip event at any time (or ensure that one flip message
9286          * can be sent by waiting for flip-done prior to queueing new flips).
9287          * Experimentation says that BCS works despite DERRMR masking all
9288          * flip-done completion events and that unmasking all planes at once
9289          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9290          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9291          */
9292         if (ring->id == RCS) {
9293                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9294                 intel_ring_emit(ring, DERRMR);
9295                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9296                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9297                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9298                 if (IS_GEN8(dev))
9299                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9300                                               MI_SRM_LRM_GLOBAL_GTT);
9301                 else
9302                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9303                                               MI_SRM_LRM_GLOBAL_GTT);
9304                 intel_ring_emit(ring, DERRMR);
9305                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9306                 if (IS_GEN8(dev)) {
9307                         intel_ring_emit(ring, 0);
9308                         intel_ring_emit(ring, MI_NOOP);
9309                 }
9310         }
9311
9312         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9313         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9314         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9315         intel_ring_emit(ring, (MI_NOOP));
9316
9317         intel_mark_page_flip_active(intel_crtc);
9318         __intel_ring_advance(ring);
9319         return 0;
9320 }
9321
9322 static bool use_mmio_flip(struct intel_engine_cs *ring,
9323                           struct drm_i915_gem_object *obj)
9324 {
9325         /*
9326          * This is not being used for older platforms, because
9327          * non-availability of flip done interrupt forces us to use
9328          * CS flips. Older platforms derive flip done using some clever
9329          * tricks involving the flip_pending status bits and vblank irqs.
9330          * So using MMIO flips there would disrupt this mechanism.
9331          */
9332
9333         if (ring == NULL)
9334                 return true;
9335
9336         if (INTEL_INFO(ring->dev)->gen < 5)
9337                 return false;
9338
9339         if (i915.use_mmio_flip < 0)
9340                 return false;
9341         else if (i915.use_mmio_flip > 0)
9342                 return true;
9343         else if (i915.enable_execlists)
9344                 return true;
9345         else
9346                 return ring != obj->ring;
9347 }
9348
9349 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9350 {
9351         struct drm_device *dev = intel_crtc->base.dev;
9352         struct drm_i915_private *dev_priv = dev->dev_private;
9353         struct intel_framebuffer *intel_fb =
9354                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9355         struct drm_i915_gem_object *obj = intel_fb->obj;
9356         u32 dspcntr;
9357         u32 reg;
9358
9359         intel_mark_page_flip_active(intel_crtc);
9360
9361         reg = DSPCNTR(intel_crtc->plane);
9362         dspcntr = I915_READ(reg);
9363
9364         if (obj->tiling_mode != I915_TILING_NONE)
9365                 dspcntr |= DISPPLANE_TILED;
9366         else
9367                 dspcntr &= ~DISPPLANE_TILED;
9368
9369         I915_WRITE(reg, dspcntr);
9370
9371         I915_WRITE(DSPSURF(intel_crtc->plane),
9372                    intel_crtc->unpin_work->gtt_offset);
9373         POSTING_READ(DSPSURF(intel_crtc->plane));
9374 }
9375
9376 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9377 {
9378         struct intel_engine_cs *ring;
9379         int ret;
9380
9381         lockdep_assert_held(&obj->base.dev->struct_mutex);
9382
9383         if (!obj->last_write_seqno)
9384                 return 0;
9385
9386         ring = obj->ring;
9387
9388         if (i915_seqno_passed(ring->get_seqno(ring, true),
9389                               obj->last_write_seqno))
9390                 return 0;
9391
9392         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9393         if (ret)
9394                 return ret;
9395
9396         if (WARN_ON(!ring->irq_get(ring)))
9397                 return 0;
9398
9399         return 1;
9400 }
9401
9402 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9403 {
9404         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9405         struct intel_crtc *intel_crtc;
9406         unsigned long irq_flags;
9407         u32 seqno;
9408
9409         seqno = ring->get_seqno(ring, false);
9410
9411         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9412         for_each_intel_crtc(ring->dev, intel_crtc) {
9413                 struct intel_mmio_flip *mmio_flip;
9414
9415                 mmio_flip = &intel_crtc->mmio_flip;
9416                 if (mmio_flip->seqno == 0)
9417                         continue;
9418
9419                 if (ring->id != mmio_flip->ring_id)
9420                         continue;
9421
9422                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9423                         intel_do_mmio_flip(intel_crtc);
9424                         mmio_flip->seqno = 0;
9425                         ring->irq_put(ring);
9426                 }
9427         }
9428         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9429 }
9430
9431 static int intel_queue_mmio_flip(struct drm_device *dev,
9432                                  struct drm_crtc *crtc,
9433                                  struct drm_framebuffer *fb,
9434                                  struct drm_i915_gem_object *obj,
9435                                  struct intel_engine_cs *ring,
9436                                  uint32_t flags)
9437 {
9438         struct drm_i915_private *dev_priv = dev->dev_private;
9439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9440         int ret;
9441
9442         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9443                 return -EBUSY;
9444
9445         ret = intel_postpone_flip(obj);
9446         if (ret < 0)
9447                 return ret;
9448         if (ret == 0) {
9449                 intel_do_mmio_flip(intel_crtc);
9450                 return 0;
9451         }
9452
9453         spin_lock_irq(&dev_priv->mmio_flip_lock);
9454         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9455         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9456         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9457
9458         /*
9459          * Double check to catch cases where irq fired before
9460          * mmio flip data was ready
9461          */
9462         intel_notify_mmio_flip(obj->ring);
9463         return 0;
9464 }
9465
9466 static int intel_default_queue_flip(struct drm_device *dev,
9467                                     struct drm_crtc *crtc,
9468                                     struct drm_framebuffer *fb,
9469                                     struct drm_i915_gem_object *obj,
9470                                     struct intel_engine_cs *ring,
9471                                     uint32_t flags)
9472 {
9473         return -ENODEV;
9474 }
9475
9476 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9477                                          struct drm_crtc *crtc)
9478 {
9479         struct drm_i915_private *dev_priv = dev->dev_private;
9480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9481         struct intel_unpin_work *work = intel_crtc->unpin_work;
9482         u32 addr;
9483
9484         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9485                 return true;
9486
9487         if (!work->enable_stall_check)
9488                 return false;
9489
9490         if (work->flip_ready_vblank == 0) {
9491                 if (work->flip_queued_ring &&
9492                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9493                                        work->flip_queued_seqno))
9494                         return false;
9495
9496                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9497         }
9498
9499         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9500                 return false;
9501
9502         /* Potential stall - if we see that the flip has happened,
9503          * assume a missed interrupt. */
9504         if (INTEL_INFO(dev)->gen >= 4)
9505                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9506         else
9507                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9508
9509         /* There is a potential issue here with a false positive after a flip
9510          * to the same address. We could address this by checking for a
9511          * non-incrementing frame counter.
9512          */
9513         return addr == work->gtt_offset;
9514 }
9515
9516 void intel_check_page_flip(struct drm_device *dev, int pipe)
9517 {
9518         struct drm_i915_private *dev_priv = dev->dev_private;
9519         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9521
9522         WARN_ON(!in_irq());
9523
9524         if (crtc == NULL)
9525                 return;
9526
9527         spin_lock(&dev->event_lock);
9528         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9529                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9530                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9531                 page_flip_completed(intel_crtc);
9532         }
9533         spin_unlock(&dev->event_lock);
9534 }
9535
9536 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9537                                 struct drm_framebuffer *fb,
9538                                 struct drm_pending_vblank_event *event,
9539                                 uint32_t page_flip_flags)
9540 {
9541         struct drm_device *dev = crtc->dev;
9542         struct drm_i915_private *dev_priv = dev->dev_private;
9543         struct drm_framebuffer *old_fb = crtc->primary->fb;
9544         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9546         enum pipe pipe = intel_crtc->pipe;
9547         struct intel_unpin_work *work;
9548         struct intel_engine_cs *ring;
9549         int ret;
9550
9551         /*
9552          * drm_mode_page_flip_ioctl() should already catch this, but double
9553          * check to be safe.  In the future we may enable pageflipping from
9554          * a disabled primary plane.
9555          */
9556         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9557                 return -EBUSY;
9558
9559         /* Can't change pixel format via MI display flips. */
9560         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9561                 return -EINVAL;
9562
9563         /*
9564          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9565          * Note that pitch changes could also affect these register.
9566          */
9567         if (INTEL_INFO(dev)->gen > 3 &&
9568             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9569              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9570                 return -EINVAL;
9571
9572         if (i915_terminally_wedged(&dev_priv->gpu_error))
9573                 goto out_hang;
9574
9575         work = kzalloc(sizeof(*work), GFP_KERNEL);
9576         if (work == NULL)
9577                 return -ENOMEM;
9578
9579         work->event = event;
9580         work->crtc = crtc;
9581         work->old_fb_obj = intel_fb_obj(old_fb);
9582         INIT_WORK(&work->work, intel_unpin_work_fn);
9583
9584         ret = drm_crtc_vblank_get(crtc);
9585         if (ret)
9586                 goto free_work;
9587
9588         /* We borrow the event spin lock for protecting unpin_work */
9589         spin_lock_irq(&dev->event_lock);
9590         if (intel_crtc->unpin_work) {
9591                 /* Before declaring the flip queue wedged, check if
9592                  * the hardware completed the operation behind our backs.
9593                  */
9594                 if (__intel_pageflip_stall_check(dev, crtc)) {
9595                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9596                         page_flip_completed(intel_crtc);
9597                 } else {
9598                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9599                         spin_unlock_irq(&dev->event_lock);
9600
9601                         drm_crtc_vblank_put(crtc);
9602                         kfree(work);
9603                         return -EBUSY;
9604                 }
9605         }
9606         intel_crtc->unpin_work = work;
9607         spin_unlock_irq(&dev->event_lock);
9608
9609         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9610                 flush_workqueue(dev_priv->wq);
9611
9612         ret = i915_mutex_lock_interruptible(dev);
9613         if (ret)
9614                 goto cleanup;
9615
9616         /* Reference the objects for the scheduled work. */
9617         drm_gem_object_reference(&work->old_fb_obj->base);
9618         drm_gem_object_reference(&obj->base);
9619
9620         crtc->primary->fb = fb;
9621
9622         work->pending_flip_obj = obj;
9623
9624         atomic_inc(&intel_crtc->unpin_work_count);
9625         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9626
9627         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9628                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9629
9630         if (IS_VALLEYVIEW(dev)) {
9631                 ring = &dev_priv->ring[BCS];
9632                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9633                         /* vlv: DISPLAY_FLIP fails to change tiling */
9634                         ring = NULL;
9635         } else if (IS_IVYBRIDGE(dev)) {
9636                 ring = &dev_priv->ring[BCS];
9637         } else if (INTEL_INFO(dev)->gen >= 7) {
9638                 ring = obj->ring;
9639                 if (ring == NULL || ring->id != RCS)
9640                         ring = &dev_priv->ring[BCS];
9641         } else {
9642                 ring = &dev_priv->ring[RCS];
9643         }
9644
9645         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9646         if (ret)
9647                 goto cleanup_pending;
9648
9649         work->gtt_offset =
9650                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9651
9652         if (use_mmio_flip(ring, obj)) {
9653                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9654                                             page_flip_flags);
9655                 if (ret)
9656                         goto cleanup_unpin;
9657
9658                 work->flip_queued_seqno = obj->last_write_seqno;
9659                 work->flip_queued_ring = obj->ring;
9660         } else {
9661                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9662                                                    page_flip_flags);
9663                 if (ret)
9664                         goto cleanup_unpin;
9665
9666                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9667                 work->flip_queued_ring = ring;
9668         }
9669
9670         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9671         work->enable_stall_check = true;
9672
9673         i915_gem_track_fb(work->old_fb_obj, obj,
9674                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9675
9676         intel_disable_fbc(dev);
9677         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9678         mutex_unlock(&dev->struct_mutex);
9679
9680         trace_i915_flip_request(intel_crtc->plane, obj);
9681
9682         return 0;
9683
9684 cleanup_unpin:
9685         intel_unpin_fb_obj(obj);
9686 cleanup_pending:
9687         atomic_dec(&intel_crtc->unpin_work_count);
9688         crtc->primary->fb = old_fb;
9689         drm_gem_object_unreference(&work->old_fb_obj->base);
9690         drm_gem_object_unreference(&obj->base);
9691         mutex_unlock(&dev->struct_mutex);
9692
9693 cleanup:
9694         spin_lock_irq(&dev->event_lock);
9695         intel_crtc->unpin_work = NULL;
9696         spin_unlock_irq(&dev->event_lock);
9697
9698         drm_crtc_vblank_put(crtc);
9699 free_work:
9700         kfree(work);
9701
9702         if (ret == -EIO) {
9703 out_hang:
9704                 intel_crtc_wait_for_pending_flips(crtc);
9705                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9706                 if (ret == 0 && event) {
9707                         spin_lock_irq(&dev->event_lock);
9708                         drm_send_vblank_event(dev, pipe, event);
9709                         spin_unlock_irq(&dev->event_lock);
9710                 }
9711         }
9712         return ret;
9713 }
9714
9715 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9716         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9717         .load_lut = intel_crtc_load_lut,
9718 };
9719
9720 /**
9721  * intel_modeset_update_staged_output_state
9722  *
9723  * Updates the staged output configuration state, e.g. after we've read out the
9724  * current hw state.
9725  */
9726 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9727 {
9728         struct intel_crtc *crtc;
9729         struct intel_encoder *encoder;
9730         struct intel_connector *connector;
9731
9732         list_for_each_entry(connector, &dev->mode_config.connector_list,
9733                             base.head) {
9734                 connector->new_encoder =
9735                         to_intel_encoder(connector->base.encoder);
9736         }
9737
9738         for_each_intel_encoder(dev, encoder) {
9739                 encoder->new_crtc =
9740                         to_intel_crtc(encoder->base.crtc);
9741         }
9742
9743         for_each_intel_crtc(dev, crtc) {
9744                 crtc->new_enabled = crtc->base.enabled;
9745
9746                 if (crtc->new_enabled)
9747                         crtc->new_config = &crtc->config;
9748                 else
9749                         crtc->new_config = NULL;
9750         }
9751 }
9752
9753 /**
9754  * intel_modeset_commit_output_state
9755  *
9756  * This function copies the stage display pipe configuration to the real one.
9757  */
9758 static void intel_modeset_commit_output_state(struct drm_device *dev)
9759 {
9760         struct intel_crtc *crtc;
9761         struct intel_encoder *encoder;
9762         struct intel_connector *connector;
9763
9764         list_for_each_entry(connector, &dev->mode_config.connector_list,
9765                             base.head) {
9766                 connector->base.encoder = &connector->new_encoder->base;
9767         }
9768
9769         for_each_intel_encoder(dev, encoder) {
9770                 encoder->base.crtc = &encoder->new_crtc->base;
9771         }
9772
9773         for_each_intel_crtc(dev, crtc) {
9774                 crtc->base.enabled = crtc->new_enabled;
9775         }
9776 }
9777
9778 static void
9779 connected_sink_compute_bpp(struct intel_connector *connector,
9780                            struct intel_crtc_config *pipe_config)
9781 {
9782         int bpp = pipe_config->pipe_bpp;
9783
9784         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9785                 connector->base.base.id,
9786                 connector->base.name);
9787
9788         /* Don't use an invalid EDID bpc value */
9789         if (connector->base.display_info.bpc &&
9790             connector->base.display_info.bpc * 3 < bpp) {
9791                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9792                               bpp, connector->base.display_info.bpc*3);
9793                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9794         }
9795
9796         /* Clamp bpp to 8 on screens without EDID 1.4 */
9797         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9798                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9799                               bpp);
9800                 pipe_config->pipe_bpp = 24;
9801         }
9802 }
9803
9804 static int
9805 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9806                           struct drm_framebuffer *fb,
9807                           struct intel_crtc_config *pipe_config)
9808 {
9809         struct drm_device *dev = crtc->base.dev;
9810         struct intel_connector *connector;
9811         int bpp;
9812
9813         switch (fb->pixel_format) {
9814         case DRM_FORMAT_C8:
9815                 bpp = 8*3; /* since we go through a colormap */
9816                 break;
9817         case DRM_FORMAT_XRGB1555:
9818         case DRM_FORMAT_ARGB1555:
9819                 /* checked in intel_framebuffer_init already */
9820                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9821                         return -EINVAL;
9822         case DRM_FORMAT_RGB565:
9823                 bpp = 6*3; /* min is 18bpp */
9824                 break;
9825         case DRM_FORMAT_XBGR8888:
9826         case DRM_FORMAT_ABGR8888:
9827                 /* checked in intel_framebuffer_init already */
9828                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9829                         return -EINVAL;
9830         case DRM_FORMAT_XRGB8888:
9831         case DRM_FORMAT_ARGB8888:
9832                 bpp = 8*3;
9833                 break;
9834         case DRM_FORMAT_XRGB2101010:
9835         case DRM_FORMAT_ARGB2101010:
9836         case DRM_FORMAT_XBGR2101010:
9837         case DRM_FORMAT_ABGR2101010:
9838                 /* checked in intel_framebuffer_init already */
9839                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9840                         return -EINVAL;
9841                 bpp = 10*3;
9842                 break;
9843         /* TODO: gen4+ supports 16 bpc floating point, too. */
9844         default:
9845                 DRM_DEBUG_KMS("unsupported depth\n");
9846                 return -EINVAL;
9847         }
9848
9849         pipe_config->pipe_bpp = bpp;
9850
9851         /* Clamp display bpp to EDID value */
9852         list_for_each_entry(connector, &dev->mode_config.connector_list,
9853                             base.head) {
9854                 if (!connector->new_encoder ||
9855                     connector->new_encoder->new_crtc != crtc)
9856                         continue;
9857
9858                 connected_sink_compute_bpp(connector, pipe_config);
9859         }
9860
9861         return bpp;
9862 }
9863
9864 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9865 {
9866         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9867                         "type: 0x%x flags: 0x%x\n",
9868                 mode->crtc_clock,
9869                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9870                 mode->crtc_hsync_end, mode->crtc_htotal,
9871                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9872                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9873 }
9874
9875 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9876                                    struct intel_crtc_config *pipe_config,
9877                                    const char *context)
9878 {
9879         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9880                       context, pipe_name(crtc->pipe));
9881
9882         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9883         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9884                       pipe_config->pipe_bpp, pipe_config->dither);
9885         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9886                       pipe_config->has_pch_encoder,
9887                       pipe_config->fdi_lanes,
9888                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9889                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9890                       pipe_config->fdi_m_n.tu);
9891         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9892                       pipe_config->has_dp_encoder,
9893                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9894                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9895                       pipe_config->dp_m_n.tu);
9896
9897         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9898                       pipe_config->has_dp_encoder,
9899                       pipe_config->dp_m2_n2.gmch_m,
9900                       pipe_config->dp_m2_n2.gmch_n,
9901                       pipe_config->dp_m2_n2.link_m,
9902                       pipe_config->dp_m2_n2.link_n,
9903                       pipe_config->dp_m2_n2.tu);
9904
9905         DRM_DEBUG_KMS("requested mode:\n");
9906         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9907         DRM_DEBUG_KMS("adjusted mode:\n");
9908         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9909         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9910         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9911         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9912                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9913         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9914                       pipe_config->gmch_pfit.control,
9915                       pipe_config->gmch_pfit.pgm_ratios,
9916                       pipe_config->gmch_pfit.lvds_border_bits);
9917         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9918                       pipe_config->pch_pfit.pos,
9919                       pipe_config->pch_pfit.size,
9920                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9921         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9922         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9923 }
9924
9925 static bool encoders_cloneable(const struct intel_encoder *a,
9926                                const struct intel_encoder *b)
9927 {
9928         /* masks could be asymmetric, so check both ways */
9929         return a == b || (a->cloneable & (1 << b->type) &&
9930                           b->cloneable & (1 << a->type));
9931 }
9932
9933 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9934                                          struct intel_encoder *encoder)
9935 {
9936         struct drm_device *dev = crtc->base.dev;
9937         struct intel_encoder *source_encoder;
9938
9939         for_each_intel_encoder(dev, source_encoder) {
9940                 if (source_encoder->new_crtc != crtc)
9941                         continue;
9942
9943                 if (!encoders_cloneable(encoder, source_encoder))
9944                         return false;
9945         }
9946
9947         return true;
9948 }
9949
9950 static bool check_encoder_cloning(struct intel_crtc *crtc)
9951 {
9952         struct drm_device *dev = crtc->base.dev;
9953         struct intel_encoder *encoder;
9954
9955         for_each_intel_encoder(dev, encoder) {
9956                 if (encoder->new_crtc != crtc)
9957                         continue;
9958
9959                 if (!check_single_encoder_cloning(crtc, encoder))
9960                         return false;
9961         }
9962
9963         return true;
9964 }
9965
9966 static struct intel_crtc_config *
9967 intel_modeset_pipe_config(struct drm_crtc *crtc,
9968                           struct drm_framebuffer *fb,
9969                           struct drm_display_mode *mode)
9970 {
9971         struct drm_device *dev = crtc->dev;
9972         struct intel_encoder *encoder;
9973         struct intel_crtc_config *pipe_config;
9974         int plane_bpp, ret = -EINVAL;
9975         bool retry = true;
9976
9977         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9978                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9979                 return ERR_PTR(-EINVAL);
9980         }
9981
9982         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9983         if (!pipe_config)
9984                 return ERR_PTR(-ENOMEM);
9985
9986         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9987         drm_mode_copy(&pipe_config->requested_mode, mode);
9988
9989         pipe_config->cpu_transcoder =
9990                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9991         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9992
9993         /*
9994          * Sanitize sync polarity flags based on requested ones. If neither
9995          * positive or negative polarity is requested, treat this as meaning
9996          * negative polarity.
9997          */
9998         if (!(pipe_config->adjusted_mode.flags &
9999               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10000                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10001
10002         if (!(pipe_config->adjusted_mode.flags &
10003               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10004                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10005
10006         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10007          * plane pixel format and any sink constraints into account. Returns the
10008          * source plane bpp so that dithering can be selected on mismatches
10009          * after encoders and crtc also have had their say. */
10010         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10011                                               fb, pipe_config);
10012         if (plane_bpp < 0)
10013                 goto fail;
10014
10015         /*
10016          * Determine the real pipe dimensions. Note that stereo modes can
10017          * increase the actual pipe size due to the frame doubling and
10018          * insertion of additional space for blanks between the frame. This
10019          * is stored in the crtc timings. We use the requested mode to do this
10020          * computation to clearly distinguish it from the adjusted mode, which
10021          * can be changed by the connectors in the below retry loop.
10022          */
10023         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10024         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10025         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10026
10027 encoder_retry:
10028         /* Ensure the port clock defaults are reset when retrying. */
10029         pipe_config->port_clock = 0;
10030         pipe_config->pixel_multiplier = 1;
10031
10032         /* Fill in default crtc timings, allow encoders to overwrite them. */
10033         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10034
10035         /* Pass our mode to the connectors and the CRTC to give them a chance to
10036          * adjust it according to limitations or connector properties, and also
10037          * a chance to reject the mode entirely.
10038          */
10039         for_each_intel_encoder(dev, encoder) {
10040
10041                 if (&encoder->new_crtc->base != crtc)
10042                         continue;
10043
10044                 if (!(encoder->compute_config(encoder, pipe_config))) {
10045                         DRM_DEBUG_KMS("Encoder config failure\n");
10046                         goto fail;
10047                 }
10048         }
10049
10050         /* Set default port clock if not overwritten by the encoder. Needs to be
10051          * done afterwards in case the encoder adjusts the mode. */
10052         if (!pipe_config->port_clock)
10053                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10054                         * pipe_config->pixel_multiplier;
10055
10056         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10057         if (ret < 0) {
10058                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10059                 goto fail;
10060         }
10061
10062         if (ret == RETRY) {
10063                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10064                         ret = -EINVAL;
10065                         goto fail;
10066                 }
10067
10068                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10069                 retry = false;
10070                 goto encoder_retry;
10071         }
10072
10073         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10074         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10075                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10076
10077         return pipe_config;
10078 fail:
10079         kfree(pipe_config);
10080         return ERR_PTR(ret);
10081 }
10082
10083 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10084  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10085 static void
10086 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10087                              unsigned *prepare_pipes, unsigned *disable_pipes)
10088 {
10089         struct intel_crtc *intel_crtc;
10090         struct drm_device *dev = crtc->dev;
10091         struct intel_encoder *encoder;
10092         struct intel_connector *connector;
10093         struct drm_crtc *tmp_crtc;
10094
10095         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10096
10097         /* Check which crtcs have changed outputs connected to them, these need
10098          * to be part of the prepare_pipes mask. We don't (yet) support global
10099          * modeset across multiple crtcs, so modeset_pipes will only have one
10100          * bit set at most. */
10101         list_for_each_entry(connector, &dev->mode_config.connector_list,
10102                             base.head) {
10103                 if (connector->base.encoder == &connector->new_encoder->base)
10104                         continue;
10105
10106                 if (connector->base.encoder) {
10107                         tmp_crtc = connector->base.encoder->crtc;
10108
10109                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10110                 }
10111
10112                 if (connector->new_encoder)
10113                         *prepare_pipes |=
10114                                 1 << connector->new_encoder->new_crtc->pipe;
10115         }
10116
10117         for_each_intel_encoder(dev, encoder) {
10118                 if (encoder->base.crtc == &encoder->new_crtc->base)
10119                         continue;
10120
10121                 if (encoder->base.crtc) {
10122                         tmp_crtc = encoder->base.crtc;
10123
10124                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10125                 }
10126
10127                 if (encoder->new_crtc)
10128                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10129         }
10130
10131         /* Check for pipes that will be enabled/disabled ... */
10132         for_each_intel_crtc(dev, intel_crtc) {
10133                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10134                         continue;
10135
10136                 if (!intel_crtc->new_enabled)
10137                         *disable_pipes |= 1 << intel_crtc->pipe;
10138                 else
10139                         *prepare_pipes |= 1 << intel_crtc->pipe;
10140         }
10141
10142
10143         /* set_mode is also used to update properties on life display pipes. */
10144         intel_crtc = to_intel_crtc(crtc);
10145         if (intel_crtc->new_enabled)
10146                 *prepare_pipes |= 1 << intel_crtc->pipe;
10147
10148         /*
10149          * For simplicity do a full modeset on any pipe where the output routing
10150          * changed. We could be more clever, but that would require us to be
10151          * more careful with calling the relevant encoder->mode_set functions.
10152          */
10153         if (*prepare_pipes)
10154                 *modeset_pipes = *prepare_pipes;
10155
10156         /* ... and mask these out. */
10157         *modeset_pipes &= ~(*disable_pipes);
10158         *prepare_pipes &= ~(*disable_pipes);
10159
10160         /*
10161          * HACK: We don't (yet) fully support global modesets. intel_set_config
10162          * obies this rule, but the modeset restore mode of
10163          * intel_modeset_setup_hw_state does not.
10164          */
10165         *modeset_pipes &= 1 << intel_crtc->pipe;
10166         *prepare_pipes &= 1 << intel_crtc->pipe;
10167
10168         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10169                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10170 }
10171
10172 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10173 {
10174         struct drm_encoder *encoder;
10175         struct drm_device *dev = crtc->dev;
10176
10177         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10178                 if (encoder->crtc == crtc)
10179                         return true;
10180
10181         return false;
10182 }
10183
10184 static void
10185 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10186 {
10187         struct intel_encoder *intel_encoder;
10188         struct intel_crtc *intel_crtc;
10189         struct drm_connector *connector;
10190
10191         for_each_intel_encoder(dev, intel_encoder) {
10192                 if (!intel_encoder->base.crtc)
10193                         continue;
10194
10195                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10196
10197                 if (prepare_pipes & (1 << intel_crtc->pipe))
10198                         intel_encoder->connectors_active = false;
10199         }
10200
10201         intel_modeset_commit_output_state(dev);
10202
10203         /* Double check state. */
10204         for_each_intel_crtc(dev, intel_crtc) {
10205                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10206                 WARN_ON(intel_crtc->new_config &&
10207                         intel_crtc->new_config != &intel_crtc->config);
10208                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10209         }
10210
10211         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10212                 if (!connector->encoder || !connector->encoder->crtc)
10213                         continue;
10214
10215                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10216
10217                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10218                         struct drm_property *dpms_property =
10219                                 dev->mode_config.dpms_property;
10220
10221                         connector->dpms = DRM_MODE_DPMS_ON;
10222                         drm_object_property_set_value(&connector->base,
10223                                                          dpms_property,
10224                                                          DRM_MODE_DPMS_ON);
10225
10226                         intel_encoder = to_intel_encoder(connector->encoder);
10227                         intel_encoder->connectors_active = true;
10228                 }
10229         }
10230
10231 }
10232
10233 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10234 {
10235         int diff;
10236
10237         if (clock1 == clock2)
10238                 return true;
10239
10240         if (!clock1 || !clock2)
10241                 return false;
10242
10243         diff = abs(clock1 - clock2);
10244
10245         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10246                 return true;
10247
10248         return false;
10249 }
10250
10251 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10252         list_for_each_entry((intel_crtc), \
10253                             &(dev)->mode_config.crtc_list, \
10254                             base.head) \
10255                 if (mask & (1 <<(intel_crtc)->pipe))
10256
10257 static bool
10258 intel_pipe_config_compare(struct drm_device *dev,
10259                           struct intel_crtc_config *current_config,
10260                           struct intel_crtc_config *pipe_config)
10261 {
10262 #define PIPE_CONF_CHECK_X(name) \
10263         if (current_config->name != pipe_config->name) { \
10264                 DRM_ERROR("mismatch in " #name " " \
10265                           "(expected 0x%08x, found 0x%08x)\n", \
10266                           current_config->name, \
10267                           pipe_config->name); \
10268                 return false; \
10269         }
10270
10271 #define PIPE_CONF_CHECK_I(name) \
10272         if (current_config->name != pipe_config->name) { \
10273                 DRM_ERROR("mismatch in " #name " " \
10274                           "(expected %i, found %i)\n", \
10275                           current_config->name, \
10276                           pipe_config->name); \
10277                 return false; \
10278         }
10279
10280 /* This is required for BDW+ where there is only one set of registers for
10281  * switching between high and low RR.
10282  * This macro can be used whenever a comparison has to be made between one
10283  * hw state and multiple sw state variables.
10284  */
10285 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10286         if ((current_config->name != pipe_config->name) && \
10287                 (current_config->alt_name != pipe_config->name)) { \
10288                         DRM_ERROR("mismatch in " #name " " \
10289                                   "(expected %i or %i, found %i)\n", \
10290                                   current_config->name, \
10291                                   current_config->alt_name, \
10292                                   pipe_config->name); \
10293                         return false; \
10294         }
10295
10296 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10297         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10298                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10299                           "(expected %i, found %i)\n", \
10300                           current_config->name & (mask), \
10301                           pipe_config->name & (mask)); \
10302                 return false; \
10303         }
10304
10305 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10306         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10307                 DRM_ERROR("mismatch in " #name " " \
10308                           "(expected %i, found %i)\n", \
10309                           current_config->name, \
10310                           pipe_config->name); \
10311                 return false; \
10312         }
10313
10314 #define PIPE_CONF_QUIRK(quirk)  \
10315         ((current_config->quirks | pipe_config->quirks) & (quirk))
10316
10317         PIPE_CONF_CHECK_I(cpu_transcoder);
10318
10319         PIPE_CONF_CHECK_I(has_pch_encoder);
10320         PIPE_CONF_CHECK_I(fdi_lanes);
10321         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10322         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10323         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10324         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10325         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10326
10327         PIPE_CONF_CHECK_I(has_dp_encoder);
10328
10329         if (INTEL_INFO(dev)->gen < 8) {
10330                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10331                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10332                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10333                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10334                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10335
10336                 if (current_config->has_drrs) {
10337                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10338                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10339                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10340                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10341                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10342                 }
10343         } else {
10344                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10345                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10346                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10347                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10348                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10349         }
10350
10351         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10352         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10354         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10355         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10357
10358         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10359         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10360         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10361         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10362         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10363         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10364
10365         PIPE_CONF_CHECK_I(pixel_multiplier);
10366         PIPE_CONF_CHECK_I(has_hdmi_sink);
10367         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10368             IS_VALLEYVIEW(dev))
10369                 PIPE_CONF_CHECK_I(limited_color_range);
10370
10371         PIPE_CONF_CHECK_I(has_audio);
10372
10373         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10374                               DRM_MODE_FLAG_INTERLACE);
10375
10376         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10377                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10378                                       DRM_MODE_FLAG_PHSYNC);
10379                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10380                                       DRM_MODE_FLAG_NHSYNC);
10381                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10382                                       DRM_MODE_FLAG_PVSYNC);
10383                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10384                                       DRM_MODE_FLAG_NVSYNC);
10385         }
10386
10387         PIPE_CONF_CHECK_I(pipe_src_w);
10388         PIPE_CONF_CHECK_I(pipe_src_h);
10389
10390         /*
10391          * FIXME: BIOS likes to set up a cloned config with lvds+external
10392          * screen. Since we don't yet re-compute the pipe config when moving
10393          * just the lvds port away to another pipe the sw tracking won't match.
10394          *
10395          * Proper atomic modesets with recomputed global state will fix this.
10396          * Until then just don't check gmch state for inherited modes.
10397          */
10398         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10399                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10400                 /* pfit ratios are autocomputed by the hw on gen4+ */
10401                 if (INTEL_INFO(dev)->gen < 4)
10402                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10403                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10404         }
10405
10406         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10407         if (current_config->pch_pfit.enabled) {
10408                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10409                 PIPE_CONF_CHECK_I(pch_pfit.size);
10410         }
10411
10412         /* BDW+ don't expose a synchronous way to read the state */
10413         if (IS_HASWELL(dev))
10414                 PIPE_CONF_CHECK_I(ips_enabled);
10415
10416         PIPE_CONF_CHECK_I(double_wide);
10417
10418         PIPE_CONF_CHECK_X(ddi_pll_sel);
10419
10420         PIPE_CONF_CHECK_I(shared_dpll);
10421         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10422         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10423         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10424         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10425         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10426
10427         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10428                 PIPE_CONF_CHECK_I(pipe_bpp);
10429
10430         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10431         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10432
10433 #undef PIPE_CONF_CHECK_X
10434 #undef PIPE_CONF_CHECK_I
10435 #undef PIPE_CONF_CHECK_I_ALT
10436 #undef PIPE_CONF_CHECK_FLAGS
10437 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10438 #undef PIPE_CONF_QUIRK
10439
10440         return true;
10441 }
10442
10443 static void
10444 check_connector_state(struct drm_device *dev)
10445 {
10446         struct intel_connector *connector;
10447
10448         list_for_each_entry(connector, &dev->mode_config.connector_list,
10449                             base.head) {
10450                 /* This also checks the encoder/connector hw state with the
10451                  * ->get_hw_state callbacks. */
10452                 intel_connector_check_state(connector);
10453
10454                 WARN(&connector->new_encoder->base != connector->base.encoder,
10455                      "connector's staged encoder doesn't match current encoder\n");
10456         }
10457 }
10458
10459 static void
10460 check_encoder_state(struct drm_device *dev)
10461 {
10462         struct intel_encoder *encoder;
10463         struct intel_connector *connector;
10464
10465         for_each_intel_encoder(dev, encoder) {
10466                 bool enabled = false;
10467                 bool active = false;
10468                 enum pipe pipe, tracked_pipe;
10469
10470                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10471                               encoder->base.base.id,
10472                               encoder->base.name);
10473
10474                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10475                      "encoder's stage crtc doesn't match current crtc\n");
10476                 WARN(encoder->connectors_active && !encoder->base.crtc,
10477                      "encoder's active_connectors set, but no crtc\n");
10478
10479                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10480                                     base.head) {
10481                         if (connector->base.encoder != &encoder->base)
10482                                 continue;
10483                         enabled = true;
10484                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10485                                 active = true;
10486                 }
10487                 /*
10488                  * for MST connectors if we unplug the connector is gone
10489                  * away but the encoder is still connected to a crtc
10490                  * until a modeset happens in response to the hotplug.
10491                  */
10492                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10493                         continue;
10494
10495                 WARN(!!encoder->base.crtc != enabled,
10496                      "encoder's enabled state mismatch "
10497                      "(expected %i, found %i)\n",
10498                      !!encoder->base.crtc, enabled);
10499                 WARN(active && !encoder->base.crtc,
10500                      "active encoder with no crtc\n");
10501
10502                 WARN(encoder->connectors_active != active,
10503                      "encoder's computed active state doesn't match tracked active state "
10504                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10505
10506                 active = encoder->get_hw_state(encoder, &pipe);
10507                 WARN(active != encoder->connectors_active,
10508                      "encoder's hw state doesn't match sw tracking "
10509                      "(expected %i, found %i)\n",
10510                      encoder->connectors_active, active);
10511
10512                 if (!encoder->base.crtc)
10513                         continue;
10514
10515                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10516                 WARN(active && pipe != tracked_pipe,
10517                      "active encoder's pipe doesn't match"
10518                      "(expected %i, found %i)\n",
10519                      tracked_pipe, pipe);
10520
10521         }
10522 }
10523
10524 static void
10525 check_crtc_state(struct drm_device *dev)
10526 {
10527         struct drm_i915_private *dev_priv = dev->dev_private;
10528         struct intel_crtc *crtc;
10529         struct intel_encoder *encoder;
10530         struct intel_crtc_config pipe_config;
10531
10532         for_each_intel_crtc(dev, crtc) {
10533                 bool enabled = false;
10534                 bool active = false;
10535
10536                 memset(&pipe_config, 0, sizeof(pipe_config));
10537
10538                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10539                               crtc->base.base.id);
10540
10541                 WARN(crtc->active && !crtc->base.enabled,
10542                      "active crtc, but not enabled in sw tracking\n");
10543
10544                 for_each_intel_encoder(dev, encoder) {
10545                         if (encoder->base.crtc != &crtc->base)
10546                                 continue;
10547                         enabled = true;
10548                         if (encoder->connectors_active)
10549                                 active = true;
10550                 }
10551
10552                 WARN(active != crtc->active,
10553                      "crtc's computed active state doesn't match tracked active state "
10554                      "(expected %i, found %i)\n", active, crtc->active);
10555                 WARN(enabled != crtc->base.enabled,
10556                      "crtc's computed enabled state doesn't match tracked enabled state "
10557                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10558
10559                 active = dev_priv->display.get_pipe_config(crtc,
10560                                                            &pipe_config);
10561
10562                 /* hw state is inconsistent with the pipe quirk */
10563                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10564                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10565                         active = crtc->active;
10566
10567                 for_each_intel_encoder(dev, encoder) {
10568                         enum pipe pipe;
10569                         if (encoder->base.crtc != &crtc->base)
10570                                 continue;
10571                         if (encoder->get_hw_state(encoder, &pipe))
10572                                 encoder->get_config(encoder, &pipe_config);
10573                 }
10574
10575                 WARN(crtc->active != active,
10576                      "crtc active state doesn't match with hw state "
10577                      "(expected %i, found %i)\n", crtc->active, active);
10578
10579                 if (active &&
10580                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10581                         WARN(1, "pipe state doesn't match!\n");
10582                         intel_dump_pipe_config(crtc, &pipe_config,
10583                                                "[hw state]");
10584                         intel_dump_pipe_config(crtc, &crtc->config,
10585                                                "[sw state]");
10586                 }
10587         }
10588 }
10589
10590 static void
10591 check_shared_dpll_state(struct drm_device *dev)
10592 {
10593         struct drm_i915_private *dev_priv = dev->dev_private;
10594         struct intel_crtc *crtc;
10595         struct intel_dpll_hw_state dpll_hw_state;
10596         int i;
10597
10598         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10599                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10600                 int enabled_crtcs = 0, active_crtcs = 0;
10601                 bool active;
10602
10603                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10604
10605                 DRM_DEBUG_KMS("%s\n", pll->name);
10606
10607                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10608
10609                 WARN(pll->active > hweight32(pll->crtc_mask),
10610                      "more active pll users than references: %i vs %i\n",
10611                      pll->active, hweight32(pll->crtc_mask));
10612                 WARN(pll->active && !pll->on,
10613                      "pll in active use but not on in sw tracking\n");
10614                 WARN(pll->on && !pll->active,
10615                      "pll in on but not on in use in sw tracking\n");
10616                 WARN(pll->on != active,
10617                      "pll on state mismatch (expected %i, found %i)\n",
10618                      pll->on, active);
10619
10620                 for_each_intel_crtc(dev, crtc) {
10621                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10622                                 enabled_crtcs++;
10623                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10624                                 active_crtcs++;
10625                 }
10626                 WARN(pll->active != active_crtcs,
10627                      "pll active crtcs mismatch (expected %i, found %i)\n",
10628                      pll->active, active_crtcs);
10629                 WARN(hweight32(pll->crtc_mask) != enabled_crtcs,
10630                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10631                      hweight32(pll->crtc_mask), enabled_crtcs);
10632
10633                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10634                                        sizeof(dpll_hw_state)),
10635                      "pll hw state mismatch\n");
10636         }
10637 }
10638
10639 void
10640 intel_modeset_check_state(struct drm_device *dev)
10641 {
10642         check_connector_state(dev);
10643         check_encoder_state(dev);
10644         check_crtc_state(dev);
10645         check_shared_dpll_state(dev);
10646 }
10647
10648 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10649                                      int dotclock)
10650 {
10651         /*
10652          * FDI already provided one idea for the dotclock.
10653          * Yell if the encoder disagrees.
10654          */
10655         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10656              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10657              pipe_config->adjusted_mode.crtc_clock, dotclock);
10658 }
10659
10660 static void update_scanline_offset(struct intel_crtc *crtc)
10661 {
10662         struct drm_device *dev = crtc->base.dev;
10663
10664         /*
10665          * The scanline counter increments at the leading edge of hsync.
10666          *
10667          * On most platforms it starts counting from vtotal-1 on the
10668          * first active line. That means the scanline counter value is
10669          * always one less than what we would expect. Ie. just after
10670          * start of vblank, which also occurs at start of hsync (on the
10671          * last active line), the scanline counter will read vblank_start-1.
10672          *
10673          * On gen2 the scanline counter starts counting from 1 instead
10674          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10675          * to keep the value positive), instead of adding one.
10676          *
10677          * On HSW+ the behaviour of the scanline counter depends on the output
10678          * type. For DP ports it behaves like most other platforms, but on HDMI
10679          * there's an extra 1 line difference. So we need to add two instead of
10680          * one to the value.
10681          */
10682         if (IS_GEN2(dev)) {
10683                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10684                 int vtotal;
10685
10686                 vtotal = mode->crtc_vtotal;
10687                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10688                         vtotal /= 2;
10689
10690                 crtc->scanline_offset = vtotal - 1;
10691         } else if (HAS_DDI(dev) &&
10692                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10693                 crtc->scanline_offset = 2;
10694         } else
10695                 crtc->scanline_offset = 1;
10696 }
10697
10698 static int __intel_set_mode(struct drm_crtc *crtc,
10699                             struct drm_display_mode *mode,
10700                             int x, int y, struct drm_framebuffer *fb)
10701 {
10702         struct drm_device *dev = crtc->dev;
10703         struct drm_i915_private *dev_priv = dev->dev_private;
10704         struct drm_display_mode *saved_mode;
10705         struct intel_crtc_config *pipe_config = NULL;
10706         struct intel_crtc *intel_crtc;
10707         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10708         int ret = 0;
10709
10710         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10711         if (!saved_mode)
10712                 return -ENOMEM;
10713
10714         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10715                                      &prepare_pipes, &disable_pipes);
10716
10717         *saved_mode = crtc->mode;
10718
10719         /* Hack: Because we don't (yet) support global modeset on multiple
10720          * crtcs, we don't keep track of the new mode for more than one crtc.
10721          * Hence simply check whether any bit is set in modeset_pipes in all the
10722          * pieces of code that are not yet converted to deal with mutliple crtcs
10723          * changing their mode at the same time. */
10724         if (modeset_pipes) {
10725                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10726                 if (IS_ERR(pipe_config)) {
10727                         ret = PTR_ERR(pipe_config);
10728                         pipe_config = NULL;
10729
10730                         goto out;
10731                 }
10732                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10733                                        "[modeset]");
10734                 to_intel_crtc(crtc)->new_config = pipe_config;
10735         }
10736
10737         /*
10738          * See if the config requires any additional preparation, e.g.
10739          * to adjust global state with pipes off.  We need to do this
10740          * here so we can get the modeset_pipe updated config for the new
10741          * mode set on this crtc.  For other crtcs we need to use the
10742          * adjusted_mode bits in the crtc directly.
10743          */
10744         if (IS_VALLEYVIEW(dev)) {
10745                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10746
10747                 /* may have added more to prepare_pipes than we should */
10748                 prepare_pipes &= ~disable_pipes;
10749         }
10750
10751         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10752                 intel_crtc_disable(&intel_crtc->base);
10753
10754         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10755                 if (intel_crtc->base.enabled)
10756                         dev_priv->display.crtc_disable(&intel_crtc->base);
10757         }
10758
10759         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10760          * to set it here already despite that we pass it down the callchain.
10761          */
10762         if (modeset_pipes) {
10763                 crtc->mode = *mode;
10764                 /* mode_set/enable/disable functions rely on a correct pipe
10765                  * config. */
10766                 to_intel_crtc(crtc)->config = *pipe_config;
10767                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10768
10769                 /*
10770                  * Calculate and store various constants which
10771                  * are later needed by vblank and swap-completion
10772                  * timestamping. They are derived from true hwmode.
10773                  */
10774                 drm_calc_timestamping_constants(crtc,
10775                                                 &pipe_config->adjusted_mode);
10776         }
10777
10778         /* Only after disabling all output pipelines that will be changed can we
10779          * update the the output configuration. */
10780         intel_modeset_update_state(dev, prepare_pipes);
10781
10782         if (dev_priv->display.modeset_global_resources)
10783                 dev_priv->display.modeset_global_resources(dev);
10784
10785         /* Set up the DPLL and any encoders state that needs to adjust or depend
10786          * on the DPLL.
10787          */
10788         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10789                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10790                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10791                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10792
10793                 mutex_lock(&dev->struct_mutex);
10794                 ret = intel_pin_and_fence_fb_obj(dev,
10795                                                  obj,
10796                                                  NULL);
10797                 if (ret != 0) {
10798                         DRM_ERROR("pin & fence failed\n");
10799                         mutex_unlock(&dev->struct_mutex);
10800                         goto done;
10801                 }
10802                 if (old_fb)
10803                         intel_unpin_fb_obj(old_obj);
10804                 i915_gem_track_fb(old_obj, obj,
10805                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10806                 mutex_unlock(&dev->struct_mutex);
10807
10808                 crtc->primary->fb = fb;
10809                 crtc->x = x;
10810                 crtc->y = y;
10811
10812                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10813                 if (ret)
10814                         goto done;
10815         }
10816
10817         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10818         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10819                 update_scanline_offset(intel_crtc);
10820
10821                 dev_priv->display.crtc_enable(&intel_crtc->base);
10822         }
10823
10824         /* FIXME: add subpixel order */
10825 done:
10826         if (ret && crtc->enabled)
10827                 crtc->mode = *saved_mode;
10828
10829 out:
10830         kfree(pipe_config);
10831         kfree(saved_mode);
10832         return ret;
10833 }
10834
10835 static int intel_set_mode(struct drm_crtc *crtc,
10836                           struct drm_display_mode *mode,
10837                           int x, int y, struct drm_framebuffer *fb)
10838 {
10839         int ret;
10840
10841         ret = __intel_set_mode(crtc, mode, x, y, fb);
10842
10843         if (ret == 0)
10844                 intel_modeset_check_state(crtc->dev);
10845
10846         return ret;
10847 }
10848
10849 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10850 {
10851         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10852 }
10853
10854 #undef for_each_intel_crtc_masked
10855
10856 static void intel_set_config_free(struct intel_set_config *config)
10857 {
10858         if (!config)
10859                 return;
10860
10861         kfree(config->save_connector_encoders);
10862         kfree(config->save_encoder_crtcs);
10863         kfree(config->save_crtc_enabled);
10864         kfree(config);
10865 }
10866
10867 static int intel_set_config_save_state(struct drm_device *dev,
10868                                        struct intel_set_config *config)
10869 {
10870         struct drm_crtc *crtc;
10871         struct drm_encoder *encoder;
10872         struct drm_connector *connector;
10873         int count;
10874
10875         config->save_crtc_enabled =
10876                 kcalloc(dev->mode_config.num_crtc,
10877                         sizeof(bool), GFP_KERNEL);
10878         if (!config->save_crtc_enabled)
10879                 return -ENOMEM;
10880
10881         config->save_encoder_crtcs =
10882                 kcalloc(dev->mode_config.num_encoder,
10883                         sizeof(struct drm_crtc *), GFP_KERNEL);
10884         if (!config->save_encoder_crtcs)
10885                 return -ENOMEM;
10886
10887         config->save_connector_encoders =
10888                 kcalloc(dev->mode_config.num_connector,
10889                         sizeof(struct drm_encoder *), GFP_KERNEL);
10890         if (!config->save_connector_encoders)
10891                 return -ENOMEM;
10892
10893         /* Copy data. Note that driver private data is not affected.
10894          * Should anything bad happen only the expected state is
10895          * restored, not the drivers personal bookkeeping.
10896          */
10897         count = 0;
10898         for_each_crtc(dev, crtc) {
10899                 config->save_crtc_enabled[count++] = crtc->enabled;
10900         }
10901
10902         count = 0;
10903         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10904                 config->save_encoder_crtcs[count++] = encoder->crtc;
10905         }
10906
10907         count = 0;
10908         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10909                 config->save_connector_encoders[count++] = connector->encoder;
10910         }
10911
10912         return 0;
10913 }
10914
10915 static void intel_set_config_restore_state(struct drm_device *dev,
10916                                            struct intel_set_config *config)
10917 {
10918         struct intel_crtc *crtc;
10919         struct intel_encoder *encoder;
10920         struct intel_connector *connector;
10921         int count;
10922
10923         count = 0;
10924         for_each_intel_crtc(dev, crtc) {
10925                 crtc->new_enabled = config->save_crtc_enabled[count++];
10926
10927                 if (crtc->new_enabled)
10928                         crtc->new_config = &crtc->config;
10929                 else
10930                         crtc->new_config = NULL;
10931         }
10932
10933         count = 0;
10934         for_each_intel_encoder(dev, encoder) {
10935                 encoder->new_crtc =
10936                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10937         }
10938
10939         count = 0;
10940         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10941                 connector->new_encoder =
10942                         to_intel_encoder(config->save_connector_encoders[count++]);
10943         }
10944 }
10945
10946 static bool
10947 is_crtc_connector_off(struct drm_mode_set *set)
10948 {
10949         int i;
10950
10951         if (set->num_connectors == 0)
10952                 return false;
10953
10954         if (WARN_ON(set->connectors == NULL))
10955                 return false;
10956
10957         for (i = 0; i < set->num_connectors; i++)
10958                 if (set->connectors[i]->encoder &&
10959                     set->connectors[i]->encoder->crtc == set->crtc &&
10960                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10961                         return true;
10962
10963         return false;
10964 }
10965
10966 static void
10967 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10968                                       struct intel_set_config *config)
10969 {
10970
10971         /* We should be able to check here if the fb has the same properties
10972          * and then just flip_or_move it */
10973         if (is_crtc_connector_off(set)) {
10974                 config->mode_changed = true;
10975         } else if (set->crtc->primary->fb != set->fb) {
10976                 /*
10977                  * If we have no fb, we can only flip as long as the crtc is
10978                  * active, otherwise we need a full mode set.  The crtc may
10979                  * be active if we've only disabled the primary plane, or
10980                  * in fastboot situations.
10981                  */
10982                 if (set->crtc->primary->fb == NULL) {
10983                         struct intel_crtc *intel_crtc =
10984                                 to_intel_crtc(set->crtc);
10985
10986                         if (intel_crtc->active) {
10987                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10988                                 config->fb_changed = true;
10989                         } else {
10990                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10991                                 config->mode_changed = true;
10992                         }
10993                 } else if (set->fb == NULL) {
10994                         config->mode_changed = true;
10995                 } else if (set->fb->pixel_format !=
10996                            set->crtc->primary->fb->pixel_format) {
10997                         config->mode_changed = true;
10998                 } else {
10999                         config->fb_changed = true;
11000                 }
11001         }
11002
11003         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11004                 config->fb_changed = true;
11005
11006         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11007                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11008                 drm_mode_debug_printmodeline(&set->crtc->mode);
11009                 drm_mode_debug_printmodeline(set->mode);
11010                 config->mode_changed = true;
11011         }
11012
11013         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11014                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11015 }
11016
11017 static int
11018 intel_modeset_stage_output_state(struct drm_device *dev,
11019                                  struct drm_mode_set *set,
11020                                  struct intel_set_config *config)
11021 {
11022         struct intel_connector *connector;
11023         struct intel_encoder *encoder;
11024         struct intel_crtc *crtc;
11025         int ro;
11026
11027         /* The upper layers ensure that we either disable a crtc or have a list
11028          * of connectors. For paranoia, double-check this. */
11029         WARN_ON(!set->fb && (set->num_connectors != 0));
11030         WARN_ON(set->fb && (set->num_connectors == 0));
11031
11032         list_for_each_entry(connector, &dev->mode_config.connector_list,
11033                             base.head) {
11034                 /* Otherwise traverse passed in connector list and get encoders
11035                  * for them. */
11036                 for (ro = 0; ro < set->num_connectors; ro++) {
11037                         if (set->connectors[ro] == &connector->base) {
11038                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11039                                 break;
11040                         }
11041                 }
11042
11043                 /* If we disable the crtc, disable all its connectors. Also, if
11044                  * the connector is on the changing crtc but not on the new
11045                  * connector list, disable it. */
11046                 if ((!set->fb || ro == set->num_connectors) &&
11047                     connector->base.encoder &&
11048                     connector->base.encoder->crtc == set->crtc) {
11049                         connector->new_encoder = NULL;
11050
11051                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11052                                 connector->base.base.id,
11053                                 connector->base.name);
11054                 }
11055
11056
11057                 if (&connector->new_encoder->base != connector->base.encoder) {
11058                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11059                         config->mode_changed = true;
11060                 }
11061         }
11062         /* connector->new_encoder is now updated for all connectors. */
11063
11064         /* Update crtc of enabled connectors. */
11065         list_for_each_entry(connector, &dev->mode_config.connector_list,
11066                             base.head) {
11067                 struct drm_crtc *new_crtc;
11068
11069                 if (!connector->new_encoder)
11070                         continue;
11071
11072                 new_crtc = connector->new_encoder->base.crtc;
11073
11074                 for (ro = 0; ro < set->num_connectors; ro++) {
11075                         if (set->connectors[ro] == &connector->base)
11076                                 new_crtc = set->crtc;
11077                 }
11078
11079                 /* Make sure the new CRTC will work with the encoder */
11080                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11081                                          new_crtc)) {
11082                         return -EINVAL;
11083                 }
11084                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11085
11086                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11087                         connector->base.base.id,
11088                         connector->base.name,
11089                         new_crtc->base.id);
11090         }
11091
11092         /* Check for any encoders that needs to be disabled. */
11093         for_each_intel_encoder(dev, encoder) {
11094                 int num_connectors = 0;
11095                 list_for_each_entry(connector,
11096                                     &dev->mode_config.connector_list,
11097                                     base.head) {
11098                         if (connector->new_encoder == encoder) {
11099                                 WARN_ON(!connector->new_encoder->new_crtc);
11100                                 num_connectors++;
11101                         }
11102                 }
11103
11104                 if (num_connectors == 0)
11105                         encoder->new_crtc = NULL;
11106                 else if (num_connectors > 1)
11107                         return -EINVAL;
11108
11109                 /* Only now check for crtc changes so we don't miss encoders
11110                  * that will be disabled. */
11111                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11112                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11113                         config->mode_changed = true;
11114                 }
11115         }
11116         /* Now we've also updated encoder->new_crtc for all encoders. */
11117         list_for_each_entry(connector, &dev->mode_config.connector_list,
11118                             base.head) {
11119                 if (connector->new_encoder)
11120                         if (connector->new_encoder != connector->encoder)
11121                                 connector->encoder = connector->new_encoder;
11122         }
11123         for_each_intel_crtc(dev, crtc) {
11124                 crtc->new_enabled = false;
11125
11126                 for_each_intel_encoder(dev, encoder) {
11127                         if (encoder->new_crtc == crtc) {
11128                                 crtc->new_enabled = true;
11129                                 break;
11130                         }
11131                 }
11132
11133                 if (crtc->new_enabled != crtc->base.enabled) {
11134                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11135                                       crtc->new_enabled ? "en" : "dis");
11136                         config->mode_changed = true;
11137                 }
11138
11139                 if (crtc->new_enabled)
11140                         crtc->new_config = &crtc->config;
11141                 else
11142                         crtc->new_config = NULL;
11143         }
11144
11145         return 0;
11146 }
11147
11148 static void disable_crtc_nofb(struct intel_crtc *crtc)
11149 {
11150         struct drm_device *dev = crtc->base.dev;
11151         struct intel_encoder *encoder;
11152         struct intel_connector *connector;
11153
11154         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11155                       pipe_name(crtc->pipe));
11156
11157         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11158                 if (connector->new_encoder &&
11159                     connector->new_encoder->new_crtc == crtc)
11160                         connector->new_encoder = NULL;
11161         }
11162
11163         for_each_intel_encoder(dev, encoder) {
11164                 if (encoder->new_crtc == crtc)
11165                         encoder->new_crtc = NULL;
11166         }
11167
11168         crtc->new_enabled = false;
11169         crtc->new_config = NULL;
11170 }
11171
11172 static int intel_crtc_set_config(struct drm_mode_set *set)
11173 {
11174         struct drm_device *dev;
11175         struct drm_mode_set save_set;
11176         struct intel_set_config *config;
11177         int ret;
11178
11179         BUG_ON(!set);
11180         BUG_ON(!set->crtc);
11181         BUG_ON(!set->crtc->helper_private);
11182
11183         /* Enforce sane interface api - has been abused by the fb helper. */
11184         BUG_ON(!set->mode && set->fb);
11185         BUG_ON(set->fb && set->num_connectors == 0);
11186
11187         if (set->fb) {
11188                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11189                                 set->crtc->base.id, set->fb->base.id,
11190                                 (int)set->num_connectors, set->x, set->y);
11191         } else {
11192                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11193         }
11194
11195         dev = set->crtc->dev;
11196
11197         ret = -ENOMEM;
11198         config = kzalloc(sizeof(*config), GFP_KERNEL);
11199         if (!config)
11200                 goto out_config;
11201
11202         ret = intel_set_config_save_state(dev, config);
11203         if (ret)
11204                 goto out_config;
11205
11206         save_set.crtc = set->crtc;
11207         save_set.mode = &set->crtc->mode;
11208         save_set.x = set->crtc->x;
11209         save_set.y = set->crtc->y;
11210         save_set.fb = set->crtc->primary->fb;
11211
11212         /* Compute whether we need a full modeset, only an fb base update or no
11213          * change at all. In the future we might also check whether only the
11214          * mode changed, e.g. for LVDS where we only change the panel fitter in
11215          * such cases. */
11216         intel_set_config_compute_mode_changes(set, config);
11217
11218         ret = intel_modeset_stage_output_state(dev, set, config);
11219         if (ret)
11220                 goto fail;
11221
11222         if (config->mode_changed) {
11223                 ret = intel_set_mode(set->crtc, set->mode,
11224                                      set->x, set->y, set->fb);
11225         } else if (config->fb_changed) {
11226                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11227
11228                 intel_crtc_wait_for_pending_flips(set->crtc);
11229
11230                 ret = intel_pipe_set_base(set->crtc,
11231                                           set->x, set->y, set->fb);
11232
11233                 /*
11234                  * We need to make sure the primary plane is re-enabled if it
11235                  * has previously been turned off.
11236                  */
11237                 if (!intel_crtc->primary_enabled && ret == 0) {
11238                         WARN_ON(!intel_crtc->active);
11239                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11240                 }
11241
11242                 /*
11243                  * In the fastboot case this may be our only check of the
11244                  * state after boot.  It would be better to only do it on
11245                  * the first update, but we don't have a nice way of doing that
11246                  * (and really, set_config isn't used much for high freq page
11247                  * flipping, so increasing its cost here shouldn't be a big
11248                  * deal).
11249                  */
11250                 if (i915.fastboot && ret == 0)
11251                         intel_modeset_check_state(set->crtc->dev);
11252         }
11253
11254         if (ret) {
11255                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11256                               set->crtc->base.id, ret);
11257 fail:
11258                 intel_set_config_restore_state(dev, config);
11259
11260                 /*
11261                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11262                  * force the pipe off to avoid oopsing in the modeset code
11263                  * due to fb==NULL. This should only happen during boot since
11264                  * we don't yet reconstruct the FB from the hardware state.
11265                  */
11266                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11267                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11268
11269                 /* Try to restore the config */
11270                 if (config->mode_changed &&
11271                     intel_set_mode(save_set.crtc, save_set.mode,
11272                                    save_set.x, save_set.y, save_set.fb))
11273                         DRM_ERROR("failed to restore config after modeset failure\n");
11274         }
11275
11276 out_config:
11277         intel_set_config_free(config);
11278         return ret;
11279 }
11280
11281 static const struct drm_crtc_funcs intel_crtc_funcs = {
11282         .gamma_set = intel_crtc_gamma_set,
11283         .set_config = intel_crtc_set_config,
11284         .destroy = intel_crtc_destroy,
11285         .page_flip = intel_crtc_page_flip,
11286 };
11287
11288 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11289                                       struct intel_shared_dpll *pll,
11290                                       struct intel_dpll_hw_state *hw_state)
11291 {
11292         uint32_t val;
11293
11294         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11295                 return false;
11296
11297         val = I915_READ(PCH_DPLL(pll->id));
11298         hw_state->dpll = val;
11299         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11300         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11301
11302         return val & DPLL_VCO_ENABLE;
11303 }
11304
11305 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11306                                   struct intel_shared_dpll *pll)
11307 {
11308         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11309         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11310 }
11311
11312 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11313                                 struct intel_shared_dpll *pll)
11314 {
11315         /* PCH refclock must be enabled first */
11316         ibx_assert_pch_refclk_enabled(dev_priv);
11317
11318         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11319
11320         /* Wait for the clocks to stabilize. */
11321         POSTING_READ(PCH_DPLL(pll->id));
11322         udelay(150);
11323
11324         /* The pixel multiplier can only be updated once the
11325          * DPLL is enabled and the clocks are stable.
11326          *
11327          * So write it again.
11328          */
11329         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11330         POSTING_READ(PCH_DPLL(pll->id));
11331         udelay(200);
11332 }
11333
11334 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11335                                  struct intel_shared_dpll *pll)
11336 {
11337         struct drm_device *dev = dev_priv->dev;
11338         struct intel_crtc *crtc;
11339
11340         /* Make sure no transcoder isn't still depending on us. */
11341         for_each_intel_crtc(dev, crtc) {
11342                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11343                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11344         }
11345
11346         I915_WRITE(PCH_DPLL(pll->id), 0);
11347         POSTING_READ(PCH_DPLL(pll->id));
11348         udelay(200);
11349 }
11350
11351 static char *ibx_pch_dpll_names[] = {
11352         "PCH DPLL A",
11353         "PCH DPLL B",
11354 };
11355
11356 static void ibx_pch_dpll_init(struct drm_device *dev)
11357 {
11358         struct drm_i915_private *dev_priv = dev->dev_private;
11359         int i;
11360
11361         dev_priv->num_shared_dpll = 2;
11362
11363         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11364                 dev_priv->shared_dplls[i].id = i;
11365                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11366                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11367                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11368                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11369                 dev_priv->shared_dplls[i].get_hw_state =
11370                         ibx_pch_dpll_get_hw_state;
11371         }
11372 }
11373
11374 static void intel_shared_dpll_init(struct drm_device *dev)
11375 {
11376         struct drm_i915_private *dev_priv = dev->dev_private;
11377
11378         if (HAS_DDI(dev))
11379                 intel_ddi_pll_init(dev);
11380         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11381                 ibx_pch_dpll_init(dev);
11382         else
11383                 dev_priv->num_shared_dpll = 0;
11384
11385         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11386 }
11387
11388 static int
11389 intel_primary_plane_disable(struct drm_plane *plane)
11390 {
11391         struct drm_device *dev = plane->dev;
11392         struct intel_crtc *intel_crtc;
11393
11394         if (!plane->fb)
11395                 return 0;
11396
11397         BUG_ON(!plane->crtc);
11398
11399         intel_crtc = to_intel_crtc(plane->crtc);
11400
11401         /*
11402          * Even though we checked plane->fb above, it's still possible that
11403          * the primary plane has been implicitly disabled because the crtc
11404          * coordinates given weren't visible, or because we detected
11405          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11406          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11407          * In either case, we need to unpin the FB and let the fb pointer get
11408          * updated, but otherwise we don't need to touch the hardware.
11409          */
11410         if (!intel_crtc->primary_enabled)
11411                 goto disable_unpin;
11412
11413         intel_crtc_wait_for_pending_flips(plane->crtc);
11414         intel_disable_primary_hw_plane(plane, plane->crtc);
11415
11416 disable_unpin:
11417         mutex_lock(&dev->struct_mutex);
11418         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11419                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11420         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11421         mutex_unlock(&dev->struct_mutex);
11422         plane->fb = NULL;
11423
11424         return 0;
11425 }
11426
11427 static int
11428 intel_check_primary_plane(struct drm_plane *plane,
11429                           struct intel_plane_state *state)
11430 {
11431         struct drm_crtc *crtc = state->crtc;
11432         struct drm_framebuffer *fb = state->fb;
11433         struct drm_rect *dest = &state->dst;
11434         struct drm_rect *src = &state->src;
11435         const struct drm_rect *clip = &state->clip;
11436
11437         return drm_plane_helper_check_update(plane, crtc, fb,
11438                                              src, dest, clip,
11439                                              DRM_PLANE_HELPER_NO_SCALING,
11440                                              DRM_PLANE_HELPER_NO_SCALING,
11441                                              false, true, &state->visible);
11442 }
11443
11444 static int
11445 intel_prepare_primary_plane(struct drm_plane *plane,
11446                             struct intel_plane_state *state)
11447 {
11448         struct drm_crtc *crtc = state->crtc;
11449         struct drm_framebuffer *fb = state->fb;
11450         struct drm_device *dev = crtc->dev;
11451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11452         enum pipe pipe = intel_crtc->pipe;
11453         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11454         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11455         int ret;
11456
11457         intel_crtc_wait_for_pending_flips(crtc);
11458
11459         if (intel_crtc_has_pending_flip(crtc)) {
11460                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11461                 return -EBUSY;
11462         }
11463
11464         if (old_obj != obj) {
11465                 mutex_lock(&dev->struct_mutex);
11466                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11467                 if (ret == 0)
11468                         i915_gem_track_fb(old_obj, obj,
11469                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11470                 mutex_unlock(&dev->struct_mutex);
11471                 if (ret != 0) {
11472                         DRM_DEBUG_KMS("pin & fence failed\n");
11473                         return ret;
11474                 }
11475         }
11476
11477         return 0;
11478 }
11479
11480 static void
11481 intel_commit_primary_plane(struct drm_plane *plane,
11482                            struct intel_plane_state *state)
11483 {
11484         struct drm_crtc *crtc = state->crtc;
11485         struct drm_framebuffer *fb = state->fb;
11486         struct drm_device *dev = crtc->dev;
11487         struct drm_i915_private *dev_priv = dev->dev_private;
11488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11489         enum pipe pipe = intel_crtc->pipe;
11490         struct drm_framebuffer *old_fb = plane->fb;
11491         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11492         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11493         struct intel_plane *intel_plane = to_intel_plane(plane);
11494         struct drm_rect *src = &state->src;
11495
11496         crtc->primary->fb = fb;
11497         crtc->x = src->x1;
11498         crtc->y = src->y1;
11499
11500         intel_plane->crtc_x = state->orig_dst.x1;
11501         intel_plane->crtc_y = state->orig_dst.y1;
11502         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11503         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11504         intel_plane->src_x = state->orig_src.x1;
11505         intel_plane->src_y = state->orig_src.y1;
11506         intel_plane->src_w = drm_rect_width(&state->orig_src);
11507         intel_plane->src_h = drm_rect_height(&state->orig_src);
11508         intel_plane->obj = obj;
11509
11510         if (intel_crtc->active) {
11511                 /*
11512                  * FBC does not work on some platforms for rotated
11513                  * planes, so disable it when rotation is not 0 and
11514                  * update it when rotation is set back to 0.
11515                  *
11516                  * FIXME: This is redundant with the fbc update done in
11517                  * the primary plane enable function except that that
11518                  * one is done too late. We eventually need to unify
11519                  * this.
11520                  */
11521                 if (intel_crtc->primary_enabled &&
11522                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11523                     dev_priv->fbc.plane == intel_crtc->plane &&
11524                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11525                         intel_disable_fbc(dev);
11526                 }
11527
11528                 if (state->visible) {
11529                         bool was_enabled = intel_crtc->primary_enabled;
11530
11531                         /* FIXME: kill this fastboot hack */
11532                         intel_update_pipe_size(intel_crtc);
11533
11534                         intel_crtc->primary_enabled = true;
11535
11536                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11537                                         crtc->x, crtc->y);
11538
11539                         /*
11540                          * BDW signals flip done immediately if the plane
11541                          * is disabled, even if the plane enable is already
11542                          * armed to occur at the next vblank :(
11543                          */
11544                         if (IS_BROADWELL(dev) && !was_enabled)
11545                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11546                 } else {
11547                         /*
11548                          * If clipping results in a non-visible primary plane,
11549                          * we'll disable the primary plane.  Note that this is
11550                          * a bit different than what happens if userspace
11551                          * explicitly disables the plane by passing fb=0
11552                          * because plane->fb still gets set and pinned.
11553                          */
11554                         intel_disable_primary_hw_plane(plane, crtc);
11555                 }
11556
11557                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11558
11559                 mutex_lock(&dev->struct_mutex);
11560                 intel_update_fbc(dev);
11561                 mutex_unlock(&dev->struct_mutex);
11562         }
11563
11564         if (old_fb && old_fb != fb) {
11565                 if (intel_crtc->active)
11566                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11567
11568                 mutex_lock(&dev->struct_mutex);
11569                 intel_unpin_fb_obj(old_obj);
11570                 mutex_unlock(&dev->struct_mutex);
11571         }
11572 }
11573
11574 static int
11575 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11576                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11577                              unsigned int crtc_w, unsigned int crtc_h,
11578                              uint32_t src_x, uint32_t src_y,
11579                              uint32_t src_w, uint32_t src_h)
11580 {
11581         struct intel_plane_state state;
11582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11583         int ret;
11584
11585         state.crtc = crtc;
11586         state.fb = fb;
11587
11588         /* sample coordinates in 16.16 fixed point */
11589         state.src.x1 = src_x;
11590         state.src.x2 = src_x + src_w;
11591         state.src.y1 = src_y;
11592         state.src.y2 = src_y + src_h;
11593
11594         /* integer pixels */
11595         state.dst.x1 = crtc_x;
11596         state.dst.x2 = crtc_x + crtc_w;
11597         state.dst.y1 = crtc_y;
11598         state.dst.y2 = crtc_y + crtc_h;
11599
11600         state.clip.x1 = 0;
11601         state.clip.y1 = 0;
11602         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11603         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11604
11605         state.orig_src = state.src;
11606         state.orig_dst = state.dst;
11607
11608         ret = intel_check_primary_plane(plane, &state);
11609         if (ret)
11610                 return ret;
11611
11612         ret = intel_prepare_primary_plane(plane, &state);
11613         if (ret)
11614                 return ret;
11615
11616         intel_commit_primary_plane(plane, &state);
11617
11618         return 0;
11619 }
11620
11621 /* Common destruction function for both primary and cursor planes */
11622 static void intel_plane_destroy(struct drm_plane *plane)
11623 {
11624         struct intel_plane *intel_plane = to_intel_plane(plane);
11625         drm_plane_cleanup(plane);
11626         kfree(intel_plane);
11627 }
11628
11629 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11630         .update_plane = intel_primary_plane_setplane,
11631         .disable_plane = intel_primary_plane_disable,
11632         .destroy = intel_plane_destroy,
11633         .set_property = intel_plane_set_property
11634 };
11635
11636 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11637                                                     int pipe)
11638 {
11639         struct intel_plane *primary;
11640         const uint32_t *intel_primary_formats;
11641         int num_formats;
11642
11643         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11644         if (primary == NULL)
11645                 return NULL;
11646
11647         primary->can_scale = false;
11648         primary->max_downscale = 1;
11649         primary->pipe = pipe;
11650         primary->plane = pipe;
11651         primary->rotation = BIT(DRM_ROTATE_0);
11652         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11653                 primary->plane = !pipe;
11654
11655         if (INTEL_INFO(dev)->gen <= 3) {
11656                 intel_primary_formats = intel_primary_formats_gen2;
11657                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11658         } else {
11659                 intel_primary_formats = intel_primary_formats_gen4;
11660                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11661         }
11662
11663         drm_universal_plane_init(dev, &primary->base, 0,
11664                                  &intel_primary_plane_funcs,
11665                                  intel_primary_formats, num_formats,
11666                                  DRM_PLANE_TYPE_PRIMARY);
11667
11668         if (INTEL_INFO(dev)->gen >= 4) {
11669                 if (!dev->mode_config.rotation_property)
11670                         dev->mode_config.rotation_property =
11671                                 drm_mode_create_rotation_property(dev,
11672                                                         BIT(DRM_ROTATE_0) |
11673                                                         BIT(DRM_ROTATE_180));
11674                 if (dev->mode_config.rotation_property)
11675                         drm_object_attach_property(&primary->base.base,
11676                                 dev->mode_config.rotation_property,
11677                                 primary->rotation);
11678         }
11679
11680         return &primary->base;
11681 }
11682
11683 static int
11684 intel_cursor_plane_disable(struct drm_plane *plane)
11685 {
11686         if (!plane->fb)
11687                 return 0;
11688
11689         BUG_ON(!plane->crtc);
11690
11691         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11692 }
11693
11694 static int
11695 intel_check_cursor_plane(struct drm_plane *plane,
11696                          struct intel_plane_state *state)
11697 {
11698         struct drm_crtc *crtc = state->crtc;
11699         struct drm_device *dev = crtc->dev;
11700         struct drm_framebuffer *fb = state->fb;
11701         struct drm_rect *dest = &state->dst;
11702         struct drm_rect *src = &state->src;
11703         const struct drm_rect *clip = &state->clip;
11704         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11705         int crtc_w, crtc_h;
11706         unsigned stride;
11707         int ret;
11708
11709         ret = drm_plane_helper_check_update(plane, crtc, fb,
11710                                             src, dest, clip,
11711                                             DRM_PLANE_HELPER_NO_SCALING,
11712                                             DRM_PLANE_HELPER_NO_SCALING,
11713                                             true, true, &state->visible);
11714         if (ret)
11715                 return ret;
11716
11717
11718         /* if we want to turn off the cursor ignore width and height */
11719         if (!obj)
11720                 return 0;
11721
11722         /* Check for which cursor types we support */
11723         crtc_w = drm_rect_width(&state->orig_dst);
11724         crtc_h = drm_rect_height(&state->orig_dst);
11725         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11726                 DRM_DEBUG("Cursor dimension not supported\n");
11727                 return -EINVAL;
11728         }
11729
11730         stride = roundup_pow_of_two(crtc_w) * 4;
11731         if (obj->base.size < stride * crtc_h) {
11732                 DRM_DEBUG_KMS("buffer is too small\n");
11733                 return -ENOMEM;
11734         }
11735
11736         if (fb == crtc->cursor->fb)
11737                 return 0;
11738
11739         /* we only need to pin inside GTT if cursor is non-phy */
11740         mutex_lock(&dev->struct_mutex);
11741         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11742                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11743                 ret = -EINVAL;
11744         }
11745         mutex_unlock(&dev->struct_mutex);
11746
11747         return ret;
11748 }
11749
11750 static int
11751 intel_commit_cursor_plane(struct drm_plane *plane,
11752                           struct intel_plane_state *state)
11753 {
11754         struct drm_crtc *crtc = state->crtc;
11755         struct drm_framebuffer *fb = state->fb;
11756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11757         struct intel_plane *intel_plane = to_intel_plane(plane);
11758         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11759         struct drm_i915_gem_object *obj = intel_fb->obj;
11760         int crtc_w, crtc_h;
11761
11762         crtc->cursor_x = state->orig_dst.x1;
11763         crtc->cursor_y = state->orig_dst.y1;
11764
11765         intel_plane->crtc_x = state->orig_dst.x1;
11766         intel_plane->crtc_y = state->orig_dst.y1;
11767         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11768         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11769         intel_plane->src_x = state->orig_src.x1;
11770         intel_plane->src_y = state->orig_src.y1;
11771         intel_plane->src_w = drm_rect_width(&state->orig_src);
11772         intel_plane->src_h = drm_rect_height(&state->orig_src);
11773         intel_plane->obj = obj;
11774
11775         if (fb != crtc->cursor->fb) {
11776                 crtc_w = drm_rect_width(&state->orig_dst);
11777                 crtc_h = drm_rect_height(&state->orig_dst);
11778                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11779         } else {
11780                 intel_crtc_update_cursor(crtc, state->visible);
11781
11782                 intel_frontbuffer_flip(crtc->dev,
11783                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11784
11785                 return 0;
11786         }
11787 }
11788
11789 static int
11790 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11791                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11792                           unsigned int crtc_w, unsigned int crtc_h,
11793                           uint32_t src_x, uint32_t src_y,
11794                           uint32_t src_w, uint32_t src_h)
11795 {
11796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11797         struct intel_plane_state state;
11798         int ret;
11799
11800         state.crtc = crtc;
11801         state.fb = fb;
11802
11803         /* sample coordinates in 16.16 fixed point */
11804         state.src.x1 = src_x;
11805         state.src.x2 = src_x + src_w;
11806         state.src.y1 = src_y;
11807         state.src.y2 = src_y + src_h;
11808
11809         /* integer pixels */
11810         state.dst.x1 = crtc_x;
11811         state.dst.x2 = crtc_x + crtc_w;
11812         state.dst.y1 = crtc_y;
11813         state.dst.y2 = crtc_y + crtc_h;
11814
11815         state.clip.x1 = 0;
11816         state.clip.y1 = 0;
11817         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11818         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11819
11820         state.orig_src = state.src;
11821         state.orig_dst = state.dst;
11822
11823         ret = intel_check_cursor_plane(plane, &state);
11824         if (ret)
11825                 return ret;
11826
11827         return intel_commit_cursor_plane(plane, &state);
11828 }
11829
11830 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11831         .update_plane = intel_cursor_plane_update,
11832         .disable_plane = intel_cursor_plane_disable,
11833         .destroy = intel_plane_destroy,
11834         .set_property = intel_plane_set_property,
11835 };
11836
11837 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11838                                                    int pipe)
11839 {
11840         struct intel_plane *cursor;
11841
11842         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11843         if (cursor == NULL)
11844                 return NULL;
11845
11846         cursor->can_scale = false;
11847         cursor->max_downscale = 1;
11848         cursor->pipe = pipe;
11849         cursor->plane = pipe;
11850         cursor->rotation = BIT(DRM_ROTATE_0);
11851
11852         drm_universal_plane_init(dev, &cursor->base, 0,
11853                                  &intel_cursor_plane_funcs,
11854                                  intel_cursor_formats,
11855                                  ARRAY_SIZE(intel_cursor_formats),
11856                                  DRM_PLANE_TYPE_CURSOR);
11857
11858         if (INTEL_INFO(dev)->gen >= 4) {
11859                 if (!dev->mode_config.rotation_property)
11860                         dev->mode_config.rotation_property =
11861                                 drm_mode_create_rotation_property(dev,
11862                                                         BIT(DRM_ROTATE_0) |
11863                                                         BIT(DRM_ROTATE_180));
11864                 if (dev->mode_config.rotation_property)
11865                         drm_object_attach_property(&cursor->base.base,
11866                                 dev->mode_config.rotation_property,
11867                                 cursor->rotation);
11868         }
11869
11870         return &cursor->base;
11871 }
11872
11873 static void intel_crtc_init(struct drm_device *dev, int pipe)
11874 {
11875         struct drm_i915_private *dev_priv = dev->dev_private;
11876         struct intel_crtc *intel_crtc;
11877         struct drm_plane *primary = NULL;
11878         struct drm_plane *cursor = NULL;
11879         int i, ret;
11880
11881         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11882         if (intel_crtc == NULL)
11883                 return;
11884
11885         primary = intel_primary_plane_create(dev, pipe);
11886         if (!primary)
11887                 goto fail;
11888
11889         cursor = intel_cursor_plane_create(dev, pipe);
11890         if (!cursor)
11891                 goto fail;
11892
11893         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11894                                         cursor, &intel_crtc_funcs);
11895         if (ret)
11896                 goto fail;
11897
11898         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11899         for (i = 0; i < 256; i++) {
11900                 intel_crtc->lut_r[i] = i;
11901                 intel_crtc->lut_g[i] = i;
11902                 intel_crtc->lut_b[i] = i;
11903         }
11904
11905         /*
11906          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11907          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11908          */
11909         intel_crtc->pipe = pipe;
11910         intel_crtc->plane = pipe;
11911         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11912                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11913                 intel_crtc->plane = !pipe;
11914         }
11915
11916         intel_crtc->cursor_base = ~0;
11917         intel_crtc->cursor_cntl = ~0;
11918         intel_crtc->cursor_size = ~0;
11919
11920         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11921                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11922         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11923         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11924
11925         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11926
11927         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11928         return;
11929
11930 fail:
11931         if (primary)
11932                 drm_plane_cleanup(primary);
11933         if (cursor)
11934                 drm_plane_cleanup(cursor);
11935         kfree(intel_crtc);
11936 }
11937
11938 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11939 {
11940         struct drm_encoder *encoder = connector->base.encoder;
11941         struct drm_device *dev = connector->base.dev;
11942
11943         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11944
11945         if (!encoder)
11946                 return INVALID_PIPE;
11947
11948         return to_intel_crtc(encoder->crtc)->pipe;
11949 }
11950
11951 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11952                                 struct drm_file *file)
11953 {
11954         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11955         struct drm_crtc *drmmode_crtc;
11956         struct intel_crtc *crtc;
11957
11958         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11959                 return -ENODEV;
11960
11961         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11962
11963         if (!drmmode_crtc) {
11964                 DRM_ERROR("no such CRTC id\n");
11965                 return -ENOENT;
11966         }
11967
11968         crtc = to_intel_crtc(drmmode_crtc);
11969         pipe_from_crtc_id->pipe = crtc->pipe;
11970
11971         return 0;
11972 }
11973
11974 static int intel_encoder_clones(struct intel_encoder *encoder)
11975 {
11976         struct drm_device *dev = encoder->base.dev;
11977         struct intel_encoder *source_encoder;
11978         int index_mask = 0;
11979         int entry = 0;
11980
11981         for_each_intel_encoder(dev, source_encoder) {
11982                 if (encoders_cloneable(encoder, source_encoder))
11983                         index_mask |= (1 << entry);
11984
11985                 entry++;
11986         }
11987
11988         return index_mask;
11989 }
11990
11991 static bool has_edp_a(struct drm_device *dev)
11992 {
11993         struct drm_i915_private *dev_priv = dev->dev_private;
11994
11995         if (!IS_MOBILE(dev))
11996                 return false;
11997
11998         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11999                 return false;
12000
12001         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12002                 return false;
12003
12004         return true;
12005 }
12006
12007 const char *intel_output_name(int output)
12008 {
12009         static const char *names[] = {
12010                 [INTEL_OUTPUT_UNUSED] = "Unused",
12011                 [INTEL_OUTPUT_ANALOG] = "Analog",
12012                 [INTEL_OUTPUT_DVO] = "DVO",
12013                 [INTEL_OUTPUT_SDVO] = "SDVO",
12014                 [INTEL_OUTPUT_LVDS] = "LVDS",
12015                 [INTEL_OUTPUT_TVOUT] = "TV",
12016                 [INTEL_OUTPUT_HDMI] = "HDMI",
12017                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12018                 [INTEL_OUTPUT_EDP] = "eDP",
12019                 [INTEL_OUTPUT_DSI] = "DSI",
12020                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12021         };
12022
12023         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12024                 return "Invalid";
12025
12026         return names[output];
12027 }
12028
12029 static bool intel_crt_present(struct drm_device *dev)
12030 {
12031         struct drm_i915_private *dev_priv = dev->dev_private;
12032
12033         if (INTEL_INFO(dev)->gen >= 9)
12034                 return false;
12035
12036         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12037                 return false;
12038
12039         if (IS_CHERRYVIEW(dev))
12040                 return false;
12041
12042         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12043                 return false;
12044
12045         return true;
12046 }
12047
12048 static void intel_setup_outputs(struct drm_device *dev)
12049 {
12050         struct drm_i915_private *dev_priv = dev->dev_private;
12051         struct intel_encoder *encoder;
12052         bool dpd_is_edp = false;
12053
12054         intel_lvds_init(dev);
12055
12056         if (intel_crt_present(dev))
12057                 intel_crt_init(dev);
12058
12059         if (HAS_DDI(dev)) {
12060                 int found;
12061
12062                 /* Haswell uses DDI functions to detect digital outputs */
12063                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12064                 /* DDI A only supports eDP */
12065                 if (found)
12066                         intel_ddi_init(dev, PORT_A);
12067
12068                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12069                  * register */
12070                 found = I915_READ(SFUSE_STRAP);
12071
12072                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12073                         intel_ddi_init(dev, PORT_B);
12074                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12075                         intel_ddi_init(dev, PORT_C);
12076                 if (found & SFUSE_STRAP_DDID_DETECTED)
12077                         intel_ddi_init(dev, PORT_D);
12078         } else if (HAS_PCH_SPLIT(dev)) {
12079                 int found;
12080                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12081
12082                 if (has_edp_a(dev))
12083                         intel_dp_init(dev, DP_A, PORT_A);
12084
12085                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12086                         /* PCH SDVOB multiplex with HDMIB */
12087                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12088                         if (!found)
12089                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12090                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12091                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12092                 }
12093
12094                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12095                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12096
12097                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12098                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12099
12100                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12101                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12102
12103                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12104                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12105         } else if (IS_VALLEYVIEW(dev)) {
12106                 /*
12107                  * The DP_DETECTED bit is the latched state of the DDC
12108                  * SDA pin at boot. However since eDP doesn't require DDC
12109                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12110                  * eDP ports may have been muxed to an alternate function.
12111                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12112                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12113                  * detect eDP ports.
12114                  */
12115                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12116                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12117                                         PORT_B);
12118                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12119                     intel_dp_is_edp(dev, PORT_B))
12120                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12121
12122                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12123                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12124                                         PORT_C);
12125                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12126                     intel_dp_is_edp(dev, PORT_C))
12127                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12128
12129                 if (IS_CHERRYVIEW(dev)) {
12130                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12131                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12132                                                 PORT_D);
12133                         /* eDP not supported on port D, so don't check VBT */
12134                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12135                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12136                 }
12137
12138                 intel_dsi_init(dev);
12139         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12140                 bool found = false;
12141
12142                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12143                         DRM_DEBUG_KMS("probing SDVOB\n");
12144                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12145                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12146                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12147                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12148                         }
12149
12150                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12151                                 intel_dp_init(dev, DP_B, PORT_B);
12152                 }
12153
12154                 /* Before G4X SDVOC doesn't have its own detect register */
12155
12156                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12157                         DRM_DEBUG_KMS("probing SDVOC\n");
12158                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12159                 }
12160
12161                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12162
12163                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12164                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12165                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12166                         }
12167                         if (SUPPORTS_INTEGRATED_DP(dev))
12168                                 intel_dp_init(dev, DP_C, PORT_C);
12169                 }
12170
12171                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12172                     (I915_READ(DP_D) & DP_DETECTED))
12173                         intel_dp_init(dev, DP_D, PORT_D);
12174         } else if (IS_GEN2(dev))
12175                 intel_dvo_init(dev);
12176
12177         if (SUPPORTS_TV(dev))
12178                 intel_tv_init(dev);
12179
12180         intel_edp_psr_init(dev);
12181
12182         for_each_intel_encoder(dev, encoder) {
12183                 encoder->base.possible_crtcs = encoder->crtc_mask;
12184                 encoder->base.possible_clones =
12185                         intel_encoder_clones(encoder);
12186         }
12187
12188         intel_init_pch_refclk(dev);
12189
12190         drm_helper_move_panel_connectors_to_head(dev);
12191 }
12192
12193 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12194 {
12195         struct drm_device *dev = fb->dev;
12196         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12197
12198         drm_framebuffer_cleanup(fb);
12199         mutex_lock(&dev->struct_mutex);
12200         WARN_ON(!intel_fb->obj->framebuffer_references--);
12201         drm_gem_object_unreference(&intel_fb->obj->base);
12202         mutex_unlock(&dev->struct_mutex);
12203         kfree(intel_fb);
12204 }
12205
12206 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12207                                                 struct drm_file *file,
12208                                                 unsigned int *handle)
12209 {
12210         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12211         struct drm_i915_gem_object *obj = intel_fb->obj;
12212
12213         return drm_gem_handle_create(file, &obj->base, handle);
12214 }
12215
12216 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12217         .destroy = intel_user_framebuffer_destroy,
12218         .create_handle = intel_user_framebuffer_create_handle,
12219 };
12220
12221 static int intel_framebuffer_init(struct drm_device *dev,
12222                                   struct intel_framebuffer *intel_fb,
12223                                   struct drm_mode_fb_cmd2 *mode_cmd,
12224                                   struct drm_i915_gem_object *obj)
12225 {
12226         int aligned_height;
12227         int pitch_limit;
12228         int ret;
12229
12230         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12231
12232         if (obj->tiling_mode == I915_TILING_Y) {
12233                 DRM_DEBUG("hardware does not support tiling Y\n");
12234                 return -EINVAL;
12235         }
12236
12237         if (mode_cmd->pitches[0] & 63) {
12238                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12239                           mode_cmd->pitches[0]);
12240                 return -EINVAL;
12241         }
12242
12243         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12244                 pitch_limit = 32*1024;
12245         } else if (INTEL_INFO(dev)->gen >= 4) {
12246                 if (obj->tiling_mode)
12247                         pitch_limit = 16*1024;
12248                 else
12249                         pitch_limit = 32*1024;
12250         } else if (INTEL_INFO(dev)->gen >= 3) {
12251                 if (obj->tiling_mode)
12252                         pitch_limit = 8*1024;
12253                 else
12254                         pitch_limit = 16*1024;
12255         } else
12256                 /* XXX DSPC is limited to 4k tiled */
12257                 pitch_limit = 8*1024;
12258
12259         if (mode_cmd->pitches[0] > pitch_limit) {
12260                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12261                           obj->tiling_mode ? "tiled" : "linear",
12262                           mode_cmd->pitches[0], pitch_limit);
12263                 return -EINVAL;
12264         }
12265
12266         if (obj->tiling_mode != I915_TILING_NONE &&
12267             mode_cmd->pitches[0] != obj->stride) {
12268                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12269                           mode_cmd->pitches[0], obj->stride);
12270                 return -EINVAL;
12271         }
12272
12273         /* Reject formats not supported by any plane early. */
12274         switch (mode_cmd->pixel_format) {
12275         case DRM_FORMAT_C8:
12276         case DRM_FORMAT_RGB565:
12277         case DRM_FORMAT_XRGB8888:
12278         case DRM_FORMAT_ARGB8888:
12279                 break;
12280         case DRM_FORMAT_XRGB1555:
12281         case DRM_FORMAT_ARGB1555:
12282                 if (INTEL_INFO(dev)->gen > 3) {
12283                         DRM_DEBUG("unsupported pixel format: %s\n",
12284                                   drm_get_format_name(mode_cmd->pixel_format));
12285                         return -EINVAL;
12286                 }
12287                 break;
12288         case DRM_FORMAT_XBGR8888:
12289         case DRM_FORMAT_ABGR8888:
12290         case DRM_FORMAT_XRGB2101010:
12291         case DRM_FORMAT_ARGB2101010:
12292         case DRM_FORMAT_XBGR2101010:
12293         case DRM_FORMAT_ABGR2101010:
12294                 if (INTEL_INFO(dev)->gen < 4) {
12295                         DRM_DEBUG("unsupported pixel format: %s\n",
12296                                   drm_get_format_name(mode_cmd->pixel_format));
12297                         return -EINVAL;
12298                 }
12299                 break;
12300         case DRM_FORMAT_YUYV:
12301         case DRM_FORMAT_UYVY:
12302         case DRM_FORMAT_YVYU:
12303         case DRM_FORMAT_VYUY:
12304                 if (INTEL_INFO(dev)->gen < 5) {
12305                         DRM_DEBUG("unsupported pixel format: %s\n",
12306                                   drm_get_format_name(mode_cmd->pixel_format));
12307                         return -EINVAL;
12308                 }
12309                 break;
12310         default:
12311                 DRM_DEBUG("unsupported pixel format: %s\n",
12312                           drm_get_format_name(mode_cmd->pixel_format));
12313                 return -EINVAL;
12314         }
12315
12316         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12317         if (mode_cmd->offsets[0] != 0)
12318                 return -EINVAL;
12319
12320         aligned_height = intel_align_height(dev, mode_cmd->height,
12321                                             obj->tiling_mode);
12322         /* FIXME drm helper for size checks (especially planar formats)? */
12323         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12324                 return -EINVAL;
12325
12326         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12327         intel_fb->obj = obj;
12328         intel_fb->obj->framebuffer_references++;
12329
12330         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12331         if (ret) {
12332                 DRM_ERROR("framebuffer init failed %d\n", ret);
12333                 return ret;
12334         }
12335
12336         return 0;
12337 }
12338
12339 static struct drm_framebuffer *
12340 intel_user_framebuffer_create(struct drm_device *dev,
12341                               struct drm_file *filp,
12342                               struct drm_mode_fb_cmd2 *mode_cmd)
12343 {
12344         struct drm_i915_gem_object *obj;
12345
12346         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12347                                                 mode_cmd->handles[0]));
12348         if (&obj->base == NULL)
12349                 return ERR_PTR(-ENOENT);
12350
12351         return intel_framebuffer_create(dev, mode_cmd, obj);
12352 }
12353
12354 #ifndef CONFIG_DRM_I915_FBDEV
12355 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12356 {
12357 }
12358 #endif
12359
12360 static const struct drm_mode_config_funcs intel_mode_funcs = {
12361         .fb_create = intel_user_framebuffer_create,
12362         .output_poll_changed = intel_fbdev_output_poll_changed,
12363 };
12364
12365 /* Set up chip specific display functions */
12366 static void intel_init_display(struct drm_device *dev)
12367 {
12368         struct drm_i915_private *dev_priv = dev->dev_private;
12369
12370         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12371                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12372         else if (IS_CHERRYVIEW(dev))
12373                 dev_priv->display.find_dpll = chv_find_best_dpll;
12374         else if (IS_VALLEYVIEW(dev))
12375                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12376         else if (IS_PINEVIEW(dev))
12377                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12378         else
12379                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12380
12381         if (HAS_DDI(dev)) {
12382                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12383                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12384                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12385                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12386                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12387                 dev_priv->display.off = ironlake_crtc_off;
12388                 if (INTEL_INFO(dev)->gen >= 9)
12389                         dev_priv->display.update_primary_plane =
12390                                 skylake_update_primary_plane;
12391                 else
12392                         dev_priv->display.update_primary_plane =
12393                                 ironlake_update_primary_plane;
12394         } else if (HAS_PCH_SPLIT(dev)) {
12395                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12396                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12397                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12398                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12399                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12400                 dev_priv->display.off = ironlake_crtc_off;
12401                 dev_priv->display.update_primary_plane =
12402                         ironlake_update_primary_plane;
12403         } else if (IS_VALLEYVIEW(dev)) {
12404                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12405                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12406                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12407                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12408                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12409                 dev_priv->display.off = i9xx_crtc_off;
12410                 dev_priv->display.update_primary_plane =
12411                         i9xx_update_primary_plane;
12412         } else {
12413                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12414                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12415                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12416                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12417                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12418                 dev_priv->display.off = i9xx_crtc_off;
12419                 dev_priv->display.update_primary_plane =
12420                         i9xx_update_primary_plane;
12421         }
12422
12423         /* Returns the core display clock speed */
12424         if (IS_VALLEYVIEW(dev))
12425                 dev_priv->display.get_display_clock_speed =
12426                         valleyview_get_display_clock_speed;
12427         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12428                 dev_priv->display.get_display_clock_speed =
12429                         i945_get_display_clock_speed;
12430         else if (IS_I915G(dev))
12431                 dev_priv->display.get_display_clock_speed =
12432                         i915_get_display_clock_speed;
12433         else if (IS_I945GM(dev) || IS_845G(dev))
12434                 dev_priv->display.get_display_clock_speed =
12435                         i9xx_misc_get_display_clock_speed;
12436         else if (IS_PINEVIEW(dev))
12437                 dev_priv->display.get_display_clock_speed =
12438                         pnv_get_display_clock_speed;
12439         else if (IS_I915GM(dev))
12440                 dev_priv->display.get_display_clock_speed =
12441                         i915gm_get_display_clock_speed;
12442         else if (IS_I865G(dev))
12443                 dev_priv->display.get_display_clock_speed =
12444                         i865_get_display_clock_speed;
12445         else if (IS_I85X(dev))
12446                 dev_priv->display.get_display_clock_speed =
12447                         i855_get_display_clock_speed;
12448         else /* 852, 830 */
12449                 dev_priv->display.get_display_clock_speed =
12450                         i830_get_display_clock_speed;
12451
12452         if (IS_GEN5(dev)) {
12453                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12454         } else if (IS_GEN6(dev)) {
12455                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12456                 dev_priv->display.modeset_global_resources =
12457                         snb_modeset_global_resources;
12458         } else if (IS_IVYBRIDGE(dev)) {
12459                 /* FIXME: detect B0+ stepping and use auto training */
12460                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12461                 dev_priv->display.modeset_global_resources =
12462                         ivb_modeset_global_resources;
12463         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12464                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12465                 dev_priv->display.modeset_global_resources =
12466                         haswell_modeset_global_resources;
12467         } else if (IS_VALLEYVIEW(dev)) {
12468                 dev_priv->display.modeset_global_resources =
12469                         valleyview_modeset_global_resources;
12470         } else if (INTEL_INFO(dev)->gen >= 9) {
12471                 dev_priv->display.modeset_global_resources =
12472                         haswell_modeset_global_resources;
12473         }
12474
12475         /* Default just returns -ENODEV to indicate unsupported */
12476         dev_priv->display.queue_flip = intel_default_queue_flip;
12477
12478         switch (INTEL_INFO(dev)->gen) {
12479         case 2:
12480                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12481                 break;
12482
12483         case 3:
12484                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12485                 break;
12486
12487         case 4:
12488         case 5:
12489                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12490                 break;
12491
12492         case 6:
12493                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12494                 break;
12495         case 7:
12496         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12497                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12498                 break;
12499         }
12500
12501         intel_panel_init_backlight_funcs(dev);
12502
12503         mutex_init(&dev_priv->pps_mutex);
12504 }
12505
12506 /*
12507  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12508  * resume, or other times.  This quirk makes sure that's the case for
12509  * affected systems.
12510  */
12511 static void quirk_pipea_force(struct drm_device *dev)
12512 {
12513         struct drm_i915_private *dev_priv = dev->dev_private;
12514
12515         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12516         DRM_INFO("applying pipe a force quirk\n");
12517 }
12518
12519 static void quirk_pipeb_force(struct drm_device *dev)
12520 {
12521         struct drm_i915_private *dev_priv = dev->dev_private;
12522
12523         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12524         DRM_INFO("applying pipe b force quirk\n");
12525 }
12526
12527 /*
12528  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12529  */
12530 static void quirk_ssc_force_disable(struct drm_device *dev)
12531 {
12532         struct drm_i915_private *dev_priv = dev->dev_private;
12533         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12534         DRM_INFO("applying lvds SSC disable quirk\n");
12535 }
12536
12537 /*
12538  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12539  * brightness value
12540  */
12541 static void quirk_invert_brightness(struct drm_device *dev)
12542 {
12543         struct drm_i915_private *dev_priv = dev->dev_private;
12544         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12545         DRM_INFO("applying inverted panel brightness quirk\n");
12546 }
12547
12548 /* Some VBT's incorrectly indicate no backlight is present */
12549 static void quirk_backlight_present(struct drm_device *dev)
12550 {
12551         struct drm_i915_private *dev_priv = dev->dev_private;
12552         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12553         DRM_INFO("applying backlight present quirk\n");
12554 }
12555
12556 struct intel_quirk {
12557         int device;
12558         int subsystem_vendor;
12559         int subsystem_device;
12560         void (*hook)(struct drm_device *dev);
12561 };
12562
12563 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12564 struct intel_dmi_quirk {
12565         void (*hook)(struct drm_device *dev);
12566         const struct dmi_system_id (*dmi_id_list)[];
12567 };
12568
12569 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12570 {
12571         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12572         return 1;
12573 }
12574
12575 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12576         {
12577                 .dmi_id_list = &(const struct dmi_system_id[]) {
12578                         {
12579                                 .callback = intel_dmi_reverse_brightness,
12580                                 .ident = "NCR Corporation",
12581                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12582                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12583                                 },
12584                         },
12585                         { }  /* terminating entry */
12586                 },
12587                 .hook = quirk_invert_brightness,
12588         },
12589 };
12590
12591 static struct intel_quirk intel_quirks[] = {
12592         /* HP Mini needs pipe A force quirk (LP: #322104) */
12593         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12594
12595         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12596         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12597
12598         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12599         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12600
12601         /* 830 needs to leave pipe A & dpll A up */
12602         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12603
12604         /* 830 needs to leave pipe B & dpll B up */
12605         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12606
12607         /* Lenovo U160 cannot use SSC on LVDS */
12608         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12609
12610         /* Sony Vaio Y cannot use SSC on LVDS */
12611         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12612
12613         /* Acer Aspire 5734Z must invert backlight brightness */
12614         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12615
12616         /* Acer/eMachines G725 */
12617         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12618
12619         /* Acer/eMachines e725 */
12620         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12621
12622         /* Acer/Packard Bell NCL20 */
12623         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12624
12625         /* Acer Aspire 4736Z */
12626         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12627
12628         /* Acer Aspire 5336 */
12629         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12630
12631         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12632         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12633
12634         /* Acer C720 Chromebook (Core i3 4005U) */
12635         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12636
12637         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12638         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12639
12640         /* HP Chromebook 14 (Celeron 2955U) */
12641         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12642 };
12643
12644 static void intel_init_quirks(struct drm_device *dev)
12645 {
12646         struct pci_dev *d = dev->pdev;
12647         int i;
12648
12649         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12650                 struct intel_quirk *q = &intel_quirks[i];
12651
12652                 if (d->device == q->device &&
12653                     (d->subsystem_vendor == q->subsystem_vendor ||
12654                      q->subsystem_vendor == PCI_ANY_ID) &&
12655                     (d->subsystem_device == q->subsystem_device ||
12656                      q->subsystem_device == PCI_ANY_ID))
12657                         q->hook(dev);
12658         }
12659         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12660                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12661                         intel_dmi_quirks[i].hook(dev);
12662         }
12663 }
12664
12665 /* Disable the VGA plane that we never use */
12666 static void i915_disable_vga(struct drm_device *dev)
12667 {
12668         struct drm_i915_private *dev_priv = dev->dev_private;
12669         u8 sr1;
12670         u32 vga_reg = i915_vgacntrl_reg(dev);
12671
12672         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12673         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12674         outb(SR01, VGA_SR_INDEX);
12675         sr1 = inb(VGA_SR_DATA);
12676         outb(sr1 | 1<<5, VGA_SR_DATA);
12677         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12678         udelay(300);
12679
12680         /*
12681          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12682          * from S3 without preserving (some of?) the other bits.
12683          */
12684         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12685         POSTING_READ(vga_reg);
12686 }
12687
12688 void intel_modeset_init_hw(struct drm_device *dev)
12689 {
12690         intel_prepare_ddi(dev);
12691
12692         if (IS_VALLEYVIEW(dev))
12693                 vlv_update_cdclk(dev);
12694
12695         intel_init_clock_gating(dev);
12696
12697         intel_enable_gt_powersave(dev);
12698 }
12699
12700 void intel_modeset_init(struct drm_device *dev)
12701 {
12702         struct drm_i915_private *dev_priv = dev->dev_private;
12703         int sprite, ret;
12704         enum pipe pipe;
12705         struct intel_crtc *crtc;
12706
12707         drm_mode_config_init(dev);
12708
12709         dev->mode_config.min_width = 0;
12710         dev->mode_config.min_height = 0;
12711
12712         dev->mode_config.preferred_depth = 24;
12713         dev->mode_config.prefer_shadow = 1;
12714
12715         dev->mode_config.funcs = &intel_mode_funcs;
12716
12717         intel_init_quirks(dev);
12718
12719         intel_init_pm(dev);
12720
12721         if (INTEL_INFO(dev)->num_pipes == 0)
12722                 return;
12723
12724         intel_init_display(dev);
12725         intel_init_audio(dev);
12726
12727         if (IS_GEN2(dev)) {
12728                 dev->mode_config.max_width = 2048;
12729                 dev->mode_config.max_height = 2048;
12730         } else if (IS_GEN3(dev)) {
12731                 dev->mode_config.max_width = 4096;
12732                 dev->mode_config.max_height = 4096;
12733         } else {
12734                 dev->mode_config.max_width = 8192;
12735                 dev->mode_config.max_height = 8192;
12736         }
12737
12738         if (IS_845G(dev) || IS_I865G(dev)) {
12739                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12740                 dev->mode_config.cursor_height = 1023;
12741         } else if (IS_GEN2(dev)) {
12742                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12743                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12744         } else {
12745                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12746                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12747         }
12748
12749         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12750
12751         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12752                       INTEL_INFO(dev)->num_pipes,
12753                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12754
12755         for_each_pipe(dev_priv, pipe) {
12756                 intel_crtc_init(dev, pipe);
12757                 for_each_sprite(pipe, sprite) {
12758                         ret = intel_plane_init(dev, pipe, sprite);
12759                         if (ret)
12760                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12761                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12762                 }
12763         }
12764
12765         intel_init_dpio(dev);
12766
12767         intel_shared_dpll_init(dev);
12768
12769         /* save the BIOS value before clobbering it */
12770         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12771         /* Just disable it once at startup */
12772         i915_disable_vga(dev);
12773         intel_setup_outputs(dev);
12774
12775         /* Just in case the BIOS is doing something questionable. */
12776         intel_disable_fbc(dev);
12777
12778         drm_modeset_lock_all(dev);
12779         intel_modeset_setup_hw_state(dev, false);
12780         drm_modeset_unlock_all(dev);
12781
12782         for_each_intel_crtc(dev, crtc) {
12783                 if (!crtc->active)
12784                         continue;
12785
12786                 /*
12787                  * Note that reserving the BIOS fb up front prevents us
12788                  * from stuffing other stolen allocations like the ring
12789                  * on top.  This prevents some ugliness at boot time, and
12790                  * can even allow for smooth boot transitions if the BIOS
12791                  * fb is large enough for the active pipe configuration.
12792                  */
12793                 if (dev_priv->display.get_plane_config) {
12794                         dev_priv->display.get_plane_config(crtc,
12795                                                            &crtc->plane_config);
12796                         /*
12797                          * If the fb is shared between multiple heads, we'll
12798                          * just get the first one.
12799                          */
12800                         intel_find_plane_obj(crtc, &crtc->plane_config);
12801                 }
12802         }
12803 }
12804
12805 static void intel_enable_pipe_a(struct drm_device *dev)
12806 {
12807         struct intel_connector *connector;
12808         struct drm_connector *crt = NULL;
12809         struct intel_load_detect_pipe load_detect_temp;
12810         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12811
12812         /* We can't just switch on the pipe A, we need to set things up with a
12813          * proper mode and output configuration. As a gross hack, enable pipe A
12814          * by enabling the load detect pipe once. */
12815         list_for_each_entry(connector,
12816                             &dev->mode_config.connector_list,
12817                             base.head) {
12818                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12819                         crt = &connector->base;
12820                         break;
12821                 }
12822         }
12823
12824         if (!crt)
12825                 return;
12826
12827         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12828                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12829 }
12830
12831 static bool
12832 intel_check_plane_mapping(struct intel_crtc *crtc)
12833 {
12834         struct drm_device *dev = crtc->base.dev;
12835         struct drm_i915_private *dev_priv = dev->dev_private;
12836         u32 reg, val;
12837
12838         if (INTEL_INFO(dev)->num_pipes == 1)
12839                 return true;
12840
12841         reg = DSPCNTR(!crtc->plane);
12842         val = I915_READ(reg);
12843
12844         if ((val & DISPLAY_PLANE_ENABLE) &&
12845             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12846                 return false;
12847
12848         return true;
12849 }
12850
12851 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12852 {
12853         struct drm_device *dev = crtc->base.dev;
12854         struct drm_i915_private *dev_priv = dev->dev_private;
12855         u32 reg;
12856
12857         /* Clear any frame start delays used for debugging left by the BIOS */
12858         reg = PIPECONF(crtc->config.cpu_transcoder);
12859         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12860
12861         /* restore vblank interrupts to correct state */
12862         if (crtc->active) {
12863                 update_scanline_offset(crtc);
12864                 drm_vblank_on(dev, crtc->pipe);
12865         } else
12866                 drm_vblank_off(dev, crtc->pipe);
12867
12868         /* We need to sanitize the plane -> pipe mapping first because this will
12869          * disable the crtc (and hence change the state) if it is wrong. Note
12870          * that gen4+ has a fixed plane -> pipe mapping.  */
12871         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12872                 struct intel_connector *connector;
12873                 bool plane;
12874
12875                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12876                               crtc->base.base.id);
12877
12878                 /* Pipe has the wrong plane attached and the plane is active.
12879                  * Temporarily change the plane mapping and disable everything
12880                  * ...  */
12881                 plane = crtc->plane;
12882                 crtc->plane = !plane;
12883                 crtc->primary_enabled = true;
12884                 dev_priv->display.crtc_disable(&crtc->base);
12885                 crtc->plane = plane;
12886
12887                 /* ... and break all links. */
12888                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12889                                     base.head) {
12890                         if (connector->encoder->base.crtc != &crtc->base)
12891                                 continue;
12892
12893                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12894                         connector->base.encoder = NULL;
12895                 }
12896                 /* multiple connectors may have the same encoder:
12897                  *  handle them and break crtc link separately */
12898                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12899                                     base.head)
12900                         if (connector->encoder->base.crtc == &crtc->base) {
12901                                 connector->encoder->base.crtc = NULL;
12902                                 connector->encoder->connectors_active = false;
12903                         }
12904
12905                 WARN_ON(crtc->active);
12906                 crtc->base.enabled = false;
12907         }
12908
12909         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12910             crtc->pipe == PIPE_A && !crtc->active) {
12911                 /* BIOS forgot to enable pipe A, this mostly happens after
12912                  * resume. Force-enable the pipe to fix this, the update_dpms
12913                  * call below we restore the pipe to the right state, but leave
12914                  * the required bits on. */
12915                 intel_enable_pipe_a(dev);
12916         }
12917
12918         /* Adjust the state of the output pipe according to whether we
12919          * have active connectors/encoders. */
12920         intel_crtc_update_dpms(&crtc->base);
12921
12922         if (crtc->active != crtc->base.enabled) {
12923                 struct intel_encoder *encoder;
12924
12925                 /* This can happen either due to bugs in the get_hw_state
12926                  * functions or because the pipe is force-enabled due to the
12927                  * pipe A quirk. */
12928                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12929                               crtc->base.base.id,
12930                               crtc->base.enabled ? "enabled" : "disabled",
12931                               crtc->active ? "enabled" : "disabled");
12932
12933                 crtc->base.enabled = crtc->active;
12934
12935                 /* Because we only establish the connector -> encoder ->
12936                  * crtc links if something is active, this means the
12937                  * crtc is now deactivated. Break the links. connector
12938                  * -> encoder links are only establish when things are
12939                  *  actually up, hence no need to break them. */
12940                 WARN_ON(crtc->active);
12941
12942                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12943                         WARN_ON(encoder->connectors_active);
12944                         encoder->base.crtc = NULL;
12945                 }
12946         }
12947
12948         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12949                 /*
12950                  * We start out with underrun reporting disabled to avoid races.
12951                  * For correct bookkeeping mark this on active crtcs.
12952                  *
12953                  * Also on gmch platforms we dont have any hardware bits to
12954                  * disable the underrun reporting. Which means we need to start
12955                  * out with underrun reporting disabled also on inactive pipes,
12956                  * since otherwise we'll complain about the garbage we read when
12957                  * e.g. coming up after runtime pm.
12958                  *
12959                  * No protection against concurrent access is required - at
12960                  * worst a fifo underrun happens which also sets this to false.
12961                  */
12962                 crtc->cpu_fifo_underrun_disabled = true;
12963                 crtc->pch_fifo_underrun_disabled = true;
12964         }
12965 }
12966
12967 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12968 {
12969         struct intel_connector *connector;
12970         struct drm_device *dev = encoder->base.dev;
12971
12972         /* We need to check both for a crtc link (meaning that the
12973          * encoder is active and trying to read from a pipe) and the
12974          * pipe itself being active. */
12975         bool has_active_crtc = encoder->base.crtc &&
12976                 to_intel_crtc(encoder->base.crtc)->active;
12977
12978         if (encoder->connectors_active && !has_active_crtc) {
12979                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12980                               encoder->base.base.id,
12981                               encoder->base.name);
12982
12983                 /* Connector is active, but has no active pipe. This is
12984                  * fallout from our resume register restoring. Disable
12985                  * the encoder manually again. */
12986                 if (encoder->base.crtc) {
12987                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12988                                       encoder->base.base.id,
12989                                       encoder->base.name);
12990                         encoder->disable(encoder);
12991                         if (encoder->post_disable)
12992                                 encoder->post_disable(encoder);
12993                 }
12994                 encoder->base.crtc = NULL;
12995                 encoder->connectors_active = false;
12996
12997                 /* Inconsistent output/port/pipe state happens presumably due to
12998                  * a bug in one of the get_hw_state functions. Or someplace else
12999                  * in our code, like the register restore mess on resume. Clamp
13000                  * things to off as a safer default. */
13001                 list_for_each_entry(connector,
13002                                     &dev->mode_config.connector_list,
13003                                     base.head) {
13004                         if (connector->encoder != encoder)
13005                                 continue;
13006                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13007                         connector->base.encoder = NULL;
13008                 }
13009         }
13010         /* Enabled encoders without active connectors will be fixed in
13011          * the crtc fixup. */
13012 }
13013
13014 void i915_redisable_vga_power_on(struct drm_device *dev)
13015 {
13016         struct drm_i915_private *dev_priv = dev->dev_private;
13017         u32 vga_reg = i915_vgacntrl_reg(dev);
13018
13019         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13020                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13021                 i915_disable_vga(dev);
13022         }
13023 }
13024
13025 void i915_redisable_vga(struct drm_device *dev)
13026 {
13027         struct drm_i915_private *dev_priv = dev->dev_private;
13028
13029         /* This function can be called both from intel_modeset_setup_hw_state or
13030          * at a very early point in our resume sequence, where the power well
13031          * structures are not yet restored. Since this function is at a very
13032          * paranoid "someone might have enabled VGA while we were not looking"
13033          * level, just check if the power well is enabled instead of trying to
13034          * follow the "don't touch the power well if we don't need it" policy
13035          * the rest of the driver uses. */
13036         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13037                 return;
13038
13039         i915_redisable_vga_power_on(dev);
13040 }
13041
13042 static bool primary_get_hw_state(struct intel_crtc *crtc)
13043 {
13044         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13045
13046         if (!crtc->active)
13047                 return false;
13048
13049         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13050 }
13051
13052 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13053 {
13054         struct drm_i915_private *dev_priv = dev->dev_private;
13055         enum pipe pipe;
13056         struct intel_crtc *crtc;
13057         struct intel_encoder *encoder;
13058         struct intel_connector *connector;
13059         int i;
13060
13061         for_each_intel_crtc(dev, crtc) {
13062                 memset(&crtc->config, 0, sizeof(crtc->config));
13063
13064                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13065
13066                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13067                                                                  &crtc->config);
13068
13069                 crtc->base.enabled = crtc->active;
13070                 crtc->primary_enabled = primary_get_hw_state(crtc);
13071
13072                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13073                               crtc->base.base.id,
13074                               crtc->active ? "enabled" : "disabled");
13075         }
13076
13077         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13078                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13079
13080                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13081                 pll->active = 0;
13082                 pll->crtc_mask = 0;
13083                 for_each_intel_crtc(dev, crtc) {
13084                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13085                                 pll->active++;
13086                                 pll->crtc_mask |= 1 << crtc->pipe;
13087                         }
13088                 }
13089
13090                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13091                               pll->name, pll->crtc_mask, pll->on);
13092
13093                 if (pll->crtc_mask)
13094                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13095         }
13096
13097         for_each_intel_encoder(dev, encoder) {
13098                 pipe = 0;
13099
13100                 if (encoder->get_hw_state(encoder, &pipe)) {
13101                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13102                         encoder->base.crtc = &crtc->base;
13103                         encoder->get_config(encoder, &crtc->config);
13104                 } else {
13105                         encoder->base.crtc = NULL;
13106                 }
13107
13108                 encoder->connectors_active = false;
13109                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13110                               encoder->base.base.id,
13111                               encoder->base.name,
13112                               encoder->base.crtc ? "enabled" : "disabled",
13113                               pipe_name(pipe));
13114         }
13115
13116         list_for_each_entry(connector, &dev->mode_config.connector_list,
13117                             base.head) {
13118                 if (connector->get_hw_state(connector)) {
13119                         connector->base.dpms = DRM_MODE_DPMS_ON;
13120                         connector->encoder->connectors_active = true;
13121                         connector->base.encoder = &connector->encoder->base;
13122                 } else {
13123                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13124                         connector->base.encoder = NULL;
13125                 }
13126                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13127                               connector->base.base.id,
13128                               connector->base.name,
13129                               connector->base.encoder ? "enabled" : "disabled");
13130         }
13131 }
13132
13133 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13134  * and i915 state tracking structures. */
13135 void intel_modeset_setup_hw_state(struct drm_device *dev,
13136                                   bool force_restore)
13137 {
13138         struct drm_i915_private *dev_priv = dev->dev_private;
13139         enum pipe pipe;
13140         struct intel_crtc *crtc;
13141         struct intel_encoder *encoder;
13142         int i;
13143
13144         intel_modeset_readout_hw_state(dev);
13145
13146         /*
13147          * Now that we have the config, copy it to each CRTC struct
13148          * Note that this could go away if we move to using crtc_config
13149          * checking everywhere.
13150          */
13151         for_each_intel_crtc(dev, crtc) {
13152                 if (crtc->active && i915.fastboot) {
13153                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13154                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13155                                       crtc->base.base.id);
13156                         drm_mode_debug_printmodeline(&crtc->base.mode);
13157                 }
13158         }
13159
13160         /* HW state is read out, now we need to sanitize this mess. */
13161         for_each_intel_encoder(dev, encoder) {
13162                 intel_sanitize_encoder(encoder);
13163         }
13164
13165         for_each_pipe(dev_priv, pipe) {
13166                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13167                 intel_sanitize_crtc(crtc);
13168                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13169         }
13170
13171         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13172                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13173
13174                 if (!pll->on || pll->active)
13175                         continue;
13176
13177                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13178
13179                 pll->disable(dev_priv, pll);
13180                 pll->on = false;
13181         }
13182
13183         if (HAS_PCH_SPLIT(dev))
13184                 ilk_wm_get_hw_state(dev);
13185
13186         if (force_restore) {
13187                 i915_redisable_vga(dev);
13188
13189                 /*
13190                  * We need to use raw interfaces for restoring state to avoid
13191                  * checking (bogus) intermediate states.
13192                  */
13193                 for_each_pipe(dev_priv, pipe) {
13194                         struct drm_crtc *crtc =
13195                                 dev_priv->pipe_to_crtc_mapping[pipe];
13196
13197                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13198                                          crtc->primary->fb);
13199                 }
13200         } else {
13201                 intel_modeset_update_staged_output_state(dev);
13202         }
13203
13204         intel_modeset_check_state(dev);
13205 }
13206
13207 void intel_modeset_gem_init(struct drm_device *dev)
13208 {
13209         struct drm_crtc *c;
13210         struct drm_i915_gem_object *obj;
13211
13212         mutex_lock(&dev->struct_mutex);
13213         intel_init_gt_powersave(dev);
13214         mutex_unlock(&dev->struct_mutex);
13215
13216         intel_modeset_init_hw(dev);
13217
13218         intel_setup_overlay(dev);
13219
13220         /*
13221          * Make sure any fbs we allocated at startup are properly
13222          * pinned & fenced.  When we do the allocation it's too early
13223          * for this.
13224          */
13225         mutex_lock(&dev->struct_mutex);
13226         for_each_crtc(dev, c) {
13227                 obj = intel_fb_obj(c->primary->fb);
13228                 if (obj == NULL)
13229                         continue;
13230
13231                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13232                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13233                                   to_intel_crtc(c)->pipe);
13234                         drm_framebuffer_unreference(c->primary->fb);
13235                         c->primary->fb = NULL;
13236                 }
13237         }
13238         mutex_unlock(&dev->struct_mutex);
13239 }
13240
13241 void intel_connector_unregister(struct intel_connector *intel_connector)
13242 {
13243         struct drm_connector *connector = &intel_connector->base;
13244
13245         intel_panel_destroy_backlight(connector);
13246         drm_connector_unregister(connector);
13247 }
13248
13249 void intel_modeset_cleanup(struct drm_device *dev)
13250 {
13251         struct drm_i915_private *dev_priv = dev->dev_private;
13252         struct drm_connector *connector;
13253
13254         /*
13255          * Interrupts and polling as the first thing to avoid creating havoc.
13256          * Too much stuff here (turning of rps, connectors, ...) would
13257          * experience fancy races otherwise.
13258          */
13259         intel_irq_uninstall(dev_priv);
13260
13261         /*
13262          * Due to the hpd irq storm handling the hotplug work can re-arm the
13263          * poll handlers. Hence disable polling after hpd handling is shut down.
13264          */
13265         drm_kms_helper_poll_fini(dev);
13266
13267         mutex_lock(&dev->struct_mutex);
13268
13269         intel_unregister_dsm_handler();
13270
13271         intel_disable_fbc(dev);
13272
13273         intel_disable_gt_powersave(dev);
13274
13275         ironlake_teardown_rc6(dev);
13276
13277         mutex_unlock(&dev->struct_mutex);
13278
13279         /* flush any delayed tasks or pending work */
13280         flush_scheduled_work();
13281
13282         /* destroy the backlight and sysfs files before encoders/connectors */
13283         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13284                 struct intel_connector *intel_connector;
13285
13286                 intel_connector = to_intel_connector(connector);
13287                 intel_connector->unregister(intel_connector);
13288         }
13289
13290         drm_mode_config_cleanup(dev);
13291
13292         intel_cleanup_overlay(dev);
13293
13294         mutex_lock(&dev->struct_mutex);
13295         intel_cleanup_gt_powersave(dev);
13296         mutex_unlock(&dev->struct_mutex);
13297 }
13298
13299 /*
13300  * Return which encoder is currently attached for connector.
13301  */
13302 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13303 {
13304         return &intel_attached_encoder(connector)->base;
13305 }
13306
13307 void intel_connector_attach_encoder(struct intel_connector *connector,
13308                                     struct intel_encoder *encoder)
13309 {
13310         connector->encoder = encoder;
13311         drm_mode_connector_attach_encoder(&connector->base,
13312                                           &encoder->base);
13313 }
13314
13315 /*
13316  * set vga decode state - true == enable VGA decode
13317  */
13318 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13319 {
13320         struct drm_i915_private *dev_priv = dev->dev_private;
13321         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13322         u16 gmch_ctrl;
13323
13324         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13325                 DRM_ERROR("failed to read control word\n");
13326                 return -EIO;
13327         }
13328
13329         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13330                 return 0;
13331
13332         if (state)
13333                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13334         else
13335                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13336
13337         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13338                 DRM_ERROR("failed to write control word\n");
13339                 return -EIO;
13340         }
13341
13342         return 0;
13343 }
13344
13345 struct intel_display_error_state {
13346
13347         u32 power_well_driver;
13348
13349         int num_transcoders;
13350
13351         struct intel_cursor_error_state {
13352                 u32 control;
13353                 u32 position;
13354                 u32 base;
13355                 u32 size;
13356         } cursor[I915_MAX_PIPES];
13357
13358         struct intel_pipe_error_state {
13359                 bool power_domain_on;
13360                 u32 source;
13361                 u32 stat;
13362         } pipe[I915_MAX_PIPES];
13363
13364         struct intel_plane_error_state {
13365                 u32 control;
13366                 u32 stride;
13367                 u32 size;
13368                 u32 pos;
13369                 u32 addr;
13370                 u32 surface;
13371                 u32 tile_offset;
13372         } plane[I915_MAX_PIPES];
13373
13374         struct intel_transcoder_error_state {
13375                 bool power_domain_on;
13376                 enum transcoder cpu_transcoder;
13377
13378                 u32 conf;
13379
13380                 u32 htotal;
13381                 u32 hblank;
13382                 u32 hsync;
13383                 u32 vtotal;
13384                 u32 vblank;
13385                 u32 vsync;
13386         } transcoder[4];
13387 };
13388
13389 struct intel_display_error_state *
13390 intel_display_capture_error_state(struct drm_device *dev)
13391 {
13392         struct drm_i915_private *dev_priv = dev->dev_private;
13393         struct intel_display_error_state *error;
13394         int transcoders[] = {
13395                 TRANSCODER_A,
13396                 TRANSCODER_B,
13397                 TRANSCODER_C,
13398                 TRANSCODER_EDP,
13399         };
13400         int i;
13401
13402         if (INTEL_INFO(dev)->num_pipes == 0)
13403                 return NULL;
13404
13405         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13406         if (error == NULL)
13407                 return NULL;
13408
13409         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13410                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13411
13412         for_each_pipe(dev_priv, i) {
13413                 error->pipe[i].power_domain_on =
13414                         __intel_display_power_is_enabled(dev_priv,
13415                                                          POWER_DOMAIN_PIPE(i));
13416                 if (!error->pipe[i].power_domain_on)
13417                         continue;
13418
13419                 error->cursor[i].control = I915_READ(CURCNTR(i));
13420                 error->cursor[i].position = I915_READ(CURPOS(i));
13421                 error->cursor[i].base = I915_READ(CURBASE(i));
13422
13423                 error->plane[i].control = I915_READ(DSPCNTR(i));
13424                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13425                 if (INTEL_INFO(dev)->gen <= 3) {
13426                         error->plane[i].size = I915_READ(DSPSIZE(i));
13427                         error->plane[i].pos = I915_READ(DSPPOS(i));
13428                 }
13429                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13430                         error->plane[i].addr = I915_READ(DSPADDR(i));
13431                 if (INTEL_INFO(dev)->gen >= 4) {
13432                         error->plane[i].surface = I915_READ(DSPSURF(i));
13433                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13434                 }
13435
13436                 error->pipe[i].source = I915_READ(PIPESRC(i));
13437
13438                 if (HAS_GMCH_DISPLAY(dev))
13439                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13440         }
13441
13442         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13443         if (HAS_DDI(dev_priv->dev))
13444                 error->num_transcoders++; /* Account for eDP. */
13445
13446         for (i = 0; i < error->num_transcoders; i++) {
13447                 enum transcoder cpu_transcoder = transcoders[i];
13448
13449                 error->transcoder[i].power_domain_on =
13450                         __intel_display_power_is_enabled(dev_priv,
13451                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13452                 if (!error->transcoder[i].power_domain_on)
13453                         continue;
13454
13455                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13456
13457                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13458                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13459                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13460                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13461                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13462                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13463                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13464         }
13465
13466         return error;
13467 }
13468
13469 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13470
13471 void
13472 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13473                                 struct drm_device *dev,
13474                                 struct intel_display_error_state *error)
13475 {
13476         struct drm_i915_private *dev_priv = dev->dev_private;
13477         int i;
13478
13479         if (!error)
13480                 return;
13481
13482         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13483         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13484                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13485                            error->power_well_driver);
13486         for_each_pipe(dev_priv, i) {
13487                 err_printf(m, "Pipe [%d]:\n", i);
13488                 err_printf(m, "  Power: %s\n",
13489                            error->pipe[i].power_domain_on ? "on" : "off");
13490                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13491                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13492
13493                 err_printf(m, "Plane [%d]:\n", i);
13494                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13495                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13496                 if (INTEL_INFO(dev)->gen <= 3) {
13497                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13498                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13499                 }
13500                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13501                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13502                 if (INTEL_INFO(dev)->gen >= 4) {
13503                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13504                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13505                 }
13506
13507                 err_printf(m, "Cursor [%d]:\n", i);
13508                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13509                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13510                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13511         }
13512
13513         for (i = 0; i < error->num_transcoders; i++) {
13514                 err_printf(m, "CPU transcoder: %c\n",
13515                            transcoder_name(error->transcoder[i].cpu_transcoder));
13516                 err_printf(m, "  Power: %s\n",
13517                            error->transcoder[i].power_domain_on ? "on" : "off");
13518                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13519                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13520                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13521                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13522                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13523                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13524                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13525         }
13526 }
13527
13528 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13529 {
13530         struct intel_crtc *crtc;
13531
13532         for_each_intel_crtc(dev, crtc) {
13533                 struct intel_unpin_work *work;
13534
13535                 spin_lock_irq(&dev->event_lock);
13536
13537                 work = crtc->unpin_work;
13538
13539                 if (work && work->event &&
13540                     work->event->base.file_priv == file) {
13541                         kfree(work->event);
13542                         work->event = NULL;
13543                 }
13544
13545                 spin_unlock_irq(&dev->event_lock);
13546         }
13547 }