drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc);
  98 static void chv_prepare_pll(struct intel_crtc *crtc);
  99
 100 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 101 {
 102         if (!connector->mst_port)
 103                 return connector->encoder;
 104         else
 105                 return &connector->mst_port->mst_encoders[pipe]->base;
 106 }
 107
 108 typedef struct {
 109         int     min, max;
 110 } intel_range_t;
 111
 112 typedef struct {
 113         int     dot_limit;
 114         int     p2_slow, p2_fast;
 115 } intel_p2_t;
 116
 117 typedef struct intel_limit intel_limit_t;
 118 struct intel_limit {
 119         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 120         intel_p2_t          p2;
 121 };
 122
 123 int
 124 intel_pch_rawclk(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127
 128         WARN_ON(!HAS_PCH_SPLIT(dev));
 129
 130         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 131 }
 132
 133 static inline u32 /* units of 100MHz */
 134 intel_fdi_link_freq(struct drm_device *dev)
 135 {
 136         if (IS_GEN5(dev)) {
 137                 struct drm_i915_private *dev_priv = dev->dev_private;
 138                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 139         } else
 140                 return 27;
 141 }
 142
 143 static const intel_limit_t intel_limits_i8xx_dac = {
 144         .dot = { .min = 25000, .max = 350000 },
 145         .vco = { .min = 908000, .max = 1512000 },
 146         .n = { .min = 2, .max = 16 },
 147         .m = { .min = 96, .max = 140 },
 148         .m1 = { .min = 18, .max = 26 },
 149         .m2 = { .min = 6, .max = 16 },
 150         .p = { .min = 4, .max = 128 },
 151         .p1 = { .min = 2, .max = 33 },
 152         .p2 = { .dot_limit = 165000,
 153                 .p2_slow = 4, .p2_fast = 2 },
 154 };
 155
 156 static const intel_limit_t intel_limits_i8xx_dvo = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 4 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_lvds = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 1, .max = 6 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 14, .p2_fast = 7 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_sdvo = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 5, .max = 80 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 200000,
 192                 .p2_slow = 10, .p2_fast = 5 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_lvds = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 7, .max = 98 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 112000,
 205                 .p2_slow = 14, .p2_fast = 7 },
 206 };
 207
 208
 209 static const intel_limit_t intel_limits_g4x_sdvo = {
 210         .dot = { .min = 25000, .max = 270000 },
 211         .vco = { .min = 1750000, .max = 3500000},
 212         .n = { .min = 1, .max = 4 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 10, .max = 30 },
 217         .p1 = { .min = 1, .max = 3},
 218         .p2 = { .dot_limit = 270000,
 219                 .p2_slow = 10,
 220                 .p2_fast = 10
 221         },
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_hdmi = {
 225         .dot = { .min = 22000, .max = 400000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 4 },
 228         .m = { .min = 104, .max = 138 },
 229         .m1 = { .min = 16, .max = 23 },
 230         .m2 = { .min = 5, .max = 11 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8},
 233         .p2 = { .dot_limit = 165000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 238         .dot = { .min = 20000, .max = 115000 },
 239         .vco = { .min = 1750000, .max = 3500000 },
 240         .n = { .min = 1, .max = 3 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 17, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 28, .max = 112 },
 245         .p1 = { .min = 2, .max = 8 },
 246         .p2 = { .dot_limit = 0,
 247                 .p2_slow = 14, .p2_fast = 14
 248         },
 249 };
 250
 251 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 252         .dot = { .min = 80000, .max = 224000 },
 253         .vco = { .min = 1750000, .max = 3500000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 104, .max = 138 },
 256         .m1 = { .min = 17, .max = 23 },
 257         .m2 = { .min = 5, .max = 11 },
 258         .p = { .min = 14, .max = 42 },
 259         .p1 = { .min = 2, .max = 6 },
 260         .p2 = { .dot_limit = 0,
 261                 .p2_slow = 7, .p2_fast = 7
 262         },
 263 };
 264
 265 static const intel_limit_t intel_limits_pineview_sdvo = {
 266         .dot = { .min = 20000, .max = 400000},
 267         .vco = { .min = 1700000, .max = 3500000 },
 268         /* Pineview's Ncounter is a ring counter */
 269         .n = { .min = 3, .max = 6 },
 270         .m = { .min = 2, .max = 256 },
 271         /* Pineview only has one combined m divider, which we treat as m2. */
 272         .m1 = { .min = 0, .max = 0 },
 273         .m2 = { .min = 0, .max = 254 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const intel_limit_t intel_limits_pineview_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1700000, .max = 3500000 },
 283         .n = { .min = 3, .max = 6 },
 284         .m = { .min = 2, .max = 256 },
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 7, .max = 112 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 14 },
 291 };
 292
 293 /* Ironlake / Sandybridge
 294  *
 295  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 296  * the range value for them is (actual_value - 2).
 297  */
 298 static const intel_limit_t intel_limits_ironlake_dac = {
 299         .dot = { .min = 25000, .max = 350000 },
 300         .vco = { .min = 1760000, .max = 3510000 },
 301         .n = { .min = 1, .max = 5 },
 302         .m = { .min = 79, .max = 127 },
 303         .m1 = { .min = 12, .max = 22 },
 304         .m2 = { .min = 5, .max = 9 },
 305         .p = { .min = 5, .max = 80 },
 306         .p1 = { .min = 1, .max = 8 },
 307         .p2 = { .dot_limit = 225000,
 308                 .p2_slow = 10, .p2_fast = 5 },
 309 };
 310
 311 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 79, .max = 118 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 28, .max = 112 },
 319         .p1 = { .min = 2, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 14, .p2_fast = 14 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 127 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 14, .max = 56 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 7, .p2_fast = 7 },
 335 };
 336
 337 /* LVDS 100mhz refclk limits. */
 338 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 339         .dot = { .min = 25000, .max = 350000 },
 340         .vco = { .min = 1760000, .max = 3510000 },
 341         .n = { .min = 1, .max = 2 },
 342         .m = { .min = 79, .max = 126 },
 343         .m1 = { .min = 12, .max = 22 },
 344         .m2 = { .min = 5, .max = 9 },
 345         .p = { .min = 28, .max = 112 },
 346         .p1 = { .min = 2, .max = 8 },
 347         .p2 = { .dot_limit = 225000,
 348                 .p2_slow = 14, .p2_fast = 14 },
 349 };
 350
 351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 14, .max = 42 },
 359         .p1 = { .min = 2, .max = 6 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 7, .p2_fast = 7 },
 362 };
 363
 364 static const intel_limit_t intel_limits_vlv = {
 365          /*
 366           * These are the data rate limits (measured in fast clocks)
 367           * since those are the strictest limits we have. The fast
 368           * clock and actual rate limits are more relaxed, so checking
 369           * them would make no difference.
 370           */
 371         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m1 = { .min = 2, .max = 3 },
 375         .m2 = { .min = 11, .max = 156 },
 376         .p1 = { .min = 2, .max = 3 },
 377         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 378 };
 379
 380 static const intel_limit_t intel_limits_chv = {
 381         /*
 382          * These are the data rate limits (measured in fast clocks)
 383          * since those are the strictest limits we have.  The fast
 384          * clock and actual rate limits are more relaxed, so checking
 385          * them would make no difference.
 386          */
 387         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 388         .vco = { .min = 4860000, .max = 6700000 },
 389         .n = { .min = 1, .max = 1 },
 390         .m1 = { .min = 2, .max = 2 },
 391         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 392         .p1 = { .min = 2, .max = 4 },
 393         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 394 };
 395
 396 static void vlv_clock(int refclk, intel_clock_t *clock)
 397 {
 398         clock->m = clock->m1 * clock->m2;
 399         clock->p = clock->p1 * clock->p2;
 400         if (WARN_ON(clock->n == 0 || clock->p == 0))
 401                 return;
 402         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 403         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 404 }
 405
 406 /**
 407  * Returns whether any output on the specified pipe is of the specified type
 408  */
 409 static bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 410 {
 411         struct drm_device *dev = crtc->base.dev;
 412         struct intel_encoder *encoder;
 413
 414         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 415                 if (encoder->type == type)
 416                         return true;
 417
 418         return false;
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->base.dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_CHERRYVIEW(dev)) {
 481                 limit = &intel_limits_chv;
 482         } else if (IS_VALLEYVIEW(dev)) {
 483                 limit = &intel_limits_vlv;
 484         } else if (!IS_GEN2(dev)) {
 485                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 486                         limit = &intel_limits_i9xx_lvds;
 487                 else
 488                         limit = &intel_limits_i9xx_sdvo;
 489         } else {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i8xx_lvds;
 492                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 493                         limit = &intel_limits_i8xx_dvo;
 494                 else
 495                         limit = &intel_limits_i8xx_dac;
 496         }
 497         return limit;
 498 }
 499
 500 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 501 static void pineview_clock(int refclk, intel_clock_t *clock)
 502 {
 503         clock->m = clock->m2 + 2;
 504         clock->p = clock->p1 * clock->p2;
 505         if (WARN_ON(clock->n == 0 || clock->p == 0))
 506                 return;
 507         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 508         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 509 }
 510
 511 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 512 {
 513         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 514 }
 515
 516 static void i9xx_clock(int refclk, intel_clock_t *clock)
 517 {
 518         clock->m = i9xx_dpll_compute_m(clock);
 519         clock->p = clock->p1 * clock->p2;
 520         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 521                 return;
 522         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 523         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 524 }
 525
 526 static void chv_clock(int refclk, intel_clock_t *clock)
 527 {
 528         clock->m = clock->m1 * clock->m2;
 529         clock->p = clock->p1 * clock->p2;
 530         if (WARN_ON(clock->n == 0 || clock->p == 0))
 531                 return;
 532         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 533                         clock->n << 22);
 534         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_device *dev,
 544                                const intel_limit_t *limit,
 545                                const intel_clock_t *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 557                 if (clock->m1 <= clock->m2)
 558                         INTELPllInvalid("m1 <= m2\n");
 559
 560         if (!IS_VALLEYVIEW(dev)) {
 561                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 562                         INTELPllInvalid("p out of range\n");
 563                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 564                         INTELPllInvalid("m out of range\n");
 565         }
 566
 567         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 568                 INTELPllInvalid("vco out of range\n");
 569         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 570          * connector, etc., rather than just a single range.
 571          */
 572         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 573                 INTELPllInvalid("dot out of range\n");
 574
 575         return true;
 576 }
 577
 578 static bool
 579 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 580                     int target, int refclk, intel_clock_t *match_clock,
 581                     intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->base.dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         if (clock.m2 >= clock.m1)
 611                                 break;
 612                         for (clock.n = limit->n.min;
 613                              clock.n <= limit->n.max; clock.n++) {
 614                                 for (clock.p1 = limit->p1.min;
 615                                         clock.p1 <= limit->p1.max; clock.p1++) {
 616                                         int this_err;
 617
 618                                         i9xx_clock(refclk, &clock);
 619                                         if (!intel_PLL_is_valid(dev, limit,
 620                                                                 &clock))
 621                                                 continue;
 622                                         if (match_clock &&
 623                                             clock.p != match_clock->p)
 624                                                 continue;
 625
 626                                         this_err = abs(clock.dot - target);
 627                                         if (this_err < err) {
 628                                                 *best_clock = clock;
 629                                                 err = this_err;
 630                                         }
 631                                 }
 632                         }
 633                 }
 634         }
 635
 636         return (err != target);
 637 }
 638
 639 static bool
 640 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 641                    int target, int refclk, intel_clock_t *match_clock,
 642                    intel_clock_t *best_clock)
 643 {
 644         struct drm_device *dev = crtc->base.dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         for (clock.n = limit->n.min;
 672                              clock.n <= limit->n.max; clock.n++) {
 673                                 for (clock.p1 = limit->p1.min;
 674                                         clock.p1 <= limit->p1.max; clock.p1++) {
 675                                         int this_err;
 676
 677                                         pineview_clock(refclk, &clock);
 678                                         if (!intel_PLL_is_valid(dev, limit,
 679                                                                 &clock))
 680                                                 continue;
 681                                         if (match_clock &&
 682                                             clock.p != match_clock->p)
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 700                    int target, int refclk, intel_clock_t *match_clock,
 701                    intel_clock_t *best_clock)
 702 {
 703         struct drm_device *dev = crtc->base.dev;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00585 */
 708         int err_most = (target >> 8) + (target >> 9);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if (intel_is_dual_link_lvds(dev))
 713                         clock.p2 = limit->p2.p2_fast;
 714                 else
 715                         clock.p2 = limit->p2.p2_slow;
 716         } else {
 717                 if (target < limit->p2.dot_limit)
 718                         clock.p2 = limit->p2.p2_slow;
 719                 else
 720                         clock.p2 = limit->p2.p2_fast;
 721         }
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724         max_n = limit->n.max;
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 /* based on hardware requirement, prefere larger m1,m2 */
 728                 for (clock.m1 = limit->m1.max;
 729                      clock.m1 >= limit->m1.min; clock.m1--) {
 730                         for (clock.m2 = limit->m2.max;
 731                              clock.m2 >= limit->m2.min; clock.m2--) {
 732                                 for (clock.p1 = limit->p1.max;
 733                                      clock.p1 >= limit->p1.min; clock.p1--) {
 734                                         int this_err;
 735
 736                                         i9xx_clock(refclk, &clock);
 737                                         if (!intel_PLL_is_valid(dev, limit,
 738                                                                 &clock))
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 757                    int target, int refclk, intel_clock_t *match_clock,
 758                    intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->base.dev;
 761         intel_clock_t clock;
 762         unsigned int bestppm = 1000000;
 763         /* min update 19.2 MHz */
 764         int max_n = min(limit->n.max, refclk / 19200);
 765         bool found = false;
 766
 767         target *= 5; /* fast clock */
 768
 769         memset(best_clock, 0, sizeof(*best_clock));
 770
 771         /* based on hardware requirement, prefer smaller n to precision */
 772         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 773                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 774                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 775                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 776                                 clock.p = clock.p1 * clock.p2;
 777                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 778                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 779                                         unsigned int ppm, diff;
 780
 781                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 782                                                                      refclk * clock.m1);
 783
 784                                         vlv_clock(refclk, &clock);
 785
 786                                         if (!intel_PLL_is_valid(dev, limit,
 787                                                                 &clock))
 788                                                 continue;
 789
 790                                         diff = abs(clock.dot - target);
 791                                         ppm = div_u64(1000000ULL * diff, target);
 792
 793                                         if (ppm < 100 && clock.p > best_clock->p) {
 794                                                 bestppm = 0;
 795                                                 *best_clock = clock;
 796                                                 found = true;
 797                                         }
 798
 799                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 800                                                 bestppm = ppm;
 801                                                 *best_clock = clock;
 802                                                 found = true;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return found;
 810 }
 811
 812 static bool
 813 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc->base.dev;
 818         intel_clock_t clock;
 819         uint64_t m2;
 820         int found = false;
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         /*
 825          * Based on hardware doc, the n always set to 1, and m1 always
 826          * set to 2.  If requires to support 200Mhz refclk, we need to
 827          * revisit this because n may not 1 anymore.
 828          */
 829         clock.n = 1, clock.m1 = 2;
 830         target *= 5;    /* fast clock */
 831
 832         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 833                 for (clock.p2 = limit->p2.p2_fast;
 834                                 clock.p2 >= limit->p2.p2_slow;
 835                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 836
 837                         clock.p = clock.p1 * clock.p2;
 838
 839                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 840                                         clock.n) << 22, refclk * clock.m1);
 841
 842                         if (m2 > INT_MAX/clock.m1)
 843                                 continue;
 844
 845                         clock.m2 = m2;
 846
 847                         chv_clock(refclk, &clock);
 848
 849                         if (!intel_PLL_is_valid(dev, limit, &clock))
 850                                 continue;
 851
 852                         /* based on hardware requirement, prefer bigger p
 853                          */
 854                         if (clock.p > best_clock->p) {
 855                                 *best_clock = clock;
 856                                 found = true;
 857                         }
 858                 }
 859         }
 860
 861         return found;
 862 }
 863
 864 bool intel_crtc_active(struct drm_crtc *crtc)
 865 {
 866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 867
 868         /* Be paranoid as we can arrive here with only partial
 869          * state retrieved from the hardware during setup.
 870          *
 871          * We can ditch the adjusted_mode.crtc_clock check as soon
 872          * as Haswell has gained clock readout/fastboot support.
 873          *
 874          * We can ditch the crtc->primary->fb check as soon as we can
 875          * properly reconstruct framebuffers.
 876          */
 877         return intel_crtc->active && crtc->primary->fb &&
 878                 intel_crtc->config.adjusted_mode.crtc_clock;
 879 }
 880
 881 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 882                                              enum pipe pipe)
 883 {
 884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 886
 887         return intel_crtc->config.cpu_transcoder;
 888 }
 889
 890 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 reg = PIPEDSL(pipe);
 894         u32 line1, line2;
 895         u32 line_mask;
 896
 897         if (IS_GEN2(dev))
 898                 line_mask = DSL_LINEMASK_GEN2;
 899         else
 900                 line_mask = DSL_LINEMASK_GEN3;
 901
 902         line1 = I915_READ(reg) & line_mask;
 903         mdelay(5);
 904         line2 = I915_READ(reg) & line_mask;
 905
 906         return line1 == line2;
 907 }
 908
 909 /*
 910  * intel_wait_for_pipe_off - wait for pipe to turn off
 911  * @crtc: crtc whose pipe to wait for
 912  *
 913  * After disabling a pipe, we can't wait for vblank in the usual way,
 914  * spinning on the vblank interrupt status bit, since we won't actually
 915  * see an interrupt when the pipe is disabled.
 916  *
 917  * On Gen4 and above:
 918  *   wait for the pipe register state bit to turn off
 919  *
 920  * Otherwise:
 921  *   wait for the display line value to settle (it usually
 922  *   ends up stopping at the start of the next frame).
 923  *
 924  */
 925 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 926 {
 927         struct drm_device *dev = crtc->base.dev;
 928         struct drm_i915_private *dev_priv = dev->dev_private;
 929         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 930         enum pipe pipe = crtc->pipe;
 931
 932         if (INTEL_INFO(dev)->gen >= 4) {
 933                 int reg = PIPECONF(cpu_transcoder);
 934
 935                 /* Wait for the Pipe State to go off */
 936                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 937                              100))
 938                         WARN(1, "pipe_off wait timed out\n");
 939         } else {
 940                 /* Wait for the display line to settle */
 941                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 942                         WARN(1, "pipe_off wait timed out\n");
 943         }
 944 }
 945
 946 /*
 947  * ibx_digital_port_connected - is the specified port connected?
 948  * @dev_priv: i915 private structure
 949  * @port: the port to test
 950  *
 951  * Returns true if @port is connected, false otherwise.
 952  */
 953 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 954                                 struct intel_digital_port *port)
 955 {
 956         u32 bit;
 957
 958         if (HAS_PCH_IBX(dev_priv->dev)) {
 959                 switch (port->port) {
 960                 case PORT_B:
 961                         bit = SDE_PORTB_HOTPLUG;
 962                         break;
 963                 case PORT_C:
 964                         bit = SDE_PORTC_HOTPLUG;
 965                         break;
 966                 case PORT_D:
 967                         bit = SDE_PORTD_HOTPLUG;
 968                         break;
 969                 default:
 970                         return true;
 971                 }
 972         } else {
 973                 switch (port->port) {
 974                 case PORT_B:
 975                         bit = SDE_PORTB_HOTPLUG_CPT;
 976                         break;
 977                 case PORT_C:
 978                         bit = SDE_PORTC_HOTPLUG_CPT;
 979                         break;
 980                 case PORT_D:
 981                         bit = SDE_PORTD_HOTPLUG_CPT;
 982                         break;
 983                 default:
 984                         return true;
 985                 }
 986         }
 987
 988         return I915_READ(SDEISR) & bit;
 989 }
 990
 991 static const char *state_string(bool enabled)
 992 {
 993         return enabled ? "on" : "off";
 994 }
 995
 996 /* Only for pre-ILK configs */
 997 void assert_pll(struct drm_i915_private *dev_priv,
 998                 enum pipe pipe, bool state)
 999 {
1000         int reg;
1001         u32 val;
1002         bool cur_state;
1003
1004         reg = DPLL(pipe);
1005         val = I915_READ(reg);
1006         cur_state = !!(val & DPLL_VCO_ENABLE);
1007         WARN(cur_state != state,
1008              "PLL state assertion failure (expected %s, current %s)\n",
1009              state_string(state), state_string(cur_state));
1010 }
1011
1012 /* XXX: the dsi pll is shared between MIPI DSI ports */
1013 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1014 {
1015         u32 val;
1016         bool cur_state;
1017
1018         mutex_lock(&dev_priv->dpio_lock);
1019         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1020         mutex_unlock(&dev_priv->dpio_lock);
1021
1022         cur_state = val & DSI_PLL_VCO_EN;
1023         WARN(cur_state != state,
1024              "DSI PLL state assertion failure (expected %s, current %s)\n",
1025              state_string(state), state_string(cur_state));
1026 }
1027 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1028 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1029
1030 struct intel_shared_dpll *
1031 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1032 {
1033         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1034
1035         if (crtc->config.shared_dpll < 0)
1036                 return NULL;
1037
1038         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1039 }
1040
1041 /* For ILK+ */
1042 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1043                         struct intel_shared_dpll *pll,
1044                         bool state)
1045 {
1046         bool cur_state;
1047         struct intel_dpll_hw_state hw_state;
1048
1049         if (WARN (!pll,
1050                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1051                 return;
1052
1053         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1054         WARN(cur_state != state,
1055              "%s assertion failure (expected %s, current %s)\n",
1056              pll->name, state_string(state), state_string(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060                           enum pipe pipe, bool state)
1061 {
1062         int reg;
1063         u32 val;
1064         bool cur_state;
1065         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1066                                                                       pipe);
1067
1068         if (HAS_DDI(dev_priv->dev)) {
1069                 /* DDI does not have a specific FDI_TX register */
1070                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1071                 val = I915_READ(reg);
1072                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1073         } else {
1074                 reg = FDI_TX_CTL(pipe);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080              state_string(state), state_string(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = FDI_RX_CTL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & FDI_RX_ENABLE);
1095         WARN(cur_state != state,
1096              "FDI RX state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1100 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1101
1102 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1103                                       enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* ILK FDI PLL is always enabled */
1109         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1110                 return;
1111
1112         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1113         if (HAS_DDI(dev_priv->dev))
1114                 return;
1115
1116         reg = FDI_TX_CTL(pipe);
1117         val = I915_READ(reg);
1118         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1119 }
1120
1121 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1122                        enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127
1128         reg = FDI_RX_CTL(pipe);
1129         val = I915_READ(reg);
1130         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1131         WARN(cur_state != state,
1132              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1133              state_string(state), state_string(cur_state));
1134 }
1135
1136 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1137                            enum pipe pipe)
1138 {
1139         struct drm_device *dev = dev_priv->dev;
1140         int pp_reg;
1141         u32 val;
1142         enum pipe panel_pipe = PIPE_A;
1143         bool locked = true;
1144
1145         if (WARN_ON(HAS_DDI(dev)))
1146                 return;
1147
1148         if (HAS_PCH_SPLIT(dev)) {
1149                 u32 port_sel;
1150
1151                 pp_reg = PCH_PP_CONTROL;
1152                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1153
1154                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1155                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1156                         panel_pipe = PIPE_B;
1157                 /* XXX: else fix for eDP */
1158         } else if (IS_VALLEYVIEW(dev)) {
1159                 /* presumably write lock depends on pipe, not port select */
1160                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1161                 panel_pipe = pipe;
1162         } else {
1163                 pp_reg = PP_CONTROL;
1164                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1165                         panel_pipe = PIPE_B;
1166         }
1167
1168         val = I915_READ(pp_reg);
1169         if (!(val & PANEL_POWER_ON) ||
1170             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1171                 locked = false;
1172
1173         WARN(panel_pipe == pipe && locked,
1174              "panel assertion failure, pipe %c regs locked\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static void assert_cursor(struct drm_i915_private *dev_priv,
1179                           enum pipe pipe, bool state)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         bool cur_state;
1183
1184         if (IS_845G(dev) || IS_I865G(dev))
1185                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1186         else
1187                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe quirk it must be always on */
1206         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1207             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1208                 state = true;
1209
1210         if (!intel_display_power_is_enabled(dev_priv,
1211                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1212                 cur_state = false;
1213         } else {
1214                 reg = PIPECONF(cpu_transcoder);
1215                 val = I915_READ(reg);
1216                 cur_state = !!(val & PIPECONF_ENABLE);
1217         }
1218
1219         WARN(cur_state != state,
1220              "pipe %c assertion failure (expected %s, current %s)\n",
1221              pipe_name(pipe), state_string(state), state_string(cur_state));
1222 }
1223
1224 static void assert_plane(struct drm_i915_private *dev_priv,
1225                          enum plane plane, bool state)
1226 {
1227         int reg;
1228         u32 val;
1229         bool cur_state;
1230
1231         reg = DSPCNTR(plane);
1232         val = I915_READ(reg);
1233         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1234         WARN(cur_state != state,
1235              "plane %c assertion failure (expected %s, current %s)\n",
1236              plane_name(plane), state_string(state), state_string(cur_state));
1237 }
1238
1239 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1240 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241
1242 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1243                                    enum pipe pipe)
1244 {
1245         struct drm_device *dev = dev_priv->dev;
1246         int reg, i;
1247         u32 val;
1248         int cur_pipe;
1249
1250         /* Primary planes are fixed to pipes on gen4+ */
1251         if (INTEL_INFO(dev)->gen >= 4) {
1252                 reg = DSPCNTR(pipe);
1253                 val = I915_READ(reg);
1254                 WARN(val & DISPLAY_PLANE_ENABLE,
1255                      "plane %c assertion failure, should be disabled but not\n",
1256                      plane_name(pipe));
1257                 return;
1258         }
1259
1260         /* Need to check both planes against the pipe */
1261         for_each_pipe(dev_priv, i) {
1262                 reg = DSPCNTR(i);
1263                 val = I915_READ(reg);
1264                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265                         DISPPLANE_SEL_PIPE_SHIFT;
1266                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268                      plane_name(i), pipe_name(pipe));
1269         }
1270 }
1271
1272 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1273                                     enum pipe pipe)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         int reg, sprite;
1277         u32 val;
1278
1279         if (INTEL_INFO(dev)->gen >= 9) {
1280                 for_each_sprite(pipe, sprite) {
1281                         val = I915_READ(PLANE_CTL(pipe, sprite));
1282                         WARN(val & PLANE_CTL_ENABLE,
1283                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite, pipe_name(pipe));
1285                 }
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 for_each_sprite(pipe, sprite) {
1288                         reg = SPCNTR(pipe, sprite);
1289                         val = I915_READ(reg);
1290                         WARN(val & SP_ENABLE,
1291                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1292                              sprite_name(pipe, sprite), pipe_name(pipe));
1293                 }
1294         } else if (INTEL_INFO(dev)->gen >= 7) {
1295                 reg = SPRCTL(pipe);
1296                 val = I915_READ(reg);
1297                 WARN(val & SPRITE_ENABLE,
1298                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1299                      plane_name(pipe), pipe_name(pipe));
1300         } else if (INTEL_INFO(dev)->gen >= 5) {
1301                 reg = DVSCNTR(pipe);
1302                 val = I915_READ(reg);
1303                 WARN(val & DVS_ENABLE,
1304                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1305                      plane_name(pipe), pipe_name(pipe));
1306         }
1307 }
1308
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312                 drm_crtc_vblank_put(crtc);
1313 }
1314
1315 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1316 {
1317         u32 val;
1318         bool enabled;
1319
1320         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1321
1322         val = I915_READ(PCH_DREF_CONTROL);
1323         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1324                             DREF_SUPERSPREAD_SOURCE_MASK));
1325         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1326 }
1327
1328 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1329                                            enum pipe pipe)
1330 {
1331         int reg;
1332         u32 val;
1333         bool enabled;
1334
1335         reg = PCH_TRANSCONF(pipe);
1336         val = I915_READ(reg);
1337         enabled = !!(val & TRANS_ENABLE);
1338         WARN(enabled,
1339              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1340              pipe_name(pipe));
1341 }
1342
1343 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1344                             enum pipe pipe, u32 port_sel, u32 val)
1345 {
1346         if ((val & DP_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1351                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1352                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1353                         return false;
1354         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1355                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1356                         return false;
1357         } else {
1358                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1359                         return false;
1360         }
1361         return true;
1362 }
1363
1364 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1365                               enum pipe pipe, u32 val)
1366 {
1367         if ((val & SDVO_ENABLE) == 0)
1368                 return false;
1369
1370         if (HAS_PCH_CPT(dev_priv->dev)) {
1371                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1372                         return false;
1373         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1374                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1375                         return false;
1376         } else {
1377                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1378                         return false;
1379         }
1380         return true;
1381 }
1382
1383 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1384                               enum pipe pipe, u32 val)
1385 {
1386         if ((val & LVDS_PORT_EN) == 0)
1387                 return false;
1388
1389         if (HAS_PCH_CPT(dev_priv->dev)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1400                               enum pipe pipe, u32 val)
1401 {
1402         if ((val & ADPA_DAC_ENABLE) == 0)
1403                 return false;
1404         if (HAS_PCH_CPT(dev_priv->dev)) {
1405                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1406                         return false;
1407         } else {
1408                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1409                         return false;
1410         }
1411         return true;
1412 }
1413
1414 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1415                                    enum pipe pipe, int reg, u32 port_sel)
1416 {
1417         u32 val = I915_READ(reg);
1418         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1419              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1420              reg, pipe_name(pipe));
1421
1422         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1423              && (val & DP_PIPEB_SELECT),
1424              "IBX PCH dp port still using transcoder B\n");
1425 }
1426
1427 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1428                                      enum pipe pipe, int reg)
1429 {
1430         u32 val = I915_READ(reg);
1431         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1432              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1433              reg, pipe_name(pipe));
1434
1435         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1436              && (val & SDVO_PIPE_B_SELECT),
1437              "IBX PCH hdmi port still using transcoder B\n");
1438 }
1439
1440 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1441                                       enum pipe pipe)
1442 {
1443         int reg;
1444         u32 val;
1445
1446         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1447         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1448         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1449
1450         reg = PCH_ADPA;
1451         val = I915_READ(reg);
1452         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1453              "PCH VGA enabled on transcoder %c, should be disabled\n",
1454              pipe_name(pipe));
1455
1456         reg = PCH_LVDS;
1457         val = I915_READ(reg);
1458         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1459              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1460              pipe_name(pipe));
1461
1462         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1463         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1464         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1465 }
1466
1467 static void intel_init_dpio(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (!IS_VALLEYVIEW(dev))
1472                 return;
1473
1474         /*
1475          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1476          * CHV x1 PHY (DP/HDMI D)
1477          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1478          */
1479         if (IS_CHERRYVIEW(dev)) {
1480                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1481                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1482         } else {
1483                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1484         }
1485 }
1486
1487 static void vlv_enable_pll(struct intel_crtc *crtc)
1488 {
1489         struct drm_device *dev = crtc->base.dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         int reg = DPLL(crtc->pipe);
1492         u32 dpll = crtc->config.dpll_hw_state.dpll;
1493
1494         assert_pipe_disabled(dev_priv, crtc->pipe);
1495
1496         /* No really, not for ILK+ */
1497         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1498
1499         /* PLL is protected by panel, make sure we can write it */
1500         if (IS_MOBILE(dev_priv->dev))
1501                 assert_panel_unlocked(dev_priv, crtc->pipe);
1502
1503         I915_WRITE(reg, dpll);
1504         POSTING_READ(reg);
1505         udelay(150);
1506
1507         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1509
1510         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1511         POSTING_READ(DPLL_MD(crtc->pipe));
1512
1513         /* We do this three times for luck */
1514         I915_WRITE(reg, dpll);
1515         POSTING_READ(reg);
1516         udelay(150); /* wait for warmup */
1517         I915_WRITE(reg, dpll);
1518         POSTING_READ(reg);
1519         udelay(150); /* wait for warmup */
1520         I915_WRITE(reg, dpll);
1521         POSTING_READ(reg);
1522         udelay(150); /* wait for warmup */
1523 }
1524
1525 static void chv_enable_pll(struct intel_crtc *crtc)
1526 {
1527         struct drm_device *dev = crtc->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         int pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1536
1537         mutex_lock(&dev_priv->dpio_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         /*
1545          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1546          */
1547         udelay(1);
1548
1549         /* Enable PLL */
1550         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1551
1552         /* Check PLL is locked */
1553         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555
1556         /* not sure when this should be written */
1557         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1558         POSTING_READ(DPLL_MD(pipe));
1559
1560         mutex_unlock(&dev_priv->dpio_lock);
1561 }
1562
1563 static int intel_num_dvo_pipes(struct drm_device *dev)
1564 {
1565         struct intel_crtc *crtc;
1566         int count = 0;
1567
1568         for_each_intel_crtc(dev, crtc)
1569                 count += crtc->active &&
1570                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1571
1572         return count;
1573 }
1574
1575 static void i9xx_enable_pll(struct intel_crtc *crtc)
1576 {
1577         struct drm_device *dev = crtc->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         int reg = DPLL(crtc->pipe);
1580         u32 dpll = crtc->config.dpll_hw_state.dpll;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         /* No really, not for ILK+ */
1585         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1586
1587         /* PLL is protected by panel, make sure we can write it */
1588         if (IS_MOBILE(dev) && !IS_I830(dev))
1589                 assert_panel_unlocked(dev_priv, crtc->pipe);
1590
1591         /* Enable DVO 2x clock on both PLLs if necessary */
1592         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1593                 /*
1594                  * It appears to be important that we don't enable this
1595                  * for the current pipe before otherwise configuring the
1596                  * PLL. No idea how this should be handled if multiple
1597                  * DVO outputs are enabled simultaneosly.
1598                  */
1599                 dpll |= DPLL_DVO_2X_MODE;
1600                 I915_WRITE(DPLL(!crtc->pipe),
1601                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1602         }
1603
1604         /* Wait for the clocks to stabilize. */
1605         POSTING_READ(reg);
1606         udelay(150);
1607
1608         if (INTEL_INFO(dev)->gen >= 4) {
1609                 I915_WRITE(DPLL_MD(crtc->pipe),
1610                            crtc->config.dpll_hw_state.dpll_md);
1611         } else {
1612                 /* The pixel multiplier can only be updated once the
1613                  * DPLL is enabled and the clocks are stable.
1614                  *
1615                  * So write it again.
1616                  */
1617                 I915_WRITE(reg, dpll);
1618         }
1619
1620         /* We do this three times for luck */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630 }
1631
1632 /**
1633  * i9xx_disable_pll - disable a PLL
1634  * @dev_priv: i915 private structure
1635  * @pipe: pipe PLL to disable
1636  *
1637  * Disable the PLL for @pipe, making sure the pipe is off first.
1638  *
1639  * Note!  This is for pre-ILK only.
1640  */
1641 static void i9xx_disable_pll(struct intel_crtc *crtc)
1642 {
1643         struct drm_device *dev = crtc->base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         enum pipe pipe = crtc->pipe;
1646
1647         /* Disable DVO 2x clock on both PLLs if necessary */
1648         if (IS_I830(dev) &&
1649             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1650             intel_num_dvo_pipes(dev) == 1) {
1651                 I915_WRITE(DPLL(PIPE_B),
1652                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1653                 I915_WRITE(DPLL(PIPE_A),
1654                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1655         }
1656
1657         /* Don't disable pipe or pipe PLLs if needed */
1658         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1659             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1660                 return;
1661
1662         /* Make sure the pipe isn't still relying on us */
1663         assert_pipe_disabled(dev_priv, pipe);
1664
1665         I915_WRITE(DPLL(pipe), 0);
1666         POSTING_READ(DPLL(pipe));
1667 }
1668
1669 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1670 {
1671         u32 val = 0;
1672
1673         /* Make sure the pipe isn't still relying on us */
1674         assert_pipe_disabled(dev_priv, pipe);
1675
1676         /*
1677          * Leave integrated clock source and reference clock enabled for pipe B.
1678          * The latter is needed for VGA hotplug / manual detection.
1679          */
1680         if (pipe == PIPE_B)
1681                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1682         I915_WRITE(DPLL(pipe), val);
1683         POSTING_READ(DPLL(pipe));
1684
1685 }
1686
1687 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1688 {
1689         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1690         u32 val;
1691
1692         /* Make sure the pipe isn't still relying on us */
1693         assert_pipe_disabled(dev_priv, pipe);
1694
1695         /* Set PLL en = 0 */
1696         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1697         if (pipe != PIPE_A)
1698                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1699         I915_WRITE(DPLL(pipe), val);
1700         POSTING_READ(DPLL(pipe));
1701
1702         mutex_lock(&dev_priv->dpio_lock);
1703
1704         /* Disable 10bit clock to display controller */
1705         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1706         val &= ~DPIO_DCLKP_EN;
1707         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1708
1709         /* disable left/right clock distribution */
1710         if (pipe != PIPE_B) {
1711                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1712                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1713                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1714         } else {
1715                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1716                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1717                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1718         }
1719
1720         mutex_unlock(&dev_priv->dpio_lock);
1721 }
1722
1723 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1724                 struct intel_digital_port *dport)
1725 {
1726         u32 port_mask;
1727         int dpll_reg;
1728
1729         switch (dport->port) {
1730         case PORT_B:
1731                 port_mask = DPLL_PORTB_READY_MASK;
1732                 dpll_reg = DPLL(0);
1733                 break;
1734         case PORT_C:
1735                 port_mask = DPLL_PORTC_READY_MASK;
1736                 dpll_reg = DPLL(0);
1737                 break;
1738         case PORT_D:
1739                 port_mask = DPLL_PORTD_READY_MASK;
1740                 dpll_reg = DPIO_PHY_STATUS;
1741                 break;
1742         default:
1743                 BUG();
1744         }
1745
1746         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1747                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1748                      port_name(dport->port), I915_READ(dpll_reg));
1749 }
1750
1751 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1752 {
1753         struct drm_device *dev = crtc->base.dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1756
1757         if (WARN_ON(pll == NULL))
1758                 return;
1759
1760         WARN_ON(!pll->refcount);
1761         if (pll->active == 0) {
1762                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1763                 WARN_ON(pll->on);
1764                 assert_shared_dpll_disabled(dev_priv, pll);
1765
1766                 pll->mode_set(dev_priv, pll);
1767         }
1768 }
1769
1770 /**
1771  * intel_enable_shared_dpll - enable PCH PLL
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe PLL to enable
1774  *
1775  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1776  * drives the transcoder clock.
1777  */
1778 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1779 {
1780         struct drm_device *dev = crtc->base.dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1783
1784         if (WARN_ON(pll == NULL))
1785                 return;
1786
1787         if (WARN_ON(pll->refcount == 0))
1788                 return;
1789
1790         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1791                       pll->name, pll->active, pll->on,
1792                       crtc->base.base.id);
1793
1794         if (pll->active++) {
1795                 WARN_ON(!pll->on);
1796                 assert_shared_dpll_enabled(dev_priv, pll);
1797                 return;
1798         }
1799         WARN_ON(pll->on);
1800
1801         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1802
1803         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1804         pll->enable(dev_priv, pll);
1805         pll->on = true;
1806 }
1807
1808 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1809 {
1810         struct drm_device *dev = crtc->base.dev;
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1813
1814         /* PCH only available on ILK+ */
1815         BUG_ON(INTEL_INFO(dev)->gen < 5);
1816         if (WARN_ON(pll == NULL))
1817                return;
1818
1819         if (WARN_ON(pll->refcount == 0))
1820                 return;
1821
1822         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1823                       pll->name, pll->active, pll->on,
1824                       crtc->base.base.id);
1825
1826         if (WARN_ON(pll->active == 0)) {
1827                 assert_shared_dpll_disabled(dev_priv, pll);
1828                 return;
1829         }
1830
1831         assert_shared_dpll_enabled(dev_priv, pll);
1832         WARN_ON(!pll->on);
1833         if (--pll->active)
1834                 return;
1835
1836         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1837         pll->disable(dev_priv, pll);
1838         pll->on = false;
1839
1840         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1841 }
1842
1843 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1844                                            enum pipe pipe)
1845 {
1846         struct drm_device *dev = dev_priv->dev;
1847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849         uint32_t reg, val, pipeconf_val;
1850
1851         /* PCH only available on ILK+ */
1852         BUG_ON(!HAS_PCH_SPLIT(dev));
1853
1854         /* Make sure PCH DPLL is enabled */
1855         assert_shared_dpll_enabled(dev_priv,
1856                                    intel_crtc_to_shared_dpll(intel_crtc));
1857
1858         /* FDI must be feeding us bits for PCH ports */
1859         assert_fdi_tx_enabled(dev_priv, pipe);
1860         assert_fdi_rx_enabled(dev_priv, pipe);
1861
1862         if (HAS_PCH_CPT(dev)) {
1863                 /* Workaround: Set the timing override bit before enabling the
1864                  * pch transcoder. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870
1871         reg = PCH_TRANSCONF(pipe);
1872         val = I915_READ(reg);
1873         pipeconf_val = I915_READ(PIPECONF(pipe));
1874
1875         if (HAS_PCH_IBX(dev_priv->dev)) {
1876                 /*
1877                  * make the BPC in transcoder be consistent with
1878                  * that in pipeconf reg.
1879                  */
1880                 val &= ~PIPECONF_BPC_MASK;
1881                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1882         }
1883
1884         val &= ~TRANS_INTERLACE_MASK;
1885         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1886                 if (HAS_PCH_IBX(dev_priv->dev) &&
1887                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1888                         val |= TRANS_LEGACY_INTERLACED_ILK;
1889                 else
1890                         val |= TRANS_INTERLACED;
1891         else
1892                 val |= TRANS_PROGRESSIVE;
1893
1894         I915_WRITE(reg, val | TRANS_ENABLE);
1895         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1896                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1897 }
1898
1899 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900                                       enum transcoder cpu_transcoder)
1901 {
1902         u32 val, pipeconf_val;
1903
1904         /* PCH only available on ILK+ */
1905         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1906
1907         /* FDI must be feeding us bits for PCH ports */
1908         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1909         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1910
1911         /* Workaround: set timing override bit. */
1912         val = I915_READ(_TRANSA_CHICKEN2);
1913         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1914         I915_WRITE(_TRANSA_CHICKEN2, val);
1915
1916         val = TRANS_ENABLE;
1917         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1918
1919         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1920             PIPECONF_INTERLACED_ILK)
1921                 val |= TRANS_INTERLACED;
1922         else
1923                 val |= TRANS_PROGRESSIVE;
1924
1925         I915_WRITE(LPT_TRANSCONF, val);
1926         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1927                 DRM_ERROR("Failed to enable PCH transcoder\n");
1928 }
1929
1930 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1931                                             enum pipe pipe)
1932 {
1933         struct drm_device *dev = dev_priv->dev;
1934         uint32_t reg, val;
1935
1936         /* FDI relies on the transcoder */
1937         assert_fdi_tx_disabled(dev_priv, pipe);
1938         assert_fdi_rx_disabled(dev_priv, pipe);
1939
1940         /* Ports must be off as well */
1941         assert_pch_ports_disabled(dev_priv, pipe);
1942
1943         reg = PCH_TRANSCONF(pipe);
1944         val = I915_READ(reg);
1945         val &= ~TRANS_ENABLE;
1946         I915_WRITE(reg, val);
1947         /* wait for PCH transcoder off, transcoder state */
1948         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1949                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1950
1951         if (!HAS_PCH_IBX(dev)) {
1952                 /* Workaround: Clear the timing override chicken bit again. */
1953                 reg = TRANS_CHICKEN2(pipe);
1954                 val = I915_READ(reg);
1955                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1956                 I915_WRITE(reg, val);
1957         }
1958 }
1959
1960 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1961 {
1962         u32 val;
1963
1964         val = I915_READ(LPT_TRANSCONF);
1965         val &= ~TRANS_ENABLE;
1966         I915_WRITE(LPT_TRANSCONF, val);
1967         /* wait for PCH transcoder off, transcoder state */
1968         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1969                 DRM_ERROR("Failed to disable PCH transcoder\n");
1970
1971         /* Workaround: clear timing override bit. */
1972         val = I915_READ(_TRANSA_CHICKEN2);
1973         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1974         I915_WRITE(_TRANSA_CHICKEN2, val);
1975 }
1976
1977 /**
1978  * intel_enable_pipe - enable a pipe, asserting requirements
1979  * @crtc: crtc responsible for the pipe
1980  *
1981  * Enable @crtc's pipe, making sure that various hardware specific requirements
1982  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1983  */
1984 static void intel_enable_pipe(struct intel_crtc *crtc)
1985 {
1986         struct drm_device *dev = crtc->base.dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         enum pipe pipe = crtc->pipe;
1989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1990                                                                       pipe);
1991         enum pipe pch_transcoder;
1992         int reg;
1993         u32 val;
1994
1995         assert_planes_disabled(dev_priv, pipe);
1996         assert_cursor_disabled(dev_priv, pipe);
1997         assert_sprites_disabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_LPT(dev_priv->dev))
2000                 pch_transcoder = TRANSCODER_A;
2001         else
2002                 pch_transcoder = pipe;
2003
2004         /*
2005          * A pipe without a PLL won't actually be able to drive bits from
2006          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2007          * need the check.
2008          */
2009         if (!HAS_PCH_SPLIT(dev_priv->dev))
2010                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2011                         assert_dsi_pll_enabled(dev_priv);
2012                 else
2013                         assert_pll_enabled(dev_priv, pipe);
2014         else {
2015                 if (crtc->config.has_pch_encoder) {
2016                         /* if driving the PCH, we need FDI enabled */
2017                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2018                         assert_fdi_tx_pll_enabled(dev_priv,
2019                                                   (enum pipe) cpu_transcoder);
2020                 }
2021                 /* FIXME: assert CPU port conditions for SNB+ */
2022         }
2023
2024         reg = PIPECONF(cpu_transcoder);
2025         val = I915_READ(reg);
2026         if (val & PIPECONF_ENABLE) {
2027                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2028                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2029                 return;
2030         }
2031
2032         I915_WRITE(reg, val | PIPECONF_ENABLE);
2033         POSTING_READ(reg);
2034 }
2035
2036 /**
2037  * intel_disable_pipe - disable a pipe, asserting requirements
2038  * @crtc: crtc whose pipes is to be disabled
2039  *
2040  * Disable the pipe of @crtc, making sure that various hardware
2041  * specific requirements are met, if applicable, e.g. plane
2042  * disabled, panel fitter off, etc.
2043  *
2044  * Will wait until the pipe has shut down before returning.
2045  */
2046 static void intel_disable_pipe(struct intel_crtc *crtc)
2047 {
2048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2049         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2050         enum pipe pipe = crtc->pipe;
2051         int reg;
2052         u32 val;
2053
2054         /*
2055          * Make sure planes won't keep trying to pump pixels to us,
2056          * or we might hang the display.
2057          */
2058         assert_planes_disabled(dev_priv, pipe);
2059         assert_cursor_disabled(dev_priv, pipe);
2060         assert_sprites_disabled(dev_priv, pipe);
2061
2062         reg = PIPECONF(cpu_transcoder);
2063         val = I915_READ(reg);
2064         if ((val & PIPECONF_ENABLE) == 0)
2065                 return;
2066
2067         /*
2068          * Double wide has implications for planes
2069          * so best keep it disabled when not needed.
2070          */
2071         if (crtc->config.double_wide)
2072                 val &= ~PIPECONF_DOUBLE_WIDE;
2073
2074         /* Don't disable pipe or pipe PLLs if needed */
2075         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2076             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2077                 val &= ~PIPECONF_ENABLE;
2078
2079         I915_WRITE(reg, val);
2080         if ((val & PIPECONF_ENABLE) == 0)
2081                 intel_wait_for_pipe_off(crtc);
2082 }
2083
2084 /*
2085  * Plane regs are double buffered, going from enabled->disabled needs a
2086  * trigger in order to latch.  The display address reg provides this.
2087  */
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089                                enum plane plane)
2090 {
2091         struct drm_device *dev = dev_priv->dev;
2092         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2093
2094         I915_WRITE(reg, I915_READ(reg));
2095         POSTING_READ(reg);
2096 }
2097
2098 /**
2099  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100  * @plane:  plane to be enabled
2101  * @crtc: crtc for the plane
2102  *
2103  * Enable @plane on @crtc, making sure that the pipe is running first.
2104  */
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106                                           struct drm_crtc *crtc)
2107 {
2108         struct drm_device *dev = plane->dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2114
2115         if (intel_crtc->primary_enabled)
2116                 return;
2117
2118         intel_crtc->primary_enabled = true;
2119
2120         dev_priv->display.update_primary_plane(crtc, plane->fb,
2121                                                crtc->x, crtc->y);
2122
2123         /*
2124          * BDW signals flip done immediately if the plane
2125          * is disabled, even if the plane enable is already
2126          * armed to occur at the next vblank :(
2127          */
2128         if (IS_BROADWELL(dev))
2129                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2130 }
2131
2132 /**
2133  * intel_disable_primary_hw_plane - disable the primary hardware plane
2134  * @plane: plane to be disabled
2135  * @crtc: crtc for the plane
2136  *
2137  * Disable @plane on @crtc, making sure that the pipe is running first.
2138  */
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140                                            struct drm_crtc *crtc)
2141 {
2142         struct drm_device *dev = plane->dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2147
2148         if (!intel_crtc->primary_enabled)
2149                 return;
2150
2151         intel_crtc->primary_enabled = false;
2152
2153         dev_priv->display.update_primary_plane(crtc, plane->fb,
2154                                                crtc->x, crtc->y);
2155 }
2156
2157 static bool need_vtd_wa(struct drm_device *dev)
2158 {
2159 #ifdef CONFIG_INTEL_IOMMU
2160         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161                 return true;
2162 #endif
2163         return false;
2164 }
2165
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167 {
2168         int tile_height;
2169
2170         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171         return ALIGN(height, tile_height);
2172 }
2173
2174 int
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176                            struct drm_i915_gem_object *obj,
2177                            struct intel_engine_cs *pipelined)
2178 {
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         u32 alignment;
2181         int ret;
2182
2183         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
2185         switch (obj->tiling_mode) {
2186         case I915_TILING_NONE:
2187                 if (INTEL_INFO(dev)->gen >= 9)
2188                         alignment = 256 * 1024;
2189                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2190                         alignment = 128 * 1024;
2191                 else if (INTEL_INFO(dev)->gen >= 4)
2192                         alignment = 4 * 1024;
2193                 else
2194                         alignment = 64 * 1024;
2195                 break;
2196         case I915_TILING_X:
2197                 if (INTEL_INFO(dev)->gen >= 9)
2198                         alignment = 256 * 1024;
2199                 else {
2200                         /* pin() will align the object as required by fence */
2201                         alignment = 0;
2202                 }
2203                 break;
2204         case I915_TILING_Y:
2205                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2206                 return -EINVAL;
2207         default:
2208                 BUG();
2209         }
2210
2211         /* Note that the w/a also requires 64 PTE of padding following the
2212          * bo. We currently fill all unused PTE with the shadow page and so
2213          * we should always have valid PTE following the scanout preventing
2214          * the VT-d warning.
2215          */
2216         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2217                 alignment = 256 * 1024;
2218
2219         /*
2220          * Global gtt pte registers are special registers which actually forward
2221          * writes to a chunk of system memory. Which means that there is no risk
2222          * that the register values disappear as soon as we call
2223          * intel_runtime_pm_put(), so it is correct to wrap only the
2224          * pin/unpin/fence and not more.
2225          */
2226         intel_runtime_pm_get(dev_priv);
2227
2228         dev_priv->mm.interruptible = false;
2229         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230         if (ret)
2231                 goto err_interruptible;
2232
2233         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234          * fence, whereas 965+ only requires a fence if using
2235          * framebuffer compression.  For simplicity, we always install
2236          * a fence as the cost is not that onerous.
2237          */
2238         ret = i915_gem_object_get_fence(obj);
2239         if (ret)
2240                 goto err_unpin;
2241
2242         i915_gem_object_pin_fence(obj);
2243
2244         dev_priv->mm.interruptible = true;
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247
2248 err_unpin:
2249         i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251         dev_priv->mm.interruptible = true;
2252         intel_runtime_pm_put(dev_priv);
2253         return ret;
2254 }
2255
2256 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2257 {
2258         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2259
2260         i915_gem_object_unpin_fence(obj);
2261         i915_gem_object_unpin_from_display_plane(obj);
2262 }
2263
2264 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2265  * is assumed to be a power-of-two. */
2266 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2267                                              unsigned int tiling_mode,
2268                                              unsigned int cpp,
2269                                              unsigned int pitch)
2270 {
2271         if (tiling_mode != I915_TILING_NONE) {
2272                 unsigned int tile_rows, tiles;
2273
2274                 tile_rows = *y / 8;
2275                 *y %= 8;
2276
2277                 tiles = *x / (512/cpp);
2278                 *x %= 512/cpp;
2279
2280                 return tile_rows * pitch * 8 + tiles * 4096;
2281         } else {
2282                 unsigned int offset;
2283
2284                 offset = *y * pitch + *x * cpp;
2285                 *y = 0;
2286                 *x = (offset & 4095) / cpp;
2287                 return offset & -4096;
2288         }
2289 }
2290
2291 int intel_format_to_fourcc(int format)
2292 {
2293         switch (format) {
2294         case DISPPLANE_8BPP:
2295                 return DRM_FORMAT_C8;
2296         case DISPPLANE_BGRX555:
2297                 return DRM_FORMAT_XRGB1555;
2298         case DISPPLANE_BGRX565:
2299                 return DRM_FORMAT_RGB565;
2300         default:
2301         case DISPPLANE_BGRX888:
2302                 return DRM_FORMAT_XRGB8888;
2303         case DISPPLANE_RGBX888:
2304                 return DRM_FORMAT_XBGR8888;
2305         case DISPPLANE_BGRX101010:
2306                 return DRM_FORMAT_XRGB2101010;
2307         case DISPPLANE_RGBX101010:
2308                 return DRM_FORMAT_XBGR2101010;
2309         }
2310 }
2311
2312 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2313                                   struct intel_plane_config *plane_config)
2314 {
2315         struct drm_device *dev = crtc->base.dev;
2316         struct drm_i915_gem_object *obj = NULL;
2317         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2318         u32 base = plane_config->base;
2319
2320         if (plane_config->size == 0)
2321                 return false;
2322
2323         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2324                                                              plane_config->size);
2325         if (!obj)
2326                 return false;
2327
2328         if (plane_config->tiled) {
2329                 obj->tiling_mode = I915_TILING_X;
2330                 obj->stride = crtc->base.primary->fb->pitches[0];
2331         }
2332
2333         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2334         mode_cmd.width = crtc->base.primary->fb->width;
2335         mode_cmd.height = crtc->base.primary->fb->height;
2336         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2337
2338         mutex_lock(&dev->struct_mutex);
2339
2340         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2341                                    &mode_cmd, obj)) {
2342                 DRM_DEBUG_KMS("intel fb init failed\n");
2343                 goto out_unref_obj;
2344         }
2345
2346         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2347         mutex_unlock(&dev->struct_mutex);
2348
2349         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2350         return true;
2351
2352 out_unref_obj:
2353         drm_gem_object_unreference(&obj->base);
2354         mutex_unlock(&dev->struct_mutex);
2355         return false;
2356 }
2357
2358 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2359                                  struct intel_plane_config *plane_config)
2360 {
2361         struct drm_device *dev = intel_crtc->base.dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct drm_crtc *c;
2364         struct intel_crtc *i;
2365         struct drm_i915_gem_object *obj;
2366
2367         if (!intel_crtc->base.primary->fb)
2368                 return;
2369
2370         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2371                 return;
2372
2373         kfree(intel_crtc->base.primary->fb);
2374         intel_crtc->base.primary->fb = NULL;
2375
2376         /*
2377          * Failed to alloc the obj, check to see if we should share
2378          * an fb with another CRTC instead
2379          */
2380         for_each_crtc(dev, c) {
2381                 i = to_intel_crtc(c);
2382
2383                 if (c == &intel_crtc->base)
2384                         continue;
2385
2386                 if (!i->active)
2387                         continue;
2388
2389                 obj = intel_fb_obj(c->primary->fb);
2390                 if (obj == NULL)
2391                         continue;
2392
2393                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2394                         if (obj->tiling_mode != I915_TILING_NONE)
2395                                 dev_priv->preserve_bios_swizzle = true;
2396
2397                         drm_framebuffer_reference(c->primary->fb);
2398                         intel_crtc->base.primary->fb = c->primary->fb;
2399                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2400                         break;
2401                 }
2402         }
2403 }
2404
2405 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2406                                       struct drm_framebuffer *fb,
2407                                       int x, int y)
2408 {
2409         struct drm_device *dev = crtc->dev;
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412         struct drm_i915_gem_object *obj;
2413         int plane = intel_crtc->plane;
2414         unsigned long linear_offset;
2415         u32 dspcntr;
2416         u32 reg = DSPCNTR(plane);
2417         int pixel_size;
2418
2419         if (!intel_crtc->primary_enabled) {
2420                 I915_WRITE(reg, 0);
2421                 if (INTEL_INFO(dev)->gen >= 4)
2422                         I915_WRITE(DSPSURF(plane), 0);
2423                 else
2424                         I915_WRITE(DSPADDR(plane), 0);
2425                 POSTING_READ(reg);
2426                 return;
2427         }
2428
2429         obj = intel_fb_obj(fb);
2430         if (WARN_ON(obj == NULL))
2431                 return;
2432
2433         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2434
2435         dspcntr = DISPPLANE_GAMMA_ENABLE;
2436
2437         dspcntr |= DISPLAY_PLANE_ENABLE;
2438
2439         if (INTEL_INFO(dev)->gen < 4) {
2440                 if (intel_crtc->pipe == PIPE_B)
2441                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2442
2443                 /* pipesrc and dspsize control the size that is scaled from,
2444                  * which should always be the user's requested size.
2445                  */
2446                 I915_WRITE(DSPSIZE(plane),
2447                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2448                            (intel_crtc->config.pipe_src_w - 1));
2449                 I915_WRITE(DSPPOS(plane), 0);
2450         }
2451
2452         switch (fb->pixel_format) {
2453         case DRM_FORMAT_C8:
2454                 dspcntr |= DISPPLANE_8BPP;
2455                 break;
2456         case DRM_FORMAT_XRGB1555:
2457         case DRM_FORMAT_ARGB1555:
2458                 dspcntr |= DISPPLANE_BGRX555;
2459                 break;
2460         case DRM_FORMAT_RGB565:
2461                 dspcntr |= DISPPLANE_BGRX565;
2462                 break;
2463         case DRM_FORMAT_XRGB8888:
2464         case DRM_FORMAT_ARGB8888:
2465                 dspcntr |= DISPPLANE_BGRX888;
2466                 break;
2467         case DRM_FORMAT_XBGR8888:
2468         case DRM_FORMAT_ABGR8888:
2469                 dspcntr |= DISPPLANE_RGBX888;
2470                 break;
2471         case DRM_FORMAT_XRGB2101010:
2472         case DRM_FORMAT_ARGB2101010:
2473                 dspcntr |= DISPPLANE_BGRX101010;
2474                 break;
2475         case DRM_FORMAT_XBGR2101010:
2476         case DRM_FORMAT_ABGR2101010:
2477                 dspcntr |= DISPPLANE_RGBX101010;
2478                 break;
2479         default:
2480                 BUG();
2481         }
2482
2483         if (INTEL_INFO(dev)->gen >= 4 &&
2484             obj->tiling_mode != I915_TILING_NONE)
2485                 dspcntr |= DISPPLANE_TILED;
2486
2487         if (IS_G4X(dev))
2488                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2489
2490         linear_offset = y * fb->pitches[0] + x * pixel_size;
2491
2492         if (INTEL_INFO(dev)->gen >= 4) {
2493                 intel_crtc->dspaddr_offset =
2494                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2495                                                        pixel_size,
2496                                                        fb->pitches[0]);
2497                 linear_offset -= intel_crtc->dspaddr_offset;
2498         } else {
2499                 intel_crtc->dspaddr_offset = linear_offset;
2500         }
2501
2502         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2503                 dspcntr |= DISPPLANE_ROTATE_180;
2504
2505                 x += (intel_crtc->config.pipe_src_w - 1);
2506                 y += (intel_crtc->config.pipe_src_h - 1);
2507
2508                 /* Finding the last pixel of the last line of the display
2509                 data and adding to linear_offset*/
2510                 linear_offset +=
2511                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2512                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2513         }
2514
2515         I915_WRITE(reg, dspcntr);
2516
2517         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2519                       fb->pitches[0]);
2520         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2521         if (INTEL_INFO(dev)->gen >= 4) {
2522                 I915_WRITE(DSPSURF(plane),
2523                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2524                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526         } else
2527                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2528         POSTING_READ(reg);
2529 }
2530
2531 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2532                                           struct drm_framebuffer *fb,
2533                                           int x, int y)
2534 {
2535         struct drm_device *dev = crtc->dev;
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2538         struct drm_i915_gem_object *obj;
2539         int plane = intel_crtc->plane;
2540         unsigned long linear_offset;
2541         u32 dspcntr;
2542         u32 reg = DSPCNTR(plane);
2543         int pixel_size;
2544
2545         if (!intel_crtc->primary_enabled) {
2546                 I915_WRITE(reg, 0);
2547                 I915_WRITE(DSPSURF(plane), 0);
2548                 POSTING_READ(reg);
2549                 return;
2550         }
2551
2552         obj = intel_fb_obj(fb);
2553         if (WARN_ON(obj == NULL))
2554                 return;
2555
2556         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2557
2558         dspcntr = DISPPLANE_GAMMA_ENABLE;
2559
2560         dspcntr |= DISPLAY_PLANE_ENABLE;
2561
2562         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2563                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2564
2565         switch (fb->pixel_format) {
2566         case DRM_FORMAT_C8:
2567                 dspcntr |= DISPPLANE_8BPP;
2568                 break;
2569         case DRM_FORMAT_RGB565:
2570                 dspcntr |= DISPPLANE_BGRX565;
2571                 break;
2572         case DRM_FORMAT_XRGB8888:
2573         case DRM_FORMAT_ARGB8888:
2574                 dspcntr |= DISPPLANE_BGRX888;
2575                 break;
2576         case DRM_FORMAT_XBGR8888:
2577         case DRM_FORMAT_ABGR8888:
2578                 dspcntr |= DISPPLANE_RGBX888;
2579                 break;
2580         case DRM_FORMAT_XRGB2101010:
2581         case DRM_FORMAT_ARGB2101010:
2582                 dspcntr |= DISPPLANE_BGRX101010;
2583                 break;
2584         case DRM_FORMAT_XBGR2101010:
2585         case DRM_FORMAT_ABGR2101010:
2586                 dspcntr |= DISPPLANE_RGBX101010;
2587                 break;
2588         default:
2589                 BUG();
2590         }
2591
2592         if (obj->tiling_mode != I915_TILING_NONE)
2593                 dspcntr |= DISPPLANE_TILED;
2594
2595         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2596                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2597
2598         linear_offset = y * fb->pitches[0] + x * pixel_size;
2599         intel_crtc->dspaddr_offset =
2600                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2601                                                pixel_size,
2602                                                fb->pitches[0]);
2603         linear_offset -= intel_crtc->dspaddr_offset;
2604         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2605                 dspcntr |= DISPPLANE_ROTATE_180;
2606
2607                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2608                         x += (intel_crtc->config.pipe_src_w - 1);
2609                         y += (intel_crtc->config.pipe_src_h - 1);
2610
2611                         /* Finding the last pixel of the last line of the display
2612                         data and adding to linear_offset*/
2613                         linear_offset +=
2614                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2615                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2616                 }
2617         }
2618
2619         I915_WRITE(reg, dspcntr);
2620
2621         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2622                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2623                       fb->pitches[0]);
2624         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2625         I915_WRITE(DSPSURF(plane),
2626                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2627         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2628                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2629         } else {
2630                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2631                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2632         }
2633         POSTING_READ(reg);
2634 }
2635
2636 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2637                                          struct drm_framebuffer *fb,
2638                                          int x, int y)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         struct intel_framebuffer *intel_fb;
2644         struct drm_i915_gem_object *obj;
2645         int pipe = intel_crtc->pipe;
2646         u32 plane_ctl, stride;
2647
2648         if (!intel_crtc->primary_enabled) {
2649                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2650                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2651                 POSTING_READ(PLANE_CTL(pipe, 0));
2652                 return;
2653         }
2654
2655         plane_ctl = PLANE_CTL_ENABLE |
2656                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2657                     PLANE_CTL_PIPE_CSC_ENABLE;
2658
2659         switch (fb->pixel_format) {
2660         case DRM_FORMAT_RGB565:
2661                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2662                 break;
2663         case DRM_FORMAT_XRGB8888:
2664                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2665                 break;
2666         case DRM_FORMAT_XBGR8888:
2667                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2668                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2669                 break;
2670         case DRM_FORMAT_XRGB2101010:
2671                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2672                 break;
2673         case DRM_FORMAT_XBGR2101010:
2674                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2675                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2676                 break;
2677         default:
2678                 BUG();
2679         }
2680
2681         intel_fb = to_intel_framebuffer(fb);
2682         obj = intel_fb->obj;
2683
2684         /*
2685          * The stride is either expressed as a multiple of 64 bytes chunks for
2686          * linear buffers or in number of tiles for tiled buffers.
2687          */
2688         switch (obj->tiling_mode) {
2689         case I915_TILING_NONE:
2690                 stride = fb->pitches[0] >> 6;
2691                 break;
2692         case I915_TILING_X:
2693                 plane_ctl |= PLANE_CTL_TILED_X;
2694                 stride = fb->pitches[0] >> 9;
2695                 break;
2696         default:
2697                 BUG();
2698         }
2699
2700         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2701         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2702                 plane_ctl |= PLANE_CTL_ROTATE_180;
2703
2704         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2705
2706         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2707                       i915_gem_obj_ggtt_offset(obj),
2708                       x, y, fb->width, fb->height,
2709                       fb->pitches[0]);
2710
2711         I915_WRITE(PLANE_POS(pipe, 0), 0);
2712         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2713         I915_WRITE(PLANE_SIZE(pipe, 0),
2714                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2715                    (intel_crtc->config.pipe_src_w - 1));
2716         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2717         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2718
2719         POSTING_READ(PLANE_SURF(pipe, 0));
2720 }
2721
2722 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2723 static int
2724 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2725                            int x, int y, enum mode_set_atomic state)
2726 {
2727         struct drm_device *dev = crtc->dev;
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729
2730         if (dev_priv->display.disable_fbc)
2731                 dev_priv->display.disable_fbc(dev);
2732
2733         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2734
2735         return 0;
2736 }
2737
2738 void intel_display_handle_reset(struct drm_device *dev)
2739 {
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct drm_crtc *crtc;
2742
2743         /*
2744          * Flips in the rings have been nuked by the reset,
2745          * so complete all pending flips so that user space
2746          * will get its events and not get stuck.
2747          *
2748          * Also update the base address of all primary
2749          * planes to the the last fb to make sure we're
2750          * showing the correct fb after a reset.
2751          *
2752          * Need to make two loops over the crtcs so that we
2753          * don't try to grab a crtc mutex before the
2754          * pending_flip_queue really got woken up.
2755          */
2756
2757         for_each_crtc(dev, crtc) {
2758                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759                 enum plane plane = intel_crtc->plane;
2760
2761                 intel_prepare_page_flip(dev, plane);
2762                 intel_finish_page_flip_plane(dev, plane);
2763         }
2764
2765         for_each_crtc(dev, crtc) {
2766                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767
2768                 drm_modeset_lock(&crtc->mutex, NULL);
2769                 /*
2770                  * FIXME: Once we have proper support for primary planes (and
2771                  * disabling them without disabling the entire crtc) allow again
2772                  * a NULL crtc->primary->fb.
2773                  */
2774                 if (intel_crtc->active && crtc->primary->fb)
2775                         dev_priv->display.update_primary_plane(crtc,
2776                                                                crtc->primary->fb,
2777                                                                crtc->x,
2778                                                                crtc->y);
2779                 drm_modeset_unlock(&crtc->mutex);
2780         }
2781 }
2782
2783 static int
2784 intel_finish_fb(struct drm_framebuffer *old_fb)
2785 {
2786         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2787         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2788         bool was_interruptible = dev_priv->mm.interruptible;
2789         int ret;
2790
2791         /* Big Hammer, we also need to ensure that any pending
2792          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2793          * current scanout is retired before unpinning the old
2794          * framebuffer.
2795          *
2796          * This should only fail upon a hung GPU, in which case we
2797          * can safely continue.
2798          */
2799         dev_priv->mm.interruptible = false;
2800         ret = i915_gem_object_finish_gpu(obj);
2801         dev_priv->mm.interruptible = was_interruptible;
2802
2803         return ret;
2804 }
2805
2806 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2807 {
2808         struct drm_device *dev = crtc->dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2811         bool pending;
2812
2813         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2814             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2815                 return false;
2816
2817         spin_lock_irq(&dev->event_lock);
2818         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2819         spin_unlock_irq(&dev->event_lock);
2820
2821         return pending;
2822 }
2823
2824 static void intel_update_pipe_size(struct intel_crtc *crtc)
2825 {
2826         struct drm_device *dev = crtc->base.dev;
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         const struct drm_display_mode *adjusted_mode;
2829
2830         if (!i915.fastboot)
2831                 return;
2832
2833         /*
2834          * Update pipe size and adjust fitter if needed: the reason for this is
2835          * that in compute_mode_changes we check the native mode (not the pfit
2836          * mode) to see if we can flip rather than do a full mode set. In the
2837          * fastboot case, we'll flip, but if we don't update the pipesrc and
2838          * pfit state, we'll end up with a big fb scanned out into the wrong
2839          * sized surface.
2840          *
2841          * To fix this properly, we need to hoist the checks up into
2842          * compute_mode_changes (or above), check the actual pfit state and
2843          * whether the platform allows pfit disable with pipe active, and only
2844          * then update the pipesrc and pfit state, even on the flip path.
2845          */
2846
2847         adjusted_mode = &crtc->config.adjusted_mode;
2848
2849         I915_WRITE(PIPESRC(crtc->pipe),
2850                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2851                    (adjusted_mode->crtc_vdisplay - 1));
2852         if (!crtc->config.pch_pfit.enabled &&
2853             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2854              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2855                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2856                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2857                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2858         }
2859         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2860         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2861 }
2862
2863 static int
2864 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2865                     struct drm_framebuffer *fb)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870         enum pipe pipe = intel_crtc->pipe;
2871         struct drm_framebuffer *old_fb = crtc->primary->fb;
2872         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2873         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2874         int ret;
2875
2876         if (intel_crtc_has_pending_flip(crtc)) {
2877                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2878                 return -EBUSY;
2879         }
2880
2881         /* no fb bound */
2882         if (!fb) {
2883                 DRM_ERROR("No FB bound\n");
2884                 return 0;
2885         }
2886
2887         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2888                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2889                           plane_name(intel_crtc->plane),
2890                           INTEL_INFO(dev)->num_pipes);
2891                 return -EINVAL;
2892         }
2893
2894         mutex_lock(&dev->struct_mutex);
2895         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2896         if (ret == 0)
2897                 i915_gem_track_fb(old_obj, obj,
2898                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2899         mutex_unlock(&dev->struct_mutex);
2900         if (ret != 0) {
2901                 DRM_ERROR("pin & fence failed\n");
2902                 return ret;
2903         }
2904
2905         intel_update_pipe_size(intel_crtc);
2906
2907         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2908
2909         if (intel_crtc->active)
2910                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2911
2912         crtc->primary->fb = fb;
2913         crtc->x = x;
2914         crtc->y = y;
2915
2916         if (old_fb) {
2917                 if (intel_crtc->active && old_fb != fb)
2918                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2919                 mutex_lock(&dev->struct_mutex);
2920                 intel_unpin_fb_obj(old_obj);
2921                 mutex_unlock(&dev->struct_mutex);
2922         }
2923
2924         mutex_lock(&dev->struct_mutex);
2925         intel_update_fbc(dev);
2926         mutex_unlock(&dev->struct_mutex);
2927
2928         return 0;
2929 }
2930
2931 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2932 {
2933         struct drm_device *dev = crtc->dev;
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936         int pipe = intel_crtc->pipe;
2937         u32 reg, temp;
2938
2939         /* enable normal train */
2940         reg = FDI_TX_CTL(pipe);
2941         temp = I915_READ(reg);
2942         if (IS_IVYBRIDGE(dev)) {
2943                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2944                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2945         } else {
2946                 temp &= ~FDI_LINK_TRAIN_NONE;
2947                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2948         }
2949         I915_WRITE(reg, temp);
2950
2951         reg = FDI_RX_CTL(pipe);
2952         temp = I915_READ(reg);
2953         if (HAS_PCH_CPT(dev)) {
2954                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2955                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2956         } else {
2957                 temp &= ~FDI_LINK_TRAIN_NONE;
2958                 temp |= FDI_LINK_TRAIN_NONE;
2959         }
2960         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2961
2962         /* wait one idle pattern time */
2963         POSTING_READ(reg);
2964         udelay(1000);
2965
2966         /* IVB wants error correction enabled */
2967         if (IS_IVYBRIDGE(dev))
2968                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2969                            FDI_FE_ERRC_ENABLE);
2970 }
2971
2972 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2973 {
2974         return crtc->base.enabled && crtc->active &&
2975                 crtc->config.has_pch_encoder;
2976 }
2977
2978 static void ivb_modeset_global_resources(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_crtc *pipe_B_crtc =
2982                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2983         struct intel_crtc *pipe_C_crtc =
2984                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2985         uint32_t temp;
2986
2987         /*
2988          * When everything is off disable fdi C so that we could enable fdi B
2989          * with all lanes. Note that we don't care about enabled pipes without
2990          * an enabled pch encoder.
2991          */
2992         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2993             !pipe_has_enabled_pch(pipe_C_crtc)) {
2994                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2995                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2996
2997                 temp = I915_READ(SOUTH_CHICKEN1);
2998                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2999                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3000                 I915_WRITE(SOUTH_CHICKEN1, temp);
3001         }
3002 }
3003
3004 /* The FDI link training functions for ILK/Ibexpeak. */
3005 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3006 {
3007         struct drm_device *dev = crtc->dev;
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010         int pipe = intel_crtc->pipe;
3011         u32 reg, temp, tries;
3012
3013         /* FDI needs bits from pipe first */
3014         assert_pipe_enabled(dev_priv, pipe);
3015
3016         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3017            for train result */
3018         reg = FDI_RX_IMR(pipe);
3019         temp = I915_READ(reg);
3020         temp &= ~FDI_RX_SYMBOL_LOCK;
3021         temp &= ~FDI_RX_BIT_LOCK;
3022         I915_WRITE(reg, temp);
3023         I915_READ(reg);
3024         udelay(150);
3025
3026         /* enable CPU FDI TX and PCH FDI RX */
3027         reg = FDI_TX_CTL(pipe);
3028         temp = I915_READ(reg);
3029         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3030         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3031         temp &= ~FDI_LINK_TRAIN_NONE;
3032         temp |= FDI_LINK_TRAIN_PATTERN_1;
3033         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3034
3035         reg = FDI_RX_CTL(pipe);
3036         temp = I915_READ(reg);
3037         temp &= ~FDI_LINK_TRAIN_NONE;
3038         temp |= FDI_LINK_TRAIN_PATTERN_1;
3039         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3040
3041         POSTING_READ(reg);
3042         udelay(150);
3043
3044         /* Ironlake workaround, enable clock pointer after FDI enable*/
3045         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3046         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3047                    FDI_RX_PHASE_SYNC_POINTER_EN);
3048
3049         reg = FDI_RX_IIR(pipe);
3050         for (tries = 0; tries < 5; tries++) {
3051                 temp = I915_READ(reg);
3052                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3053
3054                 if ((temp & FDI_RX_BIT_LOCK)) {
3055                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3056                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3057                         break;
3058                 }
3059         }
3060         if (tries == 5)
3061                 DRM_ERROR("FDI train 1 fail!\n");
3062
3063         /* Train 2 */
3064         reg = FDI_TX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         temp &= ~FDI_LINK_TRAIN_NONE;
3067         temp |= FDI_LINK_TRAIN_PATTERN_2;
3068         I915_WRITE(reg, temp);
3069
3070         reg = FDI_RX_CTL(pipe);
3071         temp = I915_READ(reg);
3072         temp &= ~FDI_LINK_TRAIN_NONE;
3073         temp |= FDI_LINK_TRAIN_PATTERN_2;
3074         I915_WRITE(reg, temp);
3075
3076         POSTING_READ(reg);
3077         udelay(150);
3078
3079         reg = FDI_RX_IIR(pipe);
3080         for (tries = 0; tries < 5; tries++) {
3081                 temp = I915_READ(reg);
3082                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3083
3084                 if (temp & FDI_RX_SYMBOL_LOCK) {
3085                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3086                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3087                         break;
3088                 }
3089         }
3090         if (tries == 5)
3091                 DRM_ERROR("FDI train 2 fail!\n");
3092
3093         DRM_DEBUG_KMS("FDI train done\n");
3094
3095 }
3096
3097 static const int snb_b_fdi_train_param[] = {
3098         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3099         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3100         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3101         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3102 };
3103
3104 /* The FDI link training functions for SNB/Cougarpoint. */
3105 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3106 {
3107         struct drm_device *dev = crtc->dev;
3108         struct drm_i915_private *dev_priv = dev->dev_private;
3109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110         int pipe = intel_crtc->pipe;
3111         u32 reg, temp, i, retry;
3112
3113         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3114            for train result */
3115         reg = FDI_RX_IMR(pipe);
3116         temp = I915_READ(reg);
3117         temp &= ~FDI_RX_SYMBOL_LOCK;
3118         temp &= ~FDI_RX_BIT_LOCK;
3119         I915_WRITE(reg, temp);
3120
3121         POSTING_READ(reg);
3122         udelay(150);
3123
3124         /* enable CPU FDI TX and PCH FDI RX */
3125         reg = FDI_TX_CTL(pipe);
3126         temp = I915_READ(reg);
3127         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3128         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3129         temp &= ~FDI_LINK_TRAIN_NONE;
3130         temp |= FDI_LINK_TRAIN_PATTERN_1;
3131         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3132         /* SNB-B */
3133         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3134         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3135
3136         I915_WRITE(FDI_RX_MISC(pipe),
3137                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3138
3139         reg = FDI_RX_CTL(pipe);
3140         temp = I915_READ(reg);
3141         if (HAS_PCH_CPT(dev)) {
3142                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3143                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3144         } else {
3145                 temp &= ~FDI_LINK_TRAIN_NONE;
3146                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3147         }
3148         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(150);
3152
3153         for (i = 0; i < 4; i++) {
3154                 reg = FDI_TX_CTL(pipe);
3155                 temp = I915_READ(reg);
3156                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3157                 temp |= snb_b_fdi_train_param[i];
3158                 I915_WRITE(reg, temp);
3159
3160                 POSTING_READ(reg);
3161                 udelay(500);
3162
3163                 for (retry = 0; retry < 5; retry++) {
3164                         reg = FDI_RX_IIR(pipe);
3165                         temp = I915_READ(reg);
3166                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3167                         if (temp & FDI_RX_BIT_LOCK) {
3168                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3169                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3170                                 break;
3171                         }
3172                         udelay(50);
3173                 }
3174                 if (retry < 5)
3175                         break;
3176         }
3177         if (i == 4)
3178                 DRM_ERROR("FDI train 1 fail!\n");
3179
3180         /* Train 2 */
3181         reg = FDI_TX_CTL(pipe);
3182         temp = I915_READ(reg);
3183         temp &= ~FDI_LINK_TRAIN_NONE;
3184         temp |= FDI_LINK_TRAIN_PATTERN_2;
3185         if (IS_GEN6(dev)) {
3186                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3187                 /* SNB-B */
3188                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3189         }
3190         I915_WRITE(reg, temp);
3191
3192         reg = FDI_RX_CTL(pipe);
3193         temp = I915_READ(reg);
3194         if (HAS_PCH_CPT(dev)) {
3195                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3196                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3197         } else {
3198                 temp &= ~FDI_LINK_TRAIN_NONE;
3199                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3200         }
3201         I915_WRITE(reg, temp);
3202
3203         POSTING_READ(reg);
3204         udelay(150);
3205
3206         for (i = 0; i < 4; i++) {
3207                 reg = FDI_TX_CTL(pipe);
3208                 temp = I915_READ(reg);
3209                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3210                 temp |= snb_b_fdi_train_param[i];
3211                 I915_WRITE(reg, temp);
3212
3213                 POSTING_READ(reg);
3214                 udelay(500);
3215
3216                 for (retry = 0; retry < 5; retry++) {
3217                         reg = FDI_RX_IIR(pipe);
3218                         temp = I915_READ(reg);
3219                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3220                         if (temp & FDI_RX_SYMBOL_LOCK) {
3221                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3222                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3223                                 break;
3224                         }
3225                         udelay(50);
3226                 }
3227                 if (retry < 5)
3228                         break;
3229         }
3230         if (i == 4)
3231                 DRM_ERROR("FDI train 2 fail!\n");
3232
3233         DRM_DEBUG_KMS("FDI train done.\n");
3234 }
3235
3236 /* Manual link training for Ivy Bridge A0 parts */
3237 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         int pipe = intel_crtc->pipe;
3243         u32 reg, temp, i, j;
3244
3245         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3246            for train result */
3247         reg = FDI_RX_IMR(pipe);
3248         temp = I915_READ(reg);
3249         temp &= ~FDI_RX_SYMBOL_LOCK;
3250         temp &= ~FDI_RX_BIT_LOCK;
3251         I915_WRITE(reg, temp);
3252
3253         POSTING_READ(reg);
3254         udelay(150);
3255
3256         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3257                       I915_READ(FDI_RX_IIR(pipe)));
3258
3259         /* Try each vswing and preemphasis setting twice before moving on */
3260         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3261                 /* disable first in case we need to retry */
3262                 reg = FDI_TX_CTL(pipe);
3263                 temp = I915_READ(reg);
3264                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3265                 temp &= ~FDI_TX_ENABLE;
3266                 I915_WRITE(reg, temp);
3267
3268                 reg = FDI_RX_CTL(pipe);
3269                 temp = I915_READ(reg);
3270                 temp &= ~FDI_LINK_TRAIN_AUTO;
3271                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3272                 temp &= ~FDI_RX_ENABLE;
3273                 I915_WRITE(reg, temp);
3274
3275                 /* enable CPU FDI TX and PCH FDI RX */
3276                 reg = FDI_TX_CTL(pipe);
3277                 temp = I915_READ(reg);
3278                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3279                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3280                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3281                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3282                 temp |= snb_b_fdi_train_param[j/2];
3283                 temp |= FDI_COMPOSITE_SYNC;
3284                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3285
3286                 I915_WRITE(FDI_RX_MISC(pipe),
3287                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3288
3289                 reg = FDI_RX_CTL(pipe);
3290                 temp = I915_READ(reg);
3291                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3292                 temp |= FDI_COMPOSITE_SYNC;
3293                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3294
3295                 POSTING_READ(reg);
3296                 udelay(1); /* should be 0.5us */
3297
3298                 for (i = 0; i < 4; i++) {
3299                         reg = FDI_RX_IIR(pipe);
3300                         temp = I915_READ(reg);
3301                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3302
3303                         if (temp & FDI_RX_BIT_LOCK ||
3304                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3305                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3306                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3307                                               i);
3308                                 break;
3309                         }
3310                         udelay(1); /* should be 0.5us */
3311                 }
3312                 if (i == 4) {
3313                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3314                         continue;
3315                 }
3316
3317                 /* Train 2 */
3318                 reg = FDI_TX_CTL(pipe);
3319                 temp = I915_READ(reg);
3320                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3321                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3322                 I915_WRITE(reg, temp);
3323
3324                 reg = FDI_RX_CTL(pipe);
3325                 temp = I915_READ(reg);
3326                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3327                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3328                 I915_WRITE(reg, temp);
3329
3330                 POSTING_READ(reg);
3331                 udelay(2); /* should be 1.5us */
3332
3333                 for (i = 0; i < 4; i++) {
3334                         reg = FDI_RX_IIR(pipe);
3335                         temp = I915_READ(reg);
3336                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3337
3338                         if (temp & FDI_RX_SYMBOL_LOCK ||
3339                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3340                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3341                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3342                                               i);
3343                                 goto train_done;
3344                         }
3345                         udelay(2); /* should be 1.5us */
3346                 }
3347                 if (i == 4)
3348                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3349         }
3350
3351 train_done:
3352         DRM_DEBUG_KMS("FDI train done.\n");
3353 }
3354
3355 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3356 {
3357         struct drm_device *dev = intel_crtc->base.dev;
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         int pipe = intel_crtc->pipe;
3360         u32 reg, temp;
3361
3362
3363         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3364         reg = FDI_RX_CTL(pipe);
3365         temp = I915_READ(reg);
3366         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3367         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3368         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3369         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3370
3371         POSTING_READ(reg);
3372         udelay(200);
3373
3374         /* Switch from Rawclk to PCDclk */
3375         temp = I915_READ(reg);
3376         I915_WRITE(reg, temp | FDI_PCDCLK);
3377
3378         POSTING_READ(reg);
3379         udelay(200);
3380
3381         /* Enable CPU FDI TX PLL, always on for Ironlake */
3382         reg = FDI_TX_CTL(pipe);
3383         temp = I915_READ(reg);
3384         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3385                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3386
3387                 POSTING_READ(reg);
3388                 udelay(100);
3389         }
3390 }
3391
3392 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3393 {
3394         struct drm_device *dev = intel_crtc->base.dev;
3395         struct drm_i915_private *dev_priv = dev->dev_private;
3396         int pipe = intel_crtc->pipe;
3397         u32 reg, temp;
3398
3399         /* Switch from PCDclk to Rawclk */
3400         reg = FDI_RX_CTL(pipe);
3401         temp = I915_READ(reg);
3402         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3403
3404         /* Disable CPU FDI TX PLL */
3405         reg = FDI_TX_CTL(pipe);
3406         temp = I915_READ(reg);
3407         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3408
3409         POSTING_READ(reg);
3410         udelay(100);
3411
3412         reg = FDI_RX_CTL(pipe);
3413         temp = I915_READ(reg);
3414         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3415
3416         /* Wait for the clocks to turn off. */
3417         POSTING_READ(reg);
3418         udelay(100);
3419 }
3420
3421 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3422 {
3423         struct drm_device *dev = crtc->dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426         int pipe = intel_crtc->pipe;
3427         u32 reg, temp;
3428
3429         /* disable CPU FDI tx and PCH FDI rx */
3430         reg = FDI_TX_CTL(pipe);
3431         temp = I915_READ(reg);
3432         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3433         POSTING_READ(reg);
3434
3435         reg = FDI_RX_CTL(pipe);
3436         temp = I915_READ(reg);
3437         temp &= ~(0x7 << 16);
3438         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3439         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3440
3441         POSTING_READ(reg);
3442         udelay(100);
3443
3444         /* Ironlake workaround, disable clock pointer after downing FDI */
3445         if (HAS_PCH_IBX(dev))
3446                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447
3448         /* still set train pattern 1 */
3449         reg = FDI_TX_CTL(pipe);
3450         temp = I915_READ(reg);
3451         temp &= ~FDI_LINK_TRAIN_NONE;
3452         temp |= FDI_LINK_TRAIN_PATTERN_1;
3453         I915_WRITE(reg, temp);
3454
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         if (HAS_PCH_CPT(dev)) {
3458                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3459                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3460         } else {
3461                 temp &= ~FDI_LINK_TRAIN_NONE;
3462                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3463         }
3464         /* BPC in FDI rx is consistent with that in PIPECONF */
3465         temp &= ~(0x07 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471 }
3472
3473 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3474 {
3475         struct intel_crtc *crtc;
3476
3477         /* Note that we don't need to be called with mode_config.lock here
3478          * as our list of CRTC objects is static for the lifetime of the
3479          * device and so cannot disappear as we iterate. Similarly, we can
3480          * happily treat the predicates as racy, atomic checks as userspace
3481          * cannot claim and pin a new fb without at least acquring the
3482          * struct_mutex and so serialising with us.
3483          */
3484         for_each_intel_crtc(dev, crtc) {
3485                 if (atomic_read(&crtc->unpin_work_count) == 0)
3486                         continue;
3487
3488                 if (crtc->unpin_work)
3489                         intel_wait_for_vblank(dev, crtc->pipe);
3490
3491                 return true;
3492         }
3493
3494         return false;
3495 }
3496
3497 static void page_flip_completed(struct intel_crtc *intel_crtc)
3498 {
3499         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3500         struct intel_unpin_work *work = intel_crtc->unpin_work;
3501
3502         /* ensure that the unpin work is consistent wrt ->pending. */
3503         smp_rmb();
3504         intel_crtc->unpin_work = NULL;
3505
3506         if (work->event)
3507                 drm_send_vblank_event(intel_crtc->base.dev,
3508                                       intel_crtc->pipe,
3509                                       work->event);
3510
3511         drm_crtc_vblank_put(&intel_crtc->base);
3512
3513         wake_up_all(&dev_priv->pending_flip_queue);
3514         queue_work(dev_priv->wq, &work->work);
3515
3516         trace_i915_flip_complete(intel_crtc->plane,
3517                                  work->pending_flip_obj);
3518 }
3519
3520 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3521 {
3522         struct drm_device *dev = crtc->dev;
3523         struct drm_i915_private *dev_priv = dev->dev_private;
3524
3525         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3526         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3527                                        !intel_crtc_has_pending_flip(crtc),
3528                                        60*HZ) == 0)) {
3529                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530
3531                 spin_lock_irq(&dev->event_lock);
3532                 if (intel_crtc->unpin_work) {
3533                         WARN_ONCE(1, "Removing stuck page flip\n");
3534                         page_flip_completed(intel_crtc);
3535                 }
3536                 spin_unlock_irq(&dev->event_lock);
3537         }
3538
3539         if (crtc->primary->fb) {
3540                 mutex_lock(&dev->struct_mutex);
3541                 intel_finish_fb(crtc->primary->fb);
3542                 mutex_unlock(&dev->struct_mutex);
3543         }
3544 }
3545
3546 /* Program iCLKIP clock to the desired frequency */
3547 static void lpt_program_iclkip(struct drm_crtc *crtc)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3552         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3553         u32 temp;
3554
3555         mutex_lock(&dev_priv->dpio_lock);
3556
3557         /* It is necessary to ungate the pixclk gate prior to programming
3558          * the divisors, and gate it back when it is done.
3559          */
3560         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3561
3562         /* Disable SSCCTL */
3563         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3564                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3565                                 SBI_SSCCTL_DISABLE,
3566                         SBI_ICLK);
3567
3568         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3569         if (clock == 20000) {
3570                 auxdiv = 1;
3571                 divsel = 0x41;
3572                 phaseinc = 0x20;
3573         } else {
3574                 /* The iCLK virtual clock root frequency is in MHz,
3575                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3576                  * divisors, it is necessary to divide one by another, so we
3577                  * convert the virtual clock precision to KHz here for higher
3578                  * precision.
3579                  */
3580                 u32 iclk_virtual_root_freq = 172800 * 1000;
3581                 u32 iclk_pi_range = 64;
3582                 u32 desired_divisor, msb_divisor_value, pi_value;
3583
3584                 desired_divisor = (iclk_virtual_root_freq / clock);
3585                 msb_divisor_value = desired_divisor / iclk_pi_range;
3586                 pi_value = desired_divisor % iclk_pi_range;
3587
3588                 auxdiv = 0;
3589                 divsel = msb_divisor_value - 2;
3590                 phaseinc = pi_value;
3591         }
3592
3593         /* This should not happen with any sane values */
3594         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3595                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3596         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3597                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3598
3599         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3600                         clock,
3601                         auxdiv,
3602                         divsel,
3603                         phasedir,
3604                         phaseinc);
3605
3606         /* Program SSCDIVINTPHASE6 */
3607         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3608         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3609         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3610         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3611         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3612         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3613         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3614         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3615
3616         /* Program SSCAUXDIV */
3617         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3618         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3619         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3620         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3621
3622         /* Enable modulator and associated divider */
3623         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3624         temp &= ~SBI_SSCCTL_DISABLE;
3625         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3626
3627         /* Wait for initialization time */
3628         udelay(24);
3629
3630         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3631
3632         mutex_unlock(&dev_priv->dpio_lock);
3633 }
3634
3635 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3636                                                 enum pipe pch_transcoder)
3637 {
3638         struct drm_device *dev = crtc->base.dev;
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3641
3642         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3643                    I915_READ(HTOTAL(cpu_transcoder)));
3644         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3645                    I915_READ(HBLANK(cpu_transcoder)));
3646         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3647                    I915_READ(HSYNC(cpu_transcoder)));
3648
3649         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3650                    I915_READ(VTOTAL(cpu_transcoder)));
3651         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3652                    I915_READ(VBLANK(cpu_transcoder)));
3653         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3654                    I915_READ(VSYNC(cpu_transcoder)));
3655         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3656                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3657 }
3658
3659 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3660 {
3661         struct drm_i915_private *dev_priv = dev->dev_private;
3662         uint32_t temp;
3663
3664         temp = I915_READ(SOUTH_CHICKEN1);
3665         if (temp & FDI_BC_BIFURCATION_SELECT)
3666                 return;
3667
3668         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3669         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3670
3671         temp |= FDI_BC_BIFURCATION_SELECT;
3672         DRM_DEBUG_KMS("enabling fdi C rx\n");
3673         I915_WRITE(SOUTH_CHICKEN1, temp);
3674         POSTING_READ(SOUTH_CHICKEN1);
3675 }
3676
3677 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3678 {
3679         struct drm_device *dev = intel_crtc->base.dev;
3680         struct drm_i915_private *dev_priv = dev->dev_private;
3681
3682         switch (intel_crtc->pipe) {
3683         case PIPE_A:
3684                 break;
3685         case PIPE_B:
3686                 if (intel_crtc->config.fdi_lanes > 2)
3687                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3688                 else
3689                         cpt_enable_fdi_bc_bifurcation(dev);
3690
3691                 break;
3692         case PIPE_C:
3693                 cpt_enable_fdi_bc_bifurcation(dev);
3694
3695                 break;
3696         default:
3697                 BUG();
3698         }
3699 }
3700
3701 /*
3702  * Enable PCH resources required for PCH ports:
3703  *   - PCH PLLs
3704  *   - FDI training & RX/TX
3705  *   - update transcoder timings
3706  *   - DP transcoding bits
3707  *   - transcoder
3708  */
3709 static void ironlake_pch_enable(struct drm_crtc *crtc)
3710 {
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714         int pipe = intel_crtc->pipe;
3715         u32 reg, temp;
3716
3717         assert_pch_transcoder_disabled(dev_priv, pipe);
3718
3719         if (IS_IVYBRIDGE(dev))
3720                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3721
3722         /* Write the TU size bits before fdi link training, so that error
3723          * detection works. */
3724         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3725                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3726
3727         /* For PCH output, training FDI link */
3728         dev_priv->display.fdi_link_train(crtc);
3729
3730         /* We need to program the right clock selection before writing the pixel
3731          * mutliplier into the DPLL. */
3732         if (HAS_PCH_CPT(dev)) {
3733                 u32 sel;
3734
3735                 temp = I915_READ(PCH_DPLL_SEL);
3736                 temp |= TRANS_DPLL_ENABLE(pipe);
3737                 sel = TRANS_DPLLB_SEL(pipe);
3738                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3739                         temp |= sel;
3740                 else
3741                         temp &= ~sel;
3742                 I915_WRITE(PCH_DPLL_SEL, temp);
3743         }
3744
3745         /* XXX: pch pll's can be enabled any time before we enable the PCH
3746          * transcoder, and we actually should do this to not upset any PCH
3747          * transcoder that already use the clock when we share it.
3748          *
3749          * Note that enable_shared_dpll tries to do the right thing, but
3750          * get_shared_dpll unconditionally resets the pll - we need that to have
3751          * the right LVDS enable sequence. */
3752         intel_enable_shared_dpll(intel_crtc);
3753
3754         /* set transcoder timing, panel must allow it */
3755         assert_panel_unlocked(dev_priv, pipe);
3756         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3757
3758         intel_fdi_normal_train(crtc);
3759
3760         /* For PCH DP, enable TRANS_DP_CTL */
3761         if (HAS_PCH_CPT(dev) &&
3762             (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3763              intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3764                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3765                 reg = TRANS_DP_CTL(pipe);
3766                 temp = I915_READ(reg);
3767                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3768                           TRANS_DP_SYNC_MASK |
3769                           TRANS_DP_BPC_MASK);
3770                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3771                          TRANS_DP_ENH_FRAMING);
3772                 temp |= bpc << 9; /* same format but at 11:9 */
3773
3774                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3775                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3776                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3777                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3778
3779                 switch (intel_trans_dp_port_sel(crtc)) {
3780                 case PCH_DP_B:
3781                         temp |= TRANS_DP_PORT_SEL_B;
3782                         break;
3783                 case PCH_DP_C:
3784                         temp |= TRANS_DP_PORT_SEL_C;
3785                         break;
3786                 case PCH_DP_D:
3787                         temp |= TRANS_DP_PORT_SEL_D;
3788                         break;
3789                 default:
3790                         BUG();
3791                 }
3792
3793                 I915_WRITE(reg, temp);
3794         }
3795
3796         ironlake_enable_pch_transcoder(dev_priv, pipe);
3797 }
3798
3799 static void lpt_pch_enable(struct drm_crtc *crtc)
3800 {
3801         struct drm_device *dev = crtc->dev;
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3805
3806         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3807
3808         lpt_program_iclkip(crtc);
3809
3810         /* Set transcoder timing. */
3811         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3812
3813         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3814 }
3815
3816 void intel_put_shared_dpll(struct intel_crtc *crtc)
3817 {
3818         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3819
3820         if (pll == NULL)
3821                 return;
3822
3823         if (pll->refcount == 0) {
3824                 WARN(1, "bad %s refcount\n", pll->name);
3825                 return;
3826         }
3827
3828         if (--pll->refcount == 0) {
3829                 WARN_ON(pll->on);
3830                 WARN_ON(pll->active);
3831         }
3832
3833         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3834 }
3835
3836 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3837 {
3838         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3839         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3840         enum intel_dpll_id i;
3841
3842         if (pll) {
3843                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3844                               crtc->base.base.id, pll->name);
3845                 intel_put_shared_dpll(crtc);
3846         }
3847
3848         if (HAS_PCH_IBX(dev_priv->dev)) {
3849                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3850                 i = (enum intel_dpll_id) crtc->pipe;
3851                 pll = &dev_priv->shared_dplls[i];
3852
3853                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3854                               crtc->base.base.id, pll->name);
3855
3856                 WARN_ON(pll->refcount);
3857
3858                 goto found;
3859         }
3860
3861         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3862                 pll = &dev_priv->shared_dplls[i];
3863
3864                 /* Only want to check enabled timings first */
3865                 if (pll->refcount == 0)
3866                         continue;
3867
3868                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3869                            sizeof(pll->hw_state)) == 0) {
3870                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3871                                       crtc->base.base.id,
3872                                       pll->name, pll->refcount, pll->active);
3873
3874                         goto found;
3875                 }
3876         }
3877
3878         /* Ok no matching timings, maybe there's a free one? */
3879         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3880                 pll = &dev_priv->shared_dplls[i];
3881                 if (pll->refcount == 0) {
3882                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3883                                       crtc->base.base.id, pll->name);
3884                         goto found;
3885                 }
3886         }
3887
3888         return NULL;
3889
3890 found:
3891         if (pll->refcount == 0)
3892                 pll->hw_state = crtc->config.dpll_hw_state;
3893
3894         crtc->config.shared_dpll = i;
3895         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3896                          pipe_name(crtc->pipe));
3897
3898         pll->refcount++;
3899
3900         return pll;
3901 }
3902
3903 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3904 {
3905         struct drm_i915_private *dev_priv = dev->dev_private;
3906         int dslreg = PIPEDSL(pipe);
3907         u32 temp;
3908
3909         temp = I915_READ(dslreg);
3910         udelay(500);
3911         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3912                 if (wait_for(I915_READ(dslreg) != temp, 5))
3913                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3914         }
3915 }
3916
3917 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3918 {
3919         struct drm_device *dev = crtc->base.dev;
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         int pipe = crtc->pipe;
3922
3923         if (crtc->config.pch_pfit.enabled) {
3924                 /* Force use of hard-coded filter coefficients
3925                  * as some pre-programmed values are broken,
3926                  * e.g. x201.
3927                  */
3928                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3929                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3930                                                  PF_PIPE_SEL_IVB(pipe));
3931                 else
3932                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3933                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3934                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3935         }
3936 }
3937
3938 static void intel_enable_planes(struct drm_crtc *crtc)
3939 {
3940         struct drm_device *dev = crtc->dev;
3941         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3942         struct drm_plane *plane;
3943         struct intel_plane *intel_plane;
3944
3945         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3946                 intel_plane = to_intel_plane(plane);
3947                 if (intel_plane->pipe == pipe)
3948                         intel_plane_restore(&intel_plane->base);
3949         }
3950 }
3951
3952 static void intel_disable_planes(struct drm_crtc *crtc)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3956         struct drm_plane *plane;
3957         struct intel_plane *intel_plane;
3958
3959         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3960                 intel_plane = to_intel_plane(plane);
3961                 if (intel_plane->pipe == pipe)
3962                         intel_plane_disable(&intel_plane->base);
3963         }
3964 }
3965
3966 void hsw_enable_ips(struct intel_crtc *crtc)
3967 {
3968         struct drm_device *dev = crtc->base.dev;
3969         struct drm_i915_private *dev_priv = dev->dev_private;
3970
3971         if (!crtc->config.ips_enabled)
3972                 return;
3973
3974         /* We can only enable IPS after we enable a plane and wait for a vblank */
3975         intel_wait_for_vblank(dev, crtc->pipe);
3976
3977         assert_plane_enabled(dev_priv, crtc->plane);
3978         if (IS_BROADWELL(dev)) {
3979                 mutex_lock(&dev_priv->rps.hw_lock);
3980                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3981                 mutex_unlock(&dev_priv->rps.hw_lock);
3982                 /* Quoting Art Runyan: "its not safe to expect any particular
3983                  * value in IPS_CTL bit 31 after enabling IPS through the
3984                  * mailbox." Moreover, the mailbox may return a bogus state,
3985                  * so we need to just enable it and continue on.
3986                  */
3987         } else {
3988                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3989                 /* The bit only becomes 1 in the next vblank, so this wait here
3990                  * is essentially intel_wait_for_vblank. If we don't have this
3991                  * and don't wait for vblanks until the end of crtc_enable, then
3992                  * the HW state readout code will complain that the expected
3993                  * IPS_CTL value is not the one we read. */
3994                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3995                         DRM_ERROR("Timed out waiting for IPS enable\n");
3996         }
3997 }
3998
3999 void hsw_disable_ips(struct intel_crtc *crtc)
4000 {
4001         struct drm_device *dev = crtc->base.dev;
4002         struct drm_i915_private *dev_priv = dev->dev_private;
4003
4004         if (!crtc->config.ips_enabled)
4005                 return;
4006
4007         assert_plane_enabled(dev_priv, crtc->plane);
4008         if (IS_BROADWELL(dev)) {
4009                 mutex_lock(&dev_priv->rps.hw_lock);
4010                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4011                 mutex_unlock(&dev_priv->rps.hw_lock);
4012                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4013                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4014                         DRM_ERROR("Timed out waiting for IPS disable\n");
4015         } else {
4016                 I915_WRITE(IPS_CTL, 0);
4017                 POSTING_READ(IPS_CTL);
4018         }
4019
4020         /* We need to wait for a vblank before we can disable the plane. */
4021         intel_wait_for_vblank(dev, crtc->pipe);
4022 }
4023
4024 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4025 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4026 {
4027         struct drm_device *dev = crtc->dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4030         enum pipe pipe = intel_crtc->pipe;
4031         int palreg = PALETTE(pipe);
4032         int i;
4033         bool reenable_ips = false;
4034
4035         /* The clocks have to be on to load the palette. */
4036         if (!crtc->enabled || !intel_crtc->active)
4037                 return;
4038
4039         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4040                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4041                         assert_dsi_pll_enabled(dev_priv);
4042                 else
4043                         assert_pll_enabled(dev_priv, pipe);
4044         }
4045
4046         /* use legacy palette for Ironlake */
4047         if (!HAS_GMCH_DISPLAY(dev))
4048                 palreg = LGC_PALETTE(pipe);
4049
4050         /* Workaround : Do not read or write the pipe palette/gamma data while
4051          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4052          */
4053         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4054             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4055              GAMMA_MODE_MODE_SPLIT)) {
4056                 hsw_disable_ips(intel_crtc);
4057                 reenable_ips = true;
4058         }
4059
4060         for (i = 0; i < 256; i++) {
4061                 I915_WRITE(palreg + 4 * i,
4062                            (intel_crtc->lut_r[i] << 16) |
4063                            (intel_crtc->lut_g[i] << 8) |
4064                            intel_crtc->lut_b[i]);
4065         }
4066
4067         if (reenable_ips)
4068                 hsw_enable_ips(intel_crtc);
4069 }
4070
4071 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4072 {
4073         if (!enable && intel_crtc->overlay) {
4074                 struct drm_device *dev = intel_crtc->base.dev;
4075                 struct drm_i915_private *dev_priv = dev->dev_private;
4076
4077                 mutex_lock(&dev->struct_mutex);
4078                 dev_priv->mm.interruptible = false;
4079                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4080                 dev_priv->mm.interruptible = true;
4081                 mutex_unlock(&dev->struct_mutex);
4082         }
4083
4084         /* Let userspace switch the overlay on again. In most cases userspace
4085          * has to recompute where to put it anyway.
4086          */
4087 }
4088
4089 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4090 {
4091         struct drm_device *dev = crtc->dev;
4092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093         int pipe = intel_crtc->pipe;
4094
4095         intel_enable_primary_hw_plane(crtc->primary, crtc);
4096         intel_enable_planes(crtc);
4097         intel_crtc_update_cursor(crtc, true);
4098         intel_crtc_dpms_overlay(intel_crtc, true);
4099
4100         hsw_enable_ips(intel_crtc);
4101
4102         mutex_lock(&dev->struct_mutex);
4103         intel_update_fbc(dev);
4104         mutex_unlock(&dev->struct_mutex);
4105
4106         /*
4107          * FIXME: Once we grow proper nuclear flip support out of this we need
4108          * to compute the mask of flip planes precisely. For the time being
4109          * consider this a flip from a NULL plane.
4110          */
4111         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4112 }
4113
4114 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         int plane = intel_crtc->plane;
4121
4122         intel_crtc_wait_for_pending_flips(crtc);
4123
4124         if (dev_priv->fbc.plane == plane)
4125                 intel_disable_fbc(dev);
4126
4127         hsw_disable_ips(intel_crtc);
4128
4129         intel_crtc_dpms_overlay(intel_crtc, false);
4130         intel_crtc_update_cursor(crtc, false);
4131         intel_disable_planes(crtc);
4132         intel_disable_primary_hw_plane(crtc->primary, crtc);
4133
4134         /*
4135          * FIXME: Once we grow proper nuclear flip support out of this we need
4136          * to compute the mask of flip planes precisely. For the time being
4137          * consider this a flip to a NULL plane.
4138          */
4139         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4140 }
4141
4142 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4143 {
4144         struct drm_device *dev = crtc->dev;
4145         struct drm_i915_private *dev_priv = dev->dev_private;
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         struct intel_encoder *encoder;
4148         int pipe = intel_crtc->pipe;
4149
4150         WARN_ON(!crtc->enabled);
4151
4152         if (intel_crtc->active)
4153                 return;
4154
4155         if (intel_crtc->config.has_pch_encoder)
4156                 intel_prepare_shared_dpll(intel_crtc);
4157
4158         if (intel_crtc->config.has_dp_encoder)
4159                 intel_dp_set_m_n(intel_crtc);
4160
4161         intel_set_pipe_timings(intel_crtc);
4162
4163         if (intel_crtc->config.has_pch_encoder) {
4164                 intel_cpu_transcoder_set_m_n(intel_crtc,
4165                                      &intel_crtc->config.fdi_m_n, NULL);
4166         }
4167
4168         ironlake_set_pipeconf(crtc);
4169
4170         intel_crtc->active = true;
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->pre_enable)
4177                         encoder->pre_enable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 /* Note: FDI PLL enabling _must_ be done before we enable the
4181                  * cpu pipes, hence this is separate from all the other fdi/pch
4182                  * enabling. */
4183                 ironlake_fdi_pll_enable(intel_crtc);
4184         } else {
4185                 assert_fdi_tx_disabled(dev_priv, pipe);
4186                 assert_fdi_rx_disabled(dev_priv, pipe);
4187         }
4188
4189         ironlake_pfit_enable(intel_crtc);
4190
4191         /*
4192          * On ILK+ LUT must be loaded before the pipe is running but with
4193          * clocks enabled
4194          */
4195         intel_crtc_load_lut(crtc);
4196
4197         intel_update_watermarks(crtc);
4198         intel_enable_pipe(intel_crtc);
4199
4200         if (intel_crtc->config.has_pch_encoder)
4201                 ironlake_pch_enable(crtc);
4202
4203         for_each_encoder_on_crtc(dev, crtc, encoder)
4204                 encoder->enable(encoder);
4205
4206         if (HAS_PCH_CPT(dev))
4207                 cpt_verify_modeset(dev, intel_crtc->pipe);
4208
4209         assert_vblank_disabled(crtc);
4210         drm_crtc_vblank_on(crtc);
4211
4212         intel_crtc_enable_planes(crtc);
4213 }
4214
4215 /* IPS only exists on ULT machines and is tied to pipe A. */
4216 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4217 {
4218         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4219 }
4220
4221 /*
4222  * This implements the workaround described in the "notes" section of the mode
4223  * set sequence documentation. When going from no pipes or single pipe to
4224  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4225  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4226  */
4227 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4228 {
4229         struct drm_device *dev = crtc->base.dev;
4230         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4231
4232         /* We want to get the other_active_crtc only if there's only 1 other
4233          * active crtc. */
4234         for_each_intel_crtc(dev, crtc_it) {
4235                 if (!crtc_it->active || crtc_it == crtc)
4236                         continue;
4237
4238                 if (other_active_crtc)
4239                         return;
4240
4241                 other_active_crtc = crtc_it;
4242         }
4243         if (!other_active_crtc)
4244                 return;
4245
4246         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4247         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4248 }
4249
4250 static void haswell_crtc_enable(struct drm_crtc *crtc)
4251 {
4252         struct drm_device *dev = crtc->dev;
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4255         struct intel_encoder *encoder;
4256         int pipe = intel_crtc->pipe;
4257
4258         WARN_ON(!crtc->enabled);
4259
4260         if (intel_crtc->active)
4261                 return;
4262
4263         if (intel_crtc_to_shared_dpll(intel_crtc))
4264                 intel_enable_shared_dpll(intel_crtc);
4265
4266         if (intel_crtc->config.has_dp_encoder)
4267                 intel_dp_set_m_n(intel_crtc);
4268
4269         intel_set_pipe_timings(intel_crtc);
4270
4271         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4272                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4273                            intel_crtc->config.pixel_multiplier - 1);
4274         }
4275
4276         if (intel_crtc->config.has_pch_encoder) {
4277                 intel_cpu_transcoder_set_m_n(intel_crtc,
4278                                      &intel_crtc->config.fdi_m_n, NULL);
4279         }
4280
4281         haswell_set_pipeconf(crtc);
4282
4283         intel_set_pipe_csc(crtc);
4284
4285         intel_crtc->active = true;
4286
4287         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4288         for_each_encoder_on_crtc(dev, crtc, encoder)
4289                 if (encoder->pre_enable)
4290                         encoder->pre_enable(encoder);
4291
4292         if (intel_crtc->config.has_pch_encoder) {
4293                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4294                                                       true);
4295                 dev_priv->display.fdi_link_train(crtc);
4296         }
4297
4298         intel_ddi_enable_pipe_clock(intel_crtc);
4299
4300         ironlake_pfit_enable(intel_crtc);
4301
4302         /*
4303          * On ILK+ LUT must be loaded before the pipe is running but with
4304          * clocks enabled
4305          */
4306         intel_crtc_load_lut(crtc);
4307
4308         intel_ddi_set_pipe_settings(crtc);
4309         intel_ddi_enable_transcoder_func(crtc);
4310
4311         intel_update_watermarks(crtc);
4312         intel_enable_pipe(intel_crtc);
4313
4314         if (intel_crtc->config.has_pch_encoder)
4315                 lpt_pch_enable(crtc);
4316
4317         if (intel_crtc->config.dp_encoder_is_mst)
4318                 intel_ddi_set_vc_payload_alloc(crtc, true);
4319
4320         for_each_encoder_on_crtc(dev, crtc, encoder) {
4321                 encoder->enable(encoder);
4322                 intel_opregion_notify_encoder(encoder, true);
4323         }
4324
4325         assert_vblank_disabled(crtc);
4326         drm_crtc_vblank_on(crtc);
4327
4328         /* If we change the relative order between pipe/planes enabling, we need
4329          * to change the workaround. */
4330         haswell_mode_set_planes_workaround(intel_crtc);
4331         intel_crtc_enable_planes(crtc);
4332 }
4333
4334 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4335 {
4336         struct drm_device *dev = crtc->base.dev;
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338         int pipe = crtc->pipe;
4339
4340         /* To avoid upsetting the power well on haswell only disable the pfit if
4341          * it's in use. The hw state code will make sure we get this right. */
4342         if (crtc->config.pch_pfit.enabled) {
4343                 I915_WRITE(PF_CTL(pipe), 0);
4344                 I915_WRITE(PF_WIN_POS(pipe), 0);
4345                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4346         }
4347 }
4348
4349 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4350 {
4351         struct drm_device *dev = crtc->dev;
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354         struct intel_encoder *encoder;
4355         int pipe = intel_crtc->pipe;
4356         u32 reg, temp;
4357
4358         if (!intel_crtc->active)
4359                 return;
4360
4361         intel_crtc_disable_planes(crtc);
4362
4363         drm_crtc_vblank_off(crtc);
4364         assert_vblank_disabled(crtc);
4365
4366         for_each_encoder_on_crtc(dev, crtc, encoder)
4367                 encoder->disable(encoder);
4368
4369         if (intel_crtc->config.has_pch_encoder)
4370                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4371
4372         intel_disable_pipe(intel_crtc);
4373
4374         ironlake_pfit_disable(intel_crtc);
4375
4376         for_each_encoder_on_crtc(dev, crtc, encoder)
4377                 if (encoder->post_disable)
4378                         encoder->post_disable(encoder);
4379
4380         if (intel_crtc->config.has_pch_encoder) {
4381                 ironlake_fdi_disable(crtc);
4382
4383                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4384                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4385
4386                 if (HAS_PCH_CPT(dev)) {
4387                         /* disable TRANS_DP_CTL */
4388                         reg = TRANS_DP_CTL(pipe);
4389                         temp = I915_READ(reg);
4390                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4391                                   TRANS_DP_PORT_SEL_MASK);
4392                         temp |= TRANS_DP_PORT_SEL_NONE;
4393                         I915_WRITE(reg, temp);
4394
4395                         /* disable DPLL_SEL */
4396                         temp = I915_READ(PCH_DPLL_SEL);
4397                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4398                         I915_WRITE(PCH_DPLL_SEL, temp);
4399                 }
4400
4401                 /* disable PCH DPLL */
4402                 intel_disable_shared_dpll(intel_crtc);
4403
4404                 ironlake_fdi_pll_disable(intel_crtc);
4405         }
4406
4407         intel_crtc->active = false;
4408         intel_update_watermarks(crtc);
4409
4410         mutex_lock(&dev->struct_mutex);
4411         intel_update_fbc(dev);
4412         mutex_unlock(&dev->struct_mutex);
4413 }
4414
4415 static void haswell_crtc_disable(struct drm_crtc *crtc)
4416 {
4417         struct drm_device *dev = crtc->dev;
4418         struct drm_i915_private *dev_priv = dev->dev_private;
4419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4420         struct intel_encoder *encoder;
4421         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4422
4423         if (!intel_crtc->active)
4424                 return;
4425
4426         intel_crtc_disable_planes(crtc);
4427
4428         drm_crtc_vblank_off(crtc);
4429         assert_vblank_disabled(crtc);
4430
4431         for_each_encoder_on_crtc(dev, crtc, encoder) {
4432                 intel_opregion_notify_encoder(encoder, false);
4433                 encoder->disable(encoder);
4434         }
4435
4436         if (intel_crtc->config.has_pch_encoder)
4437                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4438                                                       false);
4439         intel_disable_pipe(intel_crtc);
4440
4441         if (intel_crtc->config.dp_encoder_is_mst)
4442                 intel_ddi_set_vc_payload_alloc(crtc, false);
4443
4444         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4445
4446         ironlake_pfit_disable(intel_crtc);
4447
4448         intel_ddi_disable_pipe_clock(intel_crtc);
4449
4450         if (intel_crtc->config.has_pch_encoder) {
4451                 lpt_disable_pch_transcoder(dev_priv);
4452                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4453                                                       true);
4454                 intel_ddi_fdi_disable(crtc);
4455         }
4456
4457         for_each_encoder_on_crtc(dev, crtc, encoder)
4458                 if (encoder->post_disable)
4459                         encoder->post_disable(encoder);
4460
4461         intel_crtc->active = false;
4462         intel_update_watermarks(crtc);
4463
4464         mutex_lock(&dev->struct_mutex);
4465         intel_update_fbc(dev);
4466         mutex_unlock(&dev->struct_mutex);
4467
4468         if (intel_crtc_to_shared_dpll(intel_crtc))
4469                 intel_disable_shared_dpll(intel_crtc);
4470 }
4471
4472 static void ironlake_crtc_off(struct drm_crtc *crtc)
4473 {
4474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475         intel_put_shared_dpll(intel_crtc);
4476 }
4477
4478
4479 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4480 {
4481         struct drm_device *dev = crtc->base.dev;
4482         struct drm_i915_private *dev_priv = dev->dev_private;
4483         struct intel_crtc_config *pipe_config = &crtc->config;
4484
4485         if (!crtc->config.gmch_pfit.control)
4486                 return;
4487
4488         /*
4489          * The panel fitter should only be adjusted whilst the pipe is disabled,
4490          * according to register description and PRM.
4491          */
4492         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4493         assert_pipe_disabled(dev_priv, crtc->pipe);
4494
4495         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4496         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4497
4498         /* Border color in case we don't scale up to the full screen. Black by
4499          * default, change to something else for debugging. */
4500         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4501 }
4502
4503 static enum intel_display_power_domain port_to_power_domain(enum port port)
4504 {
4505         switch (port) {
4506         case PORT_A:
4507                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4508         case PORT_B:
4509                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4510         case PORT_C:
4511                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4512         case PORT_D:
4513                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4514         default:
4515                 WARN_ON_ONCE(1);
4516                 return POWER_DOMAIN_PORT_OTHER;
4517         }
4518 }
4519
4520 #define for_each_power_domain(domain, mask)                             \
4521         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4522                 if ((1 << (domain)) & (mask))
4523
4524 enum intel_display_power_domain
4525 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4526 {
4527         struct drm_device *dev = intel_encoder->base.dev;
4528         struct intel_digital_port *intel_dig_port;
4529
4530         switch (intel_encoder->type) {
4531         case INTEL_OUTPUT_UNKNOWN:
4532                 /* Only DDI platforms should ever use this output type */
4533                 WARN_ON_ONCE(!HAS_DDI(dev));
4534         case INTEL_OUTPUT_DISPLAYPORT:
4535         case INTEL_OUTPUT_HDMI:
4536         case INTEL_OUTPUT_EDP:
4537                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4538                 return port_to_power_domain(intel_dig_port->port);
4539         case INTEL_OUTPUT_DP_MST:
4540                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4541                 return port_to_power_domain(intel_dig_port->port);
4542         case INTEL_OUTPUT_ANALOG:
4543                 return POWER_DOMAIN_PORT_CRT;
4544         case INTEL_OUTPUT_DSI:
4545                 return POWER_DOMAIN_PORT_DSI;
4546         default:
4547                 return POWER_DOMAIN_PORT_OTHER;
4548         }
4549 }
4550
4551 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4552 {
4553         struct drm_device *dev = crtc->dev;
4554         struct intel_encoder *intel_encoder;
4555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556         enum pipe pipe = intel_crtc->pipe;
4557         unsigned long mask;
4558         enum transcoder transcoder;
4559
4560         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4561
4562         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4563         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4564         if (intel_crtc->config.pch_pfit.enabled ||
4565             intel_crtc->config.pch_pfit.force_thru)
4566                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4567
4568         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4569                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4570
4571         return mask;
4572 }
4573
4574 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4575 {
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4578         struct intel_crtc *crtc;
4579
4580         /*
4581          * First get all needed power domains, then put all unneeded, to avoid
4582          * any unnecessary toggling of the power wells.
4583          */
4584         for_each_intel_crtc(dev, crtc) {
4585                 enum intel_display_power_domain domain;
4586
4587                 if (!crtc->base.enabled)
4588                         continue;
4589
4590                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4591
4592                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4593                         intel_display_power_get(dev_priv, domain);
4594         }
4595
4596         for_each_intel_crtc(dev, crtc) {
4597                 enum intel_display_power_domain domain;
4598
4599                 for_each_power_domain(domain, crtc->enabled_power_domains)
4600                         intel_display_power_put(dev_priv, domain);
4601
4602                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4603         }
4604
4605         intel_display_set_init_power(dev_priv, false);
4606 }
4607
4608 /* returns HPLL frequency in kHz */
4609 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4610 {
4611         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4612
4613         /* Obtain SKU information */
4614         mutex_lock(&dev_priv->dpio_lock);
4615         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4616                 CCK_FUSE_HPLL_FREQ_MASK;
4617         mutex_unlock(&dev_priv->dpio_lock);
4618
4619         return vco_freq[hpll_freq] * 1000;
4620 }
4621
4622 static void vlv_update_cdclk(struct drm_device *dev)
4623 {
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625
4626         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4627         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4628                          dev_priv->vlv_cdclk_freq);
4629
4630         /*
4631          * Program the gmbus_freq based on the cdclk frequency.
4632          * BSpec erroneously claims we should aim for 4MHz, but
4633          * in fact 1MHz is the correct frequency.
4634          */
4635         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4636 }
4637
4638 /* Adjust CDclk dividers to allow high res or save power if possible */
4639 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         u32 val, cmd;
4643
4644         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4645
4646         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4647                 cmd = 2;
4648         else if (cdclk == 266667)
4649                 cmd = 1;
4650         else
4651                 cmd = 0;
4652
4653         mutex_lock(&dev_priv->rps.hw_lock);
4654         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4655         val &= ~DSPFREQGUAR_MASK;
4656         val |= (cmd << DSPFREQGUAR_SHIFT);
4657         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4658         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4659                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4660                      50)) {
4661                 DRM_ERROR("timed out waiting for CDclk change\n");
4662         }
4663         mutex_unlock(&dev_priv->rps.hw_lock);
4664
4665         if (cdclk == 400000) {
4666                 u32 divider, vco;
4667
4668                 vco = valleyview_get_vco(dev_priv);
4669                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4670
4671                 mutex_lock(&dev_priv->dpio_lock);
4672                 /* adjust cdclk divider */
4673                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4674                 val &= ~DISPLAY_FREQUENCY_VALUES;
4675                 val |= divider;
4676                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4677
4678                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4679                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4680                              50))
4681                         DRM_ERROR("timed out waiting for CDclk change\n");
4682                 mutex_unlock(&dev_priv->dpio_lock);
4683         }
4684
4685         mutex_lock(&dev_priv->dpio_lock);
4686         /* adjust self-refresh exit latency value */
4687         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4688         val &= ~0x7f;
4689
4690         /*
4691          * For high bandwidth configs, we set a higher latency in the bunit
4692          * so that the core display fetch happens in time to avoid underruns.
4693          */
4694         if (cdclk == 400000)
4695                 val |= 4500 / 250; /* 4.5 usec */
4696         else
4697                 val |= 3000 / 250; /* 3.0 usec */
4698         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4699         mutex_unlock(&dev_priv->dpio_lock);
4700
4701         vlv_update_cdclk(dev);
4702 }
4703
4704 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4705 {
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         u32 val, cmd;
4708
4709         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4710
4711         switch (cdclk) {
4712         case 400000:
4713                 cmd = 3;
4714                 break;
4715         case 333333:
4716         case 320000:
4717                 cmd = 2;
4718                 break;
4719         case 266667:
4720                 cmd = 1;
4721                 break;
4722         case 200000:
4723                 cmd = 0;
4724                 break;
4725         default:
4726                 WARN_ON(1);
4727                 return;
4728         }
4729
4730         mutex_lock(&dev_priv->rps.hw_lock);
4731         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4732         val &= ~DSPFREQGUAR_MASK_CHV;
4733         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4734         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4735         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4736                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4737                      50)) {
4738                 DRM_ERROR("timed out waiting for CDclk change\n");
4739         }
4740         mutex_unlock(&dev_priv->rps.hw_lock);
4741
4742         vlv_update_cdclk(dev);
4743 }
4744
4745 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4746                                  int max_pixclk)
4747 {
4748         int vco = valleyview_get_vco(dev_priv);
4749         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4750
4751         /* FIXME: Punit isn't quite ready yet */
4752         if (IS_CHERRYVIEW(dev_priv->dev))
4753                 return 400000;
4754
4755         /*
4756          * Really only a few cases to deal with, as only 4 CDclks are supported:
4757          *   200MHz
4758          *   267MHz
4759          *   320/333MHz (depends on HPLL freq)
4760          *   400MHz
4761          * So we check to see whether we're above 90% of the lower bin and
4762          * adjust if needed.
4763          *
4764          * We seem to get an unstable or solid color picture at 200MHz.
4765          * Not sure what's wrong. For now use 200MHz only when all pipes
4766          * are off.
4767          */
4768         if (max_pixclk > freq_320*9/10)
4769                 return 400000;
4770         else if (max_pixclk > 266667*9/10)
4771                 return freq_320;
4772         else if (max_pixclk > 0)
4773                 return 266667;
4774         else
4775                 return 200000;
4776 }
4777
4778 /* compute the max pixel clock for new configuration */
4779 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4780 {
4781         struct drm_device *dev = dev_priv->dev;
4782         struct intel_crtc *intel_crtc;
4783         int max_pixclk = 0;
4784
4785         for_each_intel_crtc(dev, intel_crtc) {
4786                 if (intel_crtc->new_enabled)
4787                         max_pixclk = max(max_pixclk,
4788                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4789         }
4790
4791         return max_pixclk;
4792 }
4793
4794 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4795                                             unsigned *prepare_pipes)
4796 {
4797         struct drm_i915_private *dev_priv = dev->dev_private;
4798         struct intel_crtc *intel_crtc;
4799         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4800
4801         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4802             dev_priv->vlv_cdclk_freq)
4803                 return;
4804
4805         /* disable/enable all currently active pipes while we change cdclk */
4806         for_each_intel_crtc(dev, intel_crtc)
4807                 if (intel_crtc->base.enabled)
4808                         *prepare_pipes |= (1 << intel_crtc->pipe);
4809 }
4810
4811 static void valleyview_modeset_global_resources(struct drm_device *dev)
4812 {
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4815         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4816
4817         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4818                 if (IS_CHERRYVIEW(dev))
4819                         cherryview_set_cdclk(dev, req_cdclk);
4820                 else
4821                         valleyview_set_cdclk(dev, req_cdclk);
4822         }
4823
4824         modeset_update_crtc_power_domains(dev);
4825 }
4826
4827 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4828 {
4829         struct drm_device *dev = crtc->dev;
4830         struct drm_i915_private *dev_priv = to_i915(dev);
4831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832         struct intel_encoder *encoder;
4833         int pipe = intel_crtc->pipe;
4834         bool is_dsi;
4835
4836         WARN_ON(!crtc->enabled);
4837
4838         if (intel_crtc->active)
4839                 return;
4840
4841         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4842
4843         if (!is_dsi) {
4844                 if (IS_CHERRYVIEW(dev))
4845                         chv_prepare_pll(intel_crtc);
4846                 else
4847                         vlv_prepare_pll(intel_crtc);
4848         }
4849
4850         if (intel_crtc->config.has_dp_encoder)
4851                 intel_dp_set_m_n(intel_crtc);
4852
4853         intel_set_pipe_timings(intel_crtc);
4854
4855         i9xx_set_pipeconf(intel_crtc);
4856
4857         intel_crtc->active = true;
4858
4859         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4860
4861         for_each_encoder_on_crtc(dev, crtc, encoder)
4862                 if (encoder->pre_pll_enable)
4863                         encoder->pre_pll_enable(encoder);
4864
4865         if (!is_dsi) {
4866                 if (IS_CHERRYVIEW(dev))
4867                         chv_enable_pll(intel_crtc);
4868                 else
4869                         vlv_enable_pll(intel_crtc);
4870         }
4871
4872         for_each_encoder_on_crtc(dev, crtc, encoder)
4873                 if (encoder->pre_enable)
4874                         encoder->pre_enable(encoder);
4875
4876         i9xx_pfit_enable(intel_crtc);
4877
4878         intel_crtc_load_lut(crtc);
4879
4880         intel_update_watermarks(crtc);
4881         intel_enable_pipe(intel_crtc);
4882
4883         for_each_encoder_on_crtc(dev, crtc, encoder)
4884                 encoder->enable(encoder);
4885
4886         assert_vblank_disabled(crtc);
4887         drm_crtc_vblank_on(crtc);
4888
4889         intel_crtc_enable_planes(crtc);
4890
4891         /* Underruns don't raise interrupts, so check manually. */
4892         i9xx_check_fifo_underruns(dev_priv);
4893 }
4894
4895 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4896 {
4897         struct drm_device *dev = crtc->base.dev;
4898         struct drm_i915_private *dev_priv = dev->dev_private;
4899
4900         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4901         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4902 }
4903
4904 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4905 {
4906         struct drm_device *dev = crtc->dev;
4907         struct drm_i915_private *dev_priv = to_i915(dev);
4908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909         struct intel_encoder *encoder;
4910         int pipe = intel_crtc->pipe;
4911
4912         WARN_ON(!crtc->enabled);
4913
4914         if (intel_crtc->active)
4915                 return;
4916
4917         i9xx_set_pll_dividers(intel_crtc);
4918
4919         if (intel_crtc->config.has_dp_encoder)
4920                 intel_dp_set_m_n(intel_crtc);
4921
4922         intel_set_pipe_timings(intel_crtc);
4923
4924         i9xx_set_pipeconf(intel_crtc);
4925
4926         intel_crtc->active = true;
4927
4928         if (!IS_GEN2(dev))
4929                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4930
4931         for_each_encoder_on_crtc(dev, crtc, encoder)
4932                 if (encoder->pre_enable)
4933                         encoder->pre_enable(encoder);
4934
4935         i9xx_enable_pll(intel_crtc);
4936
4937         i9xx_pfit_enable(intel_crtc);
4938
4939         intel_crtc_load_lut(crtc);
4940
4941         intel_update_watermarks(crtc);
4942         intel_enable_pipe(intel_crtc);
4943
4944         for_each_encoder_on_crtc(dev, crtc, encoder)
4945                 encoder->enable(encoder);
4946
4947         assert_vblank_disabled(crtc);
4948         drm_crtc_vblank_on(crtc);
4949
4950         intel_crtc_enable_planes(crtc);
4951
4952         /*
4953          * Gen2 reports pipe underruns whenever all planes are disabled.
4954          * So don't enable underrun reporting before at least some planes
4955          * are enabled.
4956          * FIXME: Need to fix the logic to work when we turn off all planes
4957          * but leave the pipe running.
4958          */
4959         if (IS_GEN2(dev))
4960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961
4962         /* Underruns don't raise interrupts, so check manually. */
4963         i9xx_check_fifo_underruns(dev_priv);
4964 }
4965
4966 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4967 {
4968         struct drm_device *dev = crtc->base.dev;
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970
4971         if (!crtc->config.gmch_pfit.control)
4972                 return;
4973
4974         assert_pipe_disabled(dev_priv, crtc->pipe);
4975
4976         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4977                          I915_READ(PFIT_CONTROL));
4978         I915_WRITE(PFIT_CONTROL, 0);
4979 }
4980
4981 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4982 {
4983         struct drm_device *dev = crtc->dev;
4984         struct drm_i915_private *dev_priv = dev->dev_private;
4985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986         struct intel_encoder *encoder;
4987         int pipe = intel_crtc->pipe;
4988
4989         if (!intel_crtc->active)
4990                 return;
4991
4992         /*
4993          * Gen2 reports pipe underruns whenever all planes are disabled.
4994          * So diasble underrun reporting before all the planes get disabled.
4995          * FIXME: Need to fix the logic to work when we turn off all planes
4996          * but leave the pipe running.
4997          */
4998         if (IS_GEN2(dev))
4999                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5000
5001         /*
5002          * Vblank time updates from the shadow to live plane control register
5003          * are blocked if the memory self-refresh mode is active at that
5004          * moment. So to make sure the plane gets truly disabled, disable
5005          * first the self-refresh mode. The self-refresh enable bit in turn
5006          * will be checked/applied by the HW only at the next frame start
5007          * event which is after the vblank start event, so we need to have a
5008          * wait-for-vblank between disabling the plane and the pipe.
5009          */
5010         intel_set_memory_cxsr(dev_priv, false);
5011         intel_crtc_disable_planes(crtc);
5012
5013         /*
5014          * On gen2 planes are double buffered but the pipe isn't, so we must
5015          * wait for planes to fully turn off before disabling the pipe.
5016          * We also need to wait on all gmch platforms because of the
5017          * self-refresh mode constraint explained above.
5018          */
5019         intel_wait_for_vblank(dev, pipe);
5020
5021         drm_crtc_vblank_off(crtc);
5022         assert_vblank_disabled(crtc);
5023
5024         for_each_encoder_on_crtc(dev, crtc, encoder)
5025                 encoder->disable(encoder);
5026
5027         intel_disable_pipe(intel_crtc);
5028
5029         i9xx_pfit_disable(intel_crtc);
5030
5031         for_each_encoder_on_crtc(dev, crtc, encoder)
5032                 if (encoder->post_disable)
5033                         encoder->post_disable(encoder);
5034
5035         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5036                 if (IS_CHERRYVIEW(dev))
5037                         chv_disable_pll(dev_priv, pipe);
5038                 else if (IS_VALLEYVIEW(dev))
5039                         vlv_disable_pll(dev_priv, pipe);
5040                 else
5041                         i9xx_disable_pll(intel_crtc);
5042         }
5043
5044         if (!IS_GEN2(dev))
5045                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5046
5047         intel_crtc->active = false;
5048         intel_update_watermarks(crtc);
5049
5050         mutex_lock(&dev->struct_mutex);
5051         intel_update_fbc(dev);
5052         mutex_unlock(&dev->struct_mutex);
5053 }
5054
5055 static void i9xx_crtc_off(struct drm_crtc *crtc)
5056 {
5057 }
5058
5059 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5060                                     bool enabled)
5061 {
5062         struct drm_device *dev = crtc->dev;
5063         struct drm_i915_master_private *master_priv;
5064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065         int pipe = intel_crtc->pipe;
5066
5067         if (!dev->primary->master)
5068                 return;
5069
5070         master_priv = dev->primary->master->driver_priv;
5071         if (!master_priv->sarea_priv)
5072                 return;
5073
5074         switch (pipe) {
5075         case 0:
5076                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5077                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5078                 break;
5079         case 1:
5080                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5081                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5082                 break;
5083         default:
5084                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5085                 break;
5086         }
5087 }
5088
5089 /* Master function to enable/disable CRTC and corresponding power wells */
5090 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095         enum intel_display_power_domain domain;
5096         unsigned long domains;
5097
5098         if (enable) {
5099                 if (!intel_crtc->active) {
5100                         domains = get_crtc_power_domains(crtc);
5101                         for_each_power_domain(domain, domains)
5102                                 intel_display_power_get(dev_priv, domain);
5103                         intel_crtc->enabled_power_domains = domains;
5104
5105                         dev_priv->display.crtc_enable(crtc);
5106                 }
5107         } else {
5108                 if (intel_crtc->active) {
5109                         dev_priv->display.crtc_disable(crtc);
5110
5111                         domains = intel_crtc->enabled_power_domains;
5112                         for_each_power_domain(domain, domains)
5113                                 intel_display_power_put(dev_priv, domain);
5114                         intel_crtc->enabled_power_domains = 0;
5115                 }
5116         }
5117 }
5118
5119 /**
5120  * Sets the power management mode of the pipe and plane.
5121  */
5122 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5123 {
5124         struct drm_device *dev = crtc->dev;
5125         struct intel_encoder *intel_encoder;
5126         bool enable = false;
5127
5128         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5129                 enable |= intel_encoder->connectors_active;
5130
5131         intel_crtc_control(crtc, enable);
5132
5133         intel_crtc_update_sarea(crtc, enable);
5134 }
5135
5136 static void intel_crtc_disable(struct drm_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->dev;
5139         struct drm_connector *connector;
5140         struct drm_i915_private *dev_priv = dev->dev_private;
5141         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5142         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5143
5144         /* crtc should still be enabled when we disable it. */
5145         WARN_ON(!crtc->enabled);
5146
5147         dev_priv->display.crtc_disable(crtc);
5148         intel_crtc_update_sarea(crtc, false);
5149         dev_priv->display.off(crtc);
5150
5151         if (crtc->primary->fb) {
5152                 mutex_lock(&dev->struct_mutex);
5153                 intel_unpin_fb_obj(old_obj);
5154                 i915_gem_track_fb(old_obj, NULL,
5155                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5156                 mutex_unlock(&dev->struct_mutex);
5157                 crtc->primary->fb = NULL;
5158         }
5159
5160         /* Update computed state. */
5161         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5162                 if (!connector->encoder || !connector->encoder->crtc)
5163                         continue;
5164
5165                 if (connector->encoder->crtc != crtc)
5166                         continue;
5167
5168                 connector->dpms = DRM_MODE_DPMS_OFF;
5169                 to_intel_encoder(connector->encoder)->connectors_active = false;
5170         }
5171 }
5172
5173 void intel_encoder_destroy(struct drm_encoder *encoder)
5174 {
5175         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5176
5177         drm_encoder_cleanup(encoder);
5178         kfree(intel_encoder);
5179 }
5180
5181 /* Simple dpms helper for encoders with just one connector, no cloning and only
5182  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5183  * state of the entire output pipe. */
5184 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5185 {
5186         if (mode == DRM_MODE_DPMS_ON) {
5187                 encoder->connectors_active = true;
5188
5189                 intel_crtc_update_dpms(encoder->base.crtc);
5190         } else {
5191                 encoder->connectors_active = false;
5192
5193                 intel_crtc_update_dpms(encoder->base.crtc);
5194         }
5195 }
5196
5197 /* Cross check the actual hw state with our own modeset state tracking (and it's
5198  * internal consistency). */
5199 static void intel_connector_check_state(struct intel_connector *connector)
5200 {
5201         if (connector->get_hw_state(connector)) {
5202                 struct intel_encoder *encoder = connector->encoder;
5203                 struct drm_crtc *crtc;
5204                 bool encoder_enabled;
5205                 enum pipe pipe;
5206
5207                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5208                               connector->base.base.id,
5209                               connector->base.name);
5210
5211                 /* there is no real hw state for MST connectors */
5212                 if (connector->mst_port)
5213                         return;
5214
5215                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5216                      "wrong connector dpms state\n");
5217                 WARN(connector->base.encoder != &encoder->base,
5218                      "active connector not linked to encoder\n");
5219
5220                 if (encoder) {
5221                         WARN(!encoder->connectors_active,
5222                              "encoder->connectors_active not set\n");
5223
5224                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5225                         WARN(!encoder_enabled, "encoder not enabled\n");
5226                         if (WARN_ON(!encoder->base.crtc))
5227                                 return;
5228
5229                         crtc = encoder->base.crtc;
5230
5231                         WARN(!crtc->enabled, "crtc not enabled\n");
5232                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5233                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5234                              "encoder active on the wrong pipe\n");
5235                 }
5236         }
5237 }
5238
5239 /* Even simpler default implementation, if there's really no special case to
5240  * consider. */
5241 void intel_connector_dpms(struct drm_connector *connector, int mode)
5242 {
5243         /* All the simple cases only support two dpms states. */
5244         if (mode != DRM_MODE_DPMS_ON)
5245                 mode = DRM_MODE_DPMS_OFF;
5246
5247         if (mode == connector->dpms)
5248                 return;
5249
5250         connector->dpms = mode;
5251
5252         /* Only need to change hw state when actually enabled */
5253         if (connector->encoder)
5254                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5255
5256         intel_modeset_check_state(connector->dev);
5257 }
5258
5259 /* Simple connector->get_hw_state implementation for encoders that support only
5260  * one connector and no cloning and hence the encoder state determines the state
5261  * of the connector. */
5262 bool intel_connector_get_hw_state(struct intel_connector *connector)
5263 {
5264         enum pipe pipe = 0;
5265         struct intel_encoder *encoder = connector->encoder;
5266
5267         return encoder->get_hw_state(encoder, &pipe);
5268 }
5269
5270 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5271                                      struct intel_crtc_config *pipe_config)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         struct intel_crtc *pipe_B_crtc =
5275                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5276
5277         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5278                       pipe_name(pipe), pipe_config->fdi_lanes);
5279         if (pipe_config->fdi_lanes > 4) {
5280                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5281                               pipe_name(pipe), pipe_config->fdi_lanes);
5282                 return false;
5283         }
5284
5285         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5286                 if (pipe_config->fdi_lanes > 2) {
5287                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5288                                       pipe_config->fdi_lanes);
5289                         return false;
5290                 } else {
5291                         return true;
5292                 }
5293         }
5294
5295         if (INTEL_INFO(dev)->num_pipes == 2)
5296                 return true;
5297
5298         /* Ivybridge 3 pipe is really complicated */
5299         switch (pipe) {
5300         case PIPE_A:
5301                 return true;
5302         case PIPE_B:
5303                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5304                     pipe_config->fdi_lanes > 2) {
5305                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5306                                       pipe_name(pipe), pipe_config->fdi_lanes);
5307                         return false;
5308                 }
5309                 return true;
5310         case PIPE_C:
5311                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5312                     pipe_B_crtc->config.fdi_lanes <= 2) {
5313                         if (pipe_config->fdi_lanes > 2) {
5314                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5315                                               pipe_name(pipe), pipe_config->fdi_lanes);
5316                                 return false;
5317                         }
5318                 } else {
5319                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5320                         return false;
5321                 }
5322                 return true;
5323         default:
5324                 BUG();
5325         }
5326 }
5327
5328 #define RETRY 1
5329 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5330                                        struct intel_crtc_config *pipe_config)
5331 {
5332         struct drm_device *dev = intel_crtc->base.dev;
5333         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5334         int lane, link_bw, fdi_dotclock;
5335         bool setup_ok, needs_recompute = false;
5336
5337 retry:
5338         /* FDI is a binary signal running at ~2.7GHz, encoding
5339          * each output octet as 10 bits. The actual frequency
5340          * is stored as a divider into a 100MHz clock, and the
5341          * mode pixel clock is stored in units of 1KHz.
5342          * Hence the bw of each lane in terms of the mode signal
5343          * is:
5344          */
5345         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5346
5347         fdi_dotclock = adjusted_mode->crtc_clock;
5348
5349         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5350                                            pipe_config->pipe_bpp);
5351
5352         pipe_config->fdi_lanes = lane;
5353
5354         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5355                                link_bw, &pipe_config->fdi_m_n);
5356
5357         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5358                                             intel_crtc->pipe, pipe_config);
5359         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5360                 pipe_config->pipe_bpp -= 2*3;
5361                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5362                               pipe_config->pipe_bpp);
5363                 needs_recompute = true;
5364                 pipe_config->bw_constrained = true;
5365
5366                 goto retry;
5367         }
5368
5369         if (needs_recompute)
5370                 return RETRY;
5371
5372         return setup_ok ? 0 : -EINVAL;
5373 }
5374
5375 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5376                                    struct intel_crtc_config *pipe_config)
5377 {
5378         pipe_config->ips_enabled = i915.enable_ips &&
5379                                    hsw_crtc_supports_ips(crtc) &&
5380                                    pipe_config->pipe_bpp <= 24;
5381 }
5382
5383 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5384                                      struct intel_crtc_config *pipe_config)
5385 {
5386         struct drm_device *dev = crtc->base.dev;
5387         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5388
5389         /* FIXME should check pixel clock limits on all platforms */
5390         if (INTEL_INFO(dev)->gen < 4) {
5391                 struct drm_i915_private *dev_priv = dev->dev_private;
5392                 int clock_limit =
5393                         dev_priv->display.get_display_clock_speed(dev);
5394
5395                 /*
5396                  * Enable pixel doubling when the dot clock
5397                  * is > 90% of the (display) core speed.
5398                  *
5399                  * GDG double wide on either pipe,
5400                  * otherwise pipe A only.
5401                  */
5402                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5403                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5404                         clock_limit *= 2;
5405                         pipe_config->double_wide = true;
5406                 }
5407
5408                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5409                         return -EINVAL;
5410         }
5411
5412         /*
5413          * Pipe horizontal size must be even in:
5414          * - DVO ganged mode
5415          * - LVDS dual channel mode
5416          * - Double wide pipe
5417          */
5418         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5420                 pipe_config->pipe_src_w &= ~1;
5421
5422         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5423          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5424          */
5425         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5426                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5427                 return -EINVAL;
5428
5429         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5430                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5431         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5432                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5433                  * for lvds. */
5434                 pipe_config->pipe_bpp = 8*3;
5435         }
5436
5437         if (HAS_IPS(dev))
5438                 hsw_compute_ips_config(crtc, pipe_config);
5439
5440         /*
5441          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5442          * old clock survives for now.
5443          */
5444         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5445                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5446
5447         if (pipe_config->has_pch_encoder)
5448                 return ironlake_fdi_compute_config(crtc, pipe_config);
5449
5450         return 0;
5451 }
5452
5453 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5454 {
5455         struct drm_i915_private *dev_priv = dev->dev_private;
5456         int vco = valleyview_get_vco(dev_priv);
5457         u32 val;
5458         int divider;
5459
5460         /* FIXME: Punit isn't quite ready yet */
5461         if (IS_CHERRYVIEW(dev))
5462                 return 400000;
5463
5464         mutex_lock(&dev_priv->dpio_lock);
5465         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5466         mutex_unlock(&dev_priv->dpio_lock);
5467
5468         divider = val & DISPLAY_FREQUENCY_VALUES;
5469
5470         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5471              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5472              "cdclk change in progress\n");
5473
5474         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5475 }
5476
5477 static int i945_get_display_clock_speed(struct drm_device *dev)
5478 {
5479         return 400000;
5480 }
5481
5482 static int i915_get_display_clock_speed(struct drm_device *dev)
5483 {
5484         return 333000;
5485 }
5486
5487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5488 {
5489         return 200000;
5490 }
5491
5492 static int pnv_get_display_clock_speed(struct drm_device *dev)
5493 {
5494         u16 gcfgc = 0;
5495
5496         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5497
5498         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5499         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5500                 return 267000;
5501         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5502                 return 333000;
5503         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5504                 return 444000;
5505         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5506                 return 200000;
5507         default:
5508                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5509         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5510                 return 133000;
5511         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5512                 return 167000;
5513         }
5514 }
5515
5516 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5517 {
5518         u16 gcfgc = 0;
5519
5520         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5521
5522         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5523                 return 133000;
5524         else {
5525                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5526                 case GC_DISPLAY_CLOCK_333_MHZ:
5527                         return 333000;
5528                 default:
5529                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5530                         return 190000;
5531                 }
5532         }
5533 }
5534
5535 static int i865_get_display_clock_speed(struct drm_device *dev)
5536 {
5537         return 266000;
5538 }
5539
5540 static int i855_get_display_clock_speed(struct drm_device *dev)
5541 {
5542         u16 hpllcc = 0;
5543         /* Assume that the hardware is in the high speed state.  This
5544          * should be the default.
5545          */
5546         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5547         case GC_CLOCK_133_200:
5548         case GC_CLOCK_100_200:
5549                 return 200000;
5550         case GC_CLOCK_166_250:
5551                 return 250000;
5552         case GC_CLOCK_100_133:
5553                 return 133000;
5554         }
5555
5556         /* Shouldn't happen */
5557         return 0;
5558 }
5559
5560 static int i830_get_display_clock_speed(struct drm_device *dev)
5561 {
5562         return 133000;
5563 }
5564
5565 static void
5566 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5567 {
5568         while (*num > DATA_LINK_M_N_MASK ||
5569                *den > DATA_LINK_M_N_MASK) {
5570                 *num >>= 1;
5571                 *den >>= 1;
5572         }
5573 }
5574
5575 static void compute_m_n(unsigned int m, unsigned int n,
5576                         uint32_t *ret_m, uint32_t *ret_n)
5577 {
5578         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5579         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5580         intel_reduce_m_n_ratio(ret_m, ret_n);
5581 }
5582
5583 void
5584 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5585                        int pixel_clock, int link_clock,
5586                        struct intel_link_m_n *m_n)
5587 {
5588         m_n->tu = 64;
5589
5590         compute_m_n(bits_per_pixel * pixel_clock,
5591                     link_clock * nlanes * 8,
5592                     &m_n->gmch_m, &m_n->gmch_n);
5593
5594         compute_m_n(pixel_clock, link_clock,
5595                     &m_n->link_m, &m_n->link_n);
5596 }
5597
5598 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5599 {
5600         if (i915.panel_use_ssc >= 0)
5601                 return i915.panel_use_ssc != 0;
5602         return dev_priv->vbt.lvds_use_ssc
5603                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5604 }
5605
5606 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5607 {
5608         struct drm_device *dev = crtc->base.dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         int refclk;
5611
5612         if (IS_VALLEYVIEW(dev)) {
5613                 refclk = 100000;
5614         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5615             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5616                 refclk = dev_priv->vbt.lvds_ssc_freq;
5617                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5618         } else if (!IS_GEN2(dev)) {
5619                 refclk = 96000;
5620         } else {
5621                 refclk = 48000;
5622         }
5623
5624         return refclk;
5625 }
5626
5627 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5628 {
5629         return (1 << dpll->n) << 16 | dpll->m2;
5630 }
5631
5632 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5633 {
5634         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5635 }
5636
5637 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5638                                      intel_clock_t *reduced_clock)
5639 {
5640         struct drm_device *dev = crtc->base.dev;
5641         u32 fp, fp2 = 0;
5642
5643         if (IS_PINEVIEW(dev)) {
5644                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5645                 if (reduced_clock)
5646                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5647         } else {
5648                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5649                 if (reduced_clock)
5650                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5651         }
5652
5653         crtc->config.dpll_hw_state.fp0 = fp;
5654
5655         crtc->lowfreq_avail = false;
5656         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5657             reduced_clock && i915.powersave) {
5658                 crtc->config.dpll_hw_state.fp1 = fp2;
5659                 crtc->lowfreq_avail = true;
5660         } else {
5661                 crtc->config.dpll_hw_state.fp1 = fp;
5662         }
5663 }
5664
5665 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5666                 pipe)
5667 {
5668         u32 reg_val;
5669
5670         /*
5671          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5672          * and set it to a reasonable value instead.
5673          */
5674         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5675         reg_val &= 0xffffff00;
5676         reg_val |= 0x00000030;
5677         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5678
5679         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5680         reg_val &= 0x8cffffff;
5681         reg_val = 0x8c000000;
5682         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5683
5684         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5685         reg_val &= 0xffffff00;
5686         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5687
5688         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5689         reg_val &= 0x00ffffff;
5690         reg_val |= 0xb0000000;
5691         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5692 }
5693
5694 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5695                                          struct intel_link_m_n *m_n)
5696 {
5697         struct drm_device *dev = crtc->base.dev;
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         int pipe = crtc->pipe;
5700
5701         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5702         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5703         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5704         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5705 }
5706
5707 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5708                                          struct intel_link_m_n *m_n,
5709                                          struct intel_link_m_n *m2_n2)
5710 {
5711         struct drm_device *dev = crtc->base.dev;
5712         struct drm_i915_private *dev_priv = dev->dev_private;
5713         int pipe = crtc->pipe;
5714         enum transcoder transcoder = crtc->config.cpu_transcoder;
5715
5716         if (INTEL_INFO(dev)->gen >= 5) {
5717                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5718                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5719                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5720                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5721                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5722                  * for gen < 8) and if DRRS is supported (to make sure the
5723                  * registers are not unnecessarily accessed).
5724                  */
5725                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5726                         crtc->config.has_drrs) {
5727                         I915_WRITE(PIPE_DATA_M2(transcoder),
5728                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5729                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5730                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5731                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5732                 }
5733         } else {
5734                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5736                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5737                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5738         }
5739 }
5740
5741 void intel_dp_set_m_n(struct intel_crtc *crtc)
5742 {
5743         if (crtc->config.has_pch_encoder)
5744                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5745         else
5746                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5747                                                    &crtc->config.dp_m2_n2);
5748 }
5749
5750 static void vlv_update_pll(struct intel_crtc *crtc)
5751 {
5752         u32 dpll, dpll_md;
5753
5754         /*
5755          * Enable DPIO clock input. We should never disable the reference
5756          * clock for pipe B, since VGA hotplug / manual detection depends
5757          * on it.
5758          */
5759         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5760                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5761         /* We should never disable this, set it here for state tracking */
5762         if (crtc->pipe == PIPE_B)
5763                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5764         dpll |= DPLL_VCO_ENABLE;
5765         crtc->config.dpll_hw_state.dpll = dpll;
5766
5767         dpll_md = (crtc->config.pixel_multiplier - 1)
5768                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5769         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5770 }
5771
5772 static void vlv_prepare_pll(struct intel_crtc *crtc)
5773 {
5774         struct drm_device *dev = crtc->base.dev;
5775         struct drm_i915_private *dev_priv = dev->dev_private;
5776         int pipe = crtc->pipe;
5777         u32 mdiv;
5778         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5779         u32 coreclk, reg_val;
5780
5781         mutex_lock(&dev_priv->dpio_lock);
5782
5783         bestn = crtc->config.dpll.n;
5784         bestm1 = crtc->config.dpll.m1;
5785         bestm2 = crtc->config.dpll.m2;
5786         bestp1 = crtc->config.dpll.p1;
5787         bestp2 = crtc->config.dpll.p2;
5788
5789         /* See eDP HDMI DPIO driver vbios notes doc */
5790
5791         /* PLL B needs special handling */
5792         if (pipe == PIPE_B)
5793                 vlv_pllb_recal_opamp(dev_priv, pipe);
5794
5795         /* Set up Tx target for periodic Rcomp update */
5796         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5797
5798         /* Disable target IRef on PLL */
5799         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5800         reg_val &= 0x00ffffff;
5801         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5802
5803         /* Disable fast lock */
5804         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5805
5806         /* Set idtafcrecal before PLL is enabled */
5807         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5808         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5809         mdiv |= ((bestn << DPIO_N_SHIFT));
5810         mdiv |= (1 << DPIO_K_SHIFT);
5811
5812         /*
5813          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5814          * but we don't support that).
5815          * Note: don't use the DAC post divider as it seems unstable.
5816          */
5817         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5818         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5819
5820         mdiv |= DPIO_ENABLE_CALIBRATION;
5821         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5822
5823         /* Set HBR and RBR LPF coefficients */
5824         if (crtc->config.port_clock == 162000 ||
5825             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5826             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5827                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5828                                  0x009f0003);
5829         else
5830                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5831                                  0x00d0000f);
5832
5833         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5834             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5835                 /* Use SSC source */
5836                 if (pipe == PIPE_A)
5837                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5838                                          0x0df40000);
5839                 else
5840                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5841                                          0x0df70000);
5842         } else { /* HDMI or VGA */
5843                 /* Use bend source */
5844                 if (pipe == PIPE_A)
5845                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5846                                          0x0df70000);
5847                 else
5848                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5849                                          0x0df40000);
5850         }
5851
5852         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5853         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5854         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5855             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5856                 coreclk |= 0x01000000;
5857         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5858
5859         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5860         mutex_unlock(&dev_priv->dpio_lock);
5861 }
5862
5863 static void chv_update_pll(struct intel_crtc *crtc)
5864 {
5865         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5866                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5867                 DPLL_VCO_ENABLE;
5868         if (crtc->pipe != PIPE_A)
5869                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5870
5871         crtc->config.dpll_hw_state.dpll_md =
5872                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5873 }
5874
5875 static void chv_prepare_pll(struct intel_crtc *crtc)
5876 {
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = dev->dev_private;
5879         int pipe = crtc->pipe;
5880         int dpll_reg = DPLL(crtc->pipe);
5881         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5882         u32 loopfilter, intcoeff;
5883         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5884         int refclk;
5885
5886         bestn = crtc->config.dpll.n;
5887         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5888         bestm1 = crtc->config.dpll.m1;
5889         bestm2 = crtc->config.dpll.m2 >> 22;
5890         bestp1 = crtc->config.dpll.p1;
5891         bestp2 = crtc->config.dpll.p2;
5892
5893         /*
5894          * Enable Refclk and SSC
5895          */
5896         I915_WRITE(dpll_reg,
5897                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5898
5899         mutex_lock(&dev_priv->dpio_lock);
5900
5901         /* p1 and p2 divider */
5902         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5903                         5 << DPIO_CHV_S1_DIV_SHIFT |
5904                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5905                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5906                         1 << DPIO_CHV_K_DIV_SHIFT);
5907
5908         /* Feedback post-divider - m2 */
5909         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5910
5911         /* Feedback refclk divider - n and m1 */
5912         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5913                         DPIO_CHV_M1_DIV_BY_2 |
5914                         1 << DPIO_CHV_N_DIV_SHIFT);
5915
5916         /* M2 fraction division */
5917         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5918
5919         /* M2 fraction division enable */
5920         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5921                        DPIO_CHV_FRAC_DIV_EN |
5922                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5923
5924         /* Loop filter */
5925         refclk = i9xx_get_refclk(crtc, 0);
5926         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5927                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5928         if (refclk == 100000)
5929                 intcoeff = 11;
5930         else if (refclk == 38400)
5931                 intcoeff = 10;
5932         else
5933                 intcoeff = 9;
5934         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5935         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5936
5937         /* AFC Recal */
5938         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5939                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5940                         DPIO_AFC_RECAL);
5941
5942         mutex_unlock(&dev_priv->dpio_lock);
5943 }
5944
5945 static void i9xx_update_pll(struct intel_crtc *crtc,
5946                             intel_clock_t *reduced_clock,
5947                             int num_connectors)
5948 {
5949         struct drm_device *dev = crtc->base.dev;
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         u32 dpll;
5952         bool is_sdvo;
5953         struct dpll *clock = &crtc->config.dpll;
5954
5955         i9xx_update_pll_dividers(crtc, reduced_clock);
5956
5957         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5958                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5959
5960         dpll = DPLL_VGA_MODE_DIS;
5961
5962         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5963                 dpll |= DPLLB_MODE_LVDS;
5964         else
5965                 dpll |= DPLLB_MODE_DAC_SERIAL;
5966
5967         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5968                 dpll |= (crtc->config.pixel_multiplier - 1)
5969                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5970         }
5971
5972         if (is_sdvo)
5973                 dpll |= DPLL_SDVO_HIGH_SPEED;
5974
5975         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5976                 dpll |= DPLL_SDVO_HIGH_SPEED;
5977
5978         /* compute bitmask from p1 value */
5979         if (IS_PINEVIEW(dev))
5980                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5981         else {
5982                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5983                 if (IS_G4X(dev) && reduced_clock)
5984                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5985         }
5986         switch (clock->p2) {
5987         case 5:
5988                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5989                 break;
5990         case 7:
5991                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5992                 break;
5993         case 10:
5994                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5995                 break;
5996         case 14:
5997                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5998                 break;
5999         }
6000         if (INTEL_INFO(dev)->gen >= 4)
6001                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6002
6003         if (crtc->config.sdvo_tv_clock)
6004                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6005         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6006                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6007                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6008         else
6009                 dpll |= PLL_REF_INPUT_DREFCLK;
6010
6011         dpll |= DPLL_VCO_ENABLE;
6012         crtc->config.dpll_hw_state.dpll = dpll;
6013
6014         if (INTEL_INFO(dev)->gen >= 4) {
6015                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6016                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6018         }
6019 }
6020
6021 static void i8xx_update_pll(struct intel_crtc *crtc,
6022                             intel_clock_t *reduced_clock,
6023                             int num_connectors)
6024 {
6025         struct drm_device *dev = crtc->base.dev;
6026         struct drm_i915_private *dev_priv = dev->dev_private;
6027         u32 dpll;
6028         struct dpll *clock = &crtc->config.dpll;
6029
6030         i9xx_update_pll_dividers(crtc, reduced_clock);
6031
6032         dpll = DPLL_VGA_MODE_DIS;
6033
6034         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6035                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6036         } else {
6037                 if (clock->p1 == 2)
6038                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6039                 else
6040                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6041                 if (clock->p2 == 4)
6042                         dpll |= PLL_P2_DIVIDE_BY_4;
6043         }
6044
6045         if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6046                 dpll |= DPLL_DVO_2X_MODE;
6047
6048         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6049                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6050                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6051         else
6052                 dpll |= PLL_REF_INPUT_DREFCLK;
6053
6054         dpll |= DPLL_VCO_ENABLE;
6055         crtc->config.dpll_hw_state.dpll = dpll;
6056 }
6057
6058 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6059 {
6060         struct drm_device *dev = intel_crtc->base.dev;
6061         struct drm_i915_private *dev_priv = dev->dev_private;
6062         enum pipe pipe = intel_crtc->pipe;
6063         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6064         struct drm_display_mode *adjusted_mode =
6065                 &intel_crtc->config.adjusted_mode;
6066         uint32_t crtc_vtotal, crtc_vblank_end;
6067         int vsyncshift = 0;
6068
6069         /* We need to be careful not to changed the adjusted mode, for otherwise
6070          * the hw state checker will get angry at the mismatch. */
6071         crtc_vtotal = adjusted_mode->crtc_vtotal;
6072         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6073
6074         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6075                 /* the chip adds 2 halflines automatically */
6076                 crtc_vtotal -= 1;
6077                 crtc_vblank_end -= 1;
6078
6079                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6080                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6081                 else
6082                         vsyncshift = adjusted_mode->crtc_hsync_start -
6083                                 adjusted_mode->crtc_htotal / 2;
6084                 if (vsyncshift < 0)
6085                         vsyncshift += adjusted_mode->crtc_htotal;
6086         }
6087
6088         if (INTEL_INFO(dev)->gen > 3)
6089                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6090
6091         I915_WRITE(HTOTAL(cpu_transcoder),
6092                    (adjusted_mode->crtc_hdisplay - 1) |
6093                    ((adjusted_mode->crtc_htotal - 1) << 16));
6094         I915_WRITE(HBLANK(cpu_transcoder),
6095                    (adjusted_mode->crtc_hblank_start - 1) |
6096                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6097         I915_WRITE(HSYNC(cpu_transcoder),
6098                    (adjusted_mode->crtc_hsync_start - 1) |
6099                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6100
6101         I915_WRITE(VTOTAL(cpu_transcoder),
6102                    (adjusted_mode->crtc_vdisplay - 1) |
6103                    ((crtc_vtotal - 1) << 16));
6104         I915_WRITE(VBLANK(cpu_transcoder),
6105                    (adjusted_mode->crtc_vblank_start - 1) |
6106                    ((crtc_vblank_end - 1) << 16));
6107         I915_WRITE(VSYNC(cpu_transcoder),
6108                    (adjusted_mode->crtc_vsync_start - 1) |
6109                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6110
6111         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6112          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6113          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6114          * bits. */
6115         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6116             (pipe == PIPE_B || pipe == PIPE_C))
6117                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6118
6119         /* pipesrc controls the size that is scaled from, which should
6120          * always be the user's requested size.
6121          */
6122         I915_WRITE(PIPESRC(pipe),
6123                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6124                    (intel_crtc->config.pipe_src_h - 1));
6125 }
6126
6127 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6128                                    struct intel_crtc_config *pipe_config)
6129 {
6130         struct drm_device *dev = crtc->base.dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6133         uint32_t tmp;
6134
6135         tmp = I915_READ(HTOTAL(cpu_transcoder));
6136         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6137         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6138         tmp = I915_READ(HBLANK(cpu_transcoder));
6139         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6140         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6141         tmp = I915_READ(HSYNC(cpu_transcoder));
6142         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6143         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6144
6145         tmp = I915_READ(VTOTAL(cpu_transcoder));
6146         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6147         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6148         tmp = I915_READ(VBLANK(cpu_transcoder));
6149         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6150         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6151         tmp = I915_READ(VSYNC(cpu_transcoder));
6152         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6153         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6154
6155         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6156                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6157                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6158                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6159         }
6160
6161         tmp = I915_READ(PIPESRC(crtc->pipe));
6162         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6163         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6164
6165         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6166         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6167 }
6168
6169 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6170                                  struct intel_crtc_config *pipe_config)
6171 {
6172         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6173         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6174         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6175         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6176
6177         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6178         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6179         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6180         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6181
6182         mode->flags = pipe_config->adjusted_mode.flags;
6183
6184         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6185         mode->flags |= pipe_config->adjusted_mode.flags;
6186 }
6187
6188 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6189 {
6190         struct drm_device *dev = intel_crtc->base.dev;
6191         struct drm_i915_private *dev_priv = dev->dev_private;
6192         uint32_t pipeconf;
6193
6194         pipeconf = 0;
6195
6196         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6197             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6198                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6199
6200         if (intel_crtc->config.double_wide)
6201                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6202
6203         /* only g4x and later have fancy bpc/dither controls */
6204         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6205                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6206                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6207                         pipeconf |= PIPECONF_DITHER_EN |
6208                                     PIPECONF_DITHER_TYPE_SP;
6209
6210                 switch (intel_crtc->config.pipe_bpp) {
6211                 case 18:
6212                         pipeconf |= PIPECONF_6BPC;
6213                         break;
6214                 case 24:
6215                         pipeconf |= PIPECONF_8BPC;
6216                         break;
6217                 case 30:
6218                         pipeconf |= PIPECONF_10BPC;
6219                         break;
6220                 default:
6221                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6222                         BUG();
6223                 }
6224         }
6225
6226         if (HAS_PIPE_CXSR(dev)) {
6227                 if (intel_crtc->lowfreq_avail) {
6228                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6229                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6230                 } else {
6231                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6232                 }
6233         }
6234
6235         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6236                 if (INTEL_INFO(dev)->gen < 4 ||
6237                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6238                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6239                 else
6240                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6241         } else
6242                 pipeconf |= PIPECONF_PROGRESSIVE;
6243
6244         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6245                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6246
6247         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6248         POSTING_READ(PIPECONF(intel_crtc->pipe));
6249 }
6250
6251 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6252                               int x, int y,
6253                               struct drm_framebuffer *fb)
6254 {
6255         struct drm_device *dev = crtc->base.dev;
6256         struct drm_i915_private *dev_priv = dev->dev_private;
6257         int refclk, num_connectors = 0;
6258         intel_clock_t clock, reduced_clock;
6259         bool ok, has_reduced_clock = false;
6260         bool is_lvds = false, is_dsi = false;
6261         struct intel_encoder *encoder;
6262         const intel_limit_t *limit;
6263
6264         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6265                 switch (encoder->type) {
6266                 case INTEL_OUTPUT_LVDS:
6267                         is_lvds = true;
6268                         break;
6269                 case INTEL_OUTPUT_DSI:
6270                         is_dsi = true;
6271                         break;
6272                 }
6273
6274                 num_connectors++;
6275         }
6276
6277         if (is_dsi)
6278                 return 0;
6279
6280         if (!crtc->config.clock_set) {
6281                 refclk = i9xx_get_refclk(crtc, num_connectors);
6282
6283                 /*
6284                  * Returns a set of divisors for the desired target clock with
6285                  * the given refclk, or FALSE.  The returned values represent
6286                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6287                  * 2) / p1 / p2.
6288                  */
6289                 limit = intel_limit(crtc, refclk);
6290                 ok = dev_priv->display.find_dpll(limit, crtc,
6291                                                  crtc->config.port_clock,
6292                                                  refclk, NULL, &clock);
6293                 if (!ok) {
6294                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6295                         return -EINVAL;
6296                 }
6297
6298                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6299                         /*
6300                          * Ensure we match the reduced clock's P to the target
6301                          * clock.  If the clocks don't match, we can't switch
6302                          * the display clock by using the FP0/FP1. In such case
6303                          * we will disable the LVDS downclock feature.
6304                          */
6305                         has_reduced_clock =
6306                                 dev_priv->display.find_dpll(limit, crtc,
6307                                                             dev_priv->lvds_downclock,
6308                                                             refclk, &clock,
6309                                                             &reduced_clock);
6310                 }
6311                 /* Compat-code for transition, will disappear. */
6312                 crtc->config.dpll.n = clock.n;
6313                 crtc->config.dpll.m1 = clock.m1;
6314                 crtc->config.dpll.m2 = clock.m2;
6315                 crtc->config.dpll.p1 = clock.p1;
6316                 crtc->config.dpll.p2 = clock.p2;
6317         }
6318
6319         if (IS_GEN2(dev)) {
6320                 i8xx_update_pll(crtc,
6321                                 has_reduced_clock ? &reduced_clock : NULL,
6322                                 num_connectors);
6323         } else if (IS_CHERRYVIEW(dev)) {
6324                 chv_update_pll(crtc);
6325         } else if (IS_VALLEYVIEW(dev)) {
6326                 vlv_update_pll(crtc);
6327         } else {
6328                 i9xx_update_pll(crtc,
6329                                 has_reduced_clock ? &reduced_clock : NULL,
6330                                 num_connectors);
6331         }
6332
6333         return 0;
6334 }
6335
6336 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6337                                  struct intel_crtc_config *pipe_config)
6338 {
6339         struct drm_device *dev = crtc->base.dev;
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         uint32_t tmp;
6342
6343         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6344                 return;
6345
6346         tmp = I915_READ(PFIT_CONTROL);
6347         if (!(tmp & PFIT_ENABLE))
6348                 return;
6349
6350         /* Check whether the pfit is attached to our pipe. */
6351         if (INTEL_INFO(dev)->gen < 4) {
6352                 if (crtc->pipe != PIPE_B)
6353                         return;
6354         } else {
6355                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6356                         return;
6357         }
6358
6359         pipe_config->gmch_pfit.control = tmp;
6360         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6361         if (INTEL_INFO(dev)->gen < 5)
6362                 pipe_config->gmch_pfit.lvds_border_bits =
6363                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6364 }
6365
6366 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6367                                struct intel_crtc_config *pipe_config)
6368 {
6369         struct drm_device *dev = crtc->base.dev;
6370         struct drm_i915_private *dev_priv = dev->dev_private;
6371         int pipe = pipe_config->cpu_transcoder;
6372         intel_clock_t clock;
6373         u32 mdiv;
6374         int refclk = 100000;
6375
6376         /* In case of MIPI DPLL will not even be used */
6377         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6378                 return;
6379
6380         mutex_lock(&dev_priv->dpio_lock);
6381         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6382         mutex_unlock(&dev_priv->dpio_lock);
6383
6384         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6385         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6386         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6387         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6388         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6389
6390         vlv_clock(refclk, &clock);
6391
6392         /* clock.dot is the fast clock */
6393         pipe_config->port_clock = clock.dot / 5;
6394 }
6395
6396 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6397                                   struct intel_plane_config *plane_config)
6398 {
6399         struct drm_device *dev = crtc->base.dev;
6400         struct drm_i915_private *dev_priv = dev->dev_private;
6401         u32 val, base, offset;
6402         int pipe = crtc->pipe, plane = crtc->plane;
6403         int fourcc, pixel_format;
6404         int aligned_height;
6405
6406         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6407         if (!crtc->base.primary->fb) {
6408                 DRM_DEBUG_KMS("failed to alloc fb\n");
6409                 return;
6410         }
6411
6412         val = I915_READ(DSPCNTR(plane));
6413
6414         if (INTEL_INFO(dev)->gen >= 4)
6415                 if (val & DISPPLANE_TILED)
6416                         plane_config->tiled = true;
6417
6418         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6419         fourcc = intel_format_to_fourcc(pixel_format);
6420         crtc->base.primary->fb->pixel_format = fourcc;
6421         crtc->base.primary->fb->bits_per_pixel =
6422                 drm_format_plane_cpp(fourcc, 0) * 8;
6423
6424         if (INTEL_INFO(dev)->gen >= 4) {
6425                 if (plane_config->tiled)
6426                         offset = I915_READ(DSPTILEOFF(plane));
6427                 else
6428                         offset = I915_READ(DSPLINOFF(plane));
6429                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6430         } else {
6431                 base = I915_READ(DSPADDR(plane));
6432         }
6433         plane_config->base = base;
6434
6435         val = I915_READ(PIPESRC(pipe));
6436         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6437         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6438
6439         val = I915_READ(DSPSTRIDE(pipe));
6440         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6441
6442         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6443                                             plane_config->tiled);
6444
6445         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6446                                         aligned_height);
6447
6448         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6449                       pipe, plane, crtc->base.primary->fb->width,
6450                       crtc->base.primary->fb->height,
6451                       crtc->base.primary->fb->bits_per_pixel, base,
6452                       crtc->base.primary->fb->pitches[0],
6453                       plane_config->size);
6454
6455 }
6456
6457 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6458                                struct intel_crtc_config *pipe_config)
6459 {
6460         struct drm_device *dev = crtc->base.dev;
6461         struct drm_i915_private *dev_priv = dev->dev_private;
6462         int pipe = pipe_config->cpu_transcoder;
6463         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6464         intel_clock_t clock;
6465         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6466         int refclk = 100000;
6467
6468         mutex_lock(&dev_priv->dpio_lock);
6469         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6470         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6471         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6472         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6473         mutex_unlock(&dev_priv->dpio_lock);
6474
6475         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6476         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6477         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6478         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6479         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6480
6481         chv_clock(refclk, &clock);
6482
6483         /* clock.dot is the fast clock */
6484         pipe_config->port_clock = clock.dot / 5;
6485 }
6486
6487 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6488                                  struct intel_crtc_config *pipe_config)
6489 {
6490         struct drm_device *dev = crtc->base.dev;
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         uint32_t tmp;
6493
6494         if (!intel_display_power_is_enabled(dev_priv,
6495                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6496                 return false;
6497
6498         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6499         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6500
6501         tmp = I915_READ(PIPECONF(crtc->pipe));
6502         if (!(tmp & PIPECONF_ENABLE))
6503                 return false;
6504
6505         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6506                 switch (tmp & PIPECONF_BPC_MASK) {
6507                 case PIPECONF_6BPC:
6508                         pipe_config->pipe_bpp = 18;
6509                         break;
6510                 case PIPECONF_8BPC:
6511                         pipe_config->pipe_bpp = 24;
6512                         break;
6513                 case PIPECONF_10BPC:
6514                         pipe_config->pipe_bpp = 30;
6515                         break;
6516                 default:
6517                         break;
6518                 }
6519         }
6520
6521         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6522                 pipe_config->limited_color_range = true;
6523
6524         if (INTEL_INFO(dev)->gen < 4)
6525                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6526
6527         intel_get_pipe_timings(crtc, pipe_config);
6528
6529         i9xx_get_pfit_config(crtc, pipe_config);
6530
6531         if (INTEL_INFO(dev)->gen >= 4) {
6532                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6533                 pipe_config->pixel_multiplier =
6534                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6535                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6536                 pipe_config->dpll_hw_state.dpll_md = tmp;
6537         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6538                 tmp = I915_READ(DPLL(crtc->pipe));
6539                 pipe_config->pixel_multiplier =
6540                         ((tmp & SDVO_MULTIPLIER_MASK)
6541                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6542         } else {
6543                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6544                  * port and will be fixed up in the encoder->get_config
6545                  * function. */
6546                 pipe_config->pixel_multiplier = 1;
6547         }
6548         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6549         if (!IS_VALLEYVIEW(dev)) {
6550                 /*
6551                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6552                  * on 830. Filter it out here so that we don't
6553                  * report errors due to that.
6554                  */
6555                 if (IS_I830(dev))
6556                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6557
6558                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6559                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6560         } else {
6561                 /* Mask out read-only status bits. */
6562                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6563                                                      DPLL_PORTC_READY_MASK |
6564                                                      DPLL_PORTB_READY_MASK);
6565         }
6566
6567         if (IS_CHERRYVIEW(dev))
6568                 chv_crtc_clock_get(crtc, pipe_config);
6569         else if (IS_VALLEYVIEW(dev))
6570                 vlv_crtc_clock_get(crtc, pipe_config);
6571         else
6572                 i9xx_crtc_clock_get(crtc, pipe_config);
6573
6574         return true;
6575 }
6576
6577 static void ironlake_init_pch_refclk(struct drm_device *dev)
6578 {
6579         struct drm_i915_private *dev_priv = dev->dev_private;
6580         struct intel_encoder *encoder;
6581         u32 val, final;
6582         bool has_lvds = false;
6583         bool has_cpu_edp = false;
6584         bool has_panel = false;
6585         bool has_ck505 = false;
6586         bool can_ssc = false;
6587
6588         /* We need to take the global config into account */
6589         for_each_intel_encoder(dev, encoder) {
6590                 switch (encoder->type) {
6591                 case INTEL_OUTPUT_LVDS:
6592                         has_panel = true;
6593                         has_lvds = true;
6594                         break;
6595                 case INTEL_OUTPUT_EDP:
6596                         has_panel = true;
6597                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6598                                 has_cpu_edp = true;
6599                         break;
6600                 }
6601         }
6602
6603         if (HAS_PCH_IBX(dev)) {
6604                 has_ck505 = dev_priv->vbt.display_clock_mode;
6605                 can_ssc = has_ck505;
6606         } else {
6607                 has_ck505 = false;
6608                 can_ssc = true;
6609         }
6610
6611         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6612                       has_panel, has_lvds, has_ck505);
6613
6614         /* Ironlake: try to setup display ref clock before DPLL
6615          * enabling. This is only under driver's control after
6616          * PCH B stepping, previous chipset stepping should be
6617          * ignoring this setting.
6618          */
6619         val = I915_READ(PCH_DREF_CONTROL);
6620
6621         /* As we must carefully and slowly disable/enable each source in turn,
6622          * compute the final state we want first and check if we need to
6623          * make any changes at all.
6624          */
6625         final = val;
6626         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6627         if (has_ck505)
6628                 final |= DREF_NONSPREAD_CK505_ENABLE;
6629         else
6630                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6631
6632         final &= ~DREF_SSC_SOURCE_MASK;
6633         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6634         final &= ~DREF_SSC1_ENABLE;
6635
6636         if (has_panel) {
6637                 final |= DREF_SSC_SOURCE_ENABLE;
6638
6639                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6640                         final |= DREF_SSC1_ENABLE;
6641
6642                 if (has_cpu_edp) {
6643                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6644                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6645                         else
6646                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6647                 } else
6648                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6649         } else {
6650                 final |= DREF_SSC_SOURCE_DISABLE;
6651                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6652         }
6653
6654         if (final == val)
6655                 return;
6656
6657         /* Always enable nonspread source */
6658         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6659
6660         if (has_ck505)
6661                 val |= DREF_NONSPREAD_CK505_ENABLE;
6662         else
6663                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6664
6665         if (has_panel) {
6666                 val &= ~DREF_SSC_SOURCE_MASK;
6667                 val |= DREF_SSC_SOURCE_ENABLE;
6668
6669                 /* SSC must be turned on before enabling the CPU output  */
6670                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6671                         DRM_DEBUG_KMS("Using SSC on panel\n");
6672                         val |= DREF_SSC1_ENABLE;
6673                 } else
6674                         val &= ~DREF_SSC1_ENABLE;
6675
6676                 /* Get SSC going before enabling the outputs */
6677                 I915_WRITE(PCH_DREF_CONTROL, val);
6678                 POSTING_READ(PCH_DREF_CONTROL);
6679                 udelay(200);
6680
6681                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6682
6683                 /* Enable CPU source on CPU attached eDP */
6684                 if (has_cpu_edp) {
6685                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6686                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6687                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6688                         } else
6689                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6690                 } else
6691                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6692
6693                 I915_WRITE(PCH_DREF_CONTROL, val);
6694                 POSTING_READ(PCH_DREF_CONTROL);
6695                 udelay(200);
6696         } else {
6697                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6698
6699                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6700
6701                 /* Turn off CPU output */
6702                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6703
6704                 I915_WRITE(PCH_DREF_CONTROL, val);
6705                 POSTING_READ(PCH_DREF_CONTROL);
6706                 udelay(200);
6707
6708                 /* Turn off the SSC source */
6709                 val &= ~DREF_SSC_SOURCE_MASK;
6710                 val |= DREF_SSC_SOURCE_DISABLE;
6711
6712                 /* Turn off SSC1 */
6713                 val &= ~DREF_SSC1_ENABLE;
6714
6715                 I915_WRITE(PCH_DREF_CONTROL, val);
6716                 POSTING_READ(PCH_DREF_CONTROL);
6717                 udelay(200);
6718         }
6719
6720         BUG_ON(val != final);
6721 }
6722
6723 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6724 {
6725         uint32_t tmp;
6726
6727         tmp = I915_READ(SOUTH_CHICKEN2);
6728         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6729         I915_WRITE(SOUTH_CHICKEN2, tmp);
6730
6731         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6732                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6733                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6734
6735         tmp = I915_READ(SOUTH_CHICKEN2);
6736         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6737         I915_WRITE(SOUTH_CHICKEN2, tmp);
6738
6739         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6740                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6741                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6742 }
6743
6744 /* WaMPhyProgramming:hsw */
6745 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6746 {
6747         uint32_t tmp;
6748
6749         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6750         tmp &= ~(0xFF << 24);
6751         tmp |= (0x12 << 24);
6752         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6753
6754         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6755         tmp |= (1 << 11);
6756         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6757
6758         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6759         tmp |= (1 << 11);
6760         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6761
6762         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6763         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6764         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6765
6766         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6767         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6768         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6769
6770         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6771         tmp &= ~(7 << 13);
6772         tmp |= (5 << 13);
6773         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6774
6775         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6776         tmp &= ~(7 << 13);
6777         tmp |= (5 << 13);
6778         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6779
6780         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6781         tmp &= ~0xFF;
6782         tmp |= 0x1C;
6783         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6784
6785         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6786         tmp &= ~0xFF;
6787         tmp |= 0x1C;
6788         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6789
6790         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6791         tmp &= ~(0xFF << 16);
6792         tmp |= (0x1C << 16);
6793         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6794
6795         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6796         tmp &= ~(0xFF << 16);
6797         tmp |= (0x1C << 16);
6798         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6799
6800         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6801         tmp |= (1 << 27);
6802         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6803
6804         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6805         tmp |= (1 << 27);
6806         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6807
6808         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6809         tmp &= ~(0xF << 28);
6810         tmp |= (4 << 28);
6811         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6812
6813         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6814         tmp &= ~(0xF << 28);
6815         tmp |= (4 << 28);
6816         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6817 }
6818
6819 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6820  * Programming" based on the parameters passed:
6821  * - Sequence to enable CLKOUT_DP
6822  * - Sequence to enable CLKOUT_DP without spread
6823  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6824  */
6825 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6826                                  bool with_fdi)
6827 {
6828         struct drm_i915_private *dev_priv = dev->dev_private;
6829         uint32_t reg, tmp;
6830
6831         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6832                 with_spread = true;
6833         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6834                  with_fdi, "LP PCH doesn't have FDI\n"))
6835                 with_fdi = false;
6836
6837         mutex_lock(&dev_priv->dpio_lock);
6838
6839         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6840         tmp &= ~SBI_SSCCTL_DISABLE;
6841         tmp |= SBI_SSCCTL_PATHALT;
6842         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6843
6844         udelay(24);
6845
6846         if (with_spread) {
6847                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6848                 tmp &= ~SBI_SSCCTL_PATHALT;
6849                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6850
6851                 if (with_fdi) {
6852                         lpt_reset_fdi_mphy(dev_priv);
6853                         lpt_program_fdi_mphy(dev_priv);
6854                 }
6855         }
6856
6857         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6858                SBI_GEN0 : SBI_DBUFF0;
6859         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6860         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6861         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6862
6863         mutex_unlock(&dev_priv->dpio_lock);
6864 }
6865
6866 /* Sequence to disable CLKOUT_DP */
6867 static void lpt_disable_clkout_dp(struct drm_device *dev)
6868 {
6869         struct drm_i915_private *dev_priv = dev->dev_private;
6870         uint32_t reg, tmp;
6871
6872         mutex_lock(&dev_priv->dpio_lock);
6873
6874         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6875                SBI_GEN0 : SBI_DBUFF0;
6876         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6877         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6878         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6879
6880         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6881         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6882                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6883                         tmp |= SBI_SSCCTL_PATHALT;
6884                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6885                         udelay(32);
6886                 }
6887                 tmp |= SBI_SSCCTL_DISABLE;
6888                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6889         }
6890
6891         mutex_unlock(&dev_priv->dpio_lock);
6892 }
6893
6894 static void lpt_init_pch_refclk(struct drm_device *dev)
6895 {
6896         struct intel_encoder *encoder;
6897         bool has_vga = false;
6898
6899         for_each_intel_encoder(dev, encoder) {
6900                 switch (encoder->type) {
6901                 case INTEL_OUTPUT_ANALOG:
6902                         has_vga = true;
6903                         break;
6904                 }
6905         }
6906
6907         if (has_vga)
6908                 lpt_enable_clkout_dp(dev, true, true);
6909         else
6910                 lpt_disable_clkout_dp(dev);
6911 }
6912
6913 /*
6914  * Initialize reference clocks when the driver loads
6915  */
6916 void intel_init_pch_refclk(struct drm_device *dev)
6917 {
6918         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6919                 ironlake_init_pch_refclk(dev);
6920         else if (HAS_PCH_LPT(dev))
6921                 lpt_init_pch_refclk(dev);
6922 }
6923
6924 static int ironlake_get_refclk(struct drm_crtc *crtc)
6925 {
6926         struct drm_device *dev = crtc->dev;
6927         struct drm_i915_private *dev_priv = dev->dev_private;
6928         struct intel_encoder *encoder;
6929         int num_connectors = 0;
6930         bool is_lvds = false;
6931
6932         for_each_encoder_on_crtc(dev, crtc, encoder) {
6933                 switch (encoder->type) {
6934                 case INTEL_OUTPUT_LVDS:
6935                         is_lvds = true;
6936                         break;
6937                 }
6938                 num_connectors++;
6939         }
6940
6941         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6942                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6943                               dev_priv->vbt.lvds_ssc_freq);
6944                 return dev_priv->vbt.lvds_ssc_freq;
6945         }
6946
6947         return 120000;
6948 }
6949
6950 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6951 {
6952         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6954         int pipe = intel_crtc->pipe;
6955         uint32_t val;
6956
6957         val = 0;
6958
6959         switch (intel_crtc->config.pipe_bpp) {
6960         case 18:
6961                 val |= PIPECONF_6BPC;
6962                 break;
6963         case 24:
6964                 val |= PIPECONF_8BPC;
6965                 break;
6966         case 30:
6967                 val |= PIPECONF_10BPC;
6968                 break;
6969         case 36:
6970                 val |= PIPECONF_12BPC;
6971                 break;
6972         default:
6973                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6974                 BUG();
6975         }
6976
6977         if (intel_crtc->config.dither)
6978                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6979
6980         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6981                 val |= PIPECONF_INTERLACED_ILK;
6982         else
6983                 val |= PIPECONF_PROGRESSIVE;
6984
6985         if (intel_crtc->config.limited_color_range)
6986                 val |= PIPECONF_COLOR_RANGE_SELECT;
6987
6988         I915_WRITE(PIPECONF(pipe), val);
6989         POSTING_READ(PIPECONF(pipe));
6990 }
6991
6992 /*
6993  * Set up the pipe CSC unit.
6994  *
6995  * Currently only full range RGB to limited range RGB conversion
6996  * is supported, but eventually this should handle various
6997  * RGB<->YCbCr scenarios as well.
6998  */
6999 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7000 {
7001         struct drm_device *dev = crtc->dev;
7002         struct drm_i915_private *dev_priv = dev->dev_private;
7003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7004         int pipe = intel_crtc->pipe;
7005         uint16_t coeff = 0x7800; /* 1.0 */
7006
7007         /*
7008          * TODO: Check what kind of values actually come out of the pipe
7009          * with these coeff/postoff values and adjust to get the best
7010          * accuracy. Perhaps we even need to take the bpc value into
7011          * consideration.
7012          */
7013
7014         if (intel_crtc->config.limited_color_range)
7015                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7016
7017         /*
7018          * GY/GU and RY/RU should be the other way around according
7019          * to BSpec, but reality doesn't agree. Just set them up in
7020          * a way that results in the correct picture.
7021          */
7022         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7023         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7024
7025         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7026         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7027
7028         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7029         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7030
7031         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7032         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7033         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7034
7035         if (INTEL_INFO(dev)->gen > 6) {
7036                 uint16_t postoff = 0;
7037
7038                 if (intel_crtc->config.limited_color_range)
7039                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7040
7041                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7042                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7043                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7044
7045                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7046         } else {
7047                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7048
7049                 if (intel_crtc->config.limited_color_range)
7050                         mode |= CSC_BLACK_SCREEN_OFFSET;
7051
7052                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7053         }
7054 }
7055
7056 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7057 {
7058         struct drm_device *dev = crtc->dev;
7059         struct drm_i915_private *dev_priv = dev->dev_private;
7060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7061         enum pipe pipe = intel_crtc->pipe;
7062         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7063         uint32_t val;
7064
7065         val = 0;
7066
7067         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7068                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7069
7070         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7071                 val |= PIPECONF_INTERLACED_ILK;
7072         else
7073                 val |= PIPECONF_PROGRESSIVE;
7074
7075         I915_WRITE(PIPECONF(cpu_transcoder), val);
7076         POSTING_READ(PIPECONF(cpu_transcoder));
7077
7078         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7079         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7080
7081         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7082                 val = 0;
7083
7084                 switch (intel_crtc->config.pipe_bpp) {
7085                 case 18:
7086                         val |= PIPEMISC_DITHER_6_BPC;
7087                         break;
7088                 case 24:
7089                         val |= PIPEMISC_DITHER_8_BPC;
7090                         break;
7091                 case 30:
7092                         val |= PIPEMISC_DITHER_10_BPC;
7093                         break;
7094                 case 36:
7095                         val |= PIPEMISC_DITHER_12_BPC;
7096                         break;
7097                 default:
7098                         /* Case prevented by pipe_config_set_bpp. */
7099                         BUG();
7100                 }
7101
7102                 if (intel_crtc->config.dither)
7103                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7104
7105                 I915_WRITE(PIPEMISC(pipe), val);
7106         }
7107 }
7108
7109 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7110                                     intel_clock_t *clock,
7111                                     bool *has_reduced_clock,
7112                                     intel_clock_t *reduced_clock)
7113 {
7114         struct drm_device *dev = crtc->dev;
7115         struct drm_i915_private *dev_priv = dev->dev_private;
7116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7117         int refclk;
7118         const intel_limit_t *limit;
7119         bool ret, is_lvds = false;
7120
7121         is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7122
7123         refclk = ironlake_get_refclk(crtc);
7124
7125         /*
7126          * Returns a set of divisors for the desired target clock with the given
7127          * refclk, or FALSE.  The returned values represent the clock equation:
7128          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7129          */
7130         limit = intel_limit(intel_crtc, refclk);
7131         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7132                                           intel_crtc->config.port_clock,
7133                                           refclk, NULL, clock);
7134         if (!ret)
7135                 return false;
7136
7137         if (is_lvds && dev_priv->lvds_downclock_avail) {
7138                 /*
7139                  * Ensure we match the reduced clock's P to the target clock.
7140                  * If the clocks don't match, we can't switch the display clock
7141                  * by using the FP0/FP1. In such case we will disable the LVDS
7142                  * downclock feature.
7143                 */
7144                 *has_reduced_clock =
7145                         dev_priv->display.find_dpll(limit, intel_crtc,
7146                                                     dev_priv->lvds_downclock,
7147                                                     refclk, clock,
7148                                                     reduced_clock);
7149         }
7150
7151         return true;
7152 }
7153
7154 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7155 {
7156         /*
7157          * Account for spread spectrum to avoid
7158          * oversubscribing the link. Max center spread
7159          * is 2.5%; use 5% for safety's sake.
7160          */
7161         u32 bps = target_clock * bpp * 21 / 20;
7162         return DIV_ROUND_UP(bps, link_bw * 8);
7163 }
7164
7165 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7166 {
7167         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7168 }
7169
7170 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7171                                       u32 *fp,
7172                                       intel_clock_t *reduced_clock, u32 *fp2)
7173 {
7174         struct drm_crtc *crtc = &intel_crtc->base;
7175         struct drm_device *dev = crtc->dev;
7176         struct drm_i915_private *dev_priv = dev->dev_private;
7177         struct intel_encoder *intel_encoder;
7178         uint32_t dpll;
7179         int factor, num_connectors = 0;
7180         bool is_lvds = false, is_sdvo = false;
7181
7182         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7183                 switch (intel_encoder->type) {
7184                 case INTEL_OUTPUT_LVDS:
7185                         is_lvds = true;
7186                         break;
7187                 case INTEL_OUTPUT_SDVO:
7188                 case INTEL_OUTPUT_HDMI:
7189                         is_sdvo = true;
7190                         break;
7191                 }
7192
7193                 num_connectors++;
7194         }
7195
7196         /* Enable autotuning of the PLL clock (if permissible) */
7197         factor = 21;
7198         if (is_lvds) {
7199                 if ((intel_panel_use_ssc(dev_priv) &&
7200                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7201                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7202                         factor = 25;
7203         } else if (intel_crtc->config.sdvo_tv_clock)
7204                 factor = 20;
7205
7206         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7207                 *fp |= FP_CB_TUNE;
7208
7209         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7210                 *fp2 |= FP_CB_TUNE;
7211
7212         dpll = 0;
7213
7214         if (is_lvds)
7215                 dpll |= DPLLB_MODE_LVDS;
7216         else
7217                 dpll |= DPLLB_MODE_DAC_SERIAL;
7218
7219         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7220                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7221
7222         if (is_sdvo)
7223                 dpll |= DPLL_SDVO_HIGH_SPEED;
7224         if (intel_crtc->config.has_dp_encoder)
7225                 dpll |= DPLL_SDVO_HIGH_SPEED;
7226
7227         /* compute bitmask from p1 value */
7228         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7229         /* also FPA1 */
7230         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7231
7232         switch (intel_crtc->config.dpll.p2) {
7233         case 5:
7234                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7235                 break;
7236         case 7:
7237                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7238                 break;
7239         case 10:
7240                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7241                 break;
7242         case 14:
7243                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7244                 break;
7245         }
7246
7247         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7248                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7249         else
7250                 dpll |= PLL_REF_INPUT_DREFCLK;
7251
7252         return dpll | DPLL_VCO_ENABLE;
7253 }
7254
7255 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7256                                   int x, int y,
7257                                   struct drm_framebuffer *fb)
7258 {
7259         struct drm_device *dev = crtc->base.dev;
7260         intel_clock_t clock, reduced_clock;
7261         u32 dpll = 0, fp = 0, fp2 = 0;
7262         bool ok, has_reduced_clock = false;
7263         bool is_lvds = false;
7264         struct intel_shared_dpll *pll;
7265
7266         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7267
7268         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7269              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7270
7271         ok = ironlake_compute_clocks(&crtc->base, &clock,
7272                                      &has_reduced_clock, &reduced_clock);
7273         if (!ok && !crtc->config.clock_set) {
7274                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7275                 return -EINVAL;
7276         }
7277         /* Compat-code for transition, will disappear. */
7278         if (!crtc->config.clock_set) {
7279                 crtc->config.dpll.n = clock.n;
7280                 crtc->config.dpll.m1 = clock.m1;
7281                 crtc->config.dpll.m2 = clock.m2;
7282                 crtc->config.dpll.p1 = clock.p1;
7283                 crtc->config.dpll.p2 = clock.p2;
7284         }
7285
7286         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7287         if (crtc->config.has_pch_encoder) {
7288                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7289                 if (has_reduced_clock)
7290                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7291
7292                 dpll = ironlake_compute_dpll(crtc,
7293                                              &fp, &reduced_clock,
7294                                              has_reduced_clock ? &fp2 : NULL);
7295
7296                 crtc->config.dpll_hw_state.dpll = dpll;
7297                 crtc->config.dpll_hw_state.fp0 = fp;
7298                 if (has_reduced_clock)
7299                         crtc->config.dpll_hw_state.fp1 = fp2;
7300                 else
7301                         crtc->config.dpll_hw_state.fp1 = fp;
7302
7303                 pll = intel_get_shared_dpll(crtc);
7304                 if (pll == NULL) {
7305                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7306                                          pipe_name(crtc->pipe));
7307                         return -EINVAL;
7308                 }
7309         } else
7310                 intel_put_shared_dpll(crtc);
7311
7312         if (is_lvds && has_reduced_clock && i915.powersave)
7313                 crtc->lowfreq_avail = true;
7314         else
7315                 crtc->lowfreq_avail = false;
7316
7317         return 0;
7318 }
7319
7320 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7321                                          struct intel_link_m_n *m_n)
7322 {
7323         struct drm_device *dev = crtc->base.dev;
7324         struct drm_i915_private *dev_priv = dev->dev_private;
7325         enum pipe pipe = crtc->pipe;
7326
7327         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7328         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7329         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7330                 & ~TU_SIZE_MASK;
7331         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7332         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7333                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7334 }
7335
7336 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7337                                          enum transcoder transcoder,
7338                                          struct intel_link_m_n *m_n,
7339                                          struct intel_link_m_n *m2_n2)
7340 {
7341         struct drm_device *dev = crtc->base.dev;
7342         struct drm_i915_private *dev_priv = dev->dev_private;
7343         enum pipe pipe = crtc->pipe;
7344
7345         if (INTEL_INFO(dev)->gen >= 5) {
7346                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7347                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7348                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7349                         & ~TU_SIZE_MASK;
7350                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7351                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7352                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7353                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7354                  * gen < 8) and if DRRS is supported (to make sure the
7355                  * registers are not unnecessarily read).
7356                  */
7357                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7358                         crtc->config.has_drrs) {
7359                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7360                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7361                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7362                                         & ~TU_SIZE_MASK;
7363                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7364                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7365                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7366                 }
7367         } else {
7368                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7369                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7370                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7371                         & ~TU_SIZE_MASK;
7372                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7373                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7374                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7375         }
7376 }
7377
7378 void intel_dp_get_m_n(struct intel_crtc *crtc,
7379                       struct intel_crtc_config *pipe_config)
7380 {
7381         if (crtc->config.has_pch_encoder)
7382                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7383         else
7384                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7385                                              &pipe_config->dp_m_n,
7386                                              &pipe_config->dp_m2_n2);
7387 }
7388
7389 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7390                                         struct intel_crtc_config *pipe_config)
7391 {
7392         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7393                                      &pipe_config->fdi_m_n, NULL);
7394 }
7395
7396 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7397                                      struct intel_crtc_config *pipe_config)
7398 {
7399         struct drm_device *dev = crtc->base.dev;
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401         uint32_t tmp;
7402
7403         tmp = I915_READ(PF_CTL(crtc->pipe));
7404
7405         if (tmp & PF_ENABLE) {
7406                 pipe_config->pch_pfit.enabled = true;
7407                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7408                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7409
7410                 /* We currently do not free assignements of panel fitters on
7411                  * ivb/hsw (since we don't use the higher upscaling modes which
7412                  * differentiates them) so just WARN about this case for now. */
7413                 if (IS_GEN7(dev)) {
7414                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7415                                 PF_PIPE_SEL_IVB(crtc->pipe));
7416                 }
7417         }
7418 }
7419
7420 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7421                                       struct intel_plane_config *plane_config)
7422 {
7423         struct drm_device *dev = crtc->base.dev;
7424         struct drm_i915_private *dev_priv = dev->dev_private;
7425         u32 val, base, offset;
7426         int pipe = crtc->pipe, plane = crtc->plane;
7427         int fourcc, pixel_format;
7428         int aligned_height;
7429
7430         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7431         if (!crtc->base.primary->fb) {
7432                 DRM_DEBUG_KMS("failed to alloc fb\n");
7433                 return;
7434         }
7435
7436         val = I915_READ(DSPCNTR(plane));
7437
7438         if (INTEL_INFO(dev)->gen >= 4)
7439                 if (val & DISPPLANE_TILED)
7440                         plane_config->tiled = true;
7441
7442         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7443         fourcc = intel_format_to_fourcc(pixel_format);
7444         crtc->base.primary->fb->pixel_format = fourcc;
7445         crtc->base.primary->fb->bits_per_pixel =
7446                 drm_format_plane_cpp(fourcc, 0) * 8;
7447
7448         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7449         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7450                 offset = I915_READ(DSPOFFSET(plane));
7451         } else {
7452                 if (plane_config->tiled)
7453                         offset = I915_READ(DSPTILEOFF(plane));
7454                 else
7455                         offset = I915_READ(DSPLINOFF(plane));
7456         }
7457         plane_config->base = base;
7458
7459         val = I915_READ(PIPESRC(pipe));
7460         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7461         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7462
7463         val = I915_READ(DSPSTRIDE(pipe));
7464         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7465
7466         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7467                                             plane_config->tiled);
7468
7469         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7470                                         aligned_height);
7471
7472         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7473                       pipe, plane, crtc->base.primary->fb->width,
7474                       crtc->base.primary->fb->height,
7475                       crtc->base.primary->fb->bits_per_pixel, base,
7476                       crtc->base.primary->fb->pitches[0],
7477                       plane_config->size);
7478 }
7479
7480 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7481                                      struct intel_crtc_config *pipe_config)
7482 {
7483         struct drm_device *dev = crtc->base.dev;
7484         struct drm_i915_private *dev_priv = dev->dev_private;
7485         uint32_t tmp;
7486
7487         if (!intel_display_power_is_enabled(dev_priv,
7488                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7489                 return false;
7490
7491         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7492         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7493
7494         tmp = I915_READ(PIPECONF(crtc->pipe));
7495         if (!(tmp & PIPECONF_ENABLE))
7496                 return false;
7497
7498         switch (tmp & PIPECONF_BPC_MASK) {
7499         case PIPECONF_6BPC:
7500                 pipe_config->pipe_bpp = 18;
7501                 break;
7502         case PIPECONF_8BPC:
7503                 pipe_config->pipe_bpp = 24;
7504                 break;
7505         case PIPECONF_10BPC:
7506                 pipe_config->pipe_bpp = 30;
7507                 break;
7508         case PIPECONF_12BPC:
7509                 pipe_config->pipe_bpp = 36;
7510                 break;
7511         default:
7512                 break;
7513         }
7514
7515         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7516                 pipe_config->limited_color_range = true;
7517
7518         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7519                 struct intel_shared_dpll *pll;
7520
7521                 pipe_config->has_pch_encoder = true;
7522
7523                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7524                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7525                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7526
7527                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7528
7529                 if (HAS_PCH_IBX(dev_priv->dev)) {
7530                         pipe_config->shared_dpll =
7531                                 (enum intel_dpll_id) crtc->pipe;
7532                 } else {
7533                         tmp = I915_READ(PCH_DPLL_SEL);
7534                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7535                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7536                         else
7537                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7538                 }
7539
7540                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7541
7542                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7543                                            &pipe_config->dpll_hw_state));
7544
7545                 tmp = pipe_config->dpll_hw_state.dpll;
7546                 pipe_config->pixel_multiplier =
7547                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7548                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7549
7550                 ironlake_pch_clock_get(crtc, pipe_config);
7551         } else {
7552                 pipe_config->pixel_multiplier = 1;
7553         }
7554
7555         intel_get_pipe_timings(crtc, pipe_config);
7556
7557         ironlake_get_pfit_config(crtc, pipe_config);
7558
7559         return true;
7560 }
7561
7562 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7563 {
7564         struct drm_device *dev = dev_priv->dev;
7565         struct intel_crtc *crtc;
7566
7567         for_each_intel_crtc(dev, crtc)
7568                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7569                      pipe_name(crtc->pipe));
7570
7571         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7572         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7573         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7574         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7575         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7576         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7577              "CPU PWM1 enabled\n");
7578         if (IS_HASWELL(dev))
7579                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7580                      "CPU PWM2 enabled\n");
7581         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7582              "PCH PWM1 enabled\n");
7583         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7584              "Utility pin enabled\n");
7585         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7586
7587         /*
7588          * In theory we can still leave IRQs enabled, as long as only the HPD
7589          * interrupts remain enabled. We used to check for that, but since it's
7590          * gen-specific and since we only disable LCPLL after we fully disable
7591          * the interrupts, the check below should be enough.
7592          */
7593         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7594 }
7595
7596 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7597 {
7598         struct drm_device *dev = dev_priv->dev;
7599
7600         if (IS_HASWELL(dev))
7601                 return I915_READ(D_COMP_HSW);
7602         else
7603                 return I915_READ(D_COMP_BDW);
7604 }
7605
7606 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7607 {
7608         struct drm_device *dev = dev_priv->dev;
7609
7610         if (IS_HASWELL(dev)) {
7611                 mutex_lock(&dev_priv->rps.hw_lock);
7612                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7613                                             val))
7614                         DRM_ERROR("Failed to write to D_COMP\n");
7615                 mutex_unlock(&dev_priv->rps.hw_lock);
7616         } else {
7617                 I915_WRITE(D_COMP_BDW, val);
7618                 POSTING_READ(D_COMP_BDW);
7619         }
7620 }
7621
7622 /*
7623  * This function implements pieces of two sequences from BSpec:
7624  * - Sequence for display software to disable LCPLL
7625  * - Sequence for display software to allow package C8+
7626  * The steps implemented here are just the steps that actually touch the LCPLL
7627  * register. Callers should take care of disabling all the display engine
7628  * functions, doing the mode unset, fixing interrupts, etc.
7629  */
7630 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7631                               bool switch_to_fclk, bool allow_power_down)
7632 {
7633         uint32_t val;
7634
7635         assert_can_disable_lcpll(dev_priv);
7636
7637         val = I915_READ(LCPLL_CTL);
7638
7639         if (switch_to_fclk) {
7640                 val |= LCPLL_CD_SOURCE_FCLK;
7641                 I915_WRITE(LCPLL_CTL, val);
7642
7643                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7644                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7645                         DRM_ERROR("Switching to FCLK failed\n");
7646
7647                 val = I915_READ(LCPLL_CTL);
7648         }
7649
7650         val |= LCPLL_PLL_DISABLE;
7651         I915_WRITE(LCPLL_CTL, val);
7652         POSTING_READ(LCPLL_CTL);
7653
7654         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7655                 DRM_ERROR("LCPLL still locked\n");
7656
7657         val = hsw_read_dcomp(dev_priv);
7658         val |= D_COMP_COMP_DISABLE;
7659         hsw_write_dcomp(dev_priv, val);
7660         ndelay(100);
7661
7662         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7663                      1))
7664                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7665
7666         if (allow_power_down) {
7667                 val = I915_READ(LCPLL_CTL);
7668                 val |= LCPLL_POWER_DOWN_ALLOW;
7669                 I915_WRITE(LCPLL_CTL, val);
7670                 POSTING_READ(LCPLL_CTL);
7671         }
7672 }
7673
7674 /*
7675  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7676  * source.
7677  */
7678 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7679 {
7680         uint32_t val;
7681
7682         val = I915_READ(LCPLL_CTL);
7683
7684         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7685                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7686                 return;
7687
7688         /*
7689          * Make sure we're not on PC8 state before disabling PC8, otherwise
7690          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7691          *
7692          * The other problem is that hsw_restore_lcpll() is called as part of
7693          * the runtime PM resume sequence, so we can't just call
7694          * gen6_gt_force_wake_get() because that function calls
7695          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7696          * while we are on the resume sequence. So to solve this problem we have
7697          * to call special forcewake code that doesn't touch runtime PM and
7698          * doesn't enable the forcewake delayed work.
7699          */
7700         spin_lock_irq(&dev_priv->uncore.lock);
7701         if (dev_priv->uncore.forcewake_count++ == 0)
7702                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7703         spin_unlock_irq(&dev_priv->uncore.lock);
7704
7705         if (val & LCPLL_POWER_DOWN_ALLOW) {
7706                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7707                 I915_WRITE(LCPLL_CTL, val);
7708                 POSTING_READ(LCPLL_CTL);
7709         }
7710
7711         val = hsw_read_dcomp(dev_priv);
7712         val |= D_COMP_COMP_FORCE;
7713         val &= ~D_COMP_COMP_DISABLE;
7714         hsw_write_dcomp(dev_priv, val);
7715
7716         val = I915_READ(LCPLL_CTL);
7717         val &= ~LCPLL_PLL_DISABLE;
7718         I915_WRITE(LCPLL_CTL, val);
7719
7720         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7721                 DRM_ERROR("LCPLL not locked yet\n");
7722
7723         if (val & LCPLL_CD_SOURCE_FCLK) {
7724                 val = I915_READ(LCPLL_CTL);
7725                 val &= ~LCPLL_CD_SOURCE_FCLK;
7726                 I915_WRITE(LCPLL_CTL, val);
7727
7728                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7729                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7730                         DRM_ERROR("Switching back to LCPLL failed\n");
7731         }
7732
7733         /* See the big comment above. */
7734         spin_lock_irq(&dev_priv->uncore.lock);
7735         if (--dev_priv->uncore.forcewake_count == 0)
7736                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7737         spin_unlock_irq(&dev_priv->uncore.lock);
7738 }
7739
7740 /*
7741  * Package states C8 and deeper are really deep PC states that can only be
7742  * reached when all the devices on the system allow it, so even if the graphics
7743  * device allows PC8+, it doesn't mean the system will actually get to these
7744  * states. Our driver only allows PC8+ when going into runtime PM.
7745  *
7746  * The requirements for PC8+ are that all the outputs are disabled, the power
7747  * well is disabled and most interrupts are disabled, and these are also
7748  * requirements for runtime PM. When these conditions are met, we manually do
7749  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7750  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7751  * hang the machine.
7752  *
7753  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7754  * the state of some registers, so when we come back from PC8+ we need to
7755  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7756  * need to take care of the registers kept by RC6. Notice that this happens even
7757  * if we don't put the device in PCI D3 state (which is what currently happens
7758  * because of the runtime PM support).
7759  *
7760  * For more, read "Display Sequences for Package C8" on the hardware
7761  * documentation.
7762  */
7763 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7764 {
7765         struct drm_device *dev = dev_priv->dev;
7766         uint32_t val;
7767
7768         DRM_DEBUG_KMS("Enabling package C8+\n");
7769
7770         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7771                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7772                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7773                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7774         }
7775
7776         lpt_disable_clkout_dp(dev);
7777         hsw_disable_lcpll(dev_priv, true, true);
7778 }
7779
7780 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7781 {
7782         struct drm_device *dev = dev_priv->dev;
7783         uint32_t val;
7784
7785         DRM_DEBUG_KMS("Disabling package C8+\n");
7786
7787         hsw_restore_lcpll(dev_priv);
7788         lpt_init_pch_refclk(dev);
7789
7790         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7791                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7792                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7793                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7794         }
7795
7796         intel_prepare_ddi(dev);
7797 }
7798
7799 static void snb_modeset_global_resources(struct drm_device *dev)
7800 {
7801         modeset_update_crtc_power_domains(dev);
7802 }
7803
7804 static void haswell_modeset_global_resources(struct drm_device *dev)
7805 {
7806         modeset_update_crtc_power_domains(dev);
7807 }
7808
7809 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7810                                  int x, int y,
7811                                  struct drm_framebuffer *fb)
7812 {
7813         if (!intel_ddi_pll_select(crtc))
7814                 return -EINVAL;
7815
7816         crtc->lowfreq_avail = false;
7817
7818         return 0;
7819 }
7820
7821 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7822                                 enum port port,
7823                                 struct intel_crtc_config *pipe_config)
7824 {
7825         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7826
7827         switch (pipe_config->ddi_pll_sel) {
7828         case PORT_CLK_SEL_WRPLL1:
7829                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7830                 break;
7831         case PORT_CLK_SEL_WRPLL2:
7832                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7833                 break;
7834         }
7835 }
7836
7837 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7838                                        struct intel_crtc_config *pipe_config)
7839 {
7840         struct drm_device *dev = crtc->base.dev;
7841         struct drm_i915_private *dev_priv = dev->dev_private;
7842         struct intel_shared_dpll *pll;
7843         enum port port;
7844         uint32_t tmp;
7845
7846         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7847
7848         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7849
7850         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7851
7852         if (pipe_config->shared_dpll >= 0) {
7853                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7854
7855                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7856                                            &pipe_config->dpll_hw_state));
7857         }
7858
7859         /*
7860          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7861          * DDI E. So just check whether this pipe is wired to DDI E and whether
7862          * the PCH transcoder is on.
7863          */
7864         if (INTEL_INFO(dev)->gen < 9 &&
7865             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7866                 pipe_config->has_pch_encoder = true;
7867
7868                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7869                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7870                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7871
7872                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7873         }
7874 }
7875
7876 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7877                                     struct intel_crtc_config *pipe_config)
7878 {
7879         struct drm_device *dev = crtc->base.dev;
7880         struct drm_i915_private *dev_priv = dev->dev_private;
7881         enum intel_display_power_domain pfit_domain;
7882         uint32_t tmp;
7883
7884         if (!intel_display_power_is_enabled(dev_priv,
7885                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7886                 return false;
7887
7888         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7889         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7890
7891         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7892         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7893                 enum pipe trans_edp_pipe;
7894                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7895                 default:
7896                         WARN(1, "unknown pipe linked to edp transcoder\n");
7897                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7898                 case TRANS_DDI_EDP_INPUT_A_ON:
7899                         trans_edp_pipe = PIPE_A;
7900                         break;
7901                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7902                         trans_edp_pipe = PIPE_B;
7903                         break;
7904                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7905                         trans_edp_pipe = PIPE_C;
7906                         break;
7907                 }
7908
7909                 if (trans_edp_pipe == crtc->pipe)
7910                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7911         }
7912
7913         if (!intel_display_power_is_enabled(dev_priv,
7914                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7915                 return false;
7916
7917         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7918         if (!(tmp & PIPECONF_ENABLE))
7919                 return false;
7920
7921         haswell_get_ddi_port_state(crtc, pipe_config);
7922
7923         intel_get_pipe_timings(crtc, pipe_config);
7924
7925         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7926         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7927                 ironlake_get_pfit_config(crtc, pipe_config);
7928
7929         if (IS_HASWELL(dev))
7930                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7931                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7932
7933         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7934                 pipe_config->pixel_multiplier =
7935                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7936         } else {
7937                 pipe_config->pixel_multiplier = 1;
7938         }
7939
7940         return true;
7941 }
7942
7943 static struct {
7944         int clock;
7945         u32 config;
7946 } hdmi_audio_clock[] = {
7947         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7948         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7949         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7950         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7951         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7952         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7953         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7954         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7955         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7956         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7957 };
7958
7959 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7960 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7961 {
7962         int i;
7963
7964         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7965                 if (mode->clock == hdmi_audio_clock[i].clock)
7966                         break;
7967         }
7968
7969         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7970                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7971                 i = 1;
7972         }
7973
7974         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7975                       hdmi_audio_clock[i].clock,
7976                       hdmi_audio_clock[i].config);
7977
7978         return hdmi_audio_clock[i].config;
7979 }
7980
7981 static bool intel_eld_uptodate(struct drm_connector *connector,
7982                                int reg_eldv, uint32_t bits_eldv,
7983                                int reg_elda, uint32_t bits_elda,
7984                                int reg_edid)
7985 {
7986         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7987         uint8_t *eld = connector->eld;
7988         uint32_t i;
7989
7990         i = I915_READ(reg_eldv);
7991         i &= bits_eldv;
7992
7993         if (!eld[0])
7994                 return !i;
7995
7996         if (!i)
7997                 return false;
7998
7999         i = I915_READ(reg_elda);
8000         i &= ~bits_elda;
8001         I915_WRITE(reg_elda, i);
8002
8003         for (i = 0; i < eld[2]; i++)
8004                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8005                         return false;
8006
8007         return true;
8008 }
8009
8010 static void g4x_write_eld(struct drm_connector *connector,
8011                           struct drm_crtc *crtc,
8012                           struct drm_display_mode *mode)
8013 {
8014         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8015         uint8_t *eld = connector->eld;
8016         uint32_t eldv;
8017         uint32_t len;
8018         uint32_t i;
8019
8020         i = I915_READ(G4X_AUD_VID_DID);
8021
8022         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8023                 eldv = G4X_ELDV_DEVCL_DEVBLC;
8024         else
8025                 eldv = G4X_ELDV_DEVCTG;
8026
8027         if (intel_eld_uptodate(connector,
8028                                G4X_AUD_CNTL_ST, eldv,
8029                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8030                                G4X_HDMIW_HDMIEDID))
8031                 return;
8032
8033         i = I915_READ(G4X_AUD_CNTL_ST);
8034         i &= ~(eldv | G4X_ELD_ADDR);
8035         len = (i >> 9) & 0x1f;          /* ELD buffer size */
8036         I915_WRITE(G4X_AUD_CNTL_ST, i);
8037
8038         if (!eld[0])
8039                 return;
8040
8041         len = min_t(uint8_t, eld[2], len);
8042         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8043         for (i = 0; i < len; i++)
8044                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8045
8046         i = I915_READ(G4X_AUD_CNTL_ST);
8047         i |= eldv;
8048         I915_WRITE(G4X_AUD_CNTL_ST, i);
8049 }
8050
8051 static void haswell_write_eld(struct drm_connector *connector,
8052                               struct drm_crtc *crtc,
8053                               struct drm_display_mode *mode)
8054 {
8055         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8057         uint8_t *eld = connector->eld;
8058         uint32_t eldv;
8059         uint32_t i;
8060         int len;
8061         int pipe = to_intel_crtc(crtc)->pipe;
8062         int tmp;
8063
8064         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8065         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8066         int aud_config = HSW_AUD_CFG(pipe);
8067         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8068
8069         /* Audio output enable */
8070         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8071         tmp = I915_READ(aud_cntrl_st2);
8072         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8073         I915_WRITE(aud_cntrl_st2, tmp);
8074         POSTING_READ(aud_cntrl_st2);
8075
8076         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8077
8078         /* Set ELD valid state */
8079         tmp = I915_READ(aud_cntrl_st2);
8080         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8081         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8082         I915_WRITE(aud_cntrl_st2, tmp);
8083         tmp = I915_READ(aud_cntrl_st2);
8084         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8085
8086         /* Enable HDMI mode */
8087         tmp = I915_READ(aud_config);
8088         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8089         /* clear N_programing_enable and N_value_index */
8090         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8091         I915_WRITE(aud_config, tmp);
8092
8093         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8094
8095         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8096
8097         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8098                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8099                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8100                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8101         } else {
8102                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8103         }
8104
8105         if (intel_eld_uptodate(connector,
8106                                aud_cntrl_st2, eldv,
8107                                aud_cntl_st, IBX_ELD_ADDRESS,
8108                                hdmiw_hdmiedid))
8109                 return;
8110
8111         i = I915_READ(aud_cntrl_st2);
8112         i &= ~eldv;
8113         I915_WRITE(aud_cntrl_st2, i);
8114
8115         if (!eld[0])
8116                 return;
8117
8118         i = I915_READ(aud_cntl_st);
8119         i &= ~IBX_ELD_ADDRESS;
8120         I915_WRITE(aud_cntl_st, i);
8121         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
8122         DRM_DEBUG_DRIVER("port num:%d\n", i);
8123
8124         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8125         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8126         for (i = 0; i < len; i++)
8127                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8128
8129         i = I915_READ(aud_cntrl_st2);
8130         i |= eldv;
8131         I915_WRITE(aud_cntrl_st2, i);
8132
8133 }
8134
8135 static void ironlake_write_eld(struct drm_connector *connector,
8136                                struct drm_crtc *crtc,
8137                                struct drm_display_mode *mode)
8138 {
8139         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8141         uint8_t *eld = connector->eld;
8142         uint32_t eldv;
8143         uint32_t i;
8144         int len;
8145         int hdmiw_hdmiedid;
8146         int aud_config;
8147         int aud_cntl_st;
8148         int aud_cntrl_st2;
8149         int pipe = to_intel_crtc(crtc)->pipe;
8150
8151         if (HAS_PCH_IBX(connector->dev)) {
8152                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8153                 aud_config = IBX_AUD_CFG(pipe);
8154                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8155                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8156         } else if (IS_VALLEYVIEW(connector->dev)) {
8157                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8158                 aud_config = VLV_AUD_CFG(pipe);
8159                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8160                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8161         } else {
8162                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8163                 aud_config = CPT_AUD_CFG(pipe);
8164                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8165                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8166         }
8167
8168         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8169
8170         if (IS_VALLEYVIEW(connector->dev))  {
8171                 struct intel_encoder *intel_encoder;
8172                 struct intel_digital_port *intel_dig_port;
8173
8174                 intel_encoder = intel_attached_encoder(connector);
8175                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8176                 i = intel_dig_port->port;
8177         } else {
8178                 i = I915_READ(aud_cntl_st);
8179                 i = (i >> 29) & DIP_PORT_SEL_MASK;
8180                 /* DIP_Port_Select, 0x1 = PortB */
8181         }
8182
8183         if (!i) {
8184                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8185                 /* operate blindly on all ports */
8186                 eldv = IBX_ELD_VALIDB;
8187                 eldv |= IBX_ELD_VALIDB << 4;
8188                 eldv |= IBX_ELD_VALIDB << 8;
8189         } else {
8190                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8191                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8192         }
8193
8194         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8195                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8196                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8197                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8198         } else {
8199                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8200         }
8201
8202         if (intel_eld_uptodate(connector,
8203                                aud_cntrl_st2, eldv,
8204                                aud_cntl_st, IBX_ELD_ADDRESS,
8205                                hdmiw_hdmiedid))
8206                 return;
8207
8208         i = I915_READ(aud_cntrl_st2);
8209         i &= ~eldv;
8210         I915_WRITE(aud_cntrl_st2, i);
8211
8212         if (!eld[0])
8213                 return;
8214
8215         i = I915_READ(aud_cntl_st);
8216         i &= ~IBX_ELD_ADDRESS;
8217         I915_WRITE(aud_cntl_st, i);
8218
8219         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8220         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8221         for (i = 0; i < len; i++)
8222                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8223
8224         i = I915_READ(aud_cntrl_st2);
8225         i |= eldv;
8226         I915_WRITE(aud_cntrl_st2, i);
8227 }
8228
8229 void intel_write_eld(struct drm_encoder *encoder,
8230                      struct drm_display_mode *mode)
8231 {
8232         struct drm_crtc *crtc = encoder->crtc;
8233         struct drm_connector *connector;
8234         struct drm_device *dev = encoder->dev;
8235         struct drm_i915_private *dev_priv = dev->dev_private;
8236
8237         connector = drm_select_eld(encoder, mode);
8238         if (!connector)
8239                 return;
8240
8241         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8242                          connector->base.id,
8243                          connector->name,
8244                          connector->encoder->base.id,
8245                          connector->encoder->name);
8246
8247         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8248
8249         if (dev_priv->display.write_eld)
8250                 dev_priv->display.write_eld(connector, crtc, mode);
8251 }
8252
8253 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8254 {
8255         struct drm_device *dev = crtc->dev;
8256         struct drm_i915_private *dev_priv = dev->dev_private;
8257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8258         uint32_t cntl = 0, size = 0;
8259
8260         if (base) {
8261                 unsigned int width = intel_crtc->cursor_width;
8262                 unsigned int height = intel_crtc->cursor_height;
8263                 unsigned int stride = roundup_pow_of_two(width) * 4;
8264
8265                 switch (stride) {
8266                 default:
8267                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8268                                   width, stride);
8269                         stride = 256;
8270                         /* fallthrough */
8271                 case 256:
8272                 case 512:
8273                 case 1024:
8274                 case 2048:
8275                         break;
8276                 }
8277
8278                 cntl |= CURSOR_ENABLE |
8279                         CURSOR_GAMMA_ENABLE |
8280                         CURSOR_FORMAT_ARGB |
8281                         CURSOR_STRIDE(stride);
8282
8283                 size = (height << 12) | width;
8284         }
8285
8286         if (intel_crtc->cursor_cntl != 0 &&
8287             (intel_crtc->cursor_base != base ||
8288              intel_crtc->cursor_size != size ||
8289              intel_crtc->cursor_cntl != cntl)) {
8290                 /* On these chipsets we can only modify the base/size/stride
8291                  * whilst the cursor is disabled.
8292                  */
8293                 I915_WRITE(_CURACNTR, 0);
8294                 POSTING_READ(_CURACNTR);
8295                 intel_crtc->cursor_cntl = 0;
8296         }
8297
8298         if (intel_crtc->cursor_base != base) {
8299                 I915_WRITE(_CURABASE, base);
8300                 intel_crtc->cursor_base = base;
8301         }
8302
8303         if (intel_crtc->cursor_size != size) {
8304                 I915_WRITE(CURSIZE, size);
8305                 intel_crtc->cursor_size = size;
8306         }
8307
8308         if (intel_crtc->cursor_cntl != cntl) {
8309                 I915_WRITE(_CURACNTR, cntl);
8310                 POSTING_READ(_CURACNTR);
8311                 intel_crtc->cursor_cntl = cntl;
8312         }
8313 }
8314
8315 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8316 {
8317         struct drm_device *dev = crtc->dev;
8318         struct drm_i915_private *dev_priv = dev->dev_private;
8319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8320         int pipe = intel_crtc->pipe;
8321         uint32_t cntl;
8322
8323         cntl = 0;
8324         if (base) {
8325                 cntl = MCURSOR_GAMMA_ENABLE;
8326                 switch (intel_crtc->cursor_width) {
8327                         case 64:
8328                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8329                                 break;
8330                         case 128:
8331                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8332                                 break;
8333                         case 256:
8334                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8335                                 break;
8336                         default:
8337                                 WARN_ON(1);
8338                                 return;
8339                 }
8340                 cntl |= pipe << 28; /* Connect to correct pipe */
8341
8342                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8343                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8344         }
8345
8346         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8347                 cntl |= CURSOR_ROTATE_180;
8348
8349         if (intel_crtc->cursor_cntl != cntl) {
8350                 I915_WRITE(CURCNTR(pipe), cntl);
8351                 POSTING_READ(CURCNTR(pipe));
8352                 intel_crtc->cursor_cntl = cntl;
8353         }
8354
8355         /* and commit changes on next vblank */
8356         I915_WRITE(CURBASE(pipe), base);
8357         POSTING_READ(CURBASE(pipe));
8358
8359         intel_crtc->cursor_base = base;
8360 }
8361
8362 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8363 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8364                                      bool on)
8365 {
8366         struct drm_device *dev = crtc->dev;
8367         struct drm_i915_private *dev_priv = dev->dev_private;
8368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8369         int pipe = intel_crtc->pipe;
8370         int x = crtc->cursor_x;
8371         int y = crtc->cursor_y;
8372         u32 base = 0, pos = 0;
8373
8374         if (on)
8375                 base = intel_crtc->cursor_addr;
8376
8377         if (x >= intel_crtc->config.pipe_src_w)
8378                 base = 0;
8379
8380         if (y >= intel_crtc->config.pipe_src_h)
8381                 base = 0;
8382
8383         if (x < 0) {
8384                 if (x + intel_crtc->cursor_width <= 0)
8385                         base = 0;
8386
8387                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8388                 x = -x;
8389         }
8390         pos |= x << CURSOR_X_SHIFT;
8391
8392         if (y < 0) {
8393                 if (y + intel_crtc->cursor_height <= 0)
8394                         base = 0;
8395
8396                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8397                 y = -y;
8398         }
8399         pos |= y << CURSOR_Y_SHIFT;
8400
8401         if (base == 0 && intel_crtc->cursor_base == 0)
8402                 return;
8403
8404         I915_WRITE(CURPOS(pipe), pos);
8405
8406         /* ILK+ do this automagically */
8407         if (HAS_GMCH_DISPLAY(dev) &&
8408                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8409                 base += (intel_crtc->cursor_height *
8410                         intel_crtc->cursor_width - 1) * 4;
8411         }
8412
8413         if (IS_845G(dev) || IS_I865G(dev))
8414                 i845_update_cursor(crtc, base);
8415         else
8416                 i9xx_update_cursor(crtc, base);
8417 }
8418
8419 static bool cursor_size_ok(struct drm_device *dev,
8420                            uint32_t width, uint32_t height)
8421 {
8422         if (width == 0 || height == 0)
8423                 return false;
8424
8425         /*
8426          * 845g/865g are special in that they are only limited by
8427          * the width of their cursors, the height is arbitrary up to
8428          * the precision of the register. Everything else requires
8429          * square cursors, limited to a few power-of-two sizes.
8430          */
8431         if (IS_845G(dev) || IS_I865G(dev)) {
8432                 if ((width & 63) != 0)
8433                         return false;
8434
8435                 if (width > (IS_845G(dev) ? 64 : 512))
8436                         return false;
8437
8438                 if (height > 1023)
8439                         return false;
8440         } else {
8441                 switch (width | height) {
8442                 case 256:
8443                 case 128:
8444                         if (IS_GEN2(dev))
8445                                 return false;
8446                 case 64:
8447                         break;
8448                 default:
8449                         return false;
8450                 }
8451         }
8452
8453         return true;
8454 }
8455
8456 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8457                                      struct drm_i915_gem_object *obj,
8458                                      uint32_t width, uint32_t height)
8459 {
8460         struct drm_device *dev = crtc->dev;
8461         struct drm_i915_private *dev_priv = dev->dev_private;
8462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8463         enum pipe pipe = intel_crtc->pipe;
8464         unsigned old_width;
8465         uint32_t addr;
8466         int ret;
8467
8468         /* if we want to turn off the cursor ignore width and height */
8469         if (!obj) {
8470                 DRM_DEBUG_KMS("cursor off\n");
8471                 addr = 0;
8472                 mutex_lock(&dev->struct_mutex);
8473                 goto finish;
8474         }
8475
8476         /* we only need to pin inside GTT if cursor is non-phy */
8477         mutex_lock(&dev->struct_mutex);
8478         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8479                 unsigned alignment;
8480
8481                 /*
8482                  * Global gtt pte registers are special registers which actually
8483                  * forward writes to a chunk of system memory. Which means that
8484                  * there is no risk that the register values disappear as soon
8485                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8486                  * only the pin/unpin/fence and not more.
8487                  */
8488                 intel_runtime_pm_get(dev_priv);
8489
8490                 /* Note that the w/a also requires 2 PTE of padding following
8491                  * the bo. We currently fill all unused PTE with the shadow
8492                  * page and so we should always have valid PTE following the
8493                  * cursor preventing the VT-d warning.
8494                  */
8495                 alignment = 0;
8496                 if (need_vtd_wa(dev))
8497                         alignment = 64*1024;
8498
8499                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8500                 if (ret) {
8501                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8502                         intel_runtime_pm_put(dev_priv);
8503                         goto fail_locked;
8504                 }
8505
8506                 ret = i915_gem_object_put_fence(obj);
8507                 if (ret) {
8508                         DRM_DEBUG_KMS("failed to release fence for cursor");
8509                         intel_runtime_pm_put(dev_priv);
8510                         goto fail_unpin;
8511                 }
8512
8513                 addr = i915_gem_obj_ggtt_offset(obj);
8514
8515                 intel_runtime_pm_put(dev_priv);
8516         } else {
8517                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8518                 ret = i915_gem_object_attach_phys(obj, align);
8519                 if (ret) {
8520                         DRM_DEBUG_KMS("failed to attach phys object\n");
8521                         goto fail_locked;
8522                 }
8523                 addr = obj->phys_handle->busaddr;
8524         }
8525
8526  finish:
8527         if (intel_crtc->cursor_bo) {
8528                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8529                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8530         }
8531
8532         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8533                           INTEL_FRONTBUFFER_CURSOR(pipe));
8534         mutex_unlock(&dev->struct_mutex);
8535
8536         old_width = intel_crtc->cursor_width;
8537
8538         intel_crtc->cursor_addr = addr;
8539         intel_crtc->cursor_bo = obj;
8540         intel_crtc->cursor_width = width;
8541         intel_crtc->cursor_height = height;
8542
8543         if (intel_crtc->active) {
8544                 if (old_width != width)
8545                         intel_update_watermarks(crtc);
8546                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8547         }
8548
8549         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8550
8551         return 0;
8552 fail_unpin:
8553         i915_gem_object_unpin_from_display_plane(obj);
8554 fail_locked:
8555         mutex_unlock(&dev->struct_mutex);
8556         return ret;
8557 }
8558
8559 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8560                                  u16 *blue, uint32_t start, uint32_t size)
8561 {
8562         int end = (start + size > 256) ? 256 : start + size, i;
8563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8564
8565         for (i = start; i < end; i++) {
8566                 intel_crtc->lut_r[i] = red[i] >> 8;
8567                 intel_crtc->lut_g[i] = green[i] >> 8;
8568                 intel_crtc->lut_b[i] = blue[i] >> 8;
8569         }
8570
8571         intel_crtc_load_lut(crtc);
8572 }
8573
8574 /* VESA 640x480x72Hz mode to set on the pipe */
8575 static struct drm_display_mode load_detect_mode = {
8576         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8577                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8578 };
8579
8580 struct drm_framebuffer *
8581 __intel_framebuffer_create(struct drm_device *dev,
8582                            struct drm_mode_fb_cmd2 *mode_cmd,
8583                            struct drm_i915_gem_object *obj)
8584 {
8585         struct intel_framebuffer *intel_fb;
8586         int ret;
8587
8588         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8589         if (!intel_fb) {
8590                 drm_gem_object_unreference_unlocked(&obj->base);
8591                 return ERR_PTR(-ENOMEM);
8592         }
8593
8594         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8595         if (ret)
8596                 goto err;
8597
8598         return &intel_fb->base;
8599 err:
8600         drm_gem_object_unreference_unlocked(&obj->base);
8601         kfree(intel_fb);
8602
8603         return ERR_PTR(ret);
8604 }
8605
8606 static struct drm_framebuffer *
8607 intel_framebuffer_create(struct drm_device *dev,
8608                          struct drm_mode_fb_cmd2 *mode_cmd,
8609                          struct drm_i915_gem_object *obj)
8610 {
8611         struct drm_framebuffer *fb;
8612         int ret;
8613
8614         ret = i915_mutex_lock_interruptible(dev);
8615         if (ret)
8616                 return ERR_PTR(ret);
8617         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8618         mutex_unlock(&dev->struct_mutex);
8619
8620         return fb;
8621 }
8622
8623 static u32
8624 intel_framebuffer_pitch_for_width(int width, int bpp)
8625 {
8626         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8627         return ALIGN(pitch, 64);
8628 }
8629
8630 static u32
8631 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8632 {
8633         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8634         return PAGE_ALIGN(pitch * mode->vdisplay);
8635 }
8636
8637 static struct drm_framebuffer *
8638 intel_framebuffer_create_for_mode(struct drm_device *dev,
8639                                   struct drm_display_mode *mode,
8640                                   int depth, int bpp)
8641 {
8642         struct drm_i915_gem_object *obj;
8643         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8644
8645         obj = i915_gem_alloc_object(dev,
8646                                     intel_framebuffer_size_for_mode(mode, bpp));
8647         if (obj == NULL)
8648                 return ERR_PTR(-ENOMEM);
8649
8650         mode_cmd.width = mode->hdisplay;
8651         mode_cmd.height = mode->vdisplay;
8652         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8653                                                                 bpp);
8654         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8655
8656         return intel_framebuffer_create(dev, &mode_cmd, obj);
8657 }
8658
8659 static struct drm_framebuffer *
8660 mode_fits_in_fbdev(struct drm_device *dev,
8661                    struct drm_display_mode *mode)
8662 {
8663 #ifdef CONFIG_DRM_I915_FBDEV
8664         struct drm_i915_private *dev_priv = dev->dev_private;
8665         struct drm_i915_gem_object *obj;
8666         struct drm_framebuffer *fb;
8667
8668         if (!dev_priv->fbdev)
8669                 return NULL;
8670
8671         if (!dev_priv->fbdev->fb)
8672                 return NULL;
8673
8674         obj = dev_priv->fbdev->fb->obj;
8675         BUG_ON(!obj);
8676
8677         fb = &dev_priv->fbdev->fb->base;
8678         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8679                                                                fb->bits_per_pixel))
8680                 return NULL;
8681
8682         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8683                 return NULL;
8684
8685         return fb;
8686 #else
8687         return NULL;
8688 #endif
8689 }
8690
8691 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8692                                 struct drm_display_mode *mode,
8693                                 struct intel_load_detect_pipe *old,
8694                                 struct drm_modeset_acquire_ctx *ctx)
8695 {
8696         struct intel_crtc *intel_crtc;
8697         struct intel_encoder *intel_encoder =
8698                 intel_attached_encoder(connector);
8699         struct drm_crtc *possible_crtc;
8700         struct drm_encoder *encoder = &intel_encoder->base;
8701         struct drm_crtc *crtc = NULL;
8702         struct drm_device *dev = encoder->dev;
8703         struct drm_framebuffer *fb;
8704         struct drm_mode_config *config = &dev->mode_config;
8705         int ret, i = -1;
8706
8707         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8708                       connector->base.id, connector->name,
8709                       encoder->base.id, encoder->name);
8710
8711 retry:
8712         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8713         if (ret)
8714                 goto fail_unlock;
8715
8716         /*
8717          * Algorithm gets a little messy:
8718          *
8719          *   - if the connector already has an assigned crtc, use it (but make
8720          *     sure it's on first)
8721          *
8722          *   - try to find the first unused crtc that can drive this connector,
8723          *     and use that if we find one
8724          */
8725
8726         /* See if we already have a CRTC for this connector */
8727         if (encoder->crtc) {
8728                 crtc = encoder->crtc;
8729
8730                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8731                 if (ret)
8732                         goto fail_unlock;
8733
8734                 old->dpms_mode = connector->dpms;
8735                 old->load_detect_temp = false;
8736
8737                 /* Make sure the crtc and connector are running */
8738                 if (connector->dpms != DRM_MODE_DPMS_ON)
8739                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8740
8741                 return true;
8742         }
8743
8744         /* Find an unused one (if possible) */
8745         for_each_crtc(dev, possible_crtc) {
8746                 i++;
8747                 if (!(encoder->possible_crtcs & (1 << i)))
8748                         continue;
8749                 if (possible_crtc->enabled)
8750                         continue;
8751                 /* This can occur when applying the pipe A quirk on resume. */
8752                 if (to_intel_crtc(possible_crtc)->new_enabled)
8753                         continue;
8754
8755                 crtc = possible_crtc;
8756                 break;
8757         }
8758
8759         /*
8760          * If we didn't find an unused CRTC, don't use any.
8761          */
8762         if (!crtc) {
8763                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8764                 goto fail_unlock;
8765         }
8766
8767         ret = drm_modeset_lock(&crtc->mutex, ctx);
8768         if (ret)
8769                 goto fail_unlock;
8770         intel_encoder->new_crtc = to_intel_crtc(crtc);
8771         to_intel_connector(connector)->new_encoder = intel_encoder;
8772
8773         intel_crtc = to_intel_crtc(crtc);
8774         intel_crtc->new_enabled = true;
8775         intel_crtc->new_config = &intel_crtc->config;
8776         old->dpms_mode = connector->dpms;
8777         old->load_detect_temp = true;
8778         old->release_fb = NULL;
8779
8780         if (!mode)
8781                 mode = &load_detect_mode;
8782
8783         /* We need a framebuffer large enough to accommodate all accesses
8784          * that the plane may generate whilst we perform load detection.
8785          * We can not rely on the fbcon either being present (we get called
8786          * during its initialisation to detect all boot displays, or it may
8787          * not even exist) or that it is large enough to satisfy the
8788          * requested mode.
8789          */
8790         fb = mode_fits_in_fbdev(dev, mode);
8791         if (fb == NULL) {
8792                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8793                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8794                 old->release_fb = fb;
8795         } else
8796                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8797         if (IS_ERR(fb)) {
8798                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8799                 goto fail;
8800         }
8801
8802         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8803                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8804                 if (old->release_fb)
8805                         old->release_fb->funcs->destroy(old->release_fb);
8806                 goto fail;
8807         }
8808
8809         /* let the connector get through one full cycle before testing */
8810         intel_wait_for_vblank(dev, intel_crtc->pipe);
8811         return true;
8812
8813  fail:
8814         intel_crtc->new_enabled = crtc->enabled;
8815         if (intel_crtc->new_enabled)
8816                 intel_crtc->new_config = &intel_crtc->config;
8817         else
8818                 intel_crtc->new_config = NULL;
8819 fail_unlock:
8820         if (ret == -EDEADLK) {
8821                 drm_modeset_backoff(ctx);
8822                 goto retry;
8823         }
8824
8825         return false;
8826 }
8827
8828 void intel_release_load_detect_pipe(struct drm_connector *connector,
8829                                     struct intel_load_detect_pipe *old)
8830 {
8831         struct intel_encoder *intel_encoder =
8832                 intel_attached_encoder(connector);
8833         struct drm_encoder *encoder = &intel_encoder->base;
8834         struct drm_crtc *crtc = encoder->crtc;
8835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8836
8837         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8838                       connector->base.id, connector->name,
8839                       encoder->base.id, encoder->name);
8840
8841         if (old->load_detect_temp) {
8842                 to_intel_connector(connector)->new_encoder = NULL;
8843                 intel_encoder->new_crtc = NULL;
8844                 intel_crtc->new_enabled = false;
8845                 intel_crtc->new_config = NULL;
8846                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8847
8848                 if (old->release_fb) {
8849                         drm_framebuffer_unregister_private(old->release_fb);
8850                         drm_framebuffer_unreference(old->release_fb);
8851                 }
8852
8853                 return;
8854         }
8855
8856         /* Switch crtc and encoder back off if necessary */
8857         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8858                 connector->funcs->dpms(connector, old->dpms_mode);
8859 }
8860
8861 static int i9xx_pll_refclk(struct drm_device *dev,
8862                            const struct intel_crtc_config *pipe_config)
8863 {
8864         struct drm_i915_private *dev_priv = dev->dev_private;
8865         u32 dpll = pipe_config->dpll_hw_state.dpll;
8866
8867         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8868                 return dev_priv->vbt.lvds_ssc_freq;
8869         else if (HAS_PCH_SPLIT(dev))
8870                 return 120000;
8871         else if (!IS_GEN2(dev))
8872                 return 96000;
8873         else
8874                 return 48000;
8875 }
8876
8877 /* Returns the clock of the currently programmed mode of the given pipe. */
8878 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8879                                 struct intel_crtc_config *pipe_config)
8880 {
8881         struct drm_device *dev = crtc->base.dev;
8882         struct drm_i915_private *dev_priv = dev->dev_private;
8883         int pipe = pipe_config->cpu_transcoder;
8884         u32 dpll = pipe_config->dpll_hw_state.dpll;
8885         u32 fp;
8886         intel_clock_t clock;
8887         int refclk = i9xx_pll_refclk(dev, pipe_config);
8888
8889         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8890                 fp = pipe_config->dpll_hw_state.fp0;
8891         else
8892                 fp = pipe_config->dpll_hw_state.fp1;
8893
8894         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8895         if (IS_PINEVIEW(dev)) {
8896                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8897                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8898         } else {
8899                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8900                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8901         }
8902
8903         if (!IS_GEN2(dev)) {
8904                 if (IS_PINEVIEW(dev))
8905                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8906                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8907                 else
8908                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8909                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8910
8911                 switch (dpll & DPLL_MODE_MASK) {
8912                 case DPLLB_MODE_DAC_SERIAL:
8913                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8914                                 5 : 10;
8915                         break;
8916                 case DPLLB_MODE_LVDS:
8917                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8918                                 7 : 14;
8919                         break;
8920                 default:
8921                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8922                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8923                         return;
8924                 }
8925
8926                 if (IS_PINEVIEW(dev))
8927                         pineview_clock(refclk, &clock);
8928                 else
8929                         i9xx_clock(refclk, &clock);
8930         } else {
8931                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8932                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8933
8934                 if (is_lvds) {
8935                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8936                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8937
8938                         if (lvds & LVDS_CLKB_POWER_UP)
8939                                 clock.p2 = 7;
8940                         else
8941                                 clock.p2 = 14;
8942                 } else {
8943                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8944                                 clock.p1 = 2;
8945                         else {
8946                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8947                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8948                         }
8949                         if (dpll & PLL_P2_DIVIDE_BY_4)
8950                                 clock.p2 = 4;
8951                         else
8952                                 clock.p2 = 2;
8953                 }
8954
8955                 i9xx_clock(refclk, &clock);
8956         }
8957
8958         /*
8959          * This value includes pixel_multiplier. We will use
8960          * port_clock to compute adjusted_mode.crtc_clock in the
8961          * encoder's get_config() function.
8962          */
8963         pipe_config->port_clock = clock.dot;
8964 }
8965
8966 int intel_dotclock_calculate(int link_freq,
8967                              const struct intel_link_m_n *m_n)
8968 {
8969         /*
8970          * The calculation for the data clock is:
8971          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8972          * But we want to avoid losing precison if possible, so:
8973          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8974          *
8975          * and the link clock is simpler:
8976          * link_clock = (m * link_clock) / n
8977          */
8978
8979         if (!m_n->link_n)
8980                 return 0;
8981
8982         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8983 }
8984
8985 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8986                                    struct intel_crtc_config *pipe_config)
8987 {
8988         struct drm_device *dev = crtc->base.dev;
8989
8990         /* read out port_clock from the DPLL */
8991         i9xx_crtc_clock_get(crtc, pipe_config);
8992
8993         /*
8994          * This value does not include pixel_multiplier.
8995          * We will check that port_clock and adjusted_mode.crtc_clock
8996          * agree once we know their relationship in the encoder's
8997          * get_config() function.
8998          */
8999         pipe_config->adjusted_mode.crtc_clock =
9000                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9001                                          &pipe_config->fdi_m_n);
9002 }
9003
9004 /** Returns the currently programmed mode of the given pipe. */
9005 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9006                                              struct drm_crtc *crtc)
9007 {
9008         struct drm_i915_private *dev_priv = dev->dev_private;
9009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9010         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
9011         struct drm_display_mode *mode;
9012         struct intel_crtc_config pipe_config;
9013         int htot = I915_READ(HTOTAL(cpu_transcoder));
9014         int hsync = I915_READ(HSYNC(cpu_transcoder));
9015         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9016         int vsync = I915_READ(VSYNC(cpu_transcoder));
9017         enum pipe pipe = intel_crtc->pipe;
9018
9019         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9020         if (!mode)
9021                 return NULL;
9022
9023         /*
9024          * Construct a pipe_config sufficient for getting the clock info
9025          * back out of crtc_clock_get.
9026          *
9027          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9028          * to use a real value here instead.
9029          */
9030         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9031         pipe_config.pixel_multiplier = 1;
9032         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9033         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9034         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9035         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9036
9037         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9038         mode->hdisplay = (htot & 0xffff) + 1;
9039         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9040         mode->hsync_start = (hsync & 0xffff) + 1;
9041         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9042         mode->vdisplay = (vtot & 0xffff) + 1;
9043         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9044         mode->vsync_start = (vsync & 0xffff) + 1;
9045         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9046
9047         drm_mode_set_name(mode);
9048
9049         return mode;
9050 }
9051
9052 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9053 {
9054         struct drm_device *dev = crtc->dev;
9055         struct drm_i915_private *dev_priv = dev->dev_private;
9056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9057
9058         if (!HAS_GMCH_DISPLAY(dev))
9059                 return;
9060
9061         if (!dev_priv->lvds_downclock_avail)
9062                 return;
9063
9064         /*
9065          * Since this is called by a timer, we should never get here in
9066          * the manual case.
9067          */
9068         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9069                 int pipe = intel_crtc->pipe;
9070                 int dpll_reg = DPLL(pipe);
9071                 int dpll;
9072
9073                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9074
9075                 assert_panel_unlocked(dev_priv, pipe);
9076
9077                 dpll = I915_READ(dpll_reg);
9078                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9079                 I915_WRITE(dpll_reg, dpll);
9080                 intel_wait_for_vblank(dev, pipe);
9081                 dpll = I915_READ(dpll_reg);
9082                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9083                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9084         }
9085
9086 }
9087
9088 void intel_mark_busy(struct drm_device *dev)
9089 {
9090         struct drm_i915_private *dev_priv = dev->dev_private;
9091
9092         if (dev_priv->mm.busy)
9093                 return;
9094
9095         intel_runtime_pm_get(dev_priv);
9096         i915_update_gfx_val(dev_priv);
9097         dev_priv->mm.busy = true;
9098 }
9099
9100 void intel_mark_idle(struct drm_device *dev)
9101 {
9102         struct drm_i915_private *dev_priv = dev->dev_private;
9103         struct drm_crtc *crtc;
9104
9105         if (!dev_priv->mm.busy)
9106                 return;
9107
9108         dev_priv->mm.busy = false;
9109
9110         if (!i915.powersave)
9111                 goto out;
9112
9113         for_each_crtc(dev, crtc) {
9114                 if (!crtc->primary->fb)
9115                         continue;
9116
9117                 intel_decrease_pllclock(crtc);
9118         }
9119
9120         if (INTEL_INFO(dev)->gen >= 6)
9121                 gen6_rps_idle(dev->dev_private);
9122
9123 out:
9124         intel_runtime_pm_put(dev_priv);
9125 }
9126
9127 static void intel_crtc_destroy(struct drm_crtc *crtc)
9128 {
9129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9130         struct drm_device *dev = crtc->dev;
9131         struct intel_unpin_work *work;
9132
9133         spin_lock_irq(&dev->event_lock);
9134         work = intel_crtc->unpin_work;
9135         intel_crtc->unpin_work = NULL;
9136         spin_unlock_irq(&dev->event_lock);
9137
9138         if (work) {
9139                 cancel_work_sync(&work->work);
9140                 kfree(work);
9141         }
9142
9143         drm_crtc_cleanup(crtc);
9144
9145         kfree(intel_crtc);
9146 }
9147
9148 static void intel_unpin_work_fn(struct work_struct *__work)
9149 {
9150         struct intel_unpin_work *work =
9151                 container_of(__work, struct intel_unpin_work, work);
9152         struct drm_device *dev = work->crtc->dev;
9153         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9154
9155         mutex_lock(&dev->struct_mutex);
9156         intel_unpin_fb_obj(work->old_fb_obj);
9157         drm_gem_object_unreference(&work->pending_flip_obj->base);
9158         drm_gem_object_unreference(&work->old_fb_obj->base);
9159
9160         intel_update_fbc(dev);
9161         mutex_unlock(&dev->struct_mutex);
9162
9163         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9164
9165         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9166         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9167
9168         kfree(work);
9169 }
9170
9171 static void do_intel_finish_page_flip(struct drm_device *dev,
9172                                       struct drm_crtc *crtc)
9173 {
9174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9175         struct intel_unpin_work *work;
9176         unsigned long flags;
9177
9178         /* Ignore early vblank irqs */
9179         if (intel_crtc == NULL)
9180                 return;
9181
9182         /*
9183          * This is called both by irq handlers and the reset code (to complete
9184          * lost pageflips) so needs the full irqsave spinlocks.
9185          */
9186         spin_lock_irqsave(&dev->event_lock, flags);
9187         work = intel_crtc->unpin_work;
9188
9189         /* Ensure we don't miss a work->pending update ... */
9190         smp_rmb();
9191
9192         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9193                 spin_unlock_irqrestore(&dev->event_lock, flags);
9194                 return;
9195         }
9196
9197         page_flip_completed(intel_crtc);
9198
9199         spin_unlock_irqrestore(&dev->event_lock, flags);
9200 }
9201
9202 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9203 {
9204         struct drm_i915_private *dev_priv = dev->dev_private;
9205         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9206
9207         do_intel_finish_page_flip(dev, crtc);
9208 }
9209
9210 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9211 {
9212         struct drm_i915_private *dev_priv = dev->dev_private;
9213         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9214
9215         do_intel_finish_page_flip(dev, crtc);
9216 }
9217
9218 /* Is 'a' after or equal to 'b'? */
9219 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9220 {
9221         return !((a - b) & 0x80000000);
9222 }
9223
9224 static bool page_flip_finished(struct intel_crtc *crtc)
9225 {
9226         struct drm_device *dev = crtc->base.dev;
9227         struct drm_i915_private *dev_priv = dev->dev_private;
9228
9229         /*
9230          * The relevant registers doen't exist on pre-ctg.
9231          * As the flip done interrupt doesn't trigger for mmio
9232          * flips on gmch platforms, a flip count check isn't
9233          * really needed there. But since ctg has the registers,
9234          * include it in the check anyway.
9235          */
9236         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9237                 return true;
9238
9239         /*
9240          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9241          * used the same base address. In that case the mmio flip might
9242          * have completed, but the CS hasn't even executed the flip yet.
9243          *
9244          * A flip count check isn't enough as the CS might have updated
9245          * the base address just after start of vblank, but before we
9246          * managed to process the interrupt. This means we'd complete the
9247          * CS flip too soon.
9248          *
9249          * Combining both checks should get us a good enough result. It may
9250          * still happen that the CS flip has been executed, but has not
9251          * yet actually completed. But in case the base address is the same
9252          * anyway, we don't really care.
9253          */
9254         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9255                 crtc->unpin_work->gtt_offset &&
9256                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9257                                     crtc->unpin_work->flip_count);
9258 }
9259
9260 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9261 {
9262         struct drm_i915_private *dev_priv = dev->dev_private;
9263         struct intel_crtc *intel_crtc =
9264                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9265         unsigned long flags;
9266
9267
9268         /*
9269          * This is called both by irq handlers and the reset code (to complete
9270          * lost pageflips) so needs the full irqsave spinlocks.
9271          *
9272          * NB: An MMIO update of the plane base pointer will also
9273          * generate a page-flip completion irq, i.e. every modeset
9274          * is also accompanied by a spurious intel_prepare_page_flip().
9275          */
9276         spin_lock_irqsave(&dev->event_lock, flags);
9277         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9278                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9279         spin_unlock_irqrestore(&dev->event_lock, flags);
9280 }
9281
9282 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9283 {
9284         /* Ensure that the work item is consistent when activating it ... */
9285         smp_wmb();
9286         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9287         /* and that it is marked active as soon as the irq could fire. */
9288         smp_wmb();
9289 }
9290
9291 static int intel_gen2_queue_flip(struct drm_device *dev,
9292                                  struct drm_crtc *crtc,
9293                                  struct drm_framebuffer *fb,
9294                                  struct drm_i915_gem_object *obj,
9295                                  struct intel_engine_cs *ring,
9296                                  uint32_t flags)
9297 {
9298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9299         u32 flip_mask;
9300         int ret;
9301
9302         ret = intel_ring_begin(ring, 6);
9303         if (ret)
9304                 return ret;
9305
9306         /* Can't queue multiple flips, so wait for the previous
9307          * one to finish before executing the next.
9308          */
9309         if (intel_crtc->plane)
9310                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9311         else
9312                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9313         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9314         intel_ring_emit(ring, MI_NOOP);
9315         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9316                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9317         intel_ring_emit(ring, fb->pitches[0]);
9318         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9319         intel_ring_emit(ring, 0); /* aux display base address, unused */
9320
9321         intel_mark_page_flip_active(intel_crtc);
9322         __intel_ring_advance(ring);
9323         return 0;
9324 }
9325
9326 static int intel_gen3_queue_flip(struct drm_device *dev,
9327                                  struct drm_crtc *crtc,
9328                                  struct drm_framebuffer *fb,
9329                                  struct drm_i915_gem_object *obj,
9330                                  struct intel_engine_cs *ring,
9331                                  uint32_t flags)
9332 {
9333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9334         u32 flip_mask;
9335         int ret;
9336
9337         ret = intel_ring_begin(ring, 6);
9338         if (ret)
9339                 return ret;
9340
9341         if (intel_crtc->plane)
9342                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9343         else
9344                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9345         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9346         intel_ring_emit(ring, MI_NOOP);
9347         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9348                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9349         intel_ring_emit(ring, fb->pitches[0]);
9350         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9351         intel_ring_emit(ring, MI_NOOP);
9352
9353         intel_mark_page_flip_active(intel_crtc);
9354         __intel_ring_advance(ring);
9355         return 0;
9356 }
9357
9358 static int intel_gen4_queue_flip(struct drm_device *dev,
9359                                  struct drm_crtc *crtc,
9360                                  struct drm_framebuffer *fb,
9361                                  struct drm_i915_gem_object *obj,
9362                                  struct intel_engine_cs *ring,
9363                                  uint32_t flags)
9364 {
9365         struct drm_i915_private *dev_priv = dev->dev_private;
9366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9367         uint32_t pf, pipesrc;
9368         int ret;
9369
9370         ret = intel_ring_begin(ring, 4);
9371         if (ret)
9372                 return ret;
9373
9374         /* i965+ uses the linear or tiled offsets from the
9375          * Display Registers (which do not change across a page-flip)
9376          * so we need only reprogram the base address.
9377          */
9378         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9379                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9380         intel_ring_emit(ring, fb->pitches[0]);
9381         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9382                         obj->tiling_mode);
9383
9384         /* XXX Enabling the panel-fitter across page-flip is so far
9385          * untested on non-native modes, so ignore it for now.
9386          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9387          */
9388         pf = 0;
9389         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9390         intel_ring_emit(ring, pf | pipesrc);
9391
9392         intel_mark_page_flip_active(intel_crtc);
9393         __intel_ring_advance(ring);
9394         return 0;
9395 }
9396
9397 static int intel_gen6_queue_flip(struct drm_device *dev,
9398                                  struct drm_crtc *crtc,
9399                                  struct drm_framebuffer *fb,
9400                                  struct drm_i915_gem_object *obj,
9401                                  struct intel_engine_cs *ring,
9402                                  uint32_t flags)
9403 {
9404         struct drm_i915_private *dev_priv = dev->dev_private;
9405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9406         uint32_t pf, pipesrc;
9407         int ret;
9408
9409         ret = intel_ring_begin(ring, 4);
9410         if (ret)
9411                 return ret;
9412
9413         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9414                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9415         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9416         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9417
9418         /* Contrary to the suggestions in the documentation,
9419          * "Enable Panel Fitter" does not seem to be required when page
9420          * flipping with a non-native mode, and worse causes a normal
9421          * modeset to fail.
9422          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9423          */
9424         pf = 0;
9425         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9426         intel_ring_emit(ring, pf | pipesrc);
9427
9428         intel_mark_page_flip_active(intel_crtc);
9429         __intel_ring_advance(ring);
9430         return 0;
9431 }
9432
9433 static int intel_gen7_queue_flip(struct drm_device *dev,
9434                                  struct drm_crtc *crtc,
9435                                  struct drm_framebuffer *fb,
9436                                  struct drm_i915_gem_object *obj,
9437                                  struct intel_engine_cs *ring,
9438                                  uint32_t flags)
9439 {
9440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9441         uint32_t plane_bit = 0;
9442         int len, ret;
9443
9444         switch (intel_crtc->plane) {
9445         case PLANE_A:
9446                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9447                 break;
9448         case PLANE_B:
9449                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9450                 break;
9451         case PLANE_C:
9452                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9453                 break;
9454         default:
9455                 WARN_ONCE(1, "unknown plane in flip command\n");
9456                 return -ENODEV;
9457         }
9458
9459         len = 4;
9460         if (ring->id == RCS) {
9461                 len += 6;
9462                 /*
9463                  * On Gen 8, SRM is now taking an extra dword to accommodate
9464                  * 48bits addresses, and we need a NOOP for the batch size to
9465                  * stay even.
9466                  */
9467                 if (IS_GEN8(dev))
9468                         len += 2;
9469         }
9470
9471         /*
9472          * BSpec MI_DISPLAY_FLIP for IVB:
9473          * "The full packet must be contained within the same cache line."
9474          *
9475          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9476          * cacheline, if we ever start emitting more commands before
9477          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9478          * then do the cacheline alignment, and finally emit the
9479          * MI_DISPLAY_FLIP.
9480          */
9481         ret = intel_ring_cacheline_align(ring);
9482         if (ret)
9483                 return ret;
9484
9485         ret = intel_ring_begin(ring, len);
9486         if (ret)
9487                 return ret;
9488
9489         /* Unmask the flip-done completion message. Note that the bspec says that
9490          * we should do this for both the BCS and RCS, and that we must not unmask
9491          * more than one flip event at any time (or ensure that one flip message
9492          * can be sent by waiting for flip-done prior to queueing new flips).
9493          * Experimentation says that BCS works despite DERRMR masking all
9494          * flip-done completion events and that unmasking all planes at once
9495          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9496          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9497          */
9498         if (ring->id == RCS) {
9499                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9500                 intel_ring_emit(ring, DERRMR);
9501                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9502                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9503                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9504                 if (IS_GEN8(dev))
9505                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9506                                               MI_SRM_LRM_GLOBAL_GTT);
9507                 else
9508                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9509                                               MI_SRM_LRM_GLOBAL_GTT);
9510                 intel_ring_emit(ring, DERRMR);
9511                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9512                 if (IS_GEN8(dev)) {
9513                         intel_ring_emit(ring, 0);
9514                         intel_ring_emit(ring, MI_NOOP);
9515                 }
9516         }
9517
9518         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9519         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9520         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9521         intel_ring_emit(ring, (MI_NOOP));
9522
9523         intel_mark_page_flip_active(intel_crtc);
9524         __intel_ring_advance(ring);
9525         return 0;
9526 }
9527
9528 static bool use_mmio_flip(struct intel_engine_cs *ring,
9529                           struct drm_i915_gem_object *obj)
9530 {
9531         /*
9532          * This is not being used for older platforms, because
9533          * non-availability of flip done interrupt forces us to use
9534          * CS flips. Older platforms derive flip done using some clever
9535          * tricks involving the flip_pending status bits and vblank irqs.
9536          * So using MMIO flips there would disrupt this mechanism.
9537          */
9538
9539         if (ring == NULL)
9540                 return true;
9541
9542         if (INTEL_INFO(ring->dev)->gen < 5)
9543                 return false;
9544
9545         if (i915.use_mmio_flip < 0)
9546                 return false;
9547         else if (i915.use_mmio_flip > 0)
9548                 return true;
9549         else if (i915.enable_execlists)
9550                 return true;
9551         else
9552                 return ring != obj->ring;
9553 }
9554
9555 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9556 {
9557         struct drm_device *dev = intel_crtc->base.dev;
9558         struct drm_i915_private *dev_priv = dev->dev_private;
9559         struct intel_framebuffer *intel_fb =
9560                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9561         struct drm_i915_gem_object *obj = intel_fb->obj;
9562         u32 dspcntr;
9563         u32 reg;
9564
9565         intel_mark_page_flip_active(intel_crtc);
9566
9567         reg = DSPCNTR(intel_crtc->plane);
9568         dspcntr = I915_READ(reg);
9569
9570         if (INTEL_INFO(dev)->gen >= 4) {
9571                 if (obj->tiling_mode != I915_TILING_NONE)
9572                         dspcntr |= DISPPLANE_TILED;
9573                 else
9574                         dspcntr &= ~DISPPLANE_TILED;
9575         }
9576         I915_WRITE(reg, dspcntr);
9577
9578         I915_WRITE(DSPSURF(intel_crtc->plane),
9579                    intel_crtc->unpin_work->gtt_offset);
9580         POSTING_READ(DSPSURF(intel_crtc->plane));
9581 }
9582
9583 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9584 {
9585         struct intel_engine_cs *ring;
9586         int ret;
9587
9588         lockdep_assert_held(&obj->base.dev->struct_mutex);
9589
9590         if (!obj->last_write_seqno)
9591                 return 0;
9592
9593         ring = obj->ring;
9594
9595         if (i915_seqno_passed(ring->get_seqno(ring, true),
9596                               obj->last_write_seqno))
9597                 return 0;
9598
9599         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9600         if (ret)
9601                 return ret;
9602
9603         if (WARN_ON(!ring->irq_get(ring)))
9604                 return 0;
9605
9606         return 1;
9607 }
9608
9609 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9610 {
9611         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9612         struct intel_crtc *intel_crtc;
9613         unsigned long irq_flags;
9614         u32 seqno;
9615
9616         seqno = ring->get_seqno(ring, false);
9617
9618         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9619         for_each_intel_crtc(ring->dev, intel_crtc) {
9620                 struct intel_mmio_flip *mmio_flip;
9621
9622                 mmio_flip = &intel_crtc->mmio_flip;
9623                 if (mmio_flip->seqno == 0)
9624                         continue;
9625
9626                 if (ring->id != mmio_flip->ring_id)
9627                         continue;
9628
9629                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9630                         intel_do_mmio_flip(intel_crtc);
9631                         mmio_flip->seqno = 0;
9632                         ring->irq_put(ring);
9633                 }
9634         }
9635         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9636 }
9637
9638 static int intel_queue_mmio_flip(struct drm_device *dev,
9639                                  struct drm_crtc *crtc,
9640                                  struct drm_framebuffer *fb,
9641                                  struct drm_i915_gem_object *obj,
9642                                  struct intel_engine_cs *ring,
9643                                  uint32_t flags)
9644 {
9645         struct drm_i915_private *dev_priv = dev->dev_private;
9646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9647         int ret;
9648
9649         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9650                 return -EBUSY;
9651
9652         ret = intel_postpone_flip(obj);
9653         if (ret < 0)
9654                 return ret;
9655         if (ret == 0) {
9656                 intel_do_mmio_flip(intel_crtc);
9657                 return 0;
9658         }
9659
9660         spin_lock_irq(&dev_priv->mmio_flip_lock);
9661         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9662         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9663         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9664
9665         /*
9666          * Double check to catch cases where irq fired before
9667          * mmio flip data was ready
9668          */
9669         intel_notify_mmio_flip(obj->ring);
9670         return 0;
9671 }
9672
9673 static int intel_default_queue_flip(struct drm_device *dev,
9674                                     struct drm_crtc *crtc,
9675                                     struct drm_framebuffer *fb,
9676                                     struct drm_i915_gem_object *obj,
9677                                     struct intel_engine_cs *ring,
9678                                     uint32_t flags)
9679 {
9680         return -ENODEV;
9681 }
9682
9683 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9684                                          struct drm_crtc *crtc)
9685 {
9686         struct drm_i915_private *dev_priv = dev->dev_private;
9687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9688         struct intel_unpin_work *work = intel_crtc->unpin_work;
9689         u32 addr;
9690
9691         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9692                 return true;
9693
9694         if (!work->enable_stall_check)
9695                 return false;
9696
9697         if (work->flip_ready_vblank == 0) {
9698                 if (work->flip_queued_ring &&
9699                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9700                                        work->flip_queued_seqno))
9701                         return false;
9702
9703                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9704         }
9705
9706         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9707                 return false;
9708
9709         /* Potential stall - if we see that the flip has happened,
9710          * assume a missed interrupt. */
9711         if (INTEL_INFO(dev)->gen >= 4)
9712                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9713         else
9714                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9715
9716         /* There is a potential issue here with a false positive after a flip
9717          * to the same address. We could address this by checking for a
9718          * non-incrementing frame counter.
9719          */
9720         return addr == work->gtt_offset;
9721 }
9722
9723 void intel_check_page_flip(struct drm_device *dev, int pipe)
9724 {
9725         struct drm_i915_private *dev_priv = dev->dev_private;
9726         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9728
9729         WARN_ON(!in_irq());
9730
9731         if (crtc == NULL)
9732                 return;
9733
9734         spin_lock(&dev->event_lock);
9735         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9736                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9737                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9738                 page_flip_completed(intel_crtc);
9739         }
9740         spin_unlock(&dev->event_lock);
9741 }
9742
9743 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9744                                 struct drm_framebuffer *fb,
9745                                 struct drm_pending_vblank_event *event,
9746                                 uint32_t page_flip_flags)
9747 {
9748         struct drm_device *dev = crtc->dev;
9749         struct drm_i915_private *dev_priv = dev->dev_private;
9750         struct drm_framebuffer *old_fb = crtc->primary->fb;
9751         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9753         enum pipe pipe = intel_crtc->pipe;
9754         struct intel_unpin_work *work;
9755         struct intel_engine_cs *ring;
9756         int ret;
9757
9758         /*
9759          * drm_mode_page_flip_ioctl() should already catch this, but double
9760          * check to be safe.  In the future we may enable pageflipping from
9761          * a disabled primary plane.
9762          */
9763         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9764                 return -EBUSY;
9765
9766         /* Can't change pixel format via MI display flips. */
9767         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9768                 return -EINVAL;
9769
9770         /*
9771          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9772          * Note that pitch changes could also affect these register.
9773          */
9774         if (INTEL_INFO(dev)->gen > 3 &&
9775             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9776              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9777                 return -EINVAL;
9778
9779         if (i915_terminally_wedged(&dev_priv->gpu_error))
9780                 goto out_hang;
9781
9782         work = kzalloc(sizeof(*work), GFP_KERNEL);
9783         if (work == NULL)
9784                 return -ENOMEM;
9785
9786         work->event = event;
9787         work->crtc = crtc;
9788         work->old_fb_obj = intel_fb_obj(old_fb);
9789         INIT_WORK(&work->work, intel_unpin_work_fn);
9790
9791         ret = drm_crtc_vblank_get(crtc);
9792         if (ret)
9793                 goto free_work;
9794
9795         /* We borrow the event spin lock for protecting unpin_work */
9796         spin_lock_irq(&dev->event_lock);
9797         if (intel_crtc->unpin_work) {
9798                 /* Before declaring the flip queue wedged, check if
9799                  * the hardware completed the operation behind our backs.
9800                  */
9801                 if (__intel_pageflip_stall_check(dev, crtc)) {
9802                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9803                         page_flip_completed(intel_crtc);
9804                 } else {
9805                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9806                         spin_unlock_irq(&dev->event_lock);
9807
9808                         drm_crtc_vblank_put(crtc);
9809                         kfree(work);
9810                         return -EBUSY;
9811                 }
9812         }
9813         intel_crtc->unpin_work = work;
9814         spin_unlock_irq(&dev->event_lock);
9815
9816         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9817                 flush_workqueue(dev_priv->wq);
9818
9819         ret = i915_mutex_lock_interruptible(dev);
9820         if (ret)
9821                 goto cleanup;
9822
9823         /* Reference the objects for the scheduled work. */
9824         drm_gem_object_reference(&work->old_fb_obj->base);
9825         drm_gem_object_reference(&obj->base);
9826
9827         crtc->primary->fb = fb;
9828
9829         work->pending_flip_obj = obj;
9830
9831         atomic_inc(&intel_crtc->unpin_work_count);
9832         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9833
9834         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9835                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9836
9837         if (IS_VALLEYVIEW(dev)) {
9838                 ring = &dev_priv->ring[BCS];
9839                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9840                         /* vlv: DISPLAY_FLIP fails to change tiling */
9841                         ring = NULL;
9842         } else if (IS_IVYBRIDGE(dev)) {
9843                 ring = &dev_priv->ring[BCS];
9844         } else if (INTEL_INFO(dev)->gen >= 7) {
9845                 ring = obj->ring;
9846                 if (ring == NULL || ring->id != RCS)
9847                         ring = &dev_priv->ring[BCS];
9848         } else {
9849                 ring = &dev_priv->ring[RCS];
9850         }
9851
9852         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9853         if (ret)
9854                 goto cleanup_pending;
9855
9856         work->gtt_offset =
9857                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9858
9859         if (use_mmio_flip(ring, obj)) {
9860                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9861                                             page_flip_flags);
9862                 if (ret)
9863                         goto cleanup_unpin;
9864
9865                 work->flip_queued_seqno = obj->last_write_seqno;
9866                 work->flip_queued_ring = obj->ring;
9867         } else {
9868                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9869                                                    page_flip_flags);
9870                 if (ret)
9871                         goto cleanup_unpin;
9872
9873                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9874                 work->flip_queued_ring = ring;
9875         }
9876
9877         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9878         work->enable_stall_check = true;
9879
9880         i915_gem_track_fb(work->old_fb_obj, obj,
9881                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9882
9883         intel_disable_fbc(dev);
9884         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9885         mutex_unlock(&dev->struct_mutex);
9886
9887         trace_i915_flip_request(intel_crtc->plane, obj);
9888
9889         return 0;
9890
9891 cleanup_unpin:
9892         intel_unpin_fb_obj(obj);
9893 cleanup_pending:
9894         atomic_dec(&intel_crtc->unpin_work_count);
9895         crtc->primary->fb = old_fb;
9896         drm_gem_object_unreference(&work->old_fb_obj->base);
9897         drm_gem_object_unreference(&obj->base);
9898         mutex_unlock(&dev->struct_mutex);
9899
9900 cleanup:
9901         spin_lock_irq(&dev->event_lock);
9902         intel_crtc->unpin_work = NULL;
9903         spin_unlock_irq(&dev->event_lock);
9904
9905         drm_crtc_vblank_put(crtc);
9906 free_work:
9907         kfree(work);
9908
9909         if (ret == -EIO) {
9910 out_hang:
9911                 intel_crtc_wait_for_pending_flips(crtc);
9912                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9913                 if (ret == 0 && event) {
9914                         spin_lock_irq(&dev->event_lock);
9915                         drm_send_vblank_event(dev, pipe, event);
9916                         spin_unlock_irq(&dev->event_lock);
9917                 }
9918         }
9919         return ret;
9920 }
9921
9922 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9923         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9924         .load_lut = intel_crtc_load_lut,
9925 };
9926
9927 /**
9928  * intel_modeset_update_staged_output_state
9929  *
9930  * Updates the staged output configuration state, e.g. after we've read out the
9931  * current hw state.
9932  */
9933 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9934 {
9935         struct intel_crtc *crtc;
9936         struct intel_encoder *encoder;
9937         struct intel_connector *connector;
9938
9939         list_for_each_entry(connector, &dev->mode_config.connector_list,
9940                             base.head) {
9941                 connector->new_encoder =
9942                         to_intel_encoder(connector->base.encoder);
9943         }
9944
9945         for_each_intel_encoder(dev, encoder) {
9946                 encoder->new_crtc =
9947                         to_intel_crtc(encoder->base.crtc);
9948         }
9949
9950         for_each_intel_crtc(dev, crtc) {
9951                 crtc->new_enabled = crtc->base.enabled;
9952
9953                 if (crtc->new_enabled)
9954                         crtc->new_config = &crtc->config;
9955                 else
9956                         crtc->new_config = NULL;
9957         }
9958 }
9959
9960 /**
9961  * intel_modeset_commit_output_state
9962  *
9963  * This function copies the stage display pipe configuration to the real one.
9964  */
9965 static void intel_modeset_commit_output_state(struct drm_device *dev)
9966 {
9967         struct intel_crtc *crtc;
9968         struct intel_encoder *encoder;
9969         struct intel_connector *connector;
9970
9971         list_for_each_entry(connector, &dev->mode_config.connector_list,
9972                             base.head) {
9973                 connector->base.encoder = &connector->new_encoder->base;
9974         }
9975
9976         for_each_intel_encoder(dev, encoder) {
9977                 encoder->base.crtc = &encoder->new_crtc->base;
9978         }
9979
9980         for_each_intel_crtc(dev, crtc) {
9981                 crtc->base.enabled = crtc->new_enabled;
9982         }
9983 }
9984
9985 static void
9986 connected_sink_compute_bpp(struct intel_connector *connector,
9987                            struct intel_crtc_config *pipe_config)
9988 {
9989         int bpp = pipe_config->pipe_bpp;
9990
9991         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9992                 connector->base.base.id,
9993                 connector->base.name);
9994
9995         /* Don't use an invalid EDID bpc value */
9996         if (connector->base.display_info.bpc &&
9997             connector->base.display_info.bpc * 3 < bpp) {
9998                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9999                               bpp, connector->base.display_info.bpc*3);
10000                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10001         }
10002
10003         /* Clamp bpp to 8 on screens without EDID 1.4 */
10004         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10005                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10006                               bpp);
10007                 pipe_config->pipe_bpp = 24;
10008         }
10009 }
10010
10011 static int
10012 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10013                           struct drm_framebuffer *fb,
10014                           struct intel_crtc_config *pipe_config)
10015 {
10016         struct drm_device *dev = crtc->base.dev;
10017         struct intel_connector *connector;
10018         int bpp;
10019
10020         switch (fb->pixel_format) {
10021         case DRM_FORMAT_C8:
10022                 bpp = 8*3; /* since we go through a colormap */
10023                 break;
10024         case DRM_FORMAT_XRGB1555:
10025         case DRM_FORMAT_ARGB1555:
10026                 /* checked in intel_framebuffer_init already */
10027                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10028                         return -EINVAL;
10029         case DRM_FORMAT_RGB565:
10030                 bpp = 6*3; /* min is 18bpp */
10031                 break;
10032         case DRM_FORMAT_XBGR8888:
10033         case DRM_FORMAT_ABGR8888:
10034                 /* checked in intel_framebuffer_init already */
10035                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10036                         return -EINVAL;
10037         case DRM_FORMAT_XRGB8888:
10038         case DRM_FORMAT_ARGB8888:
10039                 bpp = 8*3;
10040                 break;
10041         case DRM_FORMAT_XRGB2101010:
10042         case DRM_FORMAT_ARGB2101010:
10043         case DRM_FORMAT_XBGR2101010:
10044         case DRM_FORMAT_ABGR2101010:
10045                 /* checked in intel_framebuffer_init already */
10046                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10047                         return -EINVAL;
10048                 bpp = 10*3;
10049                 break;
10050         /* TODO: gen4+ supports 16 bpc floating point, too. */
10051         default:
10052                 DRM_DEBUG_KMS("unsupported depth\n");
10053                 return -EINVAL;
10054         }
10055
10056         pipe_config->pipe_bpp = bpp;
10057
10058         /* Clamp display bpp to EDID value */
10059         list_for_each_entry(connector, &dev->mode_config.connector_list,
10060                             base.head) {
10061                 if (!connector->new_encoder ||
10062                     connector->new_encoder->new_crtc != crtc)
10063                         continue;
10064
10065                 connected_sink_compute_bpp(connector, pipe_config);
10066         }
10067
10068         return bpp;
10069 }
10070
10071 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10072 {
10073         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10074                         "type: 0x%x flags: 0x%x\n",
10075                 mode->crtc_clock,
10076                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10077                 mode->crtc_hsync_end, mode->crtc_htotal,
10078                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10079                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10080 }
10081
10082 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10083                                    struct intel_crtc_config *pipe_config,
10084                                    const char *context)
10085 {
10086         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10087                       context, pipe_name(crtc->pipe));
10088
10089         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10090         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10091                       pipe_config->pipe_bpp, pipe_config->dither);
10092         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10093                       pipe_config->has_pch_encoder,
10094                       pipe_config->fdi_lanes,
10095                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10096                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10097                       pipe_config->fdi_m_n.tu);
10098         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10099                       pipe_config->has_dp_encoder,
10100                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10101                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10102                       pipe_config->dp_m_n.tu);
10103
10104         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10105                       pipe_config->has_dp_encoder,
10106                       pipe_config->dp_m2_n2.gmch_m,
10107                       pipe_config->dp_m2_n2.gmch_n,
10108                       pipe_config->dp_m2_n2.link_m,
10109                       pipe_config->dp_m2_n2.link_n,
10110                       pipe_config->dp_m2_n2.tu);
10111
10112         DRM_DEBUG_KMS("requested mode:\n");
10113         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10114         DRM_DEBUG_KMS("adjusted mode:\n");
10115         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10116         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10117         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10118         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10119                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10120         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10121                       pipe_config->gmch_pfit.control,
10122                       pipe_config->gmch_pfit.pgm_ratios,
10123                       pipe_config->gmch_pfit.lvds_border_bits);
10124         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10125                       pipe_config->pch_pfit.pos,
10126                       pipe_config->pch_pfit.size,
10127                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10128         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10129         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10130 }
10131
10132 static bool encoders_cloneable(const struct intel_encoder *a,
10133                                const struct intel_encoder *b)
10134 {
10135         /* masks could be asymmetric, so check both ways */
10136         return a == b || (a->cloneable & (1 << b->type) &&
10137                           b->cloneable & (1 << a->type));
10138 }
10139
10140 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10141                                          struct intel_encoder *encoder)
10142 {
10143         struct drm_device *dev = crtc->base.dev;
10144         struct intel_encoder *source_encoder;
10145
10146         for_each_intel_encoder(dev, source_encoder) {
10147                 if (source_encoder->new_crtc != crtc)
10148                         continue;
10149
10150                 if (!encoders_cloneable(encoder, source_encoder))
10151                         return false;
10152         }
10153
10154         return true;
10155 }
10156
10157 static bool check_encoder_cloning(struct intel_crtc *crtc)
10158 {
10159         struct drm_device *dev = crtc->base.dev;
10160         struct intel_encoder *encoder;
10161
10162         for_each_intel_encoder(dev, encoder) {
10163                 if (encoder->new_crtc != crtc)
10164                         continue;
10165
10166                 if (!check_single_encoder_cloning(crtc, encoder))
10167                         return false;
10168         }
10169
10170         return true;
10171 }
10172
10173 static struct intel_crtc_config *
10174 intel_modeset_pipe_config(struct drm_crtc *crtc,
10175                           struct drm_framebuffer *fb,
10176                           struct drm_display_mode *mode)
10177 {
10178         struct drm_device *dev = crtc->dev;
10179         struct intel_encoder *encoder;
10180         struct intel_crtc_config *pipe_config;
10181         int plane_bpp, ret = -EINVAL;
10182         bool retry = true;
10183
10184         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10185                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10186                 return ERR_PTR(-EINVAL);
10187         }
10188
10189         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10190         if (!pipe_config)
10191                 return ERR_PTR(-ENOMEM);
10192
10193         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10194         drm_mode_copy(&pipe_config->requested_mode, mode);
10195
10196         pipe_config->cpu_transcoder =
10197                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10198         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10199
10200         /*
10201          * Sanitize sync polarity flags based on requested ones. If neither
10202          * positive or negative polarity is requested, treat this as meaning
10203          * negative polarity.
10204          */
10205         if (!(pipe_config->adjusted_mode.flags &
10206               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10207                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10208
10209         if (!(pipe_config->adjusted_mode.flags &
10210               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10211                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10212
10213         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10214          * plane pixel format and any sink constraints into account. Returns the
10215          * source plane bpp so that dithering can be selected on mismatches
10216          * after encoders and crtc also have had their say. */
10217         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10218                                               fb, pipe_config);
10219         if (plane_bpp < 0)
10220                 goto fail;
10221
10222         /*
10223          * Determine the real pipe dimensions. Note that stereo modes can
10224          * increase the actual pipe size due to the frame doubling and
10225          * insertion of additional space for blanks between the frame. This
10226          * is stored in the crtc timings. We use the requested mode to do this
10227          * computation to clearly distinguish it from the adjusted mode, which
10228          * can be changed by the connectors in the below retry loop.
10229          */
10230         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10231         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10232         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10233
10234 encoder_retry:
10235         /* Ensure the port clock defaults are reset when retrying. */
10236         pipe_config->port_clock = 0;
10237         pipe_config->pixel_multiplier = 1;
10238
10239         /* Fill in default crtc timings, allow encoders to overwrite them. */
10240         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10241
10242         /* Pass our mode to the connectors and the CRTC to give them a chance to
10243          * adjust it according to limitations or connector properties, and also
10244          * a chance to reject the mode entirely.
10245          */
10246         for_each_intel_encoder(dev, encoder) {
10247
10248                 if (&encoder->new_crtc->base != crtc)
10249                         continue;
10250
10251                 if (!(encoder->compute_config(encoder, pipe_config))) {
10252                         DRM_DEBUG_KMS("Encoder config failure\n");
10253                         goto fail;
10254                 }
10255         }
10256
10257         /* Set default port clock if not overwritten by the encoder. Needs to be
10258          * done afterwards in case the encoder adjusts the mode. */
10259         if (!pipe_config->port_clock)
10260                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10261                         * pipe_config->pixel_multiplier;
10262
10263         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10264         if (ret < 0) {
10265                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10266                 goto fail;
10267         }
10268
10269         if (ret == RETRY) {
10270                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10271                         ret = -EINVAL;
10272                         goto fail;
10273                 }
10274
10275                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10276                 retry = false;
10277                 goto encoder_retry;
10278         }
10279
10280         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10281         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10282                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10283
10284         return pipe_config;
10285 fail:
10286         kfree(pipe_config);
10287         return ERR_PTR(ret);
10288 }
10289
10290 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10291  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10292 static void
10293 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10294                              unsigned *prepare_pipes, unsigned *disable_pipes)
10295 {
10296         struct intel_crtc *intel_crtc;
10297         struct drm_device *dev = crtc->dev;
10298         struct intel_encoder *encoder;
10299         struct intel_connector *connector;
10300         struct drm_crtc *tmp_crtc;
10301
10302         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10303
10304         /* Check which crtcs have changed outputs connected to them, these need
10305          * to be part of the prepare_pipes mask. We don't (yet) support global
10306          * modeset across multiple crtcs, so modeset_pipes will only have one
10307          * bit set at most. */
10308         list_for_each_entry(connector, &dev->mode_config.connector_list,
10309                             base.head) {
10310                 if (connector->base.encoder == &connector->new_encoder->base)
10311                         continue;
10312
10313                 if (connector->base.encoder) {
10314                         tmp_crtc = connector->base.encoder->crtc;
10315
10316                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10317                 }
10318
10319                 if (connector->new_encoder)
10320                         *prepare_pipes |=
10321                                 1 << connector->new_encoder->new_crtc->pipe;
10322         }
10323
10324         for_each_intel_encoder(dev, encoder) {
10325                 if (encoder->base.crtc == &encoder->new_crtc->base)
10326                         continue;
10327
10328                 if (encoder->base.crtc) {
10329                         tmp_crtc = encoder->base.crtc;
10330
10331                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10332                 }
10333
10334                 if (encoder->new_crtc)
10335                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10336         }
10337
10338         /* Check for pipes that will be enabled/disabled ... */
10339         for_each_intel_crtc(dev, intel_crtc) {
10340                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10341                         continue;
10342
10343                 if (!intel_crtc->new_enabled)
10344                         *disable_pipes |= 1 << intel_crtc->pipe;
10345                 else
10346                         *prepare_pipes |= 1 << intel_crtc->pipe;
10347         }
10348
10349
10350         /* set_mode is also used to update properties on life display pipes. */
10351         intel_crtc = to_intel_crtc(crtc);
10352         if (intel_crtc->new_enabled)
10353                 *prepare_pipes |= 1 << intel_crtc->pipe;
10354
10355         /*
10356          * For simplicity do a full modeset on any pipe where the output routing
10357          * changed. We could be more clever, but that would require us to be
10358          * more careful with calling the relevant encoder->mode_set functions.
10359          */
10360         if (*prepare_pipes)
10361                 *modeset_pipes = *prepare_pipes;
10362
10363         /* ... and mask these out. */
10364         *modeset_pipes &= ~(*disable_pipes);
10365         *prepare_pipes &= ~(*disable_pipes);
10366
10367         /*
10368          * HACK: We don't (yet) fully support global modesets. intel_set_config
10369          * obies this rule, but the modeset restore mode of
10370          * intel_modeset_setup_hw_state does not.
10371          */
10372         *modeset_pipes &= 1 << intel_crtc->pipe;
10373         *prepare_pipes &= 1 << intel_crtc->pipe;
10374
10375         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10376                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10377 }
10378
10379 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10380 {
10381         struct drm_encoder *encoder;
10382         struct drm_device *dev = crtc->dev;
10383
10384         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10385                 if (encoder->crtc == crtc)
10386                         return true;
10387
10388         return false;
10389 }
10390
10391 static void
10392 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10393 {
10394         struct intel_encoder *intel_encoder;
10395         struct intel_crtc *intel_crtc;
10396         struct drm_connector *connector;
10397
10398         for_each_intel_encoder(dev, intel_encoder) {
10399                 if (!intel_encoder->base.crtc)
10400                         continue;
10401
10402                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10403
10404                 if (prepare_pipes & (1 << intel_crtc->pipe))
10405                         intel_encoder->connectors_active = false;
10406         }
10407
10408         intel_modeset_commit_output_state(dev);
10409
10410         /* Double check state. */
10411         for_each_intel_crtc(dev, intel_crtc) {
10412                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10413                 WARN_ON(intel_crtc->new_config &&
10414                         intel_crtc->new_config != &intel_crtc->config);
10415                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10416         }
10417
10418         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10419                 if (!connector->encoder || !connector->encoder->crtc)
10420                         continue;
10421
10422                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10423
10424                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10425                         struct drm_property *dpms_property =
10426                                 dev->mode_config.dpms_property;
10427
10428                         connector->dpms = DRM_MODE_DPMS_ON;
10429                         drm_object_property_set_value(&connector->base,
10430                                                          dpms_property,
10431                                                          DRM_MODE_DPMS_ON);
10432
10433                         intel_encoder = to_intel_encoder(connector->encoder);
10434                         intel_encoder->connectors_active = true;
10435                 }
10436         }
10437
10438 }
10439
10440 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10441 {
10442         int diff;
10443
10444         if (clock1 == clock2)
10445                 return true;
10446
10447         if (!clock1 || !clock2)
10448                 return false;
10449
10450         diff = abs(clock1 - clock2);
10451
10452         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10453                 return true;
10454
10455         return false;
10456 }
10457
10458 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10459         list_for_each_entry((intel_crtc), \
10460                             &(dev)->mode_config.crtc_list, \
10461                             base.head) \
10462                 if (mask & (1 <<(intel_crtc)->pipe))
10463
10464 static bool
10465 intel_pipe_config_compare(struct drm_device *dev,
10466                           struct intel_crtc_config *current_config,
10467                           struct intel_crtc_config *pipe_config)
10468 {
10469 #define PIPE_CONF_CHECK_X(name) \
10470         if (current_config->name != pipe_config->name) { \
10471                 DRM_ERROR("mismatch in " #name " " \
10472                           "(expected 0x%08x, found 0x%08x)\n", \
10473                           current_config->name, \
10474                           pipe_config->name); \
10475                 return false; \
10476         }
10477
10478 #define PIPE_CONF_CHECK_I(name) \
10479         if (current_config->name != pipe_config->name) { \
10480                 DRM_ERROR("mismatch in " #name " " \
10481                           "(expected %i, found %i)\n", \
10482                           current_config->name, \
10483                           pipe_config->name); \
10484                 return false; \
10485         }
10486
10487 /* This is required for BDW+ where there is only one set of registers for
10488  * switching between high and low RR.
10489  * This macro can be used whenever a comparison has to be made between one
10490  * hw state and multiple sw state variables.
10491  */
10492 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10493         if ((current_config->name != pipe_config->name) && \
10494                 (current_config->alt_name != pipe_config->name)) { \
10495                         DRM_ERROR("mismatch in " #name " " \
10496                                   "(expected %i or %i, found %i)\n", \
10497                                   current_config->name, \
10498                                   current_config->alt_name, \
10499                                   pipe_config->name); \
10500                         return false; \
10501         }
10502
10503 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10504         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10505                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10506                           "(expected %i, found %i)\n", \
10507                           current_config->name & (mask), \
10508                           pipe_config->name & (mask)); \
10509                 return false; \
10510         }
10511
10512 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10513         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10514                 DRM_ERROR("mismatch in " #name " " \
10515                           "(expected %i, found %i)\n", \
10516                           current_config->name, \
10517                           pipe_config->name); \
10518                 return false; \
10519         }
10520
10521 #define PIPE_CONF_QUIRK(quirk)  \
10522         ((current_config->quirks | pipe_config->quirks) & (quirk))
10523
10524         PIPE_CONF_CHECK_I(cpu_transcoder);
10525
10526         PIPE_CONF_CHECK_I(has_pch_encoder);
10527         PIPE_CONF_CHECK_I(fdi_lanes);
10528         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10529         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10530         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10531         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10532         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10533
10534         PIPE_CONF_CHECK_I(has_dp_encoder);
10535
10536         if (INTEL_INFO(dev)->gen < 8) {
10537                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10538                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10539                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10540                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10541                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10542
10543                 if (current_config->has_drrs) {
10544                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10545                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10546                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10547                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10548                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10549                 }
10550         } else {
10551                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10552                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10553                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10554                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10555                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10556         }
10557
10558         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10559         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10560         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10561         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10562         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10563         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10564
10565         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10566         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10567         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10568         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10569         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10570         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10571
10572         PIPE_CONF_CHECK_I(pixel_multiplier);
10573         PIPE_CONF_CHECK_I(has_hdmi_sink);
10574         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10575             IS_VALLEYVIEW(dev))
10576                 PIPE_CONF_CHECK_I(limited_color_range);
10577
10578         PIPE_CONF_CHECK_I(has_audio);
10579
10580         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10581                               DRM_MODE_FLAG_INTERLACE);
10582
10583         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10584                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10585                                       DRM_MODE_FLAG_PHSYNC);
10586                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10587                                       DRM_MODE_FLAG_NHSYNC);
10588                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10589                                       DRM_MODE_FLAG_PVSYNC);
10590                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10591                                       DRM_MODE_FLAG_NVSYNC);
10592         }
10593
10594         PIPE_CONF_CHECK_I(pipe_src_w);
10595         PIPE_CONF_CHECK_I(pipe_src_h);
10596
10597         /*
10598          * FIXME: BIOS likes to set up a cloned config with lvds+external
10599          * screen. Since we don't yet re-compute the pipe config when moving
10600          * just the lvds port away to another pipe the sw tracking won't match.
10601          *
10602          * Proper atomic modesets with recomputed global state will fix this.
10603          * Until then just don't check gmch state for inherited modes.
10604          */
10605         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10606                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10607                 /* pfit ratios are autocomputed by the hw on gen4+ */
10608                 if (INTEL_INFO(dev)->gen < 4)
10609                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10610                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10611         }
10612
10613         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10614         if (current_config->pch_pfit.enabled) {
10615                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10616                 PIPE_CONF_CHECK_I(pch_pfit.size);
10617         }
10618
10619         /* BDW+ don't expose a synchronous way to read the state */
10620         if (IS_HASWELL(dev))
10621                 PIPE_CONF_CHECK_I(ips_enabled);
10622
10623         PIPE_CONF_CHECK_I(double_wide);
10624
10625         PIPE_CONF_CHECK_X(ddi_pll_sel);
10626
10627         PIPE_CONF_CHECK_I(shared_dpll);
10628         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10629         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10630         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10631         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10632         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10633
10634         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10635                 PIPE_CONF_CHECK_I(pipe_bpp);
10636
10637         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10638         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10639
10640 #undef PIPE_CONF_CHECK_X
10641 #undef PIPE_CONF_CHECK_I
10642 #undef PIPE_CONF_CHECK_I_ALT
10643 #undef PIPE_CONF_CHECK_FLAGS
10644 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10645 #undef PIPE_CONF_QUIRK
10646
10647         return true;
10648 }
10649
10650 static void
10651 check_connector_state(struct drm_device *dev)
10652 {
10653         struct intel_connector *connector;
10654
10655         list_for_each_entry(connector, &dev->mode_config.connector_list,
10656                             base.head) {
10657                 /* This also checks the encoder/connector hw state with the
10658                  * ->get_hw_state callbacks. */
10659                 intel_connector_check_state(connector);
10660
10661                 WARN(&connector->new_encoder->base != connector->base.encoder,
10662                      "connector's staged encoder doesn't match current encoder\n");
10663         }
10664 }
10665
10666 static void
10667 check_encoder_state(struct drm_device *dev)
10668 {
10669         struct intel_encoder *encoder;
10670         struct intel_connector *connector;
10671
10672         for_each_intel_encoder(dev, encoder) {
10673                 bool enabled = false;
10674                 bool active = false;
10675                 enum pipe pipe, tracked_pipe;
10676
10677                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10678                               encoder->base.base.id,
10679                               encoder->base.name);
10680
10681                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10682                      "encoder's stage crtc doesn't match current crtc\n");
10683                 WARN(encoder->connectors_active && !encoder->base.crtc,
10684                      "encoder's active_connectors set, but no crtc\n");
10685
10686                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10687                                     base.head) {
10688                         if (connector->base.encoder != &encoder->base)
10689                                 continue;
10690                         enabled = true;
10691                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10692                                 active = true;
10693                 }
10694                 /*
10695                  * for MST connectors if we unplug the connector is gone
10696                  * away but the encoder is still connected to a crtc
10697                  * until a modeset happens in response to the hotplug.
10698                  */
10699                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10700                         continue;
10701
10702                 WARN(!!encoder->base.crtc != enabled,
10703                      "encoder's enabled state mismatch "
10704                      "(expected %i, found %i)\n",
10705                      !!encoder->base.crtc, enabled);
10706                 WARN(active && !encoder->base.crtc,
10707                      "active encoder with no crtc\n");
10708
10709                 WARN(encoder->connectors_active != active,
10710                      "encoder's computed active state doesn't match tracked active state "
10711                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10712
10713                 active = encoder->get_hw_state(encoder, &pipe);
10714                 WARN(active != encoder->connectors_active,
10715                      "encoder's hw state doesn't match sw tracking "
10716                      "(expected %i, found %i)\n",
10717                      encoder->connectors_active, active);
10718
10719                 if (!encoder->base.crtc)
10720                         continue;
10721
10722                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10723                 WARN(active && pipe != tracked_pipe,
10724                      "active encoder's pipe doesn't match"
10725                      "(expected %i, found %i)\n",
10726                      tracked_pipe, pipe);
10727
10728         }
10729 }
10730
10731 static void
10732 check_crtc_state(struct drm_device *dev)
10733 {
10734         struct drm_i915_private *dev_priv = dev->dev_private;
10735         struct intel_crtc *crtc;
10736         struct intel_encoder *encoder;
10737         struct intel_crtc_config pipe_config;
10738
10739         for_each_intel_crtc(dev, crtc) {
10740                 bool enabled = false;
10741                 bool active = false;
10742
10743                 memset(&pipe_config, 0, sizeof(pipe_config));
10744
10745                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10746                               crtc->base.base.id);
10747
10748                 WARN(crtc->active && !crtc->base.enabled,
10749                      "active crtc, but not enabled in sw tracking\n");
10750
10751                 for_each_intel_encoder(dev, encoder) {
10752                         if (encoder->base.crtc != &crtc->base)
10753                                 continue;
10754                         enabled = true;
10755                         if (encoder->connectors_active)
10756                                 active = true;
10757                 }
10758
10759                 WARN(active != crtc->active,
10760                      "crtc's computed active state doesn't match tracked active state "
10761                      "(expected %i, found %i)\n", active, crtc->active);
10762                 WARN(enabled != crtc->base.enabled,
10763                      "crtc's computed enabled state doesn't match tracked enabled state "
10764                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10765
10766                 active = dev_priv->display.get_pipe_config(crtc,
10767                                                            &pipe_config);
10768
10769                 /* hw state is inconsistent with the pipe quirk */
10770                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10771                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10772                         active = crtc->active;
10773
10774                 for_each_intel_encoder(dev, encoder) {
10775                         enum pipe pipe;
10776                         if (encoder->base.crtc != &crtc->base)
10777                                 continue;
10778                         if (encoder->get_hw_state(encoder, &pipe))
10779                                 encoder->get_config(encoder, &pipe_config);
10780                 }
10781
10782                 WARN(crtc->active != active,
10783                      "crtc active state doesn't match with hw state "
10784                      "(expected %i, found %i)\n", crtc->active, active);
10785
10786                 if (active &&
10787                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10788                         WARN(1, "pipe state doesn't match!\n");
10789                         intel_dump_pipe_config(crtc, &pipe_config,
10790                                                "[hw state]");
10791                         intel_dump_pipe_config(crtc, &crtc->config,
10792                                                "[sw state]");
10793                 }
10794         }
10795 }
10796
10797 static void
10798 check_shared_dpll_state(struct drm_device *dev)
10799 {
10800         struct drm_i915_private *dev_priv = dev->dev_private;
10801         struct intel_crtc *crtc;
10802         struct intel_dpll_hw_state dpll_hw_state;
10803         int i;
10804
10805         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10806                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10807                 int enabled_crtcs = 0, active_crtcs = 0;
10808                 bool active;
10809
10810                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10811
10812                 DRM_DEBUG_KMS("%s\n", pll->name);
10813
10814                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10815
10816                 WARN(pll->active > pll->refcount,
10817                      "more active pll users than references: %i vs %i\n",
10818                      pll->active, pll->refcount);
10819                 WARN(pll->active && !pll->on,
10820                      "pll in active use but not on in sw tracking\n");
10821                 WARN(pll->on && !pll->active,
10822                      "pll in on but not on in use in sw tracking\n");
10823                 WARN(pll->on != active,
10824                      "pll on state mismatch (expected %i, found %i)\n",
10825                      pll->on, active);
10826
10827                 for_each_intel_crtc(dev, crtc) {
10828                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10829                                 enabled_crtcs++;
10830                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10831                                 active_crtcs++;
10832                 }
10833                 WARN(pll->active != active_crtcs,
10834                      "pll active crtcs mismatch (expected %i, found %i)\n",
10835                      pll->active, active_crtcs);
10836                 WARN(pll->refcount != enabled_crtcs,
10837                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10838                      pll->refcount, enabled_crtcs);
10839
10840                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10841                                        sizeof(dpll_hw_state)),
10842                      "pll hw state mismatch\n");
10843         }
10844 }
10845
10846 void
10847 intel_modeset_check_state(struct drm_device *dev)
10848 {
10849         check_connector_state(dev);
10850         check_encoder_state(dev);
10851         check_crtc_state(dev);
10852         check_shared_dpll_state(dev);
10853 }
10854
10855 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10856                                      int dotclock)
10857 {
10858         /*
10859          * FDI already provided one idea for the dotclock.
10860          * Yell if the encoder disagrees.
10861          */
10862         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10863              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10864              pipe_config->adjusted_mode.crtc_clock, dotclock);
10865 }
10866
10867 static void update_scanline_offset(struct intel_crtc *crtc)
10868 {
10869         struct drm_device *dev = crtc->base.dev;
10870
10871         /*
10872          * The scanline counter increments at the leading edge of hsync.
10873          *
10874          * On most platforms it starts counting from vtotal-1 on the
10875          * first active line. That means the scanline counter value is
10876          * always one less than what we would expect. Ie. just after
10877          * start of vblank, which also occurs at start of hsync (on the
10878          * last active line), the scanline counter will read vblank_start-1.
10879          *
10880          * On gen2 the scanline counter starts counting from 1 instead
10881          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10882          * to keep the value positive), instead of adding one.
10883          *
10884          * On HSW+ the behaviour of the scanline counter depends on the output
10885          * type. For DP ports it behaves like most other platforms, but on HDMI
10886          * there's an extra 1 line difference. So we need to add two instead of
10887          * one to the value.
10888          */
10889         if (IS_GEN2(dev)) {
10890                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10891                 int vtotal;
10892
10893                 vtotal = mode->crtc_vtotal;
10894                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10895                         vtotal /= 2;
10896
10897                 crtc->scanline_offset = vtotal - 1;
10898         } else if (HAS_DDI(dev) &&
10899                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10900                 crtc->scanline_offset = 2;
10901         } else
10902                 crtc->scanline_offset = 1;
10903 }
10904
10905 static int __intel_set_mode(struct drm_crtc *crtc,
10906                             struct drm_display_mode *mode,
10907                             int x, int y, struct drm_framebuffer *fb)
10908 {
10909         struct drm_device *dev = crtc->dev;
10910         struct drm_i915_private *dev_priv = dev->dev_private;
10911         struct drm_display_mode *saved_mode;
10912         struct intel_crtc_config *pipe_config = NULL;
10913         struct intel_crtc *intel_crtc;
10914         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10915         int ret = 0;
10916
10917         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10918         if (!saved_mode)
10919                 return -ENOMEM;
10920
10921         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10922                                      &prepare_pipes, &disable_pipes);
10923
10924         *saved_mode = crtc->mode;
10925
10926         /* Hack: Because we don't (yet) support global modeset on multiple
10927          * crtcs, we don't keep track of the new mode for more than one crtc.
10928          * Hence simply check whether any bit is set in modeset_pipes in all the
10929          * pieces of code that are not yet converted to deal with mutliple crtcs
10930          * changing their mode at the same time. */
10931         if (modeset_pipes) {
10932                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10933                 if (IS_ERR(pipe_config)) {
10934                         ret = PTR_ERR(pipe_config);
10935                         pipe_config = NULL;
10936
10937                         goto out;
10938                 }
10939                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10940                                        "[modeset]");
10941                 to_intel_crtc(crtc)->new_config = pipe_config;
10942         }
10943
10944         /*
10945          * See if the config requires any additional preparation, e.g.
10946          * to adjust global state with pipes off.  We need to do this
10947          * here so we can get the modeset_pipe updated config for the new
10948          * mode set on this crtc.  For other crtcs we need to use the
10949          * adjusted_mode bits in the crtc directly.
10950          */
10951         if (IS_VALLEYVIEW(dev)) {
10952                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10953
10954                 /* may have added more to prepare_pipes than we should */
10955                 prepare_pipes &= ~disable_pipes;
10956         }
10957
10958         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10959                 intel_crtc_disable(&intel_crtc->base);
10960
10961         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10962                 if (intel_crtc->base.enabled)
10963                         dev_priv->display.crtc_disable(&intel_crtc->base);
10964         }
10965
10966         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10967          * to set it here already despite that we pass it down the callchain.
10968          */
10969         if (modeset_pipes) {
10970                 crtc->mode = *mode;
10971                 /* mode_set/enable/disable functions rely on a correct pipe
10972                  * config. */
10973                 to_intel_crtc(crtc)->config = *pipe_config;
10974                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10975
10976                 /*
10977                  * Calculate and store various constants which
10978                  * are later needed by vblank and swap-completion
10979                  * timestamping. They are derived from true hwmode.
10980                  */
10981                 drm_calc_timestamping_constants(crtc,
10982                                                 &pipe_config->adjusted_mode);
10983         }
10984
10985         /* Only after disabling all output pipelines that will be changed can we
10986          * update the the output configuration. */
10987         intel_modeset_update_state(dev, prepare_pipes);
10988
10989         if (dev_priv->display.modeset_global_resources)
10990                 dev_priv->display.modeset_global_resources(dev);
10991
10992         /* Set up the DPLL and any encoders state that needs to adjust or depend
10993          * on the DPLL.
10994          */
10995         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10996                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10997                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10998                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10999
11000                 mutex_lock(&dev->struct_mutex);
11001                 ret = intel_pin_and_fence_fb_obj(dev,
11002                                                  obj,
11003                                                  NULL);
11004                 if (ret != 0) {
11005                         DRM_ERROR("pin & fence failed\n");
11006                         mutex_unlock(&dev->struct_mutex);
11007                         goto done;
11008                 }
11009                 if (old_fb)
11010                         intel_unpin_fb_obj(old_obj);
11011                 i915_gem_track_fb(old_obj, obj,
11012                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11013                 mutex_unlock(&dev->struct_mutex);
11014
11015                 crtc->primary->fb = fb;
11016                 crtc->x = x;
11017                 crtc->y = y;
11018
11019                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
11020                 if (ret)
11021                         goto done;
11022         }
11023
11024         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11025         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11026                 update_scanline_offset(intel_crtc);
11027
11028                 dev_priv->display.crtc_enable(&intel_crtc->base);
11029         }
11030
11031         /* FIXME: add subpixel order */
11032 done:
11033         if (ret && crtc->enabled)
11034                 crtc->mode = *saved_mode;
11035
11036 out:
11037         kfree(pipe_config);
11038         kfree(saved_mode);
11039         return ret;
11040 }
11041
11042 static int intel_set_mode(struct drm_crtc *crtc,
11043                           struct drm_display_mode *mode,
11044                           int x, int y, struct drm_framebuffer *fb)
11045 {
11046         int ret;
11047
11048         ret = __intel_set_mode(crtc, mode, x, y, fb);
11049
11050         if (ret == 0)
11051                 intel_modeset_check_state(crtc->dev);
11052
11053         return ret;
11054 }
11055
11056 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11057 {
11058         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11059 }
11060
11061 #undef for_each_intel_crtc_masked
11062
11063 static void intel_set_config_free(struct intel_set_config *config)
11064 {
11065         if (!config)
11066                 return;
11067
11068         kfree(config->save_connector_encoders);
11069         kfree(config->save_encoder_crtcs);
11070         kfree(config->save_crtc_enabled);
11071         kfree(config);
11072 }
11073
11074 static int intel_set_config_save_state(struct drm_device *dev,
11075                                        struct intel_set_config *config)
11076 {
11077         struct drm_crtc *crtc;
11078         struct drm_encoder *encoder;
11079         struct drm_connector *connector;
11080         int count;
11081
11082         config->save_crtc_enabled =
11083                 kcalloc(dev->mode_config.num_crtc,
11084                         sizeof(bool), GFP_KERNEL);
11085         if (!config->save_crtc_enabled)
11086                 return -ENOMEM;
11087
11088         config->save_encoder_crtcs =
11089                 kcalloc(dev->mode_config.num_encoder,
11090                         sizeof(struct drm_crtc *), GFP_KERNEL);
11091         if (!config->save_encoder_crtcs)
11092                 return -ENOMEM;
11093
11094         config->save_connector_encoders =
11095                 kcalloc(dev->mode_config.num_connector,
11096                         sizeof(struct drm_encoder *), GFP_KERNEL);
11097         if (!config->save_connector_encoders)
11098                 return -ENOMEM;
11099
11100         /* Copy data. Note that driver private data is not affected.
11101          * Should anything bad happen only the expected state is
11102          * restored, not the drivers personal bookkeeping.
11103          */
11104         count = 0;
11105         for_each_crtc(dev, crtc) {
11106                 config->save_crtc_enabled[count++] = crtc->enabled;
11107         }
11108
11109         count = 0;
11110         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11111                 config->save_encoder_crtcs[count++] = encoder->crtc;
11112         }
11113
11114         count = 0;
11115         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11116                 config->save_connector_encoders[count++] = connector->encoder;
11117         }
11118
11119         return 0;
11120 }
11121
11122 static void intel_set_config_restore_state(struct drm_device *dev,
11123                                            struct intel_set_config *config)
11124 {
11125         struct intel_crtc *crtc;
11126         struct intel_encoder *encoder;
11127         struct intel_connector *connector;
11128         int count;
11129
11130         count = 0;
11131         for_each_intel_crtc(dev, crtc) {
11132                 crtc->new_enabled = config->save_crtc_enabled[count++];
11133
11134                 if (crtc->new_enabled)
11135                         crtc->new_config = &crtc->config;
11136                 else
11137                         crtc->new_config = NULL;
11138         }
11139
11140         count = 0;
11141         for_each_intel_encoder(dev, encoder) {
11142                 encoder->new_crtc =
11143                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11144         }
11145
11146         count = 0;
11147         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11148                 connector->new_encoder =
11149                         to_intel_encoder(config->save_connector_encoders[count++]);
11150         }
11151 }
11152
11153 static bool
11154 is_crtc_connector_off(struct drm_mode_set *set)
11155 {
11156         int i;
11157
11158         if (set->num_connectors == 0)
11159                 return false;
11160
11161         if (WARN_ON(set->connectors == NULL))
11162                 return false;
11163
11164         for (i = 0; i < set->num_connectors; i++)
11165                 if (set->connectors[i]->encoder &&
11166                     set->connectors[i]->encoder->crtc == set->crtc &&
11167                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11168                         return true;
11169
11170         return false;
11171 }
11172
11173 static void
11174 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11175                                       struct intel_set_config *config)
11176 {
11177
11178         /* We should be able to check here if the fb has the same properties
11179          * and then just flip_or_move it */
11180         if (is_crtc_connector_off(set)) {
11181                 config->mode_changed = true;
11182         } else if (set->crtc->primary->fb != set->fb) {
11183                 /*
11184                  * If we have no fb, we can only flip as long as the crtc is
11185                  * active, otherwise we need a full mode set.  The crtc may
11186                  * be active if we've only disabled the primary plane, or
11187                  * in fastboot situations.
11188                  */
11189                 if (set->crtc->primary->fb == NULL) {
11190                         struct intel_crtc *intel_crtc =
11191                                 to_intel_crtc(set->crtc);
11192
11193                         if (intel_crtc->active) {
11194                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11195                                 config->fb_changed = true;
11196                         } else {
11197                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11198                                 config->mode_changed = true;
11199                         }
11200                 } else if (set->fb == NULL) {
11201                         config->mode_changed = true;
11202                 } else if (set->fb->pixel_format !=
11203                            set->crtc->primary->fb->pixel_format) {
11204                         config->mode_changed = true;
11205                 } else {
11206                         config->fb_changed = true;
11207                 }
11208         }
11209
11210         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11211                 config->fb_changed = true;
11212
11213         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11214                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11215                 drm_mode_debug_printmodeline(&set->crtc->mode);
11216                 drm_mode_debug_printmodeline(set->mode);
11217                 config->mode_changed = true;
11218         }
11219
11220         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11221                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11222 }
11223
11224 static int
11225 intel_modeset_stage_output_state(struct drm_device *dev,
11226                                  struct drm_mode_set *set,
11227                                  struct intel_set_config *config)
11228 {
11229         struct intel_connector *connector;
11230         struct intel_encoder *encoder;
11231         struct intel_crtc *crtc;
11232         int ro;
11233
11234         /* The upper layers ensure that we either disable a crtc or have a list
11235          * of connectors. For paranoia, double-check this. */
11236         WARN_ON(!set->fb && (set->num_connectors != 0));
11237         WARN_ON(set->fb && (set->num_connectors == 0));
11238
11239         list_for_each_entry(connector, &dev->mode_config.connector_list,
11240                             base.head) {
11241                 /* Otherwise traverse passed in connector list and get encoders
11242                  * for them. */
11243                 for (ro = 0; ro < set->num_connectors; ro++) {
11244                         if (set->connectors[ro] == &connector->base) {
11245                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11246                                 break;
11247                         }
11248                 }
11249
11250                 /* If we disable the crtc, disable all its connectors. Also, if
11251                  * the connector is on the changing crtc but not on the new
11252                  * connector list, disable it. */
11253                 if ((!set->fb || ro == set->num_connectors) &&
11254                     connector->base.encoder &&
11255                     connector->base.encoder->crtc == set->crtc) {
11256                         connector->new_encoder = NULL;
11257
11258                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11259                                 connector->base.base.id,
11260                                 connector->base.name);
11261                 }
11262
11263
11264                 if (&connector->new_encoder->base != connector->base.encoder) {
11265                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11266                         config->mode_changed = true;
11267                 }
11268         }
11269         /* connector->new_encoder is now updated for all connectors. */
11270
11271         /* Update crtc of enabled connectors. */
11272         list_for_each_entry(connector, &dev->mode_config.connector_list,
11273                             base.head) {
11274                 struct drm_crtc *new_crtc;
11275
11276                 if (!connector->new_encoder)
11277                         continue;
11278
11279                 new_crtc = connector->new_encoder->base.crtc;
11280
11281                 for (ro = 0; ro < set->num_connectors; ro++) {
11282                         if (set->connectors[ro] == &connector->base)
11283                                 new_crtc = set->crtc;
11284                 }
11285
11286                 /* Make sure the new CRTC will work with the encoder */
11287                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11288                                          new_crtc)) {
11289                         return -EINVAL;
11290                 }
11291                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11292
11293                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11294                         connector->base.base.id,
11295                         connector->base.name,
11296                         new_crtc->base.id);
11297         }
11298
11299         /* Check for any encoders that needs to be disabled. */
11300         for_each_intel_encoder(dev, encoder) {
11301                 int num_connectors = 0;
11302                 list_for_each_entry(connector,
11303                                     &dev->mode_config.connector_list,
11304                                     base.head) {
11305                         if (connector->new_encoder == encoder) {
11306                                 WARN_ON(!connector->new_encoder->new_crtc);
11307                                 num_connectors++;
11308                         }
11309                 }
11310
11311                 if (num_connectors == 0)
11312                         encoder->new_crtc = NULL;
11313                 else if (num_connectors > 1)
11314                         return -EINVAL;
11315
11316                 /* Only now check for crtc changes so we don't miss encoders
11317                  * that will be disabled. */
11318                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11319                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11320                         config->mode_changed = true;
11321                 }
11322         }
11323         /* Now we've also updated encoder->new_crtc for all encoders. */
11324         list_for_each_entry(connector, &dev->mode_config.connector_list,
11325                             base.head) {
11326                 if (connector->new_encoder)
11327                         if (connector->new_encoder != connector->encoder)
11328                                 connector->encoder = connector->new_encoder;
11329         }
11330         for_each_intel_crtc(dev, crtc) {
11331                 crtc->new_enabled = false;
11332
11333                 for_each_intel_encoder(dev, encoder) {
11334                         if (encoder->new_crtc == crtc) {
11335                                 crtc->new_enabled = true;
11336                                 break;
11337                         }
11338                 }
11339
11340                 if (crtc->new_enabled != crtc->base.enabled) {
11341                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11342                                       crtc->new_enabled ? "en" : "dis");
11343                         config->mode_changed = true;
11344                 }
11345
11346                 if (crtc->new_enabled)
11347                         crtc->new_config = &crtc->config;
11348                 else
11349                         crtc->new_config = NULL;
11350         }
11351
11352         return 0;
11353 }
11354
11355 static void disable_crtc_nofb(struct intel_crtc *crtc)
11356 {
11357         struct drm_device *dev = crtc->base.dev;
11358         struct intel_encoder *encoder;
11359         struct intel_connector *connector;
11360
11361         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11362                       pipe_name(crtc->pipe));
11363
11364         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11365                 if (connector->new_encoder &&
11366                     connector->new_encoder->new_crtc == crtc)
11367                         connector->new_encoder = NULL;
11368         }
11369
11370         for_each_intel_encoder(dev, encoder) {
11371                 if (encoder->new_crtc == crtc)
11372                         encoder->new_crtc = NULL;
11373         }
11374
11375         crtc->new_enabled = false;
11376         crtc->new_config = NULL;
11377 }
11378
11379 static int intel_crtc_set_config(struct drm_mode_set *set)
11380 {
11381         struct drm_device *dev;
11382         struct drm_mode_set save_set;
11383         struct intel_set_config *config;
11384         int ret;
11385
11386         BUG_ON(!set);
11387         BUG_ON(!set->crtc);
11388         BUG_ON(!set->crtc->helper_private);
11389
11390         /* Enforce sane interface api - has been abused by the fb helper. */
11391         BUG_ON(!set->mode && set->fb);
11392         BUG_ON(set->fb && set->num_connectors == 0);
11393
11394         if (set->fb) {
11395                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11396                                 set->crtc->base.id, set->fb->base.id,
11397                                 (int)set->num_connectors, set->x, set->y);
11398         } else {
11399                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11400         }
11401
11402         dev = set->crtc->dev;
11403
11404         ret = -ENOMEM;
11405         config = kzalloc(sizeof(*config), GFP_KERNEL);
11406         if (!config)
11407                 goto out_config;
11408
11409         ret = intel_set_config_save_state(dev, config);
11410         if (ret)
11411                 goto out_config;
11412
11413         save_set.crtc = set->crtc;
11414         save_set.mode = &set->crtc->mode;
11415         save_set.x = set->crtc->x;
11416         save_set.y = set->crtc->y;
11417         save_set.fb = set->crtc->primary->fb;
11418
11419         /* Compute whether we need a full modeset, only an fb base update or no
11420          * change at all. In the future we might also check whether only the
11421          * mode changed, e.g. for LVDS where we only change the panel fitter in
11422          * such cases. */
11423         intel_set_config_compute_mode_changes(set, config);
11424
11425         ret = intel_modeset_stage_output_state(dev, set, config);
11426         if (ret)
11427                 goto fail;
11428
11429         if (config->mode_changed) {
11430                 ret = intel_set_mode(set->crtc, set->mode,
11431                                      set->x, set->y, set->fb);
11432         } else if (config->fb_changed) {
11433                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11434
11435                 intel_crtc_wait_for_pending_flips(set->crtc);
11436
11437                 ret = intel_pipe_set_base(set->crtc,
11438                                           set->x, set->y, set->fb);
11439
11440                 /*
11441                  * We need to make sure the primary plane is re-enabled if it
11442                  * has previously been turned off.
11443                  */
11444                 if (!intel_crtc->primary_enabled && ret == 0) {
11445                         WARN_ON(!intel_crtc->active);
11446                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11447                 }
11448
11449                 /*
11450                  * In the fastboot case this may be our only check of the
11451                  * state after boot.  It would be better to only do it on
11452                  * the first update, but we don't have a nice way of doing that
11453                  * (and really, set_config isn't used much for high freq page
11454                  * flipping, so increasing its cost here shouldn't be a big
11455                  * deal).
11456                  */
11457                 if (i915.fastboot && ret == 0)
11458                         intel_modeset_check_state(set->crtc->dev);
11459         }
11460
11461         if (ret) {
11462                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11463                               set->crtc->base.id, ret);
11464 fail:
11465                 intel_set_config_restore_state(dev, config);
11466
11467                 /*
11468                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11469                  * force the pipe off to avoid oopsing in the modeset code
11470                  * due to fb==NULL. This should only happen during boot since
11471                  * we don't yet reconstruct the FB from the hardware state.
11472                  */
11473                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11474                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11475
11476                 /* Try to restore the config */
11477                 if (config->mode_changed &&
11478                     intel_set_mode(save_set.crtc, save_set.mode,
11479                                    save_set.x, save_set.y, save_set.fb))
11480                         DRM_ERROR("failed to restore config after modeset failure\n");
11481         }
11482
11483 out_config:
11484         intel_set_config_free(config);
11485         return ret;
11486 }
11487
11488 static const struct drm_crtc_funcs intel_crtc_funcs = {
11489         .gamma_set = intel_crtc_gamma_set,
11490         .set_config = intel_crtc_set_config,
11491         .destroy = intel_crtc_destroy,
11492         .page_flip = intel_crtc_page_flip,
11493 };
11494
11495 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11496                                       struct intel_shared_dpll *pll,
11497                                       struct intel_dpll_hw_state *hw_state)
11498 {
11499         uint32_t val;
11500
11501         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11502                 return false;
11503
11504         val = I915_READ(PCH_DPLL(pll->id));
11505         hw_state->dpll = val;
11506         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11507         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11508
11509         return val & DPLL_VCO_ENABLE;
11510 }
11511
11512 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11513                                   struct intel_shared_dpll *pll)
11514 {
11515         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11516         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11517 }
11518
11519 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11520                                 struct intel_shared_dpll *pll)
11521 {
11522         /* PCH refclock must be enabled first */
11523         ibx_assert_pch_refclk_enabled(dev_priv);
11524
11525         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11526
11527         /* Wait for the clocks to stabilize. */
11528         POSTING_READ(PCH_DPLL(pll->id));
11529         udelay(150);
11530
11531         /* The pixel multiplier can only be updated once the
11532          * DPLL is enabled and the clocks are stable.
11533          *
11534          * So write it again.
11535          */
11536         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11537         POSTING_READ(PCH_DPLL(pll->id));
11538         udelay(200);
11539 }
11540
11541 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11542                                  struct intel_shared_dpll *pll)
11543 {
11544         struct drm_device *dev = dev_priv->dev;
11545         struct intel_crtc *crtc;
11546
11547         /* Make sure no transcoder isn't still depending on us. */
11548         for_each_intel_crtc(dev, crtc) {
11549                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11550                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11551         }
11552
11553         I915_WRITE(PCH_DPLL(pll->id), 0);
11554         POSTING_READ(PCH_DPLL(pll->id));
11555         udelay(200);
11556 }
11557
11558 static char *ibx_pch_dpll_names[] = {
11559         "PCH DPLL A",
11560         "PCH DPLL B",
11561 };
11562
11563 static void ibx_pch_dpll_init(struct drm_device *dev)
11564 {
11565         struct drm_i915_private *dev_priv = dev->dev_private;
11566         int i;
11567
11568         dev_priv->num_shared_dpll = 2;
11569
11570         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11571                 dev_priv->shared_dplls[i].id = i;
11572                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11573                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11574                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11575                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11576                 dev_priv->shared_dplls[i].get_hw_state =
11577                         ibx_pch_dpll_get_hw_state;
11578         }
11579 }
11580
11581 static void intel_shared_dpll_init(struct drm_device *dev)
11582 {
11583         struct drm_i915_private *dev_priv = dev->dev_private;
11584
11585         if (HAS_DDI(dev))
11586                 intel_ddi_pll_init(dev);
11587         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11588                 ibx_pch_dpll_init(dev);
11589         else
11590                 dev_priv->num_shared_dpll = 0;
11591
11592         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11593 }
11594
11595 static int
11596 intel_primary_plane_disable(struct drm_plane *plane)
11597 {
11598         struct drm_device *dev = plane->dev;
11599         struct intel_crtc *intel_crtc;
11600
11601         if (!plane->fb)
11602                 return 0;
11603
11604         BUG_ON(!plane->crtc);
11605
11606         intel_crtc = to_intel_crtc(plane->crtc);
11607
11608         /*
11609          * Even though we checked plane->fb above, it's still possible that
11610          * the primary plane has been implicitly disabled because the crtc
11611          * coordinates given weren't visible, or because we detected
11612          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11613          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11614          * In either case, we need to unpin the FB and let the fb pointer get
11615          * updated, but otherwise we don't need to touch the hardware.
11616          */
11617         if (!intel_crtc->primary_enabled)
11618                 goto disable_unpin;
11619
11620         intel_crtc_wait_for_pending_flips(plane->crtc);
11621         intel_disable_primary_hw_plane(plane, plane->crtc);
11622
11623 disable_unpin:
11624         mutex_lock(&dev->struct_mutex);
11625         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11626                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11627         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11628         mutex_unlock(&dev->struct_mutex);
11629         plane->fb = NULL;
11630
11631         return 0;
11632 }
11633
11634 static int
11635 intel_check_primary_plane(struct drm_plane *plane,
11636                           struct intel_plane_state *state)
11637 {
11638         struct drm_crtc *crtc = state->crtc;
11639         struct drm_framebuffer *fb = state->fb;
11640         struct drm_rect *dest = &state->dst;
11641         struct drm_rect *src = &state->src;
11642         const struct drm_rect *clip = &state->clip;
11643         int ret;
11644
11645         ret = drm_plane_helper_check_update(plane, crtc, fb,
11646                                             src, dest, clip,
11647                                             DRM_PLANE_HELPER_NO_SCALING,
11648                                             DRM_PLANE_HELPER_NO_SCALING,
11649                                             false, true, &state->visible);
11650         if (ret)
11651                 return ret;
11652
11653         /* no fb bound */
11654         if (state->visible && !fb) {
11655                 DRM_ERROR("No FB bound\n");
11656                 return -EINVAL;
11657         }
11658
11659         return 0;
11660 }
11661
11662 static int
11663 intel_commit_primary_plane(struct drm_plane *plane,
11664                            struct intel_plane_state *state)
11665 {
11666         struct drm_crtc *crtc = state->crtc;
11667         struct drm_framebuffer *fb = state->fb;
11668         struct drm_device *dev = crtc->dev;
11669         struct drm_i915_private *dev_priv = dev->dev_private;
11670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11671         enum pipe pipe = intel_crtc->pipe;
11672         struct drm_framebuffer *old_fb = plane->fb;
11673         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11674         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11675         struct intel_plane *intel_plane = to_intel_plane(plane);
11676         struct drm_rect *src = &state->src;
11677         int ret;
11678
11679         intel_crtc_wait_for_pending_flips(crtc);
11680
11681         if (intel_crtc_has_pending_flip(crtc)) {
11682                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11683                 return -EBUSY;
11684         }
11685
11686         if (plane->fb != fb) {
11687                 mutex_lock(&dev->struct_mutex);
11688                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11689                 if (ret == 0)
11690                         i915_gem_track_fb(old_obj, obj,
11691                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11692                 mutex_unlock(&dev->struct_mutex);
11693                 if (ret != 0) {
11694                         DRM_DEBUG_KMS("pin & fence failed\n");
11695                         return ret;
11696                 }
11697         }
11698
11699         crtc->primary->fb = fb;
11700         crtc->x = src->x1;
11701         crtc->y = src->y1;
11702
11703         intel_plane->crtc_x = state->orig_dst.x1;
11704         intel_plane->crtc_y = state->orig_dst.y1;
11705         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11706         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11707         intel_plane->src_x = state->orig_src.x1;
11708         intel_plane->src_y = state->orig_src.y1;
11709         intel_plane->src_w = drm_rect_width(&state->orig_src);
11710         intel_plane->src_h = drm_rect_height(&state->orig_src);
11711         intel_plane->obj = obj;
11712
11713         if (intel_crtc->active) {
11714                 /*
11715                  * FBC does not work on some platforms for rotated
11716                  * planes, so disable it when rotation is not 0 and
11717                  * update it when rotation is set back to 0.
11718                  *
11719                  * FIXME: This is redundant with the fbc update done in
11720                  * the primary plane enable function except that that
11721                  * one is done too late. We eventually need to unify
11722                  * this.
11723                  */
11724                 if (intel_crtc->primary_enabled &&
11725                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11726                     dev_priv->fbc.plane == intel_crtc->plane &&
11727                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11728                         intel_disable_fbc(dev);
11729                 }
11730
11731                 if (state->visible) {
11732                         bool was_enabled = intel_crtc->primary_enabled;
11733
11734                         /* FIXME: kill this fastboot hack */
11735                         intel_update_pipe_size(intel_crtc);
11736
11737                         intel_crtc->primary_enabled = true;
11738
11739                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11740                                         crtc->x, crtc->y);
11741
11742                         /*
11743                          * BDW signals flip done immediately if the plane
11744                          * is disabled, even if the plane enable is already
11745                          * armed to occur at the next vblank :(
11746                          */
11747                         if (IS_BROADWELL(dev) && !was_enabled)
11748                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11749                 } else {
11750                         /*
11751                          * If clipping results in a non-visible primary plane,
11752                          * we'll disable the primary plane.  Note that this is
11753                          * a bit different than what happens if userspace
11754                          * explicitly disables the plane by passing fb=0
11755                          * because plane->fb still gets set and pinned.
11756                          */
11757                         intel_disable_primary_hw_plane(plane, crtc);
11758                 }
11759
11760                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11761
11762                 mutex_lock(&dev->struct_mutex);
11763                 intel_update_fbc(dev);
11764                 mutex_unlock(&dev->struct_mutex);
11765         }
11766
11767         if (old_fb && old_fb != fb) {
11768                 if (intel_crtc->active)
11769                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11770
11771                 mutex_lock(&dev->struct_mutex);
11772                 intel_unpin_fb_obj(old_obj);
11773                 mutex_unlock(&dev->struct_mutex);
11774         }
11775
11776         return 0;
11777 }
11778
11779 static int
11780 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11781                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11782                              unsigned int crtc_w, unsigned int crtc_h,
11783                              uint32_t src_x, uint32_t src_y,
11784                              uint32_t src_w, uint32_t src_h)
11785 {
11786         struct intel_plane_state state;
11787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11788         int ret;
11789
11790         state.crtc = crtc;
11791         state.fb = fb;
11792
11793         /* sample coordinates in 16.16 fixed point */
11794         state.src.x1 = src_x;
11795         state.src.x2 = src_x + src_w;
11796         state.src.y1 = src_y;
11797         state.src.y2 = src_y + src_h;
11798
11799         /* integer pixels */
11800         state.dst.x1 = crtc_x;
11801         state.dst.x2 = crtc_x + crtc_w;
11802         state.dst.y1 = crtc_y;
11803         state.dst.y2 = crtc_y + crtc_h;
11804
11805         state.clip.x1 = 0;
11806         state.clip.y1 = 0;
11807         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11808         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11809
11810         state.orig_src = state.src;
11811         state.orig_dst = state.dst;
11812
11813         ret = intel_check_primary_plane(plane, &state);
11814         if (ret)
11815                 return ret;
11816
11817         intel_commit_primary_plane(plane, &state);
11818
11819         return 0;
11820 }
11821
11822 /* Common destruction function for both primary and cursor planes */
11823 static void intel_plane_destroy(struct drm_plane *plane)
11824 {
11825         struct intel_plane *intel_plane = to_intel_plane(plane);
11826         drm_plane_cleanup(plane);
11827         kfree(intel_plane);
11828 }
11829
11830 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11831         .update_plane = intel_primary_plane_setplane,
11832         .disable_plane = intel_primary_plane_disable,
11833         .destroy = intel_plane_destroy,
11834         .set_property = intel_plane_set_property
11835 };
11836
11837 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11838                                                     int pipe)
11839 {
11840         struct intel_plane *primary;
11841         const uint32_t *intel_primary_formats;
11842         int num_formats;
11843
11844         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11845         if (primary == NULL)
11846                 return NULL;
11847
11848         primary->can_scale = false;
11849         primary->max_downscale = 1;
11850         primary->pipe = pipe;
11851         primary->plane = pipe;
11852         primary->rotation = BIT(DRM_ROTATE_0);
11853         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11854                 primary->plane = !pipe;
11855
11856         if (INTEL_INFO(dev)->gen <= 3) {
11857                 intel_primary_formats = intel_primary_formats_gen2;
11858                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11859         } else {
11860                 intel_primary_formats = intel_primary_formats_gen4;
11861                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11862         }
11863
11864         drm_universal_plane_init(dev, &primary->base, 0,
11865                                  &intel_primary_plane_funcs,
11866                                  intel_primary_formats, num_formats,
11867                                  DRM_PLANE_TYPE_PRIMARY);
11868
11869         if (INTEL_INFO(dev)->gen >= 4) {
11870                 if (!dev->mode_config.rotation_property)
11871                         dev->mode_config.rotation_property =
11872                                 drm_mode_create_rotation_property(dev,
11873                                                         BIT(DRM_ROTATE_0) |
11874                                                         BIT(DRM_ROTATE_180));
11875                 if (dev->mode_config.rotation_property)
11876                         drm_object_attach_property(&primary->base.base,
11877                                 dev->mode_config.rotation_property,
11878                                 primary->rotation);
11879         }
11880
11881         return &primary->base;
11882 }
11883
11884 static int
11885 intel_cursor_plane_disable(struct drm_plane *plane)
11886 {
11887         if (!plane->fb)
11888                 return 0;
11889
11890         BUG_ON(!plane->crtc);
11891
11892         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11893 }
11894
11895 static int
11896 intel_check_cursor_plane(struct drm_plane *plane,
11897                          struct intel_plane_state *state)
11898 {
11899         struct drm_crtc *crtc = state->crtc;
11900         struct drm_device *dev = crtc->dev;
11901         struct drm_framebuffer *fb = state->fb;
11902         struct drm_rect *dest = &state->dst;
11903         struct drm_rect *src = &state->src;
11904         const struct drm_rect *clip = &state->clip;
11905         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11906         int crtc_w, crtc_h;
11907         unsigned stride;
11908         int ret;
11909
11910         ret = drm_plane_helper_check_update(plane, crtc, fb,
11911                                             src, dest, clip,
11912                                             DRM_PLANE_HELPER_NO_SCALING,
11913                                             DRM_PLANE_HELPER_NO_SCALING,
11914                                             true, true, &state->visible);
11915         if (ret)
11916                 return ret;
11917
11918
11919         /* if we want to turn off the cursor ignore width and height */
11920         if (!obj)
11921                 return 0;
11922
11923         /* Check for which cursor types we support */
11924         crtc_w = drm_rect_width(&state->orig_dst);
11925         crtc_h = drm_rect_height(&state->orig_dst);
11926         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11927                 DRM_DEBUG("Cursor dimension not supported\n");
11928                 return -EINVAL;
11929         }
11930
11931         stride = roundup_pow_of_two(crtc_w) * 4;
11932         if (obj->base.size < stride * crtc_h) {
11933                 DRM_DEBUG_KMS("buffer is too small\n");
11934                 return -ENOMEM;
11935         }
11936
11937         if (fb == crtc->cursor->fb)
11938                 return 0;
11939
11940         /* we only need to pin inside GTT if cursor is non-phy */
11941         mutex_lock(&dev->struct_mutex);
11942         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11943                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11944                 ret = -EINVAL;
11945         }
11946         mutex_unlock(&dev->struct_mutex);
11947
11948         return ret;
11949 }
11950
11951 static int
11952 intel_commit_cursor_plane(struct drm_plane *plane,
11953                           struct intel_plane_state *state)
11954 {
11955         struct drm_crtc *crtc = state->crtc;
11956         struct drm_framebuffer *fb = state->fb;
11957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11958         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11959         struct drm_i915_gem_object *obj = intel_fb->obj;
11960         int crtc_w, crtc_h;
11961
11962         crtc->cursor_x = state->orig_dst.x1;
11963         crtc->cursor_y = state->orig_dst.y1;
11964         if (fb != crtc->cursor->fb) {
11965                 crtc_w = drm_rect_width(&state->orig_dst);
11966                 crtc_h = drm_rect_height(&state->orig_dst);
11967                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11968         } else {
11969                 intel_crtc_update_cursor(crtc, state->visible);
11970
11971                 intel_frontbuffer_flip(crtc->dev,
11972                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11973
11974                 return 0;
11975         }
11976 }
11977
11978 static int
11979 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11980                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11981                           unsigned int crtc_w, unsigned int crtc_h,
11982                           uint32_t src_x, uint32_t src_y,
11983                           uint32_t src_w, uint32_t src_h)
11984 {
11985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11986         struct intel_plane_state state;
11987         int ret;
11988
11989         state.crtc = crtc;
11990         state.fb = fb;
11991
11992         /* sample coordinates in 16.16 fixed point */
11993         state.src.x1 = src_x;
11994         state.src.x2 = src_x + src_w;
11995         state.src.y1 = src_y;
11996         state.src.y2 = src_y + src_h;
11997
11998         /* integer pixels */
11999         state.dst.x1 = crtc_x;
12000         state.dst.x2 = crtc_x + crtc_w;
12001         state.dst.y1 = crtc_y;
12002         state.dst.y2 = crtc_y + crtc_h;
12003
12004         state.clip.x1 = 0;
12005         state.clip.y1 = 0;
12006         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12007         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12008
12009         state.orig_src = state.src;
12010         state.orig_dst = state.dst;
12011
12012         ret = intel_check_cursor_plane(plane, &state);
12013         if (ret)
12014                 return ret;
12015
12016         return intel_commit_cursor_plane(plane, &state);
12017 }
12018
12019 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12020         .update_plane = intel_cursor_plane_update,
12021         .disable_plane = intel_cursor_plane_disable,
12022         .destroy = intel_plane_destroy,
12023         .set_property = intel_plane_set_property,
12024 };
12025
12026 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12027                                                    int pipe)
12028 {
12029         struct intel_plane *cursor;
12030
12031         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12032         if (cursor == NULL)
12033                 return NULL;
12034
12035         cursor->can_scale = false;
12036         cursor->max_downscale = 1;
12037         cursor->pipe = pipe;
12038         cursor->plane = pipe;
12039         cursor->rotation = BIT(DRM_ROTATE_0);
12040
12041         drm_universal_plane_init(dev, &cursor->base, 0,
12042                                  &intel_cursor_plane_funcs,
12043                                  intel_cursor_formats,
12044                                  ARRAY_SIZE(intel_cursor_formats),
12045                                  DRM_PLANE_TYPE_CURSOR);
12046
12047         if (INTEL_INFO(dev)->gen >= 4) {
12048                 if (!dev->mode_config.rotation_property)
12049                         dev->mode_config.rotation_property =
12050                                 drm_mode_create_rotation_property(dev,
12051                                                         BIT(DRM_ROTATE_0) |
12052                                                         BIT(DRM_ROTATE_180));
12053                 if (dev->mode_config.rotation_property)
12054                         drm_object_attach_property(&cursor->base.base,
12055                                 dev->mode_config.rotation_property,
12056                                 cursor->rotation);
12057         }
12058
12059         return &cursor->base;
12060 }
12061
12062 static void intel_crtc_init(struct drm_device *dev, int pipe)
12063 {
12064         struct drm_i915_private *dev_priv = dev->dev_private;
12065         struct intel_crtc *intel_crtc;
12066         struct drm_plane *primary = NULL;
12067         struct drm_plane *cursor = NULL;
12068         int i, ret;
12069
12070         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12071         if (intel_crtc == NULL)
12072                 return;
12073
12074         primary = intel_primary_plane_create(dev, pipe);
12075         if (!primary)
12076                 goto fail;
12077
12078         cursor = intel_cursor_plane_create(dev, pipe);
12079         if (!cursor)
12080                 goto fail;
12081
12082         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12083                                         cursor, &intel_crtc_funcs);
12084         if (ret)
12085                 goto fail;
12086
12087         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12088         for (i = 0; i < 256; i++) {
12089                 intel_crtc->lut_r[i] = i;
12090                 intel_crtc->lut_g[i] = i;
12091                 intel_crtc->lut_b[i] = i;
12092         }
12093
12094         /*
12095          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12096          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12097          */
12098         intel_crtc->pipe = pipe;
12099         intel_crtc->plane = pipe;
12100         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12101                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12102                 intel_crtc->plane = !pipe;
12103         }
12104
12105         intel_crtc->cursor_base = ~0;
12106         intel_crtc->cursor_cntl = ~0;
12107         intel_crtc->cursor_size = ~0;
12108
12109         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12110                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12111         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12112         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12113
12114         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12115
12116         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12117         return;
12118
12119 fail:
12120         if (primary)
12121                 drm_plane_cleanup(primary);
12122         if (cursor)
12123                 drm_plane_cleanup(cursor);
12124         kfree(intel_crtc);
12125 }
12126
12127 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12128 {
12129         struct drm_encoder *encoder = connector->base.encoder;
12130         struct drm_device *dev = connector->base.dev;
12131
12132         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12133
12134         if (!encoder)
12135                 return INVALID_PIPE;
12136
12137         return to_intel_crtc(encoder->crtc)->pipe;
12138 }
12139
12140 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12141                                 struct drm_file *file)
12142 {
12143         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12144         struct drm_crtc *drmmode_crtc;
12145         struct intel_crtc *crtc;
12146
12147         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12148                 return -ENODEV;
12149
12150         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12151
12152         if (!drmmode_crtc) {
12153                 DRM_ERROR("no such CRTC id\n");
12154                 return -ENOENT;
12155         }
12156
12157         crtc = to_intel_crtc(drmmode_crtc);
12158         pipe_from_crtc_id->pipe = crtc->pipe;
12159
12160         return 0;
12161 }
12162
12163 static int intel_encoder_clones(struct intel_encoder *encoder)
12164 {
12165         struct drm_device *dev = encoder->base.dev;
12166         struct intel_encoder *source_encoder;
12167         int index_mask = 0;
12168         int entry = 0;
12169
12170         for_each_intel_encoder(dev, source_encoder) {
12171                 if (encoders_cloneable(encoder, source_encoder))
12172                         index_mask |= (1 << entry);
12173
12174                 entry++;
12175         }
12176
12177         return index_mask;
12178 }
12179
12180 static bool has_edp_a(struct drm_device *dev)
12181 {
12182         struct drm_i915_private *dev_priv = dev->dev_private;
12183
12184         if (!IS_MOBILE(dev))
12185                 return false;
12186
12187         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12188                 return false;
12189
12190         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12191                 return false;
12192
12193         return true;
12194 }
12195
12196 const char *intel_output_name(int output)
12197 {
12198         static const char *names[] = {
12199                 [INTEL_OUTPUT_UNUSED] = "Unused",
12200                 [INTEL_OUTPUT_ANALOG] = "Analog",
12201                 [INTEL_OUTPUT_DVO] = "DVO",
12202                 [INTEL_OUTPUT_SDVO] = "SDVO",
12203                 [INTEL_OUTPUT_LVDS] = "LVDS",
12204                 [INTEL_OUTPUT_TVOUT] = "TV",
12205                 [INTEL_OUTPUT_HDMI] = "HDMI",
12206                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12207                 [INTEL_OUTPUT_EDP] = "eDP",
12208                 [INTEL_OUTPUT_DSI] = "DSI",
12209                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12210         };
12211
12212         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12213                 return "Invalid";
12214
12215         return names[output];
12216 }
12217
12218 static bool intel_crt_present(struct drm_device *dev)
12219 {
12220         struct drm_i915_private *dev_priv = dev->dev_private;
12221
12222         if (INTEL_INFO(dev)->gen >= 9)
12223                 return false;
12224
12225         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12226                 return false;
12227
12228         if (IS_CHERRYVIEW(dev))
12229                 return false;
12230
12231         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12232                 return false;
12233
12234         return true;
12235 }
12236
12237 static void intel_setup_outputs(struct drm_device *dev)
12238 {
12239         struct drm_i915_private *dev_priv = dev->dev_private;
12240         struct intel_encoder *encoder;
12241         bool dpd_is_edp = false;
12242
12243         intel_lvds_init(dev);
12244
12245         if (intel_crt_present(dev))
12246                 intel_crt_init(dev);
12247
12248         if (HAS_DDI(dev)) {
12249                 int found;
12250
12251                 /* Haswell uses DDI functions to detect digital outputs */
12252                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12253                 /* DDI A only supports eDP */
12254                 if (found)
12255                         intel_ddi_init(dev, PORT_A);
12256
12257                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12258                  * register */
12259                 found = I915_READ(SFUSE_STRAP);
12260
12261                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12262                         intel_ddi_init(dev, PORT_B);
12263                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12264                         intel_ddi_init(dev, PORT_C);
12265                 if (found & SFUSE_STRAP_DDID_DETECTED)
12266                         intel_ddi_init(dev, PORT_D);
12267         } else if (HAS_PCH_SPLIT(dev)) {
12268                 int found;
12269                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12270
12271                 if (has_edp_a(dev))
12272                         intel_dp_init(dev, DP_A, PORT_A);
12273
12274                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12275                         /* PCH SDVOB multiplex with HDMIB */
12276                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12277                         if (!found)
12278                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12279                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12280                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12281                 }
12282
12283                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12284                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12285
12286                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12287                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12288
12289                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12290                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12291
12292                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12293                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12294         } else if (IS_VALLEYVIEW(dev)) {
12295                 /*
12296                  * The DP_DETECTED bit is the latched state of the DDC
12297                  * SDA pin at boot. However since eDP doesn't require DDC
12298                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12299                  * eDP ports may have been muxed to an alternate function.
12300                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12301                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12302                  * detect eDP ports.
12303                  */
12304                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12305                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12306                                         PORT_B);
12307                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12308                     intel_dp_is_edp(dev, PORT_B))
12309                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12310
12311                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12312                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12313                                         PORT_C);
12314                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12315                     intel_dp_is_edp(dev, PORT_C))
12316                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12317
12318                 if (IS_CHERRYVIEW(dev)) {
12319                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12320                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12321                                                 PORT_D);
12322                         /* eDP not supported on port D, so don't check VBT */
12323                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12324                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12325                 }
12326
12327                 intel_dsi_init(dev);
12328         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12329                 bool found = false;
12330
12331                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12332                         DRM_DEBUG_KMS("probing SDVOB\n");
12333                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12334                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12335                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12336                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12337                         }
12338
12339                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12340                                 intel_dp_init(dev, DP_B, PORT_B);
12341                 }
12342
12343                 /* Before G4X SDVOC doesn't have its own detect register */
12344
12345                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12346                         DRM_DEBUG_KMS("probing SDVOC\n");
12347                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12348                 }
12349
12350                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12351
12352                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12353                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12354                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12355                         }
12356                         if (SUPPORTS_INTEGRATED_DP(dev))
12357                                 intel_dp_init(dev, DP_C, PORT_C);
12358                 }
12359
12360                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12361                     (I915_READ(DP_D) & DP_DETECTED))
12362                         intel_dp_init(dev, DP_D, PORT_D);
12363         } else if (IS_GEN2(dev))
12364                 intel_dvo_init(dev);
12365
12366         if (SUPPORTS_TV(dev))
12367                 intel_tv_init(dev);
12368
12369         intel_edp_psr_init(dev);
12370
12371         for_each_intel_encoder(dev, encoder) {
12372                 encoder->base.possible_crtcs = encoder->crtc_mask;
12373                 encoder->base.possible_clones =
12374                         intel_encoder_clones(encoder);
12375         }
12376
12377         intel_init_pch_refclk(dev);
12378
12379         drm_helper_move_panel_connectors_to_head(dev);
12380 }
12381
12382 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12383 {
12384         struct drm_device *dev = fb->dev;
12385         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12386
12387         drm_framebuffer_cleanup(fb);
12388         mutex_lock(&dev->struct_mutex);
12389         WARN_ON(!intel_fb->obj->framebuffer_references--);
12390         drm_gem_object_unreference(&intel_fb->obj->base);
12391         mutex_unlock(&dev->struct_mutex);
12392         kfree(intel_fb);
12393 }
12394
12395 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12396                                                 struct drm_file *file,
12397                                                 unsigned int *handle)
12398 {
12399         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12400         struct drm_i915_gem_object *obj = intel_fb->obj;
12401
12402         return drm_gem_handle_create(file, &obj->base, handle);
12403 }
12404
12405 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12406         .destroy = intel_user_framebuffer_destroy,
12407         .create_handle = intel_user_framebuffer_create_handle,
12408 };
12409
12410 static int intel_framebuffer_init(struct drm_device *dev,
12411                                   struct intel_framebuffer *intel_fb,
12412                                   struct drm_mode_fb_cmd2 *mode_cmd,
12413                                   struct drm_i915_gem_object *obj)
12414 {
12415         int aligned_height;
12416         int pitch_limit;
12417         int ret;
12418
12419         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12420
12421         if (obj->tiling_mode == I915_TILING_Y) {
12422                 DRM_DEBUG("hardware does not support tiling Y\n");
12423                 return -EINVAL;
12424         }
12425
12426         if (mode_cmd->pitches[0] & 63) {
12427                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12428                           mode_cmd->pitches[0]);
12429                 return -EINVAL;
12430         }
12431
12432         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12433                 pitch_limit = 32*1024;
12434         } else if (INTEL_INFO(dev)->gen >= 4) {
12435                 if (obj->tiling_mode)
12436                         pitch_limit = 16*1024;
12437                 else
12438                         pitch_limit = 32*1024;
12439         } else if (INTEL_INFO(dev)->gen >= 3) {
12440                 if (obj->tiling_mode)
12441                         pitch_limit = 8*1024;
12442                 else
12443                         pitch_limit = 16*1024;
12444         } else
12445                 /* XXX DSPC is limited to 4k tiled */
12446                 pitch_limit = 8*1024;
12447
12448         if (mode_cmd->pitches[0] > pitch_limit) {
12449                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12450                           obj->tiling_mode ? "tiled" : "linear",
12451                           mode_cmd->pitches[0], pitch_limit);
12452                 return -EINVAL;
12453         }
12454
12455         if (obj->tiling_mode != I915_TILING_NONE &&
12456             mode_cmd->pitches[0] != obj->stride) {
12457                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12458                           mode_cmd->pitches[0], obj->stride);
12459                 return -EINVAL;
12460         }
12461
12462         /* Reject formats not supported by any plane early. */
12463         switch (mode_cmd->pixel_format) {
12464         case DRM_FORMAT_C8:
12465         case DRM_FORMAT_RGB565:
12466         case DRM_FORMAT_XRGB8888:
12467         case DRM_FORMAT_ARGB8888:
12468                 break;
12469         case DRM_FORMAT_XRGB1555:
12470         case DRM_FORMAT_ARGB1555:
12471                 if (INTEL_INFO(dev)->gen > 3) {
12472                         DRM_DEBUG("unsupported pixel format: %s\n",
12473                                   drm_get_format_name(mode_cmd->pixel_format));
12474                         return -EINVAL;
12475                 }
12476                 break;
12477         case DRM_FORMAT_XBGR8888:
12478         case DRM_FORMAT_ABGR8888:
12479         case DRM_FORMAT_XRGB2101010:
12480         case DRM_FORMAT_ARGB2101010:
12481         case DRM_FORMAT_XBGR2101010:
12482         case DRM_FORMAT_ABGR2101010:
12483                 if (INTEL_INFO(dev)->gen < 4) {
12484                         DRM_DEBUG("unsupported pixel format: %s\n",
12485                                   drm_get_format_name(mode_cmd->pixel_format));
12486                         return -EINVAL;
12487                 }
12488                 break;
12489         case DRM_FORMAT_YUYV:
12490         case DRM_FORMAT_UYVY:
12491         case DRM_FORMAT_YVYU:
12492         case DRM_FORMAT_VYUY:
12493                 if (INTEL_INFO(dev)->gen < 5) {
12494                         DRM_DEBUG("unsupported pixel format: %s\n",
12495                                   drm_get_format_name(mode_cmd->pixel_format));
12496                         return -EINVAL;
12497                 }
12498                 break;
12499         default:
12500                 DRM_DEBUG("unsupported pixel format: %s\n",
12501                           drm_get_format_name(mode_cmd->pixel_format));
12502                 return -EINVAL;
12503         }
12504
12505         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12506         if (mode_cmd->offsets[0] != 0)
12507                 return -EINVAL;
12508
12509         aligned_height = intel_align_height(dev, mode_cmd->height,
12510                                             obj->tiling_mode);
12511         /* FIXME drm helper for size checks (especially planar formats)? */
12512         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12513                 return -EINVAL;
12514
12515         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12516         intel_fb->obj = obj;
12517         intel_fb->obj->framebuffer_references++;
12518
12519         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12520         if (ret) {
12521                 DRM_ERROR("framebuffer init failed %d\n", ret);
12522                 return ret;
12523         }
12524
12525         return 0;
12526 }
12527
12528 static struct drm_framebuffer *
12529 intel_user_framebuffer_create(struct drm_device *dev,
12530                               struct drm_file *filp,
12531                               struct drm_mode_fb_cmd2 *mode_cmd)
12532 {
12533         struct drm_i915_gem_object *obj;
12534
12535         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12536                                                 mode_cmd->handles[0]));
12537         if (&obj->base == NULL)
12538                 return ERR_PTR(-ENOENT);
12539
12540         return intel_framebuffer_create(dev, mode_cmd, obj);
12541 }
12542
12543 #ifndef CONFIG_DRM_I915_FBDEV
12544 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12545 {
12546 }
12547 #endif
12548
12549 static const struct drm_mode_config_funcs intel_mode_funcs = {
12550         .fb_create = intel_user_framebuffer_create,
12551         .output_poll_changed = intel_fbdev_output_poll_changed,
12552 };
12553
12554 /* Set up chip specific display functions */
12555 static void intel_init_display(struct drm_device *dev)
12556 {
12557         struct drm_i915_private *dev_priv = dev->dev_private;
12558
12559         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12560                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12561         else if (IS_CHERRYVIEW(dev))
12562                 dev_priv->display.find_dpll = chv_find_best_dpll;
12563         else if (IS_VALLEYVIEW(dev))
12564                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12565         else if (IS_PINEVIEW(dev))
12566                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12567         else
12568                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12569
12570         if (HAS_DDI(dev)) {
12571                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12572                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12573                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12574                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12575                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12576                 dev_priv->display.off = ironlake_crtc_off;
12577                 if (INTEL_INFO(dev)->gen >= 9)
12578                         dev_priv->display.update_primary_plane =
12579                                 skylake_update_primary_plane;
12580                 else
12581                         dev_priv->display.update_primary_plane =
12582                                 ironlake_update_primary_plane;
12583         } else if (HAS_PCH_SPLIT(dev)) {
12584                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12585                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12586                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12587                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12588                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12589                 dev_priv->display.off = ironlake_crtc_off;
12590                 dev_priv->display.update_primary_plane =
12591                         ironlake_update_primary_plane;
12592         } else if (IS_VALLEYVIEW(dev)) {
12593                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12594                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12595                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12596                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12597                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12598                 dev_priv->display.off = i9xx_crtc_off;
12599                 dev_priv->display.update_primary_plane =
12600                         i9xx_update_primary_plane;
12601         } else {
12602                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12603                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12604                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12605                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12606                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12607                 dev_priv->display.off = i9xx_crtc_off;
12608                 dev_priv->display.update_primary_plane =
12609                         i9xx_update_primary_plane;
12610         }
12611
12612         /* Returns the core display clock speed */
12613         if (IS_VALLEYVIEW(dev))
12614                 dev_priv->display.get_display_clock_speed =
12615                         valleyview_get_display_clock_speed;
12616         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12617                 dev_priv->display.get_display_clock_speed =
12618                         i945_get_display_clock_speed;
12619         else if (IS_I915G(dev))
12620                 dev_priv->display.get_display_clock_speed =
12621                         i915_get_display_clock_speed;
12622         else if (IS_I945GM(dev) || IS_845G(dev))
12623                 dev_priv->display.get_display_clock_speed =
12624                         i9xx_misc_get_display_clock_speed;
12625         else if (IS_PINEVIEW(dev))
12626                 dev_priv->display.get_display_clock_speed =
12627                         pnv_get_display_clock_speed;
12628         else if (IS_I915GM(dev))
12629                 dev_priv->display.get_display_clock_speed =
12630                         i915gm_get_display_clock_speed;
12631         else if (IS_I865G(dev))
12632                 dev_priv->display.get_display_clock_speed =
12633                         i865_get_display_clock_speed;
12634         else if (IS_I85X(dev))
12635                 dev_priv->display.get_display_clock_speed =
12636                         i855_get_display_clock_speed;
12637         else /* 852, 830 */
12638                 dev_priv->display.get_display_clock_speed =
12639                         i830_get_display_clock_speed;
12640
12641         if (IS_G4X(dev)) {
12642                 dev_priv->display.write_eld = g4x_write_eld;
12643         } else if (IS_GEN5(dev)) {
12644                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12645                 dev_priv->display.write_eld = ironlake_write_eld;
12646         } else if (IS_GEN6(dev)) {
12647                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12648                 dev_priv->display.write_eld = ironlake_write_eld;
12649                 dev_priv->display.modeset_global_resources =
12650                         snb_modeset_global_resources;
12651         } else if (IS_IVYBRIDGE(dev)) {
12652                 /* FIXME: detect B0+ stepping and use auto training */
12653                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12654                 dev_priv->display.write_eld = ironlake_write_eld;
12655                 dev_priv->display.modeset_global_resources =
12656                         ivb_modeset_global_resources;
12657         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12658                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12659                 dev_priv->display.write_eld = haswell_write_eld;
12660                 dev_priv->display.modeset_global_resources =
12661                         haswell_modeset_global_resources;
12662         } else if (IS_VALLEYVIEW(dev)) {
12663                 dev_priv->display.modeset_global_resources =
12664                         valleyview_modeset_global_resources;
12665                 dev_priv->display.write_eld = ironlake_write_eld;
12666         } else if (INTEL_INFO(dev)->gen >= 9) {
12667                 dev_priv->display.write_eld = haswell_write_eld;
12668                 dev_priv->display.modeset_global_resources =
12669                         haswell_modeset_global_resources;
12670         }
12671
12672         /* Default just returns -ENODEV to indicate unsupported */
12673         dev_priv->display.queue_flip = intel_default_queue_flip;
12674
12675         switch (INTEL_INFO(dev)->gen) {
12676         case 2:
12677                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12678                 break;
12679
12680         case 3:
12681                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12682                 break;
12683
12684         case 4:
12685         case 5:
12686                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12687                 break;
12688
12689         case 6:
12690                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12691                 break;
12692         case 7:
12693         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12694                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12695                 break;
12696         }
12697
12698         intel_panel_init_backlight_funcs(dev);
12699
12700         mutex_init(&dev_priv->pps_mutex);
12701 }
12702
12703 /*
12704  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12705  * resume, or other times.  This quirk makes sure that's the case for
12706  * affected systems.
12707  */
12708 static void quirk_pipea_force(struct drm_device *dev)
12709 {
12710         struct drm_i915_private *dev_priv = dev->dev_private;
12711
12712         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12713         DRM_INFO("applying pipe a force quirk\n");
12714 }
12715
12716 static void quirk_pipeb_force(struct drm_device *dev)
12717 {
12718         struct drm_i915_private *dev_priv = dev->dev_private;
12719
12720         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12721         DRM_INFO("applying pipe b force quirk\n");
12722 }
12723
12724 /*
12725  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12726  */
12727 static void quirk_ssc_force_disable(struct drm_device *dev)
12728 {
12729         struct drm_i915_private *dev_priv = dev->dev_private;
12730         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12731         DRM_INFO("applying lvds SSC disable quirk\n");
12732 }
12733
12734 /*
12735  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12736  * brightness value
12737  */
12738 static void quirk_invert_brightness(struct drm_device *dev)
12739 {
12740         struct drm_i915_private *dev_priv = dev->dev_private;
12741         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12742         DRM_INFO("applying inverted panel brightness quirk\n");
12743 }
12744
12745 /* Some VBT's incorrectly indicate no backlight is present */
12746 static void quirk_backlight_present(struct drm_device *dev)
12747 {
12748         struct drm_i915_private *dev_priv = dev->dev_private;
12749         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12750         DRM_INFO("applying backlight present quirk\n");
12751 }
12752
12753 struct intel_quirk {
12754         int device;
12755         int subsystem_vendor;
12756         int subsystem_device;
12757         void (*hook)(struct drm_device *dev);
12758 };
12759
12760 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12761 struct intel_dmi_quirk {
12762         void (*hook)(struct drm_device *dev);
12763         const struct dmi_system_id (*dmi_id_list)[];
12764 };
12765
12766 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12767 {
12768         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12769         return 1;
12770 }
12771
12772 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12773         {
12774                 .dmi_id_list = &(const struct dmi_system_id[]) {
12775                         {
12776                                 .callback = intel_dmi_reverse_brightness,
12777                                 .ident = "NCR Corporation",
12778                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12779                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12780                                 },
12781                         },
12782                         { }  /* terminating entry */
12783                 },
12784                 .hook = quirk_invert_brightness,
12785         },
12786 };
12787
12788 static struct intel_quirk intel_quirks[] = {
12789         /* HP Mini needs pipe A force quirk (LP: #322104) */
12790         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12791
12792         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12793         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12794
12795         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12796         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12797
12798         /* 830 needs to leave pipe A & dpll A up */
12799         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12800
12801         /* 830 needs to leave pipe B & dpll B up */
12802         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12803
12804         /* Lenovo U160 cannot use SSC on LVDS */
12805         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12806
12807         /* Sony Vaio Y cannot use SSC on LVDS */
12808         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12809
12810         /* Acer Aspire 5734Z must invert backlight brightness */
12811         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12812
12813         /* Acer/eMachines G725 */
12814         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12815
12816         /* Acer/eMachines e725 */
12817         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12818
12819         /* Acer/Packard Bell NCL20 */
12820         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12821
12822         /* Acer Aspire 4736Z */
12823         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12824
12825         /* Acer Aspire 5336 */
12826         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12827
12828         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12829         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12830
12831         /* Acer C720 Chromebook (Core i3 4005U) */
12832         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12833
12834         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12835         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12836
12837         /* HP Chromebook 14 (Celeron 2955U) */
12838         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12839 };
12840
12841 static void intel_init_quirks(struct drm_device *dev)
12842 {
12843         struct pci_dev *d = dev->pdev;
12844         int i;
12845
12846         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12847                 struct intel_quirk *q = &intel_quirks[i];
12848
12849                 if (d->device == q->device &&
12850                     (d->subsystem_vendor == q->subsystem_vendor ||
12851                      q->subsystem_vendor == PCI_ANY_ID) &&
12852                     (d->subsystem_device == q->subsystem_device ||
12853                      q->subsystem_device == PCI_ANY_ID))
12854                         q->hook(dev);
12855         }
12856         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12857                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12858                         intel_dmi_quirks[i].hook(dev);
12859         }
12860 }
12861
12862 /* Disable the VGA plane that we never use */
12863 static void i915_disable_vga(struct drm_device *dev)
12864 {
12865         struct drm_i915_private *dev_priv = dev->dev_private;
12866         u8 sr1;
12867         u32 vga_reg = i915_vgacntrl_reg(dev);
12868
12869         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12870         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12871         outb(SR01, VGA_SR_INDEX);
12872         sr1 = inb(VGA_SR_DATA);
12873         outb(sr1 | 1<<5, VGA_SR_DATA);
12874         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12875         udelay(300);
12876
12877         /*
12878          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12879          * from S3 without preserving (some of?) the other bits.
12880          */
12881         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12882         POSTING_READ(vga_reg);
12883 }
12884
12885 void intel_modeset_init_hw(struct drm_device *dev)
12886 {
12887         intel_prepare_ddi(dev);
12888
12889         if (IS_VALLEYVIEW(dev))
12890                 vlv_update_cdclk(dev);
12891
12892         intel_init_clock_gating(dev);
12893
12894         intel_enable_gt_powersave(dev);
12895 }
12896
12897 void intel_modeset_init(struct drm_device *dev)
12898 {
12899         struct drm_i915_private *dev_priv = dev->dev_private;
12900         int sprite, ret;
12901         enum pipe pipe;
12902         struct intel_crtc *crtc;
12903
12904         drm_mode_config_init(dev);
12905
12906         dev->mode_config.min_width = 0;
12907         dev->mode_config.min_height = 0;
12908
12909         dev->mode_config.preferred_depth = 24;
12910         dev->mode_config.prefer_shadow = 1;
12911
12912         dev->mode_config.funcs = &intel_mode_funcs;
12913
12914         intel_init_quirks(dev);
12915
12916         intel_init_pm(dev);
12917
12918         if (INTEL_INFO(dev)->num_pipes == 0)
12919                 return;
12920
12921         intel_init_display(dev);
12922
12923         if (IS_GEN2(dev)) {
12924                 dev->mode_config.max_width = 2048;
12925                 dev->mode_config.max_height = 2048;
12926         } else if (IS_GEN3(dev)) {
12927                 dev->mode_config.max_width = 4096;
12928                 dev->mode_config.max_height = 4096;
12929         } else {
12930                 dev->mode_config.max_width = 8192;
12931                 dev->mode_config.max_height = 8192;
12932         }
12933
12934         if (IS_845G(dev) || IS_I865G(dev)) {
12935                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12936                 dev->mode_config.cursor_height = 1023;
12937         } else if (IS_GEN2(dev)) {
12938                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12939                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12940         } else {
12941                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12942                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12943         }
12944
12945         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12946
12947         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12948                       INTEL_INFO(dev)->num_pipes,
12949                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12950
12951         for_each_pipe(dev_priv, pipe) {
12952                 intel_crtc_init(dev, pipe);
12953                 for_each_sprite(pipe, sprite) {
12954                         ret = intel_plane_init(dev, pipe, sprite);
12955                         if (ret)
12956                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12957                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12958                 }
12959         }
12960
12961         intel_init_dpio(dev);
12962
12963         intel_shared_dpll_init(dev);
12964
12965         /* save the BIOS value before clobbering it */
12966         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12967         /* Just disable it once at startup */
12968         i915_disable_vga(dev);
12969         intel_setup_outputs(dev);
12970
12971         /* Just in case the BIOS is doing something questionable. */
12972         intel_disable_fbc(dev);
12973
12974         drm_modeset_lock_all(dev);
12975         intel_modeset_setup_hw_state(dev, false);
12976         drm_modeset_unlock_all(dev);
12977
12978         for_each_intel_crtc(dev, crtc) {
12979                 if (!crtc->active)
12980                         continue;
12981
12982                 /*
12983                  * Note that reserving the BIOS fb up front prevents us
12984                  * from stuffing other stolen allocations like the ring
12985                  * on top.  This prevents some ugliness at boot time, and
12986                  * can even allow for smooth boot transitions if the BIOS
12987                  * fb is large enough for the active pipe configuration.
12988                  */
12989                 if (dev_priv->display.get_plane_config) {
12990                         dev_priv->display.get_plane_config(crtc,
12991                                                            &crtc->plane_config);
12992                         /*
12993                          * If the fb is shared between multiple heads, we'll
12994                          * just get the first one.
12995                          */
12996                         intel_find_plane_obj(crtc, &crtc->plane_config);
12997                 }
12998         }
12999 }
13000
13001 static void intel_enable_pipe_a(struct drm_device *dev)
13002 {
13003         struct intel_connector *connector;
13004         struct drm_connector *crt = NULL;
13005         struct intel_load_detect_pipe load_detect_temp;
13006         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13007
13008         /* We can't just switch on the pipe A, we need to set things up with a
13009          * proper mode and output configuration. As a gross hack, enable pipe A
13010          * by enabling the load detect pipe once. */
13011         list_for_each_entry(connector,
13012                             &dev->mode_config.connector_list,
13013                             base.head) {
13014                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13015                         crt = &connector->base;
13016                         break;
13017                 }
13018         }
13019
13020         if (!crt)
13021                 return;
13022
13023         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13024                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13025 }
13026
13027 static bool
13028 intel_check_plane_mapping(struct intel_crtc *crtc)
13029 {
13030         struct drm_device *dev = crtc->base.dev;
13031         struct drm_i915_private *dev_priv = dev->dev_private;
13032         u32 reg, val;
13033
13034         if (INTEL_INFO(dev)->num_pipes == 1)
13035                 return true;
13036
13037         reg = DSPCNTR(!crtc->plane);
13038         val = I915_READ(reg);
13039
13040         if ((val & DISPLAY_PLANE_ENABLE) &&
13041             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13042                 return false;
13043
13044         return true;
13045 }
13046
13047 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13048 {
13049         struct drm_device *dev = crtc->base.dev;
13050         struct drm_i915_private *dev_priv = dev->dev_private;
13051         u32 reg;
13052
13053         /* Clear any frame start delays used for debugging left by the BIOS */
13054         reg = PIPECONF(crtc->config.cpu_transcoder);
13055         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13056
13057         /* restore vblank interrupts to correct state */
13058         if (crtc->active) {
13059                 update_scanline_offset(crtc);
13060                 drm_vblank_on(dev, crtc->pipe);
13061         } else
13062                 drm_vblank_off(dev, crtc->pipe);
13063
13064         /* We need to sanitize the plane -> pipe mapping first because this will
13065          * disable the crtc (and hence change the state) if it is wrong. Note
13066          * that gen4+ has a fixed plane -> pipe mapping.  */
13067         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13068                 struct intel_connector *connector;
13069                 bool plane;
13070
13071                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13072                               crtc->base.base.id);
13073
13074                 /* Pipe has the wrong plane attached and the plane is active.
13075                  * Temporarily change the plane mapping and disable everything
13076                  * ...  */
13077                 plane = crtc->plane;
13078                 crtc->plane = !plane;
13079                 crtc->primary_enabled = true;
13080                 dev_priv->display.crtc_disable(&crtc->base);
13081                 crtc->plane = plane;
13082
13083                 /* ... and break all links. */
13084                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13085                                     base.head) {
13086                         if (connector->encoder->base.crtc != &crtc->base)
13087                                 continue;
13088
13089                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13090                         connector->base.encoder = NULL;
13091                 }
13092                 /* multiple connectors may have the same encoder:
13093                  *  handle them and break crtc link separately */
13094                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13095                                     base.head)
13096                         if (connector->encoder->base.crtc == &crtc->base) {
13097                                 connector->encoder->base.crtc = NULL;
13098                                 connector->encoder->connectors_active = false;
13099                         }
13100
13101                 WARN_ON(crtc->active);
13102                 crtc->base.enabled = false;
13103         }
13104
13105         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13106             crtc->pipe == PIPE_A && !crtc->active) {
13107                 /* BIOS forgot to enable pipe A, this mostly happens after
13108                  * resume. Force-enable the pipe to fix this, the update_dpms
13109                  * call below we restore the pipe to the right state, but leave
13110                  * the required bits on. */
13111                 intel_enable_pipe_a(dev);
13112         }
13113
13114         /* Adjust the state of the output pipe according to whether we
13115          * have active connectors/encoders. */
13116         intel_crtc_update_dpms(&crtc->base);
13117
13118         if (crtc->active != crtc->base.enabled) {
13119                 struct intel_encoder *encoder;
13120
13121                 /* This can happen either due to bugs in the get_hw_state
13122                  * functions or because the pipe is force-enabled due to the
13123                  * pipe A quirk. */
13124                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13125                               crtc->base.base.id,
13126                               crtc->base.enabled ? "enabled" : "disabled",
13127                               crtc->active ? "enabled" : "disabled");
13128
13129                 crtc->base.enabled = crtc->active;
13130
13131                 /* Because we only establish the connector -> encoder ->
13132                  * crtc links if something is active, this means the
13133                  * crtc is now deactivated. Break the links. connector
13134                  * -> encoder links are only establish when things are
13135                  *  actually up, hence no need to break them. */
13136                 WARN_ON(crtc->active);
13137
13138                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13139                         WARN_ON(encoder->connectors_active);
13140                         encoder->base.crtc = NULL;
13141                 }
13142         }
13143
13144         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13145                 /*
13146                  * We start out with underrun reporting disabled to avoid races.
13147                  * For correct bookkeeping mark this on active crtcs.
13148                  *
13149                  * Also on gmch platforms we dont have any hardware bits to
13150                  * disable the underrun reporting. Which means we need to start
13151                  * out with underrun reporting disabled also on inactive pipes,
13152                  * since otherwise we'll complain about the garbage we read when
13153                  * e.g. coming up after runtime pm.
13154                  *
13155                  * No protection against concurrent access is required - at
13156                  * worst a fifo underrun happens which also sets this to false.
13157                  */
13158                 crtc->cpu_fifo_underrun_disabled = true;
13159                 crtc->pch_fifo_underrun_disabled = true;
13160         }
13161 }
13162
13163 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13164 {
13165         struct intel_connector *connector;
13166         struct drm_device *dev = encoder->base.dev;
13167
13168         /* We need to check both for a crtc link (meaning that the
13169          * encoder is active and trying to read from a pipe) and the
13170          * pipe itself being active. */
13171         bool has_active_crtc = encoder->base.crtc &&
13172                 to_intel_crtc(encoder->base.crtc)->active;
13173
13174         if (encoder->connectors_active && !has_active_crtc) {
13175                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13176                               encoder->base.base.id,
13177                               encoder->base.name);
13178
13179                 /* Connector is active, but has no active pipe. This is
13180                  * fallout from our resume register restoring. Disable
13181                  * the encoder manually again. */
13182                 if (encoder->base.crtc) {
13183                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13184                                       encoder->base.base.id,
13185                                       encoder->base.name);
13186                         encoder->disable(encoder);
13187                         if (encoder->post_disable)
13188                                 encoder->post_disable(encoder);
13189                 }
13190                 encoder->base.crtc = NULL;
13191                 encoder->connectors_active = false;
13192
13193                 /* Inconsistent output/port/pipe state happens presumably due to
13194                  * a bug in one of the get_hw_state functions. Or someplace else
13195                  * in our code, like the register restore mess on resume. Clamp
13196                  * things to off as a safer default. */
13197                 list_for_each_entry(connector,
13198                                     &dev->mode_config.connector_list,
13199                                     base.head) {
13200                         if (connector->encoder != encoder)
13201                                 continue;
13202                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13203                         connector->base.encoder = NULL;
13204                 }
13205         }
13206         /* Enabled encoders without active connectors will be fixed in
13207          * the crtc fixup. */
13208 }
13209
13210 void i915_redisable_vga_power_on(struct drm_device *dev)
13211 {
13212         struct drm_i915_private *dev_priv = dev->dev_private;
13213         u32 vga_reg = i915_vgacntrl_reg(dev);
13214
13215         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13216                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13217                 i915_disable_vga(dev);
13218         }
13219 }
13220
13221 void i915_redisable_vga(struct drm_device *dev)
13222 {
13223         struct drm_i915_private *dev_priv = dev->dev_private;
13224
13225         /* This function can be called both from intel_modeset_setup_hw_state or
13226          * at a very early point in our resume sequence, where the power well
13227          * structures are not yet restored. Since this function is at a very
13228          * paranoid "someone might have enabled VGA while we were not looking"
13229          * level, just check if the power well is enabled instead of trying to
13230          * follow the "don't touch the power well if we don't need it" policy
13231          * the rest of the driver uses. */
13232         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13233                 return;
13234
13235         i915_redisable_vga_power_on(dev);
13236 }
13237
13238 static bool primary_get_hw_state(struct intel_crtc *crtc)
13239 {
13240         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13241
13242         if (!crtc->active)
13243                 return false;
13244
13245         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13246 }
13247
13248 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13249 {
13250         struct drm_i915_private *dev_priv = dev->dev_private;
13251         enum pipe pipe;
13252         struct intel_crtc *crtc;
13253         struct intel_encoder *encoder;
13254         struct intel_connector *connector;
13255         int i;
13256
13257         for_each_intel_crtc(dev, crtc) {
13258                 memset(&crtc->config, 0, sizeof(crtc->config));
13259
13260                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13261
13262                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13263                                                                  &crtc->config);
13264
13265                 crtc->base.enabled = crtc->active;
13266                 crtc->primary_enabled = primary_get_hw_state(crtc);
13267
13268                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13269                               crtc->base.base.id,
13270                               crtc->active ? "enabled" : "disabled");
13271         }
13272
13273         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13274                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13275
13276                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13277                 pll->active = 0;
13278                 for_each_intel_crtc(dev, crtc) {
13279                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13280                                 pll->active++;
13281                 }
13282                 pll->refcount = pll->active;
13283
13284                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13285                               pll->name, pll->refcount, pll->on);
13286
13287                 if (pll->refcount)
13288                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13289         }
13290
13291         for_each_intel_encoder(dev, encoder) {
13292                 pipe = 0;
13293
13294                 if (encoder->get_hw_state(encoder, &pipe)) {
13295                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13296                         encoder->base.crtc = &crtc->base;
13297                         encoder->get_config(encoder, &crtc->config);
13298                 } else {
13299                         encoder->base.crtc = NULL;
13300                 }
13301
13302                 encoder->connectors_active = false;
13303                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13304                               encoder->base.base.id,
13305                               encoder->base.name,
13306                               encoder->base.crtc ? "enabled" : "disabled",
13307                               pipe_name(pipe));
13308         }
13309
13310         list_for_each_entry(connector, &dev->mode_config.connector_list,
13311                             base.head) {
13312                 if (connector->get_hw_state(connector)) {
13313                         connector->base.dpms = DRM_MODE_DPMS_ON;
13314                         connector->encoder->connectors_active = true;
13315                         connector->base.encoder = &connector->encoder->base;
13316                 } else {
13317                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13318                         connector->base.encoder = NULL;
13319                 }
13320                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13321                               connector->base.base.id,
13322                               connector->base.name,
13323                               connector->base.encoder ? "enabled" : "disabled");
13324         }
13325 }
13326
13327 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13328  * and i915 state tracking structures. */
13329 void intel_modeset_setup_hw_state(struct drm_device *dev,
13330                                   bool force_restore)
13331 {
13332         struct drm_i915_private *dev_priv = dev->dev_private;
13333         enum pipe pipe;
13334         struct intel_crtc *crtc;
13335         struct intel_encoder *encoder;
13336         int i;
13337
13338         intel_modeset_readout_hw_state(dev);
13339
13340         /*
13341          * Now that we have the config, copy it to each CRTC struct
13342          * Note that this could go away if we move to using crtc_config
13343          * checking everywhere.
13344          */
13345         for_each_intel_crtc(dev, crtc) {
13346                 if (crtc->active && i915.fastboot) {
13347                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13348                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13349                                       crtc->base.base.id);
13350                         drm_mode_debug_printmodeline(&crtc->base.mode);
13351                 }
13352         }
13353
13354         /* HW state is read out, now we need to sanitize this mess. */
13355         for_each_intel_encoder(dev, encoder) {
13356                 intel_sanitize_encoder(encoder);
13357         }
13358
13359         for_each_pipe(dev_priv, pipe) {
13360                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13361                 intel_sanitize_crtc(crtc);
13362                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13363         }
13364
13365         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13366                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13367
13368                 if (!pll->on || pll->active)
13369                         continue;
13370
13371                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13372
13373                 pll->disable(dev_priv, pll);
13374                 pll->on = false;
13375         }
13376
13377         if (HAS_PCH_SPLIT(dev))
13378                 ilk_wm_get_hw_state(dev);
13379
13380         if (force_restore) {
13381                 i915_redisable_vga(dev);
13382
13383                 /*
13384                  * We need to use raw interfaces for restoring state to avoid
13385                  * checking (bogus) intermediate states.
13386                  */
13387                 for_each_pipe(dev_priv, pipe) {
13388                         struct drm_crtc *crtc =
13389                                 dev_priv->pipe_to_crtc_mapping[pipe];
13390
13391                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13392                                          crtc->primary->fb);
13393                 }
13394         } else {
13395                 intel_modeset_update_staged_output_state(dev);
13396         }
13397
13398         intel_modeset_check_state(dev);
13399 }
13400
13401 void intel_modeset_gem_init(struct drm_device *dev)
13402 {
13403         struct drm_crtc *c;
13404         struct drm_i915_gem_object *obj;
13405
13406         mutex_lock(&dev->struct_mutex);
13407         intel_init_gt_powersave(dev);
13408         mutex_unlock(&dev->struct_mutex);
13409
13410         intel_modeset_init_hw(dev);
13411
13412         intel_setup_overlay(dev);
13413
13414         /*
13415          * Make sure any fbs we allocated at startup are properly
13416          * pinned & fenced.  When we do the allocation it's too early
13417          * for this.
13418          */
13419         mutex_lock(&dev->struct_mutex);
13420         for_each_crtc(dev, c) {
13421                 obj = intel_fb_obj(c->primary->fb);
13422                 if (obj == NULL)
13423                         continue;
13424
13425                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13426                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13427                                   to_intel_crtc(c)->pipe);
13428                         drm_framebuffer_unreference(c->primary->fb);
13429                         c->primary->fb = NULL;
13430                 }
13431         }
13432         mutex_unlock(&dev->struct_mutex);
13433 }
13434
13435 void intel_connector_unregister(struct intel_connector *intel_connector)
13436 {
13437         struct drm_connector *connector = &intel_connector->base;
13438
13439         intel_panel_destroy_backlight(connector);
13440         drm_connector_unregister(connector);
13441 }
13442
13443 void intel_modeset_cleanup(struct drm_device *dev)
13444 {
13445         struct drm_i915_private *dev_priv = dev->dev_private;
13446         struct drm_connector *connector;
13447
13448         /*
13449          * Interrupts and polling as the first thing to avoid creating havoc.
13450          * Too much stuff here (turning of rps, connectors, ...) would
13451          * experience fancy races otherwise.
13452          */
13453         intel_irq_uninstall(dev_priv);
13454
13455         /*
13456          * Due to the hpd irq storm handling the hotplug work can re-arm the
13457          * poll handlers. Hence disable polling after hpd handling is shut down.
13458          */
13459         drm_kms_helper_poll_fini(dev);
13460
13461         mutex_lock(&dev->struct_mutex);
13462
13463         intel_unregister_dsm_handler();
13464
13465         intel_disable_fbc(dev);
13466
13467         intel_disable_gt_powersave(dev);
13468
13469         ironlake_teardown_rc6(dev);
13470
13471         mutex_unlock(&dev->struct_mutex);
13472
13473         /* flush any delayed tasks or pending work */
13474         flush_scheduled_work();
13475
13476         /* destroy the backlight and sysfs files before encoders/connectors */
13477         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13478                 struct intel_connector *intel_connector;
13479
13480                 intel_connector = to_intel_connector(connector);
13481                 intel_connector->unregister(intel_connector);
13482         }
13483
13484         drm_mode_config_cleanup(dev);
13485
13486         intel_cleanup_overlay(dev);
13487
13488         mutex_lock(&dev->struct_mutex);
13489         intel_cleanup_gt_powersave(dev);
13490         mutex_unlock(&dev->struct_mutex);
13491 }
13492
13493 /*
13494  * Return which encoder is currently attached for connector.
13495  */
13496 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13497 {
13498         return &intel_attached_encoder(connector)->base;
13499 }
13500
13501 void intel_connector_attach_encoder(struct intel_connector *connector,
13502                                     struct intel_encoder *encoder)
13503 {
13504         connector->encoder = encoder;
13505         drm_mode_connector_attach_encoder(&connector->base,
13506                                           &encoder->base);
13507 }
13508
13509 /*
13510  * set vga decode state - true == enable VGA decode
13511  */
13512 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13513 {
13514         struct drm_i915_private *dev_priv = dev->dev_private;
13515         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13516         u16 gmch_ctrl;
13517
13518         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13519                 DRM_ERROR("failed to read control word\n");
13520                 return -EIO;
13521         }
13522
13523         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13524                 return 0;
13525
13526         if (state)
13527                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13528         else
13529                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13530
13531         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13532                 DRM_ERROR("failed to write control word\n");
13533                 return -EIO;
13534         }
13535
13536         return 0;
13537 }
13538
13539 struct intel_display_error_state {
13540
13541         u32 power_well_driver;
13542
13543         int num_transcoders;
13544
13545         struct intel_cursor_error_state {
13546                 u32 control;
13547                 u32 position;
13548                 u32 base;
13549                 u32 size;
13550         } cursor[I915_MAX_PIPES];
13551
13552         struct intel_pipe_error_state {
13553                 bool power_domain_on;
13554                 u32 source;
13555                 u32 stat;
13556         } pipe[I915_MAX_PIPES];
13557
13558         struct intel_plane_error_state {
13559                 u32 control;
13560                 u32 stride;
13561                 u32 size;
13562                 u32 pos;
13563                 u32 addr;
13564                 u32 surface;
13565                 u32 tile_offset;
13566         } plane[I915_MAX_PIPES];
13567
13568         struct intel_transcoder_error_state {
13569                 bool power_domain_on;
13570                 enum transcoder cpu_transcoder;
13571
13572                 u32 conf;
13573
13574                 u32 htotal;
13575                 u32 hblank;
13576                 u32 hsync;
13577                 u32 vtotal;
13578                 u32 vblank;
13579                 u32 vsync;
13580         } transcoder[4];
13581 };
13582
13583 struct intel_display_error_state *
13584 intel_display_capture_error_state(struct drm_device *dev)
13585 {
13586         struct drm_i915_private *dev_priv = dev->dev_private;
13587         struct intel_display_error_state *error;
13588         int transcoders[] = {
13589                 TRANSCODER_A,
13590                 TRANSCODER_B,
13591                 TRANSCODER_C,
13592                 TRANSCODER_EDP,
13593         };
13594         int i;
13595
13596         if (INTEL_INFO(dev)->num_pipes == 0)
13597                 return NULL;
13598
13599         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13600         if (error == NULL)
13601                 return NULL;
13602
13603         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13604                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13605
13606         for_each_pipe(dev_priv, i) {
13607                 error->pipe[i].power_domain_on =
13608                         __intel_display_power_is_enabled(dev_priv,
13609                                                          POWER_DOMAIN_PIPE(i));
13610                 if (!error->pipe[i].power_domain_on)
13611                         continue;
13612
13613                 error->cursor[i].control = I915_READ(CURCNTR(i));
13614                 error->cursor[i].position = I915_READ(CURPOS(i));
13615                 error->cursor[i].base = I915_READ(CURBASE(i));
13616
13617                 error->plane[i].control = I915_READ(DSPCNTR(i));
13618                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13619                 if (INTEL_INFO(dev)->gen <= 3) {
13620                         error->plane[i].size = I915_READ(DSPSIZE(i));
13621                         error->plane[i].pos = I915_READ(DSPPOS(i));
13622                 }
13623                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13624                         error->plane[i].addr = I915_READ(DSPADDR(i));
13625                 if (INTEL_INFO(dev)->gen >= 4) {
13626                         error->plane[i].surface = I915_READ(DSPSURF(i));
13627                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13628                 }
13629
13630                 error->pipe[i].source = I915_READ(PIPESRC(i));
13631
13632                 if (HAS_GMCH_DISPLAY(dev))
13633                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13634         }
13635
13636         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13637         if (HAS_DDI(dev_priv->dev))
13638                 error->num_transcoders++; /* Account for eDP. */
13639
13640         for (i = 0; i < error->num_transcoders; i++) {
13641                 enum transcoder cpu_transcoder = transcoders[i];
13642
13643                 error->transcoder[i].power_domain_on =
13644                         __intel_display_power_is_enabled(dev_priv,
13645                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13646                 if (!error->transcoder[i].power_domain_on)
13647                         continue;
13648
13649                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13650
13651                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13652                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13653                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13654                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13655                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13656                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13657                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13658         }
13659
13660         return error;
13661 }
13662
13663 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13664
13665 void
13666 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13667                                 struct drm_device *dev,
13668                                 struct intel_display_error_state *error)
13669 {
13670         struct drm_i915_private *dev_priv = dev->dev_private;
13671         int i;
13672
13673         if (!error)
13674                 return;
13675
13676         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13677         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13678                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13679                            error->power_well_driver);
13680         for_each_pipe(dev_priv, i) {
13681                 err_printf(m, "Pipe [%d]:\n", i);
13682                 err_printf(m, "  Power: %s\n",
13683                            error->pipe[i].power_domain_on ? "on" : "off");
13684                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13685                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13686
13687                 err_printf(m, "Plane [%d]:\n", i);
13688                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13689                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13690                 if (INTEL_INFO(dev)->gen <= 3) {
13691                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13692                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13693                 }
13694                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13695                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13696                 if (INTEL_INFO(dev)->gen >= 4) {
13697                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13698                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13699                 }
13700
13701                 err_printf(m, "Cursor [%d]:\n", i);
13702                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13703                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13704                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13705         }
13706
13707         for (i = 0; i < error->num_transcoders; i++) {
13708                 err_printf(m, "CPU transcoder: %c\n",
13709                            transcoder_name(error->transcoder[i].cpu_transcoder));
13710                 err_printf(m, "  Power: %s\n",
13711                            error->transcoder[i].power_domain_on ? "on" : "off");
13712                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13713                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13714                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13715                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13716                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13717                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13718                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13719         }
13720 }
13721
13722 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13723 {
13724         struct intel_crtc *crtc;
13725
13726         for_each_intel_crtc(dev, crtc) {
13727                 struct intel_unpin_work *work;
13728
13729                 spin_lock_irq(&dev->event_lock);
13730
13731                 work = crtc->unpin_work;
13732
13733                 if (work && work->event &&
13734                     work->event->base.file_priv == file) {
13735                         kfree(work->event);
13736                         work->event = NULL;
13737                 }
13738
13739                 spin_unlock_irq(&dev->event_lock);
13740         }
13741 }