drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return drm_atomic_crtc_needs_modeset(state);
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 default:
1102                         return true;
1103                 }
1104         }
1105
1106         return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111         return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116                 enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121
1122         reg = DPLL(pipe);
1123         val = I915_READ(reg);
1124         cur_state = !!(val & DPLL_VCO_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "PLL state assertion failure (expected %s, current %s)\n",
1127              state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         mutex_lock(&dev_priv->sb_lock);
1137         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138         mutex_unlock(&dev_priv->sb_lock);
1139
1140         cur_state = val & DSI_PLL_VCO_EN;
1141         I915_STATE_WARN(cur_state != state,
1142              "DSI PLL state assertion failure (expected %s, current %s)\n",
1143              state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153         if (crtc->config->shared_dpll < 0)
1154                 return NULL;
1155
1156         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161                         struct intel_shared_dpll *pll,
1162                         bool state)
1163 {
1164         bool cur_state;
1165         struct intel_dpll_hw_state hw_state;
1166
1167         if (WARN (!pll,
1168                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1169                 return;
1170
1171         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172         I915_STATE_WARN(cur_state != state,
1173              "%s assertion failure (expected %s, current %s)\n",
1174              pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178                           enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184                                                                       pipe);
1185
1186         if (HAS_DDI(dev_priv->dev)) {
1187                 /* DDI does not have a specific FDI_TX register */
1188                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189                 val = I915_READ(reg);
1190                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191         } else {
1192                 reg = FDI_TX_CTL(pipe);
1193                 val = I915_READ(reg);
1194                 cur_state = !!(val & FDI_TX_ENABLE);
1195         }
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI TX state assertion failure (expected %s, current %s)\n",
1198              state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204                           enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209
1210         reg = FDI_RX_CTL(pipe);
1211         val = I915_READ(reg);
1212         cur_state = !!(val & FDI_RX_ENABLE);
1213         I915_STATE_WARN(cur_state != state,
1214              "FDI RX state assertion failure (expected %s, current %s)\n",
1215              state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221                                       enum pipe pipe)
1222 {
1223         int reg;
1224         u32 val;
1225
1226         /* ILK FDI PLL is always enabled */
1227         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228                 return;
1229
1230         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231         if (HAS_DDI(dev_priv->dev))
1232                 return;
1233
1234         reg = FDI_TX_CTL(pipe);
1235         val = I915_READ(reg);
1236         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240                        enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245
1246         reg = FDI_RX_CTL(pipe);
1247         val = I915_READ(reg);
1248         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255                            enum pipe pipe)
1256 {
1257         struct drm_device *dev = dev_priv->dev;
1258         int pp_reg;
1259         u32 val;
1260         enum pipe panel_pipe = PIPE_A;
1261         bool locked = true;
1262
1263         if (WARN_ON(HAS_DDI(dev)))
1264                 return;
1265
1266         if (HAS_PCH_SPLIT(dev)) {
1267                 u32 port_sel;
1268
1269                 pp_reg = PCH_PP_CONTROL;
1270                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274                         panel_pipe = PIPE_B;
1275                 /* XXX: else fix for eDP */
1276         } else if (IS_VALLEYVIEW(dev)) {
1277                 /* presumably write lock depends on pipe, not port select */
1278                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279                 panel_pipe = pipe;
1280         } else {
1281                 pp_reg = PP_CONTROL;
1282                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283                         panel_pipe = PIPE_B;
1284         }
1285
1286         val = I915_READ(pp_reg);
1287         if (!(val & PANEL_POWER_ON) ||
1288             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289                 locked = false;
1290
1291         I915_STATE_WARN(panel_pipe == pipe && locked,
1292              "panel assertion failure, pipe %c regs locked\n",
1293              pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297                           enum pipe pipe, bool state)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         bool cur_state;
1301
1302         if (IS_845G(dev) || IS_I865G(dev))
1303                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304         else
1305                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309              pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315                  enum pipe pipe, bool state)
1316 {
1317         int reg;
1318         u32 val;
1319         bool cur_state;
1320         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321                                                                       pipe);
1322
1323         /* if we need the pipe quirk it must be always on */
1324         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326                 state = true;
1327
1328         if (!intel_display_power_is_enabled(dev_priv,
1329                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330                 cur_state = false;
1331         } else {
1332                 reg = PIPECONF(cpu_transcoder);
1333                 val = I915_READ(reg);
1334                 cur_state = !!(val & PIPECONF_ENABLE);
1335         }
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343                          enum plane plane, bool state)
1344 {
1345         int reg;
1346         u32 val;
1347         bool cur_state;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352         I915_STATE_WARN(cur_state != state,
1353              "plane %c assertion failure (expected %s, current %s)\n",
1354              plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361                                    enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int reg, i;
1365         u32 val;
1366         int cur_pipe;
1367
1368         /* Primary planes are fixed to pipes on gen4+ */
1369         if (INTEL_INFO(dev)->gen >= 4) {
1370                 reg = DSPCNTR(pipe);
1371                 val = I915_READ(reg);
1372                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373                      "plane %c assertion failure, should be disabled but not\n",
1374                      plane_name(pipe));
1375                 return;
1376         }
1377
1378         /* Need to check both planes against the pipe */
1379         for_each_pipe(dev_priv, i) {
1380                 reg = DSPCNTR(i);
1381                 val = I915_READ(reg);
1382                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383                         DISPPLANE_SEL_PIPE_SHIFT;
1384                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386                      plane_name(i), pipe_name(pipe));
1387         }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391                                     enum pipe pipe)
1392 {
1393         struct drm_device *dev = dev_priv->dev;
1394         int reg, sprite;
1395         u32 val;
1396
1397         if (INTEL_INFO(dev)->gen >= 9) {
1398                 for_each_sprite(dev_priv, pipe, sprite) {
1399                         val = I915_READ(PLANE_CTL(pipe, sprite));
1400                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite, pipe_name(pipe));
1403                 }
1404         } else if (IS_VALLEYVIEW(dev)) {
1405                 for_each_sprite(dev_priv, pipe, sprite) {
1406                         reg = SPCNTR(pipe, sprite);
1407                         val = I915_READ(reg);
1408                         I915_STATE_WARN(val & SP_ENABLE,
1409                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite_name(pipe, sprite), pipe_name(pipe));
1411                 }
1412         } else if (INTEL_INFO(dev)->gen >= 7) {
1413                 reg = SPRCTL(pipe);
1414                 val = I915_READ(reg);
1415                 I915_STATE_WARN(val & SPRITE_ENABLE,
1416                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417                      plane_name(pipe), pipe_name(pipe));
1418         } else if (INTEL_INFO(dev)->gen >= 5) {
1419                 reg = DVSCNTR(pipe);
1420                 val = I915_READ(reg);
1421                 I915_STATE_WARN(val & DVS_ENABLE,
1422                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423                      plane_name(pipe), pipe_name(pipe));
1424         }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430                 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435         u32 val;
1436         bool enabled;
1437
1438         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440         val = I915_READ(PCH_DREF_CONTROL);
1441         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442                             DREF_SUPERSPREAD_SOURCE_MASK));
1443         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447                                            enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451         bool enabled;
1452
1453         reg = PCH_TRANSCONF(pipe);
1454         val = I915_READ(reg);
1455         enabled = !!(val & TRANS_ENABLE);
1456         I915_STATE_WARN(enabled,
1457              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458              pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462                             enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464         if ((val & DP_PORT_EN) == 0)
1465                 return false;
1466
1467         if (HAS_PCH_CPT(dev_priv->dev)) {
1468                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471                         return false;
1472         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483                               enum pipe pipe, u32 val)
1484 {
1485         if ((val & SDVO_ENABLE) == 0)
1486                 return false;
1487
1488         if (HAS_PCH_CPT(dev_priv->dev)) {
1489                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490                         return false;
1491         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493                         return false;
1494         } else {
1495                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496                         return false;
1497         }
1498         return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502                               enum pipe pipe, u32 val)
1503 {
1504         if ((val & LVDS_PORT_EN) == 0)
1505                 return false;
1506
1507         if (HAS_PCH_CPT(dev_priv->dev)) {
1508                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & ADPA_DAC_ENABLE) == 0)
1521                 return false;
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533                                    enum pipe pipe, int reg, u32 port_sel)
1534 {
1535         u32 val = I915_READ(reg);
1536         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538              reg, pipe_name(pipe));
1539
1540         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541              && (val & DP_PIPEB_SELECT),
1542              "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546                                      enum pipe pipe, int reg)
1547 {
1548         u32 val = I915_READ(reg);
1549         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551              reg, pipe_name(pipe));
1552
1553         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554              && (val & SDVO_PIPE_B_SELECT),
1555              "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559                                       enum pipe pipe)
1560 {
1561         int reg;
1562         u32 val;
1563
1564         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568         reg = PCH_ADPA;
1569         val = I915_READ(reg);
1570         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571              "PCH VGA enabled on transcoder %c, should be disabled\n",
1572              pipe_name(pipe));
1573
1574         reg = PCH_LVDS;
1575         val = I915_READ(reg);
1576         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578              pipe_name(pipe));
1579
1580         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         if (!IS_VALLEYVIEW(dev))
1590                 return;
1591
1592         /*
1593          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594          * CHV x1 PHY (DP/HDMI D)
1595          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596          */
1597         if (IS_CHERRYVIEW(dev)) {
1598                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600         } else {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602         }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606                            const struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_device *dev = crtc->base.dev;
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         int reg = DPLL(crtc->pipe);
1611         u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* No really, not for ILK+ */
1616         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618         /* PLL is protected by panel, make sure we can write it */
1619         if (IS_MOBILE(dev_priv->dev))
1620                 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622         I915_WRITE(reg, dpll);
1623         POSTING_READ(reg);
1624         udelay(150);
1625
1626         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630         POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632         /* We do this three times for luck */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645                            const struct intel_crtc_state *pipe_config)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         int pipe = crtc->pipe;
1650         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651         u32 tmp;
1652
1653         assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657         mutex_lock(&dev_priv->sb_lock);
1658
1659         /* Enable back the 10bit clock to display controller */
1660         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661         tmp |= DPIO_DCLKP_EN;
1662         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664         mutex_unlock(&dev_priv->sb_lock);
1665
1666         /*
1667          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668          */
1669         udelay(1);
1670
1671         /* Enable PLL */
1672         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674         /* Check PLL is locked */
1675         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678         /* not sure when this should be written */
1679         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680         POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685         struct intel_crtc *crtc;
1686         int count = 0;
1687
1688         for_each_intel_crtc(dev, crtc)
1689                 count += crtc->base.state->active &&
1690                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692         return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697         struct drm_device *dev = crtc->base.dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         int reg = DPLL(crtc->pipe);
1700         u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702         assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704         /* No really, not for ILK+ */
1705         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707         /* PLL is protected by panel, make sure we can write it */
1708         if (IS_MOBILE(dev) && !IS_I830(dev))
1709                 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711         /* Enable DVO 2x clock on both PLLs if necessary */
1712         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713                 /*
1714                  * It appears to be important that we don't enable this
1715                  * for the current pipe before otherwise configuring the
1716                  * PLL. No idea how this should be handled if multiple
1717                  * DVO outputs are enabled simultaneosly.
1718                  */
1719                 dpll |= DPLL_DVO_2X_MODE;
1720                 I915_WRITE(DPLL(!crtc->pipe),
1721                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722         }
1723
1724         /* Wait for the clocks to stabilize. */
1725         POSTING_READ(reg);
1726         udelay(150);
1727
1728         if (INTEL_INFO(dev)->gen >= 4) {
1729                 I915_WRITE(DPLL_MD(crtc->pipe),
1730                            crtc->config->dpll_hw_state.dpll_md);
1731         } else {
1732                 /* The pixel multiplier can only be updated once the
1733                  * DPLL is enabled and the clocks are stable.
1734                  *
1735                  * So write it again.
1736                  */
1737                 I915_WRITE(reg, dpll);
1738         }
1739
1740         /* We do this three times for luck */
1741         I915_WRITE(reg, dpll);
1742         POSTING_READ(reg);
1743         udelay(150); /* wait for warmup */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753  * i9xx_disable_pll - disable a PLL
1754  * @dev_priv: i915 private structure
1755  * @pipe: pipe PLL to disable
1756  *
1757  * Disable the PLL for @pipe, making sure the pipe is off first.
1758  *
1759  * Note!  This is for pre-ILK only.
1760  */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         enum pipe pipe = crtc->pipe;
1766
1767         /* Disable DVO 2x clock on both PLLs if necessary */
1768         if (IS_I830(dev) &&
1769             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770             !intel_num_dvo_pipes(dev)) {
1771                 I915_WRITE(DPLL(PIPE_B),
1772                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773                 I915_WRITE(DPLL(PIPE_A),
1774                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775         }
1776
1777         /* Don't disable pipe or pipe PLLs if needed */
1778         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780                 return;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786         POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791         u32 val;
1792
1793         /* Make sure the pipe isn't still relying on us */
1794         assert_pipe_disabled(dev_priv, pipe);
1795
1796         /*
1797          * Leave integrated clock source and reference clock enabled for pipe B.
1798          * The latter is needed for VGA hotplug / manual detection.
1799          */
1800         val = DPLL_VGA_MODE_DIS;
1801         if (pipe == PIPE_B)
1802                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803         I915_WRITE(DPLL(pipe), val);
1804         POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811         u32 val;
1812
1813         /* Make sure the pipe isn't still relying on us */
1814         assert_pipe_disabled(dev_priv, pipe);
1815
1816         /* Set PLL en = 0 */
1817         val = DPLL_SSC_REF_CLK_CHV |
1818                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819         if (pipe != PIPE_A)
1820                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821         I915_WRITE(DPLL(pipe), val);
1822         POSTING_READ(DPLL(pipe));
1823
1824         mutex_lock(&dev_priv->sb_lock);
1825
1826         /* Disable 10bit clock to display controller */
1827         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828         val &= ~DPIO_DCLKP_EN;
1829         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831         /* disable left/right clock distribution */
1832         if (pipe != PIPE_B) {
1833                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836         } else {
1837                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840         }
1841
1842         mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846                          struct intel_digital_port *dport,
1847                          unsigned int expected_mask)
1848 {
1849         u32 port_mask;
1850         int dpll_reg;
1851
1852         switch (dport->port) {
1853         case PORT_B:
1854                 port_mask = DPLL_PORTB_READY_MASK;
1855                 dpll_reg = DPLL(0);
1856                 break;
1857         case PORT_C:
1858                 port_mask = DPLL_PORTC_READY_MASK;
1859                 dpll_reg = DPLL(0);
1860                 expected_mask <<= 4;
1861                 break;
1862         case PORT_D:
1863                 port_mask = DPLL_PORTD_READY_MASK;
1864                 dpll_reg = DPIO_PHY_STATUS;
1865                 break;
1866         default:
1867                 BUG();
1868         }
1869
1870         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->base.dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881         if (WARN_ON(pll == NULL))
1882                 return;
1883
1884         WARN_ON(!pll->config.crtc_mask);
1885         if (pll->active == 0) {
1886                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887                 WARN_ON(pll->on);
1888                 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890                 pll->mode_set(dev_priv, pll);
1891         }
1892 }
1893
1894 /**
1895  * intel_enable_shared_dpll - enable PCH PLL
1896  * @dev_priv: i915 private structure
1897  * @pipe: pipe PLL to enable
1898  *
1899  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900  * drives the transcoder clock.
1901  */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904         struct drm_device *dev = crtc->base.dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908         if (WARN_ON(pll == NULL))
1909                 return;
1910
1911         if (WARN_ON(pll->config.crtc_mask == 0))
1912                 return;
1913
1914         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915                       pll->name, pll->active, pll->on,
1916                       crtc->base.base.id);
1917
1918         if (pll->active++) {
1919                 WARN_ON(!pll->on);
1920                 assert_shared_dpll_enabled(dev_priv, pll);
1921                 return;
1922         }
1923         WARN_ON(pll->on);
1924
1925         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928         pll->enable(dev_priv, pll);
1929         pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934         struct drm_device *dev = crtc->base.dev;
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938         /* PCH only available on ILK+ */
1939         if (INTEL_INFO(dev)->gen < 5)
1940                 return;
1941
1942         if (pll == NULL)
1943                 return;
1944
1945         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946                 return;
1947
1948         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949                       pll->name, pll->active, pll->on,
1950                       crtc->base.base.id);
1951
1952         if (WARN_ON(pll->active == 0)) {
1953                 assert_shared_dpll_disabled(dev_priv, pll);
1954                 return;
1955         }
1956
1957         assert_shared_dpll_enabled(dev_priv, pll);
1958         WARN_ON(!pll->on);
1959         if (--pll->active)
1960                 return;
1961
1962         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963         pll->disable(dev_priv, pll);
1964         pll->on = false;
1965
1966         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 }
1968
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970                                            enum pipe pipe)
1971 {
1972         struct drm_device *dev = dev_priv->dev;
1973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975         uint32_t reg, val, pipeconf_val;
1976
1977         /* PCH only available on ILK+ */
1978         BUG_ON(!HAS_PCH_SPLIT(dev));
1979
1980         /* Make sure PCH DPLL is enabled */
1981         assert_shared_dpll_enabled(dev_priv,
1982                                    intel_crtc_to_shared_dpll(intel_crtc));
1983
1984         /* FDI must be feeding us bits for PCH ports */
1985         assert_fdi_tx_enabled(dev_priv, pipe);
1986         assert_fdi_rx_enabled(dev_priv, pipe);
1987
1988         if (HAS_PCH_CPT(dev)) {
1989                 /* Workaround: Set the timing override bit before enabling the
1990                  * pch transcoder. */
1991                 reg = TRANS_CHICKEN2(pipe);
1992                 val = I915_READ(reg);
1993                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994                 I915_WRITE(reg, val);
1995         }
1996
1997         reg = PCH_TRANSCONF(pipe);
1998         val = I915_READ(reg);
1999         pipeconf_val = I915_READ(PIPECONF(pipe));
2000
2001         if (HAS_PCH_IBX(dev_priv->dev)) {
2002                 /*
2003                  * Make the BPC in transcoder be consistent with
2004                  * that in pipeconf reg. For HDMI we must use 8bpc
2005                  * here for both 8bpc and 12bpc.
2006                  */
2007                 val &= ~PIPECONF_BPC_MASK;
2008                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009                         val |= PIPECONF_8BPC;
2010                 else
2011                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2012         }
2013
2014         val &= ~TRANS_INTERLACE_MASK;
2015         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016                 if (HAS_PCH_IBX(dev_priv->dev) &&
2017                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018                         val |= TRANS_LEGACY_INTERLACED_ILK;
2019                 else
2020                         val |= TRANS_INTERLACED;
2021         else
2022                 val |= TRANS_PROGRESSIVE;
2023
2024         I915_WRITE(reg, val | TRANS_ENABLE);
2025         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030                                       enum transcoder cpu_transcoder)
2031 {
2032         u32 val, pipeconf_val;
2033
2034         /* PCH only available on ILK+ */
2035         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037         /* FDI must be feeding us bits for PCH ports */
2038         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041         /* Workaround: set timing override bit. */
2042         val = I915_READ(_TRANSA_CHICKEN2);
2043         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044         I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046         val = TRANS_ENABLE;
2047         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050             PIPECONF_INTERLACED_ILK)
2051                 val |= TRANS_INTERLACED;
2052         else
2053                 val |= TRANS_PROGRESSIVE;
2054
2055         I915_WRITE(LPT_TRANSCONF, val);
2056         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057                 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061                                             enum pipe pipe)
2062 {
2063         struct drm_device *dev = dev_priv->dev;
2064         uint32_t reg, val;
2065
2066         /* FDI relies on the transcoder */
2067         assert_fdi_tx_disabled(dev_priv, pipe);
2068         assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070         /* Ports must be off as well */
2071         assert_pch_ports_disabled(dev_priv, pipe);
2072
2073         reg = PCH_TRANSCONF(pipe);
2074         val = I915_READ(reg);
2075         val &= ~TRANS_ENABLE;
2076         I915_WRITE(reg, val);
2077         /* wait for PCH transcoder off, transcoder state */
2078         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081         if (!HAS_PCH_IBX(dev)) {
2082                 /* Workaround: Clear the timing override chicken bit again. */
2083                 reg = TRANS_CHICKEN2(pipe);
2084                 val = I915_READ(reg);
2085                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086                 I915_WRITE(reg, val);
2087         }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092         u32 val;
2093
2094         val = I915_READ(LPT_TRANSCONF);
2095         val &= ~TRANS_ENABLE;
2096         I915_WRITE(LPT_TRANSCONF, val);
2097         /* wait for PCH transcoder off, transcoder state */
2098         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099                 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101         /* Workaround: clear timing override bit. */
2102         val = I915_READ(_TRANSA_CHICKEN2);
2103         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104         I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108  * intel_enable_pipe - enable a pipe, asserting requirements
2109  * @crtc: crtc responsible for the pipe
2110  *
2111  * Enable @crtc's pipe, making sure that various hardware specific requirements
2112  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113  */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116         struct drm_device *dev = crtc->base.dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         enum pipe pipe = crtc->pipe;
2119         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120                                                                       pipe);
2121         enum pipe pch_transcoder;
2122         int reg;
2123         u32 val;
2124
2125         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
2127         assert_planes_disabled(dev_priv, pipe);
2128         assert_cursor_disabled(dev_priv, pipe);
2129         assert_sprites_disabled(dev_priv, pipe);
2130
2131         if (HAS_PCH_LPT(dev_priv->dev))
2132                 pch_transcoder = TRANSCODER_A;
2133         else
2134                 pch_transcoder = pipe;
2135
2136         /*
2137          * A pipe without a PLL won't actually be able to drive bits from
2138          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2139          * need the check.
2140          */
2141         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143                         assert_dsi_pll_enabled(dev_priv);
2144                 else
2145                         assert_pll_enabled(dev_priv, pipe);
2146         else {
2147                 if (crtc->config->has_pch_encoder) {
2148                         /* if driving the PCH, we need FDI enabled */
2149                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150                         assert_fdi_tx_pll_enabled(dev_priv,
2151                                                   (enum pipe) cpu_transcoder);
2152                 }
2153                 /* FIXME: assert CPU port conditions for SNB+ */
2154         }
2155
2156         reg = PIPECONF(cpu_transcoder);
2157         val = I915_READ(reg);
2158         if (val & PIPECONF_ENABLE) {
2159                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2161                 return;
2162         }
2163
2164         I915_WRITE(reg, val | PIPECONF_ENABLE);
2165         POSTING_READ(reg);
2166 }
2167
2168 /**
2169  * intel_disable_pipe - disable a pipe, asserting requirements
2170  * @crtc: crtc whose pipes is to be disabled
2171  *
2172  * Disable the pipe of @crtc, making sure that various hardware
2173  * specific requirements are met, if applicable, e.g. plane
2174  * disabled, panel fitter off, etc.
2175  *
2176  * Will wait until the pipe has shut down before returning.
2177  */
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2179 {
2180         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182         enum pipe pipe = crtc->pipe;
2183         int reg;
2184         u32 val;
2185
2186         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
2188         /*
2189          * Make sure planes won't keep trying to pump pixels to us,
2190          * or we might hang the display.
2191          */
2192         assert_planes_disabled(dev_priv, pipe);
2193         assert_cursor_disabled(dev_priv, pipe);
2194         assert_sprites_disabled(dev_priv, pipe);
2195
2196         reg = PIPECONF(cpu_transcoder);
2197         val = I915_READ(reg);
2198         if ((val & PIPECONF_ENABLE) == 0)
2199                 return;
2200
2201         /*
2202          * Double wide has implications for planes
2203          * so best keep it disabled when not needed.
2204          */
2205         if (crtc->config->double_wide)
2206                 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208         /* Don't disable pipe or pipe PLLs if needed */
2209         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211                 val &= ~PIPECONF_ENABLE;
2212
2213         I915_WRITE(reg, val);
2214         if ((val & PIPECONF_ENABLE) == 0)
2215                 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 static bool need_vtd_wa(struct drm_device *dev)
2219 {
2220 #ifdef CONFIG_INTEL_IOMMU
2221         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222                 return true;
2223 #endif
2224         return false;
2225 }
2226
2227 unsigned int
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229                   uint64_t fb_format_modifier)
2230 {
2231         unsigned int tile_height;
2232         uint32_t pixel_bytes;
2233
2234         switch (fb_format_modifier) {
2235         case DRM_FORMAT_MOD_NONE:
2236                 tile_height = 1;
2237                 break;
2238         case I915_FORMAT_MOD_X_TILED:
2239                 tile_height = IS_GEN2(dev) ? 16 : 8;
2240                 break;
2241         case I915_FORMAT_MOD_Y_TILED:
2242                 tile_height = 32;
2243                 break;
2244         case I915_FORMAT_MOD_Yf_TILED:
2245                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246                 switch (pixel_bytes) {
2247                 default:
2248                 case 1:
2249                         tile_height = 64;
2250                         break;
2251                 case 2:
2252                 case 4:
2253                         tile_height = 32;
2254                         break;
2255                 case 8:
2256                         tile_height = 16;
2257                         break;
2258                 case 16:
2259                         WARN_ONCE(1,
2260                                   "128-bit pixels are not supported for display!");
2261                         tile_height = 16;
2262                         break;
2263                 }
2264                 break;
2265         default:
2266                 MISSING_CASE(fb_format_modifier);
2267                 tile_height = 1;
2268                 break;
2269         }
2270
2271         return tile_height;
2272 }
2273
2274 unsigned int
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276                       uint32_t pixel_format, uint64_t fb_format_modifier)
2277 {
2278         return ALIGN(height, intel_tile_height(dev, pixel_format,
2279                                                fb_format_modifier));
2280 }
2281
2282 static int
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284                         const struct drm_plane_state *plane_state)
2285 {
2286         struct intel_rotation_info *info = &view->rotation_info;
2287         unsigned int tile_height, tile_pitch;
2288
2289         *view = i915_ggtt_view_normal;
2290
2291         if (!plane_state)
2292                 return 0;
2293
2294         if (!intel_rotation_90_or_270(plane_state->rotation))
2295                 return 0;
2296
2297         *view = i915_ggtt_view_rotated;
2298
2299         info->height = fb->height;
2300         info->pixel_format = fb->pixel_format;
2301         info->pitch = fb->pitches[0];
2302         info->fb_modifier = fb->modifier[0];
2303
2304         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305                                         fb->modifier[0]);
2306         tile_pitch = PAGE_SIZE / tile_height;
2307         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
2311         return 0;
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316         if (INTEL_INFO(dev_priv)->gen >= 9)
2317                 return 256 * 1024;
2318         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319                  IS_VALLEYVIEW(dev_priv))
2320                 return 128 * 1024;
2321         else if (INTEL_INFO(dev_priv)->gen >= 4)
2322                 return 4 * 1024;
2323         else
2324                 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329                            struct drm_framebuffer *fb,
2330                            const struct drm_plane_state *plane_state,
2331                            struct intel_engine_cs *pipelined,
2332                            struct drm_i915_gem_request **pipelined_request)
2333 {
2334         struct drm_device *dev = fb->dev;
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338         u32 alignment;
2339         int ret;
2340
2341         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343         switch (fb->modifier[0]) {
2344         case DRM_FORMAT_MOD_NONE:
2345                 alignment = intel_linear_alignment(dev_priv);
2346                 break;
2347         case I915_FORMAT_MOD_X_TILED:
2348                 if (INTEL_INFO(dev)->gen >= 9)
2349                         alignment = 256 * 1024;
2350                 else {
2351                         /* pin() will align the object as required by fence */
2352                         alignment = 0;
2353                 }
2354                 break;
2355         case I915_FORMAT_MOD_Y_TILED:
2356         case I915_FORMAT_MOD_Yf_TILED:
2357                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358                           "Y tiling bo slipped through, driver bug!\n"))
2359                         return -EINVAL;
2360                 alignment = 1 * 1024 * 1024;
2361                 break;
2362         default:
2363                 MISSING_CASE(fb->modifier[0]);
2364                 return -EINVAL;
2365         }
2366
2367         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368         if (ret)
2369                 return ret;
2370
2371         /* Note that the w/a also requires 64 PTE of padding following the
2372          * bo. We currently fill all unused PTE with the shadow page and so
2373          * we should always have valid PTE following the scanout preventing
2374          * the VT-d warning.
2375          */
2376         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377                 alignment = 256 * 1024;
2378
2379         /*
2380          * Global gtt pte registers are special registers which actually forward
2381          * writes to a chunk of system memory. Which means that there is no risk
2382          * that the register values disappear as soon as we call
2383          * intel_runtime_pm_put(), so it is correct to wrap only the
2384          * pin/unpin/fence and not more.
2385          */
2386         intel_runtime_pm_get(dev_priv);
2387
2388         dev_priv->mm.interruptible = false;
2389         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390                                                    pipelined_request, &view);
2391         if (ret)
2392                 goto err_interruptible;
2393
2394         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395          * fence, whereas 965+ only requires a fence if using
2396          * framebuffer compression.  For simplicity, we always install
2397          * a fence as the cost is not that onerous.
2398          */
2399         ret = i915_gem_object_get_fence(obj);
2400         if (ret == -EDEADLK) {
2401                 /*
2402                  * -EDEADLK means there are no free fences
2403                  * no pending flips.
2404                  *
2405                  * This is propagated to atomic, but it uses
2406                  * -EDEADLK to force a locking recovery, so
2407                  * change the returned error to -EBUSY.
2408                  */
2409                 ret = -EBUSY;
2410                 goto err_unpin;
2411         } else if (ret)
2412                 goto err_unpin;
2413
2414         i915_gem_object_pin_fence(obj);
2415
2416         dev_priv->mm.interruptible = true;
2417         intel_runtime_pm_put(dev_priv);
2418         return 0;
2419
2420 err_unpin:
2421         i915_gem_object_unpin_from_display_plane(obj, &view);
2422 err_interruptible:
2423         dev_priv->mm.interruptible = true;
2424         intel_runtime_pm_put(dev_priv);
2425         return ret;
2426 }
2427
2428 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429                                const struct drm_plane_state *plane_state)
2430 {
2431         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2432         struct i915_ggtt_view view;
2433         int ret;
2434
2435         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
2437         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438         WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
2440         i915_gem_object_unpin_fence(obj);
2441         i915_gem_object_unpin_from_display_plane(obj, &view);
2442 }
2443
2444 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445  * is assumed to be a power-of-two. */
2446 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2447                                              int *x, int *y,
2448                                              unsigned int tiling_mode,
2449                                              unsigned int cpp,
2450                                              unsigned int pitch)
2451 {
2452         if (tiling_mode != I915_TILING_NONE) {
2453                 unsigned int tile_rows, tiles;
2454
2455                 tile_rows = *y / 8;
2456                 *y %= 8;
2457
2458                 tiles = *x / (512/cpp);
2459                 *x %= 512/cpp;
2460
2461                 return tile_rows * pitch * 8 + tiles * 4096;
2462         } else {
2463                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2464                 unsigned int offset;
2465
2466                 offset = *y * pitch + *x * cpp;
2467                 *y = (offset & alignment) / pitch;
2468                 *x = ((offset & alignment) - *y * pitch) / cpp;
2469                 return offset & ~alignment;
2470         }
2471 }
2472
2473 static int i9xx_format_to_fourcc(int format)
2474 {
2475         switch (format) {
2476         case DISPPLANE_8BPP:
2477                 return DRM_FORMAT_C8;
2478         case DISPPLANE_BGRX555:
2479                 return DRM_FORMAT_XRGB1555;
2480         case DISPPLANE_BGRX565:
2481                 return DRM_FORMAT_RGB565;
2482         default:
2483         case DISPPLANE_BGRX888:
2484                 return DRM_FORMAT_XRGB8888;
2485         case DISPPLANE_RGBX888:
2486                 return DRM_FORMAT_XBGR8888;
2487         case DISPPLANE_BGRX101010:
2488                 return DRM_FORMAT_XRGB2101010;
2489         case DISPPLANE_RGBX101010:
2490                 return DRM_FORMAT_XBGR2101010;
2491         }
2492 }
2493
2494 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2495 {
2496         switch (format) {
2497         case PLANE_CTL_FORMAT_RGB_565:
2498                 return DRM_FORMAT_RGB565;
2499         default:
2500         case PLANE_CTL_FORMAT_XRGB_8888:
2501                 if (rgb_order) {
2502                         if (alpha)
2503                                 return DRM_FORMAT_ABGR8888;
2504                         else
2505                                 return DRM_FORMAT_XBGR8888;
2506                 } else {
2507                         if (alpha)
2508                                 return DRM_FORMAT_ARGB8888;
2509                         else
2510                                 return DRM_FORMAT_XRGB8888;
2511                 }
2512         case PLANE_CTL_FORMAT_XRGB_2101010:
2513                 if (rgb_order)
2514                         return DRM_FORMAT_XBGR2101010;
2515                 else
2516                         return DRM_FORMAT_XRGB2101010;
2517         }
2518 }
2519
2520 static bool
2521 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2522                               struct intel_initial_plane_config *plane_config)
2523 {
2524         struct drm_device *dev = crtc->base.dev;
2525         struct drm_i915_gem_object *obj = NULL;
2526         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2527         struct drm_framebuffer *fb = &plane_config->fb->base;
2528         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2529         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2530                                     PAGE_SIZE);
2531
2532         size_aligned -= base_aligned;
2533
2534         if (plane_config->size == 0)
2535                 return false;
2536
2537         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538                                                              base_aligned,
2539                                                              base_aligned,
2540                                                              size_aligned);
2541         if (!obj)
2542                 return false;
2543
2544         obj->tiling_mode = plane_config->tiling;
2545         if (obj->tiling_mode == I915_TILING_X)
2546                 obj->stride = fb->pitches[0];
2547
2548         mode_cmd.pixel_format = fb->pixel_format;
2549         mode_cmd.width = fb->width;
2550         mode_cmd.height = fb->height;
2551         mode_cmd.pitches[0] = fb->pitches[0];
2552         mode_cmd.modifier[0] = fb->modifier[0];
2553         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555         mutex_lock(&dev->struct_mutex);
2556         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557                                    &mode_cmd, obj)) {
2558                 DRM_DEBUG_KMS("intel fb init failed\n");
2559                 goto out_unref_obj;
2560         }
2561         mutex_unlock(&dev->struct_mutex);
2562
2563         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564         return true;
2565
2566 out_unref_obj:
2567         drm_gem_object_unreference(&obj->base);
2568         mutex_unlock(&dev->struct_mutex);
2569         return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576         if (plane->fb == plane->state->fb)
2577                 return;
2578
2579         if (plane->state->fb)
2580                 drm_framebuffer_unreference(plane->state->fb);
2581         plane->state->fb = plane->fb;
2582         if (plane->state->fb)
2583                 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588                              struct intel_initial_plane_config *plane_config)
2589 {
2590         struct drm_device *dev = intel_crtc->base.dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct drm_crtc *c;
2593         struct intel_crtc *i;
2594         struct drm_i915_gem_object *obj;
2595         struct drm_plane *primary = intel_crtc->base.primary;
2596         struct drm_plane_state *plane_state = primary->state;
2597         struct drm_framebuffer *fb;
2598
2599         if (!plane_config->fb)
2600                 return;
2601
2602         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2603                 fb = &plane_config->fb->base;
2604                 goto valid_fb;
2605         }
2606
2607         kfree(plane_config->fb);
2608
2609         /*
2610          * Failed to alloc the obj, check to see if we should share
2611          * an fb with another CRTC instead
2612          */
2613         for_each_crtc(dev, c) {
2614                 i = to_intel_crtc(c);
2615
2616                 if (c == &intel_crtc->base)
2617                         continue;
2618
2619                 if (!i->active)
2620                         continue;
2621
2622                 fb = c->primary->fb;
2623                 if (!fb)
2624                         continue;
2625
2626                 obj = intel_fb_obj(fb);
2627                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2628                         drm_framebuffer_reference(fb);
2629                         goto valid_fb;
2630                 }
2631         }
2632
2633         return;
2634
2635 valid_fb:
2636         plane_state->src_x = plane_state->src_y = 0;
2637         plane_state->src_w = fb->width << 16;
2638         plane_state->src_h = fb->height << 16;
2639
2640         plane_state->crtc_x = plane_state->src_y = 0;
2641         plane_state->crtc_w = fb->width;
2642         plane_state->crtc_h = fb->height;
2643
2644         obj = intel_fb_obj(fb);
2645         if (obj->tiling_mode != I915_TILING_NONE)
2646                 dev_priv->preserve_bios_swizzle = true;
2647
2648         drm_framebuffer_reference(fb);
2649         primary->fb = primary->state->fb = fb;
2650         primary->crtc = primary->state->crtc = &intel_crtc->base;
2651         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2652         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2653 }
2654
2655 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656                                       struct drm_framebuffer *fb,
2657                                       int x, int y)
2658 {
2659         struct drm_device *dev = crtc->dev;
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662         struct drm_plane *primary = crtc->primary;
2663         bool visible = to_intel_plane_state(primary->state)->visible;
2664         struct drm_i915_gem_object *obj;
2665         int plane = intel_crtc->plane;
2666         unsigned long linear_offset;
2667         u32 dspcntr;
2668         u32 reg = DSPCNTR(plane);
2669         int pixel_size;
2670
2671         if (!visible || !fb) {
2672                 I915_WRITE(reg, 0);
2673                 if (INTEL_INFO(dev)->gen >= 4)
2674                         I915_WRITE(DSPSURF(plane), 0);
2675                 else
2676                         I915_WRITE(DSPADDR(plane), 0);
2677                 POSTING_READ(reg);
2678                 return;
2679         }
2680
2681         obj = intel_fb_obj(fb);
2682         if (WARN_ON(obj == NULL))
2683                 return;
2684
2685         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
2687         dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
2689         dspcntr |= DISPLAY_PLANE_ENABLE;
2690
2691         if (INTEL_INFO(dev)->gen < 4) {
2692                 if (intel_crtc->pipe == PIPE_B)
2693                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695                 /* pipesrc and dspsize control the size that is scaled from,
2696                  * which should always be the user's requested size.
2697                  */
2698                 I915_WRITE(DSPSIZE(plane),
2699                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700                            (intel_crtc->config->pipe_src_w - 1));
2701                 I915_WRITE(DSPPOS(plane), 0);
2702         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703                 I915_WRITE(PRIMSIZE(plane),
2704                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705                            (intel_crtc->config->pipe_src_w - 1));
2706                 I915_WRITE(PRIMPOS(plane), 0);
2707                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2708         }
2709
2710         switch (fb->pixel_format) {
2711         case DRM_FORMAT_C8:
2712                 dspcntr |= DISPPLANE_8BPP;
2713                 break;
2714         case DRM_FORMAT_XRGB1555:
2715                 dspcntr |= DISPPLANE_BGRX555;
2716                 break;
2717         case DRM_FORMAT_RGB565:
2718                 dspcntr |= DISPPLANE_BGRX565;
2719                 break;
2720         case DRM_FORMAT_XRGB8888:
2721                 dspcntr |= DISPPLANE_BGRX888;
2722                 break;
2723         case DRM_FORMAT_XBGR8888:
2724                 dspcntr |= DISPPLANE_RGBX888;
2725                 break;
2726         case DRM_FORMAT_XRGB2101010:
2727                 dspcntr |= DISPPLANE_BGRX101010;
2728                 break;
2729         case DRM_FORMAT_XBGR2101010:
2730                 dspcntr |= DISPPLANE_RGBX101010;
2731                 break;
2732         default:
2733                 BUG();
2734         }
2735
2736         if (INTEL_INFO(dev)->gen >= 4 &&
2737             obj->tiling_mode != I915_TILING_NONE)
2738                 dspcntr |= DISPPLANE_TILED;
2739
2740         if (IS_G4X(dev))
2741                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
2743         linear_offset = y * fb->pitches[0] + x * pixel_size;
2744
2745         if (INTEL_INFO(dev)->gen >= 4) {
2746                 intel_crtc->dspaddr_offset =
2747                         intel_gen4_compute_page_offset(dev_priv,
2748                                                        &x, &y, obj->tiling_mode,
2749                                                        pixel_size,
2750                                                        fb->pitches[0]);
2751                 linear_offset -= intel_crtc->dspaddr_offset;
2752         } else {
2753                 intel_crtc->dspaddr_offset = linear_offset;
2754         }
2755
2756         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2757                 dspcntr |= DISPPLANE_ROTATE_180;
2758
2759                 x += (intel_crtc->config->pipe_src_w - 1);
2760                 y += (intel_crtc->config->pipe_src_h - 1);
2761
2762                 /* Finding the last pixel of the last line of the display
2763                 data and adding to linear_offset*/
2764                 linear_offset +=
2765                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2767         }
2768
2769         I915_WRITE(reg, dspcntr);
2770
2771         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2772         if (INTEL_INFO(dev)->gen >= 4) {
2773                 I915_WRITE(DSPSURF(plane),
2774                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2775                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2776                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2777         } else
2778                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779         POSTING_READ(reg);
2780 }
2781
2782 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783                                           struct drm_framebuffer *fb,
2784                                           int x, int y)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         struct drm_plane *primary = crtc->primary;
2790         bool visible = to_intel_plane_state(primary->state)->visible;
2791         struct drm_i915_gem_object *obj;
2792         int plane = intel_crtc->plane;
2793         unsigned long linear_offset;
2794         u32 dspcntr;
2795         u32 reg = DSPCNTR(plane);
2796         int pixel_size;
2797
2798         if (!visible || !fb) {
2799                 I915_WRITE(reg, 0);
2800                 I915_WRITE(DSPSURF(plane), 0);
2801                 POSTING_READ(reg);
2802                 return;
2803         }
2804
2805         obj = intel_fb_obj(fb);
2806         if (WARN_ON(obj == NULL))
2807                 return;
2808
2809         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
2811         dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
2813         dspcntr |= DISPLAY_PLANE_ENABLE;
2814
2815         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2817
2818         switch (fb->pixel_format) {
2819         case DRM_FORMAT_C8:
2820                 dspcntr |= DISPPLANE_8BPP;
2821                 break;
2822         case DRM_FORMAT_RGB565:
2823                 dspcntr |= DISPPLANE_BGRX565;
2824                 break;
2825         case DRM_FORMAT_XRGB8888:
2826                 dspcntr |= DISPPLANE_BGRX888;
2827                 break;
2828         case DRM_FORMAT_XBGR8888:
2829                 dspcntr |= DISPPLANE_RGBX888;
2830                 break;
2831         case DRM_FORMAT_XRGB2101010:
2832                 dspcntr |= DISPPLANE_BGRX101010;
2833                 break;
2834         case DRM_FORMAT_XBGR2101010:
2835                 dspcntr |= DISPPLANE_RGBX101010;
2836                 break;
2837         default:
2838                 BUG();
2839         }
2840
2841         if (obj->tiling_mode != I915_TILING_NONE)
2842                 dspcntr |= DISPPLANE_TILED;
2843
2844         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2845                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2846
2847         linear_offset = y * fb->pitches[0] + x * pixel_size;
2848         intel_crtc->dspaddr_offset =
2849                 intel_gen4_compute_page_offset(dev_priv,
2850                                                &x, &y, obj->tiling_mode,
2851                                                pixel_size,
2852                                                fb->pitches[0]);
2853         linear_offset -= intel_crtc->dspaddr_offset;
2854         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2855                 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2858                         x += (intel_crtc->config->pipe_src_w - 1);
2859                         y += (intel_crtc->config->pipe_src_h - 1);
2860
2861                         /* Finding the last pixel of the last line of the display
2862                         data and adding to linear_offset*/
2863                         linear_offset +=
2864                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866                 }
2867         }
2868
2869         I915_WRITE(reg, dspcntr);
2870
2871         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2872         I915_WRITE(DSPSURF(plane),
2873                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2874         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2875                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876         } else {
2877                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879         }
2880         POSTING_READ(reg);
2881 }
2882
2883 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884                               uint32_t pixel_format)
2885 {
2886         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888         /*
2889          * The stride is either expressed as a multiple of 64 bytes
2890          * chunks for linear buffers or in number of tiles for tiled
2891          * buffers.
2892          */
2893         switch (fb_modifier) {
2894         case DRM_FORMAT_MOD_NONE:
2895                 return 64;
2896         case I915_FORMAT_MOD_X_TILED:
2897                 if (INTEL_INFO(dev)->gen == 2)
2898                         return 128;
2899                 return 512;
2900         case I915_FORMAT_MOD_Y_TILED:
2901                 /* No need to check for old gens and Y tiling since this is
2902                  * about the display engine and those will be blocked before
2903                  * we get here.
2904                  */
2905                 return 128;
2906         case I915_FORMAT_MOD_Yf_TILED:
2907                 if (bits_per_pixel == 8)
2908                         return 64;
2909                 else
2910                         return 128;
2911         default:
2912                 MISSING_CASE(fb_modifier);
2913                 return 64;
2914         }
2915 }
2916
2917 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2918                                      struct drm_i915_gem_object *obj)
2919 {
2920         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2921
2922         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2923                 view = &i915_ggtt_view_rotated;
2924
2925         return i915_gem_obj_ggtt_offset_view(obj, view);
2926 }
2927
2928 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2929 {
2930         struct drm_device *dev = intel_crtc->base.dev;
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2934         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2935         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2936 }
2937
2938 /*
2939  * This function detaches (aka. unbinds) unused scalers in hardware
2940  */
2941 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2942 {
2943         struct intel_crtc_scaler_state *scaler_state;
2944         int i;
2945
2946         scaler_state = &intel_crtc->config->scaler_state;
2947
2948         /* loop through and disable scalers that aren't in use */
2949         for (i = 0; i < intel_crtc->num_scalers; i++) {
2950                 if (!scaler_state->scalers[i].in_use)
2951                         skl_detach_scaler(intel_crtc, i);
2952         }
2953 }
2954
2955 u32 skl_plane_ctl_format(uint32_t pixel_format)
2956 {
2957         switch (pixel_format) {
2958         case DRM_FORMAT_C8:
2959                 return PLANE_CTL_FORMAT_INDEXED;
2960         case DRM_FORMAT_RGB565:
2961                 return PLANE_CTL_FORMAT_RGB_565;
2962         case DRM_FORMAT_XBGR8888:
2963                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2964         case DRM_FORMAT_XRGB8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888;
2966         /*
2967          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2968          * to be already pre-multiplied. We need to add a knob (or a different
2969          * DRM_FORMAT) for user-space to configure that.
2970          */
2971         case DRM_FORMAT_ABGR8888:
2972                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2973                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974         case DRM_FORMAT_ARGB8888:
2975                 return PLANE_CTL_FORMAT_XRGB_8888 |
2976                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2977         case DRM_FORMAT_XRGB2101010:
2978                 return PLANE_CTL_FORMAT_XRGB_2101010;
2979         case DRM_FORMAT_XBGR2101010:
2980                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2981         case DRM_FORMAT_YUYV:
2982                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2983         case DRM_FORMAT_YVYU:
2984                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2985         case DRM_FORMAT_UYVY:
2986                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2987         case DRM_FORMAT_VYUY:
2988                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2989         default:
2990                 MISSING_CASE(pixel_format);
2991         }
2992
2993         return 0;
2994 }
2995
2996 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2997 {
2998         switch (fb_modifier) {
2999         case DRM_FORMAT_MOD_NONE:
3000                 break;
3001         case I915_FORMAT_MOD_X_TILED:
3002                 return PLANE_CTL_TILED_X;
3003         case I915_FORMAT_MOD_Y_TILED:
3004                 return PLANE_CTL_TILED_Y;
3005         case I915_FORMAT_MOD_Yf_TILED:
3006                 return PLANE_CTL_TILED_YF;
3007         default:
3008                 MISSING_CASE(fb_modifier);
3009         }
3010
3011         return 0;
3012 }
3013
3014 u32 skl_plane_ctl_rotation(unsigned int rotation)
3015 {
3016         switch (rotation) {
3017         case BIT(DRM_ROTATE_0):
3018                 break;
3019         /*
3020          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3021          * while i915 HW rotation is clockwise, thats why this swapping.
3022          */
3023         case BIT(DRM_ROTATE_90):
3024                 return PLANE_CTL_ROTATE_270;
3025         case BIT(DRM_ROTATE_180):
3026                 return PLANE_CTL_ROTATE_180;
3027         case BIT(DRM_ROTATE_270):
3028                 return PLANE_CTL_ROTATE_90;
3029         default:
3030                 MISSING_CASE(rotation);
3031         }
3032
3033         return 0;
3034 }
3035
3036 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3037                                          struct drm_framebuffer *fb,
3038                                          int x, int y)
3039 {
3040         struct drm_device *dev = crtc->dev;
3041         struct drm_i915_private *dev_priv = dev->dev_private;
3042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043         struct drm_plane *plane = crtc->primary;
3044         bool visible = to_intel_plane_state(plane->state)->visible;
3045         struct drm_i915_gem_object *obj;
3046         int pipe = intel_crtc->pipe;
3047         u32 plane_ctl, stride_div, stride;
3048         u32 tile_height, plane_offset, plane_size;
3049         unsigned int rotation;
3050         int x_offset, y_offset;
3051         unsigned long surf_addr;
3052         struct intel_crtc_state *crtc_state = intel_crtc->config;
3053         struct intel_plane_state *plane_state;
3054         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3055         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3056         int scaler_id = -1;
3057
3058         plane_state = to_intel_plane_state(plane->state);
3059
3060         if (!visible || !fb) {
3061                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3062                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3063                 POSTING_READ(PLANE_CTL(pipe, 0));
3064                 return;
3065         }
3066
3067         plane_ctl = PLANE_CTL_ENABLE |
3068                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3069                     PLANE_CTL_PIPE_CSC_ENABLE;
3070
3071         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3072         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3073         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3074
3075         rotation = plane->state->rotation;
3076         plane_ctl |= skl_plane_ctl_rotation(rotation);
3077
3078         obj = intel_fb_obj(fb);
3079         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3080                                                fb->pixel_format);
3081         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3082
3083         /*
3084          * FIXME: intel_plane_state->src, dst aren't set when transitional
3085          * update_plane helpers are called from legacy paths.
3086          * Once full atomic crtc is available, below check can be avoided.
3087          */
3088         if (drm_rect_width(&plane_state->src)) {
3089                 scaler_id = plane_state->scaler_id;
3090                 src_x = plane_state->src.x1 >> 16;
3091                 src_y = plane_state->src.y1 >> 16;
3092                 src_w = drm_rect_width(&plane_state->src) >> 16;
3093                 src_h = drm_rect_height(&plane_state->src) >> 16;
3094                 dst_x = plane_state->dst.x1;
3095                 dst_y = plane_state->dst.y1;
3096                 dst_w = drm_rect_width(&plane_state->dst);
3097                 dst_h = drm_rect_height(&plane_state->dst);
3098
3099                 WARN_ON(x != src_x || y != src_y);
3100         } else {
3101                 src_w = intel_crtc->config->pipe_src_w;
3102                 src_h = intel_crtc->config->pipe_src_h;
3103         }
3104
3105         if (intel_rotation_90_or_270(rotation)) {
3106                 /* stride = Surface height in tiles */
3107                 tile_height = intel_tile_height(dev, fb->pixel_format,
3108                                                 fb->modifier[0]);
3109                 stride = DIV_ROUND_UP(fb->height, tile_height);
3110                 x_offset = stride * tile_height - y - src_h;
3111                 y_offset = x;
3112                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3113         } else {
3114                 stride = fb->pitches[0] / stride_div;
3115                 x_offset = x;
3116                 y_offset = y;
3117                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3118         }
3119         plane_offset = y_offset << 16 | x_offset;
3120
3121         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3122         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3125
3126         if (scaler_id >= 0) {
3127                 uint32_t ps_ctrl = 0;
3128
3129                 WARN_ON(!dst_w || !dst_h);
3130                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131                         crtc_state->scaler_state.scalers[scaler_id].mode;
3132                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137         } else {
3138                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3139         }
3140
3141         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3142
3143         POSTING_READ(PLANE_SURF(pipe, 0));
3144 }
3145
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3147 static int
3148 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149                            int x, int y, enum mode_set_atomic state)
3150 {
3151         struct drm_device *dev = crtc->dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153
3154         if (dev_priv->fbc.disable_fbc)
3155                 dev_priv->fbc.disable_fbc(dev_priv);
3156
3157         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3158
3159         return 0;
3160 }
3161
3162 static void intel_complete_page_flips(struct drm_device *dev)
3163 {
3164         struct drm_crtc *crtc;
3165
3166         for_each_crtc(dev, crtc) {
3167                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168                 enum plane plane = intel_crtc->plane;
3169
3170                 intel_prepare_page_flip(dev, plane);
3171                 intel_finish_page_flip_plane(dev, plane);
3172         }
3173 }
3174
3175 static void intel_update_primary_planes(struct drm_device *dev)
3176 {
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178         struct drm_crtc *crtc;
3179
3180         for_each_crtc(dev, crtc) {
3181                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182
3183                 drm_modeset_lock(&crtc->mutex, NULL);
3184                 /*
3185                  * FIXME: Once we have proper support for primary planes (and
3186                  * disabling them without disabling the entire crtc) allow again
3187                  * a NULL crtc->primary->fb.
3188                  */
3189                 if (intel_crtc->active && crtc->primary->fb)
3190                         dev_priv->display.update_primary_plane(crtc,
3191                                                                crtc->primary->fb,
3192                                                                crtc->x,
3193                                                                crtc->y);
3194                 drm_modeset_unlock(&crtc->mutex);
3195         }
3196 }
3197
3198 void intel_prepare_reset(struct drm_device *dev)
3199 {
3200         /* no reset support for gen2 */
3201         if (IS_GEN2(dev))
3202                 return;
3203
3204         /* reset doesn't touch the display */
3205         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3206                 return;
3207
3208         drm_modeset_lock_all(dev);
3209         /*
3210          * Disabling the crtcs gracefully seems nicer. Also the
3211          * g33 docs say we should at least disable all the planes.
3212          */
3213         intel_display_suspend(dev);
3214 }
3215
3216 void intel_finish_reset(struct drm_device *dev)
3217 {
3218         struct drm_i915_private *dev_priv = to_i915(dev);
3219
3220         /*
3221          * Flips in the rings will be nuked by the reset,
3222          * so complete all pending flips so that user space
3223          * will get its events and not get stuck.
3224          */
3225         intel_complete_page_flips(dev);
3226
3227         /* no reset support for gen2 */
3228         if (IS_GEN2(dev))
3229                 return;
3230
3231         /* reset doesn't touch the display */
3232         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3233                 /*
3234                  * Flips in the rings have been nuked by the reset,
3235                  * so update the base address of all primary
3236                  * planes to the the last fb to make sure we're
3237                  * showing the correct fb after a reset.
3238                  */
3239                 intel_update_primary_planes(dev);
3240                 return;
3241         }
3242
3243         /*
3244          * The display has been reset as well,
3245          * so need a full re-initialization.
3246          */
3247         intel_runtime_pm_disable_interrupts(dev_priv);
3248         intel_runtime_pm_enable_interrupts(dev_priv);
3249
3250         intel_modeset_init_hw(dev);
3251
3252         spin_lock_irq(&dev_priv->irq_lock);
3253         if (dev_priv->display.hpd_irq_setup)
3254                 dev_priv->display.hpd_irq_setup(dev);
3255         spin_unlock_irq(&dev_priv->irq_lock);
3256
3257         intel_display_resume(dev);
3258
3259         intel_hpd_init(dev_priv);
3260
3261         drm_modeset_unlock_all(dev);
3262 }
3263
3264 static void
3265 intel_finish_fb(struct drm_framebuffer *old_fb)
3266 {
3267         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3268         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3269         bool was_interruptible = dev_priv->mm.interruptible;
3270         int ret;
3271
3272         /* Big Hammer, we also need to ensure that any pending
3273          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3274          * current scanout is retired before unpinning the old
3275          * framebuffer. Note that we rely on userspace rendering
3276          * into the buffer attached to the pipe they are waiting
3277          * on. If not, userspace generates a GPU hang with IPEHR
3278          * point to the MI_WAIT_FOR_EVENT.
3279          *
3280          * This should only fail upon a hung GPU, in which case we
3281          * can safely continue.
3282          */
3283         dev_priv->mm.interruptible = false;
3284         ret = i915_gem_object_wait_rendering(obj, true);
3285         dev_priv->mm.interruptible = was_interruptible;
3286
3287         WARN_ON(ret);
3288 }
3289
3290 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3291 {
3292         struct drm_device *dev = crtc->dev;
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3295         bool pending;
3296
3297         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3298             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3299                 return false;
3300
3301         spin_lock_irq(&dev->event_lock);
3302         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3303         spin_unlock_irq(&dev->event_lock);
3304
3305         return pending;
3306 }
3307
3308 static void intel_update_pipe_size(struct intel_crtc *crtc)
3309 {
3310         struct drm_device *dev = crtc->base.dev;
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         const struct drm_display_mode *adjusted_mode;
3313
3314         if (!i915.fastboot)
3315                 return;
3316
3317         /*
3318          * Update pipe size and adjust fitter if needed: the reason for this is
3319          * that in compute_mode_changes we check the native mode (not the pfit
3320          * mode) to see if we can flip rather than do a full mode set. In the
3321          * fastboot case, we'll flip, but if we don't update the pipesrc and
3322          * pfit state, we'll end up with a big fb scanned out into the wrong
3323          * sized surface.
3324          *
3325          * To fix this properly, we need to hoist the checks up into
3326          * compute_mode_changes (or above), check the actual pfit state and
3327          * whether the platform allows pfit disable with pipe active, and only
3328          * then update the pipesrc and pfit state, even on the flip path.
3329          */
3330
3331         adjusted_mode = &crtc->config->base.adjusted_mode;
3332
3333         I915_WRITE(PIPESRC(crtc->pipe),
3334                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3335                    (adjusted_mode->crtc_vdisplay - 1));
3336         if (!crtc->config->pch_pfit.enabled &&
3337             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3338              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3339                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3340                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3341                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3342         }
3343         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3344         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3345 }
3346
3347 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348 {
3349         struct drm_device *dev = crtc->dev;
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352         int pipe = intel_crtc->pipe;
3353         u32 reg, temp;
3354
3355         /* enable normal train */
3356         reg = FDI_TX_CTL(pipe);
3357         temp = I915_READ(reg);
3358         if (IS_IVYBRIDGE(dev)) {
3359                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3360                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3361         } else {
3362                 temp &= ~FDI_LINK_TRAIN_NONE;
3363                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3364         }
3365         I915_WRITE(reg, temp);
3366
3367         reg = FDI_RX_CTL(pipe);
3368         temp = I915_READ(reg);
3369         if (HAS_PCH_CPT(dev)) {
3370                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3371                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3372         } else {
3373                 temp &= ~FDI_LINK_TRAIN_NONE;
3374                 temp |= FDI_LINK_TRAIN_NONE;
3375         }
3376         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3377
3378         /* wait one idle pattern time */
3379         POSTING_READ(reg);
3380         udelay(1000);
3381
3382         /* IVB wants error correction enabled */
3383         if (IS_IVYBRIDGE(dev))
3384                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3385                            FDI_FE_ERRC_ENABLE);
3386 }
3387
3388 /* The FDI link training functions for ILK/Ibexpeak. */
3389 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3390 {
3391         struct drm_device *dev = crtc->dev;
3392         struct drm_i915_private *dev_priv = dev->dev_private;
3393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394         int pipe = intel_crtc->pipe;
3395         u32 reg, temp, tries;
3396
3397         /* FDI needs bits from pipe first */
3398         assert_pipe_enabled(dev_priv, pipe);
3399
3400         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3401            for train result */
3402         reg = FDI_RX_IMR(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_RX_SYMBOL_LOCK;
3405         temp &= ~FDI_RX_BIT_LOCK;
3406         I915_WRITE(reg, temp);
3407         I915_READ(reg);
3408         udelay(150);
3409
3410         /* enable CPU FDI TX and PCH FDI RX */
3411         reg = FDI_TX_CTL(pipe);
3412         temp = I915_READ(reg);
3413         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3414         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3415         temp &= ~FDI_LINK_TRAIN_NONE;
3416         temp |= FDI_LINK_TRAIN_PATTERN_1;
3417         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3418
3419         reg = FDI_RX_CTL(pipe);
3420         temp = I915_READ(reg);
3421         temp &= ~FDI_LINK_TRAIN_NONE;
3422         temp |= FDI_LINK_TRAIN_PATTERN_1;
3423         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3424
3425         POSTING_READ(reg);
3426         udelay(150);
3427
3428         /* Ironlake workaround, enable clock pointer after FDI enable*/
3429         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3430         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3431                    FDI_RX_PHASE_SYNC_POINTER_EN);
3432
3433         reg = FDI_RX_IIR(pipe);
3434         for (tries = 0; tries < 5; tries++) {
3435                 temp = I915_READ(reg);
3436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3437
3438                 if ((temp & FDI_RX_BIT_LOCK)) {
3439                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3440                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441                         break;
3442                 }
3443         }
3444         if (tries == 5)
3445                 DRM_ERROR("FDI train 1 fail!\n");
3446
3447         /* Train 2 */
3448         reg = FDI_TX_CTL(pipe);
3449         temp = I915_READ(reg);
3450         temp &= ~FDI_LINK_TRAIN_NONE;
3451         temp |= FDI_LINK_TRAIN_PATTERN_2;
3452         I915_WRITE(reg, temp);
3453
3454         reg = FDI_RX_CTL(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_LINK_TRAIN_NONE;
3457         temp |= FDI_LINK_TRAIN_PATTERN_2;
3458         I915_WRITE(reg, temp);
3459
3460         POSTING_READ(reg);
3461         udelay(150);
3462
3463         reg = FDI_RX_IIR(pipe);
3464         for (tries = 0; tries < 5; tries++) {
3465                 temp = I915_READ(reg);
3466                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468                 if (temp & FDI_RX_SYMBOL_LOCK) {
3469                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3470                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3471                         break;
3472                 }
3473         }
3474         if (tries == 5)
3475                 DRM_ERROR("FDI train 2 fail!\n");
3476
3477         DRM_DEBUG_KMS("FDI train done\n");
3478
3479 }
3480
3481 static const int snb_b_fdi_train_param[] = {
3482         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3483         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3484         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3485         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3486 };
3487
3488 /* The FDI link training functions for SNB/Cougarpoint. */
3489 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3490 {
3491         struct drm_device *dev = crtc->dev;
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3494         int pipe = intel_crtc->pipe;
3495         u32 reg, temp, i, retry;
3496
3497         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3498            for train result */
3499         reg = FDI_RX_IMR(pipe);
3500         temp = I915_READ(reg);
3501         temp &= ~FDI_RX_SYMBOL_LOCK;
3502         temp &= ~FDI_RX_BIT_LOCK;
3503         I915_WRITE(reg, temp);
3504
3505         POSTING_READ(reg);
3506         udelay(150);
3507
3508         /* enable CPU FDI TX and PCH FDI RX */
3509         reg = FDI_TX_CTL(pipe);
3510         temp = I915_READ(reg);
3511         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3512         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3513         temp &= ~FDI_LINK_TRAIN_NONE;
3514         temp |= FDI_LINK_TRAIN_PATTERN_1;
3515         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3516         /* SNB-B */
3517         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3518         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3519
3520         I915_WRITE(FDI_RX_MISC(pipe),
3521                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3522
3523         reg = FDI_RX_CTL(pipe);
3524         temp = I915_READ(reg);
3525         if (HAS_PCH_CPT(dev)) {
3526                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3527                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3528         } else {
3529                 temp &= ~FDI_LINK_TRAIN_NONE;
3530                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3531         }
3532         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3533
3534         POSTING_READ(reg);
3535         udelay(150);
3536
3537         for (i = 0; i < 4; i++) {
3538                 reg = FDI_TX_CTL(pipe);
3539                 temp = I915_READ(reg);
3540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3541                 temp |= snb_b_fdi_train_param[i];
3542                 I915_WRITE(reg, temp);
3543
3544                 POSTING_READ(reg);
3545                 udelay(500);
3546
3547                 for (retry = 0; retry < 5; retry++) {
3548                         reg = FDI_RX_IIR(pipe);
3549                         temp = I915_READ(reg);
3550                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3551                         if (temp & FDI_RX_BIT_LOCK) {
3552                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3553                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3554                                 break;
3555                         }
3556                         udelay(50);
3557                 }
3558                 if (retry < 5)
3559                         break;
3560         }
3561         if (i == 4)
3562                 DRM_ERROR("FDI train 1 fail!\n");
3563
3564         /* Train 2 */
3565         reg = FDI_TX_CTL(pipe);
3566         temp = I915_READ(reg);
3567         temp &= ~FDI_LINK_TRAIN_NONE;
3568         temp |= FDI_LINK_TRAIN_PATTERN_2;
3569         if (IS_GEN6(dev)) {
3570                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571                 /* SNB-B */
3572                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3573         }
3574         I915_WRITE(reg, temp);
3575
3576         reg = FDI_RX_CTL(pipe);
3577         temp = I915_READ(reg);
3578         if (HAS_PCH_CPT(dev)) {
3579                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3580                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3581         } else {
3582                 temp &= ~FDI_LINK_TRAIN_NONE;
3583                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3584         }
3585         I915_WRITE(reg, temp);
3586
3587         POSTING_READ(reg);
3588         udelay(150);
3589
3590         for (i = 0; i < 4; i++) {
3591                 reg = FDI_TX_CTL(pipe);
3592                 temp = I915_READ(reg);
3593                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3594                 temp |= snb_b_fdi_train_param[i];
3595                 I915_WRITE(reg, temp);
3596
3597                 POSTING_READ(reg);
3598                 udelay(500);
3599
3600                 for (retry = 0; retry < 5; retry++) {
3601                         reg = FDI_RX_IIR(pipe);
3602                         temp = I915_READ(reg);
3603                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3604                         if (temp & FDI_RX_SYMBOL_LOCK) {
3605                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3606                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3607                                 break;
3608                         }
3609                         udelay(50);
3610                 }
3611                 if (retry < 5)
3612                         break;
3613         }
3614         if (i == 4)
3615                 DRM_ERROR("FDI train 2 fail!\n");
3616
3617         DRM_DEBUG_KMS("FDI train done.\n");
3618 }
3619
3620 /* Manual link training for Ivy Bridge A0 parts */
3621 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626         int pipe = intel_crtc->pipe;
3627         u32 reg, temp, i, j;
3628
3629         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3630            for train result */
3631         reg = FDI_RX_IMR(pipe);
3632         temp = I915_READ(reg);
3633         temp &= ~FDI_RX_SYMBOL_LOCK;
3634         temp &= ~FDI_RX_BIT_LOCK;
3635         I915_WRITE(reg, temp);
3636
3637         POSTING_READ(reg);
3638         udelay(150);
3639
3640         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3641                       I915_READ(FDI_RX_IIR(pipe)));
3642
3643         /* Try each vswing and preemphasis setting twice before moving on */
3644         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3645                 /* disable first in case we need to retry */
3646                 reg = FDI_TX_CTL(pipe);
3647                 temp = I915_READ(reg);
3648                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3649                 temp &= ~FDI_TX_ENABLE;
3650                 I915_WRITE(reg, temp);
3651
3652                 reg = FDI_RX_CTL(pipe);
3653                 temp = I915_READ(reg);
3654                 temp &= ~FDI_LINK_TRAIN_AUTO;
3655                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3656                 temp &= ~FDI_RX_ENABLE;
3657                 I915_WRITE(reg, temp);
3658
3659                 /* enable CPU FDI TX and PCH FDI RX */
3660                 reg = FDI_TX_CTL(pipe);
3661                 temp = I915_READ(reg);
3662                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3663                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3664                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3666                 temp |= snb_b_fdi_train_param[j/2];
3667                 temp |= FDI_COMPOSITE_SYNC;
3668                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3669
3670                 I915_WRITE(FDI_RX_MISC(pipe),
3671                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3672
3673                 reg = FDI_RX_CTL(pipe);
3674                 temp = I915_READ(reg);
3675                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3676                 temp |= FDI_COMPOSITE_SYNC;
3677                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3678
3679                 POSTING_READ(reg);
3680                 udelay(1); /* should be 0.5us */
3681
3682                 for (i = 0; i < 4; i++) {
3683                         reg = FDI_RX_IIR(pipe);
3684                         temp = I915_READ(reg);
3685                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3686
3687                         if (temp & FDI_RX_BIT_LOCK ||
3688                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3689                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3690                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3691                                               i);
3692                                 break;
3693                         }
3694                         udelay(1); /* should be 0.5us */
3695                 }
3696                 if (i == 4) {
3697                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3698                         continue;
3699                 }
3700
3701                 /* Train 2 */
3702                 reg = FDI_TX_CTL(pipe);
3703                 temp = I915_READ(reg);
3704                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3705                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3706                 I915_WRITE(reg, temp);
3707
3708                 reg = FDI_RX_CTL(pipe);
3709                 temp = I915_READ(reg);
3710                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3711                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3712                 I915_WRITE(reg, temp);
3713
3714                 POSTING_READ(reg);
3715                 udelay(2); /* should be 1.5us */
3716
3717                 for (i = 0; i < 4; i++) {
3718                         reg = FDI_RX_IIR(pipe);
3719                         temp = I915_READ(reg);
3720                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3721
3722                         if (temp & FDI_RX_SYMBOL_LOCK ||
3723                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3724                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3725                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3726                                               i);
3727                                 goto train_done;
3728                         }
3729                         udelay(2); /* should be 1.5us */
3730                 }
3731                 if (i == 4)
3732                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3733         }
3734
3735 train_done:
3736         DRM_DEBUG_KMS("FDI train done.\n");
3737 }
3738
3739 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3740 {
3741         struct drm_device *dev = intel_crtc->base.dev;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         int pipe = intel_crtc->pipe;
3744         u32 reg, temp;
3745
3746
3747         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3748         reg = FDI_RX_CTL(pipe);
3749         temp = I915_READ(reg);
3750         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3751         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3752         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3753         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3754
3755         POSTING_READ(reg);
3756         udelay(200);
3757
3758         /* Switch from Rawclk to PCDclk */
3759         temp = I915_READ(reg);
3760         I915_WRITE(reg, temp | FDI_PCDCLK);
3761
3762         POSTING_READ(reg);
3763         udelay(200);
3764
3765         /* Enable CPU FDI TX PLL, always on for Ironlake */
3766         reg = FDI_TX_CTL(pipe);
3767         temp = I915_READ(reg);
3768         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3769                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3770
3771                 POSTING_READ(reg);
3772                 udelay(100);
3773         }
3774 }
3775
3776 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3777 {
3778         struct drm_device *dev = intel_crtc->base.dev;
3779         struct drm_i915_private *dev_priv = dev->dev_private;
3780         int pipe = intel_crtc->pipe;
3781         u32 reg, temp;
3782
3783         /* Switch from PCDclk to Rawclk */
3784         reg = FDI_RX_CTL(pipe);
3785         temp = I915_READ(reg);
3786         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3787
3788         /* Disable CPU FDI TX PLL */
3789         reg = FDI_TX_CTL(pipe);
3790         temp = I915_READ(reg);
3791         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3792
3793         POSTING_READ(reg);
3794         udelay(100);
3795
3796         reg = FDI_RX_CTL(pipe);
3797         temp = I915_READ(reg);
3798         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3799
3800         /* Wait for the clocks to turn off. */
3801         POSTING_READ(reg);
3802         udelay(100);
3803 }
3804
3805 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3806 {
3807         struct drm_device *dev = crtc->dev;
3808         struct drm_i915_private *dev_priv = dev->dev_private;
3809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3810         int pipe = intel_crtc->pipe;
3811         u32 reg, temp;
3812
3813         /* disable CPU FDI tx and PCH FDI rx */
3814         reg = FDI_TX_CTL(pipe);
3815         temp = I915_READ(reg);
3816         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3817         POSTING_READ(reg);
3818
3819         reg = FDI_RX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         temp &= ~(0x7 << 16);
3822         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3823         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3824
3825         POSTING_READ(reg);
3826         udelay(100);
3827
3828         /* Ironlake workaround, disable clock pointer after downing FDI */
3829         if (HAS_PCH_IBX(dev))
3830                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3831
3832         /* still set train pattern 1 */
3833         reg = FDI_TX_CTL(pipe);
3834         temp = I915_READ(reg);
3835         temp &= ~FDI_LINK_TRAIN_NONE;
3836         temp |= FDI_LINK_TRAIN_PATTERN_1;
3837         I915_WRITE(reg, temp);
3838
3839         reg = FDI_RX_CTL(pipe);
3840         temp = I915_READ(reg);
3841         if (HAS_PCH_CPT(dev)) {
3842                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3843                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3844         } else {
3845                 temp &= ~FDI_LINK_TRAIN_NONE;
3846                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3847         }
3848         /* BPC in FDI rx is consistent with that in PIPECONF */
3849         temp &= ~(0x07 << 16);
3850         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3851         I915_WRITE(reg, temp);
3852
3853         POSTING_READ(reg);
3854         udelay(100);
3855 }
3856
3857 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3858 {
3859         struct intel_crtc *crtc;
3860
3861         /* Note that we don't need to be called with mode_config.lock here
3862          * as our list of CRTC objects is static for the lifetime of the
3863          * device and so cannot disappear as we iterate. Similarly, we can
3864          * happily treat the predicates as racy, atomic checks as userspace
3865          * cannot claim and pin a new fb without at least acquring the
3866          * struct_mutex and so serialising with us.
3867          */
3868         for_each_intel_crtc(dev, crtc) {
3869                 if (atomic_read(&crtc->unpin_work_count) == 0)
3870                         continue;
3871
3872                 if (crtc->unpin_work)
3873                         intel_wait_for_vblank(dev, crtc->pipe);
3874
3875                 return true;
3876         }
3877
3878         return false;
3879 }
3880
3881 static void page_flip_completed(struct intel_crtc *intel_crtc)
3882 {
3883         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3884         struct intel_unpin_work *work = intel_crtc->unpin_work;
3885
3886         /* ensure that the unpin work is consistent wrt ->pending. */
3887         smp_rmb();
3888         intel_crtc->unpin_work = NULL;
3889
3890         if (work->event)
3891                 drm_send_vblank_event(intel_crtc->base.dev,
3892                                       intel_crtc->pipe,
3893                                       work->event);
3894
3895         drm_crtc_vblank_put(&intel_crtc->base);
3896
3897         wake_up_all(&dev_priv->pending_flip_queue);
3898         queue_work(dev_priv->wq, &work->work);
3899
3900         trace_i915_flip_complete(intel_crtc->plane,
3901                                  work->pending_flip_obj);
3902 }
3903
3904 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3905 {
3906         struct drm_device *dev = crtc->dev;
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3910         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3911                                        !intel_crtc_has_pending_flip(crtc),
3912                                        60*HZ) == 0)) {
3913                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3914
3915                 spin_lock_irq(&dev->event_lock);
3916                 if (intel_crtc->unpin_work) {
3917                         WARN_ONCE(1, "Removing stuck page flip\n");
3918                         page_flip_completed(intel_crtc);
3919                 }
3920                 spin_unlock_irq(&dev->event_lock);
3921         }
3922
3923         if (crtc->primary->fb) {
3924                 mutex_lock(&dev->struct_mutex);
3925                 intel_finish_fb(crtc->primary->fb);
3926                 mutex_unlock(&dev->struct_mutex);
3927         }
3928 }
3929
3930 /* Program iCLKIP clock to the desired frequency */
3931 static void lpt_program_iclkip(struct drm_crtc *crtc)
3932 {
3933         struct drm_device *dev = crtc->dev;
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3936         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3937         u32 temp;
3938
3939         mutex_lock(&dev_priv->sb_lock);
3940
3941         /* It is necessary to ungate the pixclk gate prior to programming
3942          * the divisors, and gate it back when it is done.
3943          */
3944         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945
3946         /* Disable SSCCTL */
3947         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3948                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3949                                 SBI_SSCCTL_DISABLE,
3950                         SBI_ICLK);
3951
3952         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3953         if (clock == 20000) {
3954                 auxdiv = 1;
3955                 divsel = 0x41;
3956                 phaseinc = 0x20;
3957         } else {
3958                 /* The iCLK virtual clock root frequency is in MHz,
3959                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3960                  * divisors, it is necessary to divide one by another, so we
3961                  * convert the virtual clock precision to KHz here for higher
3962                  * precision.
3963                  */
3964                 u32 iclk_virtual_root_freq = 172800 * 1000;
3965                 u32 iclk_pi_range = 64;
3966                 u32 desired_divisor, msb_divisor_value, pi_value;
3967
3968                 desired_divisor = (iclk_virtual_root_freq / clock);
3969                 msb_divisor_value = desired_divisor / iclk_pi_range;
3970                 pi_value = desired_divisor % iclk_pi_range;
3971
3972                 auxdiv = 0;
3973                 divsel = msb_divisor_value - 2;
3974                 phaseinc = pi_value;
3975         }
3976
3977         /* This should not happen with any sane values */
3978         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3979                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3980         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3981                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3982
3983         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3984                         clock,
3985                         auxdiv,
3986                         divsel,
3987                         phasedir,
3988                         phaseinc);
3989
3990         /* Program SSCDIVINTPHASE6 */
3991         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3992         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3993         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3994         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3995         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3996         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3997         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3998         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3999
4000         /* Program SSCAUXDIV */
4001         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4002         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4003         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4004         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4005
4006         /* Enable modulator and associated divider */
4007         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4008         temp &= ~SBI_SSCCTL_DISABLE;
4009         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4010
4011         /* Wait for initialization time */
4012         udelay(24);
4013
4014         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4015
4016         mutex_unlock(&dev_priv->sb_lock);
4017 }
4018
4019 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4020                                                 enum pipe pch_transcoder)
4021 {
4022         struct drm_device *dev = crtc->base.dev;
4023         struct drm_i915_private *dev_priv = dev->dev_private;
4024         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4025
4026         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4027                    I915_READ(HTOTAL(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4029                    I915_READ(HBLANK(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4031                    I915_READ(HSYNC(cpu_transcoder)));
4032
4033         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4034                    I915_READ(VTOTAL(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4036                    I915_READ(VBLANK(cpu_transcoder)));
4037         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4038                    I915_READ(VSYNC(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4040                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4041 }
4042
4043 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4044 {
4045         struct drm_i915_private *dev_priv = dev->dev_private;
4046         uint32_t temp;
4047
4048         temp = I915_READ(SOUTH_CHICKEN1);
4049         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4050                 return;
4051
4052         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4053         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4054
4055         temp &= ~FDI_BC_BIFURCATION_SELECT;
4056         if (enable)
4057                 temp |= FDI_BC_BIFURCATION_SELECT;
4058
4059         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4060         I915_WRITE(SOUTH_CHICKEN1, temp);
4061         POSTING_READ(SOUTH_CHICKEN1);
4062 }
4063
4064 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4065 {
4066         struct drm_device *dev = intel_crtc->base.dev;
4067
4068         switch (intel_crtc->pipe) {
4069         case PIPE_A:
4070                 break;
4071         case PIPE_B:
4072                 if (intel_crtc->config->fdi_lanes > 2)
4073                         cpt_set_fdi_bc_bifurcation(dev, false);
4074                 else
4075                         cpt_set_fdi_bc_bifurcation(dev, true);
4076
4077                 break;
4078         case PIPE_C:
4079                 cpt_set_fdi_bc_bifurcation(dev, true);
4080
4081                 break;
4082         default:
4083                 BUG();
4084         }
4085 }
4086
4087 /*
4088  * Enable PCH resources required for PCH ports:
4089  *   - PCH PLLs
4090  *   - FDI training & RX/TX
4091  *   - update transcoder timings
4092  *   - DP transcoding bits
4093  *   - transcoder
4094  */
4095 static void ironlake_pch_enable(struct drm_crtc *crtc)
4096 {
4097         struct drm_device *dev = crtc->dev;
4098         struct drm_i915_private *dev_priv = dev->dev_private;
4099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4100         int pipe = intel_crtc->pipe;
4101         u32 reg, temp;
4102
4103         assert_pch_transcoder_disabled(dev_priv, pipe);
4104
4105         if (IS_IVYBRIDGE(dev))
4106                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4107
4108         /* Write the TU size bits before fdi link training, so that error
4109          * detection works. */
4110         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4111                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4112
4113         /* For PCH output, training FDI link */
4114         dev_priv->display.fdi_link_train(crtc);
4115
4116         /* We need to program the right clock selection before writing the pixel
4117          * mutliplier into the DPLL. */
4118         if (HAS_PCH_CPT(dev)) {
4119                 u32 sel;
4120
4121                 temp = I915_READ(PCH_DPLL_SEL);
4122                 temp |= TRANS_DPLL_ENABLE(pipe);
4123                 sel = TRANS_DPLLB_SEL(pipe);
4124                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4125                         temp |= sel;
4126                 else
4127                         temp &= ~sel;
4128                 I915_WRITE(PCH_DPLL_SEL, temp);
4129         }
4130
4131         /* XXX: pch pll's can be enabled any time before we enable the PCH
4132          * transcoder, and we actually should do this to not upset any PCH
4133          * transcoder that already use the clock when we share it.
4134          *
4135          * Note that enable_shared_dpll tries to do the right thing, but
4136          * get_shared_dpll unconditionally resets the pll - we need that to have
4137          * the right LVDS enable sequence. */
4138         intel_enable_shared_dpll(intel_crtc);
4139
4140         /* set transcoder timing, panel must allow it */
4141         assert_panel_unlocked(dev_priv, pipe);
4142         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4143
4144         intel_fdi_normal_train(crtc);
4145
4146         /* For PCH DP, enable TRANS_DP_CTL */
4147         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4148                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4149                 reg = TRANS_DP_CTL(pipe);
4150                 temp = I915_READ(reg);
4151                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4152                           TRANS_DP_SYNC_MASK |
4153                           TRANS_DP_BPC_MASK);
4154                 temp |= TRANS_DP_OUTPUT_ENABLE;
4155                 temp |= bpc << 9; /* same format but at 11:9 */
4156
4157                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4158                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4159                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4160                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4161
4162                 switch (intel_trans_dp_port_sel(crtc)) {
4163                 case PCH_DP_B:
4164                         temp |= TRANS_DP_PORT_SEL_B;
4165                         break;
4166                 case PCH_DP_C:
4167                         temp |= TRANS_DP_PORT_SEL_C;
4168                         break;
4169                 case PCH_DP_D:
4170                         temp |= TRANS_DP_PORT_SEL_D;
4171                         break;
4172                 default:
4173                         BUG();
4174                 }
4175
4176                 I915_WRITE(reg, temp);
4177         }
4178
4179         ironlake_enable_pch_transcoder(dev_priv, pipe);
4180 }
4181
4182 static void lpt_pch_enable(struct drm_crtc *crtc)
4183 {
4184         struct drm_device *dev = crtc->dev;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4187         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4188
4189         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4190
4191         lpt_program_iclkip(crtc);
4192
4193         /* Set transcoder timing. */
4194         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4195
4196         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4197 }
4198
4199 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4200                                                 struct intel_crtc_state *crtc_state)
4201 {
4202         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4203         struct intel_shared_dpll *pll;
4204         struct intel_shared_dpll_config *shared_dpll;
4205         enum intel_dpll_id i;
4206
4207         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4208
4209         if (HAS_PCH_IBX(dev_priv->dev)) {
4210                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4211                 i = (enum intel_dpll_id) crtc->pipe;
4212                 pll = &dev_priv->shared_dplls[i];
4213
4214                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4215                               crtc->base.base.id, pll->name);
4216
4217                 WARN_ON(shared_dpll[i].crtc_mask);
4218
4219                 goto found;
4220         }
4221
4222         if (IS_BROXTON(dev_priv->dev)) {
4223                 /* PLL is attached to port in bxt */
4224                 struct intel_encoder *encoder;
4225                 struct intel_digital_port *intel_dig_port;
4226
4227                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4228                 if (WARN_ON(!encoder))
4229                         return NULL;
4230
4231                 intel_dig_port = enc_to_dig_port(&encoder->base);
4232                 /* 1:1 mapping between ports and PLLs */
4233                 i = (enum intel_dpll_id)intel_dig_port->port;
4234                 pll = &dev_priv->shared_dplls[i];
4235                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236                         crtc->base.base.id, pll->name);
4237                 WARN_ON(shared_dpll[i].crtc_mask);
4238
4239                 goto found;
4240         }
4241
4242         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4243                 pll = &dev_priv->shared_dplls[i];
4244
4245                 /* Only want to check enabled timings first */
4246                 if (shared_dpll[i].crtc_mask == 0)
4247                         continue;
4248
4249                 if (memcmp(&crtc_state->dpll_hw_state,
4250                            &shared_dpll[i].hw_state,
4251                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4252                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4253                                       crtc->base.base.id, pll->name,
4254                                       shared_dpll[i].crtc_mask,
4255                                       pll->active);
4256                         goto found;
4257                 }
4258         }
4259
4260         /* Ok no matching timings, maybe there's a free one? */
4261         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4262                 pll = &dev_priv->shared_dplls[i];
4263                 if (shared_dpll[i].crtc_mask == 0) {
4264                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4265                                       crtc->base.base.id, pll->name);
4266                         goto found;
4267                 }
4268         }
4269
4270         return NULL;
4271
4272 found:
4273         if (shared_dpll[i].crtc_mask == 0)
4274                 shared_dpll[i].hw_state =
4275                         crtc_state->dpll_hw_state;
4276
4277         crtc_state->shared_dpll = i;
4278         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4279                          pipe_name(crtc->pipe));
4280
4281         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4282
4283         return pll;
4284 }
4285
4286 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4287 {
4288         struct drm_i915_private *dev_priv = to_i915(state->dev);
4289         struct intel_shared_dpll_config *shared_dpll;
4290         struct intel_shared_dpll *pll;
4291         enum intel_dpll_id i;
4292
4293         if (!to_intel_atomic_state(state)->dpll_set)
4294                 return;
4295
4296         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4297         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298                 pll = &dev_priv->shared_dplls[i];
4299                 pll->config = shared_dpll[i];
4300         }
4301 }
4302
4303 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4304 {
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         int dslreg = PIPEDSL(pipe);
4307         u32 temp;
4308
4309         temp = I915_READ(dslreg);
4310         udelay(500);
4311         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4312                 if (wait_for(I915_READ(dslreg) != temp, 5))
4313                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4314         }
4315 }
4316
4317 static int
4318 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4319                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4320                   int src_w, int src_h, int dst_w, int dst_h)
4321 {
4322         struct intel_crtc_scaler_state *scaler_state =
4323                 &crtc_state->scaler_state;
4324         struct intel_crtc *intel_crtc =
4325                 to_intel_crtc(crtc_state->base.crtc);
4326         int need_scaling;
4327
4328         need_scaling = intel_rotation_90_or_270(rotation) ?
4329                 (src_h != dst_w || src_w != dst_h):
4330                 (src_w != dst_w || src_h != dst_h);
4331
4332         /*
4333          * if plane is being disabled or scaler is no more required or force detach
4334          *  - free scaler binded to this plane/crtc
4335          *  - in order to do this, update crtc->scaler_usage
4336          *
4337          * Here scaler state in crtc_state is set free so that
4338          * scaler can be assigned to other user. Actual register
4339          * update to free the scaler is done in plane/panel-fit programming.
4340          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4341          */
4342         if (force_detach || !need_scaling) {
4343                 if (*scaler_id >= 0) {
4344                         scaler_state->scaler_users &= ~(1 << scaler_user);
4345                         scaler_state->scalers[*scaler_id].in_use = 0;
4346
4347                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4348                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4349                                 intel_crtc->pipe, scaler_user, *scaler_id,
4350                                 scaler_state->scaler_users);
4351                         *scaler_id = -1;
4352                 }
4353                 return 0;
4354         }
4355
4356         /* range checks */
4357         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4358                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4359
4360                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4361                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4362                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4363                         "size is out of scaler range\n",
4364                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4365                 return -EINVAL;
4366         }
4367
4368         /* mark this plane as a scaler user in crtc_state */
4369         scaler_state->scaler_users |= (1 << scaler_user);
4370         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4371                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4372                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4373                 scaler_state->scaler_users);
4374
4375         return 0;
4376 }
4377
4378 /**
4379  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4380  *
4381  * @state: crtc's scaler state
4382  *
4383  * Return
4384  *     0 - scaler_usage updated successfully
4385  *    error - requested scaling cannot be supported or other error condition
4386  */
4387 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4388 {
4389         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4390         struct drm_display_mode *adjusted_mode =
4391                 &state->base.adjusted_mode;
4392
4393         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4394                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4395
4396         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4397                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4398                 state->pipe_src_w, state->pipe_src_h,
4399                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4400 }
4401
4402 /**
4403  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4404  *
4405  * @state: crtc's scaler state
4406  * @plane_state: atomic plane state to update
4407  *
4408  * Return
4409  *     0 - scaler_usage updated successfully
4410  *    error - requested scaling cannot be supported or other error condition
4411  */
4412 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4413                                    struct intel_plane_state *plane_state)
4414 {
4415
4416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4417         struct intel_plane *intel_plane =
4418                 to_intel_plane(plane_state->base.plane);
4419         struct drm_framebuffer *fb = plane_state->base.fb;
4420         int ret;
4421
4422         bool force_detach = !fb || !plane_state->visible;
4423
4424         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4425                       intel_plane->base.base.id, intel_crtc->pipe,
4426                       drm_plane_index(&intel_plane->base));
4427
4428         ret = skl_update_scaler(crtc_state, force_detach,
4429                                 drm_plane_index(&intel_plane->base),
4430                                 &plane_state->scaler_id,
4431                                 plane_state->base.rotation,
4432                                 drm_rect_width(&plane_state->src) >> 16,
4433                                 drm_rect_height(&plane_state->src) >> 16,
4434                                 drm_rect_width(&plane_state->dst),
4435                                 drm_rect_height(&plane_state->dst));
4436
4437         if (ret || plane_state->scaler_id < 0)
4438                 return ret;
4439
4440         /* check colorkey */
4441         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4442                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4443                               intel_plane->base.base.id);
4444                 return -EINVAL;
4445         }
4446
4447         /* Check src format */
4448         switch (fb->pixel_format) {
4449         case DRM_FORMAT_RGB565:
4450         case DRM_FORMAT_XBGR8888:
4451         case DRM_FORMAT_XRGB8888:
4452         case DRM_FORMAT_ABGR8888:
4453         case DRM_FORMAT_ARGB8888:
4454         case DRM_FORMAT_XRGB2101010:
4455         case DRM_FORMAT_XBGR2101010:
4456         case DRM_FORMAT_YUYV:
4457         case DRM_FORMAT_YVYU:
4458         case DRM_FORMAT_UYVY:
4459         case DRM_FORMAT_VYUY:
4460                 break;
4461         default:
4462                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4463                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4464                 return -EINVAL;
4465         }
4466
4467         return 0;
4468 }
4469
4470 static void skylake_scaler_disable(struct intel_crtc *crtc)
4471 {
4472         int i;
4473
4474         for (i = 0; i < crtc->num_scalers; i++)
4475                 skl_detach_scaler(crtc, i);
4476 }
4477
4478 static void skylake_pfit_enable(struct intel_crtc *crtc)
4479 {
4480         struct drm_device *dev = crtc->base.dev;
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482         int pipe = crtc->pipe;
4483         struct intel_crtc_scaler_state *scaler_state =
4484                 &crtc->config->scaler_state;
4485
4486         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4487
4488         if (crtc->config->pch_pfit.enabled) {
4489                 int id;
4490
4491                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4492                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4493                         return;
4494                 }
4495
4496                 id = scaler_state->scaler_id;
4497                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4498                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4499                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4500                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4501
4502                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4503         }
4504 }
4505
4506 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4507 {
4508         struct drm_device *dev = crtc->base.dev;
4509         struct drm_i915_private *dev_priv = dev->dev_private;
4510         int pipe = crtc->pipe;
4511
4512         if (crtc->config->pch_pfit.enabled) {
4513                 /* Force use of hard-coded filter coefficients
4514                  * as some pre-programmed values are broken,
4515                  * e.g. x201.
4516                  */
4517                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4518                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4519                                                  PF_PIPE_SEL_IVB(pipe));
4520                 else
4521                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4522                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4523                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4524         }
4525 }
4526
4527 void hsw_enable_ips(struct intel_crtc *crtc)
4528 {
4529         struct drm_device *dev = crtc->base.dev;
4530         struct drm_i915_private *dev_priv = dev->dev_private;
4531
4532         if (!crtc->config->ips_enabled)
4533                 return;
4534
4535         /* We can only enable IPS after we enable a plane and wait for a vblank */
4536         intel_wait_for_vblank(dev, crtc->pipe);
4537
4538         assert_plane_enabled(dev_priv, crtc->plane);
4539         if (IS_BROADWELL(dev)) {
4540                 mutex_lock(&dev_priv->rps.hw_lock);
4541                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4542                 mutex_unlock(&dev_priv->rps.hw_lock);
4543                 /* Quoting Art Runyan: "its not safe to expect any particular
4544                  * value in IPS_CTL bit 31 after enabling IPS through the
4545                  * mailbox." Moreover, the mailbox may return a bogus state,
4546                  * so we need to just enable it and continue on.
4547                  */
4548         } else {
4549                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4550                 /* The bit only becomes 1 in the next vblank, so this wait here
4551                  * is essentially intel_wait_for_vblank. If we don't have this
4552                  * and don't wait for vblanks until the end of crtc_enable, then
4553                  * the HW state readout code will complain that the expected
4554                  * IPS_CTL value is not the one we read. */
4555                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4556                         DRM_ERROR("Timed out waiting for IPS enable\n");
4557         }
4558 }
4559
4560 void hsw_disable_ips(struct intel_crtc *crtc)
4561 {
4562         struct drm_device *dev = crtc->base.dev;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565         if (!crtc->config->ips_enabled)
4566                 return;
4567
4568         assert_plane_enabled(dev_priv, crtc->plane);
4569         if (IS_BROADWELL(dev)) {
4570                 mutex_lock(&dev_priv->rps.hw_lock);
4571                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4572                 mutex_unlock(&dev_priv->rps.hw_lock);
4573                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4574                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4575                         DRM_ERROR("Timed out waiting for IPS disable\n");
4576         } else {
4577                 I915_WRITE(IPS_CTL, 0);
4578                 POSTING_READ(IPS_CTL);
4579         }
4580
4581         /* We need to wait for a vblank before we can disable the plane. */
4582         intel_wait_for_vblank(dev, crtc->pipe);
4583 }
4584
4585 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4586 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4587 {
4588         struct drm_device *dev = crtc->dev;
4589         struct drm_i915_private *dev_priv = dev->dev_private;
4590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4591         enum pipe pipe = intel_crtc->pipe;
4592         int palreg = PALETTE(pipe);
4593         int i;
4594         bool reenable_ips = false;
4595
4596         /* The clocks have to be on to load the palette. */
4597         if (!crtc->state->active)
4598                 return;
4599
4600         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4601                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4602                         assert_dsi_pll_enabled(dev_priv);
4603                 else
4604                         assert_pll_enabled(dev_priv, pipe);
4605         }
4606
4607         /* use legacy palette for Ironlake */
4608         if (!HAS_GMCH_DISPLAY(dev))
4609                 palreg = LGC_PALETTE(pipe);
4610
4611         /* Workaround : Do not read or write the pipe palette/gamma data while
4612          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4613          */
4614         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4615             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4616              GAMMA_MODE_MODE_SPLIT)) {
4617                 hsw_disable_ips(intel_crtc);
4618                 reenable_ips = true;
4619         }
4620
4621         for (i = 0; i < 256; i++) {
4622                 I915_WRITE(palreg + 4 * i,
4623                            (intel_crtc->lut_r[i] << 16) |
4624                            (intel_crtc->lut_g[i] << 8) |
4625                            intel_crtc->lut_b[i]);
4626         }
4627
4628         if (reenable_ips)
4629                 hsw_enable_ips(intel_crtc);
4630 }
4631
4632 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4633 {
4634         if (intel_crtc->overlay) {
4635                 struct drm_device *dev = intel_crtc->base.dev;
4636                 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638                 mutex_lock(&dev->struct_mutex);
4639                 dev_priv->mm.interruptible = false;
4640                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4641                 dev_priv->mm.interruptible = true;
4642                 mutex_unlock(&dev->struct_mutex);
4643         }
4644
4645         /* Let userspace switch the overlay on again. In most cases userspace
4646          * has to recompute where to put it anyway.
4647          */
4648 }
4649
4650 /**
4651  * intel_post_enable_primary - Perform operations after enabling primary plane
4652  * @crtc: the CRTC whose primary plane was just enabled
4653  *
4654  * Performs potentially sleeping operations that must be done after the primary
4655  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4656  * called due to an explicit primary plane update, or due to an implicit
4657  * re-enable that is caused when a sprite plane is updated to no longer
4658  * completely hide the primary plane.
4659  */
4660 static void
4661 intel_post_enable_primary(struct drm_crtc *crtc)
4662 {
4663         struct drm_device *dev = crtc->dev;
4664         struct drm_i915_private *dev_priv = dev->dev_private;
4665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4666         int pipe = intel_crtc->pipe;
4667
4668         /*
4669          * BDW signals flip done immediately if the plane
4670          * is disabled, even if the plane enable is already
4671          * armed to occur at the next vblank :(
4672          */
4673         if (IS_BROADWELL(dev))
4674                 intel_wait_for_vblank(dev, pipe);
4675
4676         /*
4677          * FIXME IPS should be fine as long as one plane is
4678          * enabled, but in practice it seems to have problems
4679          * when going from primary only to sprite only and vice
4680          * versa.
4681          */
4682         hsw_enable_ips(intel_crtc);
4683
4684         /*
4685          * Gen2 reports pipe underruns whenever all planes are disabled.
4686          * So don't enable underrun reporting before at least some planes
4687          * are enabled.
4688          * FIXME: Need to fix the logic to work when we turn off all planes
4689          * but leave the pipe running.
4690          */
4691         if (IS_GEN2(dev))
4692                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4693
4694         /* Underruns don't raise interrupts, so check manually. */
4695         if (HAS_GMCH_DISPLAY(dev))
4696                 i9xx_check_fifo_underruns(dev_priv);
4697 }
4698
4699 /**
4700  * intel_pre_disable_primary - Perform operations before disabling primary plane
4701  * @crtc: the CRTC whose primary plane is to be disabled
4702  *
4703  * Performs potentially sleeping operations that must be done before the
4704  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4705  * be called due to an explicit primary plane update, or due to an implicit
4706  * disable that is caused when a sprite plane completely hides the primary
4707  * plane.
4708  */
4709 static void
4710 intel_pre_disable_primary(struct drm_crtc *crtc)
4711 {
4712         struct drm_device *dev = crtc->dev;
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715         int pipe = intel_crtc->pipe;
4716
4717         /*
4718          * Gen2 reports pipe underruns whenever all planes are disabled.
4719          * So diasble underrun reporting before all the planes get disabled.
4720          * FIXME: Need to fix the logic to work when we turn off all planes
4721          * but leave the pipe running.
4722          */
4723         if (IS_GEN2(dev))
4724                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4725
4726         /*
4727          * Vblank time updates from the shadow to live plane control register
4728          * are blocked if the memory self-refresh mode is active at that
4729          * moment. So to make sure the plane gets truly disabled, disable
4730          * first the self-refresh mode. The self-refresh enable bit in turn
4731          * will be checked/applied by the HW only at the next frame start
4732          * event which is after the vblank start event, so we need to have a
4733          * wait-for-vblank between disabling the plane and the pipe.
4734          */
4735         if (HAS_GMCH_DISPLAY(dev)) {
4736                 intel_set_memory_cxsr(dev_priv, false);
4737                 dev_priv->wm.vlv.cxsr = false;
4738                 intel_wait_for_vblank(dev, pipe);
4739         }
4740
4741         /*
4742          * FIXME IPS should be fine as long as one plane is
4743          * enabled, but in practice it seems to have problems
4744          * when going from primary only to sprite only and vice
4745          * versa.
4746          */
4747         hsw_disable_ips(intel_crtc);
4748 }
4749
4750 static void intel_post_plane_update(struct intel_crtc *crtc)
4751 {
4752         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         struct drm_plane *plane;
4756
4757         if (atomic->wait_vblank)
4758                 intel_wait_for_vblank(dev, crtc->pipe);
4759
4760         intel_frontbuffer_flip(dev, atomic->fb_bits);
4761
4762         if (atomic->disable_cxsr)
4763                 crtc->wm.cxsr_allowed = true;
4764
4765         if (crtc->atomic.update_wm_post)
4766                 intel_update_watermarks(&crtc->base);
4767
4768         if (atomic->update_fbc)
4769                 intel_fbc_update(dev_priv);
4770
4771         if (atomic->post_enable_primary)
4772                 intel_post_enable_primary(&crtc->base);
4773
4774         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4775                 intel_update_sprite_watermarks(plane, &crtc->base,
4776                                                0, 0, 0, false, false);
4777
4778         memset(atomic, 0, sizeof(*atomic));
4779 }
4780
4781 static void intel_pre_plane_update(struct intel_crtc *crtc)
4782 {
4783         struct drm_device *dev = crtc->base.dev;
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4786         struct drm_plane *p;
4787
4788         /* Track fb's for any planes being disabled */
4789         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4790                 struct intel_plane *plane = to_intel_plane(p);
4791
4792                 mutex_lock(&dev->struct_mutex);
4793                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4794                                   plane->frontbuffer_bit);
4795                 mutex_unlock(&dev->struct_mutex);
4796         }
4797
4798         if (atomic->wait_for_flips)
4799                 intel_crtc_wait_for_pending_flips(&crtc->base);
4800
4801         if (atomic->disable_fbc)
4802                 intel_fbc_disable_crtc(crtc);
4803
4804         if (crtc->atomic.disable_ips)
4805                 hsw_disable_ips(crtc);
4806
4807         if (atomic->pre_disable_primary)
4808                 intel_pre_disable_primary(&crtc->base);
4809
4810         if (atomic->disable_cxsr) {
4811                 crtc->wm.cxsr_allowed = false;
4812                 intel_set_memory_cxsr(dev_priv, false);
4813         }
4814 }
4815
4816 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4817 {
4818         struct drm_device *dev = crtc->dev;
4819         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820         struct drm_plane *p;
4821         int pipe = intel_crtc->pipe;
4822
4823         intel_crtc_dpms_overlay_disable(intel_crtc);
4824
4825         drm_for_each_plane_mask(p, dev, plane_mask)
4826                 to_intel_plane(p)->disable_plane(p, crtc);
4827
4828         /*
4829          * FIXME: Once we grow proper nuclear flip support out of this we need
4830          * to compute the mask of flip planes precisely. For the time being
4831          * consider this a flip to a NULL plane.
4832          */
4833         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4834 }
4835
4836 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4837 {
4838         struct drm_device *dev = crtc->dev;
4839         struct drm_i915_private *dev_priv = dev->dev_private;
4840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4841         struct intel_encoder *encoder;
4842         int pipe = intel_crtc->pipe;
4843
4844         if (WARN_ON(intel_crtc->active))
4845                 return;
4846
4847         if (intel_crtc->config->has_pch_encoder)
4848                 intel_prepare_shared_dpll(intel_crtc);
4849
4850         if (intel_crtc->config->has_dp_encoder)
4851                 intel_dp_set_m_n(intel_crtc, M1_N1);
4852
4853         intel_set_pipe_timings(intel_crtc);
4854
4855         if (intel_crtc->config->has_pch_encoder) {
4856                 intel_cpu_transcoder_set_m_n(intel_crtc,
4857                                      &intel_crtc->config->fdi_m_n, NULL);
4858         }
4859
4860         ironlake_set_pipeconf(crtc);
4861
4862         intel_crtc->active = true;
4863
4864         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4865         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4866
4867         for_each_encoder_on_crtc(dev, crtc, encoder)
4868                 if (encoder->pre_enable)
4869                         encoder->pre_enable(encoder);
4870
4871         if (intel_crtc->config->has_pch_encoder) {
4872                 /* Note: FDI PLL enabling _must_ be done before we enable the
4873                  * cpu pipes, hence this is separate from all the other fdi/pch
4874                  * enabling. */
4875                 ironlake_fdi_pll_enable(intel_crtc);
4876         } else {
4877                 assert_fdi_tx_disabled(dev_priv, pipe);
4878                 assert_fdi_rx_disabled(dev_priv, pipe);
4879         }
4880
4881         ironlake_pfit_enable(intel_crtc);
4882
4883         /*
4884          * On ILK+ LUT must be loaded before the pipe is running but with
4885          * clocks enabled
4886          */
4887         intel_crtc_load_lut(crtc);
4888
4889         intel_update_watermarks(crtc);
4890         intel_enable_pipe(intel_crtc);
4891
4892         if (intel_crtc->config->has_pch_encoder)
4893                 ironlake_pch_enable(crtc);
4894
4895         assert_vblank_disabled(crtc);
4896         drm_crtc_vblank_on(crtc);
4897
4898         for_each_encoder_on_crtc(dev, crtc, encoder)
4899                 encoder->enable(encoder);
4900
4901         if (HAS_PCH_CPT(dev))
4902                 cpt_verify_modeset(dev, intel_crtc->pipe);
4903 }
4904
4905 /* IPS only exists on ULT machines and is tied to pipe A. */
4906 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4907 {
4908         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4909 }
4910
4911 static void haswell_crtc_enable(struct drm_crtc *crtc)
4912 {
4913         struct drm_device *dev = crtc->dev;
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4916         struct intel_encoder *encoder;
4917         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4918         struct intel_crtc_state *pipe_config =
4919                 to_intel_crtc_state(crtc->state);
4920
4921         if (WARN_ON(intel_crtc->active))
4922                 return;
4923
4924         if (intel_crtc_to_shared_dpll(intel_crtc))
4925                 intel_enable_shared_dpll(intel_crtc);
4926
4927         if (intel_crtc->config->has_dp_encoder)
4928                 intel_dp_set_m_n(intel_crtc, M1_N1);
4929
4930         intel_set_pipe_timings(intel_crtc);
4931
4932         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4933                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4934                            intel_crtc->config->pixel_multiplier - 1);
4935         }
4936
4937         if (intel_crtc->config->has_pch_encoder) {
4938                 intel_cpu_transcoder_set_m_n(intel_crtc,
4939                                      &intel_crtc->config->fdi_m_n, NULL);
4940         }
4941
4942         haswell_set_pipeconf(crtc);
4943
4944         intel_set_pipe_csc(crtc);
4945
4946         intel_crtc->active = true;
4947
4948         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4949         for_each_encoder_on_crtc(dev, crtc, encoder)
4950                 if (encoder->pre_enable)
4951                         encoder->pre_enable(encoder);
4952
4953         if (intel_crtc->config->has_pch_encoder) {
4954                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4955                                                       true);
4956                 dev_priv->display.fdi_link_train(crtc);
4957         }
4958
4959         intel_ddi_enable_pipe_clock(intel_crtc);
4960
4961         if (INTEL_INFO(dev)->gen == 9)
4962                 skylake_pfit_enable(intel_crtc);
4963         else if (INTEL_INFO(dev)->gen < 9)
4964                 ironlake_pfit_enable(intel_crtc);
4965         else
4966                 MISSING_CASE(INTEL_INFO(dev)->gen);
4967
4968         /*
4969          * On ILK+ LUT must be loaded before the pipe is running but with
4970          * clocks enabled
4971          */
4972         intel_crtc_load_lut(crtc);
4973
4974         intel_ddi_set_pipe_settings(crtc);
4975         intel_ddi_enable_transcoder_func(crtc);
4976
4977         intel_update_watermarks(crtc);
4978         intel_enable_pipe(intel_crtc);
4979
4980         if (intel_crtc->config->has_pch_encoder)
4981                 lpt_pch_enable(crtc);
4982
4983         if (intel_crtc->config->dp_encoder_is_mst)
4984                 intel_ddi_set_vc_payload_alloc(crtc, true);
4985
4986         assert_vblank_disabled(crtc);
4987         drm_crtc_vblank_on(crtc);
4988
4989         for_each_encoder_on_crtc(dev, crtc, encoder) {
4990                 encoder->enable(encoder);
4991                 intel_opregion_notify_encoder(encoder, true);
4992         }
4993
4994         /* If we change the relative order between pipe/planes enabling, we need
4995          * to change the workaround. */
4996         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4997         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4998                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4999                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5000         }
5001 }
5002
5003 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5004 {
5005         struct drm_device *dev = crtc->base.dev;
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007         int pipe = crtc->pipe;
5008
5009         /* To avoid upsetting the power well on haswell only disable the pfit if
5010          * it's in use. The hw state code will make sure we get this right. */
5011         if (crtc->config->pch_pfit.enabled) {
5012                 I915_WRITE(PF_CTL(pipe), 0);
5013                 I915_WRITE(PF_WIN_POS(pipe), 0);
5014                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5015         }
5016 }
5017
5018 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5019 {
5020         struct drm_device *dev = crtc->dev;
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023         struct intel_encoder *encoder;
5024         int pipe = intel_crtc->pipe;
5025         u32 reg, temp;
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 encoder->disable(encoder);
5029
5030         drm_crtc_vblank_off(crtc);
5031         assert_vblank_disabled(crtc);
5032
5033         if (intel_crtc->config->has_pch_encoder)
5034                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5035
5036         intel_disable_pipe(intel_crtc);
5037
5038         ironlake_pfit_disable(intel_crtc);
5039
5040         if (intel_crtc->config->has_pch_encoder)
5041                 ironlake_fdi_disable(crtc);
5042
5043         for_each_encoder_on_crtc(dev, crtc, encoder)
5044                 if (encoder->post_disable)
5045                         encoder->post_disable(encoder);
5046
5047         if (intel_crtc->config->has_pch_encoder) {
5048                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5049
5050                 if (HAS_PCH_CPT(dev)) {
5051                         /* disable TRANS_DP_CTL */
5052                         reg = TRANS_DP_CTL(pipe);
5053                         temp = I915_READ(reg);
5054                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5055                                   TRANS_DP_PORT_SEL_MASK);
5056                         temp |= TRANS_DP_PORT_SEL_NONE;
5057                         I915_WRITE(reg, temp);
5058
5059                         /* disable DPLL_SEL */
5060                         temp = I915_READ(PCH_DPLL_SEL);
5061                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5062                         I915_WRITE(PCH_DPLL_SEL, temp);
5063                 }
5064
5065                 ironlake_fdi_pll_disable(intel_crtc);
5066         }
5067
5068         intel_crtc->active = false;
5069         intel_update_watermarks(crtc);
5070 }
5071
5072 static void haswell_crtc_disable(struct drm_crtc *crtc)
5073 {
5074         struct drm_device *dev = crtc->dev;
5075         struct drm_i915_private *dev_priv = dev->dev_private;
5076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5077         struct intel_encoder *encoder;
5078         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5079
5080         for_each_encoder_on_crtc(dev, crtc, encoder) {
5081                 intel_opregion_notify_encoder(encoder, false);
5082                 encoder->disable(encoder);
5083         }
5084
5085         drm_crtc_vblank_off(crtc);
5086         assert_vblank_disabled(crtc);
5087
5088         if (intel_crtc->config->has_pch_encoder)
5089                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5090                                                       false);
5091         intel_disable_pipe(intel_crtc);
5092
5093         if (intel_crtc->config->dp_encoder_is_mst)
5094                 intel_ddi_set_vc_payload_alloc(crtc, false);
5095
5096         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5097
5098         if (INTEL_INFO(dev)->gen == 9)
5099                 skylake_scaler_disable(intel_crtc);
5100         else if (INTEL_INFO(dev)->gen < 9)
5101                 ironlake_pfit_disable(intel_crtc);
5102         else
5103                 MISSING_CASE(INTEL_INFO(dev)->gen);
5104
5105         intel_ddi_disable_pipe_clock(intel_crtc);
5106
5107         if (intel_crtc->config->has_pch_encoder) {
5108                 lpt_disable_pch_transcoder(dev_priv);
5109                 intel_ddi_fdi_disable(crtc);
5110         }
5111
5112         for_each_encoder_on_crtc(dev, crtc, encoder)
5113                 if (encoder->post_disable)
5114                         encoder->post_disable(encoder);
5115
5116         intel_crtc->active = false;
5117         intel_update_watermarks(crtc);
5118 }
5119
5120 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5121 {
5122         struct drm_device *dev = crtc->base.dev;
5123         struct drm_i915_private *dev_priv = dev->dev_private;
5124         struct intel_crtc_state *pipe_config = crtc->config;
5125
5126         if (!pipe_config->gmch_pfit.control)
5127                 return;
5128
5129         /*
5130          * The panel fitter should only be adjusted whilst the pipe is disabled,
5131          * according to register description and PRM.
5132          */
5133         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5134         assert_pipe_disabled(dev_priv, crtc->pipe);
5135
5136         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5137         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5138
5139         /* Border color in case we don't scale up to the full screen. Black by
5140          * default, change to something else for debugging. */
5141         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5142 }
5143
5144 static enum intel_display_power_domain port_to_power_domain(enum port port)
5145 {
5146         switch (port) {
5147         case PORT_A:
5148         case PORT_E:
5149                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5150         case PORT_B:
5151                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5152         case PORT_C:
5153                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5154         case PORT_D:
5155                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5156         default:
5157                 WARN_ON_ONCE(1);
5158                 return POWER_DOMAIN_PORT_OTHER;
5159         }
5160 }
5161
5162 #define for_each_power_domain(domain, mask)                             \
5163         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5164                 if ((1 << (domain)) & (mask))
5165
5166 enum intel_display_power_domain
5167 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169         struct drm_device *dev = intel_encoder->base.dev;
5170         struct intel_digital_port *intel_dig_port;
5171
5172         switch (intel_encoder->type) {
5173         case INTEL_OUTPUT_UNKNOWN:
5174                 /* Only DDI platforms should ever use this output type */
5175                 WARN_ON_ONCE(!HAS_DDI(dev));
5176         case INTEL_OUTPUT_DISPLAYPORT:
5177         case INTEL_OUTPUT_HDMI:
5178         case INTEL_OUTPUT_EDP:
5179                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5180                 return port_to_power_domain(intel_dig_port->port);
5181         case INTEL_OUTPUT_DP_MST:
5182                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5183                 return port_to_power_domain(intel_dig_port->port);
5184         case INTEL_OUTPUT_ANALOG:
5185                 return POWER_DOMAIN_PORT_CRT;
5186         case INTEL_OUTPUT_DSI:
5187                 return POWER_DOMAIN_PORT_DSI;
5188         default:
5189                 return POWER_DOMAIN_PORT_OTHER;
5190         }
5191 }
5192
5193 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5194 {
5195         struct drm_device *dev = crtc->dev;
5196         struct intel_encoder *intel_encoder;
5197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198         enum pipe pipe = intel_crtc->pipe;
5199         unsigned long mask;
5200         enum transcoder transcoder;
5201
5202         if (!crtc->state->active)
5203                 return 0;
5204
5205         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5206
5207         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5208         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5209         if (intel_crtc->config->pch_pfit.enabled ||
5210             intel_crtc->config->pch_pfit.force_thru)
5211                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5212
5213         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5214                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5215
5216         return mask;
5217 }
5218
5219 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5220 {
5221         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223         enum intel_display_power_domain domain;
5224         unsigned long domains, new_domains, old_domains;
5225
5226         old_domains = intel_crtc->enabled_power_domains;
5227         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5228
5229         domains = new_domains & ~old_domains;
5230
5231         for_each_power_domain(domain, domains)
5232                 intel_display_power_get(dev_priv, domain);
5233
5234         return old_domains & ~new_domains;
5235 }
5236
5237 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5238                                       unsigned long domains)
5239 {
5240         enum intel_display_power_domain domain;
5241
5242         for_each_power_domain(domain, domains)
5243                 intel_display_power_put(dev_priv, domain);
5244 }
5245
5246 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5247 {
5248         struct drm_device *dev = state->dev;
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250         unsigned long put_domains[I915_MAX_PIPES] = {};
5251         struct drm_crtc_state *crtc_state;
5252         struct drm_crtc *crtc;
5253         int i;
5254
5255         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5256                 if (needs_modeset(crtc->state))
5257                         put_domains[to_intel_crtc(crtc)->pipe] =
5258                                 modeset_get_crtc_power_domains(crtc);
5259         }
5260
5261         if (dev_priv->display.modeset_commit_cdclk) {
5262                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5263
5264                 if (cdclk != dev_priv->cdclk_freq &&
5265                     !WARN_ON(!state->allow_modeset))
5266                         dev_priv->display.modeset_commit_cdclk(state);
5267         }
5268
5269         for (i = 0; i < I915_MAX_PIPES; i++)
5270                 if (put_domains[i])
5271                         modeset_put_power_domains(dev_priv, put_domains[i]);
5272 }
5273
5274 static void intel_update_max_cdclk(struct drm_device *dev)
5275 {
5276         struct drm_i915_private *dev_priv = dev->dev_private;
5277
5278         if (IS_SKYLAKE(dev)) {
5279                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5280
5281                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5282                         dev_priv->max_cdclk_freq = 675000;
5283                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5284                         dev_priv->max_cdclk_freq = 540000;
5285                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5286                         dev_priv->max_cdclk_freq = 450000;
5287                 else
5288                         dev_priv->max_cdclk_freq = 337500;
5289         } else if (IS_BROADWELL(dev))  {
5290                 /*
5291                  * FIXME with extra cooling we can allow
5292                  * 540 MHz for ULX and 675 Mhz for ULT.
5293                  * How can we know if extra cooling is
5294                  * available? PCI ID, VTB, something else?
5295                  */
5296                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5297                         dev_priv->max_cdclk_freq = 450000;
5298                 else if (IS_BDW_ULX(dev))
5299                         dev_priv->max_cdclk_freq = 450000;
5300                 else if (IS_BDW_ULT(dev))
5301                         dev_priv->max_cdclk_freq = 540000;
5302                 else
5303                         dev_priv->max_cdclk_freq = 675000;
5304         } else if (IS_CHERRYVIEW(dev)) {
5305                 dev_priv->max_cdclk_freq = 320000;
5306         } else if (IS_VALLEYVIEW(dev)) {
5307                 dev_priv->max_cdclk_freq = 400000;
5308         } else {
5309                 /* otherwise assume cdclk is fixed */
5310                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5311         }
5312
5313         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5314                          dev_priv->max_cdclk_freq);
5315 }
5316
5317 static void intel_update_cdclk(struct drm_device *dev)
5318 {
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320
5321         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5322         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5323                          dev_priv->cdclk_freq);
5324
5325         /*
5326          * Program the gmbus_freq based on the cdclk frequency.
5327          * BSpec erroneously claims we should aim for 4MHz, but
5328          * in fact 1MHz is the correct frequency.
5329          */
5330         if (IS_VALLEYVIEW(dev)) {
5331                 /*
5332                  * Program the gmbus_freq based on the cdclk frequency.
5333                  * BSpec erroneously claims we should aim for 4MHz, but
5334                  * in fact 1MHz is the correct frequency.
5335                  */
5336                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5337         }
5338
5339         if (dev_priv->max_cdclk_freq == 0)
5340                 intel_update_max_cdclk(dev);
5341 }
5342
5343 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5344 {
5345         struct drm_i915_private *dev_priv = dev->dev_private;
5346         uint32_t divider;
5347         uint32_t ratio;
5348         uint32_t current_freq;
5349         int ret;
5350
5351         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5352         switch (frequency) {
5353         case 144000:
5354                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5355                 ratio = BXT_DE_PLL_RATIO(60);
5356                 break;
5357         case 288000:
5358                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5359                 ratio = BXT_DE_PLL_RATIO(60);
5360                 break;
5361         case 384000:
5362                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5363                 ratio = BXT_DE_PLL_RATIO(60);
5364                 break;
5365         case 576000:
5366                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5367                 ratio = BXT_DE_PLL_RATIO(60);
5368                 break;
5369         case 624000:
5370                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371                 ratio = BXT_DE_PLL_RATIO(65);
5372                 break;
5373         case 19200:
5374                 /*
5375                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5376                  * to suppress GCC warning.
5377                  */
5378                 ratio = 0;
5379                 divider = 0;
5380                 break;
5381         default:
5382                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5383
5384                 return;
5385         }
5386
5387         mutex_lock(&dev_priv->rps.hw_lock);
5388         /* Inform power controller of upcoming frequency change */
5389         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5390                                       0x80000000);
5391         mutex_unlock(&dev_priv->rps.hw_lock);
5392
5393         if (ret) {
5394                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5395                           ret, frequency);
5396                 return;
5397         }
5398
5399         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5400         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5401         current_freq = current_freq * 500 + 1000;
5402
5403         /*
5404          * DE PLL has to be disabled when
5405          * - setting to 19.2MHz (bypass, PLL isn't used)
5406          * - before setting to 624MHz (PLL needs toggling)
5407          * - before setting to any frequency from 624MHz (PLL needs toggling)
5408          */
5409         if (frequency == 19200 || frequency == 624000 ||
5410             current_freq == 624000) {
5411                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5412                 /* Timeout 200us */
5413                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5414                              1))
5415                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5416         }
5417
5418         if (frequency != 19200) {
5419                 uint32_t val;
5420
5421                 val = I915_READ(BXT_DE_PLL_CTL);
5422                 val &= ~BXT_DE_PLL_RATIO_MASK;
5423                 val |= ratio;
5424                 I915_WRITE(BXT_DE_PLL_CTL, val);
5425
5426                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5427                 /* Timeout 200us */
5428                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5429                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5430
5431                 val = I915_READ(CDCLK_CTL);
5432                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5433                 val |= divider;
5434                 /*
5435                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5436                  * enable otherwise.
5437                  */
5438                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5439                 if (frequency >= 500000)
5440                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5441
5442                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5443                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5444                 val |= (frequency - 1000) / 500;
5445                 I915_WRITE(CDCLK_CTL, val);
5446         }
5447
5448         mutex_lock(&dev_priv->rps.hw_lock);
5449         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450                                       DIV_ROUND_UP(frequency, 25000));
5451         mutex_unlock(&dev_priv->rps.hw_lock);
5452
5453         if (ret) {
5454                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5455                           ret, frequency);
5456                 return;
5457         }
5458
5459         intel_update_cdclk(dev);
5460 }
5461
5462 void broxton_init_cdclk(struct drm_device *dev)
5463 {
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         uint32_t val;
5466
5467         /*
5468          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5469          * or else the reset will hang because there is no PCH to respond.
5470          * Move the handshake programming to initialization sequence.
5471          * Previously was left up to BIOS.
5472          */
5473         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5474         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5475         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5476
5477         /* Enable PG1 for cdclk */
5478         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5479
5480         /* check if cd clock is enabled */
5481         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5482                 DRM_DEBUG_KMS("Display already initialized\n");
5483                 return;
5484         }
5485
5486         /*
5487          * FIXME:
5488          * - The initial CDCLK needs to be read from VBT.
5489          *   Need to make this change after VBT has changes for BXT.
5490          * - check if setting the max (or any) cdclk freq is really necessary
5491          *   here, it belongs to modeset time
5492          */
5493         broxton_set_cdclk(dev, 624000);
5494
5495         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5496         POSTING_READ(DBUF_CTL);
5497
5498         udelay(10);
5499
5500         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5501                 DRM_ERROR("DBuf power enable timeout!\n");
5502 }
5503
5504 void broxton_uninit_cdclk(struct drm_device *dev)
5505 {
5506         struct drm_i915_private *dev_priv = dev->dev_private;
5507
5508         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5509         POSTING_READ(DBUF_CTL);
5510
5511         udelay(10);
5512
5513         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5514                 DRM_ERROR("DBuf power disable timeout!\n");
5515
5516         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5517         broxton_set_cdclk(dev, 19200);
5518
5519         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5520 }
5521
5522 static const struct skl_cdclk_entry {
5523         unsigned int freq;
5524         unsigned int vco;
5525 } skl_cdclk_frequencies[] = {
5526         { .freq = 308570, .vco = 8640 },
5527         { .freq = 337500, .vco = 8100 },
5528         { .freq = 432000, .vco = 8640 },
5529         { .freq = 450000, .vco = 8100 },
5530         { .freq = 540000, .vco = 8100 },
5531         { .freq = 617140, .vco = 8640 },
5532         { .freq = 675000, .vco = 8100 },
5533 };
5534
5535 static unsigned int skl_cdclk_decimal(unsigned int freq)
5536 {
5537         return (freq - 1000) / 500;
5538 }
5539
5540 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5541 {
5542         unsigned int i;
5543
5544         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5545                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5546
5547                 if (e->freq == freq)
5548                         return e->vco;
5549         }
5550
5551         return 8100;
5552 }
5553
5554 static void
5555 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5556 {
5557         unsigned int min_freq;
5558         u32 val;
5559
5560         /* select the minimum CDCLK before enabling DPLL 0 */
5561         val = I915_READ(CDCLK_CTL);
5562         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5563         val |= CDCLK_FREQ_337_308;
5564
5565         if (required_vco == 8640)
5566                 min_freq = 308570;
5567         else
5568                 min_freq = 337500;
5569
5570         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5571
5572         I915_WRITE(CDCLK_CTL, val);
5573         POSTING_READ(CDCLK_CTL);
5574
5575         /*
5576          * We always enable DPLL0 with the lowest link rate possible, but still
5577          * taking into account the VCO required to operate the eDP panel at the
5578          * desired frequency. The usual DP link rates operate with a VCO of
5579          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5580          * The modeset code is responsible for the selection of the exact link
5581          * rate later on, with the constraint of choosing a frequency that
5582          * works with required_vco.
5583          */
5584         val = I915_READ(DPLL_CTRL1);
5585
5586         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5587                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5588         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5589         if (required_vco == 8640)
5590                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5591                                             SKL_DPLL0);
5592         else
5593                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5594                                             SKL_DPLL0);
5595
5596         I915_WRITE(DPLL_CTRL1, val);
5597         POSTING_READ(DPLL_CTRL1);
5598
5599         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5600
5601         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5602                 DRM_ERROR("DPLL0 not locked\n");
5603 }
5604
5605 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5606 {
5607         int ret;
5608         u32 val;
5609
5610         /* inform PCU we want to change CDCLK */
5611         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5612         mutex_lock(&dev_priv->rps.hw_lock);
5613         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5614         mutex_unlock(&dev_priv->rps.hw_lock);
5615
5616         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5617 }
5618
5619 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5620 {
5621         unsigned int i;
5622
5623         for (i = 0; i < 15; i++) {
5624                 if (skl_cdclk_pcu_ready(dev_priv))
5625                         return true;
5626                 udelay(10);
5627         }
5628
5629         return false;
5630 }
5631
5632 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5633 {
5634         struct drm_device *dev = dev_priv->dev;
5635         u32 freq_select, pcu_ack;
5636
5637         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5638
5639         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5640                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5641                 return;
5642         }
5643
5644         /* set CDCLK_CTL */
5645         switch(freq) {
5646         case 450000:
5647         case 432000:
5648                 freq_select = CDCLK_FREQ_450_432;
5649                 pcu_ack = 1;
5650                 break;
5651         case 540000:
5652                 freq_select = CDCLK_FREQ_540;
5653                 pcu_ack = 2;
5654                 break;
5655         case 308570:
5656         case 337500:
5657         default:
5658                 freq_select = CDCLK_FREQ_337_308;
5659                 pcu_ack = 0;
5660                 break;
5661         case 617140:
5662         case 675000:
5663                 freq_select = CDCLK_FREQ_675_617;
5664                 pcu_ack = 3;
5665                 break;
5666         }
5667
5668         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5669         POSTING_READ(CDCLK_CTL);
5670
5671         /* inform PCU of the change */
5672         mutex_lock(&dev_priv->rps.hw_lock);
5673         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5674         mutex_unlock(&dev_priv->rps.hw_lock);
5675
5676         intel_update_cdclk(dev);
5677 }
5678
5679 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5680 {
5681         /* disable DBUF power */
5682         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5683         POSTING_READ(DBUF_CTL);
5684
5685         udelay(10);
5686
5687         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5688                 DRM_ERROR("DBuf power disable timeout\n");
5689
5690         /* disable DPLL0 */
5691         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5692         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5693                 DRM_ERROR("Couldn't disable DPLL0\n");
5694
5695         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5696 }
5697
5698 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5699 {
5700         u32 val;
5701         unsigned int required_vco;
5702
5703         /* enable PCH reset handshake */
5704         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5705         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5706
5707         /* enable PG1 and Misc I/O */
5708         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5709
5710         /* DPLL0 already enabed !? */
5711         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5712                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5713                 return;
5714         }
5715
5716         /* enable DPLL0 */
5717         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5718         skl_dpll0_enable(dev_priv, required_vco);
5719
5720         /* set CDCLK to the frequency the BIOS chose */
5721         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5722
5723         /* enable DBUF power */
5724         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5725         POSTING_READ(DBUF_CTL);
5726
5727         udelay(10);
5728
5729         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5730                 DRM_ERROR("DBuf power enable timeout\n");
5731 }
5732
5733 /* returns HPLL frequency in kHz */
5734 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5735 {
5736         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5737
5738         /* Obtain SKU information */
5739         mutex_lock(&dev_priv->sb_lock);
5740         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5741                 CCK_FUSE_HPLL_FREQ_MASK;
5742         mutex_unlock(&dev_priv->sb_lock);
5743
5744         return vco_freq[hpll_freq] * 1000;
5745 }
5746
5747 /* Adjust CDclk dividers to allow high res or save power if possible */
5748 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5749 {
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751         u32 val, cmd;
5752
5753         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754                                         != dev_priv->cdclk_freq);
5755
5756         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5757                 cmd = 2;
5758         else if (cdclk == 266667)
5759                 cmd = 1;
5760         else
5761                 cmd = 0;
5762
5763         mutex_lock(&dev_priv->rps.hw_lock);
5764         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5765         val &= ~DSPFREQGUAR_MASK;
5766         val |= (cmd << DSPFREQGUAR_SHIFT);
5767         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5768         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5769                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5770                      50)) {
5771                 DRM_ERROR("timed out waiting for CDclk change\n");
5772         }
5773         mutex_unlock(&dev_priv->rps.hw_lock);
5774
5775         mutex_lock(&dev_priv->sb_lock);
5776
5777         if (cdclk == 400000) {
5778                 u32 divider;
5779
5780                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5781
5782                 /* adjust cdclk divider */
5783                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5784                 val &= ~DISPLAY_FREQUENCY_VALUES;
5785                 val |= divider;
5786                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5787
5788                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5789                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5790                              50))
5791                         DRM_ERROR("timed out waiting for CDclk change\n");
5792         }
5793
5794         /* adjust self-refresh exit latency value */
5795         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5796         val &= ~0x7f;
5797
5798         /*
5799          * For high bandwidth configs, we set a higher latency in the bunit
5800          * so that the core display fetch happens in time to avoid underruns.
5801          */
5802         if (cdclk == 400000)
5803                 val |= 4500 / 250; /* 4.5 usec */
5804         else
5805                 val |= 3000 / 250; /* 3.0 usec */
5806         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5807
5808         mutex_unlock(&dev_priv->sb_lock);
5809
5810         intel_update_cdclk(dev);
5811 }
5812
5813 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5814 {
5815         struct drm_i915_private *dev_priv = dev->dev_private;
5816         u32 val, cmd;
5817
5818         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5819                                                 != dev_priv->cdclk_freq);
5820
5821         switch (cdclk) {
5822         case 333333:
5823         case 320000:
5824         case 266667:
5825         case 200000:
5826                 break;
5827         default:
5828                 MISSING_CASE(cdclk);
5829                 return;
5830         }
5831
5832         /*
5833          * Specs are full of misinformation, but testing on actual
5834          * hardware has shown that we just need to write the desired
5835          * CCK divider into the Punit register.
5836          */
5837         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5838
5839         mutex_lock(&dev_priv->rps.hw_lock);
5840         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5841         val &= ~DSPFREQGUAR_MASK_CHV;
5842         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5843         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5844         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5845                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5846                      50)) {
5847                 DRM_ERROR("timed out waiting for CDclk change\n");
5848         }
5849         mutex_unlock(&dev_priv->rps.hw_lock);
5850
5851         intel_update_cdclk(dev);
5852 }
5853
5854 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5855                                  int max_pixclk)
5856 {
5857         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5858         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5859
5860         /*
5861          * Really only a few cases to deal with, as only 4 CDclks are supported:
5862          *   200MHz
5863          *   267MHz
5864          *   320/333MHz (depends on HPLL freq)
5865          *   400MHz (VLV only)
5866          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5867          * of the lower bin and adjust if needed.
5868          *
5869          * We seem to get an unstable or solid color picture at 200MHz.
5870          * Not sure what's wrong. For now use 200MHz only when all pipes
5871          * are off.
5872          */
5873         if (!IS_CHERRYVIEW(dev_priv) &&
5874             max_pixclk > freq_320*limit/100)
5875                 return 400000;
5876         else if (max_pixclk > 266667*limit/100)
5877                 return freq_320;
5878         else if (max_pixclk > 0)
5879                 return 266667;
5880         else
5881                 return 200000;
5882 }
5883
5884 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5885                               int max_pixclk)
5886 {
5887         /*
5888          * FIXME:
5889          * - remove the guardband, it's not needed on BXT
5890          * - set 19.2MHz bypass frequency if there are no active pipes
5891          */
5892         if (max_pixclk > 576000*9/10)
5893                 return 624000;
5894         else if (max_pixclk > 384000*9/10)
5895                 return 576000;
5896         else if (max_pixclk > 288000*9/10)
5897                 return 384000;
5898         else if (max_pixclk > 144000*9/10)
5899                 return 288000;
5900         else
5901                 return 144000;
5902 }
5903
5904 /* Compute the max pixel clock for new configuration. Uses atomic state if
5905  * that's non-NULL, look at current state otherwise. */
5906 static int intel_mode_max_pixclk(struct drm_device *dev,
5907                                  struct drm_atomic_state *state)
5908 {
5909         struct intel_crtc *intel_crtc;
5910         struct intel_crtc_state *crtc_state;
5911         int max_pixclk = 0;
5912
5913         for_each_intel_crtc(dev, intel_crtc) {
5914                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5915                 if (IS_ERR(crtc_state))
5916                         return PTR_ERR(crtc_state);
5917
5918                 if (!crtc_state->base.enable)
5919                         continue;
5920
5921                 max_pixclk = max(max_pixclk,
5922                                  crtc_state->base.adjusted_mode.crtc_clock);
5923         }
5924
5925         return max_pixclk;
5926 }
5927
5928 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5929 {
5930         struct drm_device *dev = state->dev;
5931         struct drm_i915_private *dev_priv = dev->dev_private;
5932         int max_pixclk = intel_mode_max_pixclk(dev, state);
5933
5934         if (max_pixclk < 0)
5935                 return max_pixclk;
5936
5937         to_intel_atomic_state(state)->cdclk =
5938                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5939
5940         return 0;
5941 }
5942
5943 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5944 {
5945         struct drm_device *dev = state->dev;
5946         struct drm_i915_private *dev_priv = dev->dev_private;
5947         int max_pixclk = intel_mode_max_pixclk(dev, state);
5948
5949         if (max_pixclk < 0)
5950                 return max_pixclk;
5951
5952         to_intel_atomic_state(state)->cdclk =
5953                 broxton_calc_cdclk(dev_priv, max_pixclk);
5954
5955         return 0;
5956 }
5957
5958 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5959 {
5960         unsigned int credits, default_credits;
5961
5962         if (IS_CHERRYVIEW(dev_priv))
5963                 default_credits = PFI_CREDIT(12);
5964         else
5965                 default_credits = PFI_CREDIT(8);
5966
5967         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5968                 /* CHV suggested value is 31 or 63 */
5969                 if (IS_CHERRYVIEW(dev_priv))
5970                         credits = PFI_CREDIT_63;
5971                 else
5972                         credits = PFI_CREDIT(15);
5973         } else {
5974                 credits = default_credits;
5975         }
5976
5977         /*
5978          * WA - write default credits before re-programming
5979          * FIXME: should we also set the resend bit here?
5980          */
5981         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5982                    default_credits);
5983
5984         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985                    credits | PFI_CREDIT_RESEND);
5986
5987         /*
5988          * FIXME is this guaranteed to clear
5989          * immediately or should we poll for it?
5990          */
5991         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5992 }
5993
5994 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5995 {
5996         struct drm_device *dev = old_state->dev;
5997         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999
6000         /*
6001          * FIXME: We can end up here with all power domains off, yet
6002          * with a CDCLK frequency other than the minimum. To account
6003          * for this take the PIPE-A power domain, which covers the HW
6004          * blocks needed for the following programming. This can be
6005          * removed once it's guaranteed that we get here either with
6006          * the minimum CDCLK set, or the required power domains
6007          * enabled.
6008          */
6009         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6010
6011         if (IS_CHERRYVIEW(dev))
6012                 cherryview_set_cdclk(dev, req_cdclk);
6013         else
6014                 valleyview_set_cdclk(dev, req_cdclk);
6015
6016         vlv_program_pfi_credits(dev_priv);
6017
6018         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6019 }
6020
6021 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6022 {
6023         struct drm_device *dev = crtc->dev;
6024         struct drm_i915_private *dev_priv = to_i915(dev);
6025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6026         struct intel_encoder *encoder;
6027         int pipe = intel_crtc->pipe;
6028         bool is_dsi;
6029
6030         if (WARN_ON(intel_crtc->active))
6031                 return;
6032
6033         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6034
6035         if (!is_dsi) {
6036                 if (IS_CHERRYVIEW(dev))
6037                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6038                 else
6039                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6040         }
6041
6042         if (intel_crtc->config->has_dp_encoder)
6043                 intel_dp_set_m_n(intel_crtc, M1_N1);
6044
6045         intel_set_pipe_timings(intel_crtc);
6046
6047         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6048                 struct drm_i915_private *dev_priv = dev->dev_private;
6049
6050                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6051                 I915_WRITE(CHV_CANVAS(pipe), 0);
6052         }
6053
6054         i9xx_set_pipeconf(intel_crtc);
6055
6056         intel_crtc->active = true;
6057
6058         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6059
6060         for_each_encoder_on_crtc(dev, crtc, encoder)
6061                 if (encoder->pre_pll_enable)
6062                         encoder->pre_pll_enable(encoder);
6063
6064         if (!is_dsi) {
6065                 if (IS_CHERRYVIEW(dev))
6066                         chv_enable_pll(intel_crtc, intel_crtc->config);
6067                 else
6068                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6069         }
6070
6071         for_each_encoder_on_crtc(dev, crtc, encoder)
6072                 if (encoder->pre_enable)
6073                         encoder->pre_enable(encoder);
6074
6075         i9xx_pfit_enable(intel_crtc);
6076
6077         intel_crtc_load_lut(crtc);
6078
6079         intel_enable_pipe(intel_crtc);
6080
6081         assert_vblank_disabled(crtc);
6082         drm_crtc_vblank_on(crtc);
6083
6084         for_each_encoder_on_crtc(dev, crtc, encoder)
6085                 encoder->enable(encoder);
6086 }
6087
6088 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6089 {
6090         struct drm_device *dev = crtc->base.dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6094         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6095 }
6096
6097 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6098 {
6099         struct drm_device *dev = crtc->dev;
6100         struct drm_i915_private *dev_priv = to_i915(dev);
6101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102         struct intel_encoder *encoder;
6103         int pipe = intel_crtc->pipe;
6104
6105         if (WARN_ON(intel_crtc->active))
6106                 return;
6107
6108         i9xx_set_pll_dividers(intel_crtc);
6109
6110         if (intel_crtc->config->has_dp_encoder)
6111                 intel_dp_set_m_n(intel_crtc, M1_N1);
6112
6113         intel_set_pipe_timings(intel_crtc);
6114
6115         i9xx_set_pipeconf(intel_crtc);
6116
6117         intel_crtc->active = true;
6118
6119         if (!IS_GEN2(dev))
6120                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6121
6122         for_each_encoder_on_crtc(dev, crtc, encoder)
6123                 if (encoder->pre_enable)
6124                         encoder->pre_enable(encoder);
6125
6126         i9xx_enable_pll(intel_crtc);
6127
6128         i9xx_pfit_enable(intel_crtc);
6129
6130         intel_crtc_load_lut(crtc);
6131
6132         intel_update_watermarks(crtc);
6133         intel_enable_pipe(intel_crtc);
6134
6135         assert_vblank_disabled(crtc);
6136         drm_crtc_vblank_on(crtc);
6137
6138         for_each_encoder_on_crtc(dev, crtc, encoder)
6139                 encoder->enable(encoder);
6140 }
6141
6142 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6143 {
6144         struct drm_device *dev = crtc->base.dev;
6145         struct drm_i915_private *dev_priv = dev->dev_private;
6146
6147         if (!crtc->config->gmch_pfit.control)
6148                 return;
6149
6150         assert_pipe_disabled(dev_priv, crtc->pipe);
6151
6152         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6153                          I915_READ(PFIT_CONTROL));
6154         I915_WRITE(PFIT_CONTROL, 0);
6155 }
6156
6157 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6158 {
6159         struct drm_device *dev = crtc->dev;
6160         struct drm_i915_private *dev_priv = dev->dev_private;
6161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6162         struct intel_encoder *encoder;
6163         int pipe = intel_crtc->pipe;
6164
6165         /*
6166          * On gen2 planes are double buffered but the pipe isn't, so we must
6167          * wait for planes to fully turn off before disabling the pipe.
6168          * We also need to wait on all gmch platforms because of the
6169          * self-refresh mode constraint explained above.
6170          */
6171         intel_wait_for_vblank(dev, pipe);
6172
6173         for_each_encoder_on_crtc(dev, crtc, encoder)
6174                 encoder->disable(encoder);
6175
6176         drm_crtc_vblank_off(crtc);
6177         assert_vblank_disabled(crtc);
6178
6179         intel_disable_pipe(intel_crtc);
6180
6181         i9xx_pfit_disable(intel_crtc);
6182
6183         for_each_encoder_on_crtc(dev, crtc, encoder)
6184                 if (encoder->post_disable)
6185                         encoder->post_disable(encoder);
6186
6187         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6188                 if (IS_CHERRYVIEW(dev))
6189                         chv_disable_pll(dev_priv, pipe);
6190                 else if (IS_VALLEYVIEW(dev))
6191                         vlv_disable_pll(dev_priv, pipe);
6192                 else
6193                         i9xx_disable_pll(intel_crtc);
6194         }
6195
6196         if (!IS_GEN2(dev))
6197                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6198
6199         intel_crtc->active = false;
6200         intel_update_watermarks(crtc);
6201 }
6202
6203 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6204 {
6205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6206         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6207         enum intel_display_power_domain domain;
6208         unsigned long domains;
6209
6210         if (!intel_crtc->active)
6211                 return;
6212
6213         if (to_intel_plane_state(crtc->primary->state)->visible) {
6214                 intel_crtc_wait_for_pending_flips(crtc);
6215                 intel_pre_disable_primary(crtc);
6216         }
6217
6218         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6219         dev_priv->display.crtc_disable(crtc);
6220         intel_disable_shared_dpll(intel_crtc);
6221
6222         domains = intel_crtc->enabled_power_domains;
6223         for_each_power_domain(domain, domains)
6224                 intel_display_power_put(dev_priv, domain);
6225         intel_crtc->enabled_power_domains = 0;
6226 }
6227
6228 /*
6229  * turn all crtc's off, but do not adjust state
6230  * This has to be paired with a call to intel_modeset_setup_hw_state.
6231  */
6232 int intel_display_suspend(struct drm_device *dev)
6233 {
6234         struct drm_mode_config *config = &dev->mode_config;
6235         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6236         struct drm_atomic_state *state;
6237         struct drm_crtc *crtc;
6238         unsigned crtc_mask = 0;
6239         int ret = 0;
6240
6241         if (WARN_ON(!ctx))
6242                 return 0;
6243
6244         lockdep_assert_held(&ctx->ww_ctx);
6245         state = drm_atomic_state_alloc(dev);
6246         if (WARN_ON(!state))
6247                 return -ENOMEM;
6248
6249         state->acquire_ctx = ctx;
6250         state->allow_modeset = true;
6251
6252         for_each_crtc(dev, crtc) {
6253                 struct drm_crtc_state *crtc_state =
6254                         drm_atomic_get_crtc_state(state, crtc);
6255
6256                 ret = PTR_ERR_OR_ZERO(crtc_state);
6257                 if (ret)
6258                         goto free;
6259
6260                 if (!crtc_state->active)
6261                         continue;
6262
6263                 crtc_state->active = false;
6264                 crtc_mask |= 1 << drm_crtc_index(crtc);
6265         }
6266
6267         if (crtc_mask) {
6268                 ret = drm_atomic_commit(state);
6269
6270                 if (!ret) {
6271                         for_each_crtc(dev, crtc)
6272                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6273                                         crtc->state->active = true;
6274
6275                         return ret;
6276                 }
6277         }
6278
6279 free:
6280         if (ret)
6281                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6282         drm_atomic_state_free(state);
6283         return ret;
6284 }
6285
6286 void intel_encoder_destroy(struct drm_encoder *encoder)
6287 {
6288         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6289
6290         drm_encoder_cleanup(encoder);
6291         kfree(intel_encoder);
6292 }
6293
6294 /* Cross check the actual hw state with our own modeset state tracking (and it's
6295  * internal consistency). */
6296 static void intel_connector_check_state(struct intel_connector *connector)
6297 {
6298         struct drm_crtc *crtc = connector->base.state->crtc;
6299
6300         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6301                       connector->base.base.id,
6302                       connector->base.name);
6303
6304         if (connector->get_hw_state(connector)) {
6305                 struct drm_encoder *encoder = &connector->encoder->base;
6306                 struct drm_connector_state *conn_state = connector->base.state;
6307
6308                 I915_STATE_WARN(!crtc,
6309                          "connector enabled without attached crtc\n");
6310
6311                 if (!crtc)
6312                         return;
6313
6314                 I915_STATE_WARN(!crtc->state->active,
6315                       "connector is active, but attached crtc isn't\n");
6316
6317                 if (!encoder)
6318                         return;
6319
6320                 I915_STATE_WARN(conn_state->best_encoder != encoder,
6321                         "atomic encoder doesn't match attached encoder\n");
6322
6323                 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6324                         "attached encoder crtc differs from connector crtc\n");
6325         } else {
6326                 I915_STATE_WARN(crtc && crtc->state->active,
6327                         "attached crtc is active, but connector isn't\n");
6328                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6329                         "best encoder set without crtc!\n");
6330         }
6331 }
6332
6333 int intel_connector_init(struct intel_connector *connector)
6334 {
6335         struct drm_connector_state *connector_state;
6336
6337         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6338         if (!connector_state)
6339                 return -ENOMEM;
6340
6341         connector->base.state = connector_state;
6342         return 0;
6343 }
6344
6345 struct intel_connector *intel_connector_alloc(void)
6346 {
6347         struct intel_connector *connector;
6348
6349         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6350         if (!connector)
6351                 return NULL;
6352
6353         if (intel_connector_init(connector) < 0) {
6354                 kfree(connector);
6355                 return NULL;
6356         }
6357
6358         return connector;
6359 }
6360
6361 /* Simple connector->get_hw_state implementation for encoders that support only
6362  * one connector and no cloning and hence the encoder state determines the state
6363  * of the connector. */
6364 bool intel_connector_get_hw_state(struct intel_connector *connector)
6365 {
6366         enum pipe pipe = 0;
6367         struct intel_encoder *encoder = connector->encoder;
6368
6369         return encoder->get_hw_state(encoder, &pipe);
6370 }
6371
6372 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6373 {
6374         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6375                 return crtc_state->fdi_lanes;
6376
6377         return 0;
6378 }
6379
6380 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6381                                      struct intel_crtc_state *pipe_config)
6382 {
6383         struct drm_atomic_state *state = pipe_config->base.state;
6384         struct intel_crtc *other_crtc;
6385         struct intel_crtc_state *other_crtc_state;
6386
6387         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6388                       pipe_name(pipe), pipe_config->fdi_lanes);
6389         if (pipe_config->fdi_lanes > 4) {
6390                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6391                               pipe_name(pipe), pipe_config->fdi_lanes);
6392                 return -EINVAL;
6393         }
6394
6395         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6396                 if (pipe_config->fdi_lanes > 2) {
6397                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6398                                       pipe_config->fdi_lanes);
6399                         return -EINVAL;
6400                 } else {
6401                         return 0;
6402                 }
6403         }
6404
6405         if (INTEL_INFO(dev)->num_pipes == 2)
6406                 return 0;
6407
6408         /* Ivybridge 3 pipe is really complicated */
6409         switch (pipe) {
6410         case PIPE_A:
6411                 return 0;
6412         case PIPE_B:
6413                 if (pipe_config->fdi_lanes <= 2)
6414                         return 0;
6415
6416                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6417                 other_crtc_state =
6418                         intel_atomic_get_crtc_state(state, other_crtc);
6419                 if (IS_ERR(other_crtc_state))
6420                         return PTR_ERR(other_crtc_state);
6421
6422                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6423                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6424                                       pipe_name(pipe), pipe_config->fdi_lanes);
6425                         return -EINVAL;
6426                 }
6427                 return 0;
6428         case PIPE_C:
6429                 if (pipe_config->fdi_lanes > 2) {
6430                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6431                                       pipe_name(pipe), pipe_config->fdi_lanes);
6432                         return -EINVAL;
6433                 }
6434
6435                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6436                 other_crtc_state =
6437                         intel_atomic_get_crtc_state(state, other_crtc);
6438                 if (IS_ERR(other_crtc_state))
6439                         return PTR_ERR(other_crtc_state);
6440
6441                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6442                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6443                         return -EINVAL;
6444                 }
6445                 return 0;
6446         default:
6447                 BUG();
6448         }
6449 }
6450
6451 #define RETRY 1
6452 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6453                                        struct intel_crtc_state *pipe_config)
6454 {
6455         struct drm_device *dev = intel_crtc->base.dev;
6456         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6457         int lane, link_bw, fdi_dotclock, ret;
6458         bool needs_recompute = false;
6459
6460 retry:
6461         /* FDI is a binary signal running at ~2.7GHz, encoding
6462          * each output octet as 10 bits. The actual frequency
6463          * is stored as a divider into a 100MHz clock, and the
6464          * mode pixel clock is stored in units of 1KHz.
6465          * Hence the bw of each lane in terms of the mode signal
6466          * is:
6467          */
6468         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6469
6470         fdi_dotclock = adjusted_mode->crtc_clock;
6471
6472         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6473                                            pipe_config->pipe_bpp);
6474
6475         pipe_config->fdi_lanes = lane;
6476
6477         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6478                                link_bw, &pipe_config->fdi_m_n);
6479
6480         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6481                                        intel_crtc->pipe, pipe_config);
6482         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6483                 pipe_config->pipe_bpp -= 2*3;
6484                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6485                               pipe_config->pipe_bpp);
6486                 needs_recompute = true;
6487                 pipe_config->bw_constrained = true;
6488
6489                 goto retry;
6490         }
6491
6492         if (needs_recompute)
6493                 return RETRY;
6494
6495         return ret;
6496 }
6497
6498 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6499                                      struct intel_crtc_state *pipe_config)
6500 {
6501         if (pipe_config->pipe_bpp > 24)
6502                 return false;
6503
6504         /* HSW can handle pixel rate up to cdclk? */
6505         if (IS_HASWELL(dev_priv->dev))
6506                 return true;
6507
6508         /*
6509          * We compare against max which means we must take
6510          * the increased cdclk requirement into account when
6511          * calculating the new cdclk.
6512          *
6513          * Should measure whether using a lower cdclk w/o IPS
6514          */
6515         return ilk_pipe_pixel_rate(pipe_config) <=
6516                 dev_priv->max_cdclk_freq * 95 / 100;
6517 }
6518
6519 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6520                                    struct intel_crtc_state *pipe_config)
6521 {
6522         struct drm_device *dev = crtc->base.dev;
6523         struct drm_i915_private *dev_priv = dev->dev_private;
6524
6525         pipe_config->ips_enabled = i915.enable_ips &&
6526                 hsw_crtc_supports_ips(crtc) &&
6527                 pipe_config_supports_ips(dev_priv, pipe_config);
6528 }
6529
6530 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6531                                      struct intel_crtc_state *pipe_config)
6532 {
6533         struct drm_device *dev = crtc->base.dev;
6534         struct drm_i915_private *dev_priv = dev->dev_private;
6535         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6536
6537         /* FIXME should check pixel clock limits on all platforms */
6538         if (INTEL_INFO(dev)->gen < 4) {
6539                 int clock_limit = dev_priv->max_cdclk_freq;
6540
6541                 /*
6542                  * Enable pixel doubling when the dot clock
6543                  * is > 90% of the (display) core speed.
6544                  *
6545                  * GDG double wide on either pipe,
6546                  * otherwise pipe A only.
6547                  */
6548                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6549                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6550                         clock_limit *= 2;
6551                         pipe_config->double_wide = true;
6552                 }
6553
6554                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6555                         return -EINVAL;
6556         }
6557
6558         /*
6559          * Pipe horizontal size must be even in:
6560          * - DVO ganged mode
6561          * - LVDS dual channel mode
6562          * - Double wide pipe
6563          */
6564         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6565              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6566                 pipe_config->pipe_src_w &= ~1;
6567
6568         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6569          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6570          */
6571         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6572                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6573                 return -EINVAL;
6574
6575         if (HAS_IPS(dev))
6576                 hsw_compute_ips_config(crtc, pipe_config);
6577
6578         if (pipe_config->has_pch_encoder)
6579                 return ironlake_fdi_compute_config(crtc, pipe_config);
6580
6581         return 0;
6582 }
6583
6584 static int skylake_get_display_clock_speed(struct drm_device *dev)
6585 {
6586         struct drm_i915_private *dev_priv = to_i915(dev);
6587         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6588         uint32_t cdctl = I915_READ(CDCLK_CTL);
6589         uint32_t linkrate;
6590
6591         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6592                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6593
6594         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6595                 return 540000;
6596
6597         linkrate = (I915_READ(DPLL_CTRL1) &
6598                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6599
6600         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6601             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6602                 /* vco 8640 */
6603                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6604                 case CDCLK_FREQ_450_432:
6605                         return 432000;
6606                 case CDCLK_FREQ_337_308:
6607                         return 308570;
6608                 case CDCLK_FREQ_675_617:
6609                         return 617140;
6610                 default:
6611                         WARN(1, "Unknown cd freq selection\n");
6612                 }
6613         } else {
6614                 /* vco 8100 */
6615                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6616                 case CDCLK_FREQ_450_432:
6617                         return 450000;
6618                 case CDCLK_FREQ_337_308:
6619                         return 337500;
6620                 case CDCLK_FREQ_675_617:
6621                         return 675000;
6622                 default:
6623                         WARN(1, "Unknown cd freq selection\n");
6624                 }
6625         }
6626
6627         /* error case, do as if DPLL0 isn't enabled */
6628         return 24000;
6629 }
6630
6631 static int broxton_get_display_clock_speed(struct drm_device *dev)
6632 {
6633         struct drm_i915_private *dev_priv = to_i915(dev);
6634         uint32_t cdctl = I915_READ(CDCLK_CTL);
6635         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6636         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6637         int cdclk;
6638
6639         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6640                 return 19200;
6641
6642         cdclk = 19200 * pll_ratio / 2;
6643
6644         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6645         case BXT_CDCLK_CD2X_DIV_SEL_1:
6646                 return cdclk;  /* 576MHz or 624MHz */
6647         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6648                 return cdclk * 2 / 3; /* 384MHz */
6649         case BXT_CDCLK_CD2X_DIV_SEL_2:
6650                 return cdclk / 2; /* 288MHz */
6651         case BXT_CDCLK_CD2X_DIV_SEL_4:
6652                 return cdclk / 4; /* 144MHz */
6653         }
6654
6655         /* error case, do as if DE PLL isn't enabled */
6656         return 19200;
6657 }
6658
6659 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6660 {
6661         struct drm_i915_private *dev_priv = dev->dev_private;
6662         uint32_t lcpll = I915_READ(LCPLL_CTL);
6663         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6664
6665         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6666                 return 800000;
6667         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6668                 return 450000;
6669         else if (freq == LCPLL_CLK_FREQ_450)
6670                 return 450000;
6671         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6672                 return 540000;
6673         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6674                 return 337500;
6675         else
6676                 return 675000;
6677 }
6678
6679 static int haswell_get_display_clock_speed(struct drm_device *dev)
6680 {
6681         struct drm_i915_private *dev_priv = dev->dev_private;
6682         uint32_t lcpll = I915_READ(LCPLL_CTL);
6683         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6684
6685         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6686                 return 800000;
6687         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6688                 return 450000;
6689         else if (freq == LCPLL_CLK_FREQ_450)
6690                 return 450000;
6691         else if (IS_HSW_ULT(dev))
6692                 return 337500;
6693         else
6694                 return 540000;
6695 }
6696
6697 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6698 {
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         u32 val;
6701         int divider;
6702
6703         if (dev_priv->hpll_freq == 0)
6704                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6705
6706         mutex_lock(&dev_priv->sb_lock);
6707         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6708         mutex_unlock(&dev_priv->sb_lock);
6709
6710         divider = val & DISPLAY_FREQUENCY_VALUES;
6711
6712         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6713              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6714              "cdclk change in progress\n");
6715
6716         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6717 }
6718
6719 static int ilk_get_display_clock_speed(struct drm_device *dev)
6720 {
6721         return 450000;
6722 }
6723
6724 static int i945_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         return 400000;
6727 }
6728
6729 static int i915_get_display_clock_speed(struct drm_device *dev)
6730 {
6731         return 333333;
6732 }
6733
6734 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6735 {
6736         return 200000;
6737 }
6738
6739 static int pnv_get_display_clock_speed(struct drm_device *dev)
6740 {
6741         u16 gcfgc = 0;
6742
6743         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6744
6745         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6746         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6747                 return 266667;
6748         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6749                 return 333333;
6750         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6751                 return 444444;
6752         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6753                 return 200000;
6754         default:
6755                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6756         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6757                 return 133333;
6758         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6759                 return 166667;
6760         }
6761 }
6762
6763 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6764 {
6765         u16 gcfgc = 0;
6766
6767         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768
6769         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6770                 return 133333;
6771         else {
6772                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6773                 case GC_DISPLAY_CLOCK_333_MHZ:
6774                         return 333333;
6775                 default:
6776                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6777                         return 190000;
6778                 }
6779         }
6780 }
6781
6782 static int i865_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         return 266667;
6785 }
6786
6787 static int i85x_get_display_clock_speed(struct drm_device *dev)
6788 {
6789         u16 hpllcc = 0;
6790
6791         /*
6792          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6793          * encoding is different :(
6794          * FIXME is this the right way to detect 852GM/852GMV?
6795          */
6796         if (dev->pdev->revision == 0x1)
6797                 return 133333;
6798
6799         pci_bus_read_config_word(dev->pdev->bus,
6800                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6801
6802         /* Assume that the hardware is in the high speed state.  This
6803          * should be the default.
6804          */
6805         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6806         case GC_CLOCK_133_200:
6807         case GC_CLOCK_133_200_2:
6808         case GC_CLOCK_100_200:
6809                 return 200000;
6810         case GC_CLOCK_166_250:
6811                 return 250000;
6812         case GC_CLOCK_100_133:
6813                 return 133333;
6814         case GC_CLOCK_133_266:
6815         case GC_CLOCK_133_266_2:
6816         case GC_CLOCK_166_266:
6817                 return 266667;
6818         }
6819
6820         /* Shouldn't happen */
6821         return 0;
6822 }
6823
6824 static int i830_get_display_clock_speed(struct drm_device *dev)
6825 {
6826         return 133333;
6827 }
6828
6829 static unsigned int intel_hpll_vco(struct drm_device *dev)
6830 {
6831         struct drm_i915_private *dev_priv = dev->dev_private;
6832         static const unsigned int blb_vco[8] = {
6833                 [0] = 3200000,
6834                 [1] = 4000000,
6835                 [2] = 5333333,
6836                 [3] = 4800000,
6837                 [4] = 6400000,
6838         };
6839         static const unsigned int pnv_vco[8] = {
6840                 [0] = 3200000,
6841                 [1] = 4000000,
6842                 [2] = 5333333,
6843                 [3] = 4800000,
6844                 [4] = 2666667,
6845         };
6846         static const unsigned int cl_vco[8] = {
6847                 [0] = 3200000,
6848                 [1] = 4000000,
6849                 [2] = 5333333,
6850                 [3] = 6400000,
6851                 [4] = 3333333,
6852                 [5] = 3566667,
6853                 [6] = 4266667,
6854         };
6855         static const unsigned int elk_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860         };
6861         static const unsigned int ctg_vco[8] = {
6862                 [0] = 3200000,
6863                 [1] = 4000000,
6864                 [2] = 5333333,
6865                 [3] = 6400000,
6866                 [4] = 2666667,
6867                 [5] = 4266667,
6868         };
6869         const unsigned int *vco_table;
6870         unsigned int vco;
6871         uint8_t tmp = 0;
6872
6873         /* FIXME other chipsets? */
6874         if (IS_GM45(dev))
6875                 vco_table = ctg_vco;
6876         else if (IS_G4X(dev))
6877                 vco_table = elk_vco;
6878         else if (IS_CRESTLINE(dev))
6879                 vco_table = cl_vco;
6880         else if (IS_PINEVIEW(dev))
6881                 vco_table = pnv_vco;
6882         else if (IS_G33(dev))
6883                 vco_table = blb_vco;
6884         else
6885                 return 0;
6886
6887         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6888
6889         vco = vco_table[tmp & 0x7];
6890         if (vco == 0)
6891                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6892         else
6893                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6894
6895         return vco;
6896 }
6897
6898 static int gm45_get_display_clock_speed(struct drm_device *dev)
6899 {
6900         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6901         uint16_t tmp = 0;
6902
6903         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6904
6905         cdclk_sel = (tmp >> 12) & 0x1;
6906
6907         switch (vco) {
6908         case 2666667:
6909         case 4000000:
6910         case 5333333:
6911                 return cdclk_sel ? 333333 : 222222;
6912         case 3200000:
6913                 return cdclk_sel ? 320000 : 228571;
6914         default:
6915                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6916                 return 222222;
6917         }
6918 }
6919
6920 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6921 {
6922         static const uint8_t div_3200[] = { 16, 10,  8 };
6923         static const uint8_t div_4000[] = { 20, 12, 10 };
6924         static const uint8_t div_5333[] = { 24, 16, 14 };
6925         const uint8_t *div_table;
6926         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6927         uint16_t tmp = 0;
6928
6929         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6930
6931         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6932
6933         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6934                 goto fail;
6935
6936         switch (vco) {
6937         case 3200000:
6938                 div_table = div_3200;
6939                 break;
6940         case 4000000:
6941                 div_table = div_4000;
6942                 break;
6943         case 5333333:
6944                 div_table = div_5333;
6945                 break;
6946         default:
6947                 goto fail;
6948         }
6949
6950         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6951
6952 fail:
6953         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6954         return 200000;
6955 }
6956
6957 static int g33_get_display_clock_speed(struct drm_device *dev)
6958 {
6959         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6960         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6961         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6962         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6963         const uint8_t *div_table;
6964         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965         uint16_t tmp = 0;
6966
6967         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969         cdclk_sel = (tmp >> 4) & 0x7;
6970
6971         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6972                 goto fail;
6973
6974         switch (vco) {
6975         case 3200000:
6976                 div_table = div_3200;
6977                 break;
6978         case 4000000:
6979                 div_table = div_4000;
6980                 break;
6981         case 4800000:
6982                 div_table = div_4800;
6983                 break;
6984         case 5333333:
6985                 div_table = div_5333;
6986                 break;
6987         default:
6988                 goto fail;
6989         }
6990
6991         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6992
6993 fail:
6994         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6995         return 190476;
6996 }
6997
6998 static void
6999 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7000 {
7001         while (*num > DATA_LINK_M_N_MASK ||
7002                *den > DATA_LINK_M_N_MASK) {
7003                 *num >>= 1;
7004                 *den >>= 1;
7005         }
7006 }
7007
7008 static void compute_m_n(unsigned int m, unsigned int n,
7009                         uint32_t *ret_m, uint32_t *ret_n)
7010 {
7011         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7012         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7013         intel_reduce_m_n_ratio(ret_m, ret_n);
7014 }
7015
7016 void
7017 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7018                        int pixel_clock, int link_clock,
7019                        struct intel_link_m_n *m_n)
7020 {
7021         m_n->tu = 64;
7022
7023         compute_m_n(bits_per_pixel * pixel_clock,
7024                     link_clock * nlanes * 8,
7025                     &m_n->gmch_m, &m_n->gmch_n);
7026
7027         compute_m_n(pixel_clock, link_clock,
7028                     &m_n->link_m, &m_n->link_n);
7029 }
7030
7031 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7032 {
7033         if (i915.panel_use_ssc >= 0)
7034                 return i915.panel_use_ssc != 0;
7035         return dev_priv->vbt.lvds_use_ssc
7036                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7037 }
7038
7039 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7040                            int num_connectors)
7041 {
7042         struct drm_device *dev = crtc_state->base.crtc->dev;
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         int refclk;
7045
7046         WARN_ON(!crtc_state->base.state);
7047
7048         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7049                 refclk = 100000;
7050         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7051             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7052                 refclk = dev_priv->vbt.lvds_ssc_freq;
7053                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7054         } else if (!IS_GEN2(dev)) {
7055                 refclk = 96000;
7056         } else {
7057                 refclk = 48000;
7058         }
7059
7060         return refclk;
7061 }
7062
7063 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7064 {
7065         return (1 << dpll->n) << 16 | dpll->m2;
7066 }
7067
7068 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7069 {
7070         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7071 }
7072
7073 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7074                                      struct intel_crtc_state *crtc_state,
7075                                      intel_clock_t *reduced_clock)
7076 {
7077         struct drm_device *dev = crtc->base.dev;
7078         u32 fp, fp2 = 0;
7079
7080         if (IS_PINEVIEW(dev)) {
7081                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7082                 if (reduced_clock)
7083                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7084         } else {
7085                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7086                 if (reduced_clock)
7087                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7088         }
7089
7090         crtc_state->dpll_hw_state.fp0 = fp;
7091
7092         crtc->lowfreq_avail = false;
7093         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7094             reduced_clock) {
7095                 crtc_state->dpll_hw_state.fp1 = fp2;
7096                 crtc->lowfreq_avail = true;
7097         } else {
7098                 crtc_state->dpll_hw_state.fp1 = fp;
7099         }
7100 }
7101
7102 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7103                 pipe)
7104 {
7105         u32 reg_val;
7106
7107         /*
7108          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7109          * and set it to a reasonable value instead.
7110          */
7111         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7112         reg_val &= 0xffffff00;
7113         reg_val |= 0x00000030;
7114         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7115
7116         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7117         reg_val &= 0x8cffffff;
7118         reg_val = 0x8c000000;
7119         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7120
7121         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7122         reg_val &= 0xffffff00;
7123         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7124
7125         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7126         reg_val &= 0x00ffffff;
7127         reg_val |= 0xb0000000;
7128         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7129 }
7130
7131 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7132                                          struct intel_link_m_n *m_n)
7133 {
7134         struct drm_device *dev = crtc->base.dev;
7135         struct drm_i915_private *dev_priv = dev->dev_private;
7136         int pipe = crtc->pipe;
7137
7138         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7139         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7140         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7141         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7142 }
7143
7144 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7145                                          struct intel_link_m_n *m_n,
7146                                          struct intel_link_m_n *m2_n2)
7147 {
7148         struct drm_device *dev = crtc->base.dev;
7149         struct drm_i915_private *dev_priv = dev->dev_private;
7150         int pipe = crtc->pipe;
7151         enum transcoder transcoder = crtc->config->cpu_transcoder;
7152
7153         if (INTEL_INFO(dev)->gen >= 5) {
7154                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7155                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7156                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7157                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7158                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7159                  * for gen < 8) and if DRRS is supported (to make sure the
7160                  * registers are not unnecessarily accessed).
7161                  */
7162                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7163                         crtc->config->has_drrs) {
7164                         I915_WRITE(PIPE_DATA_M2(transcoder),
7165                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7166                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7167                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7168                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7169                 }
7170         } else {
7171                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7173                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7174                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7175         }
7176 }
7177
7178 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7179 {
7180         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7181
7182         if (m_n == M1_N1) {
7183                 dp_m_n = &crtc->config->dp_m_n;
7184                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7185         } else if (m_n == M2_N2) {
7186
7187                 /*
7188                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7189                  * needs to be programmed into M1_N1.
7190                  */
7191                 dp_m_n = &crtc->config->dp_m2_n2;
7192         } else {
7193                 DRM_ERROR("Unsupported divider value\n");
7194                 return;
7195         }
7196
7197         if (crtc->config->has_pch_encoder)
7198                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7199         else
7200                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7201 }
7202
7203 static void vlv_compute_dpll(struct intel_crtc *crtc,
7204                              struct intel_crtc_state *pipe_config)
7205 {
7206         u32 dpll, dpll_md;
7207
7208         /*
7209          * Enable DPIO clock input. We should never disable the reference
7210          * clock for pipe B, since VGA hotplug / manual detection depends
7211          * on it.
7212          */
7213         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7214                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7215         /* We should never disable this, set it here for state tracking */
7216         if (crtc->pipe == PIPE_B)
7217                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7218         dpll |= DPLL_VCO_ENABLE;
7219         pipe_config->dpll_hw_state.dpll = dpll;
7220
7221         dpll_md = (pipe_config->pixel_multiplier - 1)
7222                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7223         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7224 }
7225
7226 static void vlv_prepare_pll(struct intel_crtc *crtc,
7227                             const struct intel_crtc_state *pipe_config)
7228 {
7229         struct drm_device *dev = crtc->base.dev;
7230         struct drm_i915_private *dev_priv = dev->dev_private;
7231         int pipe = crtc->pipe;
7232         u32 mdiv;
7233         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7234         u32 coreclk, reg_val;
7235
7236         mutex_lock(&dev_priv->sb_lock);
7237
7238         bestn = pipe_config->dpll.n;
7239         bestm1 = pipe_config->dpll.m1;
7240         bestm2 = pipe_config->dpll.m2;
7241         bestp1 = pipe_config->dpll.p1;
7242         bestp2 = pipe_config->dpll.p2;
7243
7244         /* See eDP HDMI DPIO driver vbios notes doc */
7245
7246         /* PLL B needs special handling */
7247         if (pipe == PIPE_B)
7248                 vlv_pllb_recal_opamp(dev_priv, pipe);
7249
7250         /* Set up Tx target for periodic Rcomp update */
7251         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7252
7253         /* Disable target IRef on PLL */
7254         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7255         reg_val &= 0x00ffffff;
7256         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7257
7258         /* Disable fast lock */
7259         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7260
7261         /* Set idtafcrecal before PLL is enabled */
7262         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7263         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7264         mdiv |= ((bestn << DPIO_N_SHIFT));
7265         mdiv |= (1 << DPIO_K_SHIFT);
7266
7267         /*
7268          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7269          * but we don't support that).
7270          * Note: don't use the DAC post divider as it seems unstable.
7271          */
7272         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7273         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7274
7275         mdiv |= DPIO_ENABLE_CALIBRATION;
7276         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277
7278         /* Set HBR and RBR LPF coefficients */
7279         if (pipe_config->port_clock == 162000 ||
7280             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7281             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7282                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7283                                  0x009f0003);
7284         else
7285                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7286                                  0x00d0000f);
7287
7288         if (pipe_config->has_dp_encoder) {
7289                 /* Use SSC source */
7290                 if (pipe == PIPE_A)
7291                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7292                                          0x0df40000);
7293                 else
7294                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295                                          0x0df70000);
7296         } else { /* HDMI or VGA */
7297                 /* Use bend source */
7298                 if (pipe == PIPE_A)
7299                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7300                                          0x0df70000);
7301                 else
7302                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7303                                          0x0df40000);
7304         }
7305
7306         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7307         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7308         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7309             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7310                 coreclk |= 0x01000000;
7311         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7312
7313         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7314         mutex_unlock(&dev_priv->sb_lock);
7315 }
7316
7317 static void chv_compute_dpll(struct intel_crtc *crtc,
7318                              struct intel_crtc_state *pipe_config)
7319 {
7320         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7321                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7322                 DPLL_VCO_ENABLE;
7323         if (crtc->pipe != PIPE_A)
7324                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7325
7326         pipe_config->dpll_hw_state.dpll_md =
7327                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7328 }
7329
7330 static void chv_prepare_pll(struct intel_crtc *crtc,
7331                             const struct intel_crtc_state *pipe_config)
7332 {
7333         struct drm_device *dev = crtc->base.dev;
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335         int pipe = crtc->pipe;
7336         int dpll_reg = DPLL(crtc->pipe);
7337         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7338         u32 loopfilter, tribuf_calcntr;
7339         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7340         u32 dpio_val;
7341         int vco;
7342
7343         bestn = pipe_config->dpll.n;
7344         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7345         bestm1 = pipe_config->dpll.m1;
7346         bestm2 = pipe_config->dpll.m2 >> 22;
7347         bestp1 = pipe_config->dpll.p1;
7348         bestp2 = pipe_config->dpll.p2;
7349         vco = pipe_config->dpll.vco;
7350         dpio_val = 0;
7351         loopfilter = 0;
7352
7353         /*
7354          * Enable Refclk and SSC
7355          */
7356         I915_WRITE(dpll_reg,
7357                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7358
7359         mutex_lock(&dev_priv->sb_lock);
7360
7361         /* p1 and p2 divider */
7362         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7363                         5 << DPIO_CHV_S1_DIV_SHIFT |
7364                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7365                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7366                         1 << DPIO_CHV_K_DIV_SHIFT);
7367
7368         /* Feedback post-divider - m2 */
7369         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7370
7371         /* Feedback refclk divider - n and m1 */
7372         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7373                         DPIO_CHV_M1_DIV_BY_2 |
7374                         1 << DPIO_CHV_N_DIV_SHIFT);
7375
7376         /* M2 fraction division */
7377         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7378
7379         /* M2 fraction division enable */
7380         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7381         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7382         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7383         if (bestm2_frac)
7384                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7385         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7386
7387         /* Program digital lock detect threshold */
7388         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7389         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7390                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7391         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7392         if (!bestm2_frac)
7393                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7394         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7395
7396         /* Loop filter */
7397         if (vco == 5400000) {
7398                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7399                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7400                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7401                 tribuf_calcntr = 0x9;
7402         } else if (vco <= 6200000) {
7403                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7404                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7405                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7406                 tribuf_calcntr = 0x9;
7407         } else if (vco <= 6480000) {
7408                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7409                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7410                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7411                 tribuf_calcntr = 0x8;
7412         } else {
7413                 /* Not supported. Apply the same limits as in the max case */
7414                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7415                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7416                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7417                 tribuf_calcntr = 0;
7418         }
7419         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7420
7421         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7422         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7423         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7424         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7425
7426         /* AFC Recal */
7427         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7428                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7429                         DPIO_AFC_RECAL);
7430
7431         mutex_unlock(&dev_priv->sb_lock);
7432 }
7433
7434 /**
7435  * vlv_force_pll_on - forcibly enable just the PLL
7436  * @dev_priv: i915 private structure
7437  * @pipe: pipe PLL to enable
7438  * @dpll: PLL configuration
7439  *
7440  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7441  * in cases where we need the PLL enabled even when @pipe is not going to
7442  * be enabled.
7443  */
7444 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7445                       const struct dpll *dpll)
7446 {
7447         struct intel_crtc *crtc =
7448                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7449         struct intel_crtc_state pipe_config = {
7450                 .base.crtc = &crtc->base,
7451                 .pixel_multiplier = 1,
7452                 .dpll = *dpll,
7453         };
7454
7455         if (IS_CHERRYVIEW(dev)) {
7456                 chv_compute_dpll(crtc, &pipe_config);
7457                 chv_prepare_pll(crtc, &pipe_config);
7458                 chv_enable_pll(crtc, &pipe_config);
7459         } else {
7460                 vlv_compute_dpll(crtc, &pipe_config);
7461                 vlv_prepare_pll(crtc, &pipe_config);
7462                 vlv_enable_pll(crtc, &pipe_config);
7463         }
7464 }
7465
7466 /**
7467  * vlv_force_pll_off - forcibly disable just the PLL
7468  * @dev_priv: i915 private structure
7469  * @pipe: pipe PLL to disable
7470  *
7471  * Disable the PLL for @pipe. To be used in cases where we need
7472  * the PLL enabled even when @pipe is not going to be enabled.
7473  */
7474 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7475 {
7476         if (IS_CHERRYVIEW(dev))
7477                 chv_disable_pll(to_i915(dev), pipe);
7478         else
7479                 vlv_disable_pll(to_i915(dev), pipe);
7480 }
7481
7482 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7483                               struct intel_crtc_state *crtc_state,
7484                               intel_clock_t *reduced_clock,
7485                               int num_connectors)
7486 {
7487         struct drm_device *dev = crtc->base.dev;
7488         struct drm_i915_private *dev_priv = dev->dev_private;
7489         u32 dpll;
7490         bool is_sdvo;
7491         struct dpll *clock = &crtc_state->dpll;
7492
7493         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7494
7495         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7496                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7497
7498         dpll = DPLL_VGA_MODE_DIS;
7499
7500         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7501                 dpll |= DPLLB_MODE_LVDS;
7502         else
7503                 dpll |= DPLLB_MODE_DAC_SERIAL;
7504
7505         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7506                 dpll |= (crtc_state->pixel_multiplier - 1)
7507                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7508         }
7509
7510         if (is_sdvo)
7511                 dpll |= DPLL_SDVO_HIGH_SPEED;
7512
7513         if (crtc_state->has_dp_encoder)
7514                 dpll |= DPLL_SDVO_HIGH_SPEED;
7515
7516         /* compute bitmask from p1 value */
7517         if (IS_PINEVIEW(dev))
7518                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7519         else {
7520                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7521                 if (IS_G4X(dev) && reduced_clock)
7522                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7523         }
7524         switch (clock->p2) {
7525         case 5:
7526                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7527                 break;
7528         case 7:
7529                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7530                 break;
7531         case 10:
7532                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7533                 break;
7534         case 14:
7535                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7536                 break;
7537         }
7538         if (INTEL_INFO(dev)->gen >= 4)
7539                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7540
7541         if (crtc_state->sdvo_tv_clock)
7542                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7543         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7544                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7545                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7546         else
7547                 dpll |= PLL_REF_INPUT_DREFCLK;
7548
7549         dpll |= DPLL_VCO_ENABLE;
7550         crtc_state->dpll_hw_state.dpll = dpll;
7551
7552         if (INTEL_INFO(dev)->gen >= 4) {
7553                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7554                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7555                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7556         }
7557 }
7558
7559 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7560                               struct intel_crtc_state *crtc_state,
7561                               intel_clock_t *reduced_clock,
7562                               int num_connectors)
7563 {
7564         struct drm_device *dev = crtc->base.dev;
7565         struct drm_i915_private *dev_priv = dev->dev_private;
7566         u32 dpll;
7567         struct dpll *clock = &crtc_state->dpll;
7568
7569         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7570
7571         dpll = DPLL_VGA_MODE_DIS;
7572
7573         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7574                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7575         } else {
7576                 if (clock->p1 == 2)
7577                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7578                 else
7579                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7580                 if (clock->p2 == 4)
7581                         dpll |= PLL_P2_DIVIDE_BY_4;
7582         }
7583
7584         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7585                 dpll |= DPLL_DVO_2X_MODE;
7586
7587         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7588                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7589                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7590         else
7591                 dpll |= PLL_REF_INPUT_DREFCLK;
7592
7593         dpll |= DPLL_VCO_ENABLE;
7594         crtc_state->dpll_hw_state.dpll = dpll;
7595 }
7596
7597 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7598 {
7599         struct drm_device *dev = intel_crtc->base.dev;
7600         struct drm_i915_private *dev_priv = dev->dev_private;
7601         enum pipe pipe = intel_crtc->pipe;
7602         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7603         struct drm_display_mode *adjusted_mode =
7604                 &intel_crtc->config->base.adjusted_mode;
7605         uint32_t crtc_vtotal, crtc_vblank_end;
7606         int vsyncshift = 0;
7607
7608         /* We need to be careful not to changed the adjusted mode, for otherwise
7609          * the hw state checker will get angry at the mismatch. */
7610         crtc_vtotal = adjusted_mode->crtc_vtotal;
7611         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7612
7613         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7614                 /* the chip adds 2 halflines automatically */
7615                 crtc_vtotal -= 1;
7616                 crtc_vblank_end -= 1;
7617
7618                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7619                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7620                 else
7621                         vsyncshift = adjusted_mode->crtc_hsync_start -
7622                                 adjusted_mode->crtc_htotal / 2;
7623                 if (vsyncshift < 0)
7624                         vsyncshift += adjusted_mode->crtc_htotal;
7625         }
7626
7627         if (INTEL_INFO(dev)->gen > 3)
7628                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7629
7630         I915_WRITE(HTOTAL(cpu_transcoder),
7631                    (adjusted_mode->crtc_hdisplay - 1) |
7632                    ((adjusted_mode->crtc_htotal - 1) << 16));
7633         I915_WRITE(HBLANK(cpu_transcoder),
7634                    (adjusted_mode->crtc_hblank_start - 1) |
7635                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7636         I915_WRITE(HSYNC(cpu_transcoder),
7637                    (adjusted_mode->crtc_hsync_start - 1) |
7638                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7639
7640         I915_WRITE(VTOTAL(cpu_transcoder),
7641                    (adjusted_mode->crtc_vdisplay - 1) |
7642                    ((crtc_vtotal - 1) << 16));
7643         I915_WRITE(VBLANK(cpu_transcoder),
7644                    (adjusted_mode->crtc_vblank_start - 1) |
7645                    ((crtc_vblank_end - 1) << 16));
7646         I915_WRITE(VSYNC(cpu_transcoder),
7647                    (adjusted_mode->crtc_vsync_start - 1) |
7648                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7649
7650         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7651          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7652          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7653          * bits. */
7654         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7655             (pipe == PIPE_B || pipe == PIPE_C))
7656                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7657
7658         /* pipesrc controls the size that is scaled from, which should
7659          * always be the user's requested size.
7660          */
7661         I915_WRITE(PIPESRC(pipe),
7662                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7663                    (intel_crtc->config->pipe_src_h - 1));
7664 }
7665
7666 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7667                                    struct intel_crtc_state *pipe_config)
7668 {
7669         struct drm_device *dev = crtc->base.dev;
7670         struct drm_i915_private *dev_priv = dev->dev_private;
7671         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7672         uint32_t tmp;
7673
7674         tmp = I915_READ(HTOTAL(cpu_transcoder));
7675         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7676         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7677         tmp = I915_READ(HBLANK(cpu_transcoder));
7678         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7679         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7680         tmp = I915_READ(HSYNC(cpu_transcoder));
7681         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7682         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7683
7684         tmp = I915_READ(VTOTAL(cpu_transcoder));
7685         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7686         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7687         tmp = I915_READ(VBLANK(cpu_transcoder));
7688         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7689         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7690         tmp = I915_READ(VSYNC(cpu_transcoder));
7691         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7692         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7693
7694         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7695                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7696                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7697                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7698         }
7699
7700         tmp = I915_READ(PIPESRC(crtc->pipe));
7701         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7702         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7703
7704         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7705         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7706 }
7707
7708 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7709                                  struct intel_crtc_state *pipe_config)
7710 {
7711         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7712         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7713         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7714         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7715
7716         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7717         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7718         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7719         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7720
7721         mode->flags = pipe_config->base.adjusted_mode.flags;
7722         mode->type = DRM_MODE_TYPE_DRIVER;
7723
7724         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7725         mode->flags |= pipe_config->base.adjusted_mode.flags;
7726
7727         mode->hsync = drm_mode_hsync(mode);
7728         mode->vrefresh = drm_mode_vrefresh(mode);
7729         drm_mode_set_name(mode);
7730 }
7731
7732 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7733 {
7734         struct drm_device *dev = intel_crtc->base.dev;
7735         struct drm_i915_private *dev_priv = dev->dev_private;
7736         uint32_t pipeconf;
7737
7738         pipeconf = 0;
7739
7740         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7741             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7742                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7743
7744         if (intel_crtc->config->double_wide)
7745                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7746
7747         /* only g4x and later have fancy bpc/dither controls */
7748         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7749                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7750                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7751                         pipeconf |= PIPECONF_DITHER_EN |
7752                                     PIPECONF_DITHER_TYPE_SP;
7753
7754                 switch (intel_crtc->config->pipe_bpp) {
7755                 case 18:
7756                         pipeconf |= PIPECONF_6BPC;
7757                         break;
7758                 case 24:
7759                         pipeconf |= PIPECONF_8BPC;
7760                         break;
7761                 case 30:
7762                         pipeconf |= PIPECONF_10BPC;
7763                         break;
7764                 default:
7765                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7766                         BUG();
7767                 }
7768         }
7769
7770         if (HAS_PIPE_CXSR(dev)) {
7771                 if (intel_crtc->lowfreq_avail) {
7772                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7773                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7774                 } else {
7775                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7776                 }
7777         }
7778
7779         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7780                 if (INTEL_INFO(dev)->gen < 4 ||
7781                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7782                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7783                 else
7784                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7785         } else
7786                 pipeconf |= PIPECONF_PROGRESSIVE;
7787
7788         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7789                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7790
7791         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7792         POSTING_READ(PIPECONF(intel_crtc->pipe));
7793 }
7794
7795 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7796                                    struct intel_crtc_state *crtc_state)
7797 {
7798         struct drm_device *dev = crtc->base.dev;
7799         struct drm_i915_private *dev_priv = dev->dev_private;
7800         int refclk, num_connectors = 0;
7801         intel_clock_t clock;
7802         bool ok;
7803         bool is_dsi = false;
7804         struct intel_encoder *encoder;
7805         const intel_limit_t *limit;
7806         struct drm_atomic_state *state = crtc_state->base.state;
7807         struct drm_connector *connector;
7808         struct drm_connector_state *connector_state;
7809         int i;
7810
7811         memset(&crtc_state->dpll_hw_state, 0,
7812                sizeof(crtc_state->dpll_hw_state));
7813
7814         for_each_connector_in_state(state, connector, connector_state, i) {
7815                 if (connector_state->crtc != &crtc->base)
7816                         continue;
7817
7818                 encoder = to_intel_encoder(connector_state->best_encoder);
7819
7820                 switch (encoder->type) {
7821                 case INTEL_OUTPUT_DSI:
7822                         is_dsi = true;
7823                         break;
7824                 default:
7825                         break;
7826                 }
7827
7828                 num_connectors++;
7829         }
7830
7831         if (is_dsi)
7832                 return 0;
7833
7834         if (!crtc_state->clock_set) {
7835                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7836
7837                 /*
7838                  * Returns a set of divisors for the desired target clock with
7839                  * the given refclk, or FALSE.  The returned values represent
7840                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7841                  * 2) / p1 / p2.
7842                  */
7843                 limit = intel_limit(crtc_state, refclk);
7844                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7845                                                  crtc_state->port_clock,
7846                                                  refclk, NULL, &clock);
7847                 if (!ok) {
7848                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7849                         return -EINVAL;
7850                 }
7851
7852                 /* Compat-code for transition, will disappear. */
7853                 crtc_state->dpll.n = clock.n;
7854                 crtc_state->dpll.m1 = clock.m1;
7855                 crtc_state->dpll.m2 = clock.m2;
7856                 crtc_state->dpll.p1 = clock.p1;
7857                 crtc_state->dpll.p2 = clock.p2;
7858         }
7859
7860         if (IS_GEN2(dev)) {
7861                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7862                                   num_connectors);
7863         } else if (IS_CHERRYVIEW(dev)) {
7864                 chv_compute_dpll(crtc, crtc_state);
7865         } else if (IS_VALLEYVIEW(dev)) {
7866                 vlv_compute_dpll(crtc, crtc_state);
7867         } else {
7868                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7869                                   num_connectors);
7870         }
7871
7872         return 0;
7873 }
7874
7875 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7876                                  struct intel_crtc_state *pipe_config)
7877 {
7878         struct drm_device *dev = crtc->base.dev;
7879         struct drm_i915_private *dev_priv = dev->dev_private;
7880         uint32_t tmp;
7881
7882         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7883                 return;
7884
7885         tmp = I915_READ(PFIT_CONTROL);
7886         if (!(tmp & PFIT_ENABLE))
7887                 return;
7888
7889         /* Check whether the pfit is attached to our pipe. */
7890         if (INTEL_INFO(dev)->gen < 4) {
7891                 if (crtc->pipe != PIPE_B)
7892                         return;
7893         } else {
7894                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7895                         return;
7896         }
7897
7898         pipe_config->gmch_pfit.control = tmp;
7899         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7900         if (INTEL_INFO(dev)->gen < 5)
7901                 pipe_config->gmch_pfit.lvds_border_bits =
7902                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7903 }
7904
7905 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7906                                struct intel_crtc_state *pipe_config)
7907 {
7908         struct drm_device *dev = crtc->base.dev;
7909         struct drm_i915_private *dev_priv = dev->dev_private;
7910         int pipe = pipe_config->cpu_transcoder;
7911         intel_clock_t clock;
7912         u32 mdiv;
7913         int refclk = 100000;
7914
7915         /* In case of MIPI DPLL will not even be used */
7916         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7917                 return;
7918
7919         mutex_lock(&dev_priv->sb_lock);
7920         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7921         mutex_unlock(&dev_priv->sb_lock);
7922
7923         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7924         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7925         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7926         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7927         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7928
7929         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7930 }
7931
7932 static void
7933 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7934                               struct intel_initial_plane_config *plane_config)
7935 {
7936         struct drm_device *dev = crtc->base.dev;
7937         struct drm_i915_private *dev_priv = dev->dev_private;
7938         u32 val, base, offset;
7939         int pipe = crtc->pipe, plane = crtc->plane;
7940         int fourcc, pixel_format;
7941         unsigned int aligned_height;
7942         struct drm_framebuffer *fb;
7943         struct intel_framebuffer *intel_fb;
7944
7945         val = I915_READ(DSPCNTR(plane));
7946         if (!(val & DISPLAY_PLANE_ENABLE))
7947                 return;
7948
7949         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7950         if (!intel_fb) {
7951                 DRM_DEBUG_KMS("failed to alloc fb\n");
7952                 return;
7953         }
7954
7955         fb = &intel_fb->base;
7956
7957         if (INTEL_INFO(dev)->gen >= 4) {
7958                 if (val & DISPPLANE_TILED) {
7959                         plane_config->tiling = I915_TILING_X;
7960                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7961                 }
7962         }
7963
7964         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7965         fourcc = i9xx_format_to_fourcc(pixel_format);
7966         fb->pixel_format = fourcc;
7967         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7968
7969         if (INTEL_INFO(dev)->gen >= 4) {
7970                 if (plane_config->tiling)
7971                         offset = I915_READ(DSPTILEOFF(plane));
7972                 else
7973                         offset = I915_READ(DSPLINOFF(plane));
7974                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7975         } else {
7976                 base = I915_READ(DSPADDR(plane));
7977         }
7978         plane_config->base = base;
7979
7980         val = I915_READ(PIPESRC(pipe));
7981         fb->width = ((val >> 16) & 0xfff) + 1;
7982         fb->height = ((val >> 0) & 0xfff) + 1;
7983
7984         val = I915_READ(DSPSTRIDE(pipe));
7985         fb->pitches[0] = val & 0xffffffc0;
7986
7987         aligned_height = intel_fb_align_height(dev, fb->height,
7988                                                fb->pixel_format,
7989                                                fb->modifier[0]);
7990
7991         plane_config->size = fb->pitches[0] * aligned_height;
7992
7993         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7994                       pipe_name(pipe), plane, fb->width, fb->height,
7995                       fb->bits_per_pixel, base, fb->pitches[0],
7996                       plane_config->size);
7997
7998         plane_config->fb = intel_fb;
7999 }
8000
8001 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8002                                struct intel_crtc_state *pipe_config)
8003 {
8004         struct drm_device *dev = crtc->base.dev;
8005         struct drm_i915_private *dev_priv = dev->dev_private;
8006         int pipe = pipe_config->cpu_transcoder;
8007         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8008         intel_clock_t clock;
8009         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8010         int refclk = 100000;
8011
8012         mutex_lock(&dev_priv->sb_lock);
8013         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8014         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8015         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8016         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8017         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8018         mutex_unlock(&dev_priv->sb_lock);
8019
8020         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8021         clock.m2 = (pll_dw0 & 0xff) << 22;
8022         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8023                 clock.m2 |= pll_dw2 & 0x3fffff;
8024         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8025         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8026         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8027
8028         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8029 }
8030
8031 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8032                                  struct intel_crtc_state *pipe_config)
8033 {
8034         struct drm_device *dev = crtc->base.dev;
8035         struct drm_i915_private *dev_priv = dev->dev_private;
8036         uint32_t tmp;
8037
8038         if (!intel_display_power_is_enabled(dev_priv,
8039                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8040                 return false;
8041
8042         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8043         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8044
8045         tmp = I915_READ(PIPECONF(crtc->pipe));
8046         if (!(tmp & PIPECONF_ENABLE))
8047                 return false;
8048
8049         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8050                 switch (tmp & PIPECONF_BPC_MASK) {
8051                 case PIPECONF_6BPC:
8052                         pipe_config->pipe_bpp = 18;
8053                         break;
8054                 case PIPECONF_8BPC:
8055                         pipe_config->pipe_bpp = 24;
8056                         break;
8057                 case PIPECONF_10BPC:
8058                         pipe_config->pipe_bpp = 30;
8059                         break;
8060                 default:
8061                         break;
8062                 }
8063         }
8064
8065         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8066                 pipe_config->limited_color_range = true;
8067
8068         if (INTEL_INFO(dev)->gen < 4)
8069                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8070
8071         intel_get_pipe_timings(crtc, pipe_config);
8072
8073         i9xx_get_pfit_config(crtc, pipe_config);
8074
8075         if (INTEL_INFO(dev)->gen >= 4) {
8076                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8077                 pipe_config->pixel_multiplier =
8078                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8079                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8080                 pipe_config->dpll_hw_state.dpll_md = tmp;
8081         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8082                 tmp = I915_READ(DPLL(crtc->pipe));
8083                 pipe_config->pixel_multiplier =
8084                         ((tmp & SDVO_MULTIPLIER_MASK)
8085                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8086         } else {
8087                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8088                  * port and will be fixed up in the encoder->get_config
8089                  * function. */
8090                 pipe_config->pixel_multiplier = 1;
8091         }
8092         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8093         if (!IS_VALLEYVIEW(dev)) {
8094                 /*
8095                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8096                  * on 830. Filter it out here so that we don't
8097                  * report errors due to that.
8098                  */
8099                 if (IS_I830(dev))
8100                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8101
8102                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8103                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8104         } else {
8105                 /* Mask out read-only status bits. */
8106                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8107                                                      DPLL_PORTC_READY_MASK |
8108                                                      DPLL_PORTB_READY_MASK);
8109         }
8110
8111         if (IS_CHERRYVIEW(dev))
8112                 chv_crtc_clock_get(crtc, pipe_config);
8113         else if (IS_VALLEYVIEW(dev))
8114                 vlv_crtc_clock_get(crtc, pipe_config);
8115         else
8116                 i9xx_crtc_clock_get(crtc, pipe_config);
8117
8118         return true;
8119 }
8120
8121 static void ironlake_init_pch_refclk(struct drm_device *dev)
8122 {
8123         struct drm_i915_private *dev_priv = dev->dev_private;
8124         struct intel_encoder *encoder;
8125         u32 val, final;
8126         bool has_lvds = false;
8127         bool has_cpu_edp = false;
8128         bool has_panel = false;
8129         bool has_ck505 = false;
8130         bool can_ssc = false;
8131
8132         /* We need to take the global config into account */
8133         for_each_intel_encoder(dev, encoder) {
8134                 switch (encoder->type) {
8135                 case INTEL_OUTPUT_LVDS:
8136                         has_panel = true;
8137                         has_lvds = true;
8138                         break;
8139                 case INTEL_OUTPUT_EDP:
8140                         has_panel = true;
8141                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8142                                 has_cpu_edp = true;
8143                         break;
8144                 default:
8145                         break;
8146                 }
8147         }
8148
8149         if (HAS_PCH_IBX(dev)) {
8150                 has_ck505 = dev_priv->vbt.display_clock_mode;
8151                 can_ssc = has_ck505;
8152         } else {
8153                 has_ck505 = false;
8154                 can_ssc = true;
8155         }
8156
8157         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8158                       has_panel, has_lvds, has_ck505);
8159
8160         /* Ironlake: try to setup display ref clock before DPLL
8161          * enabling. This is only under driver's control after
8162          * PCH B stepping, previous chipset stepping should be
8163          * ignoring this setting.
8164          */
8165         val = I915_READ(PCH_DREF_CONTROL);
8166
8167         /* As we must carefully and slowly disable/enable each source in turn,
8168          * compute the final state we want first and check if we need to
8169          * make any changes at all.
8170          */
8171         final = val;
8172         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8173         if (has_ck505)
8174                 final |= DREF_NONSPREAD_CK505_ENABLE;
8175         else
8176                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8177
8178         final &= ~DREF_SSC_SOURCE_MASK;
8179         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8180         final &= ~DREF_SSC1_ENABLE;
8181
8182         if (has_panel) {
8183                 final |= DREF_SSC_SOURCE_ENABLE;
8184
8185                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8186                         final |= DREF_SSC1_ENABLE;
8187
8188                 if (has_cpu_edp) {
8189                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8190                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8191                         else
8192                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8193                 } else
8194                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8195         } else {
8196                 final |= DREF_SSC_SOURCE_DISABLE;
8197                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8198         }
8199
8200         if (final == val)
8201                 return;
8202
8203         /* Always enable nonspread source */
8204         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8205
8206         if (has_ck505)
8207                 val |= DREF_NONSPREAD_CK505_ENABLE;
8208         else
8209                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8210
8211         if (has_panel) {
8212                 val &= ~DREF_SSC_SOURCE_MASK;
8213                 val |= DREF_SSC_SOURCE_ENABLE;
8214
8215                 /* SSC must be turned on before enabling the CPU output  */
8216                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8217                         DRM_DEBUG_KMS("Using SSC on panel\n");
8218                         val |= DREF_SSC1_ENABLE;
8219                 } else
8220                         val &= ~DREF_SSC1_ENABLE;
8221
8222                 /* Get SSC going before enabling the outputs */
8223                 I915_WRITE(PCH_DREF_CONTROL, val);
8224                 POSTING_READ(PCH_DREF_CONTROL);
8225                 udelay(200);
8226
8227                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8228
8229                 /* Enable CPU source on CPU attached eDP */
8230                 if (has_cpu_edp) {
8231                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8232                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8233                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8234                         } else
8235                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8236                 } else
8237                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8238
8239                 I915_WRITE(PCH_DREF_CONTROL, val);
8240                 POSTING_READ(PCH_DREF_CONTROL);
8241                 udelay(200);
8242         } else {
8243                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8244
8245                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8246
8247                 /* Turn off CPU output */
8248                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8249
8250                 I915_WRITE(PCH_DREF_CONTROL, val);
8251                 POSTING_READ(PCH_DREF_CONTROL);
8252                 udelay(200);
8253
8254                 /* Turn off the SSC source */
8255                 val &= ~DREF_SSC_SOURCE_MASK;
8256                 val |= DREF_SSC_SOURCE_DISABLE;
8257
8258                 /* Turn off SSC1 */
8259                 val &= ~DREF_SSC1_ENABLE;
8260
8261                 I915_WRITE(PCH_DREF_CONTROL, val);
8262                 POSTING_READ(PCH_DREF_CONTROL);
8263                 udelay(200);
8264         }
8265
8266         BUG_ON(val != final);
8267 }
8268
8269 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8270 {
8271         uint32_t tmp;
8272
8273         tmp = I915_READ(SOUTH_CHICKEN2);
8274         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8275         I915_WRITE(SOUTH_CHICKEN2, tmp);
8276
8277         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8278                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8279                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8280
8281         tmp = I915_READ(SOUTH_CHICKEN2);
8282         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8283         I915_WRITE(SOUTH_CHICKEN2, tmp);
8284
8285         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8286                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8287                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8288 }
8289
8290 /* WaMPhyProgramming:hsw */
8291 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8292 {
8293         uint32_t tmp;
8294
8295         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8296         tmp &= ~(0xFF << 24);
8297         tmp |= (0x12 << 24);
8298         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8299
8300         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8301         tmp |= (1 << 11);
8302         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8303
8304         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8305         tmp |= (1 << 11);
8306         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8307
8308         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8309         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8310         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8311
8312         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8313         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8314         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8315
8316         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8317         tmp &= ~(7 << 13);
8318         tmp |= (5 << 13);
8319         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8320
8321         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8322         tmp &= ~(7 << 13);
8323         tmp |= (5 << 13);
8324         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8325
8326         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8327         tmp &= ~0xFF;
8328         tmp |= 0x1C;
8329         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8330
8331         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8332         tmp &= ~0xFF;
8333         tmp |= 0x1C;
8334         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8335
8336         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8337         tmp &= ~(0xFF << 16);
8338         tmp |= (0x1C << 16);
8339         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8340
8341         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8342         tmp &= ~(0xFF << 16);
8343         tmp |= (0x1C << 16);
8344         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8345
8346         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8347         tmp |= (1 << 27);
8348         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8349
8350         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8351         tmp |= (1 << 27);
8352         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8355         tmp &= ~(0xF << 28);
8356         tmp |= (4 << 28);
8357         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8358
8359         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8360         tmp &= ~(0xF << 28);
8361         tmp |= (4 << 28);
8362         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8363 }
8364
8365 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8366  * Programming" based on the parameters passed:
8367  * - Sequence to enable CLKOUT_DP
8368  * - Sequence to enable CLKOUT_DP without spread
8369  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8370  */
8371 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8372                                  bool with_fdi)
8373 {
8374         struct drm_i915_private *dev_priv = dev->dev_private;
8375         uint32_t reg, tmp;
8376
8377         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8378                 with_spread = true;
8379         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8380                  with_fdi, "LP PCH doesn't have FDI\n"))
8381                 with_fdi = false;
8382
8383         mutex_lock(&dev_priv->sb_lock);
8384
8385         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8386         tmp &= ~SBI_SSCCTL_DISABLE;
8387         tmp |= SBI_SSCCTL_PATHALT;
8388         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8389
8390         udelay(24);
8391
8392         if (with_spread) {
8393                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8394                 tmp &= ~SBI_SSCCTL_PATHALT;
8395                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8396
8397                 if (with_fdi) {
8398                         lpt_reset_fdi_mphy(dev_priv);
8399                         lpt_program_fdi_mphy(dev_priv);
8400                 }
8401         }
8402
8403         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8404                SBI_GEN0 : SBI_DBUFF0;
8405         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8406         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8407         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8408
8409         mutex_unlock(&dev_priv->sb_lock);
8410 }
8411
8412 /* Sequence to disable CLKOUT_DP */
8413 static void lpt_disable_clkout_dp(struct drm_device *dev)
8414 {
8415         struct drm_i915_private *dev_priv = dev->dev_private;
8416         uint32_t reg, tmp;
8417
8418         mutex_lock(&dev_priv->sb_lock);
8419
8420         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8421                SBI_GEN0 : SBI_DBUFF0;
8422         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8423         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8424         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8425
8426         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8427         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8428                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8429                         tmp |= SBI_SSCCTL_PATHALT;
8430                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8431                         udelay(32);
8432                 }
8433                 tmp |= SBI_SSCCTL_DISABLE;
8434                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8435         }
8436
8437         mutex_unlock(&dev_priv->sb_lock);
8438 }
8439
8440 static void lpt_init_pch_refclk(struct drm_device *dev)
8441 {
8442         struct intel_encoder *encoder;
8443         bool has_vga = false;
8444
8445         for_each_intel_encoder(dev, encoder) {
8446                 switch (encoder->type) {
8447                 case INTEL_OUTPUT_ANALOG:
8448                         has_vga = true;
8449                         break;
8450                 default:
8451                         break;
8452                 }
8453         }
8454
8455         if (has_vga)
8456                 lpt_enable_clkout_dp(dev, true, true);
8457         else
8458                 lpt_disable_clkout_dp(dev);
8459 }
8460
8461 /*
8462  * Initialize reference clocks when the driver loads
8463  */
8464 void intel_init_pch_refclk(struct drm_device *dev)
8465 {
8466         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8467                 ironlake_init_pch_refclk(dev);
8468         else if (HAS_PCH_LPT(dev))
8469                 lpt_init_pch_refclk(dev);
8470 }
8471
8472 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8473 {
8474         struct drm_device *dev = crtc_state->base.crtc->dev;
8475         struct drm_i915_private *dev_priv = dev->dev_private;
8476         struct drm_atomic_state *state = crtc_state->base.state;
8477         struct drm_connector *connector;
8478         struct drm_connector_state *connector_state;
8479         struct intel_encoder *encoder;
8480         int num_connectors = 0, i;
8481         bool is_lvds = false;
8482
8483         for_each_connector_in_state(state, connector, connector_state, i) {
8484                 if (connector_state->crtc != crtc_state->base.crtc)
8485                         continue;
8486
8487                 encoder = to_intel_encoder(connector_state->best_encoder);
8488
8489                 switch (encoder->type) {
8490                 case INTEL_OUTPUT_LVDS:
8491                         is_lvds = true;
8492                         break;
8493                 default:
8494                         break;
8495                 }
8496                 num_connectors++;
8497         }
8498
8499         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8500                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8501                               dev_priv->vbt.lvds_ssc_freq);
8502                 return dev_priv->vbt.lvds_ssc_freq;
8503         }
8504
8505         return 120000;
8506 }
8507
8508 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8509 {
8510         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8512         int pipe = intel_crtc->pipe;
8513         uint32_t val;
8514
8515         val = 0;
8516
8517         switch (intel_crtc->config->pipe_bpp) {
8518         case 18:
8519                 val |= PIPECONF_6BPC;
8520                 break;
8521         case 24:
8522                 val |= PIPECONF_8BPC;
8523                 break;
8524         case 30:
8525                 val |= PIPECONF_10BPC;
8526                 break;
8527         case 36:
8528                 val |= PIPECONF_12BPC;
8529                 break;
8530         default:
8531                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8532                 BUG();
8533         }
8534
8535         if (intel_crtc->config->dither)
8536                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8537
8538         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8539                 val |= PIPECONF_INTERLACED_ILK;
8540         else
8541                 val |= PIPECONF_PROGRESSIVE;
8542
8543         if (intel_crtc->config->limited_color_range)
8544                 val |= PIPECONF_COLOR_RANGE_SELECT;
8545
8546         I915_WRITE(PIPECONF(pipe), val);
8547         POSTING_READ(PIPECONF(pipe));
8548 }
8549
8550 /*
8551  * Set up the pipe CSC unit.
8552  *
8553  * Currently only full range RGB to limited range RGB conversion
8554  * is supported, but eventually this should handle various
8555  * RGB<->YCbCr scenarios as well.
8556  */
8557 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8558 {
8559         struct drm_device *dev = crtc->dev;
8560         struct drm_i915_private *dev_priv = dev->dev_private;
8561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8562         int pipe = intel_crtc->pipe;
8563         uint16_t coeff = 0x7800; /* 1.0 */
8564
8565         /*
8566          * TODO: Check what kind of values actually come out of the pipe
8567          * with these coeff/postoff values and adjust to get the best
8568          * accuracy. Perhaps we even need to take the bpc value into
8569          * consideration.
8570          */
8571
8572         if (intel_crtc->config->limited_color_range)
8573                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8574
8575         /*
8576          * GY/GU and RY/RU should be the other way around according
8577          * to BSpec, but reality doesn't agree. Just set them up in
8578          * a way that results in the correct picture.
8579          */
8580         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8581         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8582
8583         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8584         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8585
8586         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8587         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8588
8589         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8590         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8591         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8592
8593         if (INTEL_INFO(dev)->gen > 6) {
8594                 uint16_t postoff = 0;
8595
8596                 if (intel_crtc->config->limited_color_range)
8597                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8598
8599                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8600                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8601                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8602
8603                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8604         } else {
8605                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8606
8607                 if (intel_crtc->config->limited_color_range)
8608                         mode |= CSC_BLACK_SCREEN_OFFSET;
8609
8610                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8611         }
8612 }
8613
8614 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8615 {
8616         struct drm_device *dev = crtc->dev;
8617         struct drm_i915_private *dev_priv = dev->dev_private;
8618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8619         enum pipe pipe = intel_crtc->pipe;
8620         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8621         uint32_t val;
8622
8623         val = 0;
8624
8625         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8626                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8627
8628         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8629                 val |= PIPECONF_INTERLACED_ILK;
8630         else
8631                 val |= PIPECONF_PROGRESSIVE;
8632
8633         I915_WRITE(PIPECONF(cpu_transcoder), val);
8634         POSTING_READ(PIPECONF(cpu_transcoder));
8635
8636         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8637         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8638
8639         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8640                 val = 0;
8641
8642                 switch (intel_crtc->config->pipe_bpp) {
8643                 case 18:
8644                         val |= PIPEMISC_DITHER_6_BPC;
8645                         break;
8646                 case 24:
8647                         val |= PIPEMISC_DITHER_8_BPC;
8648                         break;
8649                 case 30:
8650                         val |= PIPEMISC_DITHER_10_BPC;
8651                         break;
8652                 case 36:
8653                         val |= PIPEMISC_DITHER_12_BPC;
8654                         break;
8655                 default:
8656                         /* Case prevented by pipe_config_set_bpp. */
8657                         BUG();
8658                 }
8659
8660                 if (intel_crtc->config->dither)
8661                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8662
8663                 I915_WRITE(PIPEMISC(pipe), val);
8664         }
8665 }
8666
8667 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8668                                     struct intel_crtc_state *crtc_state,
8669                                     intel_clock_t *clock,
8670                                     bool *has_reduced_clock,
8671                                     intel_clock_t *reduced_clock)
8672 {
8673         struct drm_device *dev = crtc->dev;
8674         struct drm_i915_private *dev_priv = dev->dev_private;
8675         int refclk;
8676         const intel_limit_t *limit;
8677         bool ret;
8678
8679         refclk = ironlake_get_refclk(crtc_state);
8680
8681         /*
8682          * Returns a set of divisors for the desired target clock with the given
8683          * refclk, or FALSE.  The returned values represent the clock equation:
8684          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8685          */
8686         limit = intel_limit(crtc_state, refclk);
8687         ret = dev_priv->display.find_dpll(limit, crtc_state,
8688                                           crtc_state->port_clock,
8689                                           refclk, NULL, clock);
8690         if (!ret)
8691                 return false;
8692
8693         return true;
8694 }
8695
8696 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8697 {
8698         /*
8699          * Account for spread spectrum to avoid
8700          * oversubscribing the link. Max center spread
8701          * is 2.5%; use 5% for safety's sake.
8702          */
8703         u32 bps = target_clock * bpp * 21 / 20;
8704         return DIV_ROUND_UP(bps, link_bw * 8);
8705 }
8706
8707 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8708 {
8709         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8710 }
8711
8712 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8713                                       struct intel_crtc_state *crtc_state,
8714                                       u32 *fp,
8715                                       intel_clock_t *reduced_clock, u32 *fp2)
8716 {
8717         struct drm_crtc *crtc = &intel_crtc->base;
8718         struct drm_device *dev = crtc->dev;
8719         struct drm_i915_private *dev_priv = dev->dev_private;
8720         struct drm_atomic_state *state = crtc_state->base.state;
8721         struct drm_connector *connector;
8722         struct drm_connector_state *connector_state;
8723         struct intel_encoder *encoder;
8724         uint32_t dpll;
8725         int factor, num_connectors = 0, i;
8726         bool is_lvds = false, is_sdvo = false;
8727
8728         for_each_connector_in_state(state, connector, connector_state, i) {
8729                 if (connector_state->crtc != crtc_state->base.crtc)
8730                         continue;
8731
8732                 encoder = to_intel_encoder(connector_state->best_encoder);
8733
8734                 switch (encoder->type) {
8735                 case INTEL_OUTPUT_LVDS:
8736                         is_lvds = true;
8737                         break;
8738                 case INTEL_OUTPUT_SDVO:
8739                 case INTEL_OUTPUT_HDMI:
8740                         is_sdvo = true;
8741                         break;
8742                 default:
8743                         break;
8744                 }
8745
8746                 num_connectors++;
8747         }
8748
8749         /* Enable autotuning of the PLL clock (if permissible) */
8750         factor = 21;
8751         if (is_lvds) {
8752                 if ((intel_panel_use_ssc(dev_priv) &&
8753                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8754                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8755                         factor = 25;
8756         } else if (crtc_state->sdvo_tv_clock)
8757                 factor = 20;
8758
8759         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8760                 *fp |= FP_CB_TUNE;
8761
8762         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8763                 *fp2 |= FP_CB_TUNE;
8764
8765         dpll = 0;
8766
8767         if (is_lvds)
8768                 dpll |= DPLLB_MODE_LVDS;
8769         else
8770                 dpll |= DPLLB_MODE_DAC_SERIAL;
8771
8772         dpll |= (crtc_state->pixel_multiplier - 1)
8773                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8774
8775         if (is_sdvo)
8776                 dpll |= DPLL_SDVO_HIGH_SPEED;
8777         if (crtc_state->has_dp_encoder)
8778                 dpll |= DPLL_SDVO_HIGH_SPEED;
8779
8780         /* compute bitmask from p1 value */
8781         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8782         /* also FPA1 */
8783         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8784
8785         switch (crtc_state->dpll.p2) {
8786         case 5:
8787                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8788                 break;
8789         case 7:
8790                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8791                 break;
8792         case 10:
8793                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8794                 break;
8795         case 14:
8796                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8797                 break;
8798         }
8799
8800         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8801                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8802         else
8803                 dpll |= PLL_REF_INPUT_DREFCLK;
8804
8805         return dpll | DPLL_VCO_ENABLE;
8806 }
8807
8808 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8809                                        struct intel_crtc_state *crtc_state)
8810 {
8811         struct drm_device *dev = crtc->base.dev;
8812         intel_clock_t clock, reduced_clock;
8813         u32 dpll = 0, fp = 0, fp2 = 0;
8814         bool ok, has_reduced_clock = false;
8815         bool is_lvds = false;
8816         struct intel_shared_dpll *pll;
8817
8818         memset(&crtc_state->dpll_hw_state, 0,
8819                sizeof(crtc_state->dpll_hw_state));
8820
8821         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8822
8823         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8824              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8825
8826         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8827                                      &has_reduced_clock, &reduced_clock);
8828         if (!ok && !crtc_state->clock_set) {
8829                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8830                 return -EINVAL;
8831         }
8832         /* Compat-code for transition, will disappear. */
8833         if (!crtc_state->clock_set) {
8834                 crtc_state->dpll.n = clock.n;
8835                 crtc_state->dpll.m1 = clock.m1;
8836                 crtc_state->dpll.m2 = clock.m2;
8837                 crtc_state->dpll.p1 = clock.p1;
8838                 crtc_state->dpll.p2 = clock.p2;
8839         }
8840
8841         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8842         if (crtc_state->has_pch_encoder) {
8843                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8844                 if (has_reduced_clock)
8845                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8846
8847                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8848                                              &fp, &reduced_clock,
8849                                              has_reduced_clock ? &fp2 : NULL);
8850
8851                 crtc_state->dpll_hw_state.dpll = dpll;
8852                 crtc_state->dpll_hw_state.fp0 = fp;
8853                 if (has_reduced_clock)
8854                         crtc_state->dpll_hw_state.fp1 = fp2;
8855                 else
8856                         crtc_state->dpll_hw_state.fp1 = fp;
8857
8858                 pll = intel_get_shared_dpll(crtc, crtc_state);
8859                 if (pll == NULL) {
8860                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8861                                          pipe_name(crtc->pipe));
8862                         return -EINVAL;
8863                 }
8864         }
8865
8866         if (is_lvds && has_reduced_clock)
8867                 crtc->lowfreq_avail = true;
8868         else
8869                 crtc->lowfreq_avail = false;
8870
8871         return 0;
8872 }
8873
8874 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8875                                          struct intel_link_m_n *m_n)
8876 {
8877         struct drm_device *dev = crtc->base.dev;
8878         struct drm_i915_private *dev_priv = dev->dev_private;
8879         enum pipe pipe = crtc->pipe;
8880
8881         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8882         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8883         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8884                 & ~TU_SIZE_MASK;
8885         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8886         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8887                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8888 }
8889
8890 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8891                                          enum transcoder transcoder,
8892                                          struct intel_link_m_n *m_n,
8893                                          struct intel_link_m_n *m2_n2)
8894 {
8895         struct drm_device *dev = crtc->base.dev;
8896         struct drm_i915_private *dev_priv = dev->dev_private;
8897         enum pipe pipe = crtc->pipe;
8898
8899         if (INTEL_INFO(dev)->gen >= 5) {
8900                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8901                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8902                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8903                         & ~TU_SIZE_MASK;
8904                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8905                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8906                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8907                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8908                  * gen < 8) and if DRRS is supported (to make sure the
8909                  * registers are not unnecessarily read).
8910                  */
8911                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8912                         crtc->config->has_drrs) {
8913                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8914                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8915                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8916                                         & ~TU_SIZE_MASK;
8917                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8918                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8919                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8920                 }
8921         } else {
8922                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8923                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8924                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8925                         & ~TU_SIZE_MASK;
8926                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8927                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8928                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8929         }
8930 }
8931
8932 void intel_dp_get_m_n(struct intel_crtc *crtc,
8933                       struct intel_crtc_state *pipe_config)
8934 {
8935         if (pipe_config->has_pch_encoder)
8936                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8937         else
8938                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8939                                              &pipe_config->dp_m_n,
8940                                              &pipe_config->dp_m2_n2);
8941 }
8942
8943 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8944                                         struct intel_crtc_state *pipe_config)
8945 {
8946         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8947                                      &pipe_config->fdi_m_n, NULL);
8948 }
8949
8950 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8951                                     struct intel_crtc_state *pipe_config)
8952 {
8953         struct drm_device *dev = crtc->base.dev;
8954         struct drm_i915_private *dev_priv = dev->dev_private;
8955         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8956         uint32_t ps_ctrl = 0;
8957         int id = -1;
8958         int i;
8959
8960         /* find scaler attached to this pipe */
8961         for (i = 0; i < crtc->num_scalers; i++) {
8962                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8963                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8964                         id = i;
8965                         pipe_config->pch_pfit.enabled = true;
8966                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8967                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8968                         break;
8969                 }
8970         }
8971
8972         scaler_state->scaler_id = id;
8973         if (id >= 0) {
8974                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8975         } else {
8976                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8977         }
8978 }
8979
8980 static void
8981 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8982                                  struct intel_initial_plane_config *plane_config)
8983 {
8984         struct drm_device *dev = crtc->base.dev;
8985         struct drm_i915_private *dev_priv = dev->dev_private;
8986         u32 val, base, offset, stride_mult, tiling;
8987         int pipe = crtc->pipe;
8988         int fourcc, pixel_format;
8989         unsigned int aligned_height;
8990         struct drm_framebuffer *fb;
8991         struct intel_framebuffer *intel_fb;
8992
8993         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8994         if (!intel_fb) {
8995                 DRM_DEBUG_KMS("failed to alloc fb\n");
8996                 return;
8997         }
8998
8999         fb = &intel_fb->base;
9000
9001         val = I915_READ(PLANE_CTL(pipe, 0));
9002         if (!(val & PLANE_CTL_ENABLE))
9003                 goto error;
9004
9005         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9006         fourcc = skl_format_to_fourcc(pixel_format,
9007                                       val & PLANE_CTL_ORDER_RGBX,
9008                                       val & PLANE_CTL_ALPHA_MASK);
9009         fb->pixel_format = fourcc;
9010         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9011
9012         tiling = val & PLANE_CTL_TILED_MASK;
9013         switch (tiling) {
9014         case PLANE_CTL_TILED_LINEAR:
9015                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9016                 break;
9017         case PLANE_CTL_TILED_X:
9018                 plane_config->tiling = I915_TILING_X;
9019                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9020                 break;
9021         case PLANE_CTL_TILED_Y:
9022                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9023                 break;
9024         case PLANE_CTL_TILED_YF:
9025                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9026                 break;
9027         default:
9028                 MISSING_CASE(tiling);
9029                 goto error;
9030         }
9031
9032         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9033         plane_config->base = base;
9034
9035         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9036
9037         val = I915_READ(PLANE_SIZE(pipe, 0));
9038         fb->height = ((val >> 16) & 0xfff) + 1;
9039         fb->width = ((val >> 0) & 0x1fff) + 1;
9040
9041         val = I915_READ(PLANE_STRIDE(pipe, 0));
9042         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9043                                                 fb->pixel_format);
9044         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9045
9046         aligned_height = intel_fb_align_height(dev, fb->height,
9047                                                fb->pixel_format,
9048                                                fb->modifier[0]);
9049
9050         plane_config->size = fb->pitches[0] * aligned_height;
9051
9052         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9053                       pipe_name(pipe), fb->width, fb->height,
9054                       fb->bits_per_pixel, base, fb->pitches[0],
9055                       plane_config->size);
9056
9057         plane_config->fb = intel_fb;
9058         return;
9059
9060 error:
9061         kfree(fb);
9062 }
9063
9064 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9065                                      struct intel_crtc_state *pipe_config)
9066 {
9067         struct drm_device *dev = crtc->base.dev;
9068         struct drm_i915_private *dev_priv = dev->dev_private;
9069         uint32_t tmp;
9070
9071         tmp = I915_READ(PF_CTL(crtc->pipe));
9072
9073         if (tmp & PF_ENABLE) {
9074                 pipe_config->pch_pfit.enabled = true;
9075                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9076                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9077
9078                 /* We currently do not free assignements of panel fitters on
9079                  * ivb/hsw (since we don't use the higher upscaling modes which
9080                  * differentiates them) so just WARN about this case for now. */
9081                 if (IS_GEN7(dev)) {
9082                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9083                                 PF_PIPE_SEL_IVB(crtc->pipe));
9084                 }
9085         }
9086 }
9087
9088 static void
9089 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9090                                   struct intel_initial_plane_config *plane_config)
9091 {
9092         struct drm_device *dev = crtc->base.dev;
9093         struct drm_i915_private *dev_priv = dev->dev_private;
9094         u32 val, base, offset;
9095         int pipe = crtc->pipe;
9096         int fourcc, pixel_format;
9097         unsigned int aligned_height;
9098         struct drm_framebuffer *fb;
9099         struct intel_framebuffer *intel_fb;
9100
9101         val = I915_READ(DSPCNTR(pipe));
9102         if (!(val & DISPLAY_PLANE_ENABLE))
9103                 return;
9104
9105         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9106         if (!intel_fb) {
9107                 DRM_DEBUG_KMS("failed to alloc fb\n");
9108                 return;
9109         }
9110
9111         fb = &intel_fb->base;
9112
9113         if (INTEL_INFO(dev)->gen >= 4) {
9114                 if (val & DISPPLANE_TILED) {
9115                         plane_config->tiling = I915_TILING_X;
9116                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9117                 }
9118         }
9119
9120         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9121         fourcc = i9xx_format_to_fourcc(pixel_format);
9122         fb->pixel_format = fourcc;
9123         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9124
9125         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9126         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9127                 offset = I915_READ(DSPOFFSET(pipe));
9128         } else {
9129                 if (plane_config->tiling)
9130                         offset = I915_READ(DSPTILEOFF(pipe));
9131                 else
9132                         offset = I915_READ(DSPLINOFF(pipe));
9133         }
9134         plane_config->base = base;
9135
9136         val = I915_READ(PIPESRC(pipe));
9137         fb->width = ((val >> 16) & 0xfff) + 1;
9138         fb->height = ((val >> 0) & 0xfff) + 1;
9139
9140         val = I915_READ(DSPSTRIDE(pipe));
9141         fb->pitches[0] = val & 0xffffffc0;
9142
9143         aligned_height = intel_fb_align_height(dev, fb->height,
9144                                                fb->pixel_format,
9145                                                fb->modifier[0]);
9146
9147         plane_config->size = fb->pitches[0] * aligned_height;
9148
9149         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9150                       pipe_name(pipe), fb->width, fb->height,
9151                       fb->bits_per_pixel, base, fb->pitches[0],
9152                       plane_config->size);
9153
9154         plane_config->fb = intel_fb;
9155 }
9156
9157 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9158                                      struct intel_crtc_state *pipe_config)
9159 {
9160         struct drm_device *dev = crtc->base.dev;
9161         struct drm_i915_private *dev_priv = dev->dev_private;
9162         uint32_t tmp;
9163
9164         if (!intel_display_power_is_enabled(dev_priv,
9165                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9166                 return false;
9167
9168         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9169         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9170
9171         tmp = I915_READ(PIPECONF(crtc->pipe));
9172         if (!(tmp & PIPECONF_ENABLE))
9173                 return false;
9174
9175         switch (tmp & PIPECONF_BPC_MASK) {
9176         case PIPECONF_6BPC:
9177                 pipe_config->pipe_bpp = 18;
9178                 break;
9179         case PIPECONF_8BPC:
9180                 pipe_config->pipe_bpp = 24;
9181                 break;
9182         case PIPECONF_10BPC:
9183                 pipe_config->pipe_bpp = 30;
9184                 break;
9185         case PIPECONF_12BPC:
9186                 pipe_config->pipe_bpp = 36;
9187                 break;
9188         default:
9189                 break;
9190         }
9191
9192         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9193                 pipe_config->limited_color_range = true;
9194
9195         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9196                 struct intel_shared_dpll *pll;
9197
9198                 pipe_config->has_pch_encoder = true;
9199
9200                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9201                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9202                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9203
9204                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9205
9206                 if (HAS_PCH_IBX(dev_priv->dev)) {
9207                         pipe_config->shared_dpll =
9208                                 (enum intel_dpll_id) crtc->pipe;
9209                 } else {
9210                         tmp = I915_READ(PCH_DPLL_SEL);
9211                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9212                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9213                         else
9214                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9215                 }
9216
9217                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9218
9219                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9220                                            &pipe_config->dpll_hw_state));
9221
9222                 tmp = pipe_config->dpll_hw_state.dpll;
9223                 pipe_config->pixel_multiplier =
9224                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9225                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9226
9227                 ironlake_pch_clock_get(crtc, pipe_config);
9228         } else {
9229                 pipe_config->pixel_multiplier = 1;
9230         }
9231
9232         intel_get_pipe_timings(crtc, pipe_config);
9233
9234         ironlake_get_pfit_config(crtc, pipe_config);
9235
9236         return true;
9237 }
9238
9239 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9240 {
9241         struct drm_device *dev = dev_priv->dev;
9242         struct intel_crtc *crtc;
9243
9244         for_each_intel_crtc(dev, crtc)
9245                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9246                      pipe_name(crtc->pipe));
9247
9248         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9249         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9250         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9251         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9252         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9253         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9254              "CPU PWM1 enabled\n");
9255         if (IS_HASWELL(dev))
9256                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9257                      "CPU PWM2 enabled\n");
9258         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9259              "PCH PWM1 enabled\n");
9260         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9261              "Utility pin enabled\n");
9262         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9263
9264         /*
9265          * In theory we can still leave IRQs enabled, as long as only the HPD
9266          * interrupts remain enabled. We used to check for that, but since it's
9267          * gen-specific and since we only disable LCPLL after we fully disable
9268          * the interrupts, the check below should be enough.
9269          */
9270         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9271 }
9272
9273 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9274 {
9275         struct drm_device *dev = dev_priv->dev;
9276
9277         if (IS_HASWELL(dev))
9278                 return I915_READ(D_COMP_HSW);
9279         else
9280                 return I915_READ(D_COMP_BDW);
9281 }
9282
9283 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9284 {
9285         struct drm_device *dev = dev_priv->dev;
9286
9287         if (IS_HASWELL(dev)) {
9288                 mutex_lock(&dev_priv->rps.hw_lock);
9289                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9290                                             val))
9291                         DRM_ERROR("Failed to write to D_COMP\n");
9292                 mutex_unlock(&dev_priv->rps.hw_lock);
9293         } else {
9294                 I915_WRITE(D_COMP_BDW, val);
9295                 POSTING_READ(D_COMP_BDW);
9296         }
9297 }
9298
9299 /*
9300  * This function implements pieces of two sequences from BSpec:
9301  * - Sequence for display software to disable LCPLL
9302  * - Sequence for display software to allow package C8+
9303  * The steps implemented here are just the steps that actually touch the LCPLL
9304  * register. Callers should take care of disabling all the display engine
9305  * functions, doing the mode unset, fixing interrupts, etc.
9306  */
9307 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9308                               bool switch_to_fclk, bool allow_power_down)
9309 {
9310         uint32_t val;
9311
9312         assert_can_disable_lcpll(dev_priv);
9313
9314         val = I915_READ(LCPLL_CTL);
9315
9316         if (switch_to_fclk) {
9317                 val |= LCPLL_CD_SOURCE_FCLK;
9318                 I915_WRITE(LCPLL_CTL, val);
9319
9320                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9321                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9322                         DRM_ERROR("Switching to FCLK failed\n");
9323
9324                 val = I915_READ(LCPLL_CTL);
9325         }
9326
9327         val |= LCPLL_PLL_DISABLE;
9328         I915_WRITE(LCPLL_CTL, val);
9329         POSTING_READ(LCPLL_CTL);
9330
9331         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9332                 DRM_ERROR("LCPLL still locked\n");
9333
9334         val = hsw_read_dcomp(dev_priv);
9335         val |= D_COMP_COMP_DISABLE;
9336         hsw_write_dcomp(dev_priv, val);
9337         ndelay(100);
9338
9339         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9340                      1))
9341                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9342
9343         if (allow_power_down) {
9344                 val = I915_READ(LCPLL_CTL);
9345                 val |= LCPLL_POWER_DOWN_ALLOW;
9346                 I915_WRITE(LCPLL_CTL, val);
9347                 POSTING_READ(LCPLL_CTL);
9348         }
9349 }
9350
9351 /*
9352  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9353  * source.
9354  */
9355 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9356 {
9357         uint32_t val;
9358
9359         val = I915_READ(LCPLL_CTL);
9360
9361         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9362                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9363                 return;
9364
9365         /*
9366          * Make sure we're not on PC8 state before disabling PC8, otherwise
9367          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9368          */
9369         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9370
9371         if (val & LCPLL_POWER_DOWN_ALLOW) {
9372                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9373                 I915_WRITE(LCPLL_CTL, val);
9374                 POSTING_READ(LCPLL_CTL);
9375         }
9376
9377         val = hsw_read_dcomp(dev_priv);
9378         val |= D_COMP_COMP_FORCE;
9379         val &= ~D_COMP_COMP_DISABLE;
9380         hsw_write_dcomp(dev_priv, val);
9381
9382         val = I915_READ(LCPLL_CTL);
9383         val &= ~LCPLL_PLL_DISABLE;
9384         I915_WRITE(LCPLL_CTL, val);
9385
9386         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9387                 DRM_ERROR("LCPLL not locked yet\n");
9388
9389         if (val & LCPLL_CD_SOURCE_FCLK) {
9390                 val = I915_READ(LCPLL_CTL);
9391                 val &= ~LCPLL_CD_SOURCE_FCLK;
9392                 I915_WRITE(LCPLL_CTL, val);
9393
9394                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9395                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9396                         DRM_ERROR("Switching back to LCPLL failed\n");
9397         }
9398
9399         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9400         intel_update_cdclk(dev_priv->dev);
9401 }
9402
9403 /*
9404  * Package states C8 and deeper are really deep PC states that can only be
9405  * reached when all the devices on the system allow it, so even if the graphics
9406  * device allows PC8+, it doesn't mean the system will actually get to these
9407  * states. Our driver only allows PC8+ when going into runtime PM.
9408  *
9409  * The requirements for PC8+ are that all the outputs are disabled, the power
9410  * well is disabled and most interrupts are disabled, and these are also
9411  * requirements for runtime PM. When these conditions are met, we manually do
9412  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9413  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9414  * hang the machine.
9415  *
9416  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9417  * the state of some registers, so when we come back from PC8+ we need to
9418  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9419  * need to take care of the registers kept by RC6. Notice that this happens even
9420  * if we don't put the device in PCI D3 state (which is what currently happens
9421  * because of the runtime PM support).
9422  *
9423  * For more, read "Display Sequences for Package C8" on the hardware
9424  * documentation.
9425  */
9426 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9427 {
9428         struct drm_device *dev = dev_priv->dev;
9429         uint32_t val;
9430
9431         DRM_DEBUG_KMS("Enabling package C8+\n");
9432
9433         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9434                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9435                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9436                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9437         }
9438
9439         lpt_disable_clkout_dp(dev);
9440         hsw_disable_lcpll(dev_priv, true, true);
9441 }
9442
9443 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9444 {
9445         struct drm_device *dev = dev_priv->dev;
9446         uint32_t val;
9447
9448         DRM_DEBUG_KMS("Disabling package C8+\n");
9449
9450         hsw_restore_lcpll(dev_priv);
9451         lpt_init_pch_refclk(dev);
9452
9453         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9454                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9455                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9456                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9457         }
9458
9459         intel_prepare_ddi(dev);
9460 }
9461
9462 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9463 {
9464         struct drm_device *dev = old_state->dev;
9465         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9466
9467         broxton_set_cdclk(dev, req_cdclk);
9468 }
9469
9470 /* compute the max rate for new configuration */
9471 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9472 {
9473         struct intel_crtc *intel_crtc;
9474         struct intel_crtc_state *crtc_state;
9475         int max_pixel_rate = 0;
9476
9477         for_each_intel_crtc(state->dev, intel_crtc) {
9478                 int pixel_rate;
9479
9480                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9481                 if (IS_ERR(crtc_state))
9482                         return PTR_ERR(crtc_state);
9483
9484                 if (!crtc_state->base.enable)
9485                         continue;
9486
9487                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9488
9489                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9490                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9491                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9492
9493                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9494         }
9495
9496         return max_pixel_rate;
9497 }
9498
9499 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9500 {
9501         struct drm_i915_private *dev_priv = dev->dev_private;
9502         uint32_t val, data;
9503         int ret;
9504
9505         if (WARN((I915_READ(LCPLL_CTL) &
9506                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9507                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9508                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9509                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9510                  "trying to change cdclk frequency with cdclk not enabled\n"))
9511                 return;
9512
9513         mutex_lock(&dev_priv->rps.hw_lock);
9514         ret = sandybridge_pcode_write(dev_priv,
9515                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9516         mutex_unlock(&dev_priv->rps.hw_lock);
9517         if (ret) {
9518                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9519                 return;
9520         }
9521
9522         val = I915_READ(LCPLL_CTL);
9523         val |= LCPLL_CD_SOURCE_FCLK;
9524         I915_WRITE(LCPLL_CTL, val);
9525
9526         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9527                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9528                 DRM_ERROR("Switching to FCLK failed\n");
9529
9530         val = I915_READ(LCPLL_CTL);
9531         val &= ~LCPLL_CLK_FREQ_MASK;
9532
9533         switch (cdclk) {
9534         case 450000:
9535                 val |= LCPLL_CLK_FREQ_450;
9536                 data = 0;
9537                 break;
9538         case 540000:
9539                 val |= LCPLL_CLK_FREQ_54O_BDW;
9540                 data = 1;
9541                 break;
9542         case 337500:
9543                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9544                 data = 2;
9545                 break;
9546         case 675000:
9547                 val |= LCPLL_CLK_FREQ_675_BDW;
9548                 data = 3;
9549                 break;
9550         default:
9551                 WARN(1, "invalid cdclk frequency\n");
9552                 return;
9553         }
9554
9555         I915_WRITE(LCPLL_CTL, val);
9556
9557         val = I915_READ(LCPLL_CTL);
9558         val &= ~LCPLL_CD_SOURCE_FCLK;
9559         I915_WRITE(LCPLL_CTL, val);
9560
9561         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9562                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9563                 DRM_ERROR("Switching back to LCPLL failed\n");
9564
9565         mutex_lock(&dev_priv->rps.hw_lock);
9566         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9567         mutex_unlock(&dev_priv->rps.hw_lock);
9568
9569         intel_update_cdclk(dev);
9570
9571         WARN(cdclk != dev_priv->cdclk_freq,
9572              "cdclk requested %d kHz but got %d kHz\n",
9573              cdclk, dev_priv->cdclk_freq);
9574 }
9575
9576 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9577 {
9578         struct drm_i915_private *dev_priv = to_i915(state->dev);
9579         int max_pixclk = ilk_max_pixel_rate(state);
9580         int cdclk;
9581
9582         /*
9583          * FIXME should also account for plane ratio
9584          * once 64bpp pixel formats are supported.
9585          */
9586         if (max_pixclk > 540000)
9587                 cdclk = 675000;
9588         else if (max_pixclk > 450000)
9589                 cdclk = 540000;
9590         else if (max_pixclk > 337500)
9591                 cdclk = 450000;
9592         else
9593                 cdclk = 337500;
9594
9595         /*
9596          * FIXME move the cdclk caclulation to
9597          * compute_config() so we can fail gracegully.
9598          */
9599         if (cdclk > dev_priv->max_cdclk_freq) {
9600                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9601                           cdclk, dev_priv->max_cdclk_freq);
9602                 cdclk = dev_priv->max_cdclk_freq;
9603         }
9604
9605         to_intel_atomic_state(state)->cdclk = cdclk;
9606
9607         return 0;
9608 }
9609
9610 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9611 {
9612         struct drm_device *dev = old_state->dev;
9613         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9614
9615         broadwell_set_cdclk(dev, req_cdclk);
9616 }
9617
9618 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9619                                       struct intel_crtc_state *crtc_state)
9620 {
9621         if (!intel_ddi_pll_select(crtc, crtc_state))
9622                 return -EINVAL;
9623
9624         crtc->lowfreq_avail = false;
9625
9626         return 0;
9627 }
9628
9629 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9630                                 enum port port,
9631                                 struct intel_crtc_state *pipe_config)
9632 {
9633         switch (port) {
9634         case PORT_A:
9635                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9636                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9637                 break;
9638         case PORT_B:
9639                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9640                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9641                 break;
9642         case PORT_C:
9643                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9644                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9645                 break;
9646         default:
9647                 DRM_ERROR("Incorrect port type\n");
9648         }
9649 }
9650
9651 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9652                                 enum port port,
9653                                 struct intel_crtc_state *pipe_config)
9654 {
9655         u32 temp, dpll_ctl1;
9656
9657         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9658         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9659
9660         switch (pipe_config->ddi_pll_sel) {
9661         case SKL_DPLL0:
9662                 /*
9663                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9664                  * of the shared DPLL framework and thus needs to be read out
9665                  * separately
9666                  */
9667                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9668                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9669                 break;
9670         case SKL_DPLL1:
9671                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9672                 break;
9673         case SKL_DPLL2:
9674                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9675                 break;
9676         case SKL_DPLL3:
9677                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9678                 break;
9679         }
9680 }
9681
9682 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9683                                 enum port port,
9684                                 struct intel_crtc_state *pipe_config)
9685 {
9686         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9687
9688         switch (pipe_config->ddi_pll_sel) {
9689         case PORT_CLK_SEL_WRPLL1:
9690                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9691                 break;
9692         case PORT_CLK_SEL_WRPLL2:
9693                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9694                 break;
9695         }
9696 }
9697
9698 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9699                                        struct intel_crtc_state *pipe_config)
9700 {
9701         struct drm_device *dev = crtc->base.dev;
9702         struct drm_i915_private *dev_priv = dev->dev_private;
9703         struct intel_shared_dpll *pll;
9704         enum port port;
9705         uint32_t tmp;
9706
9707         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9708
9709         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9710
9711         if (IS_SKYLAKE(dev))
9712                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9713         else if (IS_BROXTON(dev))
9714                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9715         else
9716                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9717
9718         if (pipe_config->shared_dpll >= 0) {
9719                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9720
9721                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9722                                            &pipe_config->dpll_hw_state));
9723         }
9724
9725         /*
9726          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9727          * DDI E. So just check whether this pipe is wired to DDI E and whether
9728          * the PCH transcoder is on.
9729          */
9730         if (INTEL_INFO(dev)->gen < 9 &&
9731             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9732                 pipe_config->has_pch_encoder = true;
9733
9734                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9735                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9736                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9737
9738                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9739         }
9740 }
9741
9742 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9743                                     struct intel_crtc_state *pipe_config)
9744 {
9745         struct drm_device *dev = crtc->base.dev;
9746         struct drm_i915_private *dev_priv = dev->dev_private;
9747         enum intel_display_power_domain pfit_domain;
9748         uint32_t tmp;
9749
9750         if (!intel_display_power_is_enabled(dev_priv,
9751                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9752                 return false;
9753
9754         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9755         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9756
9757         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9758         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9759                 enum pipe trans_edp_pipe;
9760                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9761                 default:
9762                         WARN(1, "unknown pipe linked to edp transcoder\n");
9763                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9764                 case TRANS_DDI_EDP_INPUT_A_ON:
9765                         trans_edp_pipe = PIPE_A;
9766                         break;
9767                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9768                         trans_edp_pipe = PIPE_B;
9769                         break;
9770                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9771                         trans_edp_pipe = PIPE_C;
9772                         break;
9773                 }
9774
9775                 if (trans_edp_pipe == crtc->pipe)
9776                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9777         }
9778
9779         if (!intel_display_power_is_enabled(dev_priv,
9780                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9781                 return false;
9782
9783         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9784         if (!(tmp & PIPECONF_ENABLE))
9785                 return false;
9786
9787         haswell_get_ddi_port_state(crtc, pipe_config);
9788
9789         intel_get_pipe_timings(crtc, pipe_config);
9790
9791         if (INTEL_INFO(dev)->gen >= 9) {
9792                 skl_init_scalers(dev, crtc, pipe_config);
9793         }
9794
9795         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9796
9797         if (INTEL_INFO(dev)->gen >= 9) {
9798                 pipe_config->scaler_state.scaler_id = -1;
9799                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9800         }
9801
9802         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9803                 if (INTEL_INFO(dev)->gen == 9)
9804                         skylake_get_pfit_config(crtc, pipe_config);
9805                 else if (INTEL_INFO(dev)->gen < 9)
9806                         ironlake_get_pfit_config(crtc, pipe_config);
9807                 else
9808                         MISSING_CASE(INTEL_INFO(dev)->gen);
9809         }
9810
9811         if (IS_HASWELL(dev))
9812                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9813                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9814
9815         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9816                 pipe_config->pixel_multiplier =
9817                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9818         } else {
9819                 pipe_config->pixel_multiplier = 1;
9820         }
9821
9822         return true;
9823 }
9824
9825 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9826 {
9827         struct drm_device *dev = crtc->dev;
9828         struct drm_i915_private *dev_priv = dev->dev_private;
9829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9830         uint32_t cntl = 0, size = 0;
9831
9832         if (base) {
9833                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9834                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9835                 unsigned int stride = roundup_pow_of_two(width) * 4;
9836
9837                 switch (stride) {
9838                 default:
9839                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9840                                   width, stride);
9841                         stride = 256;
9842                         /* fallthrough */
9843                 case 256:
9844                 case 512:
9845                 case 1024:
9846                 case 2048:
9847                         break;
9848                 }
9849
9850                 cntl |= CURSOR_ENABLE |
9851                         CURSOR_GAMMA_ENABLE |
9852                         CURSOR_FORMAT_ARGB |
9853                         CURSOR_STRIDE(stride);
9854
9855                 size = (height << 12) | width;
9856         }
9857
9858         if (intel_crtc->cursor_cntl != 0 &&
9859             (intel_crtc->cursor_base != base ||
9860              intel_crtc->cursor_size != size ||
9861              intel_crtc->cursor_cntl != cntl)) {
9862                 /* On these chipsets we can only modify the base/size/stride
9863                  * whilst the cursor is disabled.
9864                  */
9865                 I915_WRITE(_CURACNTR, 0);
9866                 POSTING_READ(_CURACNTR);
9867                 intel_crtc->cursor_cntl = 0;
9868         }
9869
9870         if (intel_crtc->cursor_base != base) {
9871                 I915_WRITE(_CURABASE, base);
9872                 intel_crtc->cursor_base = base;
9873         }
9874
9875         if (intel_crtc->cursor_size != size) {
9876                 I915_WRITE(CURSIZE, size);
9877                 intel_crtc->cursor_size = size;
9878         }
9879
9880         if (intel_crtc->cursor_cntl != cntl) {
9881                 I915_WRITE(_CURACNTR, cntl);
9882                 POSTING_READ(_CURACNTR);
9883                 intel_crtc->cursor_cntl = cntl;
9884         }
9885 }
9886
9887 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9888 {
9889         struct drm_device *dev = crtc->dev;
9890         struct drm_i915_private *dev_priv = dev->dev_private;
9891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9892         int pipe = intel_crtc->pipe;
9893         uint32_t cntl;
9894
9895         cntl = 0;
9896         if (base) {
9897                 cntl = MCURSOR_GAMMA_ENABLE;
9898                 switch (intel_crtc->base.cursor->state->crtc_w) {
9899                         case 64:
9900                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9901                                 break;
9902                         case 128:
9903                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9904                                 break;
9905                         case 256:
9906                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9907                                 break;
9908                         default:
9909                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9910                                 return;
9911                 }
9912                 cntl |= pipe << 28; /* Connect to correct pipe */
9913
9914                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9915                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9916         }
9917
9918         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9919                 cntl |= CURSOR_ROTATE_180;
9920
9921         if (intel_crtc->cursor_cntl != cntl) {
9922                 I915_WRITE(CURCNTR(pipe), cntl);
9923                 POSTING_READ(CURCNTR(pipe));
9924                 intel_crtc->cursor_cntl = cntl;
9925         }
9926
9927         /* and commit changes on next vblank */
9928         I915_WRITE(CURBASE(pipe), base);
9929         POSTING_READ(CURBASE(pipe));
9930
9931         intel_crtc->cursor_base = base;
9932 }
9933
9934 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9935 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9936                                      bool on)
9937 {
9938         struct drm_device *dev = crtc->dev;
9939         struct drm_i915_private *dev_priv = dev->dev_private;
9940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9941         int pipe = intel_crtc->pipe;
9942         int x = crtc->cursor_x;
9943         int y = crtc->cursor_y;
9944         u32 base = 0, pos = 0;
9945
9946         if (on)
9947                 base = intel_crtc->cursor_addr;
9948
9949         if (x >= intel_crtc->config->pipe_src_w)
9950                 base = 0;
9951
9952         if (y >= intel_crtc->config->pipe_src_h)
9953                 base = 0;
9954
9955         if (x < 0) {
9956                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9957                         base = 0;
9958
9959                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9960                 x = -x;
9961         }
9962         pos |= x << CURSOR_X_SHIFT;
9963
9964         if (y < 0) {
9965                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9966                         base = 0;
9967
9968                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9969                 y = -y;
9970         }
9971         pos |= y << CURSOR_Y_SHIFT;
9972
9973         if (base == 0 && intel_crtc->cursor_base == 0)
9974                 return;
9975
9976         I915_WRITE(CURPOS(pipe), pos);
9977
9978         /* ILK+ do this automagically */
9979         if (HAS_GMCH_DISPLAY(dev) &&
9980             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9981                 base += (intel_crtc->base.cursor->state->crtc_h *
9982                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9983         }
9984
9985         if (IS_845G(dev) || IS_I865G(dev))
9986                 i845_update_cursor(crtc, base);
9987         else
9988                 i9xx_update_cursor(crtc, base);
9989 }
9990
9991 static bool cursor_size_ok(struct drm_device *dev,
9992                            uint32_t width, uint32_t height)
9993 {
9994         if (width == 0 || height == 0)
9995                 return false;
9996
9997         /*
9998          * 845g/865g are special in that they are only limited by
9999          * the width of their cursors, the height is arbitrary up to
10000          * the precision of the register. Everything else requires
10001          * square cursors, limited to a few power-of-two sizes.
10002          */
10003         if (IS_845G(dev) || IS_I865G(dev)) {
10004                 if ((width & 63) != 0)
10005                         return false;
10006
10007                 if (width > (IS_845G(dev) ? 64 : 512))
10008                         return false;
10009
10010                 if (height > 1023)
10011                         return false;
10012         } else {
10013                 switch (width | height) {
10014                 case 256:
10015                 case 128:
10016                         if (IS_GEN2(dev))
10017                                 return false;
10018                 case 64:
10019                         break;
10020                 default:
10021                         return false;
10022                 }
10023         }
10024
10025         return true;
10026 }
10027
10028 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10029                                  u16 *blue, uint32_t start, uint32_t size)
10030 {
10031         int end = (start + size > 256) ? 256 : start + size, i;
10032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10033
10034         for (i = start; i < end; i++) {
10035                 intel_crtc->lut_r[i] = red[i] >> 8;
10036                 intel_crtc->lut_g[i] = green[i] >> 8;
10037                 intel_crtc->lut_b[i] = blue[i] >> 8;
10038         }
10039
10040         intel_crtc_load_lut(crtc);
10041 }
10042
10043 /* VESA 640x480x72Hz mode to set on the pipe */
10044 static struct drm_display_mode load_detect_mode = {
10045         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10046                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10047 };
10048
10049 struct drm_framebuffer *
10050 __intel_framebuffer_create(struct drm_device *dev,
10051                            struct drm_mode_fb_cmd2 *mode_cmd,
10052                            struct drm_i915_gem_object *obj)
10053 {
10054         struct intel_framebuffer *intel_fb;
10055         int ret;
10056
10057         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10058         if (!intel_fb) {
10059                 drm_gem_object_unreference(&obj->base);
10060                 return ERR_PTR(-ENOMEM);
10061         }
10062
10063         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10064         if (ret)
10065                 goto err;
10066
10067         return &intel_fb->base;
10068 err:
10069         drm_gem_object_unreference(&obj->base);
10070         kfree(intel_fb);
10071
10072         return ERR_PTR(ret);
10073 }
10074
10075 static struct drm_framebuffer *
10076 intel_framebuffer_create(struct drm_device *dev,
10077                          struct drm_mode_fb_cmd2 *mode_cmd,
10078                          struct drm_i915_gem_object *obj)
10079 {
10080         struct drm_framebuffer *fb;
10081         int ret;
10082
10083         ret = i915_mutex_lock_interruptible(dev);
10084         if (ret)
10085                 return ERR_PTR(ret);
10086         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10087         mutex_unlock(&dev->struct_mutex);
10088
10089         return fb;
10090 }
10091
10092 static u32
10093 intel_framebuffer_pitch_for_width(int width, int bpp)
10094 {
10095         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10096         return ALIGN(pitch, 64);
10097 }
10098
10099 static u32
10100 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10101 {
10102         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10103         return PAGE_ALIGN(pitch * mode->vdisplay);
10104 }
10105
10106 static struct drm_framebuffer *
10107 intel_framebuffer_create_for_mode(struct drm_device *dev,
10108                                   struct drm_display_mode *mode,
10109                                   int depth, int bpp)
10110 {
10111         struct drm_i915_gem_object *obj;
10112         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10113
10114         obj = i915_gem_alloc_object(dev,
10115                                     intel_framebuffer_size_for_mode(mode, bpp));
10116         if (obj == NULL)
10117                 return ERR_PTR(-ENOMEM);
10118
10119         mode_cmd.width = mode->hdisplay;
10120         mode_cmd.height = mode->vdisplay;
10121         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10122                                                                 bpp);
10123         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10124
10125         return intel_framebuffer_create(dev, &mode_cmd, obj);
10126 }
10127
10128 static struct drm_framebuffer *
10129 mode_fits_in_fbdev(struct drm_device *dev,
10130                    struct drm_display_mode *mode)
10131 {
10132 #ifdef CONFIG_DRM_I915_FBDEV
10133         struct drm_i915_private *dev_priv = dev->dev_private;
10134         struct drm_i915_gem_object *obj;
10135         struct drm_framebuffer *fb;
10136
10137         if (!dev_priv->fbdev)
10138                 return NULL;
10139
10140         if (!dev_priv->fbdev->fb)
10141                 return NULL;
10142
10143         obj = dev_priv->fbdev->fb->obj;
10144         BUG_ON(!obj);
10145
10146         fb = &dev_priv->fbdev->fb->base;
10147         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10148                                                                fb->bits_per_pixel))
10149                 return NULL;
10150
10151         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10152                 return NULL;
10153
10154         return fb;
10155 #else
10156         return NULL;
10157 #endif
10158 }
10159
10160 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10161                                            struct drm_crtc *crtc,
10162                                            struct drm_display_mode *mode,
10163                                            struct drm_framebuffer *fb,
10164                                            int x, int y)
10165 {
10166         struct drm_plane_state *plane_state;
10167         int hdisplay, vdisplay;
10168         int ret;
10169
10170         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10171         if (IS_ERR(plane_state))
10172                 return PTR_ERR(plane_state);
10173
10174         if (mode)
10175                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10176         else
10177                 hdisplay = vdisplay = 0;
10178
10179         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10180         if (ret)
10181                 return ret;
10182         drm_atomic_set_fb_for_plane(plane_state, fb);
10183         plane_state->crtc_x = 0;
10184         plane_state->crtc_y = 0;
10185         plane_state->crtc_w = hdisplay;
10186         plane_state->crtc_h = vdisplay;
10187         plane_state->src_x = x << 16;
10188         plane_state->src_y = y << 16;
10189         plane_state->src_w = hdisplay << 16;
10190         plane_state->src_h = vdisplay << 16;
10191
10192         return 0;
10193 }
10194
10195 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10196                                 struct drm_display_mode *mode,
10197                                 struct intel_load_detect_pipe *old,
10198                                 struct drm_modeset_acquire_ctx *ctx)
10199 {
10200         struct intel_crtc *intel_crtc;
10201         struct intel_encoder *intel_encoder =
10202                 intel_attached_encoder(connector);
10203         struct drm_crtc *possible_crtc;
10204         struct drm_encoder *encoder = &intel_encoder->base;
10205         struct drm_crtc *crtc = NULL;
10206         struct drm_device *dev = encoder->dev;
10207         struct drm_framebuffer *fb;
10208         struct drm_mode_config *config = &dev->mode_config;
10209         struct drm_atomic_state *state = NULL;
10210         struct drm_connector_state *connector_state;
10211         struct intel_crtc_state *crtc_state;
10212         int ret, i = -1;
10213
10214         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10215                       connector->base.id, connector->name,
10216                       encoder->base.id, encoder->name);
10217
10218 retry:
10219         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10220         if (ret)
10221                 goto fail;
10222
10223         /*
10224          * Algorithm gets a little messy:
10225          *
10226          *   - if the connector already has an assigned crtc, use it (but make
10227          *     sure it's on first)
10228          *
10229          *   - try to find the first unused crtc that can drive this connector,
10230          *     and use that if we find one
10231          */
10232
10233         /* See if we already have a CRTC for this connector */
10234         if (encoder->crtc) {
10235                 crtc = encoder->crtc;
10236
10237                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10238                 if (ret)
10239                         goto fail;
10240                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10241                 if (ret)
10242                         goto fail;
10243
10244                 old->dpms_mode = connector->dpms;
10245                 old->load_detect_temp = false;
10246
10247                 /* Make sure the crtc and connector are running */
10248                 if (connector->dpms != DRM_MODE_DPMS_ON)
10249                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10250
10251                 return true;
10252         }
10253
10254         /* Find an unused one (if possible) */
10255         for_each_crtc(dev, possible_crtc) {
10256                 i++;
10257                 if (!(encoder->possible_crtcs & (1 << i)))
10258                         continue;
10259                 if (possible_crtc->state->enable)
10260                         continue;
10261
10262                 crtc = possible_crtc;
10263                 break;
10264         }
10265
10266         /*
10267          * If we didn't find an unused CRTC, don't use any.
10268          */
10269         if (!crtc) {
10270                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10271                 goto fail;
10272         }
10273
10274         ret = drm_modeset_lock(&crtc->mutex, ctx);
10275         if (ret)
10276                 goto fail;
10277         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10278         if (ret)
10279                 goto fail;
10280
10281         intel_crtc = to_intel_crtc(crtc);
10282         old->dpms_mode = connector->dpms;
10283         old->load_detect_temp = true;
10284         old->release_fb = NULL;
10285
10286         state = drm_atomic_state_alloc(dev);
10287         if (!state)
10288                 return false;
10289
10290         state->acquire_ctx = ctx;
10291
10292         connector_state = drm_atomic_get_connector_state(state, connector);
10293         if (IS_ERR(connector_state)) {
10294                 ret = PTR_ERR(connector_state);
10295                 goto fail;
10296         }
10297
10298         connector_state->crtc = crtc;
10299         connector_state->best_encoder = &intel_encoder->base;
10300
10301         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10302         if (IS_ERR(crtc_state)) {
10303                 ret = PTR_ERR(crtc_state);
10304                 goto fail;
10305         }
10306
10307         crtc_state->base.active = crtc_state->base.enable = true;
10308
10309         if (!mode)
10310                 mode = &load_detect_mode;
10311
10312         /* We need a framebuffer large enough to accommodate all accesses
10313          * that the plane may generate whilst we perform load detection.
10314          * We can not rely on the fbcon either being present (we get called
10315          * during its initialisation to detect all boot displays, or it may
10316          * not even exist) or that it is large enough to satisfy the
10317          * requested mode.
10318          */
10319         fb = mode_fits_in_fbdev(dev, mode);
10320         if (fb == NULL) {
10321                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10322                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10323                 old->release_fb = fb;
10324         } else
10325                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10326         if (IS_ERR(fb)) {
10327                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10328                 goto fail;
10329         }
10330
10331         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10332         if (ret)
10333                 goto fail;
10334
10335         drm_mode_copy(&crtc_state->base.mode, mode);
10336
10337         if (drm_atomic_commit(state)) {
10338                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10339                 if (old->release_fb)
10340                         old->release_fb->funcs->destroy(old->release_fb);
10341                 goto fail;
10342         }
10343         crtc->primary->crtc = crtc;
10344
10345         /* let the connector get through one full cycle before testing */
10346         intel_wait_for_vblank(dev, intel_crtc->pipe);
10347         return true;
10348
10349 fail:
10350         drm_atomic_state_free(state);
10351         state = NULL;
10352
10353         if (ret == -EDEADLK) {
10354                 drm_modeset_backoff(ctx);
10355                 goto retry;
10356         }
10357
10358         return false;
10359 }
10360
10361 void intel_release_load_detect_pipe(struct drm_connector *connector,
10362                                     struct intel_load_detect_pipe *old,
10363                                     struct drm_modeset_acquire_ctx *ctx)
10364 {
10365         struct drm_device *dev = connector->dev;
10366         struct intel_encoder *intel_encoder =
10367                 intel_attached_encoder(connector);
10368         struct drm_encoder *encoder = &intel_encoder->base;
10369         struct drm_crtc *crtc = encoder->crtc;
10370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10371         struct drm_atomic_state *state;
10372         struct drm_connector_state *connector_state;
10373         struct intel_crtc_state *crtc_state;
10374         int ret;
10375
10376         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10377                       connector->base.id, connector->name,
10378                       encoder->base.id, encoder->name);
10379
10380         if (old->load_detect_temp) {
10381                 state = drm_atomic_state_alloc(dev);
10382                 if (!state)
10383                         goto fail;
10384
10385                 state->acquire_ctx = ctx;
10386
10387                 connector_state = drm_atomic_get_connector_state(state, connector);
10388                 if (IS_ERR(connector_state))
10389                         goto fail;
10390
10391                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392                 if (IS_ERR(crtc_state))
10393                         goto fail;
10394
10395                 connector_state->best_encoder = NULL;
10396                 connector_state->crtc = NULL;
10397
10398                 crtc_state->base.enable = crtc_state->base.active = false;
10399
10400                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10401                                                       0, 0);
10402                 if (ret)
10403                         goto fail;
10404
10405                 ret = drm_atomic_commit(state);
10406                 if (ret)
10407                         goto fail;
10408
10409                 if (old->release_fb) {
10410                         drm_framebuffer_unregister_private(old->release_fb);
10411                         drm_framebuffer_unreference(old->release_fb);
10412                 }
10413
10414                 return;
10415         }
10416
10417         /* Switch crtc and encoder back off if necessary */
10418         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10419                 connector->funcs->dpms(connector, old->dpms_mode);
10420
10421         return;
10422 fail:
10423         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10424         drm_atomic_state_free(state);
10425 }
10426
10427 static int i9xx_pll_refclk(struct drm_device *dev,
10428                            const struct intel_crtc_state *pipe_config)
10429 {
10430         struct drm_i915_private *dev_priv = dev->dev_private;
10431         u32 dpll = pipe_config->dpll_hw_state.dpll;
10432
10433         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10434                 return dev_priv->vbt.lvds_ssc_freq;
10435         else if (HAS_PCH_SPLIT(dev))
10436                 return 120000;
10437         else if (!IS_GEN2(dev))
10438                 return 96000;
10439         else
10440                 return 48000;
10441 }
10442
10443 /* Returns the clock of the currently programmed mode of the given pipe. */
10444 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10445                                 struct intel_crtc_state *pipe_config)
10446 {
10447         struct drm_device *dev = crtc->base.dev;
10448         struct drm_i915_private *dev_priv = dev->dev_private;
10449         int pipe = pipe_config->cpu_transcoder;
10450         u32 dpll = pipe_config->dpll_hw_state.dpll;
10451         u32 fp;
10452         intel_clock_t clock;
10453         int port_clock;
10454         int refclk = i9xx_pll_refclk(dev, pipe_config);
10455
10456         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10457                 fp = pipe_config->dpll_hw_state.fp0;
10458         else
10459                 fp = pipe_config->dpll_hw_state.fp1;
10460
10461         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10462         if (IS_PINEVIEW(dev)) {
10463                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10464                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10465         } else {
10466                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10467                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10468         }
10469
10470         if (!IS_GEN2(dev)) {
10471                 if (IS_PINEVIEW(dev))
10472                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10473                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10474                 else
10475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10476                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10477
10478                 switch (dpll & DPLL_MODE_MASK) {
10479                 case DPLLB_MODE_DAC_SERIAL:
10480                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10481                                 5 : 10;
10482                         break;
10483                 case DPLLB_MODE_LVDS:
10484                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10485                                 7 : 14;
10486                         break;
10487                 default:
10488                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10489                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10490                         return;
10491                 }
10492
10493                 if (IS_PINEVIEW(dev))
10494                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10495                 else
10496                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10497         } else {
10498                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10499                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10500
10501                 if (is_lvds) {
10502                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10503                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10504
10505                         if (lvds & LVDS_CLKB_POWER_UP)
10506                                 clock.p2 = 7;
10507                         else
10508                                 clock.p2 = 14;
10509                 } else {
10510                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10511                                 clock.p1 = 2;
10512                         else {
10513                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10514                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10515                         }
10516                         if (dpll & PLL_P2_DIVIDE_BY_4)
10517                                 clock.p2 = 4;
10518                         else
10519                                 clock.p2 = 2;
10520                 }
10521
10522                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10523         }
10524
10525         /*
10526          * This value includes pixel_multiplier. We will use
10527          * port_clock to compute adjusted_mode.crtc_clock in the
10528          * encoder's get_config() function.
10529          */
10530         pipe_config->port_clock = port_clock;
10531 }
10532
10533 int intel_dotclock_calculate(int link_freq,
10534                              const struct intel_link_m_n *m_n)
10535 {
10536         /*
10537          * The calculation for the data clock is:
10538          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10539          * But we want to avoid losing precison if possible, so:
10540          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10541          *
10542          * and the link clock is simpler:
10543          * link_clock = (m * link_clock) / n
10544          */
10545
10546         if (!m_n->link_n)
10547                 return 0;
10548
10549         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10550 }
10551
10552 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10553                                    struct intel_crtc_state *pipe_config)
10554 {
10555         struct drm_device *dev = crtc->base.dev;
10556
10557         /* read out port_clock from the DPLL */
10558         i9xx_crtc_clock_get(crtc, pipe_config);
10559
10560         /*
10561          * This value does not include pixel_multiplier.
10562          * We will check that port_clock and adjusted_mode.crtc_clock
10563          * agree once we know their relationship in the encoder's
10564          * get_config() function.
10565          */
10566         pipe_config->base.adjusted_mode.crtc_clock =
10567                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10568                                          &pipe_config->fdi_m_n);
10569 }
10570
10571 /** Returns the currently programmed mode of the given pipe. */
10572 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10573                                              struct drm_crtc *crtc)
10574 {
10575         struct drm_i915_private *dev_priv = dev->dev_private;
10576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10577         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10578         struct drm_display_mode *mode;
10579         struct intel_crtc_state pipe_config;
10580         int htot = I915_READ(HTOTAL(cpu_transcoder));
10581         int hsync = I915_READ(HSYNC(cpu_transcoder));
10582         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10583         int vsync = I915_READ(VSYNC(cpu_transcoder));
10584         enum pipe pipe = intel_crtc->pipe;
10585
10586         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10587         if (!mode)
10588                 return NULL;
10589
10590         /*
10591          * Construct a pipe_config sufficient for getting the clock info
10592          * back out of crtc_clock_get.
10593          *
10594          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10595          * to use a real value here instead.
10596          */
10597         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10598         pipe_config.pixel_multiplier = 1;
10599         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10600         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10601         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10602         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10603
10604         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10605         mode->hdisplay = (htot & 0xffff) + 1;
10606         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10607         mode->hsync_start = (hsync & 0xffff) + 1;
10608         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10609         mode->vdisplay = (vtot & 0xffff) + 1;
10610         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10611         mode->vsync_start = (vsync & 0xffff) + 1;
10612         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10613
10614         drm_mode_set_name(mode);
10615
10616         return mode;
10617 }
10618
10619 void intel_mark_busy(struct drm_device *dev)
10620 {
10621         struct drm_i915_private *dev_priv = dev->dev_private;
10622
10623         if (dev_priv->mm.busy)
10624                 return;
10625
10626         intel_runtime_pm_get(dev_priv);
10627         i915_update_gfx_val(dev_priv);
10628         if (INTEL_INFO(dev)->gen >= 6)
10629                 gen6_rps_busy(dev_priv);
10630         dev_priv->mm.busy = true;
10631 }
10632
10633 void intel_mark_idle(struct drm_device *dev)
10634 {
10635         struct drm_i915_private *dev_priv = dev->dev_private;
10636
10637         if (!dev_priv->mm.busy)
10638                 return;
10639
10640         dev_priv->mm.busy = false;
10641
10642         if (INTEL_INFO(dev)->gen >= 6)
10643                 gen6_rps_idle(dev->dev_private);
10644
10645         intel_runtime_pm_put(dev_priv);
10646 }
10647
10648 static void intel_crtc_destroy(struct drm_crtc *crtc)
10649 {
10650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10651         struct drm_device *dev = crtc->dev;
10652         struct intel_unpin_work *work;
10653
10654         spin_lock_irq(&dev->event_lock);
10655         work = intel_crtc->unpin_work;
10656         intel_crtc->unpin_work = NULL;
10657         spin_unlock_irq(&dev->event_lock);
10658
10659         if (work) {
10660                 cancel_work_sync(&work->work);
10661                 kfree(work);
10662         }
10663
10664         drm_crtc_cleanup(crtc);
10665
10666         kfree(intel_crtc);
10667 }
10668
10669 static void intel_unpin_work_fn(struct work_struct *__work)
10670 {
10671         struct intel_unpin_work *work =
10672                 container_of(__work, struct intel_unpin_work, work);
10673         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10674         struct drm_device *dev = crtc->base.dev;
10675         struct drm_plane *primary = crtc->base.primary;
10676
10677         mutex_lock(&dev->struct_mutex);
10678         intel_unpin_fb_obj(work->old_fb, primary->state);
10679         drm_gem_object_unreference(&work->pending_flip_obj->base);
10680
10681         if (work->flip_queued_req)
10682                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10683         mutex_unlock(&dev->struct_mutex);
10684
10685         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10686         drm_framebuffer_unreference(work->old_fb);
10687
10688         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10689         atomic_dec(&crtc->unpin_work_count);
10690
10691         kfree(work);
10692 }
10693
10694 static void do_intel_finish_page_flip(struct drm_device *dev,
10695                                       struct drm_crtc *crtc)
10696 {
10697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10698         struct intel_unpin_work *work;
10699         unsigned long flags;
10700
10701         /* Ignore early vblank irqs */
10702         if (intel_crtc == NULL)
10703                 return;
10704
10705         /*
10706          * This is called both by irq handlers and the reset code (to complete
10707          * lost pageflips) so needs the full irqsave spinlocks.
10708          */
10709         spin_lock_irqsave(&dev->event_lock, flags);
10710         work = intel_crtc->unpin_work;
10711
10712         /* Ensure we don't miss a work->pending update ... */
10713         smp_rmb();
10714
10715         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10716                 spin_unlock_irqrestore(&dev->event_lock, flags);
10717                 return;
10718         }
10719
10720         page_flip_completed(intel_crtc);
10721
10722         spin_unlock_irqrestore(&dev->event_lock, flags);
10723 }
10724
10725 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10726 {
10727         struct drm_i915_private *dev_priv = dev->dev_private;
10728         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10729
10730         do_intel_finish_page_flip(dev, crtc);
10731 }
10732
10733 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10734 {
10735         struct drm_i915_private *dev_priv = dev->dev_private;
10736         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10737
10738         do_intel_finish_page_flip(dev, crtc);
10739 }
10740
10741 /* Is 'a' after or equal to 'b'? */
10742 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10743 {
10744         return !((a - b) & 0x80000000);
10745 }
10746
10747 static bool page_flip_finished(struct intel_crtc *crtc)
10748 {
10749         struct drm_device *dev = crtc->base.dev;
10750         struct drm_i915_private *dev_priv = dev->dev_private;
10751
10752         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10753             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10754                 return true;
10755
10756         /*
10757          * The relevant registers doen't exist on pre-ctg.
10758          * As the flip done interrupt doesn't trigger for mmio
10759          * flips on gmch platforms, a flip count check isn't
10760          * really needed there. But since ctg has the registers,
10761          * include it in the check anyway.
10762          */
10763         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10764                 return true;
10765
10766         /*
10767          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10768          * used the same base address. In that case the mmio flip might
10769          * have completed, but the CS hasn't even executed the flip yet.
10770          *
10771          * A flip count check isn't enough as the CS might have updated
10772          * the base address just after start of vblank, but before we
10773          * managed to process the interrupt. This means we'd complete the
10774          * CS flip too soon.
10775          *
10776          * Combining both checks should get us a good enough result. It may
10777          * still happen that the CS flip has been executed, but has not
10778          * yet actually completed. But in case the base address is the same
10779          * anyway, we don't really care.
10780          */
10781         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10782                 crtc->unpin_work->gtt_offset &&
10783                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10784                                     crtc->unpin_work->flip_count);
10785 }
10786
10787 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10788 {
10789         struct drm_i915_private *dev_priv = dev->dev_private;
10790         struct intel_crtc *intel_crtc =
10791                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10792         unsigned long flags;
10793
10794
10795         /*
10796          * This is called both by irq handlers and the reset code (to complete
10797          * lost pageflips) so needs the full irqsave spinlocks.
10798          *
10799          * NB: An MMIO update of the plane base pointer will also
10800          * generate a page-flip completion irq, i.e. every modeset
10801          * is also accompanied by a spurious intel_prepare_page_flip().
10802          */
10803         spin_lock_irqsave(&dev->event_lock, flags);
10804         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10805                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10806         spin_unlock_irqrestore(&dev->event_lock, flags);
10807 }
10808
10809 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10810 {
10811         /* Ensure that the work item is consistent when activating it ... */
10812         smp_wmb();
10813         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10814         /* and that it is marked active as soon as the irq could fire. */
10815         smp_wmb();
10816 }
10817
10818 static int intel_gen2_queue_flip(struct drm_device *dev,
10819                                  struct drm_crtc *crtc,
10820                                  struct drm_framebuffer *fb,
10821                                  struct drm_i915_gem_object *obj,
10822                                  struct drm_i915_gem_request *req,
10823                                  uint32_t flags)
10824 {
10825         struct intel_engine_cs *ring = req->ring;
10826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10827         u32 flip_mask;
10828         int ret;
10829
10830         ret = intel_ring_begin(req, 6);
10831         if (ret)
10832                 return ret;
10833
10834         /* Can't queue multiple flips, so wait for the previous
10835          * one to finish before executing the next.
10836          */
10837         if (intel_crtc->plane)
10838                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10839         else
10840                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10841         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10842         intel_ring_emit(ring, MI_NOOP);
10843         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10844                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10845         intel_ring_emit(ring, fb->pitches[0]);
10846         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10847         intel_ring_emit(ring, 0); /* aux display base address, unused */
10848
10849         intel_mark_page_flip_active(intel_crtc);
10850         return 0;
10851 }
10852
10853 static int intel_gen3_queue_flip(struct drm_device *dev,
10854                                  struct drm_crtc *crtc,
10855                                  struct drm_framebuffer *fb,
10856                                  struct drm_i915_gem_object *obj,
10857                                  struct drm_i915_gem_request *req,
10858                                  uint32_t flags)
10859 {
10860         struct intel_engine_cs *ring = req->ring;
10861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10862         u32 flip_mask;
10863         int ret;
10864
10865         ret = intel_ring_begin(req, 6);
10866         if (ret)
10867                 return ret;
10868
10869         if (intel_crtc->plane)
10870                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10871         else
10872                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10873         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10874         intel_ring_emit(ring, MI_NOOP);
10875         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10876                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10877         intel_ring_emit(ring, fb->pitches[0]);
10878         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10879         intel_ring_emit(ring, MI_NOOP);
10880
10881         intel_mark_page_flip_active(intel_crtc);
10882         return 0;
10883 }
10884
10885 static int intel_gen4_queue_flip(struct drm_device *dev,
10886                                  struct drm_crtc *crtc,
10887                                  struct drm_framebuffer *fb,
10888                                  struct drm_i915_gem_object *obj,
10889                                  struct drm_i915_gem_request *req,
10890                                  uint32_t flags)
10891 {
10892         struct intel_engine_cs *ring = req->ring;
10893         struct drm_i915_private *dev_priv = dev->dev_private;
10894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10895         uint32_t pf, pipesrc;
10896         int ret;
10897
10898         ret = intel_ring_begin(req, 4);
10899         if (ret)
10900                 return ret;
10901
10902         /* i965+ uses the linear or tiled offsets from the
10903          * Display Registers (which do not change across a page-flip)
10904          * so we need only reprogram the base address.
10905          */
10906         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10907                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10908         intel_ring_emit(ring, fb->pitches[0]);
10909         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10910                         obj->tiling_mode);
10911
10912         /* XXX Enabling the panel-fitter across page-flip is so far
10913          * untested on non-native modes, so ignore it for now.
10914          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10915          */
10916         pf = 0;
10917         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10918         intel_ring_emit(ring, pf | pipesrc);
10919
10920         intel_mark_page_flip_active(intel_crtc);
10921         return 0;
10922 }
10923
10924 static int intel_gen6_queue_flip(struct drm_device *dev,
10925                                  struct drm_crtc *crtc,
10926                                  struct drm_framebuffer *fb,
10927                                  struct drm_i915_gem_object *obj,
10928                                  struct drm_i915_gem_request *req,
10929                                  uint32_t flags)
10930 {
10931         struct intel_engine_cs *ring = req->ring;
10932         struct drm_i915_private *dev_priv = dev->dev_private;
10933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10934         uint32_t pf, pipesrc;
10935         int ret;
10936
10937         ret = intel_ring_begin(req, 4);
10938         if (ret)
10939                 return ret;
10940
10941         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10942                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10943         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10944         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10945
10946         /* Contrary to the suggestions in the documentation,
10947          * "Enable Panel Fitter" does not seem to be required when page
10948          * flipping with a non-native mode, and worse causes a normal
10949          * modeset to fail.
10950          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10951          */
10952         pf = 0;
10953         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10954         intel_ring_emit(ring, pf | pipesrc);
10955
10956         intel_mark_page_flip_active(intel_crtc);
10957         return 0;
10958 }
10959
10960 static int intel_gen7_queue_flip(struct drm_device *dev,
10961                                  struct drm_crtc *crtc,
10962                                  struct drm_framebuffer *fb,
10963                                  struct drm_i915_gem_object *obj,
10964                                  struct drm_i915_gem_request *req,
10965                                  uint32_t flags)
10966 {
10967         struct intel_engine_cs *ring = req->ring;
10968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10969         uint32_t plane_bit = 0;
10970         int len, ret;
10971
10972         switch (intel_crtc->plane) {
10973         case PLANE_A:
10974                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10975                 break;
10976         case PLANE_B:
10977                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10978                 break;
10979         case PLANE_C:
10980                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10981                 break;
10982         default:
10983                 WARN_ONCE(1, "unknown plane in flip command\n");
10984                 return -ENODEV;
10985         }
10986
10987         len = 4;
10988         if (ring->id == RCS) {
10989                 len += 6;
10990                 /*
10991                  * On Gen 8, SRM is now taking an extra dword to accommodate
10992                  * 48bits addresses, and we need a NOOP for the batch size to
10993                  * stay even.
10994                  */
10995                 if (IS_GEN8(dev))
10996                         len += 2;
10997         }
10998
10999         /*
11000          * BSpec MI_DISPLAY_FLIP for IVB:
11001          * "The full packet must be contained within the same cache line."
11002          *
11003          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11004          * cacheline, if we ever start emitting more commands before
11005          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11006          * then do the cacheline alignment, and finally emit the
11007          * MI_DISPLAY_FLIP.
11008          */
11009         ret = intel_ring_cacheline_align(req);
11010         if (ret)
11011                 return ret;
11012
11013         ret = intel_ring_begin(req, len);
11014         if (ret)
11015                 return ret;
11016
11017         /* Unmask the flip-done completion message. Note that the bspec says that
11018          * we should do this for both the BCS and RCS, and that we must not unmask
11019          * more than one flip event at any time (or ensure that one flip message
11020          * can be sent by waiting for flip-done prior to queueing new flips).
11021          * Experimentation says that BCS works despite DERRMR masking all
11022          * flip-done completion events and that unmasking all planes at once
11023          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11024          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11025          */
11026         if (ring->id == RCS) {
11027                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11028                 intel_ring_emit(ring, DERRMR);
11029                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11030                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11031                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11032                 if (IS_GEN8(dev))
11033                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11034                                               MI_SRM_LRM_GLOBAL_GTT);
11035                 else
11036                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11037                                               MI_SRM_LRM_GLOBAL_GTT);
11038                 intel_ring_emit(ring, DERRMR);
11039                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11040                 if (IS_GEN8(dev)) {
11041                         intel_ring_emit(ring, 0);
11042                         intel_ring_emit(ring, MI_NOOP);
11043                 }
11044         }
11045
11046         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11047         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11048         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11049         intel_ring_emit(ring, (MI_NOOP));
11050
11051         intel_mark_page_flip_active(intel_crtc);
11052         return 0;
11053 }
11054
11055 static bool use_mmio_flip(struct intel_engine_cs *ring,
11056                           struct drm_i915_gem_object *obj)
11057 {
11058         /*
11059          * This is not being used for older platforms, because
11060          * non-availability of flip done interrupt forces us to use
11061          * CS flips. Older platforms derive flip done using some clever
11062          * tricks involving the flip_pending status bits and vblank irqs.
11063          * So using MMIO flips there would disrupt this mechanism.
11064          */
11065
11066         if (ring == NULL)
11067                 return true;
11068
11069         if (INTEL_INFO(ring->dev)->gen < 5)
11070                 return false;
11071
11072         if (i915.use_mmio_flip < 0)
11073                 return false;
11074         else if (i915.use_mmio_flip > 0)
11075                 return true;
11076         else if (i915.enable_execlists)
11077                 return true;
11078         else
11079                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11080 }
11081
11082 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11083 {
11084         struct drm_device *dev = intel_crtc->base.dev;
11085         struct drm_i915_private *dev_priv = dev->dev_private;
11086         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11087         const enum pipe pipe = intel_crtc->pipe;
11088         u32 ctl, stride;
11089
11090         ctl = I915_READ(PLANE_CTL(pipe, 0));
11091         ctl &= ~PLANE_CTL_TILED_MASK;
11092         switch (fb->modifier[0]) {
11093         case DRM_FORMAT_MOD_NONE:
11094                 break;
11095         case I915_FORMAT_MOD_X_TILED:
11096                 ctl |= PLANE_CTL_TILED_X;
11097                 break;
11098         case I915_FORMAT_MOD_Y_TILED:
11099                 ctl |= PLANE_CTL_TILED_Y;
11100                 break;
11101         case I915_FORMAT_MOD_Yf_TILED:
11102                 ctl |= PLANE_CTL_TILED_YF;
11103                 break;
11104         default:
11105                 MISSING_CASE(fb->modifier[0]);
11106         }
11107
11108         /*
11109          * The stride is either expressed as a multiple of 64 bytes chunks for
11110          * linear buffers or in number of tiles for tiled buffers.
11111          */
11112         stride = fb->pitches[0] /
11113                  intel_fb_stride_alignment(dev, fb->modifier[0],
11114                                            fb->pixel_format);
11115
11116         /*
11117          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11118          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11119          */
11120         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11121         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11122
11123         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11124         POSTING_READ(PLANE_SURF(pipe, 0));
11125 }
11126
11127 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11128 {
11129         struct drm_device *dev = intel_crtc->base.dev;
11130         struct drm_i915_private *dev_priv = dev->dev_private;
11131         struct intel_framebuffer *intel_fb =
11132                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11133         struct drm_i915_gem_object *obj = intel_fb->obj;
11134         u32 dspcntr;
11135         u32 reg;
11136
11137         reg = DSPCNTR(intel_crtc->plane);
11138         dspcntr = I915_READ(reg);
11139
11140         if (obj->tiling_mode != I915_TILING_NONE)
11141                 dspcntr |= DISPPLANE_TILED;
11142         else
11143                 dspcntr &= ~DISPPLANE_TILED;
11144
11145         I915_WRITE(reg, dspcntr);
11146
11147         I915_WRITE(DSPSURF(intel_crtc->plane),
11148                    intel_crtc->unpin_work->gtt_offset);
11149         POSTING_READ(DSPSURF(intel_crtc->plane));
11150
11151 }
11152
11153 /*
11154  * XXX: This is the temporary way to update the plane registers until we get
11155  * around to using the usual plane update functions for MMIO flips
11156  */
11157 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11158 {
11159         struct drm_device *dev = intel_crtc->base.dev;
11160         u32 start_vbl_count;
11161
11162         intel_mark_page_flip_active(intel_crtc);
11163
11164         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11165
11166         if (INTEL_INFO(dev)->gen >= 9)
11167                 skl_do_mmio_flip(intel_crtc);
11168         else
11169                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11170                 ilk_do_mmio_flip(intel_crtc);
11171
11172         intel_pipe_update_end(intel_crtc, start_vbl_count);
11173 }
11174
11175 static void intel_mmio_flip_work_func(struct work_struct *work)
11176 {
11177         struct intel_mmio_flip *mmio_flip =
11178                 container_of(work, struct intel_mmio_flip, work);
11179
11180         if (mmio_flip->req)
11181                 WARN_ON(__i915_wait_request(mmio_flip->req,
11182                                             mmio_flip->crtc->reset_counter,
11183                                             false, NULL,
11184                                             &mmio_flip->i915->rps.mmioflips));
11185
11186         intel_do_mmio_flip(mmio_flip->crtc);
11187
11188         i915_gem_request_unreference__unlocked(mmio_flip->req);
11189         kfree(mmio_flip);
11190 }
11191
11192 static int intel_queue_mmio_flip(struct drm_device *dev,
11193                                  struct drm_crtc *crtc,
11194                                  struct drm_framebuffer *fb,
11195                                  struct drm_i915_gem_object *obj,
11196                                  struct intel_engine_cs *ring,
11197                                  uint32_t flags)
11198 {
11199         struct intel_mmio_flip *mmio_flip;
11200
11201         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11202         if (mmio_flip == NULL)
11203                 return -ENOMEM;
11204
11205         mmio_flip->i915 = to_i915(dev);
11206         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11207         mmio_flip->crtc = to_intel_crtc(crtc);
11208
11209         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11210         schedule_work(&mmio_flip->work);
11211
11212         return 0;
11213 }
11214
11215 static int intel_default_queue_flip(struct drm_device *dev,
11216                                     struct drm_crtc *crtc,
11217                                     struct drm_framebuffer *fb,
11218                                     struct drm_i915_gem_object *obj,
11219                                     struct drm_i915_gem_request *req,
11220                                     uint32_t flags)
11221 {
11222         return -ENODEV;
11223 }
11224
11225 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11226                                          struct drm_crtc *crtc)
11227 {
11228         struct drm_i915_private *dev_priv = dev->dev_private;
11229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11230         struct intel_unpin_work *work = intel_crtc->unpin_work;
11231         u32 addr;
11232
11233         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11234                 return true;
11235
11236         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11237                 return false;
11238
11239         if (!work->enable_stall_check)
11240                 return false;
11241
11242         if (work->flip_ready_vblank == 0) {
11243                 if (work->flip_queued_req &&
11244                     !i915_gem_request_completed(work->flip_queued_req, true))
11245                         return false;
11246
11247                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11248         }
11249
11250         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11251                 return false;
11252
11253         /* Potential stall - if we see that the flip has happened,
11254          * assume a missed interrupt. */
11255         if (INTEL_INFO(dev)->gen >= 4)
11256                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11257         else
11258                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11259
11260         /* There is a potential issue here with a false positive after a flip
11261          * to the same address. We could address this by checking for a
11262          * non-incrementing frame counter.
11263          */
11264         return addr == work->gtt_offset;
11265 }
11266
11267 void intel_check_page_flip(struct drm_device *dev, int pipe)
11268 {
11269         struct drm_i915_private *dev_priv = dev->dev_private;
11270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11272         struct intel_unpin_work *work;
11273
11274         WARN_ON(!in_interrupt());
11275
11276         if (crtc == NULL)
11277                 return;
11278
11279         spin_lock(&dev->event_lock);
11280         work = intel_crtc->unpin_work;
11281         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11282                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11283                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11284                 page_flip_completed(intel_crtc);
11285                 work = NULL;
11286         }
11287         if (work != NULL &&
11288             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11289                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11290         spin_unlock(&dev->event_lock);
11291 }
11292
11293 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11294                                 struct drm_framebuffer *fb,
11295                                 struct drm_pending_vblank_event *event,
11296                                 uint32_t page_flip_flags)
11297 {
11298         struct drm_device *dev = crtc->dev;
11299         struct drm_i915_private *dev_priv = dev->dev_private;
11300         struct drm_framebuffer *old_fb = crtc->primary->fb;
11301         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11303         struct drm_plane *primary = crtc->primary;
11304         enum pipe pipe = intel_crtc->pipe;
11305         struct intel_unpin_work *work;
11306         struct intel_engine_cs *ring;
11307         bool mmio_flip;
11308         struct drm_i915_gem_request *request = NULL;
11309         int ret;
11310
11311         /*
11312          * drm_mode_page_flip_ioctl() should already catch this, but double
11313          * check to be safe.  In the future we may enable pageflipping from
11314          * a disabled primary plane.
11315          */
11316         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11317                 return -EBUSY;
11318
11319         /* Can't change pixel format via MI display flips. */
11320         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11321                 return -EINVAL;
11322
11323         /*
11324          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11325          * Note that pitch changes could also affect these register.
11326          */
11327         if (INTEL_INFO(dev)->gen > 3 &&
11328             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11329              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11330                 return -EINVAL;
11331
11332         if (i915_terminally_wedged(&dev_priv->gpu_error))
11333                 goto out_hang;
11334
11335         work = kzalloc(sizeof(*work), GFP_KERNEL);
11336         if (work == NULL)
11337                 return -ENOMEM;
11338
11339         work->event = event;
11340         work->crtc = crtc;
11341         work->old_fb = old_fb;
11342         INIT_WORK(&work->work, intel_unpin_work_fn);
11343
11344         ret = drm_crtc_vblank_get(crtc);
11345         if (ret)
11346                 goto free_work;
11347
11348         /* We borrow the event spin lock for protecting unpin_work */
11349         spin_lock_irq(&dev->event_lock);
11350         if (intel_crtc->unpin_work) {
11351                 /* Before declaring the flip queue wedged, check if
11352                  * the hardware completed the operation behind our backs.
11353                  */
11354                 if (__intel_pageflip_stall_check(dev, crtc)) {
11355                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11356                         page_flip_completed(intel_crtc);
11357                 } else {
11358                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11359                         spin_unlock_irq(&dev->event_lock);
11360
11361                         drm_crtc_vblank_put(crtc);
11362                         kfree(work);
11363                         return -EBUSY;
11364                 }
11365         }
11366         intel_crtc->unpin_work = work;
11367         spin_unlock_irq(&dev->event_lock);
11368
11369         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11370                 flush_workqueue(dev_priv->wq);
11371
11372         /* Reference the objects for the scheduled work. */
11373         drm_framebuffer_reference(work->old_fb);
11374         drm_gem_object_reference(&obj->base);
11375
11376         crtc->primary->fb = fb;
11377         update_state_fb(crtc->primary);
11378
11379         work->pending_flip_obj = obj;
11380
11381         ret = i915_mutex_lock_interruptible(dev);
11382         if (ret)
11383                 goto cleanup;
11384
11385         atomic_inc(&intel_crtc->unpin_work_count);
11386         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11387
11388         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11389                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11390
11391         if (IS_VALLEYVIEW(dev)) {
11392                 ring = &dev_priv->ring[BCS];
11393                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11394                         /* vlv: DISPLAY_FLIP fails to change tiling */
11395                         ring = NULL;
11396         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11397                 ring = &dev_priv->ring[BCS];
11398         } else if (INTEL_INFO(dev)->gen >= 7) {
11399                 ring = i915_gem_request_get_ring(obj->last_write_req);
11400                 if (ring == NULL || ring->id != RCS)
11401                         ring = &dev_priv->ring[BCS];
11402         } else {
11403                 ring = &dev_priv->ring[RCS];
11404         }
11405
11406         mmio_flip = use_mmio_flip(ring, obj);
11407
11408         /* When using CS flips, we want to emit semaphores between rings.
11409          * However, when using mmio flips we will create a task to do the
11410          * synchronisation, so all we want here is to pin the framebuffer
11411          * into the display plane and skip any waits.
11412          */
11413         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11414                                          crtc->primary->state,
11415                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11416         if (ret)
11417                 goto cleanup_pending;
11418
11419         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11420                                                   + intel_crtc->dspaddr_offset;
11421
11422         if (mmio_flip) {
11423                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11424                                             page_flip_flags);
11425                 if (ret)
11426                         goto cleanup_unpin;
11427
11428                 i915_gem_request_assign(&work->flip_queued_req,
11429                                         obj->last_write_req);
11430         } else {
11431                 if (!request) {
11432                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11433                         if (ret)
11434                                 goto cleanup_unpin;
11435                 }
11436
11437                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11438                                                    page_flip_flags);
11439                 if (ret)
11440                         goto cleanup_unpin;
11441
11442                 i915_gem_request_assign(&work->flip_queued_req, request);
11443         }
11444
11445         if (request)
11446                 i915_add_request_no_flush(request);
11447
11448         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11449         work->enable_stall_check = true;
11450
11451         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11452                           to_intel_plane(primary)->frontbuffer_bit);
11453         mutex_unlock(&dev->struct_mutex);
11454
11455         intel_fbc_disable_crtc(intel_crtc);
11456         intel_frontbuffer_flip_prepare(dev,
11457                                        to_intel_plane(primary)->frontbuffer_bit);
11458
11459         trace_i915_flip_request(intel_crtc->plane, obj);
11460
11461         return 0;
11462
11463 cleanup_unpin:
11464         intel_unpin_fb_obj(fb, crtc->primary->state);
11465 cleanup_pending:
11466         if (request)
11467                 i915_gem_request_cancel(request);
11468         atomic_dec(&intel_crtc->unpin_work_count);
11469         mutex_unlock(&dev->struct_mutex);
11470 cleanup:
11471         crtc->primary->fb = old_fb;
11472         update_state_fb(crtc->primary);
11473
11474         drm_gem_object_unreference_unlocked(&obj->base);
11475         drm_framebuffer_unreference(work->old_fb);
11476
11477         spin_lock_irq(&dev->event_lock);
11478         intel_crtc->unpin_work = NULL;
11479         spin_unlock_irq(&dev->event_lock);
11480
11481         drm_crtc_vblank_put(crtc);
11482 free_work:
11483         kfree(work);
11484
11485         if (ret == -EIO) {
11486                 struct drm_atomic_state *state;
11487                 struct drm_plane_state *plane_state;
11488
11489 out_hang:
11490                 state = drm_atomic_state_alloc(dev);
11491                 if (!state)
11492                         return -ENOMEM;
11493                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11494
11495 retry:
11496                 plane_state = drm_atomic_get_plane_state(state, primary);
11497                 ret = PTR_ERR_OR_ZERO(plane_state);
11498                 if (!ret) {
11499                         drm_atomic_set_fb_for_plane(plane_state, fb);
11500
11501                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11502                         if (!ret)
11503                                 ret = drm_atomic_commit(state);
11504                 }
11505
11506                 if (ret == -EDEADLK) {
11507                         drm_modeset_backoff(state->acquire_ctx);
11508                         drm_atomic_state_clear(state);
11509                         goto retry;
11510                 }
11511
11512                 if (ret)
11513                         drm_atomic_state_free(state);
11514
11515                 if (ret == 0 && event) {
11516                         spin_lock_irq(&dev->event_lock);
11517                         drm_send_vblank_event(dev, pipe, event);
11518                         spin_unlock_irq(&dev->event_lock);
11519                 }
11520         }
11521         return ret;
11522 }
11523
11524
11525 /**
11526  * intel_wm_need_update - Check whether watermarks need updating
11527  * @plane: drm plane
11528  * @state: new plane state
11529  *
11530  * Check current plane state versus the new one to determine whether
11531  * watermarks need to be recalculated.
11532  *
11533  * Returns true or false.
11534  */
11535 static bool intel_wm_need_update(struct drm_plane *plane,
11536                                  struct drm_plane_state *state)
11537 {
11538         /* Update watermarks on tiling changes. */
11539         if (!plane->state->fb || !state->fb ||
11540             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11541             plane->state->rotation != state->rotation)
11542                 return true;
11543
11544         if (plane->state->crtc_w != state->crtc_w)
11545                 return true;
11546
11547         return false;
11548 }
11549
11550 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11551                                     struct drm_plane_state *plane_state)
11552 {
11553         struct drm_crtc *crtc = crtc_state->crtc;
11554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11555         struct drm_plane *plane = plane_state->plane;
11556         struct drm_device *dev = crtc->dev;
11557         struct drm_i915_private *dev_priv = dev->dev_private;
11558         struct intel_plane_state *old_plane_state =
11559                 to_intel_plane_state(plane->state);
11560         int idx = intel_crtc->base.base.id, ret;
11561         int i = drm_plane_index(plane);
11562         bool mode_changed = needs_modeset(crtc_state);
11563         bool was_crtc_enabled = crtc->state->active;
11564         bool is_crtc_enabled = crtc_state->active;
11565
11566         bool turn_off, turn_on, visible, was_visible;
11567         struct drm_framebuffer *fb = plane_state->fb;
11568
11569         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11570             plane->type != DRM_PLANE_TYPE_CURSOR) {
11571                 ret = skl_update_scaler_plane(
11572                         to_intel_crtc_state(crtc_state),
11573                         to_intel_plane_state(plane_state));
11574                 if (ret)
11575                         return ret;
11576         }
11577
11578         /*
11579          * Disabling a plane is always okay; we just need to update
11580          * fb tracking in a special way since cleanup_fb() won't
11581          * get called by the plane helpers.
11582          */
11583         if (old_plane_state->base.fb && !fb)
11584                 intel_crtc->atomic.disabled_planes |= 1 << i;
11585
11586         was_visible = old_plane_state->visible;
11587         visible = to_intel_plane_state(plane_state)->visible;
11588
11589         if (!was_crtc_enabled && WARN_ON(was_visible))
11590                 was_visible = false;
11591
11592         if (!is_crtc_enabled && WARN_ON(visible))
11593                 visible = false;
11594
11595         if (!was_visible && !visible)
11596                 return 0;
11597
11598         turn_off = was_visible && (!visible || mode_changed);
11599         turn_on = visible && (!was_visible || mode_changed);
11600
11601         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11602                          plane->base.id, fb ? fb->base.id : -1);
11603
11604         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11605                          plane->base.id, was_visible, visible,
11606                          turn_off, turn_on, mode_changed);
11607
11608         if (turn_on) {
11609                 intel_crtc->atomic.update_wm_pre = true;
11610                 /* must disable cxsr around plane enable/disable */
11611                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11612                         intel_crtc->atomic.disable_cxsr = true;
11613                         /* to potentially re-enable cxsr */
11614                         intel_crtc->atomic.wait_vblank = true;
11615                         intel_crtc->atomic.update_wm_post = true;
11616                 }
11617         } else if (turn_off) {
11618                 intel_crtc->atomic.update_wm_post = true;
11619                 /* must disable cxsr around plane enable/disable */
11620                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11621                         if (is_crtc_enabled)
11622                                 intel_crtc->atomic.wait_vblank = true;
11623                         intel_crtc->atomic.disable_cxsr = true;
11624                 }
11625         } else if (intel_wm_need_update(plane, plane_state)) {
11626                 intel_crtc->atomic.update_wm_pre = true;
11627         }
11628
11629         if (visible || was_visible)
11630                 intel_crtc->atomic.fb_bits |=
11631                         to_intel_plane(plane)->frontbuffer_bit;
11632
11633         switch (plane->type) {
11634         case DRM_PLANE_TYPE_PRIMARY:
11635                 intel_crtc->atomic.wait_for_flips = true;
11636                 intel_crtc->atomic.pre_disable_primary = turn_off;
11637                 intel_crtc->atomic.post_enable_primary = turn_on;
11638
11639                 if (turn_off) {
11640                         /*
11641                          * FIXME: Actually if we will still have any other
11642                          * plane enabled on the pipe we could let IPS enabled
11643                          * still, but for now lets consider that when we make
11644                          * primary invisible by setting DSPCNTR to 0 on
11645                          * update_primary_plane function IPS needs to be
11646                          * disable.
11647                          */
11648                         intel_crtc->atomic.disable_ips = true;
11649
11650                         intel_crtc->atomic.disable_fbc = true;
11651                 }
11652
11653                 /*
11654                  * FBC does not work on some platforms for rotated
11655                  * planes, so disable it when rotation is not 0 and
11656                  * update it when rotation is set back to 0.
11657                  *
11658                  * FIXME: This is redundant with the fbc update done in
11659                  * the primary plane enable function except that that
11660                  * one is done too late. We eventually need to unify
11661                  * this.
11662                  */
11663
11664                 if (visible &&
11665                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11666                     dev_priv->fbc.crtc == intel_crtc &&
11667                     plane_state->rotation != BIT(DRM_ROTATE_0))
11668                         intel_crtc->atomic.disable_fbc = true;
11669
11670                 /*
11671                  * BDW signals flip done immediately if the plane
11672                  * is disabled, even if the plane enable is already
11673                  * armed to occur at the next vblank :(
11674                  */
11675                 if (turn_on && IS_BROADWELL(dev))
11676                         intel_crtc->atomic.wait_vblank = true;
11677
11678                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11679                 break;
11680         case DRM_PLANE_TYPE_CURSOR:
11681                 break;
11682         case DRM_PLANE_TYPE_OVERLAY:
11683                 if (turn_off && !mode_changed) {
11684                         intel_crtc->atomic.wait_vblank = true;
11685                         intel_crtc->atomic.update_sprite_watermarks |=
11686                                 1 << i;
11687                 }
11688         }
11689         return 0;
11690 }
11691
11692 static bool encoders_cloneable(const struct intel_encoder *a,
11693                                const struct intel_encoder *b)
11694 {
11695         /* masks could be asymmetric, so check both ways */
11696         return a == b || (a->cloneable & (1 << b->type) &&
11697                           b->cloneable & (1 << a->type));
11698 }
11699
11700 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11701                                          struct intel_crtc *crtc,
11702                                          struct intel_encoder *encoder)
11703 {
11704         struct intel_encoder *source_encoder;
11705         struct drm_connector *connector;
11706         struct drm_connector_state *connector_state;
11707         int i;
11708
11709         for_each_connector_in_state(state, connector, connector_state, i) {
11710                 if (connector_state->crtc != &crtc->base)
11711                         continue;
11712
11713                 source_encoder =
11714                         to_intel_encoder(connector_state->best_encoder);
11715                 if (!encoders_cloneable(encoder, source_encoder))
11716                         return false;
11717         }
11718
11719         return true;
11720 }
11721
11722 static bool check_encoder_cloning(struct drm_atomic_state *state,
11723                                   struct intel_crtc *crtc)
11724 {
11725         struct intel_encoder *encoder;
11726         struct drm_connector *connector;
11727         struct drm_connector_state *connector_state;
11728         int i;
11729
11730         for_each_connector_in_state(state, connector, connector_state, i) {
11731                 if (connector_state->crtc != &crtc->base)
11732                         continue;
11733
11734                 encoder = to_intel_encoder(connector_state->best_encoder);
11735                 if (!check_single_encoder_cloning(state, crtc, encoder))
11736                         return false;
11737         }
11738
11739         return true;
11740 }
11741
11742 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11743                                    struct drm_crtc_state *crtc_state)
11744 {
11745         struct drm_device *dev = crtc->dev;
11746         struct drm_i915_private *dev_priv = dev->dev_private;
11747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11748         struct intel_crtc_state *pipe_config =
11749                 to_intel_crtc_state(crtc_state);
11750         struct drm_atomic_state *state = crtc_state->state;
11751         int ret;
11752         bool mode_changed = needs_modeset(crtc_state);
11753
11754         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11755                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11756                 return -EINVAL;
11757         }
11758
11759         if (mode_changed && !crtc_state->active)
11760                 intel_crtc->atomic.update_wm_post = true;
11761
11762         if (mode_changed && crtc_state->enable &&
11763             dev_priv->display.crtc_compute_clock &&
11764             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11765                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11766                                                            pipe_config);
11767                 if (ret)
11768                         return ret;
11769         }
11770
11771         ret = 0;
11772         if (INTEL_INFO(dev)->gen >= 9) {
11773                 if (mode_changed)
11774                         ret = skl_update_scaler_crtc(pipe_config);
11775
11776                 if (!ret)
11777                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11778                                                          pipe_config);
11779         }
11780
11781         return ret;
11782 }
11783
11784 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11785         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11786         .load_lut = intel_crtc_load_lut,
11787         .atomic_begin = intel_begin_crtc_commit,
11788         .atomic_flush = intel_finish_crtc_commit,
11789         .atomic_check = intel_crtc_atomic_check,
11790 };
11791
11792 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11793 {
11794         struct intel_connector *connector;
11795
11796         for_each_intel_connector(dev, connector) {
11797                 if (connector->base.encoder) {
11798                         connector->base.state->best_encoder =
11799                                 connector->base.encoder;
11800                         connector->base.state->crtc =
11801                                 connector->base.encoder->crtc;
11802                 } else {
11803                         connector->base.state->best_encoder = NULL;
11804                         connector->base.state->crtc = NULL;
11805                 }
11806         }
11807 }
11808
11809 static void
11810 connected_sink_compute_bpp(struct intel_connector *connector,
11811                            struct intel_crtc_state *pipe_config)
11812 {
11813         int bpp = pipe_config->pipe_bpp;
11814
11815         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11816                 connector->base.base.id,
11817                 connector->base.name);
11818
11819         /* Don't use an invalid EDID bpc value */
11820         if (connector->base.display_info.bpc &&
11821             connector->base.display_info.bpc * 3 < bpp) {
11822                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11823                               bpp, connector->base.display_info.bpc*3);
11824                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11825         }
11826
11827         /* Clamp bpp to 8 on screens without EDID 1.4 */
11828         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11829                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11830                               bpp);
11831                 pipe_config->pipe_bpp = 24;
11832         }
11833 }
11834
11835 static int
11836 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11837                           struct intel_crtc_state *pipe_config)
11838 {
11839         struct drm_device *dev = crtc->base.dev;
11840         struct drm_atomic_state *state;
11841         struct drm_connector *connector;
11842         struct drm_connector_state *connector_state;
11843         int bpp, i;
11844
11845         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11846                 bpp = 10*3;
11847         else if (INTEL_INFO(dev)->gen >= 5)
11848                 bpp = 12*3;
11849         else
11850                 bpp = 8*3;
11851
11852
11853         pipe_config->pipe_bpp = bpp;
11854
11855         state = pipe_config->base.state;
11856
11857         /* Clamp display bpp to EDID value */
11858         for_each_connector_in_state(state, connector, connector_state, i) {
11859                 if (connector_state->crtc != &crtc->base)
11860                         continue;
11861
11862                 connected_sink_compute_bpp(to_intel_connector(connector),
11863                                            pipe_config);
11864         }
11865
11866         return bpp;
11867 }
11868
11869 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11870 {
11871         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11872                         "type: 0x%x flags: 0x%x\n",
11873                 mode->crtc_clock,
11874                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11875                 mode->crtc_hsync_end, mode->crtc_htotal,
11876                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11877                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11878 }
11879
11880 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11881                                    struct intel_crtc_state *pipe_config,
11882                                    const char *context)
11883 {
11884         struct drm_device *dev = crtc->base.dev;
11885         struct drm_plane *plane;
11886         struct intel_plane *intel_plane;
11887         struct intel_plane_state *state;
11888         struct drm_framebuffer *fb;
11889
11890         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11891                       context, pipe_config, pipe_name(crtc->pipe));
11892
11893         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11894         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11895                       pipe_config->pipe_bpp, pipe_config->dither);
11896         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11897                       pipe_config->has_pch_encoder,
11898                       pipe_config->fdi_lanes,
11899                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11900                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11901                       pipe_config->fdi_m_n.tu);
11902         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11903                       pipe_config->has_dp_encoder,
11904                       pipe_config->lane_count,
11905                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11906                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11907                       pipe_config->dp_m_n.tu);
11908
11909         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11910                       pipe_config->has_dp_encoder,
11911                       pipe_config->lane_count,
11912                       pipe_config->dp_m2_n2.gmch_m,
11913                       pipe_config->dp_m2_n2.gmch_n,
11914                       pipe_config->dp_m2_n2.link_m,
11915                       pipe_config->dp_m2_n2.link_n,
11916                       pipe_config->dp_m2_n2.tu);
11917
11918         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11919                       pipe_config->has_audio,
11920                       pipe_config->has_infoframe);
11921
11922         DRM_DEBUG_KMS("requested mode:\n");
11923         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11924         DRM_DEBUG_KMS("adjusted mode:\n");
11925         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11926         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11927         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11928         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11929                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11930         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11931                       crtc->num_scalers,
11932                       pipe_config->scaler_state.scaler_users,
11933                       pipe_config->scaler_state.scaler_id);
11934         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11935                       pipe_config->gmch_pfit.control,
11936                       pipe_config->gmch_pfit.pgm_ratios,
11937                       pipe_config->gmch_pfit.lvds_border_bits);
11938         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11939                       pipe_config->pch_pfit.pos,
11940                       pipe_config->pch_pfit.size,
11941                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11942         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11943         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11944
11945         if (IS_BROXTON(dev)) {
11946                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11947                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11948                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11949                               pipe_config->ddi_pll_sel,
11950                               pipe_config->dpll_hw_state.ebb0,
11951                               pipe_config->dpll_hw_state.ebb4,
11952                               pipe_config->dpll_hw_state.pll0,
11953                               pipe_config->dpll_hw_state.pll1,
11954                               pipe_config->dpll_hw_state.pll2,
11955                               pipe_config->dpll_hw_state.pll3,
11956                               pipe_config->dpll_hw_state.pll6,
11957                               pipe_config->dpll_hw_state.pll8,
11958                               pipe_config->dpll_hw_state.pll9,
11959                               pipe_config->dpll_hw_state.pll10,
11960                               pipe_config->dpll_hw_state.pcsdw12);
11961         } else if (IS_SKYLAKE(dev)) {
11962                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11963                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11964                               pipe_config->ddi_pll_sel,
11965                               pipe_config->dpll_hw_state.ctrl1,
11966                               pipe_config->dpll_hw_state.cfgcr1,
11967                               pipe_config->dpll_hw_state.cfgcr2);
11968         } else if (HAS_DDI(dev)) {
11969                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11970                               pipe_config->ddi_pll_sel,
11971                               pipe_config->dpll_hw_state.wrpll);
11972         } else {
11973                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11974                               "fp0: 0x%x, fp1: 0x%x\n",
11975                               pipe_config->dpll_hw_state.dpll,
11976                               pipe_config->dpll_hw_state.dpll_md,
11977                               pipe_config->dpll_hw_state.fp0,
11978                               pipe_config->dpll_hw_state.fp1);
11979         }
11980
11981         DRM_DEBUG_KMS("planes on this crtc\n");
11982         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11983                 intel_plane = to_intel_plane(plane);
11984                 if (intel_plane->pipe != crtc->pipe)
11985                         continue;
11986
11987                 state = to_intel_plane_state(plane->state);
11988                 fb = state->base.fb;
11989                 if (!fb) {
11990                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11991                                 "disabled, scaler_id = %d\n",
11992                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11993                                 plane->base.id, intel_plane->pipe,
11994                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11995                                 drm_plane_index(plane), state->scaler_id);
11996                         continue;
11997                 }
11998
11999                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12000                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12001                         plane->base.id, intel_plane->pipe,
12002                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12003                         drm_plane_index(plane));
12004                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12005                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12006                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12007                         state->scaler_id,
12008                         state->src.x1 >> 16, state->src.y1 >> 16,
12009                         drm_rect_width(&state->src) >> 16,
12010                         drm_rect_height(&state->src) >> 16,
12011                         state->dst.x1, state->dst.y1,
12012                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12013         }
12014 }
12015
12016 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12017 {
12018         struct drm_device *dev = state->dev;
12019         struct intel_encoder *encoder;
12020         struct drm_connector *connector;
12021         struct drm_connector_state *connector_state;
12022         unsigned int used_ports = 0;
12023         int i;
12024
12025         /*
12026          * Walk the connector list instead of the encoder
12027          * list to detect the problem on ddi platforms
12028          * where there's just one encoder per digital port.
12029          */
12030         for_each_connector_in_state(state, connector, connector_state, i) {
12031                 if (!connector_state->best_encoder)
12032                         continue;
12033
12034                 encoder = to_intel_encoder(connector_state->best_encoder);
12035
12036                 WARN_ON(!connector_state->crtc);
12037
12038                 switch (encoder->type) {
12039                         unsigned int port_mask;
12040                 case INTEL_OUTPUT_UNKNOWN:
12041                         if (WARN_ON(!HAS_DDI(dev)))
12042                                 break;
12043                 case INTEL_OUTPUT_DISPLAYPORT:
12044                 case INTEL_OUTPUT_HDMI:
12045                 case INTEL_OUTPUT_EDP:
12046                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12047
12048                         /* the same port mustn't appear more than once */
12049                         if (used_ports & port_mask)
12050                                 return false;
12051
12052                         used_ports |= port_mask;
12053                 default:
12054                         break;
12055                 }
12056         }
12057
12058         return true;
12059 }
12060
12061 static void
12062 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12063 {
12064         struct drm_crtc_state tmp_state;
12065         struct intel_crtc_scaler_state scaler_state;
12066         struct intel_dpll_hw_state dpll_hw_state;
12067         enum intel_dpll_id shared_dpll;
12068         uint32_t ddi_pll_sel;
12069         bool force_thru;
12070
12071         /* FIXME: before the switch to atomic started, a new pipe_config was
12072          * kzalloc'd. Code that depends on any field being zero should be
12073          * fixed, so that the crtc_state can be safely duplicated. For now,
12074          * only fields that are know to not cause problems are preserved. */
12075
12076         tmp_state = crtc_state->base;
12077         scaler_state = crtc_state->scaler_state;
12078         shared_dpll = crtc_state->shared_dpll;
12079         dpll_hw_state = crtc_state->dpll_hw_state;
12080         ddi_pll_sel = crtc_state->ddi_pll_sel;
12081         force_thru = crtc_state->pch_pfit.force_thru;
12082
12083         memset(crtc_state, 0, sizeof *crtc_state);
12084
12085         crtc_state->base = tmp_state;
12086         crtc_state->scaler_state = scaler_state;
12087         crtc_state->shared_dpll = shared_dpll;
12088         crtc_state->dpll_hw_state = dpll_hw_state;
12089         crtc_state->ddi_pll_sel = ddi_pll_sel;
12090         crtc_state->pch_pfit.force_thru = force_thru;
12091 }
12092
12093 static int
12094 intel_modeset_pipe_config(struct drm_crtc *crtc,
12095                           struct intel_crtc_state *pipe_config)
12096 {
12097         struct drm_atomic_state *state = pipe_config->base.state;
12098         struct intel_encoder *encoder;
12099         struct drm_connector *connector;
12100         struct drm_connector_state *connector_state;
12101         int base_bpp, ret = -EINVAL;
12102         int i;
12103         bool retry = true;
12104
12105         clear_intel_crtc_state(pipe_config);
12106
12107         pipe_config->cpu_transcoder =
12108                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12109
12110         /*
12111          * Sanitize sync polarity flags based on requested ones. If neither
12112          * positive or negative polarity is requested, treat this as meaning
12113          * negative polarity.
12114          */
12115         if (!(pipe_config->base.adjusted_mode.flags &
12116               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12117                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12118
12119         if (!(pipe_config->base.adjusted_mode.flags &
12120               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12121                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12122
12123         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12124          * plane pixel format and any sink constraints into account. Returns the
12125          * source plane bpp so that dithering can be selected on mismatches
12126          * after encoders and crtc also have had their say. */
12127         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12128                                              pipe_config);
12129         if (base_bpp < 0)
12130                 goto fail;
12131
12132         /*
12133          * Determine the real pipe dimensions. Note that stereo modes can
12134          * increase the actual pipe size due to the frame doubling and
12135          * insertion of additional space for blanks between the frame. This
12136          * is stored in the crtc timings. We use the requested mode to do this
12137          * computation to clearly distinguish it from the adjusted mode, which
12138          * can be changed by the connectors in the below retry loop.
12139          */
12140         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12141                                &pipe_config->pipe_src_w,
12142                                &pipe_config->pipe_src_h);
12143
12144 encoder_retry:
12145         /* Ensure the port clock defaults are reset when retrying. */
12146         pipe_config->port_clock = 0;
12147         pipe_config->pixel_multiplier = 1;
12148
12149         /* Fill in default crtc timings, allow encoders to overwrite them. */
12150         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12151                               CRTC_STEREO_DOUBLE);
12152
12153         /* Pass our mode to the connectors and the CRTC to give them a chance to
12154          * adjust it according to limitations or connector properties, and also
12155          * a chance to reject the mode entirely.
12156          */
12157         for_each_connector_in_state(state, connector, connector_state, i) {
12158                 if (connector_state->crtc != crtc)
12159                         continue;
12160
12161                 encoder = to_intel_encoder(connector_state->best_encoder);
12162
12163                 if (!(encoder->compute_config(encoder, pipe_config))) {
12164                         DRM_DEBUG_KMS("Encoder config failure\n");
12165                         goto fail;
12166                 }
12167         }
12168
12169         /* Set default port clock if not overwritten by the encoder. Needs to be
12170          * done afterwards in case the encoder adjusts the mode. */
12171         if (!pipe_config->port_clock)
12172                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12173                         * pipe_config->pixel_multiplier;
12174
12175         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12176         if (ret < 0) {
12177                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12178                 goto fail;
12179         }
12180
12181         if (ret == RETRY) {
12182                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12183                         ret = -EINVAL;
12184                         goto fail;
12185                 }
12186
12187                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12188                 retry = false;
12189                 goto encoder_retry;
12190         }
12191
12192         /* Dithering seems to not pass-through bits correctly when it should, so
12193          * only enable it on 6bpc panels. */
12194         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12195         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12196                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12197
12198 fail:
12199         return ret;
12200 }
12201
12202 static void
12203 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12204 {
12205         struct drm_crtc *crtc;
12206         struct drm_crtc_state *crtc_state;
12207         int i;
12208
12209         /* Double check state. */
12210         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12211                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12212
12213                 /* Update hwmode for vblank functions */
12214                 if (crtc->state->active)
12215                         crtc->hwmode = crtc->state->adjusted_mode;
12216                 else
12217                         crtc->hwmode.crtc_clock = 0;
12218         }
12219 }
12220
12221 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12222 {
12223         int diff;
12224
12225         if (clock1 == clock2)
12226                 return true;
12227
12228         if (!clock1 || !clock2)
12229                 return false;
12230
12231         diff = abs(clock1 - clock2);
12232
12233         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12234                 return true;
12235
12236         return false;
12237 }
12238
12239 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12240         list_for_each_entry((intel_crtc), \
12241                             &(dev)->mode_config.crtc_list, \
12242                             base.head) \
12243                 if (mask & (1 <<(intel_crtc)->pipe))
12244
12245
12246 static bool
12247 intel_compare_m_n(unsigned int m, unsigned int n,
12248                   unsigned int m2, unsigned int n2,
12249                   bool exact)
12250 {
12251         if (m == m2 && n == n2)
12252                 return true;
12253
12254         if (exact || !m || !n || !m2 || !n2)
12255                 return false;
12256
12257         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12258
12259         if (m > m2) {
12260                 while (m > m2) {
12261                         m2 <<= 1;
12262                         n2 <<= 1;
12263                 }
12264         } else if (m < m2) {
12265                 while (m < m2) {
12266                         m <<= 1;
12267                         n <<= 1;
12268                 }
12269         }
12270
12271         return m == m2 && n == n2;
12272 }
12273
12274 static bool
12275 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12276                        struct intel_link_m_n *m2_n2,
12277                        bool adjust)
12278 {
12279         if (m_n->tu == m2_n2->tu &&
12280             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12281                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12282             intel_compare_m_n(m_n->link_m, m_n->link_n,
12283                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12284                 if (adjust)
12285                         *m2_n2 = *m_n;
12286
12287                 return true;
12288         }
12289
12290         return false;
12291 }
12292
12293 static bool
12294 intel_pipe_config_compare(struct drm_device *dev,
12295                           struct intel_crtc_state *current_config,
12296                           struct intel_crtc_state *pipe_config,
12297                           bool adjust)
12298 {
12299         bool ret = true;
12300
12301 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12302         do { \
12303                 if (!adjust) \
12304                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12305                 else \
12306                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12307         } while (0)
12308
12309 #define PIPE_CONF_CHECK_X(name) \
12310         if (current_config->name != pipe_config->name) { \
12311                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12312                           "(expected 0x%08x, found 0x%08x)\n", \
12313                           current_config->name, \
12314                           pipe_config->name); \
12315                 ret = false; \
12316         }
12317
12318 #define PIPE_CONF_CHECK_I(name) \
12319         if (current_config->name != pipe_config->name) { \
12320                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12321                           "(expected %i, found %i)\n", \
12322                           current_config->name, \
12323                           pipe_config->name); \
12324                 ret = false; \
12325         }
12326
12327 #define PIPE_CONF_CHECK_M_N(name) \
12328         if (!intel_compare_link_m_n(&current_config->name, \
12329                                     &pipe_config->name,\
12330                                     adjust)) { \
12331                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12332                           "(expected tu %i gmch %i/%i link %i/%i, " \
12333                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12334                           current_config->name.tu, \
12335                           current_config->name.gmch_m, \
12336                           current_config->name.gmch_n, \
12337                           current_config->name.link_m, \
12338                           current_config->name.link_n, \
12339                           pipe_config->name.tu, \
12340                           pipe_config->name.gmch_m, \
12341                           pipe_config->name.gmch_n, \
12342                           pipe_config->name.link_m, \
12343                           pipe_config->name.link_n); \
12344                 ret = false; \
12345         }
12346
12347 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12348         if (!intel_compare_link_m_n(&current_config->name, \
12349                                     &pipe_config->name, adjust) && \
12350             !intel_compare_link_m_n(&current_config->alt_name, \
12351                                     &pipe_config->name, adjust)) { \
12352                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353                           "(expected tu %i gmch %i/%i link %i/%i, " \
12354                           "or tu %i gmch %i/%i link %i/%i, " \
12355                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12356                           current_config->name.tu, \
12357                           current_config->name.gmch_m, \
12358                           current_config->name.gmch_n, \
12359                           current_config->name.link_m, \
12360                           current_config->name.link_n, \
12361                           current_config->alt_name.tu, \
12362                           current_config->alt_name.gmch_m, \
12363                           current_config->alt_name.gmch_n, \
12364                           current_config->alt_name.link_m, \
12365                           current_config->alt_name.link_n, \
12366                           pipe_config->name.tu, \
12367                           pipe_config->name.gmch_m, \
12368                           pipe_config->name.gmch_n, \
12369                           pipe_config->name.link_m, \
12370                           pipe_config->name.link_n); \
12371                 ret = false; \
12372         }
12373
12374 /* This is required for BDW+ where there is only one set of registers for
12375  * switching between high and low RR.
12376  * This macro can be used whenever a comparison has to be made between one
12377  * hw state and multiple sw state variables.
12378  */
12379 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12380         if ((current_config->name != pipe_config->name) && \
12381                 (current_config->alt_name != pipe_config->name)) { \
12382                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12383                                   "(expected %i or %i, found %i)\n", \
12384                                   current_config->name, \
12385                                   current_config->alt_name, \
12386                                   pipe_config->name); \
12387                         ret = false; \
12388         }
12389
12390 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12391         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12392                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12393                           "(expected %i, found %i)\n", \
12394                           current_config->name & (mask), \
12395                           pipe_config->name & (mask)); \
12396                 ret = false; \
12397         }
12398
12399 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12400         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12401                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12402                           "(expected %i, found %i)\n", \
12403                           current_config->name, \
12404                           pipe_config->name); \
12405                 ret = false; \
12406         }
12407
12408 #define PIPE_CONF_QUIRK(quirk)  \
12409         ((current_config->quirks | pipe_config->quirks) & (quirk))
12410
12411         PIPE_CONF_CHECK_I(cpu_transcoder);
12412
12413         PIPE_CONF_CHECK_I(has_pch_encoder);
12414         PIPE_CONF_CHECK_I(fdi_lanes);
12415         PIPE_CONF_CHECK_M_N(fdi_m_n);
12416
12417         PIPE_CONF_CHECK_I(has_dp_encoder);
12418         PIPE_CONF_CHECK_I(lane_count);
12419
12420         if (INTEL_INFO(dev)->gen < 8) {
12421                 PIPE_CONF_CHECK_M_N(dp_m_n);
12422
12423                 PIPE_CONF_CHECK_I(has_drrs);
12424                 if (current_config->has_drrs)
12425                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12426         } else
12427                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12428
12429         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12430         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12431         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12432         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12433         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12434         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12435
12436         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12437         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12438         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12439         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12440         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12441         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12442
12443         PIPE_CONF_CHECK_I(pixel_multiplier);
12444         PIPE_CONF_CHECK_I(has_hdmi_sink);
12445         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12446             IS_VALLEYVIEW(dev))
12447                 PIPE_CONF_CHECK_I(limited_color_range);
12448         PIPE_CONF_CHECK_I(has_infoframe);
12449
12450         PIPE_CONF_CHECK_I(has_audio);
12451
12452         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12453                               DRM_MODE_FLAG_INTERLACE);
12454
12455         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12456                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12457                                       DRM_MODE_FLAG_PHSYNC);
12458                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12459                                       DRM_MODE_FLAG_NHSYNC);
12460                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12461                                       DRM_MODE_FLAG_PVSYNC);
12462                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12463                                       DRM_MODE_FLAG_NVSYNC);
12464         }
12465
12466         PIPE_CONF_CHECK_I(pipe_src_w);
12467         PIPE_CONF_CHECK_I(pipe_src_h);
12468
12469         PIPE_CONF_CHECK_I(gmch_pfit.control);
12470         /* pfit ratios are autocomputed by the hw on gen4+ */
12471         if (INTEL_INFO(dev)->gen < 4)
12472                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12473         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12474
12475         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12476         if (current_config->pch_pfit.enabled) {
12477                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12478                 PIPE_CONF_CHECK_I(pch_pfit.size);
12479         }
12480
12481         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12482
12483         /* BDW+ don't expose a synchronous way to read the state */
12484         if (IS_HASWELL(dev))
12485                 PIPE_CONF_CHECK_I(ips_enabled);
12486
12487         PIPE_CONF_CHECK_I(double_wide);
12488
12489         PIPE_CONF_CHECK_X(ddi_pll_sel);
12490
12491         PIPE_CONF_CHECK_I(shared_dpll);
12492         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12493         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12494         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12495         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12496         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12497         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12498         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12499         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12500
12501         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12502                 PIPE_CONF_CHECK_I(pipe_bpp);
12503
12504         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12505         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12506
12507 #undef PIPE_CONF_CHECK_X
12508 #undef PIPE_CONF_CHECK_I
12509 #undef PIPE_CONF_CHECK_I_ALT
12510 #undef PIPE_CONF_CHECK_FLAGS
12511 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12512 #undef PIPE_CONF_QUIRK
12513 #undef INTEL_ERR_OR_DBG_KMS
12514
12515         return ret;
12516 }
12517
12518 static void check_wm_state(struct drm_device *dev)
12519 {
12520         struct drm_i915_private *dev_priv = dev->dev_private;
12521         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12522         struct intel_crtc *intel_crtc;
12523         int plane;
12524
12525         if (INTEL_INFO(dev)->gen < 9)
12526                 return;
12527
12528         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12529         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12530
12531         for_each_intel_crtc(dev, intel_crtc) {
12532                 struct skl_ddb_entry *hw_entry, *sw_entry;
12533                 const enum pipe pipe = intel_crtc->pipe;
12534
12535                 if (!intel_crtc->active)
12536                         continue;
12537
12538                 /* planes */
12539                 for_each_plane(dev_priv, pipe, plane) {
12540                         hw_entry = &hw_ddb.plane[pipe][plane];
12541                         sw_entry = &sw_ddb->plane[pipe][plane];
12542
12543                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12544                                 continue;
12545
12546                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12547                                   "(expected (%u,%u), found (%u,%u))\n",
12548                                   pipe_name(pipe), plane + 1,
12549                                   sw_entry->start, sw_entry->end,
12550                                   hw_entry->start, hw_entry->end);
12551                 }
12552
12553                 /* cursor */
12554                 hw_entry = &hw_ddb.cursor[pipe];
12555                 sw_entry = &sw_ddb->cursor[pipe];
12556
12557                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12558                         continue;
12559
12560                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12561                           "(expected (%u,%u), found (%u,%u))\n",
12562                           pipe_name(pipe),
12563                           sw_entry->start, sw_entry->end,
12564                           hw_entry->start, hw_entry->end);
12565         }
12566 }
12567
12568 static void
12569 check_connector_state(struct drm_device *dev,
12570                       struct drm_atomic_state *old_state)
12571 {
12572         struct drm_connector_state *old_conn_state;
12573         struct drm_connector *connector;
12574         int i;
12575
12576         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12577                 struct drm_encoder *encoder = connector->encoder;
12578                 struct drm_connector_state *state = connector->state;
12579
12580                 /* This also checks the encoder/connector hw state with the
12581                  * ->get_hw_state callbacks. */
12582                 intel_connector_check_state(to_intel_connector(connector));
12583
12584                 I915_STATE_WARN(state->best_encoder != encoder,
12585                      "connector's atomic encoder doesn't match legacy encoder\n");
12586         }
12587 }
12588
12589 static void
12590 check_encoder_state(struct drm_device *dev)
12591 {
12592         struct intel_encoder *encoder;
12593         struct intel_connector *connector;
12594
12595         for_each_intel_encoder(dev, encoder) {
12596                 bool enabled = false;
12597                 enum pipe pipe;
12598
12599                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12600                               encoder->base.base.id,
12601                               encoder->base.name);
12602
12603                 for_each_intel_connector(dev, connector) {
12604                         if (connector->base.state->best_encoder != &encoder->base)
12605                                 continue;
12606                         enabled = true;
12607
12608                         I915_STATE_WARN(connector->base.state->crtc !=
12609                                         encoder->base.crtc,
12610                              "connector's crtc doesn't match encoder crtc\n");
12611                 }
12612
12613                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12614                      "encoder's enabled state mismatch "
12615                      "(expected %i, found %i)\n",
12616                      !!encoder->base.crtc, enabled);
12617
12618                 if (!encoder->base.crtc) {
12619                         bool active;
12620
12621                         active = encoder->get_hw_state(encoder, &pipe);
12622                         I915_STATE_WARN(active,
12623                              "encoder detached but still enabled on pipe %c.\n",
12624                              pipe_name(pipe));
12625                 }
12626         }
12627 }
12628
12629 static void
12630 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12631 {
12632         struct drm_i915_private *dev_priv = dev->dev_private;
12633         struct intel_encoder *encoder;
12634         struct drm_crtc_state *old_crtc_state;
12635         struct drm_crtc *crtc;
12636         int i;
12637
12638         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12639                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12640                 struct intel_crtc_state *pipe_config, *sw_config;
12641                 bool active;
12642
12643                 if (!needs_modeset(crtc->state))
12644                         continue;
12645
12646                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12647                 pipe_config = to_intel_crtc_state(old_crtc_state);
12648                 memset(pipe_config, 0, sizeof(*pipe_config));
12649                 pipe_config->base.crtc = crtc;
12650                 pipe_config->base.state = old_state;
12651
12652                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12653                               crtc->base.id);
12654
12655                 active = dev_priv->display.get_pipe_config(intel_crtc,
12656                                                            pipe_config);
12657
12658                 /* hw state is inconsistent with the pipe quirk */
12659                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12660                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12661                         active = crtc->state->active;
12662
12663                 I915_STATE_WARN(crtc->state->active != active,
12664                      "crtc active state doesn't match with hw state "
12665                      "(expected %i, found %i)\n", crtc->state->active, active);
12666
12667                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12668                      "transitional active state does not match atomic hw state "
12669                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12670
12671                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12672                         enum pipe pipe;
12673
12674                         active = encoder->get_hw_state(encoder, &pipe);
12675                         I915_STATE_WARN(active != crtc->state->active,
12676                                 "[ENCODER:%i] active %i with crtc active %i\n",
12677                                 encoder->base.base.id, active, crtc->state->active);
12678
12679                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12680                                         "Encoder connected to wrong pipe %c\n",
12681                                         pipe_name(pipe));
12682
12683                         if (active)
12684                                 encoder->get_config(encoder, pipe_config);
12685                 }
12686
12687                 if (!crtc->state->active)
12688                         continue;
12689
12690                 sw_config = to_intel_crtc_state(crtc->state);
12691                 if (!intel_pipe_config_compare(dev, sw_config,
12692                                                pipe_config, false)) {
12693                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12694                         intel_dump_pipe_config(intel_crtc, pipe_config,
12695                                                "[hw state]");
12696                         intel_dump_pipe_config(intel_crtc, sw_config,
12697                                                "[sw state]");
12698                 }
12699         }
12700 }
12701
12702 static void
12703 check_shared_dpll_state(struct drm_device *dev)
12704 {
12705         struct drm_i915_private *dev_priv = dev->dev_private;
12706         struct intel_crtc *crtc;
12707         struct intel_dpll_hw_state dpll_hw_state;
12708         int i;
12709
12710         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12711                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12712                 int enabled_crtcs = 0, active_crtcs = 0;
12713                 bool active;
12714
12715                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12716
12717                 DRM_DEBUG_KMS("%s\n", pll->name);
12718
12719                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12720
12721                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12722                      "more active pll users than references: %i vs %i\n",
12723                      pll->active, hweight32(pll->config.crtc_mask));
12724                 I915_STATE_WARN(pll->active && !pll->on,
12725                      "pll in active use but not on in sw tracking\n");
12726                 I915_STATE_WARN(pll->on && !pll->active,
12727                      "pll in on but not on in use in sw tracking\n");
12728                 I915_STATE_WARN(pll->on != active,
12729                      "pll on state mismatch (expected %i, found %i)\n",
12730                      pll->on, active);
12731
12732                 for_each_intel_crtc(dev, crtc) {
12733                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12734                                 enabled_crtcs++;
12735                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12736                                 active_crtcs++;
12737                 }
12738                 I915_STATE_WARN(pll->active != active_crtcs,
12739                      "pll active crtcs mismatch (expected %i, found %i)\n",
12740                      pll->active, active_crtcs);
12741                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12742                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12743                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12744
12745                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12746                                        sizeof(dpll_hw_state)),
12747                      "pll hw state mismatch\n");
12748         }
12749 }
12750
12751 static void
12752 intel_modeset_check_state(struct drm_device *dev,
12753                           struct drm_atomic_state *old_state)
12754 {
12755         check_wm_state(dev);
12756         check_connector_state(dev, old_state);
12757         check_encoder_state(dev);
12758         check_crtc_state(dev, old_state);
12759         check_shared_dpll_state(dev);
12760 }
12761
12762 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12763                                      int dotclock)
12764 {
12765         /*
12766          * FDI already provided one idea for the dotclock.
12767          * Yell if the encoder disagrees.
12768          */
12769         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12770              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12771              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12772 }
12773
12774 static void update_scanline_offset(struct intel_crtc *crtc)
12775 {
12776         struct drm_device *dev = crtc->base.dev;
12777
12778         /*
12779          * The scanline counter increments at the leading edge of hsync.
12780          *
12781          * On most platforms it starts counting from vtotal-1 on the
12782          * first active line. That means the scanline counter value is
12783          * always one less than what we would expect. Ie. just after
12784          * start of vblank, which also occurs at start of hsync (on the
12785          * last active line), the scanline counter will read vblank_start-1.
12786          *
12787          * On gen2 the scanline counter starts counting from 1 instead
12788          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12789          * to keep the value positive), instead of adding one.
12790          *
12791          * On HSW+ the behaviour of the scanline counter depends on the output
12792          * type. For DP ports it behaves like most other platforms, but on HDMI
12793          * there's an extra 1 line difference. So we need to add two instead of
12794          * one to the value.
12795          */
12796         if (IS_GEN2(dev)) {
12797                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12798                 int vtotal;
12799
12800                 vtotal = mode->crtc_vtotal;
12801                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12802                         vtotal /= 2;
12803
12804                 crtc->scanline_offset = vtotal - 1;
12805         } else if (HAS_DDI(dev) &&
12806                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12807                 crtc->scanline_offset = 2;
12808         } else
12809                 crtc->scanline_offset = 1;
12810 }
12811
12812 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12813 {
12814         struct drm_device *dev = state->dev;
12815         struct drm_i915_private *dev_priv = to_i915(dev);
12816         struct intel_shared_dpll_config *shared_dpll = NULL;
12817         struct intel_crtc *intel_crtc;
12818         struct intel_crtc_state *intel_crtc_state;
12819         struct drm_crtc *crtc;
12820         struct drm_crtc_state *crtc_state;
12821         int i;
12822
12823         if (!dev_priv->display.crtc_compute_clock)
12824                 return;
12825
12826         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12827                 int dpll;
12828
12829                 intel_crtc = to_intel_crtc(crtc);
12830                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12831                 dpll = intel_crtc_state->shared_dpll;
12832
12833                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12834                         continue;
12835
12836                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12837
12838                 if (!shared_dpll)
12839                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12840
12841                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12842         }
12843 }
12844
12845 /*
12846  * This implements the workaround described in the "notes" section of the mode
12847  * set sequence documentation. When going from no pipes or single pipe to
12848  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12849  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12850  */
12851 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12852 {
12853         struct drm_crtc_state *crtc_state;
12854         struct intel_crtc *intel_crtc;
12855         struct drm_crtc *crtc;
12856         struct intel_crtc_state *first_crtc_state = NULL;
12857         struct intel_crtc_state *other_crtc_state = NULL;
12858         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12859         int i;
12860
12861         /* look at all crtc's that are going to be enabled in during modeset */
12862         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12863                 intel_crtc = to_intel_crtc(crtc);
12864
12865                 if (!crtc_state->active || !needs_modeset(crtc_state))
12866                         continue;
12867
12868                 if (first_crtc_state) {
12869                         other_crtc_state = to_intel_crtc_state(crtc_state);
12870                         break;
12871                 } else {
12872                         first_crtc_state = to_intel_crtc_state(crtc_state);
12873                         first_pipe = intel_crtc->pipe;
12874                 }
12875         }
12876
12877         /* No workaround needed? */
12878         if (!first_crtc_state)
12879                 return 0;
12880
12881         /* w/a possibly needed, check how many crtc's are already enabled. */
12882         for_each_intel_crtc(state->dev, intel_crtc) {
12883                 struct intel_crtc_state *pipe_config;
12884
12885                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12886                 if (IS_ERR(pipe_config))
12887                         return PTR_ERR(pipe_config);
12888
12889                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12890
12891                 if (!pipe_config->base.active ||
12892                     needs_modeset(&pipe_config->base))
12893                         continue;
12894
12895                 /* 2 or more enabled crtcs means no need for w/a */
12896                 if (enabled_pipe != INVALID_PIPE)
12897                         return 0;
12898
12899                 enabled_pipe = intel_crtc->pipe;
12900         }
12901
12902         if (enabled_pipe != INVALID_PIPE)
12903                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12904         else if (other_crtc_state)
12905                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12906
12907         return 0;
12908 }
12909
12910 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12911 {
12912         struct drm_crtc *crtc;
12913         struct drm_crtc_state *crtc_state;
12914         int ret = 0;
12915
12916         /* add all active pipes to the state */
12917         for_each_crtc(state->dev, crtc) {
12918                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12919                 if (IS_ERR(crtc_state))
12920                         return PTR_ERR(crtc_state);
12921
12922                 if (!crtc_state->active || needs_modeset(crtc_state))
12923                         continue;
12924
12925                 crtc_state->mode_changed = true;
12926
12927                 ret = drm_atomic_add_affected_connectors(state, crtc);
12928                 if (ret)
12929                         break;
12930
12931                 ret = drm_atomic_add_affected_planes(state, crtc);
12932                 if (ret)
12933                         break;
12934         }
12935
12936         return ret;
12937 }
12938
12939
12940 static int intel_modeset_checks(struct drm_atomic_state *state)
12941 {
12942         struct drm_device *dev = state->dev;
12943         struct drm_i915_private *dev_priv = dev->dev_private;
12944         int ret;
12945
12946         if (!check_digital_port_conflicts(state)) {
12947                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12948                 return -EINVAL;
12949         }
12950
12951         /*
12952          * See if the config requires any additional preparation, e.g.
12953          * to adjust global state with pipes off.  We need to do this
12954          * here so we can get the modeset_pipe updated config for the new
12955          * mode set on this crtc.  For other crtcs we need to use the
12956          * adjusted_mode bits in the crtc directly.
12957          */
12958         if (dev_priv->display.modeset_calc_cdclk) {
12959                 unsigned int cdclk;
12960
12961                 ret = dev_priv->display.modeset_calc_cdclk(state);
12962
12963                 cdclk = to_intel_atomic_state(state)->cdclk;
12964                 if (!ret && cdclk != dev_priv->cdclk_freq)
12965                         ret = intel_modeset_all_pipes(state);
12966
12967                 if (ret < 0)
12968                         return ret;
12969         } else
12970                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12971
12972         intel_modeset_clear_plls(state);
12973
12974         if (IS_HASWELL(dev))
12975                 return haswell_mode_set_planes_workaround(state);
12976
12977         return 0;
12978 }
12979
12980 /**
12981  * intel_atomic_check - validate state object
12982  * @dev: drm device
12983  * @state: state to validate
12984  */
12985 static int intel_atomic_check(struct drm_device *dev,
12986                               struct drm_atomic_state *state)
12987 {
12988         struct drm_crtc *crtc;
12989         struct drm_crtc_state *crtc_state;
12990         int ret, i;
12991         bool any_ms = false;
12992
12993         ret = drm_atomic_helper_check_modeset(dev, state);
12994         if (ret)
12995                 return ret;
12996
12997         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12998                 struct intel_crtc_state *pipe_config =
12999                         to_intel_crtc_state(crtc_state);
13000
13001                 /* Catch I915_MODE_FLAG_INHERITED */
13002                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13003                         crtc_state->mode_changed = true;
13004
13005                 if (!crtc_state->enable) {
13006                         if (needs_modeset(crtc_state))
13007                                 any_ms = true;
13008                         continue;
13009                 }
13010
13011                 if (!needs_modeset(crtc_state))
13012                         continue;
13013
13014                 /* FIXME: For only active_changed we shouldn't need to do any
13015                  * state recomputation at all. */
13016
13017                 ret = drm_atomic_add_affected_connectors(state, crtc);
13018                 if (ret)
13019                         return ret;
13020
13021                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13022                 if (ret)
13023                         return ret;
13024
13025                 if (i915.fastboot &&
13026                     intel_pipe_config_compare(state->dev,
13027                                         to_intel_crtc_state(crtc->state),
13028                                         pipe_config, true)) {
13029                         crtc_state->mode_changed = false;
13030                 }
13031
13032                 if (needs_modeset(crtc_state)) {
13033                         any_ms = true;
13034
13035                         ret = drm_atomic_add_affected_planes(state, crtc);
13036                         if (ret)
13037                                 return ret;
13038                 }
13039
13040                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13041                                        needs_modeset(crtc_state) ?
13042                                        "[modeset]" : "[fastset]");
13043         }
13044
13045         if (any_ms) {
13046                 ret = intel_modeset_checks(state);
13047
13048                 if (ret)
13049                         return ret;
13050         } else
13051                 to_intel_atomic_state(state)->cdclk =
13052                         to_i915(state->dev)->cdclk_freq;
13053
13054         return drm_atomic_helper_check_planes(state->dev, state);
13055 }
13056
13057 /**
13058  * intel_atomic_commit - commit validated state object
13059  * @dev: DRM device
13060  * @state: the top-level driver state object
13061  * @async: asynchronous commit
13062  *
13063  * This function commits a top-level state object that has been validated
13064  * with drm_atomic_helper_check().
13065  *
13066  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13067  * we can only handle plane-related operations and do not yet support
13068  * asynchronous commit.
13069  *
13070  * RETURNS
13071  * Zero for success or -errno.
13072  */
13073 static int intel_atomic_commit(struct drm_device *dev,
13074                                struct drm_atomic_state *state,
13075                                bool async)
13076 {
13077         struct drm_i915_private *dev_priv = dev->dev_private;
13078         struct drm_crtc *crtc;
13079         struct drm_crtc_state *crtc_state;
13080         int ret = 0;
13081         int i;
13082         bool any_ms = false;
13083
13084         if (async) {
13085                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13086                 return -EINVAL;
13087         }
13088
13089         ret = drm_atomic_helper_prepare_planes(dev, state);
13090         if (ret)
13091                 return ret;
13092
13093         drm_atomic_helper_swap_state(dev, state);
13094
13095         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13096                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13097
13098                 if (!needs_modeset(crtc->state))
13099                         continue;
13100
13101                 any_ms = true;
13102                 intel_pre_plane_update(intel_crtc);
13103
13104                 if (crtc_state->active) {
13105                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13106                         dev_priv->display.crtc_disable(crtc);
13107                         intel_crtc->active = false;
13108                         intel_disable_shared_dpll(intel_crtc);
13109                 }
13110         }
13111
13112         /* Only after disabling all output pipelines that will be changed can we
13113          * update the the output configuration. */
13114         intel_modeset_update_crtc_state(state);
13115
13116         if (any_ms) {
13117                 intel_shared_dpll_commit(state);
13118
13119                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13120                 modeset_update_crtc_power_domains(state);
13121         }
13122
13123         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13124         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13125                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13126                 bool modeset = needs_modeset(crtc->state);
13127
13128                 if (modeset && crtc->state->active) {
13129                         update_scanline_offset(to_intel_crtc(crtc));
13130                         dev_priv->display.crtc_enable(crtc);
13131                 }
13132
13133                 if (!modeset)
13134                         intel_pre_plane_update(intel_crtc);
13135
13136                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13137                 intel_post_plane_update(intel_crtc);
13138         }
13139
13140         /* FIXME: add subpixel order */
13141
13142         drm_atomic_helper_wait_for_vblanks(dev, state);
13143         drm_atomic_helper_cleanup_planes(dev, state);
13144
13145         if (any_ms)
13146                 intel_modeset_check_state(dev, state);
13147
13148         drm_atomic_state_free(state);
13149
13150         return 0;
13151 }
13152
13153 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13154 {
13155         struct drm_device *dev = crtc->dev;
13156         struct drm_atomic_state *state;
13157         struct drm_crtc_state *crtc_state;
13158         int ret;
13159
13160         state = drm_atomic_state_alloc(dev);
13161         if (!state) {
13162                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13163                               crtc->base.id);
13164                 return;
13165         }
13166
13167         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13168
13169 retry:
13170         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13171         ret = PTR_ERR_OR_ZERO(crtc_state);
13172         if (!ret) {
13173                 if (!crtc_state->active)
13174                         goto out;
13175
13176                 crtc_state->mode_changed = true;
13177                 ret = drm_atomic_commit(state);
13178         }
13179
13180         if (ret == -EDEADLK) {
13181                 drm_atomic_state_clear(state);
13182                 drm_modeset_backoff(state->acquire_ctx);
13183                 goto retry;
13184         }
13185
13186         if (ret)
13187 out:
13188                 drm_atomic_state_free(state);
13189 }
13190
13191 #undef for_each_intel_crtc_masked
13192
13193 static const struct drm_crtc_funcs intel_crtc_funcs = {
13194         .gamma_set = intel_crtc_gamma_set,
13195         .set_config = drm_atomic_helper_set_config,
13196         .destroy = intel_crtc_destroy,
13197         .page_flip = intel_crtc_page_flip,
13198         .atomic_duplicate_state = intel_crtc_duplicate_state,
13199         .atomic_destroy_state = intel_crtc_destroy_state,
13200 };
13201
13202 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13203                                       struct intel_shared_dpll *pll,
13204                                       struct intel_dpll_hw_state *hw_state)
13205 {
13206         uint32_t val;
13207
13208         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13209                 return false;
13210
13211         val = I915_READ(PCH_DPLL(pll->id));
13212         hw_state->dpll = val;
13213         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13214         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13215
13216         return val & DPLL_VCO_ENABLE;
13217 }
13218
13219 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13220                                   struct intel_shared_dpll *pll)
13221 {
13222         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13223         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13224 }
13225
13226 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13227                                 struct intel_shared_dpll *pll)
13228 {
13229         /* PCH refclock must be enabled first */
13230         ibx_assert_pch_refclk_enabled(dev_priv);
13231
13232         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13233
13234         /* Wait for the clocks to stabilize. */
13235         POSTING_READ(PCH_DPLL(pll->id));
13236         udelay(150);
13237
13238         /* The pixel multiplier can only be updated once the
13239          * DPLL is enabled and the clocks are stable.
13240          *
13241          * So write it again.
13242          */
13243         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13244         POSTING_READ(PCH_DPLL(pll->id));
13245         udelay(200);
13246 }
13247
13248 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13249                                  struct intel_shared_dpll *pll)
13250 {
13251         struct drm_device *dev = dev_priv->dev;
13252         struct intel_crtc *crtc;
13253
13254         /* Make sure no transcoder isn't still depending on us. */
13255         for_each_intel_crtc(dev, crtc) {
13256                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13257                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13258         }
13259
13260         I915_WRITE(PCH_DPLL(pll->id), 0);
13261         POSTING_READ(PCH_DPLL(pll->id));
13262         udelay(200);
13263 }
13264
13265 static char *ibx_pch_dpll_names[] = {
13266         "PCH DPLL A",
13267         "PCH DPLL B",
13268 };
13269
13270 static void ibx_pch_dpll_init(struct drm_device *dev)
13271 {
13272         struct drm_i915_private *dev_priv = dev->dev_private;
13273         int i;
13274
13275         dev_priv->num_shared_dpll = 2;
13276
13277         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13278                 dev_priv->shared_dplls[i].id = i;
13279                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13280                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13281                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13282                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13283                 dev_priv->shared_dplls[i].get_hw_state =
13284                         ibx_pch_dpll_get_hw_state;
13285         }
13286 }
13287
13288 static void intel_shared_dpll_init(struct drm_device *dev)
13289 {
13290         struct drm_i915_private *dev_priv = dev->dev_private;
13291
13292         intel_update_cdclk(dev);
13293
13294         if (HAS_DDI(dev))
13295                 intel_ddi_pll_init(dev);
13296         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13297                 ibx_pch_dpll_init(dev);
13298         else
13299                 dev_priv->num_shared_dpll = 0;
13300
13301         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13302 }
13303
13304 /**
13305  * intel_prepare_plane_fb - Prepare fb for usage on plane
13306  * @plane: drm plane to prepare for
13307  * @fb: framebuffer to prepare for presentation
13308  *
13309  * Prepares a framebuffer for usage on a display plane.  Generally this
13310  * involves pinning the underlying object and updating the frontbuffer tracking
13311  * bits.  Some older platforms need special physical address handling for
13312  * cursor planes.
13313  *
13314  * Returns 0 on success, negative error code on failure.
13315  */
13316 int
13317 intel_prepare_plane_fb(struct drm_plane *plane,
13318                        struct drm_framebuffer *fb,
13319                        const struct drm_plane_state *new_state)
13320 {
13321         struct drm_device *dev = plane->dev;
13322         struct intel_plane *intel_plane = to_intel_plane(plane);
13323         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13324         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13325         int ret = 0;
13326
13327         if (!obj)
13328                 return 0;
13329
13330         mutex_lock(&dev->struct_mutex);
13331
13332         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13333             INTEL_INFO(dev)->cursor_needs_physical) {
13334                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13335                 ret = i915_gem_object_attach_phys(obj, align);
13336                 if (ret)
13337                         DRM_DEBUG_KMS("failed to attach phys object\n");
13338         } else {
13339                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13340         }
13341
13342         if (ret == 0)
13343                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13344
13345         mutex_unlock(&dev->struct_mutex);
13346
13347         return ret;
13348 }
13349
13350 /**
13351  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13352  * @plane: drm plane to clean up for
13353  * @fb: old framebuffer that was on plane
13354  *
13355  * Cleans up a framebuffer that has just been removed from a plane.
13356  */
13357 void
13358 intel_cleanup_plane_fb(struct drm_plane *plane,
13359                        struct drm_framebuffer *fb,
13360                        const struct drm_plane_state *old_state)
13361 {
13362         struct drm_device *dev = plane->dev;
13363         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13364
13365         if (WARN_ON(!obj))
13366                 return;
13367
13368         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13369             !INTEL_INFO(dev)->cursor_needs_physical) {
13370                 mutex_lock(&dev->struct_mutex);
13371                 intel_unpin_fb_obj(fb, old_state);
13372                 mutex_unlock(&dev->struct_mutex);
13373         }
13374 }
13375
13376 int
13377 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13378 {
13379         int max_scale;
13380         struct drm_device *dev;
13381         struct drm_i915_private *dev_priv;
13382         int crtc_clock, cdclk;
13383
13384         if (!intel_crtc || !crtc_state)
13385                 return DRM_PLANE_HELPER_NO_SCALING;
13386
13387         dev = intel_crtc->base.dev;
13388         dev_priv = dev->dev_private;
13389         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13390         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13391
13392         if (!crtc_clock || !cdclk)
13393                 return DRM_PLANE_HELPER_NO_SCALING;
13394
13395         /*
13396          * skl max scale is lower of:
13397          *    close to 3 but not 3, -1 is for that purpose
13398          *            or
13399          *    cdclk/crtc_clock
13400          */
13401         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13402
13403         return max_scale;
13404 }
13405
13406 static int
13407 intel_check_primary_plane(struct drm_plane *plane,
13408                           struct intel_crtc_state *crtc_state,
13409                           struct intel_plane_state *state)
13410 {
13411         struct drm_crtc *crtc = state->base.crtc;
13412         struct drm_framebuffer *fb = state->base.fb;
13413         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13414         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13415         bool can_position = false;
13416
13417         /* use scaler when colorkey is not required */
13418         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13419             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13420                 min_scale = 1;
13421                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13422                 can_position = true;
13423         }
13424
13425         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13426                                              &state->dst, &state->clip,
13427                                              min_scale, max_scale,
13428                                              can_position, true,
13429                                              &state->visible);
13430 }
13431
13432 static void
13433 intel_commit_primary_plane(struct drm_plane *plane,
13434                            struct intel_plane_state *state)
13435 {
13436         struct drm_crtc *crtc = state->base.crtc;
13437         struct drm_framebuffer *fb = state->base.fb;
13438         struct drm_device *dev = plane->dev;
13439         struct drm_i915_private *dev_priv = dev->dev_private;
13440         struct intel_crtc *intel_crtc;
13441         struct drm_rect *src = &state->src;
13442
13443         crtc = crtc ? crtc : plane->crtc;
13444         intel_crtc = to_intel_crtc(crtc);
13445
13446         plane->fb = fb;
13447         crtc->x = src->x1 >> 16;
13448         crtc->y = src->y1 >> 16;
13449
13450         if (!crtc->state->active)
13451                 return;
13452
13453         if (state->visible)
13454                 /* FIXME: kill this fastboot hack */
13455                 intel_update_pipe_size(intel_crtc);
13456
13457         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13458 }
13459
13460 static void
13461 intel_disable_primary_plane(struct drm_plane *plane,
13462                             struct drm_crtc *crtc)
13463 {
13464         struct drm_device *dev = plane->dev;
13465         struct drm_i915_private *dev_priv = dev->dev_private;
13466
13467         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13468 }
13469
13470 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13471                                     struct drm_crtc_state *old_crtc_state)
13472 {
13473         struct drm_device *dev = crtc->dev;
13474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13475
13476         if (intel_crtc->atomic.update_wm_pre)
13477                 intel_update_watermarks(crtc);
13478
13479         /* Perform vblank evasion around commit operation */
13480         if (crtc->state->active)
13481                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13482
13483         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13484                 skl_detach_scalers(intel_crtc);
13485 }
13486
13487 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13488                                      struct drm_crtc_state *old_crtc_state)
13489 {
13490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13491
13492         if (crtc->state->active)
13493                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13494 }
13495
13496 /**
13497  * intel_plane_destroy - destroy a plane
13498  * @plane: plane to destroy
13499  *
13500  * Common destruction function for all types of planes (primary, cursor,
13501  * sprite).
13502  */
13503 void intel_plane_destroy(struct drm_plane *plane)
13504 {
13505         struct intel_plane *intel_plane = to_intel_plane(plane);
13506         drm_plane_cleanup(plane);
13507         kfree(intel_plane);
13508 }
13509
13510 const struct drm_plane_funcs intel_plane_funcs = {
13511         .update_plane = drm_atomic_helper_update_plane,
13512         .disable_plane = drm_atomic_helper_disable_plane,
13513         .destroy = intel_plane_destroy,
13514         .set_property = drm_atomic_helper_plane_set_property,
13515         .atomic_get_property = intel_plane_atomic_get_property,
13516         .atomic_set_property = intel_plane_atomic_set_property,
13517         .atomic_duplicate_state = intel_plane_duplicate_state,
13518         .atomic_destroy_state = intel_plane_destroy_state,
13519
13520 };
13521
13522 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13523                                                     int pipe)
13524 {
13525         struct intel_plane *primary;
13526         struct intel_plane_state *state;
13527         const uint32_t *intel_primary_formats;
13528         int num_formats;
13529
13530         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13531         if (primary == NULL)
13532                 return NULL;
13533
13534         state = intel_create_plane_state(&primary->base);
13535         if (!state) {
13536                 kfree(primary);
13537                 return NULL;
13538         }
13539         primary->base.state = &state->base;
13540
13541         primary->can_scale = false;
13542         primary->max_downscale = 1;
13543         if (INTEL_INFO(dev)->gen >= 9) {
13544                 primary->can_scale = true;
13545                 state->scaler_id = -1;
13546         }
13547         primary->pipe = pipe;
13548         primary->plane = pipe;
13549         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13550         primary->check_plane = intel_check_primary_plane;
13551         primary->commit_plane = intel_commit_primary_plane;
13552         primary->disable_plane = intel_disable_primary_plane;
13553         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13554                 primary->plane = !pipe;
13555
13556         if (INTEL_INFO(dev)->gen >= 9) {
13557                 intel_primary_formats = skl_primary_formats;
13558                 num_formats = ARRAY_SIZE(skl_primary_formats);
13559         } else if (INTEL_INFO(dev)->gen >= 4) {
13560                 intel_primary_formats = i965_primary_formats;
13561                 num_formats = ARRAY_SIZE(i965_primary_formats);
13562         } else {
13563                 intel_primary_formats = i8xx_primary_formats;
13564                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13565         }
13566
13567         drm_universal_plane_init(dev, &primary->base, 0,
13568                                  &intel_plane_funcs,
13569                                  intel_primary_formats, num_formats,
13570                                  DRM_PLANE_TYPE_PRIMARY);
13571
13572         if (INTEL_INFO(dev)->gen >= 4)
13573                 intel_create_rotation_property(dev, primary);
13574
13575         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13576
13577         return &primary->base;
13578 }
13579
13580 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13581 {
13582         if (!dev->mode_config.rotation_property) {
13583                 unsigned long flags = BIT(DRM_ROTATE_0) |
13584                         BIT(DRM_ROTATE_180);
13585
13586                 if (INTEL_INFO(dev)->gen >= 9)
13587                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13588
13589                 dev->mode_config.rotation_property =
13590                         drm_mode_create_rotation_property(dev, flags);
13591         }
13592         if (dev->mode_config.rotation_property)
13593                 drm_object_attach_property(&plane->base.base,
13594                                 dev->mode_config.rotation_property,
13595                                 plane->base.state->rotation);
13596 }
13597
13598 static int
13599 intel_check_cursor_plane(struct drm_plane *plane,
13600                          struct intel_crtc_state *crtc_state,
13601                          struct intel_plane_state *state)
13602 {
13603         struct drm_crtc *crtc = crtc_state->base.crtc;
13604         struct drm_framebuffer *fb = state->base.fb;
13605         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13606         unsigned stride;
13607         int ret;
13608
13609         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13610                                             &state->dst, &state->clip,
13611                                             DRM_PLANE_HELPER_NO_SCALING,
13612                                             DRM_PLANE_HELPER_NO_SCALING,
13613                                             true, true, &state->visible);
13614         if (ret)
13615                 return ret;
13616
13617         /* if we want to turn off the cursor ignore width and height */
13618         if (!obj)
13619                 return 0;
13620
13621         /* Check for which cursor types we support */
13622         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13623                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13624                           state->base.crtc_w, state->base.crtc_h);
13625                 return -EINVAL;
13626         }
13627
13628         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13629         if (obj->base.size < stride * state->base.crtc_h) {
13630                 DRM_DEBUG_KMS("buffer is too small\n");
13631                 return -ENOMEM;
13632         }
13633
13634         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13635                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13636                 return -EINVAL;
13637         }
13638
13639         return 0;
13640 }
13641
13642 static void
13643 intel_disable_cursor_plane(struct drm_plane *plane,
13644                            struct drm_crtc *crtc)
13645 {
13646         intel_crtc_update_cursor(crtc, false);
13647 }
13648
13649 static void
13650 intel_commit_cursor_plane(struct drm_plane *plane,
13651                           struct intel_plane_state *state)
13652 {
13653         struct drm_crtc *crtc = state->base.crtc;
13654         struct drm_device *dev = plane->dev;
13655         struct intel_crtc *intel_crtc;
13656         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13657         uint32_t addr;
13658
13659         crtc = crtc ? crtc : plane->crtc;
13660         intel_crtc = to_intel_crtc(crtc);
13661
13662         plane->fb = state->base.fb;
13663         crtc->cursor_x = state->base.crtc_x;
13664         crtc->cursor_y = state->base.crtc_y;
13665
13666         if (intel_crtc->cursor_bo == obj)
13667                 goto update;
13668
13669         if (!obj)
13670                 addr = 0;
13671         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13672                 addr = i915_gem_obj_ggtt_offset(obj);
13673         else
13674                 addr = obj->phys_handle->busaddr;
13675
13676         intel_crtc->cursor_addr = addr;
13677         intel_crtc->cursor_bo = obj;
13678
13679 update:
13680         if (crtc->state->active)
13681                 intel_crtc_update_cursor(crtc, state->visible);
13682 }
13683
13684 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13685                                                    int pipe)
13686 {
13687         struct intel_plane *cursor;
13688         struct intel_plane_state *state;
13689
13690         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13691         if (cursor == NULL)
13692                 return NULL;
13693
13694         state = intel_create_plane_state(&cursor->base);
13695         if (!state) {
13696                 kfree(cursor);
13697                 return NULL;
13698         }
13699         cursor->base.state = &state->base;
13700
13701         cursor->can_scale = false;
13702         cursor->max_downscale = 1;
13703         cursor->pipe = pipe;
13704         cursor->plane = pipe;
13705         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13706         cursor->check_plane = intel_check_cursor_plane;
13707         cursor->commit_plane = intel_commit_cursor_plane;
13708         cursor->disable_plane = intel_disable_cursor_plane;
13709
13710         drm_universal_plane_init(dev, &cursor->base, 0,
13711                                  &intel_plane_funcs,
13712                                  intel_cursor_formats,
13713                                  ARRAY_SIZE(intel_cursor_formats),
13714                                  DRM_PLANE_TYPE_CURSOR);
13715
13716         if (INTEL_INFO(dev)->gen >= 4) {
13717                 if (!dev->mode_config.rotation_property)
13718                         dev->mode_config.rotation_property =
13719                                 drm_mode_create_rotation_property(dev,
13720                                                         BIT(DRM_ROTATE_0) |
13721                                                         BIT(DRM_ROTATE_180));
13722                 if (dev->mode_config.rotation_property)
13723                         drm_object_attach_property(&cursor->base.base,
13724                                 dev->mode_config.rotation_property,
13725                                 state->base.rotation);
13726         }
13727
13728         if (INTEL_INFO(dev)->gen >=9)
13729                 state->scaler_id = -1;
13730
13731         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13732
13733         return &cursor->base;
13734 }
13735
13736 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13737         struct intel_crtc_state *crtc_state)
13738 {
13739         int i;
13740         struct intel_scaler *intel_scaler;
13741         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13742
13743         for (i = 0; i < intel_crtc->num_scalers; i++) {
13744                 intel_scaler = &scaler_state->scalers[i];
13745                 intel_scaler->in_use = 0;
13746                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13747         }
13748
13749         scaler_state->scaler_id = -1;
13750 }
13751
13752 static void intel_crtc_init(struct drm_device *dev, int pipe)
13753 {
13754         struct drm_i915_private *dev_priv = dev->dev_private;
13755         struct intel_crtc *intel_crtc;
13756         struct intel_crtc_state *crtc_state = NULL;
13757         struct drm_plane *primary = NULL;
13758         struct drm_plane *cursor = NULL;
13759         int i, ret;
13760
13761         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13762         if (intel_crtc == NULL)
13763                 return;
13764
13765         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13766         if (!crtc_state)
13767                 goto fail;
13768         intel_crtc->config = crtc_state;
13769         intel_crtc->base.state = &crtc_state->base;
13770         crtc_state->base.crtc = &intel_crtc->base;
13771
13772         /* initialize shared scalers */
13773         if (INTEL_INFO(dev)->gen >= 9) {
13774                 if (pipe == PIPE_C)
13775                         intel_crtc->num_scalers = 1;
13776                 else
13777                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13778
13779                 skl_init_scalers(dev, intel_crtc, crtc_state);
13780         }
13781
13782         primary = intel_primary_plane_create(dev, pipe);
13783         if (!primary)
13784                 goto fail;
13785
13786         cursor = intel_cursor_plane_create(dev, pipe);
13787         if (!cursor)
13788                 goto fail;
13789
13790         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13791                                         cursor, &intel_crtc_funcs);
13792         if (ret)
13793                 goto fail;
13794
13795         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13796         for (i = 0; i < 256; i++) {
13797                 intel_crtc->lut_r[i] = i;
13798                 intel_crtc->lut_g[i] = i;
13799                 intel_crtc->lut_b[i] = i;
13800         }
13801
13802         /*
13803          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13804          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13805          */
13806         intel_crtc->pipe = pipe;
13807         intel_crtc->plane = pipe;
13808         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13809                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13810                 intel_crtc->plane = !pipe;
13811         }
13812
13813         intel_crtc->cursor_base = ~0;
13814         intel_crtc->cursor_cntl = ~0;
13815         intel_crtc->cursor_size = ~0;
13816
13817         intel_crtc->wm.cxsr_allowed = true;
13818
13819         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13820                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13821         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13822         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13823
13824         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13825
13826         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13827         return;
13828
13829 fail:
13830         if (primary)
13831                 drm_plane_cleanup(primary);
13832         if (cursor)
13833                 drm_plane_cleanup(cursor);
13834         kfree(crtc_state);
13835         kfree(intel_crtc);
13836 }
13837
13838 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13839 {
13840         struct drm_encoder *encoder = connector->base.encoder;
13841         struct drm_device *dev = connector->base.dev;
13842
13843         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13844
13845         if (!encoder || WARN_ON(!encoder->crtc))
13846                 return INVALID_PIPE;
13847
13848         return to_intel_crtc(encoder->crtc)->pipe;
13849 }
13850
13851 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13852                                 struct drm_file *file)
13853 {
13854         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13855         struct drm_crtc *drmmode_crtc;
13856         struct intel_crtc *crtc;
13857
13858         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13859
13860         if (!drmmode_crtc) {
13861                 DRM_ERROR("no such CRTC id\n");
13862                 return -ENOENT;
13863         }
13864
13865         crtc = to_intel_crtc(drmmode_crtc);
13866         pipe_from_crtc_id->pipe = crtc->pipe;
13867
13868         return 0;
13869 }
13870
13871 static int intel_encoder_clones(struct intel_encoder *encoder)
13872 {
13873         struct drm_device *dev = encoder->base.dev;
13874         struct intel_encoder *source_encoder;
13875         int index_mask = 0;
13876         int entry = 0;
13877
13878         for_each_intel_encoder(dev, source_encoder) {
13879                 if (encoders_cloneable(encoder, source_encoder))
13880                         index_mask |= (1 << entry);
13881
13882                 entry++;
13883         }
13884
13885         return index_mask;
13886 }
13887
13888 static bool has_edp_a(struct drm_device *dev)
13889 {
13890         struct drm_i915_private *dev_priv = dev->dev_private;
13891
13892         if (!IS_MOBILE(dev))
13893                 return false;
13894
13895         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13896                 return false;
13897
13898         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13899                 return false;
13900
13901         return true;
13902 }
13903
13904 static bool intel_crt_present(struct drm_device *dev)
13905 {
13906         struct drm_i915_private *dev_priv = dev->dev_private;
13907
13908         if (INTEL_INFO(dev)->gen >= 9)
13909                 return false;
13910
13911         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13912                 return false;
13913
13914         if (IS_CHERRYVIEW(dev))
13915                 return false;
13916
13917         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13918                 return false;
13919
13920         return true;
13921 }
13922
13923 static void intel_setup_outputs(struct drm_device *dev)
13924 {
13925         struct drm_i915_private *dev_priv = dev->dev_private;
13926         struct intel_encoder *encoder;
13927         bool dpd_is_edp = false;
13928
13929         intel_lvds_init(dev);
13930
13931         if (intel_crt_present(dev))
13932                 intel_crt_init(dev);
13933
13934         if (IS_BROXTON(dev)) {
13935                 /*
13936                  * FIXME: Broxton doesn't support port detection via the
13937                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13938                  * detect the ports.
13939                  */
13940                 intel_ddi_init(dev, PORT_A);
13941                 intel_ddi_init(dev, PORT_B);
13942                 intel_ddi_init(dev, PORT_C);
13943         } else if (HAS_DDI(dev)) {
13944                 int found;
13945
13946                 /*
13947                  * Haswell uses DDI functions to detect digital outputs.
13948                  * On SKL pre-D0 the strap isn't connected, so we assume
13949                  * it's there.
13950                  */
13951                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13952                 /* WaIgnoreDDIAStrap: skl */
13953                 if (found || IS_SKYLAKE(dev))
13954                         intel_ddi_init(dev, PORT_A);
13955
13956                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13957                  * register */
13958                 found = I915_READ(SFUSE_STRAP);
13959
13960                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13961                         intel_ddi_init(dev, PORT_B);
13962                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13963                         intel_ddi_init(dev, PORT_C);
13964                 if (found & SFUSE_STRAP_DDID_DETECTED)
13965                         intel_ddi_init(dev, PORT_D);
13966         } else if (HAS_PCH_SPLIT(dev)) {
13967                 int found;
13968                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13969
13970                 if (has_edp_a(dev))
13971                         intel_dp_init(dev, DP_A, PORT_A);
13972
13973                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13974                         /* PCH SDVOB multiplex with HDMIB */
13975                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13976                         if (!found)
13977                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13978                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13979                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13980                 }
13981
13982                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13983                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13984
13985                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13986                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13987
13988                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13989                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13990
13991                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13992                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13993         } else if (IS_VALLEYVIEW(dev)) {
13994                 /*
13995                  * The DP_DETECTED bit is the latched state of the DDC
13996                  * SDA pin at boot. However since eDP doesn't require DDC
13997                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13998                  * eDP ports may have been muxed to an alternate function.
13999                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14000                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14001                  * detect eDP ports.
14002                  */
14003                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14004                     !intel_dp_is_edp(dev, PORT_B))
14005                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14006                                         PORT_B);
14007                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14008                     intel_dp_is_edp(dev, PORT_B))
14009                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14010
14011                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14012                     !intel_dp_is_edp(dev, PORT_C))
14013                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14014                                         PORT_C);
14015                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14016                     intel_dp_is_edp(dev, PORT_C))
14017                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14018
14019                 if (IS_CHERRYVIEW(dev)) {
14020                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14021                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14022                                                 PORT_D);
14023                         /* eDP not supported on port D, so don't check VBT */
14024                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14025                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14026                 }
14027
14028                 intel_dsi_init(dev);
14029         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14030                 bool found = false;
14031
14032                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14033                         DRM_DEBUG_KMS("probing SDVOB\n");
14034                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14035                         if (!found && IS_G4X(dev)) {
14036                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14037                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14038                         }
14039
14040                         if (!found && IS_G4X(dev))
14041                                 intel_dp_init(dev, DP_B, PORT_B);
14042                 }
14043
14044                 /* Before G4X SDVOC doesn't have its own detect register */
14045
14046                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14047                         DRM_DEBUG_KMS("probing SDVOC\n");
14048                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14049                 }
14050
14051                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14052
14053                         if (IS_G4X(dev)) {
14054                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14055                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14056                         }
14057                         if (IS_G4X(dev))
14058                                 intel_dp_init(dev, DP_C, PORT_C);
14059                 }
14060
14061                 if (IS_G4X(dev) &&
14062                     (I915_READ(DP_D) & DP_DETECTED))
14063                         intel_dp_init(dev, DP_D, PORT_D);
14064         } else if (IS_GEN2(dev))
14065                 intel_dvo_init(dev);
14066
14067         if (SUPPORTS_TV(dev))
14068                 intel_tv_init(dev);
14069
14070         intel_psr_init(dev);
14071
14072         for_each_intel_encoder(dev, encoder) {
14073                 encoder->base.possible_crtcs = encoder->crtc_mask;
14074                 encoder->base.possible_clones =
14075                         intel_encoder_clones(encoder);
14076         }
14077
14078         intel_init_pch_refclk(dev);
14079
14080         drm_helper_move_panel_connectors_to_head(dev);
14081 }
14082
14083 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14084 {
14085         struct drm_device *dev = fb->dev;
14086         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14087
14088         drm_framebuffer_cleanup(fb);
14089         mutex_lock(&dev->struct_mutex);
14090         WARN_ON(!intel_fb->obj->framebuffer_references--);
14091         drm_gem_object_unreference(&intel_fb->obj->base);
14092         mutex_unlock(&dev->struct_mutex);
14093         kfree(intel_fb);
14094 }
14095
14096 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14097                                                 struct drm_file *file,
14098                                                 unsigned int *handle)
14099 {
14100         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14101         struct drm_i915_gem_object *obj = intel_fb->obj;
14102
14103         return drm_gem_handle_create(file, &obj->base, handle);
14104 }
14105
14106 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14107                                         struct drm_file *file,
14108                                         unsigned flags, unsigned color,
14109                                         struct drm_clip_rect *clips,
14110                                         unsigned num_clips)
14111 {
14112         struct drm_device *dev = fb->dev;
14113         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14114         struct drm_i915_gem_object *obj = intel_fb->obj;
14115
14116         mutex_lock(&dev->struct_mutex);
14117         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14118         mutex_unlock(&dev->struct_mutex);
14119
14120         return 0;
14121 }
14122
14123 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14124         .destroy = intel_user_framebuffer_destroy,
14125         .create_handle = intel_user_framebuffer_create_handle,
14126         .dirty = intel_user_framebuffer_dirty,
14127 };
14128
14129 static
14130 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14131                          uint32_t pixel_format)
14132 {
14133         u32 gen = INTEL_INFO(dev)->gen;
14134
14135         if (gen >= 9) {
14136                 /* "The stride in bytes must not exceed the of the size of 8K
14137                  *  pixels and 32K bytes."
14138                  */
14139                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14140         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14141                 return 32*1024;
14142         } else if (gen >= 4) {
14143                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14144                         return 16*1024;
14145                 else
14146                         return 32*1024;
14147         } else if (gen >= 3) {
14148                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14149                         return 8*1024;
14150                 else
14151                         return 16*1024;
14152         } else {
14153                 /* XXX DSPC is limited to 4k tiled */
14154                 return 8*1024;
14155         }
14156 }
14157
14158 static int intel_framebuffer_init(struct drm_device *dev,
14159                                   struct intel_framebuffer *intel_fb,
14160                                   struct drm_mode_fb_cmd2 *mode_cmd,
14161                                   struct drm_i915_gem_object *obj)
14162 {
14163         unsigned int aligned_height;
14164         int ret;
14165         u32 pitch_limit, stride_alignment;
14166
14167         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14168
14169         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14170                 /* Enforce that fb modifier and tiling mode match, but only for
14171                  * X-tiled. This is needed for FBC. */
14172                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14173                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14174                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14175                         return -EINVAL;
14176                 }
14177         } else {
14178                 if (obj->tiling_mode == I915_TILING_X)
14179                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14180                 else if (obj->tiling_mode == I915_TILING_Y) {
14181                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14182                         return -EINVAL;
14183                 }
14184         }
14185
14186         /* Passed in modifier sanity checking. */
14187         switch (mode_cmd->modifier[0]) {
14188         case I915_FORMAT_MOD_Y_TILED:
14189         case I915_FORMAT_MOD_Yf_TILED:
14190                 if (INTEL_INFO(dev)->gen < 9) {
14191                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14192                                   mode_cmd->modifier[0]);
14193                         return -EINVAL;
14194                 }
14195         case DRM_FORMAT_MOD_NONE:
14196         case I915_FORMAT_MOD_X_TILED:
14197                 break;
14198         default:
14199                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14200                           mode_cmd->modifier[0]);
14201                 return -EINVAL;
14202         }
14203
14204         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14205                                                      mode_cmd->pixel_format);
14206         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14207                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14208                           mode_cmd->pitches[0], stride_alignment);
14209                 return -EINVAL;
14210         }
14211
14212         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14213                                            mode_cmd->pixel_format);
14214         if (mode_cmd->pitches[0] > pitch_limit) {
14215                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14216                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14217                           "tiled" : "linear",
14218                           mode_cmd->pitches[0], pitch_limit);
14219                 return -EINVAL;
14220         }
14221
14222         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14223             mode_cmd->pitches[0] != obj->stride) {
14224                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14225                           mode_cmd->pitches[0], obj->stride);
14226                 return -EINVAL;
14227         }
14228
14229         /* Reject formats not supported by any plane early. */
14230         switch (mode_cmd->pixel_format) {
14231         case DRM_FORMAT_C8:
14232         case DRM_FORMAT_RGB565:
14233         case DRM_FORMAT_XRGB8888:
14234         case DRM_FORMAT_ARGB8888:
14235                 break;
14236         case DRM_FORMAT_XRGB1555:
14237                 if (INTEL_INFO(dev)->gen > 3) {
14238                         DRM_DEBUG("unsupported pixel format: %s\n",
14239                                   drm_get_format_name(mode_cmd->pixel_format));
14240                         return -EINVAL;
14241                 }
14242                 break;
14243         case DRM_FORMAT_ABGR8888:
14244                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14245                         DRM_DEBUG("unsupported pixel format: %s\n",
14246                                   drm_get_format_name(mode_cmd->pixel_format));
14247                         return -EINVAL;
14248                 }
14249                 break;
14250         case DRM_FORMAT_XBGR8888:
14251         case DRM_FORMAT_XRGB2101010:
14252         case DRM_FORMAT_XBGR2101010:
14253                 if (INTEL_INFO(dev)->gen < 4) {
14254                         DRM_DEBUG("unsupported pixel format: %s\n",
14255                                   drm_get_format_name(mode_cmd->pixel_format));
14256                         return -EINVAL;
14257                 }
14258                 break;
14259         case DRM_FORMAT_ABGR2101010:
14260                 if (!IS_VALLEYVIEW(dev)) {
14261                         DRM_DEBUG("unsupported pixel format: %s\n",
14262                                   drm_get_format_name(mode_cmd->pixel_format));
14263                         return -EINVAL;
14264                 }
14265                 break;
14266         case DRM_FORMAT_YUYV:
14267         case DRM_FORMAT_UYVY:
14268         case DRM_FORMAT_YVYU:
14269         case DRM_FORMAT_VYUY:
14270                 if (INTEL_INFO(dev)->gen < 5) {
14271                         DRM_DEBUG("unsupported pixel format: %s\n",
14272                                   drm_get_format_name(mode_cmd->pixel_format));
14273                         return -EINVAL;
14274                 }
14275                 break;
14276         default:
14277                 DRM_DEBUG("unsupported pixel format: %s\n",
14278                           drm_get_format_name(mode_cmd->pixel_format));
14279                 return -EINVAL;
14280         }
14281
14282         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14283         if (mode_cmd->offsets[0] != 0)
14284                 return -EINVAL;
14285
14286         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14287                                                mode_cmd->pixel_format,
14288                                                mode_cmd->modifier[0]);
14289         /* FIXME drm helper for size checks (especially planar formats)? */
14290         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14291                 return -EINVAL;
14292
14293         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14294         intel_fb->obj = obj;
14295         intel_fb->obj->framebuffer_references++;
14296
14297         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14298         if (ret) {
14299                 DRM_ERROR("framebuffer init failed %d\n", ret);
14300                 return ret;
14301         }
14302
14303         return 0;
14304 }
14305
14306 static struct drm_framebuffer *
14307 intel_user_framebuffer_create(struct drm_device *dev,
14308                               struct drm_file *filp,
14309                               struct drm_mode_fb_cmd2 *mode_cmd)
14310 {
14311         struct drm_i915_gem_object *obj;
14312
14313         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14314                                                 mode_cmd->handles[0]));
14315         if (&obj->base == NULL)
14316                 return ERR_PTR(-ENOENT);
14317
14318         return intel_framebuffer_create(dev, mode_cmd, obj);
14319 }
14320
14321 #ifndef CONFIG_DRM_I915_FBDEV
14322 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14323 {
14324 }
14325 #endif
14326
14327 static const struct drm_mode_config_funcs intel_mode_funcs = {
14328         .fb_create = intel_user_framebuffer_create,
14329         .output_poll_changed = intel_fbdev_output_poll_changed,
14330         .atomic_check = intel_atomic_check,
14331         .atomic_commit = intel_atomic_commit,
14332         .atomic_state_alloc = intel_atomic_state_alloc,
14333         .atomic_state_clear = intel_atomic_state_clear,
14334 };
14335
14336 /* Set up chip specific display functions */
14337 static void intel_init_display(struct drm_device *dev)
14338 {
14339         struct drm_i915_private *dev_priv = dev->dev_private;
14340
14341         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14342                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14343         else if (IS_CHERRYVIEW(dev))
14344                 dev_priv->display.find_dpll = chv_find_best_dpll;
14345         else if (IS_VALLEYVIEW(dev))
14346                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14347         else if (IS_PINEVIEW(dev))
14348                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14349         else
14350                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14351
14352         if (INTEL_INFO(dev)->gen >= 9) {
14353                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14354                 dev_priv->display.get_initial_plane_config =
14355                         skylake_get_initial_plane_config;
14356                 dev_priv->display.crtc_compute_clock =
14357                         haswell_crtc_compute_clock;
14358                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14359                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14360                 dev_priv->display.update_primary_plane =
14361                         skylake_update_primary_plane;
14362         } else if (HAS_DDI(dev)) {
14363                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14364                 dev_priv->display.get_initial_plane_config =
14365                         ironlake_get_initial_plane_config;
14366                 dev_priv->display.crtc_compute_clock =
14367                         haswell_crtc_compute_clock;
14368                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14369                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14370                 dev_priv->display.update_primary_plane =
14371                         ironlake_update_primary_plane;
14372         } else if (HAS_PCH_SPLIT(dev)) {
14373                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14374                 dev_priv->display.get_initial_plane_config =
14375                         ironlake_get_initial_plane_config;
14376                 dev_priv->display.crtc_compute_clock =
14377                         ironlake_crtc_compute_clock;
14378                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14379                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14380                 dev_priv->display.update_primary_plane =
14381                         ironlake_update_primary_plane;
14382         } else if (IS_VALLEYVIEW(dev)) {
14383                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14384                 dev_priv->display.get_initial_plane_config =
14385                         i9xx_get_initial_plane_config;
14386                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14387                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14388                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14389                 dev_priv->display.update_primary_plane =
14390                         i9xx_update_primary_plane;
14391         } else {
14392                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14393                 dev_priv->display.get_initial_plane_config =
14394                         i9xx_get_initial_plane_config;
14395                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14396                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14397                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14398                 dev_priv->display.update_primary_plane =
14399                         i9xx_update_primary_plane;
14400         }
14401
14402         /* Returns the core display clock speed */
14403         if (IS_SKYLAKE(dev))
14404                 dev_priv->display.get_display_clock_speed =
14405                         skylake_get_display_clock_speed;
14406         else if (IS_BROXTON(dev))
14407                 dev_priv->display.get_display_clock_speed =
14408                         broxton_get_display_clock_speed;
14409         else if (IS_BROADWELL(dev))
14410                 dev_priv->display.get_display_clock_speed =
14411                         broadwell_get_display_clock_speed;
14412         else if (IS_HASWELL(dev))
14413                 dev_priv->display.get_display_clock_speed =
14414                         haswell_get_display_clock_speed;
14415         else if (IS_VALLEYVIEW(dev))
14416                 dev_priv->display.get_display_clock_speed =
14417                         valleyview_get_display_clock_speed;
14418         else if (IS_GEN5(dev))
14419                 dev_priv->display.get_display_clock_speed =
14420                         ilk_get_display_clock_speed;
14421         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14422                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14423                 dev_priv->display.get_display_clock_speed =
14424                         i945_get_display_clock_speed;
14425         else if (IS_GM45(dev))
14426                 dev_priv->display.get_display_clock_speed =
14427                         gm45_get_display_clock_speed;
14428         else if (IS_CRESTLINE(dev))
14429                 dev_priv->display.get_display_clock_speed =
14430                         i965gm_get_display_clock_speed;
14431         else if (IS_PINEVIEW(dev))
14432                 dev_priv->display.get_display_clock_speed =
14433                         pnv_get_display_clock_speed;
14434         else if (IS_G33(dev) || IS_G4X(dev))
14435                 dev_priv->display.get_display_clock_speed =
14436                         g33_get_display_clock_speed;
14437         else if (IS_I915G(dev))
14438                 dev_priv->display.get_display_clock_speed =
14439                         i915_get_display_clock_speed;
14440         else if (IS_I945GM(dev) || IS_845G(dev))
14441                 dev_priv->display.get_display_clock_speed =
14442                         i9xx_misc_get_display_clock_speed;
14443         else if (IS_PINEVIEW(dev))
14444                 dev_priv->display.get_display_clock_speed =
14445                         pnv_get_display_clock_speed;
14446         else if (IS_I915GM(dev))
14447                 dev_priv->display.get_display_clock_speed =
14448                         i915gm_get_display_clock_speed;
14449         else if (IS_I865G(dev))
14450                 dev_priv->display.get_display_clock_speed =
14451                         i865_get_display_clock_speed;
14452         else if (IS_I85X(dev))
14453                 dev_priv->display.get_display_clock_speed =
14454                         i85x_get_display_clock_speed;
14455         else { /* 830 */
14456                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14457                 dev_priv->display.get_display_clock_speed =
14458                         i830_get_display_clock_speed;
14459         }
14460
14461         if (IS_GEN5(dev)) {
14462                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14463         } else if (IS_GEN6(dev)) {
14464                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14465         } else if (IS_IVYBRIDGE(dev)) {
14466                 /* FIXME: detect B0+ stepping and use auto training */
14467                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14468         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14469                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14470                 if (IS_BROADWELL(dev)) {
14471                         dev_priv->display.modeset_commit_cdclk =
14472                                 broadwell_modeset_commit_cdclk;
14473                         dev_priv->display.modeset_calc_cdclk =
14474                                 broadwell_modeset_calc_cdclk;
14475                 }
14476         } else if (IS_VALLEYVIEW(dev)) {
14477                 dev_priv->display.modeset_commit_cdclk =
14478                         valleyview_modeset_commit_cdclk;
14479                 dev_priv->display.modeset_calc_cdclk =
14480                         valleyview_modeset_calc_cdclk;
14481         } else if (IS_BROXTON(dev)) {
14482                 dev_priv->display.modeset_commit_cdclk =
14483                         broxton_modeset_commit_cdclk;
14484                 dev_priv->display.modeset_calc_cdclk =
14485                         broxton_modeset_calc_cdclk;
14486         }
14487
14488         switch (INTEL_INFO(dev)->gen) {
14489         case 2:
14490                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14491                 break;
14492
14493         case 3:
14494                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14495                 break;
14496
14497         case 4:
14498         case 5:
14499                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14500                 break;
14501
14502         case 6:
14503                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14504                 break;
14505         case 7:
14506         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14507                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14508                 break;
14509         case 9:
14510                 /* Drop through - unsupported since execlist only. */
14511         default:
14512                 /* Default just returns -ENODEV to indicate unsupported */
14513                 dev_priv->display.queue_flip = intel_default_queue_flip;
14514         }
14515
14516         intel_panel_init_backlight_funcs(dev);
14517
14518         mutex_init(&dev_priv->pps_mutex);
14519 }
14520
14521 /*
14522  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14523  * resume, or other times.  This quirk makes sure that's the case for
14524  * affected systems.
14525  */
14526 static void quirk_pipea_force(struct drm_device *dev)
14527 {
14528         struct drm_i915_private *dev_priv = dev->dev_private;
14529
14530         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14531         DRM_INFO("applying pipe a force quirk\n");
14532 }
14533
14534 static void quirk_pipeb_force(struct drm_device *dev)
14535 {
14536         struct drm_i915_private *dev_priv = dev->dev_private;
14537
14538         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14539         DRM_INFO("applying pipe b force quirk\n");
14540 }
14541
14542 /*
14543  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14544  */
14545 static void quirk_ssc_force_disable(struct drm_device *dev)
14546 {
14547         struct drm_i915_private *dev_priv = dev->dev_private;
14548         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14549         DRM_INFO("applying lvds SSC disable quirk\n");
14550 }
14551
14552 /*
14553  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14554  * brightness value
14555  */
14556 static void quirk_invert_brightness(struct drm_device *dev)
14557 {
14558         struct drm_i915_private *dev_priv = dev->dev_private;
14559         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14560         DRM_INFO("applying inverted panel brightness quirk\n");
14561 }
14562
14563 /* Some VBT's incorrectly indicate no backlight is present */
14564 static void quirk_backlight_present(struct drm_device *dev)
14565 {
14566         struct drm_i915_private *dev_priv = dev->dev_private;
14567         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14568         DRM_INFO("applying backlight present quirk\n");
14569 }
14570
14571 struct intel_quirk {
14572         int device;
14573         int subsystem_vendor;
14574         int subsystem_device;
14575         void (*hook)(struct drm_device *dev);
14576 };
14577
14578 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14579 struct intel_dmi_quirk {
14580         void (*hook)(struct drm_device *dev);
14581         const struct dmi_system_id (*dmi_id_list)[];
14582 };
14583
14584 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14585 {
14586         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14587         return 1;
14588 }
14589
14590 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14591         {
14592                 .dmi_id_list = &(const struct dmi_system_id[]) {
14593                         {
14594                                 .callback = intel_dmi_reverse_brightness,
14595                                 .ident = "NCR Corporation",
14596                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14597                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14598                                 },
14599                         },
14600                         { }  /* terminating entry */
14601                 },
14602                 .hook = quirk_invert_brightness,
14603         },
14604 };
14605
14606 static struct intel_quirk intel_quirks[] = {
14607         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14608         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14609
14610         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14611         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14612
14613         /* 830 needs to leave pipe A & dpll A up */
14614         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14615
14616         /* 830 needs to leave pipe B & dpll B up */
14617         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14618
14619         /* Lenovo U160 cannot use SSC on LVDS */
14620         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14621
14622         /* Sony Vaio Y cannot use SSC on LVDS */
14623         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14624
14625         /* Acer Aspire 5734Z must invert backlight brightness */
14626         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14627
14628         /* Acer/eMachines G725 */
14629         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14630
14631         /* Acer/eMachines e725 */
14632         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14633
14634         /* Acer/Packard Bell NCL20 */
14635         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14636
14637         /* Acer Aspire 4736Z */
14638         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14639
14640         /* Acer Aspire 5336 */
14641         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14642
14643         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14644         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14645
14646         /* Acer C720 Chromebook (Core i3 4005U) */
14647         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14648
14649         /* Apple Macbook 2,1 (Core 2 T7400) */
14650         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14651
14652         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14653         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14654
14655         /* HP Chromebook 14 (Celeron 2955U) */
14656         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14657
14658         /* Dell Chromebook 11 */
14659         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14660 };
14661
14662 static void intel_init_quirks(struct drm_device *dev)
14663 {
14664         struct pci_dev *d = dev->pdev;
14665         int i;
14666
14667         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14668                 struct intel_quirk *q = &intel_quirks[i];
14669
14670                 if (d->device == q->device &&
14671                     (d->subsystem_vendor == q->subsystem_vendor ||
14672                      q->subsystem_vendor == PCI_ANY_ID) &&
14673                     (d->subsystem_device == q->subsystem_device ||
14674                      q->subsystem_device == PCI_ANY_ID))
14675                         q->hook(dev);
14676         }
14677         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14678                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14679                         intel_dmi_quirks[i].hook(dev);
14680         }
14681 }
14682
14683 /* Disable the VGA plane that we never use */
14684 static void i915_disable_vga(struct drm_device *dev)
14685 {
14686         struct drm_i915_private *dev_priv = dev->dev_private;
14687         u8 sr1;
14688         u32 vga_reg = i915_vgacntrl_reg(dev);
14689
14690         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14691         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14692         outb(SR01, VGA_SR_INDEX);
14693         sr1 = inb(VGA_SR_DATA);
14694         outb(sr1 | 1<<5, VGA_SR_DATA);
14695         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14696         udelay(300);
14697
14698         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14699         POSTING_READ(vga_reg);
14700 }
14701
14702 void intel_modeset_init_hw(struct drm_device *dev)
14703 {
14704         intel_update_cdclk(dev);
14705         intel_prepare_ddi(dev);
14706         intel_init_clock_gating(dev);
14707         intel_enable_gt_powersave(dev);
14708 }
14709
14710 void intel_modeset_init(struct drm_device *dev)
14711 {
14712         struct drm_i915_private *dev_priv = dev->dev_private;
14713         int sprite, ret;
14714         enum pipe pipe;
14715         struct intel_crtc *crtc;
14716
14717         drm_mode_config_init(dev);
14718
14719         dev->mode_config.min_width = 0;
14720         dev->mode_config.min_height = 0;
14721
14722         dev->mode_config.preferred_depth = 24;
14723         dev->mode_config.prefer_shadow = 1;
14724
14725         dev->mode_config.allow_fb_modifiers = true;
14726
14727         dev->mode_config.funcs = &intel_mode_funcs;
14728
14729         intel_init_quirks(dev);
14730
14731         intel_init_pm(dev);
14732
14733         if (INTEL_INFO(dev)->num_pipes == 0)
14734                 return;
14735
14736         intel_init_display(dev);
14737         intel_init_audio(dev);
14738
14739         if (IS_GEN2(dev)) {
14740                 dev->mode_config.max_width = 2048;
14741                 dev->mode_config.max_height = 2048;
14742         } else if (IS_GEN3(dev)) {
14743                 dev->mode_config.max_width = 4096;
14744                 dev->mode_config.max_height = 4096;
14745         } else {
14746                 dev->mode_config.max_width = 8192;
14747                 dev->mode_config.max_height = 8192;
14748         }
14749
14750         if (IS_845G(dev) || IS_I865G(dev)) {
14751                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14752                 dev->mode_config.cursor_height = 1023;
14753         } else if (IS_GEN2(dev)) {
14754                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14755                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14756         } else {
14757                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14758                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14759         }
14760
14761         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14762
14763         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14764                       INTEL_INFO(dev)->num_pipes,
14765                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14766
14767         for_each_pipe(dev_priv, pipe) {
14768                 intel_crtc_init(dev, pipe);
14769                 for_each_sprite(dev_priv, pipe, sprite) {
14770                         ret = intel_plane_init(dev, pipe, sprite);
14771                         if (ret)
14772                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14773                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14774                 }
14775         }
14776
14777         intel_init_dpio(dev);
14778
14779         intel_shared_dpll_init(dev);
14780
14781         /* Just disable it once at startup */
14782         i915_disable_vga(dev);
14783         intel_setup_outputs(dev);
14784
14785         /* Just in case the BIOS is doing something questionable. */
14786         intel_fbc_disable(dev_priv);
14787
14788         drm_modeset_lock_all(dev);
14789         intel_modeset_setup_hw_state(dev);
14790         drm_modeset_unlock_all(dev);
14791
14792         for_each_intel_crtc(dev, crtc) {
14793                 struct intel_initial_plane_config plane_config = {};
14794
14795                 if (!crtc->active)
14796                         continue;
14797
14798                 /*
14799                  * Note that reserving the BIOS fb up front prevents us
14800                  * from stuffing other stolen allocations like the ring
14801                  * on top.  This prevents some ugliness at boot time, and
14802                  * can even allow for smooth boot transitions if the BIOS
14803                  * fb is large enough for the active pipe configuration.
14804                  */
14805                 dev_priv->display.get_initial_plane_config(crtc,
14806                                                            &plane_config);
14807
14808                 /*
14809                  * If the fb is shared between multiple heads, we'll
14810                  * just get the first one.
14811                  */
14812                 intel_find_initial_plane_obj(crtc, &plane_config);
14813         }
14814 }
14815
14816 static void intel_enable_pipe_a(struct drm_device *dev)
14817 {
14818         struct intel_connector *connector;
14819         struct drm_connector *crt = NULL;
14820         struct intel_load_detect_pipe load_detect_temp;
14821         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14822
14823         /* We can't just switch on the pipe A, we need to set things up with a
14824          * proper mode and output configuration. As a gross hack, enable pipe A
14825          * by enabling the load detect pipe once. */
14826         for_each_intel_connector(dev, connector) {
14827                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14828                         crt = &connector->base;
14829                         break;
14830                 }
14831         }
14832
14833         if (!crt)
14834                 return;
14835
14836         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14837                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14838 }
14839
14840 static bool
14841 intel_check_plane_mapping(struct intel_crtc *crtc)
14842 {
14843         struct drm_device *dev = crtc->base.dev;
14844         struct drm_i915_private *dev_priv = dev->dev_private;
14845         u32 reg, val;
14846
14847         if (INTEL_INFO(dev)->num_pipes == 1)
14848                 return true;
14849
14850         reg = DSPCNTR(!crtc->plane);
14851         val = I915_READ(reg);
14852
14853         if ((val & DISPLAY_PLANE_ENABLE) &&
14854             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14855                 return false;
14856
14857         return true;
14858 }
14859
14860 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14861 {
14862         struct drm_device *dev = crtc->base.dev;
14863         struct drm_i915_private *dev_priv = dev->dev_private;
14864         struct intel_encoder *encoder;
14865         u32 reg;
14866         bool enable;
14867
14868         /* Clear any frame start delays used for debugging left by the BIOS */
14869         reg = PIPECONF(crtc->config->cpu_transcoder);
14870         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14871
14872         /* restore vblank interrupts to correct state */
14873         drm_crtc_vblank_reset(&crtc->base);
14874         if (crtc->active) {
14875                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14876                 update_scanline_offset(crtc);
14877                 drm_crtc_vblank_on(&crtc->base);
14878         }
14879
14880         /* We need to sanitize the plane -> pipe mapping first because this will
14881          * disable the crtc (and hence change the state) if it is wrong. Note
14882          * that gen4+ has a fixed plane -> pipe mapping.  */
14883         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14884                 bool plane;
14885
14886                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14887                               crtc->base.base.id);
14888
14889                 /* Pipe has the wrong plane attached and the plane is active.
14890                  * Temporarily change the plane mapping and disable everything
14891                  * ...  */
14892                 plane = crtc->plane;
14893                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14894                 crtc->plane = !plane;
14895                 intel_crtc_disable_noatomic(&crtc->base);
14896                 crtc->plane = plane;
14897         }
14898
14899         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14900             crtc->pipe == PIPE_A && !crtc->active) {
14901                 /* BIOS forgot to enable pipe A, this mostly happens after
14902                  * resume. Force-enable the pipe to fix this, the update_dpms
14903                  * call below we restore the pipe to the right state, but leave
14904                  * the required bits on. */
14905                 intel_enable_pipe_a(dev);
14906         }
14907
14908         /* Adjust the state of the output pipe according to whether we
14909          * have active connectors/encoders. */
14910         enable = false;
14911         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14912                 enable = true;
14913                 break;
14914         }
14915
14916         if (!enable)
14917                 intel_crtc_disable_noatomic(&crtc->base);
14918
14919         if (crtc->active != crtc->base.state->active) {
14920
14921                 /* This can happen either due to bugs in the get_hw_state
14922                  * functions or because of calls to intel_crtc_disable_noatomic,
14923                  * or because the pipe is force-enabled due to the
14924                  * pipe A quirk. */
14925                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14926                               crtc->base.base.id,
14927                               crtc->base.state->enable ? "enabled" : "disabled",
14928                               crtc->active ? "enabled" : "disabled");
14929
14930                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14931                 crtc->base.state->active = crtc->active;
14932                 crtc->base.enabled = crtc->active;
14933
14934                 /* Because we only establish the connector -> encoder ->
14935                  * crtc links if something is active, this means the
14936                  * crtc is now deactivated. Break the links. connector
14937                  * -> encoder links are only establish when things are
14938                  *  actually up, hence no need to break them. */
14939                 WARN_ON(crtc->active);
14940
14941                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14942                         encoder->base.crtc = NULL;
14943         }
14944
14945         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14946                 /*
14947                  * We start out with underrun reporting disabled to avoid races.
14948                  * For correct bookkeeping mark this on active crtcs.
14949                  *
14950                  * Also on gmch platforms we dont have any hardware bits to
14951                  * disable the underrun reporting. Which means we need to start
14952                  * out with underrun reporting disabled also on inactive pipes,
14953                  * since otherwise we'll complain about the garbage we read when
14954                  * e.g. coming up after runtime pm.
14955                  *
14956                  * No protection against concurrent access is required - at
14957                  * worst a fifo underrun happens which also sets this to false.
14958                  */
14959                 crtc->cpu_fifo_underrun_disabled = true;
14960                 crtc->pch_fifo_underrun_disabled = true;
14961         }
14962 }
14963
14964 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14965 {
14966         struct intel_connector *connector;
14967         struct drm_device *dev = encoder->base.dev;
14968         bool active = false;
14969
14970         /* We need to check both for a crtc link (meaning that the
14971          * encoder is active and trying to read from a pipe) and the
14972          * pipe itself being active. */
14973         bool has_active_crtc = encoder->base.crtc &&
14974                 to_intel_crtc(encoder->base.crtc)->active;
14975
14976         for_each_intel_connector(dev, connector) {
14977                 if (connector->base.encoder != &encoder->base)
14978                         continue;
14979
14980                 active = true;
14981                 break;
14982         }
14983
14984         if (active && !has_active_crtc) {
14985                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14986                               encoder->base.base.id,
14987                               encoder->base.name);
14988
14989                 /* Connector is active, but has no active pipe. This is
14990                  * fallout from our resume register restoring. Disable
14991                  * the encoder manually again. */
14992                 if (encoder->base.crtc) {
14993                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14994                                       encoder->base.base.id,
14995                                       encoder->base.name);
14996                         encoder->disable(encoder);
14997                         if (encoder->post_disable)
14998                                 encoder->post_disable(encoder);
14999                 }
15000                 encoder->base.crtc = NULL;
15001
15002                 /* Inconsistent output/port/pipe state happens presumably due to
15003                  * a bug in one of the get_hw_state functions. Or someplace else
15004                  * in our code, like the register restore mess on resume. Clamp
15005                  * things to off as a safer default. */
15006                 for_each_intel_connector(dev, connector) {
15007                         if (connector->encoder != encoder)
15008                                 continue;
15009                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15010                         connector->base.encoder = NULL;
15011                 }
15012         }
15013         /* Enabled encoders without active connectors will be fixed in
15014          * the crtc fixup. */
15015 }
15016
15017 void i915_redisable_vga_power_on(struct drm_device *dev)
15018 {
15019         struct drm_i915_private *dev_priv = dev->dev_private;
15020         u32 vga_reg = i915_vgacntrl_reg(dev);
15021
15022         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15023                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15024                 i915_disable_vga(dev);
15025         }
15026 }
15027
15028 void i915_redisable_vga(struct drm_device *dev)
15029 {
15030         struct drm_i915_private *dev_priv = dev->dev_private;
15031
15032         /* This function can be called both from intel_modeset_setup_hw_state or
15033          * at a very early point in our resume sequence, where the power well
15034          * structures are not yet restored. Since this function is at a very
15035          * paranoid "someone might have enabled VGA while we were not looking"
15036          * level, just check if the power well is enabled instead of trying to
15037          * follow the "don't touch the power well if we don't need it" policy
15038          * the rest of the driver uses. */
15039         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15040                 return;
15041
15042         i915_redisable_vga_power_on(dev);
15043 }
15044
15045 static bool primary_get_hw_state(struct intel_crtc *crtc)
15046 {
15047         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15048
15049         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15050 }
15051
15052 static void readout_plane_state(struct intel_crtc *crtc,
15053                                 struct intel_crtc_state *crtc_state)
15054 {
15055         struct intel_plane *p;
15056         struct intel_plane_state *plane_state;
15057         bool active = crtc_state->base.active;
15058
15059         for_each_intel_plane(crtc->base.dev, p) {
15060                 if (crtc->pipe != p->pipe)
15061                         continue;
15062
15063                 plane_state = to_intel_plane_state(p->base.state);
15064
15065                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15066                         plane_state->visible = primary_get_hw_state(crtc);
15067                 else {
15068                         if (active)
15069                                 p->disable_plane(&p->base, &crtc->base);
15070
15071                         plane_state->visible = false;
15072                 }
15073         }
15074 }
15075
15076 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15077 {
15078         struct drm_i915_private *dev_priv = dev->dev_private;
15079         enum pipe pipe;
15080         struct intel_crtc *crtc;
15081         struct intel_encoder *encoder;
15082         struct intel_connector *connector;
15083         int i;
15084
15085         for_each_intel_crtc(dev, crtc) {
15086                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15087                 memset(crtc->config, 0, sizeof(*crtc->config));
15088                 crtc->config->base.crtc = &crtc->base;
15089
15090                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15091                                                                  crtc->config);
15092
15093                 crtc->base.state->active = crtc->active;
15094                 crtc->base.enabled = crtc->active;
15095
15096                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15097                 if (crtc->base.state->active) {
15098                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15099                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15100                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15101
15102                         /*
15103                          * The initial mode needs to be set in order to keep
15104                          * the atomic core happy. It wants a valid mode if the
15105                          * crtc's enabled, so we do the above call.
15106                          *
15107                          * At this point some state updated by the connectors
15108                          * in their ->detect() callback has not run yet, so
15109                          * no recalculation can be done yet.
15110                          *
15111                          * Even if we could do a recalculation and modeset
15112                          * right now it would cause a double modeset if
15113                          * fbdev or userspace chooses a different initial mode.
15114                          *
15115                          * If that happens, someone indicated they wanted a
15116                          * mode change, which means it's safe to do a full
15117                          * recalculation.
15118                          */
15119                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15120                 }
15121
15122                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15123                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15124
15125                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15126                               crtc->base.base.id,
15127                               crtc->active ? "enabled" : "disabled");
15128         }
15129
15130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15131                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15132
15133                 pll->on = pll->get_hw_state(dev_priv, pll,
15134                                             &pll->config.hw_state);
15135                 pll->active = 0;
15136                 pll->config.crtc_mask = 0;
15137                 for_each_intel_crtc(dev, crtc) {
15138                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15139                                 pll->active++;
15140                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15141                         }
15142                 }
15143
15144                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15145                               pll->name, pll->config.crtc_mask, pll->on);
15146
15147                 if (pll->config.crtc_mask)
15148                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15149         }
15150
15151         for_each_intel_encoder(dev, encoder) {
15152                 pipe = 0;
15153
15154                 if (encoder->get_hw_state(encoder, &pipe)) {
15155                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15156                         encoder->base.crtc = &crtc->base;
15157                         encoder->get_config(encoder, crtc->config);
15158                 } else {
15159                         encoder->base.crtc = NULL;
15160                 }
15161
15162                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15163                               encoder->base.base.id,
15164                               encoder->base.name,
15165                               encoder->base.crtc ? "enabled" : "disabled",
15166                               pipe_name(pipe));
15167         }
15168
15169         for_each_intel_connector(dev, connector) {
15170                 if (connector->get_hw_state(connector)) {
15171                         connector->base.dpms = DRM_MODE_DPMS_ON;
15172                         connector->base.encoder = &connector->encoder->base;
15173                 } else {
15174                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15175                         connector->base.encoder = NULL;
15176                 }
15177                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15178                               connector->base.base.id,
15179                               connector->base.name,
15180                               connector->base.encoder ? "enabled" : "disabled");
15181         }
15182 }
15183
15184 /* Scan out the current hw modeset state,
15185  * and sanitizes it to the current state
15186  */
15187 static void
15188 intel_modeset_setup_hw_state(struct drm_device *dev)
15189 {
15190         struct drm_i915_private *dev_priv = dev->dev_private;
15191         enum pipe pipe;
15192         struct intel_crtc *crtc;
15193         struct intel_encoder *encoder;
15194         int i;
15195
15196         intel_modeset_readout_hw_state(dev);
15197
15198         /* HW state is read out, now we need to sanitize this mess. */
15199         for_each_intel_encoder(dev, encoder) {
15200                 intel_sanitize_encoder(encoder);
15201         }
15202
15203         for_each_pipe(dev_priv, pipe) {
15204                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15205                 intel_sanitize_crtc(crtc);
15206                 intel_dump_pipe_config(crtc, crtc->config,
15207                                        "[setup_hw_state]");
15208         }
15209
15210         intel_modeset_update_connector_atomic_state(dev);
15211
15212         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15213                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15214
15215                 if (!pll->on || pll->active)
15216                         continue;
15217
15218                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15219
15220                 pll->disable(dev_priv, pll);
15221                 pll->on = false;
15222         }
15223
15224         if (IS_VALLEYVIEW(dev))
15225                 vlv_wm_get_hw_state(dev);
15226         else if (IS_GEN9(dev))
15227                 skl_wm_get_hw_state(dev);
15228         else if (HAS_PCH_SPLIT(dev))
15229                 ilk_wm_get_hw_state(dev);
15230
15231         for_each_intel_crtc(dev, crtc) {
15232                 unsigned long put_domains;
15233
15234                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15235                 if (WARN_ON(put_domains))
15236                         modeset_put_power_domains(dev_priv, put_domains);
15237         }
15238         intel_display_set_init_power(dev_priv, false);
15239 }
15240
15241 void intel_display_resume(struct drm_device *dev)
15242 {
15243         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15244         struct intel_connector *conn;
15245         struct intel_plane *plane;
15246         struct drm_crtc *crtc;
15247         int ret;
15248
15249         if (!state)
15250                 return;
15251
15252         state->acquire_ctx = dev->mode_config.acquire_ctx;
15253
15254         /* preserve complete old state, including dpll */
15255         intel_atomic_get_shared_dpll_state(state);
15256
15257         for_each_crtc(dev, crtc) {
15258                 struct drm_crtc_state *crtc_state =
15259                         drm_atomic_get_crtc_state(state, crtc);
15260
15261                 ret = PTR_ERR_OR_ZERO(crtc_state);
15262                 if (ret)
15263                         goto err;
15264
15265                 /* force a restore */
15266                 crtc_state->mode_changed = true;
15267         }
15268
15269         for_each_intel_plane(dev, plane) {
15270                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15271                 if (ret)
15272                         goto err;
15273         }
15274
15275         for_each_intel_connector(dev, conn) {
15276                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15277                 if (ret)
15278                         goto err;
15279         }
15280
15281         intel_modeset_setup_hw_state(dev);
15282
15283         i915_redisable_vga(dev);
15284         ret = drm_atomic_commit(state);
15285         if (!ret)
15286                 return;
15287
15288 err:
15289         DRM_ERROR("Restoring old state failed with %i\n", ret);
15290         drm_atomic_state_free(state);
15291 }
15292
15293 void intel_modeset_gem_init(struct drm_device *dev)
15294 {
15295         struct drm_i915_private *dev_priv = dev->dev_private;
15296         struct drm_crtc *c;
15297         struct drm_i915_gem_object *obj;
15298         int ret;
15299
15300         mutex_lock(&dev->struct_mutex);
15301         intel_init_gt_powersave(dev);
15302         mutex_unlock(&dev->struct_mutex);
15303
15304         /*
15305          * There may be no VBT; and if the BIOS enabled SSC we can
15306          * just keep using it to avoid unnecessary flicker.  Whereas if the
15307          * BIOS isn't using it, don't assume it will work even if the VBT
15308          * indicates as much.
15309          */
15310         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15311                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15312                                                 DREF_SSC1_ENABLE);
15313
15314         intel_modeset_init_hw(dev);
15315
15316         intel_setup_overlay(dev);
15317
15318         /*
15319          * Make sure any fbs we allocated at startup are properly
15320          * pinned & fenced.  When we do the allocation it's too early
15321          * for this.
15322          */
15323         for_each_crtc(dev, c) {
15324                 obj = intel_fb_obj(c->primary->fb);
15325                 if (obj == NULL)
15326                         continue;
15327
15328                 mutex_lock(&dev->struct_mutex);
15329                 ret = intel_pin_and_fence_fb_obj(c->primary,
15330                                                  c->primary->fb,
15331                                                  c->primary->state,
15332                                                  NULL, NULL);
15333                 mutex_unlock(&dev->struct_mutex);
15334                 if (ret) {
15335                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15336                                   to_intel_crtc(c)->pipe);
15337                         drm_framebuffer_unreference(c->primary->fb);
15338                         c->primary->fb = NULL;
15339                         c->primary->crtc = c->primary->state->crtc = NULL;
15340                         update_state_fb(c->primary);
15341                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15342                 }
15343         }
15344
15345         intel_backlight_register(dev);
15346 }
15347
15348 void intel_connector_unregister(struct intel_connector *intel_connector)
15349 {
15350         struct drm_connector *connector = &intel_connector->base;
15351
15352         intel_panel_destroy_backlight(connector);
15353         drm_connector_unregister(connector);
15354 }
15355
15356 void intel_modeset_cleanup(struct drm_device *dev)
15357 {
15358         struct drm_i915_private *dev_priv = dev->dev_private;
15359         struct drm_connector *connector;
15360
15361         intel_disable_gt_powersave(dev);
15362
15363         intel_backlight_unregister(dev);
15364
15365         /*
15366          * Interrupts and polling as the first thing to avoid creating havoc.
15367          * Too much stuff here (turning of connectors, ...) would
15368          * experience fancy races otherwise.
15369          */
15370         intel_irq_uninstall(dev_priv);
15371
15372         /*
15373          * Due to the hpd irq storm handling the hotplug work can re-arm the
15374          * poll handlers. Hence disable polling after hpd handling is shut down.
15375          */
15376         drm_kms_helper_poll_fini(dev);
15377
15378         intel_unregister_dsm_handler();
15379
15380         intel_fbc_disable(dev_priv);
15381
15382         /* flush any delayed tasks or pending work */
15383         flush_scheduled_work();
15384
15385         /* destroy the backlight and sysfs files before encoders/connectors */
15386         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15387                 struct intel_connector *intel_connector;
15388
15389                 intel_connector = to_intel_connector(connector);
15390                 intel_connector->unregister(intel_connector);
15391         }
15392
15393         drm_mode_config_cleanup(dev);
15394
15395         intel_cleanup_overlay(dev);
15396
15397         mutex_lock(&dev->struct_mutex);
15398         intel_cleanup_gt_powersave(dev);
15399         mutex_unlock(&dev->struct_mutex);
15400 }
15401
15402 /*
15403  * Return which encoder is currently attached for connector.
15404  */
15405 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15406 {
15407         return &intel_attached_encoder(connector)->base;
15408 }
15409
15410 void intel_connector_attach_encoder(struct intel_connector *connector,
15411                                     struct intel_encoder *encoder)
15412 {
15413         connector->encoder = encoder;
15414         drm_mode_connector_attach_encoder(&connector->base,
15415                                           &encoder->base);
15416 }
15417
15418 /*
15419  * set vga decode state - true == enable VGA decode
15420  */
15421 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15422 {
15423         struct drm_i915_private *dev_priv = dev->dev_private;
15424         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15425         u16 gmch_ctrl;
15426
15427         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15428                 DRM_ERROR("failed to read control word\n");
15429                 return -EIO;
15430         }
15431
15432         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15433                 return 0;
15434
15435         if (state)
15436                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15437         else
15438                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15439
15440         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15441                 DRM_ERROR("failed to write control word\n");
15442                 return -EIO;
15443         }
15444
15445         return 0;
15446 }
15447
15448 struct intel_display_error_state {
15449
15450         u32 power_well_driver;
15451
15452         int num_transcoders;
15453
15454         struct intel_cursor_error_state {
15455                 u32 control;
15456                 u32 position;
15457                 u32 base;
15458                 u32 size;
15459         } cursor[I915_MAX_PIPES];
15460
15461         struct intel_pipe_error_state {
15462                 bool power_domain_on;
15463                 u32 source;
15464                 u32 stat;
15465         } pipe[I915_MAX_PIPES];
15466
15467         struct intel_plane_error_state {
15468                 u32 control;
15469                 u32 stride;
15470                 u32 size;
15471                 u32 pos;
15472                 u32 addr;
15473                 u32 surface;
15474                 u32 tile_offset;
15475         } plane[I915_MAX_PIPES];
15476
15477         struct intel_transcoder_error_state {
15478                 bool power_domain_on;
15479                 enum transcoder cpu_transcoder;
15480
15481                 u32 conf;
15482
15483                 u32 htotal;
15484                 u32 hblank;
15485                 u32 hsync;
15486                 u32 vtotal;
15487                 u32 vblank;
15488                 u32 vsync;
15489         } transcoder[4];
15490 };
15491
15492 struct intel_display_error_state *
15493 intel_display_capture_error_state(struct drm_device *dev)
15494 {
15495         struct drm_i915_private *dev_priv = dev->dev_private;
15496         struct intel_display_error_state *error;
15497         int transcoders[] = {
15498                 TRANSCODER_A,
15499                 TRANSCODER_B,
15500                 TRANSCODER_C,
15501                 TRANSCODER_EDP,
15502         };
15503         int i;
15504
15505         if (INTEL_INFO(dev)->num_pipes == 0)
15506                 return NULL;
15507
15508         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15509         if (error == NULL)
15510                 return NULL;
15511
15512         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15513                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15514
15515         for_each_pipe(dev_priv, i) {
15516                 error->pipe[i].power_domain_on =
15517                         __intel_display_power_is_enabled(dev_priv,
15518                                                          POWER_DOMAIN_PIPE(i));
15519                 if (!error->pipe[i].power_domain_on)
15520                         continue;
15521
15522                 error->cursor[i].control = I915_READ(CURCNTR(i));
15523                 error->cursor[i].position = I915_READ(CURPOS(i));
15524                 error->cursor[i].base = I915_READ(CURBASE(i));
15525
15526                 error->plane[i].control = I915_READ(DSPCNTR(i));
15527                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15528                 if (INTEL_INFO(dev)->gen <= 3) {
15529                         error->plane[i].size = I915_READ(DSPSIZE(i));
15530                         error->plane[i].pos = I915_READ(DSPPOS(i));
15531                 }
15532                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15533                         error->plane[i].addr = I915_READ(DSPADDR(i));
15534                 if (INTEL_INFO(dev)->gen >= 4) {
15535                         error->plane[i].surface = I915_READ(DSPSURF(i));
15536                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15537                 }
15538
15539                 error->pipe[i].source = I915_READ(PIPESRC(i));
15540
15541                 if (HAS_GMCH_DISPLAY(dev))
15542                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15543         }
15544
15545         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15546         if (HAS_DDI(dev_priv->dev))
15547                 error->num_transcoders++; /* Account for eDP. */
15548
15549         for (i = 0; i < error->num_transcoders; i++) {
15550                 enum transcoder cpu_transcoder = transcoders[i];
15551
15552                 error->transcoder[i].power_domain_on =
15553                         __intel_display_power_is_enabled(dev_priv,
15554                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15555                 if (!error->transcoder[i].power_domain_on)
15556                         continue;
15557
15558                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15559
15560                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15561                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15562                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15563                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15564                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15565                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15566                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15567         }
15568
15569         return error;
15570 }
15571
15572 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15573
15574 void
15575 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15576                                 struct drm_device *dev,
15577                                 struct intel_display_error_state *error)
15578 {
15579         struct drm_i915_private *dev_priv = dev->dev_private;
15580         int i;
15581
15582         if (!error)
15583                 return;
15584
15585         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15586         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15587                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15588                            error->power_well_driver);
15589         for_each_pipe(dev_priv, i) {
15590                 err_printf(m, "Pipe [%d]:\n", i);
15591                 err_printf(m, "  Power: %s\n",
15592                            error->pipe[i].power_domain_on ? "on" : "off");
15593                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15594                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15595
15596                 err_printf(m, "Plane [%d]:\n", i);
15597                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15598                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15599                 if (INTEL_INFO(dev)->gen <= 3) {
15600                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15601                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15602                 }
15603                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15604                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15605                 if (INTEL_INFO(dev)->gen >= 4) {
15606                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15607                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15608                 }
15609
15610                 err_printf(m, "Cursor [%d]:\n", i);
15611                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15612                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15613                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15614         }
15615
15616         for (i = 0; i < error->num_transcoders; i++) {
15617                 err_printf(m, "CPU transcoder: %c\n",
15618                            transcoder_name(error->transcoder[i].cpu_transcoder));
15619                 err_printf(m, "  Power: %s\n",
15620                            error->transcoder[i].power_domain_on ? "on" : "off");
15621                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15622                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15623                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15624                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15625                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15626                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15627                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15628         }
15629 }
15630
15631 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15632 {
15633         struct intel_crtc *crtc;
15634
15635         for_each_intel_crtc(dev, crtc) {
15636                 struct intel_unpin_work *work;
15637
15638                 spin_lock_irq(&dev->event_lock);
15639
15640                 work = crtc->unpin_work;
15641
15642                 if (work && work->event &&
15643                     work->event->base.file_priv == file) {
15644                         kfree(work->event);
15645                         work->event = NULL;
15646                 }
15647
15648                 spin_unlock_irq(&dev->event_lock);
15649         }
15650 }