2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
66 typedef struct intel_limit intel_limit_t;
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
76 intel_pch_rawclk(struct drm_device *dev)
78 struct drm_i915_private *dev_priv = dev->dev_private;
80 WARN_ON(!HAS_PCH_SPLIT(dev));
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
85 static inline u32 /* units of 100MHz */
86 intel_fdi_link_freq(struct drm_device *dev)
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
95 static const intel_limit_t intel_limits_i8xx_dac = {
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
134 static const intel_limit_t intel_limits_i9xx_sdvo = {
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
147 static const intel_limit_t intel_limits_i9xx_lvds = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
161 static const intel_limit_t intel_limits_g4x_sdvo = {
162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
176 static const intel_limit_t intel_limits_g4x_hdmi = {
177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
217 static const intel_limit_t intel_limits_pineview_sdvo = {
218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
220 /* Pineview's Ncounter is a ring counter */
221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
223 /* Pineview only has one combined m divider, which we treat as m2. */
224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
232 static const intel_limit_t intel_limits_pineview_lvds = {
233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
245 /* Ironlake / Sandybridge
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
250 static const intel_limit_t intel_limits_ironlake_dac = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
289 /* LVDS 100mhz refclk limits. */
290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
298 .p1 = { .min = 2, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
311 .p1 = { .min = 2, .max = 6 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
316 static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
324 .p1 = { .min = 1, .max = 3 },
325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
329 static const intel_limit_t intel_limits_vlv_hdmi = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
342 static const intel_limit_t intel_limits_vlv_dp = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 },
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 struct drm_device *dev = crtc->dev;
359 const intel_limit_t *limit;
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
362 if (intel_is_dual_link_lvds(dev)) {
363 if (refclk == 100000)
364 limit = &intel_limits_ironlake_dual_lvds_100m;
366 limit = &intel_limits_ironlake_dual_lvds;
368 if (refclk == 100000)
369 limit = &intel_limits_ironlake_single_lvds_100m;
371 limit = &intel_limits_ironlake_single_lvds;
374 limit = &intel_limits_ironlake_dac;
379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
385 if (intel_is_dual_link_lvds(dev))
386 limit = &intel_limits_g4x_dual_channel_lvds;
388 limit = &intel_limits_g4x_single_channel_lvds;
389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
391 limit = &intel_limits_g4x_hdmi;
392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
393 limit = &intel_limits_g4x_sdvo;
394 } else /* The option is for other outputs */
395 limit = &intel_limits_i9xx_sdvo;
400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
405 if (HAS_PCH_SPLIT(dev))
406 limit = intel_ironlake_limit(crtc, refclk);
407 else if (IS_G4X(dev)) {
408 limit = intel_g4x_limit(crtc);
409 } else if (IS_PINEVIEW(dev)) {
410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
411 limit = &intel_limits_pineview_lvds;
413 limit = &intel_limits_pineview_sdvo;
414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
420 limit = &intel_limits_vlv_dp;
421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
425 limit = &intel_limits_i9xx_sdvo;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_i8xx_lvds;
429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
430 limit = &intel_limits_i8xx_dvo;
432 limit = &intel_limits_i8xx_dac;
437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
438 static void pineview_clock(int refclk, intel_clock_t *clock)
440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
451 static void i9xx_clock(int refclk, intel_clock_t *clock)
453 clock->m = i9xx_dpll_compute_m(clock);
454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
460 * Returns whether any output on the specified pipe is of the specified type
462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
464 struct drm_device *dev = crtc->dev;
465 struct intel_encoder *encoder;
467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
474 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
480 static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
485 INTELPllInvalid("p1 out of range\n");
486 if (clock->p < limit->p.min || limit->p.max < clock->p)
487 INTELPllInvalid("p out of range\n");
488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
489 INTELPllInvalid("m2 out of range\n");
490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
491 INTELPllInvalid("m1 out of range\n");
492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
493 INTELPllInvalid("m1 <= m2\n");
494 if (clock->m < limit->m.min || limit->m.max < clock->m)
495 INTELPllInvalid("m out of range\n");
496 if (clock->n < limit->n.min || limit->n.max < clock->n)
497 INTELPllInvalid("n out of range\n");
498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
499 INTELPllInvalid("vco out of range\n");
500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
504 INTELPllInvalid("dot out of range\n");
510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
514 struct drm_device *dev = crtc->dev;
518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
524 if (intel_is_dual_link_lvds(dev))
525 clock.p2 = limit->p2.p2_fast;
527 clock.p2 = limit->p2.p2_slow;
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
532 clock.p2 = limit->p2.p2_fast;
535 memset(best_clock, 0, sizeof(*best_clock));
537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
541 if (clock.m2 >= clock.m1)
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
554 clock.p != match_clock->p)
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
567 return (err != target);
571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
575 struct drm_device *dev = crtc->dev;
579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
585 if (intel_is_dual_link_lvds(dev))
586 clock.p2 = limit->p2.p2_fast;
588 clock.p2 = limit->p2.p2_slow;
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
593 clock.p2 = limit->p2.p2_fast;
596 memset(best_clock, 0, sizeof(*best_clock));
598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
608 pineview_clock(refclk, &clock);
609 if (!intel_PLL_is_valid(dev, limit,
613 clock.p != match_clock->p)
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
626 return (err != target);
630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
634 struct drm_device *dev = crtc->dev;
638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (intel_is_dual_link_lvds(dev))
644 clock.p2 = limit->p2.p2_fast;
646 clock.p2 = limit->p2.p2_slow;
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
651 clock.p2 = limit->p2.p2_fast;
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
656 /* based on hardware requirement, prefer smaller n to precision */
657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
658 /* based on hardware requirement, prefere larger m1,m2 */
659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
667 i9xx_clock(refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
672 this_err = abs(clock.dot - target);
673 if (this_err < err_most) {
687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
693 u32 updrate, minupdate, p;
694 unsigned long bestppm, ppm, absppm;
698 dotclk = target * 1000;
701 fastclk = dotclk / (2*100);
704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
728 if (absppm < bestppm - 10) {
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
760 return intel_crtc->config.cpu_transcoder;
763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
768 frame = I915_READ(frame_reg);
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
775 * intel_wait_for_vblank - wait for vblank on a given pipe
777 * @pipe: pipe to wait for
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 int pipestat_reg = PIPESTAT(pipe);
787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
808 /* Wait for vblank interrupt bit to set */
809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
812 DRM_DEBUG_KMS("vblank wait timed out\n");
816 * intel_wait_for_pipe_off - wait for pipe to turn off
818 * @pipe: pipe to wait for
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
825 * wait for the pipe register state bit to turn off
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
838 if (INTEL_INFO(dev)->gen >= 4) {
839 int reg = PIPECONF(cpu_transcoder);
841 /* Wait for the Pipe State to go off */
842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
844 WARN(1, "pipe_off wait timed out\n");
846 u32 last_line, line_mask;
847 int reg = PIPEDSL(pipe);
848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
851 line_mask = DSL_LINEMASK_GEN2;
853 line_mask = DSL_LINEMASK_GEN3;
855 /* Wait for the display line to settle */
857 last_line = I915_READ(reg) & line_mask;
859 } while (((I915_READ(reg) & line_mask) != last_line) &&
860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
862 WARN(1, "pipe_off wait timed out\n");
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
871 * Returns true if @port is connected, false otherwise.
873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
878 if (HAS_PCH_IBX(dev_priv->dev)) {
881 bit = SDE_PORTB_HOTPLUG;
884 bit = SDE_PORTC_HOTPLUG;
887 bit = SDE_PORTD_HOTPLUG;
895 bit = SDE_PORTB_HOTPLUG_CPT;
898 bit = SDE_PORTC_HOTPLUG_CPT;
901 bit = SDE_PORTD_HOTPLUG_CPT;
908 return I915_READ(SDEISR) & bit;
911 static const char *state_string(bool enabled)
913 return enabled ? "on" : "off";
916 /* Only for pre-ILK configs */
917 void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
932 struct intel_shared_dpll *
933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
937 if (crtc->config.shared_dpll < 0)
940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
949 struct intel_dpll_hw_state hw_state;
951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 "asserting DPLL %s with no DPLL\n", state_string(state)))
960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
961 WARN(cur_state != state,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
978 val = I915_READ(reg);
979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv->dev))
1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1046 int pp_reg, lvds_reg;
1048 enum pipe panel_pipe = PIPE_A;
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1055 pp_reg = PP_CONTROL;
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe), state_string(state), state_string(cur_state));
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1120 struct drm_device *dev = dev_priv->dev;
1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1135 /* Need to check both planes against the pipe */
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1150 struct drm_device *dev = dev_priv->dev;
1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1164 val = I915_READ(reg);
1165 WARN((val & SPRITE_ENABLE),
1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
1170 val = I915_READ(reg);
1171 WARN((val & DVS_ENABLE),
1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(pipe), pipe_name(pipe));
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1200 reg = PCH_TRANSCONF(pipe);
1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
1211 if ((val & DP_PORT_EN) == 0)
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1229 if ((val & SDVO_ENABLE) == 0)
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1245 if ((val & LVDS_PORT_EN) == 0)
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, int reg, u32 port_sel)
1276 u32 val = I915_READ(reg);
1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279 reg, pipe_name(pipe));
1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
1283 "IBX PCH dp port still using transcoder B\n");
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1289 u32 val = I915_READ(reg);
1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292 reg, pipe_name(pipe));
1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295 && (val & SDVO_PIPE_B_SELECT),
1296 "IBX PCH hdmi port still using transcoder B\n");
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1310 val = I915_READ(reg);
1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
1316 val = I915_READ(reg);
1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
1333 assert_pipe_disabled(dev_priv, crtc->pipe);
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340 assert_panel_unlocked(dev_priv, crtc->pipe);
1342 I915_WRITE(reg, dpll);
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
1352 /* We do this three times for luck */
1353 I915_WRITE(reg, dpll);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg, dpll);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg, dpll);
1361 udelay(150); /* wait for warmup */
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
1371 assert_pipe_disabled(dev_priv, crtc->pipe);
1373 /* No really, not for ILK+ */
1374 BUG_ON(dev_priv->info->gen >= 5);
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
1380 I915_WRITE(reg, dpll);
1382 /* Wait for the clocks to stabilize. */
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1393 * So write it again.
1395 I915_WRITE(reg, dpll);
1398 /* We do this three times for luck */
1399 I915_WRITE(reg, dpll);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg, dpll);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg, dpll);
1407 udelay(150); /* wait for warmup */
1411 * i9xx_disable_pll - disable a PLL
1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1417 * Note! This is for pre-ILK only.
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
1432 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1439 port_mask = DPLL_PORTC_READY_MASK;
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1447 * ironlake_enable_shared_dpll - enable PCH PLL
1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1454 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1459 /* PCH PLLs only available on ILK, SNB and IVB */
1460 BUG_ON(dev_priv->info->gen < 5);
1461 if (WARN_ON(pll == NULL))
1464 if (WARN_ON(pll->refcount == 0))
1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
1469 crtc->base.base.id);
1471 if (pll->active++) {
1473 assert_shared_dpll_enabled(dev_priv, pll);
1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479 pll->enable(dev_priv, pll);
1483 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
1490 if (WARN_ON(pll == NULL))
1493 if (WARN_ON(pll->refcount == 0))
1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
1498 crtc->base.base.id);
1500 if (WARN_ON(pll->active == 0)) {
1501 assert_shared_dpll_disabled(dev_priv, pll);
1505 assert_shared_dpll_enabled(dev_priv, pll);
1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511 pll->disable(dev_priv, pll);
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1518 struct drm_device *dev = dev_priv->dev;
1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521 uint32_t reg, val, pipeconf_val;
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1526 /* Make sure PCH DPLL is enabled */
1527 assert_shared_dpll_enabled(dev_priv,
1528 intel_crtc_to_shared_dpll(intel_crtc));
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
1543 reg = PCH_TRANSCONF(pipe);
1544 val = I915_READ(reg);
1545 pipeconf_val = I915_READ(PIPECONF(pipe));
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1562 val |= TRANS_INTERLACED;
1564 val |= TRANS_PROGRESSIVE;
1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572 enum transcoder cpu_transcoder)
1574 u32 val, pipeconf_val;
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1579 /* FDI must be feeding us bits for PCH ports */
1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
1593 val |= TRANS_INTERLACED;
1595 val |= TRANS_PROGRESSIVE;
1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599 DRM_ERROR("Failed to enable PCH transcoder\n");
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1605 struct drm_device *dev = dev_priv->dev;
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1615 reg = PCH_TRANSCONF(pipe);
1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1636 val = I915_READ(LPT_TRANSCONF);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(LPT_TRANSCONF, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641 DRM_ERROR("Failed to disable PCH transcoder\n");
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1650 * intel_enable_pipe - enable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1658 * @pipe should be %PIPE_A or %PIPE_B.
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1663 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1668 enum pipe pch_transcoder;
1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1675 if (HAS_PCH_LPT(dev_priv->dev))
1676 pch_transcoder = TRANSCODER_A;
1678 pch_transcoder = pipe;
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
1686 assert_pll_enabled(dev_priv, pipe);
1689 /* if driving the PCH, we need FDI enabled */
1690 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1691 assert_fdi_tx_pll_enabled(dev_priv,
1692 (enum pipe) cpu_transcoder);
1694 /* FIXME: assert CPU port conditions for SNB+ */
1697 reg = PIPECONF(cpu_transcoder);
1698 val = I915_READ(reg);
1699 if (val & PIPECONF_ENABLE)
1702 I915_WRITE(reg, val | PIPECONF_ENABLE);
1703 intel_wait_for_vblank(dev_priv->dev, pipe);
1707 * intel_disable_pipe - disable a pipe, asserting requirements
1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe to disable
1711 * Disable @pipe, making sure that various hardware specific requirements
1712 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1714 * @pipe should be %PIPE_A or %PIPE_B.
1716 * Will wait until the pipe has shut down before returning.
1718 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1721 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 * Make sure planes won't keep trying to pump pixels to us,
1728 * or we might hang the display.
1730 assert_planes_disabled(dev_priv, pipe);
1731 assert_sprites_disabled(dev_priv, pipe);
1733 /* Don't disable pipe A or pipe A PLLs if needed */
1734 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1737 reg = PIPECONF(cpu_transcoder);
1738 val = I915_READ(reg);
1739 if ((val & PIPECONF_ENABLE) == 0)
1742 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1747 * Plane regs are double buffered, going from enabled->disabled needs a
1748 * trigger in order to latch. The display address reg provides this.
1750 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1753 if (dev_priv->info->gen >= 4)
1754 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1756 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1760 * intel_enable_plane - enable a display plane on a given pipe
1761 * @dev_priv: i915 private structure
1762 * @plane: plane to enable
1763 * @pipe: pipe being fed
1765 * Enable @plane on @pipe, making sure that @pipe is running first.
1767 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768 enum plane plane, enum pipe pipe)
1773 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774 assert_pipe_enabled(dev_priv, pipe);
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
1778 if (val & DISPLAY_PLANE_ENABLE)
1781 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1787 * intel_disable_plane - disable a display plane
1788 * @dev_priv: i915 private structure
1789 * @plane: plane to disable
1790 * @pipe: pipe consuming the data
1792 * Disable @plane; should be an independent operation.
1794 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795 enum plane plane, enum pipe pipe)
1800 reg = DSPCNTR(plane);
1801 val = I915_READ(reg);
1802 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1805 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806 intel_flush_display_plane(dev_priv, plane);
1807 intel_wait_for_vblank(dev_priv->dev, pipe);
1810 static bool need_vtd_wa(struct drm_device *dev)
1812 #ifdef CONFIG_INTEL_IOMMU
1813 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1820 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821 struct drm_i915_gem_object *obj,
1822 struct intel_ring_buffer *pipelined)
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1828 switch (obj->tiling_mode) {
1829 case I915_TILING_NONE:
1830 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831 alignment = 128 * 1024;
1832 else if (INTEL_INFO(dev)->gen >= 4)
1833 alignment = 4 * 1024;
1835 alignment = 64 * 1024;
1838 /* pin() will align the object as required by fence */
1842 /* Despite that we check this in framebuffer_init userspace can
1843 * screw us over and change the tiling after the fact. Only
1844 * pinned buffers can't change their tiling. */
1845 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1851 /* Note that the w/a also requires 64 PTE of padding following the
1852 * bo. We currently fill all unused PTE with the shadow page and so
1853 * we should always have valid PTE following the scanout preventing
1856 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857 alignment = 256 * 1024;
1859 dev_priv->mm.interruptible = false;
1860 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1862 goto err_interruptible;
1864 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865 * fence, whereas 965+ only requires a fence if using
1866 * framebuffer compression. For simplicity, we always install
1867 * a fence as the cost is not that onerous.
1869 ret = i915_gem_object_get_fence(obj);
1873 i915_gem_object_pin_fence(obj);
1875 dev_priv->mm.interruptible = true;
1879 i915_gem_object_unpin_from_display_plane(obj);
1881 dev_priv->mm.interruptible = true;
1885 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1887 i915_gem_object_unpin_fence(obj);
1888 i915_gem_object_unpin_from_display_plane(obj);
1891 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892 * is assumed to be a power-of-two. */
1893 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894 unsigned int tiling_mode,
1898 if (tiling_mode != I915_TILING_NONE) {
1899 unsigned int tile_rows, tiles;
1904 tiles = *x / (512/cpp);
1907 return tile_rows * pitch * 8 + tiles * 4096;
1909 unsigned int offset;
1911 offset = *y * pitch + *x * cpp;
1913 *x = (offset & 4095) / cpp;
1914 return offset & -4096;
1918 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1921 struct drm_device *dev = crtc->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924 struct intel_framebuffer *intel_fb;
1925 struct drm_i915_gem_object *obj;
1926 int plane = intel_crtc->plane;
1927 unsigned long linear_offset;
1936 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1940 intel_fb = to_intel_framebuffer(fb);
1941 obj = intel_fb->obj;
1943 reg = DSPCNTR(plane);
1944 dspcntr = I915_READ(reg);
1945 /* Mask out pixel format bits in case we change it */
1946 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947 switch (fb->pixel_format) {
1949 dspcntr |= DISPPLANE_8BPP;
1951 case DRM_FORMAT_XRGB1555:
1952 case DRM_FORMAT_ARGB1555:
1953 dspcntr |= DISPPLANE_BGRX555;
1955 case DRM_FORMAT_RGB565:
1956 dspcntr |= DISPPLANE_BGRX565;
1958 case DRM_FORMAT_XRGB8888:
1959 case DRM_FORMAT_ARGB8888:
1960 dspcntr |= DISPPLANE_BGRX888;
1962 case DRM_FORMAT_XBGR8888:
1963 case DRM_FORMAT_ABGR8888:
1964 dspcntr |= DISPPLANE_RGBX888;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 dspcntr |= DISPPLANE_BGRX101010;
1970 case DRM_FORMAT_XBGR2101010:
1971 case DRM_FORMAT_ABGR2101010:
1972 dspcntr |= DISPPLANE_RGBX101010;
1978 if (INTEL_INFO(dev)->gen >= 4) {
1979 if (obj->tiling_mode != I915_TILING_NONE)
1980 dspcntr |= DISPPLANE_TILED;
1982 dspcntr &= ~DISPPLANE_TILED;
1986 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1988 I915_WRITE(reg, dspcntr);
1990 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 intel_crtc->dspaddr_offset =
1994 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995 fb->bits_per_pixel / 8,
1997 linear_offset -= intel_crtc->dspaddr_offset;
1999 intel_crtc->dspaddr_offset = linear_offset;
2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2005 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006 if (INTEL_INFO(dev)->gen >= 4) {
2007 I915_MODIFY_DISPBASE(DSPSURF(plane),
2008 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010 I915_WRITE(DSPLINOFF(plane), linear_offset);
2012 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2018 static int ironlake_update_plane(struct drm_crtc *crtc,
2019 struct drm_framebuffer *fb, int x, int y)
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2037 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->pixel_format) {
2050 dspcntr |= DISPPLANE_8BPP;
2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2078 dspcntr &= ~DISPPLANE_TILED;
2081 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2083 I915_WRITE(reg, dspcntr);
2085 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2086 intel_crtc->dspaddr_offset =
2087 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2088 fb->bits_per_pixel / 8,
2090 linear_offset -= intel_crtc->dspaddr_offset;
2092 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2093 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2095 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2096 I915_MODIFY_DISPBASE(DSPSURF(plane),
2097 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2098 if (IS_HASWELL(dev)) {
2099 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2101 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
2119 intel_increase_pllclock(crtc);
2121 return dev_priv->display.update_plane(crtc, fb, x, y);
2124 void intel_display_handle_reset(struct drm_device *dev)
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 struct drm_crtc *crtc;
2130 * Flips in the rings have been nuked by the reset,
2131 * so complete all pending flips so that user space
2132 * will get its events and not get stuck.
2134 * Also update the base address of all primary
2135 * planes to the the last fb to make sure we're
2136 * showing the correct fb after a reset.
2138 * Need to make two loops over the crtcs so that we
2139 * don't try to grab a crtc mutex before the
2140 * pending_flip_queue really got woken up.
2143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145 enum plane plane = intel_crtc->plane;
2147 intel_prepare_page_flip(dev, plane);
2148 intel_finish_page_flip_plane(dev, plane);
2151 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154 mutex_lock(&crtc->mutex);
2155 if (intel_crtc->active)
2156 dev_priv->display.update_plane(crtc, crtc->fb,
2158 mutex_unlock(&crtc->mutex);
2163 intel_finish_fb(struct drm_framebuffer *old_fb)
2165 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2166 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2167 bool was_interruptible = dev_priv->mm.interruptible;
2170 /* Big Hammer, we also need to ensure that any pending
2171 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2172 * current scanout is retired before unpinning the old
2175 * This should only fail upon a hung GPU, in which case we
2176 * can safely continue.
2178 dev_priv->mm.interruptible = false;
2179 ret = i915_gem_object_finish_gpu(obj);
2180 dev_priv->mm.interruptible = was_interruptible;
2185 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_master_private *master_priv;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2191 if (!dev->primary->master)
2194 master_priv = dev->primary->master->driver_priv;
2195 if (!master_priv->sarea_priv)
2198 switch (intel_crtc->pipe) {
2200 master_priv->sarea_priv->pipeA_x = x;
2201 master_priv->sarea_priv->pipeA_y = y;
2204 master_priv->sarea_priv->pipeB_x = x;
2205 master_priv->sarea_priv->pipeB_y = y;
2213 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2214 struct drm_framebuffer *fb)
2216 struct drm_device *dev = crtc->dev;
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2219 struct drm_framebuffer *old_fb;
2224 DRM_ERROR("No FB bound\n");
2228 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2229 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2230 plane_name(intel_crtc->plane),
2231 INTEL_INFO(dev)->num_pipes);
2235 mutex_lock(&dev->struct_mutex);
2236 ret = intel_pin_and_fence_fb_obj(dev,
2237 to_intel_framebuffer(fb)->obj,
2240 mutex_unlock(&dev->struct_mutex);
2241 DRM_ERROR("pin & fence failed\n");
2245 /* Update pipe size and adjust fitter if needed */
2246 if (i915_fastboot) {
2247 I915_WRITE(PIPESRC(intel_crtc->pipe),
2248 ((crtc->mode.hdisplay - 1) << 16) |
2249 (crtc->mode.vdisplay - 1));
2250 if (!intel_crtc->config.pch_pfit.size &&
2251 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2252 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2253 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2254 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2255 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2259 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2261 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2262 mutex_unlock(&dev->struct_mutex);
2263 DRM_ERROR("failed to update base address\n");
2273 if (intel_crtc->active && old_fb != fb)
2274 intel_wait_for_vblank(dev, intel_crtc->pipe);
2275 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2278 intel_update_fbc(dev);
2279 intel_edp_psr_update(dev);
2280 mutex_unlock(&dev->struct_mutex);
2282 intel_crtc_update_sarea_pos(crtc, x, y);
2287 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2295 /* enable normal train */
2296 reg = FDI_TX_CTL(pipe);
2297 temp = I915_READ(reg);
2298 if (IS_IVYBRIDGE(dev)) {
2299 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2300 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2302 temp &= ~FDI_LINK_TRAIN_NONE;
2303 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2305 I915_WRITE(reg, temp);
2307 reg = FDI_RX_CTL(pipe);
2308 temp = I915_READ(reg);
2309 if (HAS_PCH_CPT(dev)) {
2310 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2311 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2313 temp &= ~FDI_LINK_TRAIN_NONE;
2314 temp |= FDI_LINK_TRAIN_NONE;
2316 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2318 /* wait one idle pattern time */
2322 /* IVB wants error correction enabled */
2323 if (IS_IVYBRIDGE(dev))
2324 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2325 FDI_FE_ERRC_ENABLE);
2328 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2330 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2333 static void ivb_modeset_global_resources(struct drm_device *dev)
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *pipe_B_crtc =
2337 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2338 struct intel_crtc *pipe_C_crtc =
2339 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2343 * When everything is off disable fdi C so that we could enable fdi B
2344 * with all lanes. Note that we don't care about enabled pipes without
2345 * an enabled pch encoder.
2347 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2348 !pipe_has_enabled_pch(pipe_C_crtc)) {
2349 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2350 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2352 temp = I915_READ(SOUTH_CHICKEN1);
2353 temp &= ~FDI_BC_BIFURCATION_SELECT;
2354 DRM_DEBUG_KMS("disabling fdi C rx\n");
2355 I915_WRITE(SOUTH_CHICKEN1, temp);
2359 /* The FDI link training functions for ILK/Ibexpeak. */
2360 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362 struct drm_device *dev = crtc->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 int pipe = intel_crtc->pipe;
2366 int plane = intel_crtc->plane;
2367 u32 reg, temp, tries;
2369 /* FDI needs bits from pipe & plane first */
2370 assert_pipe_enabled(dev_priv, pipe);
2371 assert_plane_enabled(dev_priv, plane);
2373 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 reg = FDI_RX_IMR(pipe);
2376 temp = I915_READ(reg);
2377 temp &= ~FDI_RX_SYMBOL_LOCK;
2378 temp &= ~FDI_RX_BIT_LOCK;
2379 I915_WRITE(reg, temp);
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2387 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_1;
2390 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2392 reg = FDI_RX_CTL(pipe);
2393 temp = I915_READ(reg);
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_PATTERN_1;
2396 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2401 /* Ironlake workaround, enable clock pointer after FDI enable*/
2402 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2403 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2404 FDI_RX_PHASE_SYNC_POINTER_EN);
2406 reg = FDI_RX_IIR(pipe);
2407 for (tries = 0; tries < 5; tries++) {
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2411 if ((temp & FDI_RX_BIT_LOCK)) {
2412 DRM_DEBUG_KMS("FDI train 1 done.\n");
2413 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2418 DRM_ERROR("FDI train 1 fail!\n");
2421 reg = FDI_TX_CTL(pipe);
2422 temp = I915_READ(reg);
2423 temp &= ~FDI_LINK_TRAIN_NONE;
2424 temp |= FDI_LINK_TRAIN_PATTERN_2;
2425 I915_WRITE(reg, temp);
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_2;
2431 I915_WRITE(reg, temp);
2436 reg = FDI_RX_IIR(pipe);
2437 for (tries = 0; tries < 5; tries++) {
2438 temp = I915_READ(reg);
2439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2441 if (temp & FDI_RX_SYMBOL_LOCK) {
2442 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2443 DRM_DEBUG_KMS("FDI train 2 done.\n");
2448 DRM_ERROR("FDI train 2 fail!\n");
2450 DRM_DEBUG_KMS("FDI train done\n");
2454 static const int snb_b_fdi_train_param[] = {
2455 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2456 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2457 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2458 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2461 /* The FDI link training functions for SNB/Cougarpoint. */
2462 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2464 struct drm_device *dev = crtc->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467 int pipe = intel_crtc->pipe;
2468 u32 reg, temp, i, retry;
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
2476 I915_WRITE(reg, temp);
2481 /* enable CPU FDI TX and PCH FDI RX */
2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2485 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2486 temp &= ~FDI_LINK_TRAIN_NONE;
2487 temp |= FDI_LINK_TRAIN_PATTERN_1;
2488 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2490 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2491 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2493 I915_WRITE(FDI_RX_MISC(pipe),
2494 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2510 for (i = 0; i < 4; i++) {
2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= snb_b_fdi_train_param[i];
2515 I915_WRITE(reg, temp);
2520 for (retry = 0; retry < 5; retry++) {
2521 reg = FDI_RX_IIR(pipe);
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524 if (temp & FDI_RX_BIT_LOCK) {
2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2535 DRM_ERROR("FDI train 1 fail!\n");
2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547 I915_WRITE(reg, temp);
2549 reg = FDI_RX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 if (HAS_PCH_CPT(dev)) {
2552 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2558 I915_WRITE(reg, temp);
2563 for (i = 0; i < 4; i++) {
2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 temp |= snb_b_fdi_train_param[i];
2568 I915_WRITE(reg, temp);
2573 for (retry = 0; retry < 5; retry++) {
2574 reg = FDI_RX_IIR(pipe);
2575 temp = I915_READ(reg);
2576 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2577 if (temp & FDI_RX_SYMBOL_LOCK) {
2578 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2579 DRM_DEBUG_KMS("FDI train 2 done.\n");
2588 DRM_ERROR("FDI train 2 fail!\n");
2590 DRM_DEBUG_KMS("FDI train done.\n");
2593 /* Manual link training for Ivy Bridge A0 parts */
2594 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
2600 u32 reg, temp, i, j;
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
2608 I915_WRITE(reg, temp);
2613 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2614 I915_READ(FDI_RX_IIR(pipe)));
2616 /* Try each vswing and preemphasis setting twice before moving on */
2617 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2618 /* disable first in case we need to retry */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622 temp &= ~FDI_TX_ENABLE;
2623 I915_WRITE(reg, temp);
2625 reg = FDI_RX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~FDI_LINK_TRAIN_AUTO;
2628 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2629 temp &= ~FDI_RX_ENABLE;
2630 I915_WRITE(reg, temp);
2632 /* enable CPU FDI TX and PCH FDI RX */
2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2636 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2637 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 temp |= snb_b_fdi_train_param[j/2];
2640 temp |= FDI_COMPOSITE_SYNC;
2641 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2643 I915_WRITE(FDI_RX_MISC(pipe),
2644 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2649 temp |= FDI_COMPOSITE_SYNC;
2650 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653 udelay(1); /* should be 0.5us */
2655 for (i = 0; i < 4; i++) {
2656 reg = FDI_RX_IIR(pipe);
2657 temp = I915_READ(reg);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2660 if (temp & FDI_RX_BIT_LOCK ||
2661 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2662 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2663 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2667 udelay(1); /* should be 0.5us */
2670 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2675 reg = FDI_TX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2679 I915_WRITE(reg, temp);
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685 I915_WRITE(reg, temp);
2688 udelay(2); /* should be 1.5us */
2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_RX_IIR(pipe);
2692 temp = I915_READ(reg);
2693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695 if (temp & FDI_RX_SYMBOL_LOCK ||
2696 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2697 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2698 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2702 udelay(2); /* should be 1.5us */
2705 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2709 DRM_DEBUG_KMS("FDI train done.\n");
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2714 struct drm_device *dev = intel_crtc->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int pipe = intel_crtc->pipe;
2720 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2721 reg = FDI_RX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2724 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2725 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2726 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2731 /* Switch from Rawclk to PCDclk */
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp | FDI_PCDCLK);
2738 /* Enable CPU FDI TX PLL, always on for Ironlake */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2742 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2751 struct drm_device *dev = intel_crtc->base.dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 int pipe = intel_crtc->pipe;
2756 /* Switch from PCDclk to Rawclk */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2761 /* Disable CPU FDI TX PLL */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2769 reg = FDI_RX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2773 /* Wait for the clocks to turn off. */
2778 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 int pipe = intel_crtc->pipe;
2786 /* disable CPU FDI tx and PCH FDI rx */
2787 reg = FDI_TX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~(0x7 << 16);
2795 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2796 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2801 /* Ironlake workaround, disable clock pointer after downing FDI */
2802 if (HAS_PCH_IBX(dev)) {
2803 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2806 /* still set train pattern 1 */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_NONE;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1;
2811 I915_WRITE(reg, temp);
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 if (HAS_PCH_CPT(dev)) {
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1;
2822 /* BPC in FDI rx is consistent with that in PIPECONF */
2823 temp &= ~(0x07 << 16);
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp);
2831 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2836 unsigned long flags;
2839 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2840 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843 spin_lock_irqsave(&dev->event_lock, flags);
2844 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2845 spin_unlock_irqrestore(&dev->event_lock, flags);
2850 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2852 struct drm_device *dev = crtc->dev;
2853 struct drm_i915_private *dev_priv = dev->dev_private;
2855 if (crtc->fb == NULL)
2858 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2860 wait_event(dev_priv->pending_flip_queue,
2861 !intel_crtc_has_pending_flip(crtc));
2863 mutex_lock(&dev->struct_mutex);
2864 intel_finish_fb(crtc->fb);
2865 mutex_unlock(&dev->struct_mutex);
2868 /* Program iCLKIP clock to the desired frequency */
2869 static void lpt_program_iclkip(struct drm_crtc *crtc)
2871 struct drm_device *dev = crtc->dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2876 mutex_lock(&dev_priv->dpio_lock);
2878 /* It is necessary to ungate the pixclk gate prior to programming
2879 * the divisors, and gate it back when it is done.
2881 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2883 /* Disable SSCCTL */
2884 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2885 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2889 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2890 if (crtc->mode.clock == 20000) {
2895 /* The iCLK virtual clock root frequency is in MHz,
2896 * but the crtc->mode.clock in in KHz. To get the divisors,
2897 * it is necessary to divide one by another, so we
2898 * convert the virtual clock precision to KHz here for higher
2901 u32 iclk_virtual_root_freq = 172800 * 1000;
2902 u32 iclk_pi_range = 64;
2903 u32 desired_divisor, msb_divisor_value, pi_value;
2905 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2906 msb_divisor_value = desired_divisor / iclk_pi_range;
2907 pi_value = desired_divisor % iclk_pi_range;
2910 divsel = msb_divisor_value - 2;
2911 phaseinc = pi_value;
2914 /* This should not happen with any sane values */
2915 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2916 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2917 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2918 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2920 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2927 /* Program SSCDIVINTPHASE6 */
2928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2937 /* Program SSCAUXDIV */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2943 /* Enable modulator and associated divider */
2944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2945 temp &= ~SBI_SSCCTL_DISABLE;
2946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2948 /* Wait for initialization time */
2951 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2953 mutex_unlock(&dev_priv->dpio_lock);
2956 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2957 enum pipe pch_transcoder)
2959 struct drm_device *dev = crtc->base.dev;
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2963 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2964 I915_READ(HTOTAL(cpu_transcoder)));
2965 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2966 I915_READ(HBLANK(cpu_transcoder)));
2967 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2968 I915_READ(HSYNC(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2971 I915_READ(VTOTAL(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2973 I915_READ(VBLANK(cpu_transcoder)));
2974 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2975 I915_READ(VSYNC(cpu_transcoder)));
2976 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2977 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2981 * Enable PCH resources required for PCH ports:
2983 * - FDI training & RX/TX
2984 * - update transcoder timings
2985 * - DP transcoding bits
2988 static void ironlake_pch_enable(struct drm_crtc *crtc)
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2993 int pipe = intel_crtc->pipe;
2996 assert_pch_transcoder_disabled(dev_priv, pipe);
2998 /* Write the TU size bits before fdi link training, so that error
2999 * detection works. */
3000 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3003 /* For PCH output, training FDI link */
3004 dev_priv->display.fdi_link_train(crtc);
3006 /* We need to program the right clock selection before writing the pixel
3007 * mutliplier into the DPLL. */
3008 if (HAS_PCH_CPT(dev)) {
3011 temp = I915_READ(PCH_DPLL_SEL);
3012 temp |= TRANS_DPLL_ENABLE(pipe);
3013 sel = TRANS_DPLLB_SEL(pipe);
3014 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3018 I915_WRITE(PCH_DPLL_SEL, temp);
3021 /* XXX: pch pll's can be enabled any time before we enable the PCH
3022 * transcoder, and we actually should do this to not upset any PCH
3023 * transcoder that already use the clock when we share it.
3025 * Note that enable_shared_dpll tries to do the right thing, but
3026 * get_shared_dpll unconditionally resets the pll - we need that to have
3027 * the right LVDS enable sequence. */
3028 ironlake_enable_shared_dpll(intel_crtc);
3030 /* set transcoder timing, panel must allow it */
3031 assert_panel_unlocked(dev_priv, pipe);
3032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3034 intel_fdi_normal_train(crtc);
3036 /* For PCH DP, enable TRANS_DP_CTL */
3037 if (HAS_PCH_CPT(dev) &&
3038 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3039 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3040 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3041 reg = TRANS_DP_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3044 TRANS_DP_SYNC_MASK |
3046 temp |= (TRANS_DP_OUTPUT_ENABLE |
3047 TRANS_DP_ENH_FRAMING);
3048 temp |= bpc << 9; /* same format but at 11:9 */
3050 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3051 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3052 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3053 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3055 switch (intel_trans_dp_port_sel(crtc)) {
3057 temp |= TRANS_DP_PORT_SEL_B;
3060 temp |= TRANS_DP_PORT_SEL_C;
3063 temp |= TRANS_DP_PORT_SEL_D;
3069 I915_WRITE(reg, temp);
3072 ironlake_enable_pch_transcoder(dev_priv, pipe);
3075 static void lpt_pch_enable(struct drm_crtc *crtc)
3077 struct drm_device *dev = crtc->dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3082 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3084 lpt_program_iclkip(crtc);
3086 /* Set transcoder timing. */
3087 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3089 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3092 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3094 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3099 if (pll->refcount == 0) {
3100 WARN(1, "bad %s refcount\n", pll->name);
3104 if (--pll->refcount == 0) {
3106 WARN_ON(pll->active);
3109 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3112 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3115 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3116 enum intel_dpll_id i;
3119 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3120 crtc->base.base.id, pll->name);
3121 intel_put_shared_dpll(crtc);
3124 if (HAS_PCH_IBX(dev_priv->dev)) {
3125 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3126 i = (enum intel_dpll_id) crtc->pipe;
3127 pll = &dev_priv->shared_dplls[i];
3129 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3130 crtc->base.base.id, pll->name);
3135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3136 pll = &dev_priv->shared_dplls[i];
3138 /* Only want to check enabled timings first */
3139 if (pll->refcount == 0)
3142 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3143 sizeof(pll->hw_state)) == 0) {
3144 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3146 pll->name, pll->refcount, pll->active);
3152 /* Ok no matching timings, maybe there's a free one? */
3153 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3154 pll = &dev_priv->shared_dplls[i];
3155 if (pll->refcount == 0) {
3156 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3157 crtc->base.base.id, pll->name);
3165 crtc->config.shared_dpll = i;
3166 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3167 pipe_name(crtc->pipe));
3169 if (pll->active == 0) {
3170 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3171 sizeof(pll->hw_state));
3173 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3175 assert_shared_dpll_disabled(dev_priv, pll);
3177 pll->mode_set(dev_priv, pll);
3184 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 int dslreg = PIPEDSL(pipe);
3190 temp = I915_READ(dslreg);
3192 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3193 if (wait_for(I915_READ(dslreg) != temp, 5))
3194 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3198 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3200 struct drm_device *dev = crtc->base.dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 int pipe = crtc->pipe;
3204 if (crtc->config.pch_pfit.size) {
3205 /* Force use of hard-coded filter coefficients
3206 * as some pre-programmed values are broken,
3209 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3210 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3211 PF_PIPE_SEL_IVB(pipe));
3213 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3214 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3215 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3219 static void intel_enable_planes(struct drm_crtc *crtc)
3221 struct drm_device *dev = crtc->dev;
3222 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3223 struct intel_plane *intel_plane;
3225 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3226 if (intel_plane->pipe == pipe)
3227 intel_plane_restore(&intel_plane->base);
3230 static void intel_disable_planes(struct drm_crtc *crtc)
3232 struct drm_device *dev = crtc->dev;
3233 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3234 struct intel_plane *intel_plane;
3236 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3237 if (intel_plane->pipe == pipe)
3238 intel_plane_disable(&intel_plane->base);
3241 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3243 struct drm_device *dev = crtc->dev;
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3246 struct intel_encoder *encoder;
3247 int pipe = intel_crtc->pipe;
3248 int plane = intel_crtc->plane;
3250 WARN_ON(!crtc->enabled);
3252 if (intel_crtc->active)
3255 intel_crtc->active = true;
3257 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3258 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3260 intel_update_watermarks(dev);
3262 for_each_encoder_on_crtc(dev, crtc, encoder)
3263 if (encoder->pre_enable)
3264 encoder->pre_enable(encoder);
3266 if (intel_crtc->config.has_pch_encoder) {
3267 /* Note: FDI PLL enabling _must_ be done before we enable the
3268 * cpu pipes, hence this is separate from all the other fdi/pch
3270 ironlake_fdi_pll_enable(intel_crtc);
3272 assert_fdi_tx_disabled(dev_priv, pipe);
3273 assert_fdi_rx_disabled(dev_priv, pipe);
3276 ironlake_pfit_enable(intel_crtc);
3279 * On ILK+ LUT must be loaded before the pipe is running but with
3282 intel_crtc_load_lut(crtc);
3284 intel_enable_pipe(dev_priv, pipe,
3285 intel_crtc->config.has_pch_encoder);
3286 intel_enable_plane(dev_priv, plane, pipe);
3287 intel_enable_planes(crtc);
3288 intel_crtc_update_cursor(crtc, true);
3290 if (intel_crtc->config.has_pch_encoder)
3291 ironlake_pch_enable(crtc);
3293 mutex_lock(&dev->struct_mutex);
3294 intel_update_fbc(dev);
3295 mutex_unlock(&dev->struct_mutex);
3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 encoder->enable(encoder);
3300 if (HAS_PCH_CPT(dev))
3301 cpt_verify_modeset(dev, intel_crtc->pipe);
3304 * There seems to be a race in PCH platform hw (at least on some
3305 * outputs) where an enabled pipe still completes any pageflip right
3306 * away (as if the pipe is off) instead of waiting for vblank. As soon
3307 * as the first vblank happend, everything works as expected. Hence just
3308 * wait for one vblank before returning to avoid strange things
3311 intel_wait_for_vblank(dev, intel_crtc->pipe);
3314 /* IPS only exists on ULT machines and is tied to pipe A. */
3315 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3317 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3320 static void hsw_enable_ips(struct intel_crtc *crtc)
3322 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3324 if (!crtc->config.ips_enabled)
3327 /* We can only enable IPS after we enable a plane and wait for a vblank.
3328 * We guarantee that the plane is enabled by calling intel_enable_ips
3329 * only after intel_enable_plane. And intel_enable_plane already waits
3330 * for a vblank, so all we need to do here is to enable the IPS bit. */
3331 assert_plane_enabled(dev_priv, crtc->plane);
3332 I915_WRITE(IPS_CTL, IPS_ENABLE);
3335 static void hsw_disable_ips(struct intel_crtc *crtc)
3337 struct drm_device *dev = crtc->base.dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3340 if (!crtc->config.ips_enabled)
3343 assert_plane_enabled(dev_priv, crtc->plane);
3344 I915_WRITE(IPS_CTL, 0);
3346 /* We need to wait for a vblank before we can disable the plane. */
3347 intel_wait_for_vblank(dev, crtc->pipe);
3350 static void haswell_crtc_enable(struct drm_crtc *crtc)
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 struct intel_encoder *encoder;
3356 int pipe = intel_crtc->pipe;
3357 int plane = intel_crtc->plane;
3359 WARN_ON(!crtc->enabled);
3361 if (intel_crtc->active)
3364 intel_crtc->active = true;
3366 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3367 if (intel_crtc->config.has_pch_encoder)
3368 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3370 intel_update_watermarks(dev);
3372 if (intel_crtc->config.has_pch_encoder)
3373 dev_priv->display.fdi_link_train(crtc);
3375 for_each_encoder_on_crtc(dev, crtc, encoder)
3376 if (encoder->pre_enable)
3377 encoder->pre_enable(encoder);
3379 intel_ddi_enable_pipe_clock(intel_crtc);
3381 ironlake_pfit_enable(intel_crtc);
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3387 intel_crtc_load_lut(crtc);
3389 intel_ddi_set_pipe_settings(crtc);
3390 intel_ddi_enable_transcoder_func(crtc);
3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
3394 intel_enable_plane(dev_priv, plane, pipe);
3395 intel_enable_planes(crtc);
3396 intel_crtc_update_cursor(crtc, true);
3398 hsw_enable_ips(intel_crtc);
3400 if (intel_crtc->config.has_pch_encoder)
3401 lpt_pch_enable(crtc);
3403 mutex_lock(&dev->struct_mutex);
3404 intel_update_fbc(dev);
3405 mutex_unlock(&dev->struct_mutex);
3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 encoder->enable(encoder);
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
3421 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3423 struct drm_device *dev = crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = crtc->pipe;
3427 /* To avoid upsetting the power well on haswell only disable the pfit if
3428 * it's in use. The hw state code will make sure we get this right. */
3429 if (crtc->config.pch_pfit.size) {
3430 I915_WRITE(PF_CTL(pipe), 0);
3431 I915_WRITE(PF_WIN_POS(pipe), 0);
3432 I915_WRITE(PF_WIN_SZ(pipe), 0);
3436 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3438 struct drm_device *dev = crtc->dev;
3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3441 struct intel_encoder *encoder;
3442 int pipe = intel_crtc->pipe;
3443 int plane = intel_crtc->plane;
3447 if (!intel_crtc->active)
3450 for_each_encoder_on_crtc(dev, crtc, encoder)
3451 encoder->disable(encoder);
3453 intel_crtc_wait_for_pending_flips(crtc);
3454 drm_vblank_off(dev, pipe);
3456 if (dev_priv->fbc.plane == plane)
3457 intel_disable_fbc(dev);
3459 intel_crtc_update_cursor(crtc, false);
3460 intel_disable_planes(crtc);
3461 intel_disable_plane(dev_priv, plane, pipe);
3463 if (intel_crtc->config.has_pch_encoder)
3464 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3466 intel_disable_pipe(dev_priv, pipe);
3468 ironlake_pfit_disable(intel_crtc);
3470 for_each_encoder_on_crtc(dev, crtc, encoder)
3471 if (encoder->post_disable)
3472 encoder->post_disable(encoder);
3474 if (intel_crtc->config.has_pch_encoder) {
3475 ironlake_fdi_disable(crtc);
3477 ironlake_disable_pch_transcoder(dev_priv, pipe);
3478 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3480 if (HAS_PCH_CPT(dev)) {
3481 /* disable TRANS_DP_CTL */
3482 reg = TRANS_DP_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3485 TRANS_DP_PORT_SEL_MASK);
3486 temp |= TRANS_DP_PORT_SEL_NONE;
3487 I915_WRITE(reg, temp);
3489 /* disable DPLL_SEL */
3490 temp = I915_READ(PCH_DPLL_SEL);
3491 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3492 I915_WRITE(PCH_DPLL_SEL, temp);
3495 /* disable PCH DPLL */
3496 intel_disable_shared_dpll(intel_crtc);
3498 ironlake_fdi_pll_disable(intel_crtc);
3501 intel_crtc->active = false;
3502 intel_update_watermarks(dev);
3504 mutex_lock(&dev->struct_mutex);
3505 intel_update_fbc(dev);
3506 mutex_unlock(&dev->struct_mutex);
3509 static void haswell_crtc_disable(struct drm_crtc *crtc)
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3517 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3519 if (!intel_crtc->active)
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3525 intel_crtc_wait_for_pending_flips(crtc);
3526 drm_vblank_off(dev, pipe);
3528 /* FBC must be disabled before disabling the plane on HSW. */
3529 if (dev_priv->fbc.plane == plane)
3530 intel_disable_fbc(dev);
3532 hsw_disable_ips(intel_crtc);
3534 intel_crtc_update_cursor(crtc, false);
3535 intel_disable_planes(crtc);
3536 intel_disable_plane(dev_priv, plane, pipe);
3538 if (intel_crtc->config.has_pch_encoder)
3539 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3540 intel_disable_pipe(dev_priv, pipe);
3542 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3544 ironlake_pfit_disable(intel_crtc);
3546 intel_ddi_disable_pipe_clock(intel_crtc);
3548 for_each_encoder_on_crtc(dev, crtc, encoder)
3549 if (encoder->post_disable)
3550 encoder->post_disable(encoder);
3552 if (intel_crtc->config.has_pch_encoder) {
3553 lpt_disable_pch_transcoder(dev_priv);
3554 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3555 intel_ddi_fdi_disable(crtc);
3558 intel_crtc->active = false;
3559 intel_update_watermarks(dev);
3561 mutex_lock(&dev->struct_mutex);
3562 intel_update_fbc(dev);
3563 mutex_unlock(&dev->struct_mutex);
3566 static void ironlake_crtc_off(struct drm_crtc *crtc)
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 intel_put_shared_dpll(intel_crtc);
3572 static void haswell_crtc_off(struct drm_crtc *crtc)
3574 intel_ddi_put_crtc_pll(crtc);
3577 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579 if (!enable && intel_crtc->overlay) {
3580 struct drm_device *dev = intel_crtc->base.dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3583 mutex_lock(&dev->struct_mutex);
3584 dev_priv->mm.interruptible = false;
3585 (void) intel_overlay_switch_off(intel_crtc->overlay);
3586 dev_priv->mm.interruptible = true;
3587 mutex_unlock(&dev->struct_mutex);
3590 /* Let userspace switch the overlay on again. In most cases userspace
3591 * has to recompute where to put it anyway.
3596 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3597 * cursor plane briefly if not already running after enabling the display
3599 * This workaround avoids occasional blank screens when self refresh is
3603 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3605 u32 cntl = I915_READ(CURCNTR(pipe));
3607 if ((cntl & CURSOR_MODE) == 0) {
3608 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3610 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3611 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3612 intel_wait_for_vblank(dev_priv->dev, pipe);
3613 I915_WRITE(CURCNTR(pipe), cntl);
3614 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3615 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3619 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3621 struct drm_device *dev = crtc->base.dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc_config *pipe_config = &crtc->config;
3625 if (!crtc->config.gmch_pfit.control)
3629 * The panel fitter should only be adjusted whilst the pipe is disabled,
3630 * according to register description and PRM.
3632 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3633 assert_pipe_disabled(dev_priv, crtc->pipe);
3635 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3636 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3638 /* Border color in case we don't scale up to the full screen. Black by
3639 * default, change to something else for debugging. */
3640 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3643 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648 struct intel_encoder *encoder;
3649 int pipe = intel_crtc->pipe;
3650 int plane = intel_crtc->plane;
3652 WARN_ON(!crtc->enabled);
3654 if (intel_crtc->active)
3657 intel_crtc->active = true;
3658 intel_update_watermarks(dev);
3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3661 if (encoder->pre_pll_enable)
3662 encoder->pre_pll_enable(encoder);
3664 vlv_enable_pll(intel_crtc);
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->pre_enable)
3668 encoder->pre_enable(encoder);
3670 i9xx_pfit_enable(intel_crtc);
3672 intel_crtc_load_lut(crtc);
3674 intel_enable_pipe(dev_priv, pipe, false);
3675 intel_enable_plane(dev_priv, plane, pipe);
3676 intel_enable_planes(crtc);
3677 intel_crtc_update_cursor(crtc, true);
3679 intel_update_fbc(dev);
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3685 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690 struct intel_encoder *encoder;
3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
3694 WARN_ON(!crtc->enabled);
3696 if (intel_crtc->active)
3699 intel_crtc->active = true;
3700 intel_update_watermarks(dev);
3702 for_each_encoder_on_crtc(dev, crtc, encoder)
3703 if (encoder->pre_enable)
3704 encoder->pre_enable(encoder);
3706 i9xx_enable_pll(intel_crtc);
3708 i9xx_pfit_enable(intel_crtc);
3710 intel_crtc_load_lut(crtc);
3712 intel_enable_pipe(dev_priv, pipe, false);
3713 intel_enable_plane(dev_priv, plane, pipe);
3714 intel_enable_planes(crtc);
3715 /* The fixup needs to happen before cursor is enabled */
3717 g4x_fixup_plane(dev_priv, pipe);
3718 intel_crtc_update_cursor(crtc, true);
3720 /* Give the overlay scaler a chance to enable if it's on this pipe */
3721 intel_crtc_dpms_overlay(intel_crtc, true);
3723 intel_update_fbc(dev);
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3729 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3731 struct drm_device *dev = crtc->base.dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3734 if (!crtc->config.gmch_pfit.control)
3737 assert_pipe_disabled(dev_priv, crtc->pipe);
3739 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3740 I915_READ(PFIT_CONTROL));
3741 I915_WRITE(PFIT_CONTROL, 0);
3744 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3746 struct drm_device *dev = crtc->dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3749 struct intel_encoder *encoder;
3750 int pipe = intel_crtc->pipe;
3751 int plane = intel_crtc->plane;
3753 if (!intel_crtc->active)
3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 encoder->disable(encoder);
3759 /* Give the overlay scaler a chance to disable if it's on this pipe */
3760 intel_crtc_wait_for_pending_flips(crtc);
3761 drm_vblank_off(dev, pipe);
3763 if (dev_priv->fbc.plane == plane)
3764 intel_disable_fbc(dev);
3766 intel_crtc_dpms_overlay(intel_crtc, false);
3767 intel_crtc_update_cursor(crtc, false);
3768 intel_disable_planes(crtc);
3769 intel_disable_plane(dev_priv, plane, pipe);
3771 intel_disable_pipe(dev_priv, pipe);
3773 i9xx_pfit_disable(intel_crtc);
3775 for_each_encoder_on_crtc(dev, crtc, encoder)
3776 if (encoder->post_disable)
3777 encoder->post_disable(encoder);
3779 i9xx_disable_pll(dev_priv, pipe);
3781 intel_crtc->active = false;
3782 intel_update_fbc(dev);
3783 intel_update_watermarks(dev);
3786 static void i9xx_crtc_off(struct drm_crtc *crtc)
3790 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_master_private *master_priv;
3795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796 int pipe = intel_crtc->pipe;
3798 if (!dev->primary->master)
3801 master_priv = dev->primary->master->driver_priv;
3802 if (!master_priv->sarea_priv)
3807 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3808 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3812 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3821 * Sets the power management mode of the pipe and plane.
3823 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_encoder *intel_encoder;
3828 bool enable = false;
3830 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3831 enable |= intel_encoder->connectors_active;
3834 dev_priv->display.crtc_enable(crtc);
3836 dev_priv->display.crtc_disable(crtc);
3838 intel_crtc_update_sarea(crtc, enable);
3841 static void intel_crtc_disable(struct drm_crtc *crtc)
3843 struct drm_device *dev = crtc->dev;
3844 struct drm_connector *connector;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848 /* crtc should still be enabled when we disable it. */
3849 WARN_ON(!crtc->enabled);
3851 dev_priv->display.crtc_disable(crtc);
3852 intel_crtc->eld_vld = false;
3853 intel_crtc_update_sarea(crtc, false);
3854 dev_priv->display.off(crtc);
3856 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3857 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3860 mutex_lock(&dev->struct_mutex);
3861 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3862 mutex_unlock(&dev->struct_mutex);
3866 /* Update computed state. */
3867 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3868 if (!connector->encoder || !connector->encoder->crtc)
3871 if (connector->encoder->crtc != crtc)
3874 connector->dpms = DRM_MODE_DPMS_OFF;
3875 to_intel_encoder(connector->encoder)->connectors_active = false;
3879 void intel_encoder_destroy(struct drm_encoder *encoder)
3881 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3883 drm_encoder_cleanup(encoder);
3884 kfree(intel_encoder);
3887 /* Simple dpms helper for encoders with just one connector, no cloning and only
3888 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3889 * state of the entire output pipe. */
3890 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3892 if (mode == DRM_MODE_DPMS_ON) {
3893 encoder->connectors_active = true;
3895 intel_crtc_update_dpms(encoder->base.crtc);
3897 encoder->connectors_active = false;
3899 intel_crtc_update_dpms(encoder->base.crtc);
3903 /* Cross check the actual hw state with our own modeset state tracking (and it's
3904 * internal consistency). */
3905 static void intel_connector_check_state(struct intel_connector *connector)
3907 if (connector->get_hw_state(connector)) {
3908 struct intel_encoder *encoder = connector->encoder;
3909 struct drm_crtc *crtc;
3910 bool encoder_enabled;
3913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3914 connector->base.base.id,
3915 drm_get_connector_name(&connector->base));
3917 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3918 "wrong connector dpms state\n");
3919 WARN(connector->base.encoder != &encoder->base,
3920 "active connector not linked to encoder\n");
3921 WARN(!encoder->connectors_active,
3922 "encoder->connectors_active not set\n");
3924 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3925 WARN(!encoder_enabled, "encoder not enabled\n");
3926 if (WARN_ON(!encoder->base.crtc))
3929 crtc = encoder->base.crtc;
3931 WARN(!crtc->enabled, "crtc not enabled\n");
3932 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3933 WARN(pipe != to_intel_crtc(crtc)->pipe,
3934 "encoder active on the wrong pipe\n");
3938 /* Even simpler default implementation, if there's really no special case to
3940 void intel_connector_dpms(struct drm_connector *connector, int mode)
3942 struct intel_encoder *encoder = intel_attached_encoder(connector);
3944 /* All the simple cases only support two dpms states. */
3945 if (mode != DRM_MODE_DPMS_ON)
3946 mode = DRM_MODE_DPMS_OFF;
3948 if (mode == connector->dpms)
3951 connector->dpms = mode;
3953 /* Only need to change hw state when actually enabled */
3954 if (encoder->base.crtc)
3955 intel_encoder_dpms(encoder, mode);
3957 WARN_ON(encoder->connectors_active != false);
3959 intel_modeset_check_state(connector->dev);
3962 /* Simple connector->get_hw_state implementation for encoders that support only
3963 * one connector and no cloning and hence the encoder state determines the state
3964 * of the connector. */
3965 bool intel_connector_get_hw_state(struct intel_connector *connector)
3968 struct intel_encoder *encoder = connector->encoder;
3970 return encoder->get_hw_state(encoder, &pipe);
3973 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3974 struct intel_crtc_config *pipe_config)
3976 struct drm_i915_private *dev_priv = dev->dev_private;
3977 struct intel_crtc *pipe_B_crtc =
3978 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3980 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3982 if (pipe_config->fdi_lanes > 4) {
3983 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3984 pipe_name(pipe), pipe_config->fdi_lanes);
3988 if (IS_HASWELL(dev)) {
3989 if (pipe_config->fdi_lanes > 2) {
3990 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3991 pipe_config->fdi_lanes);
3998 if (INTEL_INFO(dev)->num_pipes == 2)
4001 /* Ivybridge 3 pipe is really complicated */
4006 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4007 pipe_config->fdi_lanes > 2) {
4008 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4009 pipe_name(pipe), pipe_config->fdi_lanes);
4014 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4015 pipe_B_crtc->config.fdi_lanes <= 2) {
4016 if (pipe_config->fdi_lanes > 2) {
4017 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4018 pipe_name(pipe), pipe_config->fdi_lanes);
4022 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4032 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4033 struct intel_crtc_config *pipe_config)
4035 struct drm_device *dev = intel_crtc->base.dev;
4036 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4037 int lane, link_bw, fdi_dotclock;
4038 bool setup_ok, needs_recompute = false;
4041 /* FDI is a binary signal running at ~2.7GHz, encoding
4042 * each output octet as 10 bits. The actual frequency
4043 * is stored as a divider into a 100MHz clock, and the
4044 * mode pixel clock is stored in units of 1KHz.
4045 * Hence the bw of each lane in terms of the mode signal
4048 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4050 fdi_dotclock = adjusted_mode->clock;
4051 fdi_dotclock /= pipe_config->pixel_multiplier;
4053 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4054 pipe_config->pipe_bpp);
4056 pipe_config->fdi_lanes = lane;
4058 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4059 link_bw, &pipe_config->fdi_m_n);
4061 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4062 intel_crtc->pipe, pipe_config);
4063 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4064 pipe_config->pipe_bpp -= 2*3;
4065 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4066 pipe_config->pipe_bpp);
4067 needs_recompute = true;
4068 pipe_config->bw_constrained = true;
4073 if (needs_recompute)
4076 return setup_ok ? 0 : -EINVAL;
4079 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4080 struct intel_crtc_config *pipe_config)
4082 pipe_config->ips_enabled = i915_enable_ips &&
4083 hsw_crtc_supports_ips(crtc) &&
4084 pipe_config->pipe_bpp <= 24;
4087 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4088 struct intel_crtc_config *pipe_config)
4090 struct drm_device *dev = crtc->base.dev;
4091 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4093 if (HAS_PCH_SPLIT(dev)) {
4094 /* FDI link clock is fixed at 2.7G */
4095 if (pipe_config->requested_mode.clock * 3
4096 > IRONLAKE_FDI_FREQ * 4)
4100 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4101 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4103 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4104 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4107 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4108 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4109 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4110 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4112 pipe_config->pipe_bpp = 8*3;
4116 hsw_compute_ips_config(crtc, pipe_config);
4118 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4119 * clock survives for now. */
4120 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4121 pipe_config->shared_dpll = crtc->config.shared_dpll;
4123 if (pipe_config->has_pch_encoder)
4124 return ironlake_fdi_compute_config(crtc, pipe_config);
4129 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4131 return 400000; /* FIXME */
4134 static int i945_get_display_clock_speed(struct drm_device *dev)
4139 static int i915_get_display_clock_speed(struct drm_device *dev)
4144 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4149 static int pnv_get_display_clock_speed(struct drm_device *dev)
4153 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4155 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4156 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4158 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4160 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4162 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4165 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4166 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4168 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4173 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4177 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4179 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4182 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4183 case GC_DISPLAY_CLOCK_333_MHZ:
4186 case GC_DISPLAY_CLOCK_190_200_MHZ:
4192 static int i865_get_display_clock_speed(struct drm_device *dev)
4197 static int i855_get_display_clock_speed(struct drm_device *dev)
4200 /* Assume that the hardware is in the high speed state. This
4201 * should be the default.
4203 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4204 case GC_CLOCK_133_200:
4205 case GC_CLOCK_100_200:
4207 case GC_CLOCK_166_250:
4209 case GC_CLOCK_100_133:
4213 /* Shouldn't happen */
4217 static int i830_get_display_clock_speed(struct drm_device *dev)
4223 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4225 while (*num > DATA_LINK_M_N_MASK ||
4226 *den > DATA_LINK_M_N_MASK) {
4232 static void compute_m_n(unsigned int m, unsigned int n,
4233 uint32_t *ret_m, uint32_t *ret_n)
4235 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4236 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4237 intel_reduce_m_n_ratio(ret_m, ret_n);
4241 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4242 int pixel_clock, int link_clock,
4243 struct intel_link_m_n *m_n)
4247 compute_m_n(bits_per_pixel * pixel_clock,
4248 link_clock * nlanes * 8,
4249 &m_n->gmch_m, &m_n->gmch_n);
4251 compute_m_n(pixel_clock, link_clock,
4252 &m_n->link_m, &m_n->link_n);
4255 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4257 if (i915_panel_use_ssc >= 0)
4258 return i915_panel_use_ssc != 0;
4259 return dev_priv->vbt.lvds_use_ssc
4260 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4263 static int vlv_get_refclk(struct drm_crtc *crtc)
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 int refclk = 27000; /* for DP & HDMI */
4269 return 100000; /* only one validated so far */
4271 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4273 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4274 if (intel_panel_use_ssc(dev_priv))
4278 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4285 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4287 struct drm_device *dev = crtc->dev;
4288 struct drm_i915_private *dev_priv = dev->dev_private;
4291 if (IS_VALLEYVIEW(dev)) {
4292 refclk = vlv_get_refclk(crtc);
4293 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4294 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4295 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4296 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4298 } else if (!IS_GEN2(dev)) {
4307 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4309 return (1 << dpll->n) << 16 | dpll->m2;
4312 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4314 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4317 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4318 intel_clock_t *reduced_clock)
4320 struct drm_device *dev = crtc->base.dev;
4321 struct drm_i915_private *dev_priv = dev->dev_private;
4322 int pipe = crtc->pipe;
4325 if (IS_PINEVIEW(dev)) {
4326 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4328 fp2 = pnv_dpll_compute_fp(reduced_clock);
4330 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4332 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4335 I915_WRITE(FP0(pipe), fp);
4336 crtc->config.dpll_hw_state.fp0 = fp;
4338 crtc->lowfreq_avail = false;
4339 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4340 reduced_clock && i915_powersave) {
4341 I915_WRITE(FP1(pipe), fp2);
4342 crtc->config.dpll_hw_state.fp1 = fp2;
4343 crtc->lowfreq_avail = true;
4345 I915_WRITE(FP1(pipe), fp);
4346 crtc->config.dpll_hw_state.fp1 = fp;
4350 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4355 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4356 * and set it to a reasonable value instead.
4358 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4359 reg_val &= 0xffffff00;
4360 reg_val |= 0x00000030;
4361 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4363 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4364 reg_val &= 0x8cffffff;
4365 reg_val = 0x8c000000;
4366 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4368 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4369 reg_val &= 0xffffff00;
4370 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4372 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4373 reg_val &= 0x00ffffff;
4374 reg_val |= 0xb0000000;
4375 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4378 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4379 struct intel_link_m_n *m_n)
4381 struct drm_device *dev = crtc->base.dev;
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 int pipe = crtc->pipe;
4385 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4386 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4387 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4388 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4391 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4392 struct intel_link_m_n *m_n)
4394 struct drm_device *dev = crtc->base.dev;
4395 struct drm_i915_private *dev_priv = dev->dev_private;
4396 int pipe = crtc->pipe;
4397 enum transcoder transcoder = crtc->config.cpu_transcoder;
4399 if (INTEL_INFO(dev)->gen >= 5) {
4400 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4401 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4402 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4403 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4405 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4406 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4407 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4408 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4412 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4414 if (crtc->config.has_pch_encoder)
4415 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4417 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4420 static void vlv_update_pll(struct intel_crtc *crtc)
4422 struct drm_device *dev = crtc->base.dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 int pipe = crtc->pipe;
4426 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4427 u32 coreclk, reg_val, dpll_md;
4429 mutex_lock(&dev_priv->dpio_lock);
4431 bestn = crtc->config.dpll.n;
4432 bestm1 = crtc->config.dpll.m1;
4433 bestm2 = crtc->config.dpll.m2;
4434 bestp1 = crtc->config.dpll.p1;
4435 bestp2 = crtc->config.dpll.p2;
4437 /* See eDP HDMI DPIO driver vbios notes doc */
4439 /* PLL B needs special handling */
4441 vlv_pllb_recal_opamp(dev_priv);
4443 /* Set up Tx target for periodic Rcomp update */
4444 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4446 /* Disable target IRef on PLL */
4447 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4448 reg_val &= 0x00ffffff;
4449 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4451 /* Disable fast lock */
4452 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4454 /* Set idtafcrecal before PLL is enabled */
4455 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4456 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4457 mdiv |= ((bestn << DPIO_N_SHIFT));
4458 mdiv |= (1 << DPIO_K_SHIFT);
4461 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4462 * but we don't support that).
4463 * Note: don't use the DAC post divider as it seems unstable.
4465 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4466 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4468 mdiv |= DPIO_ENABLE_CALIBRATION;
4469 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4471 /* Set HBR and RBR LPF coefficients */
4472 if (crtc->config.port_clock == 162000 ||
4473 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4474 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4475 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4478 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4482 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4483 /* Use SSC source */
4485 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4490 } else { /* HDMI or VGA */
4491 /* Use bend source */
4493 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4496 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4500 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4501 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4502 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4503 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4504 coreclk |= 0x01000000;
4505 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4507 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4509 /* Enable DPIO clock input */
4510 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4511 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4513 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4515 dpll |= DPLL_VCO_ENABLE;
4516 crtc->config.dpll_hw_state.dpll = dpll;
4518 dpll_md = (crtc->config.pixel_multiplier - 1)
4519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4520 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4522 if (crtc->config.has_dp_encoder)
4523 intel_dp_set_m_n(crtc);
4525 mutex_unlock(&dev_priv->dpio_lock);
4528 static void i9xx_update_pll(struct intel_crtc *crtc,
4529 intel_clock_t *reduced_clock,
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct dpll *clock = &crtc->config.dpll;
4538 i9xx_update_pll_dividers(crtc, reduced_clock);
4540 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4541 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4543 dpll = DPLL_VGA_MODE_DIS;
4545 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4546 dpll |= DPLLB_MODE_LVDS;
4548 dpll |= DPLLB_MODE_DAC_SERIAL;
4550 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4551 dpll |= (crtc->config.pixel_multiplier - 1)
4552 << SDVO_MULTIPLIER_SHIFT_HIRES;
4556 dpll |= DPLL_SDVO_HIGH_SPEED;
4558 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4559 dpll |= DPLL_SDVO_HIGH_SPEED;
4561 /* compute bitmask from p1 value */
4562 if (IS_PINEVIEW(dev))
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4566 if (IS_G4X(dev) && reduced_clock)
4567 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4569 switch (clock->p2) {
4571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4577 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4580 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4583 if (INTEL_INFO(dev)->gen >= 4)
4584 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4586 if (crtc->config.sdvo_tv_clock)
4587 dpll |= PLL_REF_INPUT_TVCLKINBC;
4588 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4594 dpll |= DPLL_VCO_ENABLE;
4595 crtc->config.dpll_hw_state.dpll = dpll;
4597 if (INTEL_INFO(dev)->gen >= 4) {
4598 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4599 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4600 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4603 if (crtc->config.has_dp_encoder)
4604 intel_dp_set_m_n(crtc);
4607 static void i8xx_update_pll(struct intel_crtc *crtc,
4608 intel_clock_t *reduced_clock,
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4614 struct dpll *clock = &crtc->config.dpll;
4616 i9xx_update_pll_dividers(crtc, reduced_clock);
4618 dpll = DPLL_VGA_MODE_DIS;
4620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4621 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4624 dpll |= PLL_P1_DIVIDE_BY_TWO;
4626 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4628 dpll |= PLL_P2_DIVIDE_BY_4;
4631 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4632 dpll |= DPLL_DVO_2X_MODE;
4634 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4635 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4638 dpll |= PLL_REF_INPUT_DREFCLK;
4640 dpll |= DPLL_VCO_ENABLE;
4641 crtc->config.dpll_hw_state.dpll = dpll;
4644 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4646 struct drm_device *dev = intel_crtc->base.dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 enum pipe pipe = intel_crtc->pipe;
4649 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4650 struct drm_display_mode *adjusted_mode =
4651 &intel_crtc->config.adjusted_mode;
4652 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4653 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4655 /* We need to be careful not to changed the adjusted mode, for otherwise
4656 * the hw state checker will get angry at the mismatch. */
4657 crtc_vtotal = adjusted_mode->crtc_vtotal;
4658 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4660 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4661 /* the chip adds 2 halflines automatically */
4663 crtc_vblank_end -= 1;
4664 vsyncshift = adjusted_mode->crtc_hsync_start
4665 - adjusted_mode->crtc_htotal / 2;
4670 if (INTEL_INFO(dev)->gen > 3)
4671 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4673 I915_WRITE(HTOTAL(cpu_transcoder),
4674 (adjusted_mode->crtc_hdisplay - 1) |
4675 ((adjusted_mode->crtc_htotal - 1) << 16));
4676 I915_WRITE(HBLANK(cpu_transcoder),
4677 (adjusted_mode->crtc_hblank_start - 1) |
4678 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4679 I915_WRITE(HSYNC(cpu_transcoder),
4680 (adjusted_mode->crtc_hsync_start - 1) |
4681 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4683 I915_WRITE(VTOTAL(cpu_transcoder),
4684 (adjusted_mode->crtc_vdisplay - 1) |
4685 ((crtc_vtotal - 1) << 16));
4686 I915_WRITE(VBLANK(cpu_transcoder),
4687 (adjusted_mode->crtc_vblank_start - 1) |
4688 ((crtc_vblank_end - 1) << 16));
4689 I915_WRITE(VSYNC(cpu_transcoder),
4690 (adjusted_mode->crtc_vsync_start - 1) |
4691 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4693 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4694 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4695 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4697 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4698 (pipe == PIPE_B || pipe == PIPE_C))
4699 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4701 /* pipesrc controls the size that is scaled from, which should
4702 * always be the user's requested size.
4704 I915_WRITE(PIPESRC(pipe),
4705 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4708 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4709 struct intel_crtc_config *pipe_config)
4711 struct drm_device *dev = crtc->base.dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4716 tmp = I915_READ(HTOTAL(cpu_transcoder));
4717 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4718 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4719 tmp = I915_READ(HBLANK(cpu_transcoder));
4720 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4721 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4722 tmp = I915_READ(HSYNC(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4726 tmp = I915_READ(VTOTAL(cpu_transcoder));
4727 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4728 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4729 tmp = I915_READ(VBLANK(cpu_transcoder));
4730 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4731 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4732 tmp = I915_READ(VSYNC(cpu_transcoder));
4733 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4734 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4736 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4737 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4738 pipe_config->adjusted_mode.crtc_vtotal += 1;
4739 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4742 tmp = I915_READ(PIPESRC(crtc->pipe));
4743 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4744 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4747 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4748 struct intel_crtc_config *pipe_config)
4750 struct drm_crtc *crtc = &intel_crtc->base;
4752 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4753 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4754 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4755 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4757 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4758 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4759 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4760 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4762 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4764 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4765 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4768 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4770 struct drm_device *dev = intel_crtc->base.dev;
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4776 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4777 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4780 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4783 if (intel_crtc->config.requested_mode.clock >
4784 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4785 pipeconf |= PIPECONF_DOUBLE_WIDE;
4788 /* only g4x and later have fancy bpc/dither controls */
4789 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4790 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4791 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4792 pipeconf |= PIPECONF_DITHER_EN |
4793 PIPECONF_DITHER_TYPE_SP;
4795 switch (intel_crtc->config.pipe_bpp) {
4797 pipeconf |= PIPECONF_6BPC;
4800 pipeconf |= PIPECONF_8BPC;
4803 pipeconf |= PIPECONF_10BPC;
4806 /* Case prevented by intel_choose_pipe_bpp_dither. */
4811 if (HAS_PIPE_CXSR(dev)) {
4812 if (intel_crtc->lowfreq_avail) {
4813 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4814 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4816 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4820 if (!IS_GEN2(dev) &&
4821 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4822 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4824 pipeconf |= PIPECONF_PROGRESSIVE;
4826 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4827 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4829 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4830 POSTING_READ(PIPECONF(intel_crtc->pipe));
4833 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4835 struct drm_framebuffer *fb)
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4841 int pipe = intel_crtc->pipe;
4842 int plane = intel_crtc->plane;
4843 int refclk, num_connectors = 0;
4844 intel_clock_t clock, reduced_clock;
4846 bool ok, has_reduced_clock = false;
4847 bool is_lvds = false;
4848 struct intel_encoder *encoder;
4849 const intel_limit_t *limit;
4852 for_each_encoder_on_crtc(dev, crtc, encoder) {
4853 switch (encoder->type) {
4854 case INTEL_OUTPUT_LVDS:
4862 refclk = i9xx_get_refclk(crtc, num_connectors);
4865 * Returns a set of divisors for the desired target clock with the given
4866 * refclk, or FALSE. The returned values represent the clock equation:
4867 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4869 limit = intel_limit(crtc, refclk);
4870 ok = dev_priv->display.find_dpll(limit, crtc,
4871 intel_crtc->config.port_clock,
4872 refclk, NULL, &clock);
4873 if (!ok && !intel_crtc->config.clock_set) {
4874 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4878 /* Ensure that the cursor is valid for the new mode before changing... */
4879 intel_crtc_update_cursor(crtc, true);
4881 if (is_lvds && dev_priv->lvds_downclock_avail) {
4883 * Ensure we match the reduced clock's P to the target clock.
4884 * If the clocks don't match, we can't switch the display clock
4885 * by using the FP0/FP1. In such case we will disable the LVDS
4886 * downclock feature.
4889 dev_priv->display.find_dpll(limit, crtc,
4890 dev_priv->lvds_downclock,
4894 /* Compat-code for transition, will disappear. */
4895 if (!intel_crtc->config.clock_set) {
4896 intel_crtc->config.dpll.n = clock.n;
4897 intel_crtc->config.dpll.m1 = clock.m1;
4898 intel_crtc->config.dpll.m2 = clock.m2;
4899 intel_crtc->config.dpll.p1 = clock.p1;
4900 intel_crtc->config.dpll.p2 = clock.p2;
4904 i8xx_update_pll(intel_crtc,
4905 has_reduced_clock ? &reduced_clock : NULL,
4907 else if (IS_VALLEYVIEW(dev))
4908 vlv_update_pll(intel_crtc);
4910 i9xx_update_pll(intel_crtc,
4911 has_reduced_clock ? &reduced_clock : NULL,
4914 /* Set up the display plane register */
4915 dspcntr = DISPPLANE_GAMMA_ENABLE;
4917 if (!IS_VALLEYVIEW(dev)) {
4919 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4921 dspcntr |= DISPPLANE_SEL_PIPE_B;
4924 intel_set_pipe_timings(intel_crtc);
4926 /* pipesrc and dspsize control the size that is scaled from,
4927 * which should always be the user's requested size.
4929 I915_WRITE(DSPSIZE(plane),
4930 ((mode->vdisplay - 1) << 16) |
4931 (mode->hdisplay - 1));
4932 I915_WRITE(DSPPOS(plane), 0);
4934 i9xx_set_pipeconf(intel_crtc);
4936 I915_WRITE(DSPCNTR(plane), dspcntr);
4937 POSTING_READ(DSPCNTR(plane));
4939 ret = intel_pipe_set_base(crtc, x, y, fb);
4941 intel_update_watermarks(dev);
4946 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4947 struct intel_crtc_config *pipe_config)
4949 struct drm_device *dev = crtc->base.dev;
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4953 tmp = I915_READ(PFIT_CONTROL);
4954 if (!(tmp & PFIT_ENABLE))
4957 /* Check whether the pfit is attached to our pipe. */
4958 if (INTEL_INFO(dev)->gen < 4) {
4959 if (crtc->pipe != PIPE_B)
4962 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4966 pipe_config->gmch_pfit.control = tmp;
4967 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4968 if (INTEL_INFO(dev)->gen < 5)
4969 pipe_config->gmch_pfit.lvds_border_bits =
4970 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4973 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4974 struct intel_crtc_config *pipe_config)
4976 struct drm_device *dev = crtc->base.dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4980 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4981 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4983 tmp = I915_READ(PIPECONF(crtc->pipe));
4984 if (!(tmp & PIPECONF_ENABLE))
4987 intel_get_pipe_timings(crtc, pipe_config);
4989 i9xx_get_pfit_config(crtc, pipe_config);
4991 if (INTEL_INFO(dev)->gen >= 4) {
4992 tmp = I915_READ(DPLL_MD(crtc->pipe));
4993 pipe_config->pixel_multiplier =
4994 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4995 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4996 pipe_config->dpll_hw_state.dpll_md = tmp;
4997 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4998 tmp = I915_READ(DPLL(crtc->pipe));
4999 pipe_config->pixel_multiplier =
5000 ((tmp & SDVO_MULTIPLIER_MASK)
5001 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5003 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5004 * port and will be fixed up in the encoder->get_config
5006 pipe_config->pixel_multiplier = 1;
5008 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5009 if (!IS_VALLEYVIEW(dev)) {
5010 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5011 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5013 /* Mask out read-only status bits. */
5014 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5015 DPLL_PORTC_READY_MASK |
5016 DPLL_PORTB_READY_MASK);
5022 static void ironlake_init_pch_refclk(struct drm_device *dev)
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025 struct drm_mode_config *mode_config = &dev->mode_config;
5026 struct intel_encoder *encoder;
5028 bool has_lvds = false;
5029 bool has_cpu_edp = false;
5030 bool has_panel = false;
5031 bool has_ck505 = false;
5032 bool can_ssc = false;
5034 /* We need to take the global config into account */
5035 list_for_each_entry(encoder, &mode_config->encoder_list,
5037 switch (encoder->type) {
5038 case INTEL_OUTPUT_LVDS:
5042 case INTEL_OUTPUT_EDP:
5044 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5050 if (HAS_PCH_IBX(dev)) {
5051 has_ck505 = dev_priv->vbt.display_clock_mode;
5052 can_ssc = has_ck505;
5058 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5059 has_panel, has_lvds, has_ck505);
5061 /* Ironlake: try to setup display ref clock before DPLL
5062 * enabling. This is only under driver's control after
5063 * PCH B stepping, previous chipset stepping should be
5064 * ignoring this setting.
5066 val = I915_READ(PCH_DREF_CONTROL);
5068 /* As we must carefully and slowly disable/enable each source in turn,
5069 * compute the final state we want first and check if we need to
5070 * make any changes at all.
5073 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5075 final |= DREF_NONSPREAD_CK505_ENABLE;
5077 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5079 final &= ~DREF_SSC_SOURCE_MASK;
5080 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5081 final &= ~DREF_SSC1_ENABLE;
5084 final |= DREF_SSC_SOURCE_ENABLE;
5086 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5087 final |= DREF_SSC1_ENABLE;
5090 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5091 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5093 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5095 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5097 final |= DREF_SSC_SOURCE_DISABLE;
5098 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104 /* Always enable nonspread source */
5105 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5108 val |= DREF_NONSPREAD_CK505_ENABLE;
5110 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5113 val &= ~DREF_SSC_SOURCE_MASK;
5114 val |= DREF_SSC_SOURCE_ENABLE;
5116 /* SSC must be turned on before enabling the CPU output */
5117 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5118 DRM_DEBUG_KMS("Using SSC on panel\n");
5119 val |= DREF_SSC1_ENABLE;
5121 val &= ~DREF_SSC1_ENABLE;
5123 /* Get SSC going before enabling the outputs */
5124 I915_WRITE(PCH_DREF_CONTROL, val);
5125 POSTING_READ(PCH_DREF_CONTROL);
5128 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5130 /* Enable CPU source on CPU attached eDP */
5132 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5133 DRM_DEBUG_KMS("Using SSC on eDP\n");
5134 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5137 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5139 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5141 I915_WRITE(PCH_DREF_CONTROL, val);
5142 POSTING_READ(PCH_DREF_CONTROL);
5145 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5147 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5149 /* Turn off CPU output */
5150 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5152 I915_WRITE(PCH_DREF_CONTROL, val);
5153 POSTING_READ(PCH_DREF_CONTROL);
5156 /* Turn off the SSC source */
5157 val &= ~DREF_SSC_SOURCE_MASK;
5158 val |= DREF_SSC_SOURCE_DISABLE;
5161 val &= ~DREF_SSC1_ENABLE;
5163 I915_WRITE(PCH_DREF_CONTROL, val);
5164 POSTING_READ(PCH_DREF_CONTROL);
5168 BUG_ON(val != final);
5171 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5175 tmp = I915_READ(SOUTH_CHICKEN2);
5176 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5177 I915_WRITE(SOUTH_CHICKEN2, tmp);
5179 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5181 DRM_ERROR("FDI mPHY reset assert timeout\n");
5183 tmp = I915_READ(SOUTH_CHICKEN2);
5184 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5185 I915_WRITE(SOUTH_CHICKEN2, tmp);
5187 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5189 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5192 /* WaMPhyProgramming:hsw */
5193 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5197 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5198 tmp &= ~(0xFF << 24);
5199 tmp |= (0x12 << 24);
5200 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5202 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5204 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5206 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5208 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5210 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5211 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5212 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5214 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5215 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5216 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5218 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5221 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5223 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5226 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5228 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5231 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5233 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5236 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5238 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5239 tmp &= ~(0xFF << 16);
5240 tmp |= (0x1C << 16);
5241 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5243 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5244 tmp &= ~(0xFF << 16);
5245 tmp |= (0x1C << 16);
5246 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5248 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5250 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5252 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5254 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5256 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5257 tmp &= ~(0xF << 28);
5259 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5261 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5262 tmp &= ~(0xF << 28);
5264 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5267 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5268 * Programming" based on the parameters passed:
5269 * - Sequence to enable CLKOUT_DP
5270 * - Sequence to enable CLKOUT_DP without spread
5271 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5273 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5279 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5281 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5282 with_fdi, "LP PCH doesn't have FDI\n"))
5285 mutex_lock(&dev_priv->dpio_lock);
5287 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5288 tmp &= ~SBI_SSCCTL_DISABLE;
5289 tmp |= SBI_SSCCTL_PATHALT;
5290 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5295 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5296 tmp &= ~SBI_SSCCTL_PATHALT;
5297 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5300 lpt_reset_fdi_mphy(dev_priv);
5301 lpt_program_fdi_mphy(dev_priv);
5305 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5306 SBI_GEN0 : SBI_DBUFF0;
5307 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5308 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5309 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5311 mutex_unlock(&dev_priv->dpio_lock);
5314 /* Sequence to disable CLKOUT_DP */
5315 static void lpt_disable_clkout_dp(struct drm_device *dev)
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5320 mutex_lock(&dev_priv->dpio_lock);
5322 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5323 SBI_GEN0 : SBI_DBUFF0;
5324 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5325 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5326 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5328 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5329 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5330 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5331 tmp |= SBI_SSCCTL_PATHALT;
5332 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5335 tmp |= SBI_SSCCTL_DISABLE;
5336 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5339 mutex_unlock(&dev_priv->dpio_lock);
5342 static void lpt_init_pch_refclk(struct drm_device *dev)
5344 struct drm_mode_config *mode_config = &dev->mode_config;
5345 struct intel_encoder *encoder;
5346 bool has_vga = false;
5348 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5349 switch (encoder->type) {
5350 case INTEL_OUTPUT_ANALOG:
5357 lpt_enable_clkout_dp(dev, true, true);
5359 lpt_disable_clkout_dp(dev);
5363 * Initialize reference clocks when the driver loads
5365 void intel_init_pch_refclk(struct drm_device *dev)
5367 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5368 ironlake_init_pch_refclk(dev);
5369 else if (HAS_PCH_LPT(dev))
5370 lpt_init_pch_refclk(dev);
5373 static int ironlake_get_refclk(struct drm_crtc *crtc)
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_encoder *encoder;
5378 int num_connectors = 0;
5379 bool is_lvds = false;
5381 for_each_encoder_on_crtc(dev, crtc, encoder) {
5382 switch (encoder->type) {
5383 case INTEL_OUTPUT_LVDS:
5390 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5391 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5392 dev_priv->vbt.lvds_ssc_freq);
5393 return dev_priv->vbt.lvds_ssc_freq * 1000;
5399 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5401 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403 int pipe = intel_crtc->pipe;
5408 switch (intel_crtc->config.pipe_bpp) {
5410 val |= PIPECONF_6BPC;
5413 val |= PIPECONF_8BPC;
5416 val |= PIPECONF_10BPC;
5419 val |= PIPECONF_12BPC;
5422 /* Case prevented by intel_choose_pipe_bpp_dither. */
5426 if (intel_crtc->config.dither)
5427 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5429 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5430 val |= PIPECONF_INTERLACED_ILK;
5432 val |= PIPECONF_PROGRESSIVE;
5434 if (intel_crtc->config.limited_color_range)
5435 val |= PIPECONF_COLOR_RANGE_SELECT;
5437 I915_WRITE(PIPECONF(pipe), val);
5438 POSTING_READ(PIPECONF(pipe));
5442 * Set up the pipe CSC unit.
5444 * Currently only full range RGB to limited range RGB conversion
5445 * is supported, but eventually this should handle various
5446 * RGB<->YCbCr scenarios as well.
5448 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453 int pipe = intel_crtc->pipe;
5454 uint16_t coeff = 0x7800; /* 1.0 */
5457 * TODO: Check what kind of values actually come out of the pipe
5458 * with these coeff/postoff values and adjust to get the best
5459 * accuracy. Perhaps we even need to take the bpc value into
5463 if (intel_crtc->config.limited_color_range)
5464 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5467 * GY/GU and RY/RU should be the other way around according
5468 * to BSpec, but reality doesn't agree. Just set them up in
5469 * a way that results in the correct picture.
5471 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5472 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5474 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5475 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5477 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5478 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5480 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5481 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5482 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5484 if (INTEL_INFO(dev)->gen > 6) {
5485 uint16_t postoff = 0;
5487 if (intel_crtc->config.limited_color_range)
5488 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5490 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5491 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5492 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5494 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5496 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5498 if (intel_crtc->config.limited_color_range)
5499 mode |= CSC_BLACK_SCREEN_OFFSET;
5501 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5505 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5507 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5514 if (intel_crtc->config.dither)
5515 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5517 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5518 val |= PIPECONF_INTERLACED_ILK;
5520 val |= PIPECONF_PROGRESSIVE;
5522 I915_WRITE(PIPECONF(cpu_transcoder), val);
5523 POSTING_READ(PIPECONF(cpu_transcoder));
5525 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5526 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5529 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5530 intel_clock_t *clock,
5531 bool *has_reduced_clock,
5532 intel_clock_t *reduced_clock)
5534 struct drm_device *dev = crtc->dev;
5535 struct drm_i915_private *dev_priv = dev->dev_private;
5536 struct intel_encoder *intel_encoder;
5538 const intel_limit_t *limit;
5539 bool ret, is_lvds = false;
5541 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5542 switch (intel_encoder->type) {
5543 case INTEL_OUTPUT_LVDS:
5549 refclk = ironlake_get_refclk(crtc);
5552 * Returns a set of divisors for the desired target clock with the given
5553 * refclk, or FALSE. The returned values represent the clock equation:
5554 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5556 limit = intel_limit(crtc, refclk);
5557 ret = dev_priv->display.find_dpll(limit, crtc,
5558 to_intel_crtc(crtc)->config.port_clock,
5559 refclk, NULL, clock);
5563 if (is_lvds && dev_priv->lvds_downclock_avail) {
5565 * Ensure we match the reduced clock's P to the target clock.
5566 * If the clocks don't match, we can't switch the display clock
5567 * by using the FP0/FP1. In such case we will disable the LVDS
5568 * downclock feature.
5570 *has_reduced_clock =
5571 dev_priv->display.find_dpll(limit, crtc,
5572 dev_priv->lvds_downclock,
5580 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5585 temp = I915_READ(SOUTH_CHICKEN1);
5586 if (temp & FDI_BC_BIFURCATION_SELECT)
5589 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5590 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5592 temp |= FDI_BC_BIFURCATION_SELECT;
5593 DRM_DEBUG_KMS("enabling fdi C rx\n");
5594 I915_WRITE(SOUTH_CHICKEN1, temp);
5595 POSTING_READ(SOUTH_CHICKEN1);
5598 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5600 struct drm_device *dev = intel_crtc->base.dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5603 switch (intel_crtc->pipe) {
5607 if (intel_crtc->config.fdi_lanes > 2)
5608 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5610 cpt_enable_fdi_bc_bifurcation(dev);
5614 cpt_enable_fdi_bc_bifurcation(dev);
5622 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5625 * Account for spread spectrum to avoid
5626 * oversubscribing the link. Max center spread
5627 * is 2.5%; use 5% for safety's sake.
5629 u32 bps = target_clock * bpp * 21 / 20;
5630 return bps / (link_bw * 8) + 1;
5633 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5635 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5638 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5640 intel_clock_t *reduced_clock, u32 *fp2)
5642 struct drm_crtc *crtc = &intel_crtc->base;
5643 struct drm_device *dev = crtc->dev;
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 struct intel_encoder *intel_encoder;
5647 int factor, num_connectors = 0;
5648 bool is_lvds = false, is_sdvo = false;
5650 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5651 switch (intel_encoder->type) {
5652 case INTEL_OUTPUT_LVDS:
5655 case INTEL_OUTPUT_SDVO:
5656 case INTEL_OUTPUT_HDMI:
5664 /* Enable autotuning of the PLL clock (if permissible) */
5667 if ((intel_panel_use_ssc(dev_priv) &&
5668 dev_priv->vbt.lvds_ssc_freq == 100) ||
5669 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5671 } else if (intel_crtc->config.sdvo_tv_clock)
5674 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5677 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5683 dpll |= DPLLB_MODE_LVDS;
5685 dpll |= DPLLB_MODE_DAC_SERIAL;
5687 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5688 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5691 dpll |= DPLL_SDVO_HIGH_SPEED;
5692 if (intel_crtc->config.has_dp_encoder)
5693 dpll |= DPLL_SDVO_HIGH_SPEED;
5695 /* compute bitmask from p1 value */
5696 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5698 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5700 switch (intel_crtc->config.dpll.p2) {
5702 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5705 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5708 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5711 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5715 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5716 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5718 dpll |= PLL_REF_INPUT_DREFCLK;
5720 return dpll | DPLL_VCO_ENABLE;
5723 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5725 struct drm_framebuffer *fb)
5727 struct drm_device *dev = crtc->dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5730 int pipe = intel_crtc->pipe;
5731 int plane = intel_crtc->plane;
5732 int num_connectors = 0;
5733 intel_clock_t clock, reduced_clock;
5734 u32 dpll = 0, fp = 0, fp2 = 0;
5735 bool ok, has_reduced_clock = false;
5736 bool is_lvds = false;
5737 struct intel_encoder *encoder;
5738 struct intel_shared_dpll *pll;
5741 for_each_encoder_on_crtc(dev, crtc, encoder) {
5742 switch (encoder->type) {
5743 case INTEL_OUTPUT_LVDS:
5751 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5752 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5754 ok = ironlake_compute_clocks(crtc, &clock,
5755 &has_reduced_clock, &reduced_clock);
5756 if (!ok && !intel_crtc->config.clock_set) {
5757 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5760 /* Compat-code for transition, will disappear. */
5761 if (!intel_crtc->config.clock_set) {
5762 intel_crtc->config.dpll.n = clock.n;
5763 intel_crtc->config.dpll.m1 = clock.m1;
5764 intel_crtc->config.dpll.m2 = clock.m2;
5765 intel_crtc->config.dpll.p1 = clock.p1;
5766 intel_crtc->config.dpll.p2 = clock.p2;
5769 /* Ensure that the cursor is valid for the new mode before changing... */
5770 intel_crtc_update_cursor(crtc, true);
5772 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5773 if (intel_crtc->config.has_pch_encoder) {
5774 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5775 if (has_reduced_clock)
5776 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5778 dpll = ironlake_compute_dpll(intel_crtc,
5779 &fp, &reduced_clock,
5780 has_reduced_clock ? &fp2 : NULL);
5782 intel_crtc->config.dpll_hw_state.dpll = dpll;
5783 intel_crtc->config.dpll_hw_state.fp0 = fp;
5784 if (has_reduced_clock)
5785 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5787 intel_crtc->config.dpll_hw_state.fp1 = fp;
5789 pll = intel_get_shared_dpll(intel_crtc);
5791 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5796 intel_put_shared_dpll(intel_crtc);
5798 if (intel_crtc->config.has_dp_encoder)
5799 intel_dp_set_m_n(intel_crtc);
5801 if (is_lvds && has_reduced_clock && i915_powersave)
5802 intel_crtc->lowfreq_avail = true;
5804 intel_crtc->lowfreq_avail = false;
5806 if (intel_crtc->config.has_pch_encoder) {
5807 pll = intel_crtc_to_shared_dpll(intel_crtc);
5811 intel_set_pipe_timings(intel_crtc);
5813 if (intel_crtc->config.has_pch_encoder) {
5814 intel_cpu_transcoder_set_m_n(intel_crtc,
5815 &intel_crtc->config.fdi_m_n);
5818 if (IS_IVYBRIDGE(dev))
5819 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5821 ironlake_set_pipeconf(crtc);
5823 /* Set up the display plane register */
5824 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5825 POSTING_READ(DSPCNTR(plane));
5827 ret = intel_pipe_set_base(crtc, x, y, fb);
5829 intel_update_watermarks(dev);
5834 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5835 struct intel_crtc_config *pipe_config)
5837 struct drm_device *dev = crtc->base.dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 enum transcoder transcoder = pipe_config->cpu_transcoder;
5841 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5842 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5843 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5845 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5846 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5847 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5850 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5851 struct intel_crtc_config *pipe_config)
5853 struct drm_device *dev = crtc->base.dev;
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5857 tmp = I915_READ(PF_CTL(crtc->pipe));
5859 if (tmp & PF_ENABLE) {
5860 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5861 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5863 /* We currently do not free assignements of panel fitters on
5864 * ivb/hsw (since we don't use the higher upscaling modes which
5865 * differentiates them) so just WARN about this case for now. */
5867 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5868 PF_PIPE_SEL_IVB(crtc->pipe));
5873 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5874 struct intel_crtc_config *pipe_config)
5876 struct drm_device *dev = crtc->base.dev;
5877 struct drm_i915_private *dev_priv = dev->dev_private;
5880 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5881 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5883 tmp = I915_READ(PIPECONF(crtc->pipe));
5884 if (!(tmp & PIPECONF_ENABLE))
5887 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5888 struct intel_shared_dpll *pll;
5890 pipe_config->has_pch_encoder = true;
5892 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5893 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5894 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5896 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5898 if (HAS_PCH_IBX(dev_priv->dev)) {
5899 pipe_config->shared_dpll =
5900 (enum intel_dpll_id) crtc->pipe;
5902 tmp = I915_READ(PCH_DPLL_SEL);
5903 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5906 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5909 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5911 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5912 &pipe_config->dpll_hw_state));
5914 tmp = pipe_config->dpll_hw_state.dpll;
5915 pipe_config->pixel_multiplier =
5916 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5917 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5919 pipe_config->pixel_multiplier = 1;
5922 intel_get_pipe_timings(crtc, pipe_config);
5924 ironlake_get_pfit_config(crtc, pipe_config);
5929 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5931 struct drm_device *dev = dev_priv->dev;
5932 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5933 struct intel_crtc *crtc;
5934 unsigned long irqflags;
5937 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5938 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5939 pipe_name(crtc->pipe));
5941 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5942 WARN(plls->spll_refcount, "SPLL enabled\n");
5943 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5944 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5945 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5946 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5947 "CPU PWM1 enabled\n");
5948 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5949 "CPU PWM2 enabled\n");
5950 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5951 "PCH PWM1 enabled\n");
5952 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5953 "Utility pin enabled\n");
5954 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5956 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5957 val = I915_READ(DEIMR);
5958 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5959 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5960 val = I915_READ(SDEIMR);
5961 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5962 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5963 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5967 * This function implements pieces of two sequences from BSpec:
5968 * - Sequence for display software to disable LCPLL
5969 * - Sequence for display software to allow package C8+
5970 * The steps implemented here are just the steps that actually touch the LCPLL
5971 * register. Callers should take care of disabling all the display engine
5972 * functions, doing the mode unset, fixing interrupts, etc.
5974 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5975 bool switch_to_fclk, bool allow_power_down)
5979 assert_can_disable_lcpll(dev_priv);
5981 val = I915_READ(LCPLL_CTL);
5983 if (switch_to_fclk) {
5984 val |= LCPLL_CD_SOURCE_FCLK;
5985 I915_WRITE(LCPLL_CTL, val);
5987 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5988 LCPLL_CD_SOURCE_FCLK_DONE, 1))
5989 DRM_ERROR("Switching to FCLK failed\n");
5991 val = I915_READ(LCPLL_CTL);
5994 val |= LCPLL_PLL_DISABLE;
5995 I915_WRITE(LCPLL_CTL, val);
5996 POSTING_READ(LCPLL_CTL);
5998 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
5999 DRM_ERROR("LCPLL still locked\n");
6001 val = I915_READ(D_COMP);
6002 val |= D_COMP_COMP_DISABLE;
6003 I915_WRITE(D_COMP, val);
6004 POSTING_READ(D_COMP);
6007 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6008 DRM_ERROR("D_COMP RCOMP still in progress\n");
6010 if (allow_power_down) {
6011 val = I915_READ(LCPLL_CTL);
6012 val |= LCPLL_POWER_DOWN_ALLOW;
6013 I915_WRITE(LCPLL_CTL, val);
6014 POSTING_READ(LCPLL_CTL);
6019 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6022 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6026 val = I915_READ(LCPLL_CTL);
6028 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6029 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6032 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6033 * we'll hang the machine! */
6034 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6036 if (val & LCPLL_POWER_DOWN_ALLOW) {
6037 val &= ~LCPLL_POWER_DOWN_ALLOW;
6038 I915_WRITE(LCPLL_CTL, val);
6039 POSTING_READ(LCPLL_CTL);
6042 val = I915_READ(D_COMP);
6043 val |= D_COMP_COMP_FORCE;
6044 val &= ~D_COMP_COMP_DISABLE;
6045 I915_WRITE(D_COMP, val);
6046 POSTING_READ(D_COMP);
6048 val = I915_READ(LCPLL_CTL);
6049 val &= ~LCPLL_PLL_DISABLE;
6050 I915_WRITE(LCPLL_CTL, val);
6052 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6053 DRM_ERROR("LCPLL not locked yet\n");
6055 if (val & LCPLL_CD_SOURCE_FCLK) {
6056 val = I915_READ(LCPLL_CTL);
6057 val &= ~LCPLL_CD_SOURCE_FCLK;
6058 I915_WRITE(LCPLL_CTL, val);
6060 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6061 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6062 DRM_ERROR("Switching back to LCPLL failed\n");
6065 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6068 void hsw_enable_pc8_work(struct work_struct *__work)
6070 struct drm_i915_private *dev_priv =
6071 container_of(to_delayed_work(__work), struct drm_i915_private,
6073 struct drm_device *dev = dev_priv->dev;
6076 if (dev_priv->pc8.enabled)
6079 DRM_DEBUG_KMS("Enabling package C8+\n");
6081 dev_priv->pc8.enabled = true;
6083 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6084 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6085 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6086 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6089 lpt_disable_clkout_dp(dev);
6090 hsw_pc8_disable_interrupts(dev);
6091 hsw_disable_lcpll(dev_priv, true, true);
6094 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6096 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6097 WARN(dev_priv->pc8.disable_count < 1,
6098 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6100 dev_priv->pc8.disable_count--;
6101 if (dev_priv->pc8.disable_count != 0)
6104 schedule_delayed_work(&dev_priv->pc8.enable_work,
6105 msecs_to_jiffies(i915_pc8_timeout));
6108 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6110 struct drm_device *dev = dev_priv->dev;
6113 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6114 WARN(dev_priv->pc8.disable_count < 0,
6115 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6117 dev_priv->pc8.disable_count++;
6118 if (dev_priv->pc8.disable_count != 1)
6121 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6122 if (!dev_priv->pc8.enabled)
6125 DRM_DEBUG_KMS("Disabling package C8+\n");
6127 hsw_restore_lcpll(dev_priv);
6128 hsw_pc8_restore_interrupts(dev);
6129 lpt_init_pch_refclk(dev);
6131 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6132 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6133 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6134 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6137 intel_prepare_ddi(dev);
6138 i915_gem_init_swizzling(dev);
6139 mutex_lock(&dev_priv->rps.hw_lock);
6140 gen6_update_ring_freq(dev);
6141 mutex_unlock(&dev_priv->rps.hw_lock);
6142 dev_priv->pc8.enabled = false;
6145 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6147 mutex_lock(&dev_priv->pc8.lock);
6148 __hsw_enable_package_c8(dev_priv);
6149 mutex_unlock(&dev_priv->pc8.lock);
6152 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6154 mutex_lock(&dev_priv->pc8.lock);
6155 __hsw_disable_package_c8(dev_priv);
6156 mutex_unlock(&dev_priv->pc8.lock);
6159 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6161 struct drm_device *dev = dev_priv->dev;
6162 struct intel_crtc *crtc;
6165 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6166 if (crtc->base.enabled)
6169 /* This case is still possible since we have the i915.disable_power_well
6170 * parameter and also the KVMr or something else might be requesting the
6172 val = I915_READ(HSW_PWR_WELL_DRIVER);
6174 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6181 /* Since we're called from modeset_global_resources there's no way to
6182 * symmetrically increase and decrease the refcount, so we use
6183 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6186 static void hsw_update_package_c8(struct drm_device *dev)
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6191 if (!i915_enable_pc8)
6194 mutex_lock(&dev_priv->pc8.lock);
6196 allow = hsw_can_enable_package_c8(dev_priv);
6198 if (allow == dev_priv->pc8.requirements_met)
6201 dev_priv->pc8.requirements_met = allow;
6204 __hsw_enable_package_c8(dev_priv);
6206 __hsw_disable_package_c8(dev_priv);
6209 mutex_unlock(&dev_priv->pc8.lock);
6212 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6214 if (!dev_priv->pc8.gpu_idle) {
6215 dev_priv->pc8.gpu_idle = true;
6216 hsw_enable_package_c8(dev_priv);
6220 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6222 if (dev_priv->pc8.gpu_idle) {
6223 dev_priv->pc8.gpu_idle = false;
6224 hsw_disable_package_c8(dev_priv);
6228 static void haswell_modeset_global_resources(struct drm_device *dev)
6230 bool enable = false;
6231 struct intel_crtc *crtc;
6233 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6234 if (!crtc->base.enabled)
6237 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6238 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6242 intel_set_power_well(dev, enable);
6244 hsw_update_package_c8(dev);
6247 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6249 struct drm_framebuffer *fb)
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254 int plane = intel_crtc->plane;
6257 if (!intel_ddi_pll_mode_set(crtc))
6260 /* Ensure that the cursor is valid for the new mode before changing... */
6261 intel_crtc_update_cursor(crtc, true);
6263 if (intel_crtc->config.has_dp_encoder)
6264 intel_dp_set_m_n(intel_crtc);
6266 intel_crtc->lowfreq_avail = false;
6268 intel_set_pipe_timings(intel_crtc);
6270 if (intel_crtc->config.has_pch_encoder) {
6271 intel_cpu_transcoder_set_m_n(intel_crtc,
6272 &intel_crtc->config.fdi_m_n);
6275 haswell_set_pipeconf(crtc);
6277 intel_set_pipe_csc(crtc);
6279 /* Set up the display plane register */
6280 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6281 POSTING_READ(DSPCNTR(plane));
6283 ret = intel_pipe_set_base(crtc, x, y, fb);
6285 intel_update_watermarks(dev);
6290 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6291 struct intel_crtc_config *pipe_config)
6293 struct drm_device *dev = crtc->base.dev;
6294 struct drm_i915_private *dev_priv = dev->dev_private;
6295 enum intel_display_power_domain pfit_domain;
6298 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6299 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6301 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6302 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6303 enum pipe trans_edp_pipe;
6304 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6306 WARN(1, "unknown pipe linked to edp transcoder\n");
6307 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6308 case TRANS_DDI_EDP_INPUT_A_ON:
6309 trans_edp_pipe = PIPE_A;
6311 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6312 trans_edp_pipe = PIPE_B;
6314 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6315 trans_edp_pipe = PIPE_C;
6319 if (trans_edp_pipe == crtc->pipe)
6320 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6323 if (!intel_display_power_enabled(dev,
6324 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6327 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6328 if (!(tmp & PIPECONF_ENABLE))
6332 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6333 * DDI E. So just check whether this pipe is wired to DDI E and whether
6334 * the PCH transcoder is on.
6336 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6337 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6338 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6339 pipe_config->has_pch_encoder = true;
6341 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6342 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6343 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6345 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6348 intel_get_pipe_timings(crtc, pipe_config);
6350 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6351 if (intel_display_power_enabled(dev, pfit_domain))
6352 ironlake_get_pfit_config(crtc, pipe_config);
6354 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6355 (I915_READ(IPS_CTL) & IPS_ENABLE);
6357 pipe_config->pixel_multiplier = 1;
6362 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6364 struct drm_framebuffer *fb)
6366 struct drm_device *dev = crtc->dev;
6367 struct drm_i915_private *dev_priv = dev->dev_private;
6368 struct intel_encoder *encoder;
6369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6370 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6371 int pipe = intel_crtc->pipe;
6374 drm_vblank_pre_modeset(dev, pipe);
6376 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6378 drm_vblank_post_modeset(dev, pipe);
6383 for_each_encoder_on_crtc(dev, crtc, encoder) {
6384 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6385 encoder->base.base.id,
6386 drm_get_encoder_name(&encoder->base),
6387 mode->base.id, mode->name);
6388 encoder->mode_set(encoder);
6394 static bool intel_eld_uptodate(struct drm_connector *connector,
6395 int reg_eldv, uint32_t bits_eldv,
6396 int reg_elda, uint32_t bits_elda,
6399 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6400 uint8_t *eld = connector->eld;
6403 i = I915_READ(reg_eldv);
6412 i = I915_READ(reg_elda);
6414 I915_WRITE(reg_elda, i);
6416 for (i = 0; i < eld[2]; i++)
6417 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6423 static void g4x_write_eld(struct drm_connector *connector,
6424 struct drm_crtc *crtc)
6426 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6427 uint8_t *eld = connector->eld;
6432 i = I915_READ(G4X_AUD_VID_DID);
6434 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6435 eldv = G4X_ELDV_DEVCL_DEVBLC;
6437 eldv = G4X_ELDV_DEVCTG;
6439 if (intel_eld_uptodate(connector,
6440 G4X_AUD_CNTL_ST, eldv,
6441 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6442 G4X_HDMIW_HDMIEDID))
6445 i = I915_READ(G4X_AUD_CNTL_ST);
6446 i &= ~(eldv | G4X_ELD_ADDR);
6447 len = (i >> 9) & 0x1f; /* ELD buffer size */
6448 I915_WRITE(G4X_AUD_CNTL_ST, i);
6453 len = min_t(uint8_t, eld[2], len);
6454 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6455 for (i = 0; i < len; i++)
6456 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6458 i = I915_READ(G4X_AUD_CNTL_ST);
6460 I915_WRITE(G4X_AUD_CNTL_ST, i);
6463 static void haswell_write_eld(struct drm_connector *connector,
6464 struct drm_crtc *crtc)
6466 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6467 uint8_t *eld = connector->eld;
6468 struct drm_device *dev = crtc->dev;
6469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473 int pipe = to_intel_crtc(crtc)->pipe;
6476 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6477 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6478 int aud_config = HSW_AUD_CFG(pipe);
6479 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6482 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6484 /* Audio output enable */
6485 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6486 tmp = I915_READ(aud_cntrl_st2);
6487 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6488 I915_WRITE(aud_cntrl_st2, tmp);
6490 /* Wait for 1 vertical blank */
6491 intel_wait_for_vblank(dev, pipe);
6493 /* Set ELD valid state */
6494 tmp = I915_READ(aud_cntrl_st2);
6495 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6496 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6497 I915_WRITE(aud_cntrl_st2, tmp);
6498 tmp = I915_READ(aud_cntrl_st2);
6499 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6501 /* Enable HDMI mode */
6502 tmp = I915_READ(aud_config);
6503 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6504 /* clear N_programing_enable and N_value_index */
6505 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6506 I915_WRITE(aud_config, tmp);
6508 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6510 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6511 intel_crtc->eld_vld = true;
6513 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6514 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6515 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6516 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6518 I915_WRITE(aud_config, 0);
6520 if (intel_eld_uptodate(connector,
6521 aud_cntrl_st2, eldv,
6522 aud_cntl_st, IBX_ELD_ADDRESS,
6526 i = I915_READ(aud_cntrl_st2);
6528 I915_WRITE(aud_cntrl_st2, i);
6533 i = I915_READ(aud_cntl_st);
6534 i &= ~IBX_ELD_ADDRESS;
6535 I915_WRITE(aud_cntl_st, i);
6536 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6537 DRM_DEBUG_DRIVER("port num:%d\n", i);
6539 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6540 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6541 for (i = 0; i < len; i++)
6542 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6544 i = I915_READ(aud_cntrl_st2);
6546 I915_WRITE(aud_cntrl_st2, i);
6550 static void ironlake_write_eld(struct drm_connector *connector,
6551 struct drm_crtc *crtc)
6553 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6554 uint8_t *eld = connector->eld;
6562 int pipe = to_intel_crtc(crtc)->pipe;
6564 if (HAS_PCH_IBX(connector->dev)) {
6565 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6566 aud_config = IBX_AUD_CFG(pipe);
6567 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6568 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6570 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6571 aud_config = CPT_AUD_CFG(pipe);
6572 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6573 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6576 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6578 i = I915_READ(aud_cntl_st);
6579 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6581 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6582 /* operate blindly on all ports */
6583 eldv = IBX_ELD_VALIDB;
6584 eldv |= IBX_ELD_VALIDB << 4;
6585 eldv |= IBX_ELD_VALIDB << 8;
6587 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6588 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6592 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6593 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6594 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6596 I915_WRITE(aud_config, 0);
6598 if (intel_eld_uptodate(connector,
6599 aud_cntrl_st2, eldv,
6600 aud_cntl_st, IBX_ELD_ADDRESS,
6604 i = I915_READ(aud_cntrl_st2);
6606 I915_WRITE(aud_cntrl_st2, i);
6611 i = I915_READ(aud_cntl_st);
6612 i &= ~IBX_ELD_ADDRESS;
6613 I915_WRITE(aud_cntl_st, i);
6615 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6616 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6617 for (i = 0; i < len; i++)
6618 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6620 i = I915_READ(aud_cntrl_st2);
6622 I915_WRITE(aud_cntrl_st2, i);
6625 void intel_write_eld(struct drm_encoder *encoder,
6626 struct drm_display_mode *mode)
6628 struct drm_crtc *crtc = encoder->crtc;
6629 struct drm_connector *connector;
6630 struct drm_device *dev = encoder->dev;
6631 struct drm_i915_private *dev_priv = dev->dev_private;
6633 connector = drm_select_eld(encoder, mode);
6637 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6639 drm_get_connector_name(connector),
6640 connector->encoder->base.id,
6641 drm_get_encoder_name(connector->encoder));
6643 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6645 if (dev_priv->display.write_eld)
6646 dev_priv->display.write_eld(connector, crtc);
6649 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6650 void intel_crtc_load_lut(struct drm_crtc *crtc)
6652 struct drm_device *dev = crtc->dev;
6653 struct drm_i915_private *dev_priv = dev->dev_private;
6654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655 enum pipe pipe = intel_crtc->pipe;
6656 int palreg = PALETTE(pipe);
6658 bool reenable_ips = false;
6660 /* The clocks have to be on to load the palette. */
6661 if (!crtc->enabled || !intel_crtc->active)
6664 if (!HAS_PCH_SPLIT(dev_priv->dev))
6665 assert_pll_enabled(dev_priv, pipe);
6667 /* use legacy palette for Ironlake */
6668 if (HAS_PCH_SPLIT(dev))
6669 palreg = LGC_PALETTE(pipe);
6671 /* Workaround : Do not read or write the pipe palette/gamma data while
6672 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6674 if (intel_crtc->config.ips_enabled &&
6675 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6676 GAMMA_MODE_MODE_SPLIT)) {
6677 hsw_disable_ips(intel_crtc);
6678 reenable_ips = true;
6681 for (i = 0; i < 256; i++) {
6682 I915_WRITE(palreg + 4 * i,
6683 (intel_crtc->lut_r[i] << 16) |
6684 (intel_crtc->lut_g[i] << 8) |
6685 intel_crtc->lut_b[i]);
6689 hsw_enable_ips(intel_crtc);
6692 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6694 struct drm_device *dev = crtc->dev;
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 bool visible = base != 0;
6700 if (intel_crtc->cursor_visible == visible)
6703 cntl = I915_READ(_CURACNTR);
6705 /* On these chipsets we can only modify the base whilst
6706 * the cursor is disabled.
6708 I915_WRITE(_CURABASE, base);
6710 cntl &= ~(CURSOR_FORMAT_MASK);
6711 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6712 cntl |= CURSOR_ENABLE |
6713 CURSOR_GAMMA_ENABLE |
6716 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6717 I915_WRITE(_CURACNTR, cntl);
6719 intel_crtc->cursor_visible = visible;
6722 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6724 struct drm_device *dev = crtc->dev;
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6727 int pipe = intel_crtc->pipe;
6728 bool visible = base != 0;
6730 if (intel_crtc->cursor_visible != visible) {
6731 uint32_t cntl = I915_READ(CURCNTR(pipe));
6733 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6734 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6735 cntl |= pipe << 28; /* Connect to correct pipe */
6737 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6738 cntl |= CURSOR_MODE_DISABLE;
6740 I915_WRITE(CURCNTR(pipe), cntl);
6742 intel_crtc->cursor_visible = visible;
6744 /* and commit changes on next vblank */
6745 I915_WRITE(CURBASE(pipe), base);
6748 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6750 struct drm_device *dev = crtc->dev;
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6753 int pipe = intel_crtc->pipe;
6754 bool visible = base != 0;
6756 if (intel_crtc->cursor_visible != visible) {
6757 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6759 cntl &= ~CURSOR_MODE;
6760 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6762 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6763 cntl |= CURSOR_MODE_DISABLE;
6765 if (IS_HASWELL(dev))
6766 cntl |= CURSOR_PIPE_CSC_ENABLE;
6767 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6769 intel_crtc->cursor_visible = visible;
6771 /* and commit changes on next vblank */
6772 I915_WRITE(CURBASE_IVB(pipe), base);
6775 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6776 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6779 struct drm_device *dev = crtc->dev;
6780 struct drm_i915_private *dev_priv = dev->dev_private;
6781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6782 int pipe = intel_crtc->pipe;
6783 int x = intel_crtc->cursor_x;
6784 int y = intel_crtc->cursor_y;
6790 if (on && crtc->enabled && crtc->fb) {
6791 base = intel_crtc->cursor_addr;
6792 if (x > (int) crtc->fb->width)
6795 if (y > (int) crtc->fb->height)
6801 if (x + intel_crtc->cursor_width < 0)
6804 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6807 pos |= x << CURSOR_X_SHIFT;
6810 if (y + intel_crtc->cursor_height < 0)
6813 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6816 pos |= y << CURSOR_Y_SHIFT;
6818 visible = base != 0;
6819 if (!visible && !intel_crtc->cursor_visible)
6822 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6823 I915_WRITE(CURPOS_IVB(pipe), pos);
6824 ivb_update_cursor(crtc, base);
6826 I915_WRITE(CURPOS(pipe), pos);
6827 if (IS_845G(dev) || IS_I865G(dev))
6828 i845_update_cursor(crtc, base);
6830 i9xx_update_cursor(crtc, base);
6834 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6835 struct drm_file *file,
6837 uint32_t width, uint32_t height)
6839 struct drm_device *dev = crtc->dev;
6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6842 struct drm_i915_gem_object *obj;
6846 /* if we want to turn off the cursor ignore width and height */
6848 DRM_DEBUG_KMS("cursor off\n");
6851 mutex_lock(&dev->struct_mutex);
6855 /* Currently we only support 64x64 cursors */
6856 if (width != 64 || height != 64) {
6857 DRM_ERROR("we currently only support 64x64 cursors\n");
6861 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6862 if (&obj->base == NULL)
6865 if (obj->base.size < width * height * 4) {
6866 DRM_ERROR("buffer is to small\n");
6871 /* we only need to pin inside GTT if cursor is non-phy */
6872 mutex_lock(&dev->struct_mutex);
6873 if (!dev_priv->info->cursor_needs_physical) {
6876 if (obj->tiling_mode) {
6877 DRM_ERROR("cursor cannot be tiled\n");
6882 /* Note that the w/a also requires 2 PTE of padding following
6883 * the bo. We currently fill all unused PTE with the shadow
6884 * page and so we should always have valid PTE following the
6885 * cursor preventing the VT-d warning.
6888 if (need_vtd_wa(dev))
6889 alignment = 64*1024;
6891 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6893 DRM_ERROR("failed to move cursor bo into the GTT\n");
6897 ret = i915_gem_object_put_fence(obj);
6899 DRM_ERROR("failed to release fence for cursor");
6903 addr = i915_gem_obj_ggtt_offset(obj);
6905 int align = IS_I830(dev) ? 16 * 1024 : 256;
6906 ret = i915_gem_attach_phys_object(dev, obj,
6907 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6910 DRM_ERROR("failed to attach phys object\n");
6913 addr = obj->phys_obj->handle->busaddr;
6917 I915_WRITE(CURSIZE, (height << 12) | width);
6920 if (intel_crtc->cursor_bo) {
6921 if (dev_priv->info->cursor_needs_physical) {
6922 if (intel_crtc->cursor_bo != obj)
6923 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6925 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6926 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6929 mutex_unlock(&dev->struct_mutex);
6931 intel_crtc->cursor_addr = addr;
6932 intel_crtc->cursor_bo = obj;
6933 intel_crtc->cursor_width = width;
6934 intel_crtc->cursor_height = height;
6936 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6940 i915_gem_object_unpin_from_display_plane(obj);
6942 mutex_unlock(&dev->struct_mutex);
6944 drm_gem_object_unreference_unlocked(&obj->base);
6948 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6952 intel_crtc->cursor_x = x;
6953 intel_crtc->cursor_y = y;
6955 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6960 /** Sets the color ramps on behalf of RandR */
6961 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6962 u16 blue, int regno)
6964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6966 intel_crtc->lut_r[regno] = red >> 8;
6967 intel_crtc->lut_g[regno] = green >> 8;
6968 intel_crtc->lut_b[regno] = blue >> 8;
6971 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6972 u16 *blue, int regno)
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976 *red = intel_crtc->lut_r[regno] << 8;
6977 *green = intel_crtc->lut_g[regno] << 8;
6978 *blue = intel_crtc->lut_b[regno] << 8;
6981 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6982 u16 *blue, uint32_t start, uint32_t size)
6984 int end = (start + size > 256) ? 256 : start + size, i;
6985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6987 for (i = start; i < end; i++) {
6988 intel_crtc->lut_r[i] = red[i] >> 8;
6989 intel_crtc->lut_g[i] = green[i] >> 8;
6990 intel_crtc->lut_b[i] = blue[i] >> 8;
6993 intel_crtc_load_lut(crtc);
6996 /* VESA 640x480x72Hz mode to set on the pipe */
6997 static struct drm_display_mode load_detect_mode = {
6998 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6999 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7002 static struct drm_framebuffer *
7003 intel_framebuffer_create(struct drm_device *dev,
7004 struct drm_mode_fb_cmd2 *mode_cmd,
7005 struct drm_i915_gem_object *obj)
7007 struct intel_framebuffer *intel_fb;
7010 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7012 drm_gem_object_unreference_unlocked(&obj->base);
7013 return ERR_PTR(-ENOMEM);
7016 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7018 drm_gem_object_unreference_unlocked(&obj->base);
7020 return ERR_PTR(ret);
7023 return &intel_fb->base;
7027 intel_framebuffer_pitch_for_width(int width, int bpp)
7029 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7030 return ALIGN(pitch, 64);
7034 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7036 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7037 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7040 static struct drm_framebuffer *
7041 intel_framebuffer_create_for_mode(struct drm_device *dev,
7042 struct drm_display_mode *mode,
7045 struct drm_i915_gem_object *obj;
7046 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7048 obj = i915_gem_alloc_object(dev,
7049 intel_framebuffer_size_for_mode(mode, bpp));
7051 return ERR_PTR(-ENOMEM);
7053 mode_cmd.width = mode->hdisplay;
7054 mode_cmd.height = mode->vdisplay;
7055 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7057 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7059 return intel_framebuffer_create(dev, &mode_cmd, obj);
7062 static struct drm_framebuffer *
7063 mode_fits_in_fbdev(struct drm_device *dev,
7064 struct drm_display_mode *mode)
7066 struct drm_i915_private *dev_priv = dev->dev_private;
7067 struct drm_i915_gem_object *obj;
7068 struct drm_framebuffer *fb;
7070 if (dev_priv->fbdev == NULL)
7073 obj = dev_priv->fbdev->ifb.obj;
7077 fb = &dev_priv->fbdev->ifb.base;
7078 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7079 fb->bits_per_pixel))
7082 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7088 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7089 struct drm_display_mode *mode,
7090 struct intel_load_detect_pipe *old)
7092 struct intel_crtc *intel_crtc;
7093 struct intel_encoder *intel_encoder =
7094 intel_attached_encoder(connector);
7095 struct drm_crtc *possible_crtc;
7096 struct drm_encoder *encoder = &intel_encoder->base;
7097 struct drm_crtc *crtc = NULL;
7098 struct drm_device *dev = encoder->dev;
7099 struct drm_framebuffer *fb;
7102 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7103 connector->base.id, drm_get_connector_name(connector),
7104 encoder->base.id, drm_get_encoder_name(encoder));
7107 * Algorithm gets a little messy:
7109 * - if the connector already has an assigned crtc, use it (but make
7110 * sure it's on first)
7112 * - try to find the first unused crtc that can drive this connector,
7113 * and use that if we find one
7116 /* See if we already have a CRTC for this connector */
7117 if (encoder->crtc) {
7118 crtc = encoder->crtc;
7120 mutex_lock(&crtc->mutex);
7122 old->dpms_mode = connector->dpms;
7123 old->load_detect_temp = false;
7125 /* Make sure the crtc and connector are running */
7126 if (connector->dpms != DRM_MODE_DPMS_ON)
7127 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7132 /* Find an unused one (if possible) */
7133 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7135 if (!(encoder->possible_crtcs & (1 << i)))
7137 if (!possible_crtc->enabled) {
7138 crtc = possible_crtc;
7144 * If we didn't find an unused CRTC, don't use any.
7147 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7151 mutex_lock(&crtc->mutex);
7152 intel_encoder->new_crtc = to_intel_crtc(crtc);
7153 to_intel_connector(connector)->new_encoder = intel_encoder;
7155 intel_crtc = to_intel_crtc(crtc);
7156 old->dpms_mode = connector->dpms;
7157 old->load_detect_temp = true;
7158 old->release_fb = NULL;
7161 mode = &load_detect_mode;
7163 /* We need a framebuffer large enough to accommodate all accesses
7164 * that the plane may generate whilst we perform load detection.
7165 * We can not rely on the fbcon either being present (we get called
7166 * during its initialisation to detect all boot displays, or it may
7167 * not even exist) or that it is large enough to satisfy the
7170 fb = mode_fits_in_fbdev(dev, mode);
7172 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7173 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7174 old->release_fb = fb;
7176 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7178 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7179 mutex_unlock(&crtc->mutex);
7183 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7184 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7185 if (old->release_fb)
7186 old->release_fb->funcs->destroy(old->release_fb);
7187 mutex_unlock(&crtc->mutex);
7191 /* let the connector get through one full cycle before testing */
7192 intel_wait_for_vblank(dev, intel_crtc->pipe);
7196 void intel_release_load_detect_pipe(struct drm_connector *connector,
7197 struct intel_load_detect_pipe *old)
7199 struct intel_encoder *intel_encoder =
7200 intel_attached_encoder(connector);
7201 struct drm_encoder *encoder = &intel_encoder->base;
7202 struct drm_crtc *crtc = encoder->crtc;
7204 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7205 connector->base.id, drm_get_connector_name(connector),
7206 encoder->base.id, drm_get_encoder_name(encoder));
7208 if (old->load_detect_temp) {
7209 to_intel_connector(connector)->new_encoder = NULL;
7210 intel_encoder->new_crtc = NULL;
7211 intel_set_mode(crtc, NULL, 0, 0, NULL);
7213 if (old->release_fb) {
7214 drm_framebuffer_unregister_private(old->release_fb);
7215 drm_framebuffer_unreference(old->release_fb);
7218 mutex_unlock(&crtc->mutex);
7222 /* Switch crtc and encoder back off if necessary */
7223 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7224 connector->funcs->dpms(connector, old->dpms_mode);
7226 mutex_unlock(&crtc->mutex);
7229 /* Returns the clock of the currently programmed mode of the given pipe. */
7230 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7231 struct intel_crtc_config *pipe_config)
7233 struct drm_device *dev = crtc->base.dev;
7234 struct drm_i915_private *dev_priv = dev->dev_private;
7235 int pipe = pipe_config->cpu_transcoder;
7236 u32 dpll = I915_READ(DPLL(pipe));
7238 intel_clock_t clock;
7240 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7241 fp = I915_READ(FP0(pipe));
7243 fp = I915_READ(FP1(pipe));
7245 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7246 if (IS_PINEVIEW(dev)) {
7247 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7248 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7250 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7251 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7254 if (!IS_GEN2(dev)) {
7255 if (IS_PINEVIEW(dev))
7256 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7257 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7259 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7260 DPLL_FPA01_P1_POST_DIV_SHIFT);
7262 switch (dpll & DPLL_MODE_MASK) {
7263 case DPLLB_MODE_DAC_SERIAL:
7264 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7267 case DPLLB_MODE_LVDS:
7268 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7272 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7273 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7274 pipe_config->adjusted_mode.clock = 0;
7278 if (IS_PINEVIEW(dev))
7279 pineview_clock(96000, &clock);
7281 i9xx_clock(96000, &clock);
7283 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7286 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7287 DPLL_FPA01_P1_POST_DIV_SHIFT);
7290 if ((dpll & PLL_REF_INPUT_MASK) ==
7291 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7292 /* XXX: might not be 66MHz */
7293 i9xx_clock(66000, &clock);
7295 i9xx_clock(48000, &clock);
7297 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7300 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7301 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7303 if (dpll & PLL_P2_DIVIDE_BY_4)
7308 i9xx_clock(48000, &clock);
7312 pipe_config->adjusted_mode.clock = clock.dot *
7313 pipe_config->pixel_multiplier;
7316 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7317 struct intel_crtc_config *pipe_config)
7319 struct drm_device *dev = crtc->base.dev;
7320 struct drm_i915_private *dev_priv = dev->dev_private;
7321 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7322 int link_freq, repeat;
7326 repeat = pipe_config->pixel_multiplier;
7329 * The calculation for the data clock is:
7330 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7331 * But we want to avoid losing precison if possible, so:
7332 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7334 * and the link clock is simpler:
7335 * link_clock = (m * link_clock * repeat) / n
7339 * We need to get the FDI or DP link clock here to derive
7342 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7343 * For DP, it's either 1.62GHz or 2.7GHz.
7344 * We do our calculations in 10*MHz since we don't need much precison.
7346 if (pipe_config->has_pch_encoder)
7347 link_freq = intel_fdi_link_freq(dev) * 10000;
7349 link_freq = pipe_config->port_clock;
7351 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7352 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7354 if (!link_m || !link_n)
7357 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7358 do_div(clock, link_n);
7360 pipe_config->adjusted_mode.clock = clock;
7363 /** Returns the currently programmed mode of the given pipe. */
7364 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7365 struct drm_crtc *crtc)
7367 struct drm_i915_private *dev_priv = dev->dev_private;
7368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7369 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7370 struct drm_display_mode *mode;
7371 struct intel_crtc_config pipe_config;
7372 int htot = I915_READ(HTOTAL(cpu_transcoder));
7373 int hsync = I915_READ(HSYNC(cpu_transcoder));
7374 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7375 int vsync = I915_READ(VSYNC(cpu_transcoder));
7377 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7382 * Construct a pipe_config sufficient for getting the clock info
7383 * back out of crtc_clock_get.
7385 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7386 * to use a real value here instead.
7388 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7389 pipe_config.pixel_multiplier = 1;
7390 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7392 mode->clock = pipe_config.adjusted_mode.clock;
7393 mode->hdisplay = (htot & 0xffff) + 1;
7394 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7395 mode->hsync_start = (hsync & 0xffff) + 1;
7396 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7397 mode->vdisplay = (vtot & 0xffff) + 1;
7398 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7399 mode->vsync_start = (vsync & 0xffff) + 1;
7400 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7402 drm_mode_set_name(mode);
7407 static void intel_increase_pllclock(struct drm_crtc *crtc)
7409 struct drm_device *dev = crtc->dev;
7410 drm_i915_private_t *dev_priv = dev->dev_private;
7411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7412 int pipe = intel_crtc->pipe;
7413 int dpll_reg = DPLL(pipe);
7416 if (HAS_PCH_SPLIT(dev))
7419 if (!dev_priv->lvds_downclock_avail)
7422 dpll = I915_READ(dpll_reg);
7423 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7424 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7426 assert_panel_unlocked(dev_priv, pipe);
7428 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7429 I915_WRITE(dpll_reg, dpll);
7430 intel_wait_for_vblank(dev, pipe);
7432 dpll = I915_READ(dpll_reg);
7433 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7434 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7438 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7440 struct drm_device *dev = crtc->dev;
7441 drm_i915_private_t *dev_priv = dev->dev_private;
7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7444 if (HAS_PCH_SPLIT(dev))
7447 if (!dev_priv->lvds_downclock_avail)
7451 * Since this is called by a timer, we should never get here in
7454 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7455 int pipe = intel_crtc->pipe;
7456 int dpll_reg = DPLL(pipe);
7459 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7461 assert_panel_unlocked(dev_priv, pipe);
7463 dpll = I915_READ(dpll_reg);
7464 dpll |= DISPLAY_RATE_SELECT_FPA1;
7465 I915_WRITE(dpll_reg, dpll);
7466 intel_wait_for_vblank(dev, pipe);
7467 dpll = I915_READ(dpll_reg);
7468 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7469 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7474 void intel_mark_busy(struct drm_device *dev)
7476 struct drm_i915_private *dev_priv = dev->dev_private;
7478 hsw_package_c8_gpu_busy(dev_priv);
7479 i915_update_gfx_val(dev_priv);
7482 void intel_mark_idle(struct drm_device *dev)
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 struct drm_crtc *crtc;
7487 hsw_package_c8_gpu_idle(dev_priv);
7489 if (!i915_powersave)
7492 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7496 intel_decrease_pllclock(crtc);
7500 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7501 struct intel_ring_buffer *ring)
7503 struct drm_device *dev = obj->base.dev;
7504 struct drm_crtc *crtc;
7506 if (!i915_powersave)
7509 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7513 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7516 intel_increase_pllclock(crtc);
7517 if (ring && intel_fbc_enabled(dev))
7518 ring->fbc_dirty = true;
7522 static void intel_crtc_destroy(struct drm_crtc *crtc)
7524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7525 struct drm_device *dev = crtc->dev;
7526 struct intel_unpin_work *work;
7527 unsigned long flags;
7529 spin_lock_irqsave(&dev->event_lock, flags);
7530 work = intel_crtc->unpin_work;
7531 intel_crtc->unpin_work = NULL;
7532 spin_unlock_irqrestore(&dev->event_lock, flags);
7535 cancel_work_sync(&work->work);
7539 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7541 drm_crtc_cleanup(crtc);
7546 static void intel_unpin_work_fn(struct work_struct *__work)
7548 struct intel_unpin_work *work =
7549 container_of(__work, struct intel_unpin_work, work);
7550 struct drm_device *dev = work->crtc->dev;
7552 mutex_lock(&dev->struct_mutex);
7553 intel_unpin_fb_obj(work->old_fb_obj);
7554 drm_gem_object_unreference(&work->pending_flip_obj->base);
7555 drm_gem_object_unreference(&work->old_fb_obj->base);
7557 intel_update_fbc(dev);
7558 mutex_unlock(&dev->struct_mutex);
7560 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7561 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7566 static void do_intel_finish_page_flip(struct drm_device *dev,
7567 struct drm_crtc *crtc)
7569 drm_i915_private_t *dev_priv = dev->dev_private;
7570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7571 struct intel_unpin_work *work;
7572 unsigned long flags;
7574 /* Ignore early vblank irqs */
7575 if (intel_crtc == NULL)
7578 spin_lock_irqsave(&dev->event_lock, flags);
7579 work = intel_crtc->unpin_work;
7581 /* Ensure we don't miss a work->pending update ... */
7584 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7585 spin_unlock_irqrestore(&dev->event_lock, flags);
7589 /* and that the unpin work is consistent wrt ->pending. */
7592 intel_crtc->unpin_work = NULL;
7595 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7597 drm_vblank_put(dev, intel_crtc->pipe);
7599 spin_unlock_irqrestore(&dev->event_lock, flags);
7601 wake_up_all(&dev_priv->pending_flip_queue);
7603 queue_work(dev_priv->wq, &work->work);
7605 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7608 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7610 drm_i915_private_t *dev_priv = dev->dev_private;
7611 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7613 do_intel_finish_page_flip(dev, crtc);
7616 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7618 drm_i915_private_t *dev_priv = dev->dev_private;
7619 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7621 do_intel_finish_page_flip(dev, crtc);
7624 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7626 drm_i915_private_t *dev_priv = dev->dev_private;
7627 struct intel_crtc *intel_crtc =
7628 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7629 unsigned long flags;
7631 /* NB: An MMIO update of the plane base pointer will also
7632 * generate a page-flip completion irq, i.e. every modeset
7633 * is also accompanied by a spurious intel_prepare_page_flip().
7635 spin_lock_irqsave(&dev->event_lock, flags);
7636 if (intel_crtc->unpin_work)
7637 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7638 spin_unlock_irqrestore(&dev->event_lock, flags);
7641 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7643 /* Ensure that the work item is consistent when activating it ... */
7645 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7646 /* and that it is marked active as soon as the irq could fire. */
7650 static int intel_gen2_queue_flip(struct drm_device *dev,
7651 struct drm_crtc *crtc,
7652 struct drm_framebuffer *fb,
7653 struct drm_i915_gem_object *obj,
7656 struct drm_i915_private *dev_priv = dev->dev_private;
7657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7659 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7662 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7666 ret = intel_ring_begin(ring, 6);
7670 /* Can't queue multiple flips, so wait for the previous
7671 * one to finish before executing the next.
7673 if (intel_crtc->plane)
7674 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7676 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7677 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7678 intel_ring_emit(ring, MI_NOOP);
7679 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7680 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7681 intel_ring_emit(ring, fb->pitches[0]);
7682 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7683 intel_ring_emit(ring, 0); /* aux display base address, unused */
7685 intel_mark_page_flip_active(intel_crtc);
7686 intel_ring_advance(ring);
7690 intel_unpin_fb_obj(obj);
7695 static int intel_gen3_queue_flip(struct drm_device *dev,
7696 struct drm_crtc *crtc,
7697 struct drm_framebuffer *fb,
7698 struct drm_i915_gem_object *obj,
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7704 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7707 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7711 ret = intel_ring_begin(ring, 6);
7715 if (intel_crtc->plane)
7716 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7718 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7719 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7720 intel_ring_emit(ring, MI_NOOP);
7721 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7722 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7723 intel_ring_emit(ring, fb->pitches[0]);
7724 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7725 intel_ring_emit(ring, MI_NOOP);
7727 intel_mark_page_flip_active(intel_crtc);
7728 intel_ring_advance(ring);
7732 intel_unpin_fb_obj(obj);
7737 static int intel_gen4_queue_flip(struct drm_device *dev,
7738 struct drm_crtc *crtc,
7739 struct drm_framebuffer *fb,
7740 struct drm_i915_gem_object *obj,
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7745 uint32_t pf, pipesrc;
7746 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7749 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7753 ret = intel_ring_begin(ring, 4);
7757 /* i965+ uses the linear or tiled offsets from the
7758 * Display Registers (which do not change across a page-flip)
7759 * so we need only reprogram the base address.
7761 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7762 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7763 intel_ring_emit(ring, fb->pitches[0]);
7764 intel_ring_emit(ring,
7765 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7768 /* XXX Enabling the panel-fitter across page-flip is so far
7769 * untested on non-native modes, so ignore it for now.
7770 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7773 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7774 intel_ring_emit(ring, pf | pipesrc);
7776 intel_mark_page_flip_active(intel_crtc);
7777 intel_ring_advance(ring);
7781 intel_unpin_fb_obj(obj);
7786 static int intel_gen6_queue_flip(struct drm_device *dev,
7787 struct drm_crtc *crtc,
7788 struct drm_framebuffer *fb,
7789 struct drm_i915_gem_object *obj,
7792 struct drm_i915_private *dev_priv = dev->dev_private;
7793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7794 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7795 uint32_t pf, pipesrc;
7798 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7802 ret = intel_ring_begin(ring, 4);
7806 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7807 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7808 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7809 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7811 /* Contrary to the suggestions in the documentation,
7812 * "Enable Panel Fitter" does not seem to be required when page
7813 * flipping with a non-native mode, and worse causes a normal
7815 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7818 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7819 intel_ring_emit(ring, pf | pipesrc);
7821 intel_mark_page_flip_active(intel_crtc);
7822 intel_ring_advance(ring);
7826 intel_unpin_fb_obj(obj);
7832 * On gen7 we currently use the blit ring because (in early silicon at least)
7833 * the render ring doesn't give us interrpts for page flip completion, which
7834 * means clients will hang after the first flip is queued. Fortunately the
7835 * blit ring generates interrupts properly, so use it instead.
7837 static int intel_gen7_queue_flip(struct drm_device *dev,
7838 struct drm_crtc *crtc,
7839 struct drm_framebuffer *fb,
7840 struct drm_i915_gem_object *obj,
7843 struct drm_i915_private *dev_priv = dev->dev_private;
7844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7845 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7846 uint32_t plane_bit = 0;
7849 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7853 switch(intel_crtc->plane) {
7855 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7858 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7861 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7864 WARN_ONCE(1, "unknown plane in flip command\n");
7869 ret = intel_ring_begin(ring, 4);
7873 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7874 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7875 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7876 intel_ring_emit(ring, (MI_NOOP));
7878 intel_mark_page_flip_active(intel_crtc);
7879 intel_ring_advance(ring);
7883 intel_unpin_fb_obj(obj);
7888 static int intel_default_queue_flip(struct drm_device *dev,
7889 struct drm_crtc *crtc,
7890 struct drm_framebuffer *fb,
7891 struct drm_i915_gem_object *obj,
7897 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7898 struct drm_framebuffer *fb,
7899 struct drm_pending_vblank_event *event,
7900 uint32_t page_flip_flags)
7902 struct drm_device *dev = crtc->dev;
7903 struct drm_i915_private *dev_priv = dev->dev_private;
7904 struct drm_framebuffer *old_fb = crtc->fb;
7905 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7907 struct intel_unpin_work *work;
7908 unsigned long flags;
7911 /* Can't change pixel format via MI display flips. */
7912 if (fb->pixel_format != crtc->fb->pixel_format)
7916 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7917 * Note that pitch changes could also affect these register.
7919 if (INTEL_INFO(dev)->gen > 3 &&
7920 (fb->offsets[0] != crtc->fb->offsets[0] ||
7921 fb->pitches[0] != crtc->fb->pitches[0]))
7924 work = kzalloc(sizeof *work, GFP_KERNEL);
7928 work->event = event;
7930 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7931 INIT_WORK(&work->work, intel_unpin_work_fn);
7933 ret = drm_vblank_get(dev, intel_crtc->pipe);
7937 /* We borrow the event spin lock for protecting unpin_work */
7938 spin_lock_irqsave(&dev->event_lock, flags);
7939 if (intel_crtc->unpin_work) {
7940 spin_unlock_irqrestore(&dev->event_lock, flags);
7942 drm_vblank_put(dev, intel_crtc->pipe);
7944 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7947 intel_crtc->unpin_work = work;
7948 spin_unlock_irqrestore(&dev->event_lock, flags);
7950 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7951 flush_workqueue(dev_priv->wq);
7953 ret = i915_mutex_lock_interruptible(dev);
7957 /* Reference the objects for the scheduled work. */
7958 drm_gem_object_reference(&work->old_fb_obj->base);
7959 drm_gem_object_reference(&obj->base);
7963 work->pending_flip_obj = obj;
7965 work->enable_stall_check = true;
7967 atomic_inc(&intel_crtc->unpin_work_count);
7968 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7970 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
7972 goto cleanup_pending;
7974 intel_disable_fbc(dev);
7975 intel_mark_fb_busy(obj, NULL);
7976 mutex_unlock(&dev->struct_mutex);
7978 trace_i915_flip_request(intel_crtc->plane, obj);
7983 atomic_dec(&intel_crtc->unpin_work_count);
7985 drm_gem_object_unreference(&work->old_fb_obj->base);
7986 drm_gem_object_unreference(&obj->base);
7987 mutex_unlock(&dev->struct_mutex);
7990 spin_lock_irqsave(&dev->event_lock, flags);
7991 intel_crtc->unpin_work = NULL;
7992 spin_unlock_irqrestore(&dev->event_lock, flags);
7994 drm_vblank_put(dev, intel_crtc->pipe);
8001 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8002 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8003 .load_lut = intel_crtc_load_lut,
8006 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8007 struct drm_crtc *crtc)
8009 struct drm_device *dev;
8010 struct drm_crtc *tmp;
8013 WARN(!crtc, "checking null crtc?\n");
8017 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8023 if (encoder->possible_crtcs & crtc_mask)
8029 * intel_modeset_update_staged_output_state
8031 * Updates the staged output configuration state, e.g. after we've read out the
8034 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8036 struct intel_encoder *encoder;
8037 struct intel_connector *connector;
8039 list_for_each_entry(connector, &dev->mode_config.connector_list,
8041 connector->new_encoder =
8042 to_intel_encoder(connector->base.encoder);
8045 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8048 to_intel_crtc(encoder->base.crtc);
8053 * intel_modeset_commit_output_state
8055 * This function copies the stage display pipe configuration to the real one.
8057 static void intel_modeset_commit_output_state(struct drm_device *dev)
8059 struct intel_encoder *encoder;
8060 struct intel_connector *connector;
8062 list_for_each_entry(connector, &dev->mode_config.connector_list,
8064 connector->base.encoder = &connector->new_encoder->base;
8067 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8069 encoder->base.crtc = &encoder->new_crtc->base;
8074 connected_sink_compute_bpp(struct intel_connector * connector,
8075 struct intel_crtc_config *pipe_config)
8077 int bpp = pipe_config->pipe_bpp;
8079 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8080 connector->base.base.id,
8081 drm_get_connector_name(&connector->base));
8083 /* Don't use an invalid EDID bpc value */
8084 if (connector->base.display_info.bpc &&
8085 connector->base.display_info.bpc * 3 < bpp) {
8086 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8087 bpp, connector->base.display_info.bpc*3);
8088 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8091 /* Clamp bpp to 8 on screens without EDID 1.4 */
8092 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8093 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8095 pipe_config->pipe_bpp = 24;
8100 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8101 struct drm_framebuffer *fb,
8102 struct intel_crtc_config *pipe_config)
8104 struct drm_device *dev = crtc->base.dev;
8105 struct intel_connector *connector;
8108 switch (fb->pixel_format) {
8110 bpp = 8*3; /* since we go through a colormap */
8112 case DRM_FORMAT_XRGB1555:
8113 case DRM_FORMAT_ARGB1555:
8114 /* checked in intel_framebuffer_init already */
8115 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8117 case DRM_FORMAT_RGB565:
8118 bpp = 6*3; /* min is 18bpp */
8120 case DRM_FORMAT_XBGR8888:
8121 case DRM_FORMAT_ABGR8888:
8122 /* checked in intel_framebuffer_init already */
8123 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8125 case DRM_FORMAT_XRGB8888:
8126 case DRM_FORMAT_ARGB8888:
8129 case DRM_FORMAT_XRGB2101010:
8130 case DRM_FORMAT_ARGB2101010:
8131 case DRM_FORMAT_XBGR2101010:
8132 case DRM_FORMAT_ABGR2101010:
8133 /* checked in intel_framebuffer_init already */
8134 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8138 /* TODO: gen4+ supports 16 bpc floating point, too. */
8140 DRM_DEBUG_KMS("unsupported depth\n");
8144 pipe_config->pipe_bpp = bpp;
8146 /* Clamp display bpp to EDID value */
8147 list_for_each_entry(connector, &dev->mode_config.connector_list,
8149 if (!connector->new_encoder ||
8150 connector->new_encoder->new_crtc != crtc)
8153 connected_sink_compute_bpp(connector, pipe_config);
8159 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8160 struct intel_crtc_config *pipe_config,
8161 const char *context)
8163 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8164 context, pipe_name(crtc->pipe));
8166 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8167 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8168 pipe_config->pipe_bpp, pipe_config->dither);
8169 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8170 pipe_config->has_pch_encoder,
8171 pipe_config->fdi_lanes,
8172 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8173 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8174 pipe_config->fdi_m_n.tu);
8175 DRM_DEBUG_KMS("requested mode:\n");
8176 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8177 DRM_DEBUG_KMS("adjusted mode:\n");
8178 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8179 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8180 pipe_config->gmch_pfit.control,
8181 pipe_config->gmch_pfit.pgm_ratios,
8182 pipe_config->gmch_pfit.lvds_border_bits);
8183 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8184 pipe_config->pch_pfit.pos,
8185 pipe_config->pch_pfit.size);
8186 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8189 static bool check_encoder_cloning(struct drm_crtc *crtc)
8191 int num_encoders = 0;
8192 bool uncloneable_encoders = false;
8193 struct intel_encoder *encoder;
8195 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8197 if (&encoder->new_crtc->base != crtc)
8201 if (!encoder->cloneable)
8202 uncloneable_encoders = true;
8205 return !(num_encoders > 1 && uncloneable_encoders);
8208 static struct intel_crtc_config *
8209 intel_modeset_pipe_config(struct drm_crtc *crtc,
8210 struct drm_framebuffer *fb,
8211 struct drm_display_mode *mode)
8213 struct drm_device *dev = crtc->dev;
8214 struct intel_encoder *encoder;
8215 struct intel_crtc_config *pipe_config;
8216 int plane_bpp, ret = -EINVAL;
8219 if (!check_encoder_cloning(crtc)) {
8220 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8221 return ERR_PTR(-EINVAL);
8224 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8226 return ERR_PTR(-ENOMEM);
8228 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8229 drm_mode_copy(&pipe_config->requested_mode, mode);
8230 pipe_config->cpu_transcoder =
8231 (enum transcoder) to_intel_crtc(crtc)->pipe;
8232 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8235 * Sanitize sync polarity flags based on requested ones. If neither
8236 * positive or negative polarity is requested, treat this as meaning
8237 * negative polarity.
8239 if (!(pipe_config->adjusted_mode.flags &
8240 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8241 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8243 if (!(pipe_config->adjusted_mode.flags &
8244 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8245 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8247 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8248 * plane pixel format and any sink constraints into account. Returns the
8249 * source plane bpp so that dithering can be selected on mismatches
8250 * after encoders and crtc also have had their say. */
8251 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8257 /* Ensure the port clock defaults are reset when retrying. */
8258 pipe_config->port_clock = 0;
8259 pipe_config->pixel_multiplier = 1;
8261 /* Fill in default crtc timings, allow encoders to overwrite them. */
8262 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8264 /* Pass our mode to the connectors and the CRTC to give them a chance to
8265 * adjust it according to limitations or connector properties, and also
8266 * a chance to reject the mode entirely.
8268 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8271 if (&encoder->new_crtc->base != crtc)
8274 if (!(encoder->compute_config(encoder, pipe_config))) {
8275 DRM_DEBUG_KMS("Encoder config failure\n");
8280 /* Set default port clock if not overwritten by the encoder. Needs to be
8281 * done afterwards in case the encoder adjusts the mode. */
8282 if (!pipe_config->port_clock)
8283 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8285 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8287 DRM_DEBUG_KMS("CRTC fixup failed\n");
8292 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8297 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8302 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8303 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8304 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8309 return ERR_PTR(ret);
8312 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8313 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8315 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8316 unsigned *prepare_pipes, unsigned *disable_pipes)
8318 struct intel_crtc *intel_crtc;
8319 struct drm_device *dev = crtc->dev;
8320 struct intel_encoder *encoder;
8321 struct intel_connector *connector;
8322 struct drm_crtc *tmp_crtc;
8324 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8326 /* Check which crtcs have changed outputs connected to them, these need
8327 * to be part of the prepare_pipes mask. We don't (yet) support global
8328 * modeset across multiple crtcs, so modeset_pipes will only have one
8329 * bit set at most. */
8330 list_for_each_entry(connector, &dev->mode_config.connector_list,
8332 if (connector->base.encoder == &connector->new_encoder->base)
8335 if (connector->base.encoder) {
8336 tmp_crtc = connector->base.encoder->crtc;
8338 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8341 if (connector->new_encoder)
8343 1 << connector->new_encoder->new_crtc->pipe;
8346 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8348 if (encoder->base.crtc == &encoder->new_crtc->base)
8351 if (encoder->base.crtc) {
8352 tmp_crtc = encoder->base.crtc;
8354 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8357 if (encoder->new_crtc)
8358 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8361 /* Check for any pipes that will be fully disabled ... */
8362 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8366 /* Don't try to disable disabled crtcs. */
8367 if (!intel_crtc->base.enabled)
8370 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8372 if (encoder->new_crtc == intel_crtc)
8377 *disable_pipes |= 1 << intel_crtc->pipe;
8381 /* set_mode is also used to update properties on life display pipes. */
8382 intel_crtc = to_intel_crtc(crtc);
8384 *prepare_pipes |= 1 << intel_crtc->pipe;
8387 * For simplicity do a full modeset on any pipe where the output routing
8388 * changed. We could be more clever, but that would require us to be
8389 * more careful with calling the relevant encoder->mode_set functions.
8392 *modeset_pipes = *prepare_pipes;
8394 /* ... and mask these out. */
8395 *modeset_pipes &= ~(*disable_pipes);
8396 *prepare_pipes &= ~(*disable_pipes);
8399 * HACK: We don't (yet) fully support global modesets. intel_set_config
8400 * obies this rule, but the modeset restore mode of
8401 * intel_modeset_setup_hw_state does not.
8403 *modeset_pipes &= 1 << intel_crtc->pipe;
8404 *prepare_pipes &= 1 << intel_crtc->pipe;
8406 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8407 *modeset_pipes, *prepare_pipes, *disable_pipes);
8410 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8412 struct drm_encoder *encoder;
8413 struct drm_device *dev = crtc->dev;
8415 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8416 if (encoder->crtc == crtc)
8423 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8425 struct intel_encoder *intel_encoder;
8426 struct intel_crtc *intel_crtc;
8427 struct drm_connector *connector;
8429 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8431 if (!intel_encoder->base.crtc)
8434 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8436 if (prepare_pipes & (1 << intel_crtc->pipe))
8437 intel_encoder->connectors_active = false;
8440 intel_modeset_commit_output_state(dev);
8442 /* Update computed state. */
8443 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8445 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8448 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8449 if (!connector->encoder || !connector->encoder->crtc)
8452 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8454 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8455 struct drm_property *dpms_property =
8456 dev->mode_config.dpms_property;
8458 connector->dpms = DRM_MODE_DPMS_ON;
8459 drm_object_property_set_value(&connector->base,
8463 intel_encoder = to_intel_encoder(connector->encoder);
8464 intel_encoder->connectors_active = true;
8470 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8471 struct intel_crtc_config *new)
8473 int clock1, clock2, diff;
8475 clock1 = cur->adjusted_mode.clock;
8476 clock2 = new->adjusted_mode.clock;
8478 if (clock1 == clock2)
8481 if (!clock1 || !clock2)
8484 diff = abs(clock1 - clock2);
8486 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8492 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8493 list_for_each_entry((intel_crtc), \
8494 &(dev)->mode_config.crtc_list, \
8496 if (mask & (1 <<(intel_crtc)->pipe))
8499 intel_pipe_config_compare(struct drm_device *dev,
8500 struct intel_crtc_config *current_config,
8501 struct intel_crtc_config *pipe_config)
8503 #define PIPE_CONF_CHECK_X(name) \
8504 if (current_config->name != pipe_config->name) { \
8505 DRM_ERROR("mismatch in " #name " " \
8506 "(expected 0x%08x, found 0x%08x)\n", \
8507 current_config->name, \
8508 pipe_config->name); \
8512 #define PIPE_CONF_CHECK_I(name) \
8513 if (current_config->name != pipe_config->name) { \
8514 DRM_ERROR("mismatch in " #name " " \
8515 "(expected %i, found %i)\n", \
8516 current_config->name, \
8517 pipe_config->name); \
8521 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8522 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8523 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8524 "(expected %i, found %i)\n", \
8525 current_config->name & (mask), \
8526 pipe_config->name & (mask)); \
8530 #define PIPE_CONF_QUIRK(quirk) \
8531 ((current_config->quirks | pipe_config->quirks) & (quirk))
8533 PIPE_CONF_CHECK_I(cpu_transcoder);
8535 PIPE_CONF_CHECK_I(has_pch_encoder);
8536 PIPE_CONF_CHECK_I(fdi_lanes);
8537 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8538 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8539 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8540 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8541 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8543 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8544 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8545 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8546 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8547 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8548 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8550 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8551 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8552 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8553 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8554 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8555 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8557 PIPE_CONF_CHECK_I(pixel_multiplier);
8559 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8560 DRM_MODE_FLAG_INTERLACE);
8562 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8563 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8564 DRM_MODE_FLAG_PHSYNC);
8565 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8566 DRM_MODE_FLAG_NHSYNC);
8567 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8568 DRM_MODE_FLAG_PVSYNC);
8569 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8570 DRM_MODE_FLAG_NVSYNC);
8573 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8574 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8576 PIPE_CONF_CHECK_I(gmch_pfit.control);
8577 /* pfit ratios are autocomputed by the hw on gen4+ */
8578 if (INTEL_INFO(dev)->gen < 4)
8579 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8580 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8581 PIPE_CONF_CHECK_I(pch_pfit.pos);
8582 PIPE_CONF_CHECK_I(pch_pfit.size);
8584 PIPE_CONF_CHECK_I(ips_enabled);
8586 PIPE_CONF_CHECK_I(shared_dpll);
8587 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8588 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8589 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8590 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8592 #undef PIPE_CONF_CHECK_X
8593 #undef PIPE_CONF_CHECK_I
8594 #undef PIPE_CONF_CHECK_FLAGS
8595 #undef PIPE_CONF_QUIRK
8597 if (!IS_HASWELL(dev)) {
8598 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8599 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8600 current_config->adjusted_mode.clock,
8601 pipe_config->adjusted_mode.clock);
8610 check_connector_state(struct drm_device *dev)
8612 struct intel_connector *connector;
8614 list_for_each_entry(connector, &dev->mode_config.connector_list,
8616 /* This also checks the encoder/connector hw state with the
8617 * ->get_hw_state callbacks. */
8618 intel_connector_check_state(connector);
8620 WARN(&connector->new_encoder->base != connector->base.encoder,
8621 "connector's staged encoder doesn't match current encoder\n");
8626 check_encoder_state(struct drm_device *dev)
8628 struct intel_encoder *encoder;
8629 struct intel_connector *connector;
8631 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8633 bool enabled = false;
8634 bool active = false;
8635 enum pipe pipe, tracked_pipe;
8637 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8638 encoder->base.base.id,
8639 drm_get_encoder_name(&encoder->base));
8641 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8642 "encoder's stage crtc doesn't match current crtc\n");
8643 WARN(encoder->connectors_active && !encoder->base.crtc,
8644 "encoder's active_connectors set, but no crtc\n");
8646 list_for_each_entry(connector, &dev->mode_config.connector_list,
8648 if (connector->base.encoder != &encoder->base)
8651 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8654 WARN(!!encoder->base.crtc != enabled,
8655 "encoder's enabled state mismatch "
8656 "(expected %i, found %i)\n",
8657 !!encoder->base.crtc, enabled);
8658 WARN(active && !encoder->base.crtc,
8659 "active encoder with no crtc\n");
8661 WARN(encoder->connectors_active != active,
8662 "encoder's computed active state doesn't match tracked active state "
8663 "(expected %i, found %i)\n", active, encoder->connectors_active);
8665 active = encoder->get_hw_state(encoder, &pipe);
8666 WARN(active != encoder->connectors_active,
8667 "encoder's hw state doesn't match sw tracking "
8668 "(expected %i, found %i)\n",
8669 encoder->connectors_active, active);
8671 if (!encoder->base.crtc)
8674 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8675 WARN(active && pipe != tracked_pipe,
8676 "active encoder's pipe doesn't match"
8677 "(expected %i, found %i)\n",
8678 tracked_pipe, pipe);
8684 check_crtc_state(struct drm_device *dev)
8686 drm_i915_private_t *dev_priv = dev->dev_private;
8687 struct intel_crtc *crtc;
8688 struct intel_encoder *encoder;
8689 struct intel_crtc_config pipe_config;
8691 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8693 bool enabled = false;
8694 bool active = false;
8696 memset(&pipe_config, 0, sizeof(pipe_config));
8698 DRM_DEBUG_KMS("[CRTC:%d]\n",
8699 crtc->base.base.id);
8701 WARN(crtc->active && !crtc->base.enabled,
8702 "active crtc, but not enabled in sw tracking\n");
8704 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8706 if (encoder->base.crtc != &crtc->base)
8709 if (encoder->connectors_active)
8713 WARN(active != crtc->active,
8714 "crtc's computed active state doesn't match tracked active state "
8715 "(expected %i, found %i)\n", active, crtc->active);
8716 WARN(enabled != crtc->base.enabled,
8717 "crtc's computed enabled state doesn't match tracked enabled state "
8718 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8720 active = dev_priv->display.get_pipe_config(crtc,
8723 /* hw state is inconsistent with the pipe A quirk */
8724 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8725 active = crtc->active;
8727 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8730 if (encoder->base.crtc != &crtc->base)
8732 if (encoder->get_config &&
8733 encoder->get_hw_state(encoder, &pipe))
8734 encoder->get_config(encoder, &pipe_config);
8737 if (dev_priv->display.get_clock)
8738 dev_priv->display.get_clock(crtc, &pipe_config);
8740 WARN(crtc->active != active,
8741 "crtc active state doesn't match with hw state "
8742 "(expected %i, found %i)\n", crtc->active, active);
8745 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8746 WARN(1, "pipe state doesn't match!\n");
8747 intel_dump_pipe_config(crtc, &pipe_config,
8749 intel_dump_pipe_config(crtc, &crtc->config,
8756 check_shared_dpll_state(struct drm_device *dev)
8758 drm_i915_private_t *dev_priv = dev->dev_private;
8759 struct intel_crtc *crtc;
8760 struct intel_dpll_hw_state dpll_hw_state;
8763 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8764 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8765 int enabled_crtcs = 0, active_crtcs = 0;
8768 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8770 DRM_DEBUG_KMS("%s\n", pll->name);
8772 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8774 WARN(pll->active > pll->refcount,
8775 "more active pll users than references: %i vs %i\n",
8776 pll->active, pll->refcount);
8777 WARN(pll->active && !pll->on,
8778 "pll in active use but not on in sw tracking\n");
8779 WARN(pll->on && !pll->active,
8780 "pll in on but not on in use in sw tracking\n");
8781 WARN(pll->on != active,
8782 "pll on state mismatch (expected %i, found %i)\n",
8785 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8787 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8789 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8792 WARN(pll->active != active_crtcs,
8793 "pll active crtcs mismatch (expected %i, found %i)\n",
8794 pll->active, active_crtcs);
8795 WARN(pll->refcount != enabled_crtcs,
8796 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8797 pll->refcount, enabled_crtcs);
8799 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8800 sizeof(dpll_hw_state)),
8801 "pll hw state mismatch\n");
8806 intel_modeset_check_state(struct drm_device *dev)
8808 check_connector_state(dev);
8809 check_encoder_state(dev);
8810 check_crtc_state(dev);
8811 check_shared_dpll_state(dev);
8814 static int __intel_set_mode(struct drm_crtc *crtc,
8815 struct drm_display_mode *mode,
8816 int x, int y, struct drm_framebuffer *fb)
8818 struct drm_device *dev = crtc->dev;
8819 drm_i915_private_t *dev_priv = dev->dev_private;
8820 struct drm_display_mode *saved_mode, *saved_hwmode;
8821 struct intel_crtc_config *pipe_config = NULL;
8822 struct intel_crtc *intel_crtc;
8823 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8826 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8829 saved_hwmode = saved_mode + 1;
8831 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8832 &prepare_pipes, &disable_pipes);
8834 *saved_hwmode = crtc->hwmode;
8835 *saved_mode = crtc->mode;
8837 /* Hack: Because we don't (yet) support global modeset on multiple
8838 * crtcs, we don't keep track of the new mode for more than one crtc.
8839 * Hence simply check whether any bit is set in modeset_pipes in all the
8840 * pieces of code that are not yet converted to deal with mutliple crtcs
8841 * changing their mode at the same time. */
8842 if (modeset_pipes) {
8843 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8844 if (IS_ERR(pipe_config)) {
8845 ret = PTR_ERR(pipe_config);
8850 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8854 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8855 intel_crtc_disable(&intel_crtc->base);
8857 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8858 if (intel_crtc->base.enabled)
8859 dev_priv->display.crtc_disable(&intel_crtc->base);
8862 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8863 * to set it here already despite that we pass it down the callchain.
8865 if (modeset_pipes) {
8867 /* mode_set/enable/disable functions rely on a correct pipe
8869 to_intel_crtc(crtc)->config = *pipe_config;
8872 /* Only after disabling all output pipelines that will be changed can we
8873 * update the the output configuration. */
8874 intel_modeset_update_state(dev, prepare_pipes);
8876 if (dev_priv->display.modeset_global_resources)
8877 dev_priv->display.modeset_global_resources(dev);
8879 /* Set up the DPLL and any encoders state that needs to adjust or depend
8882 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8883 ret = intel_crtc_mode_set(&intel_crtc->base,
8889 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8890 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8891 dev_priv->display.crtc_enable(&intel_crtc->base);
8893 if (modeset_pipes) {
8894 /* Store real post-adjustment hardware mode. */
8895 crtc->hwmode = pipe_config->adjusted_mode;
8897 /* Calculate and store various constants which
8898 * are later needed by vblank and swap-completion
8899 * timestamping. They are derived from true hwmode.
8901 drm_calc_timestamping_constants(crtc);
8904 /* FIXME: add subpixel order */
8906 if (ret && crtc->enabled) {
8907 crtc->hwmode = *saved_hwmode;
8908 crtc->mode = *saved_mode;
8917 static int intel_set_mode(struct drm_crtc *crtc,
8918 struct drm_display_mode *mode,
8919 int x, int y, struct drm_framebuffer *fb)
8923 ret = __intel_set_mode(crtc, mode, x, y, fb);
8926 intel_modeset_check_state(crtc->dev);
8931 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8933 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8936 #undef for_each_intel_crtc_masked
8938 static void intel_set_config_free(struct intel_set_config *config)
8943 kfree(config->save_connector_encoders);
8944 kfree(config->save_encoder_crtcs);
8948 static int intel_set_config_save_state(struct drm_device *dev,
8949 struct intel_set_config *config)
8951 struct drm_encoder *encoder;
8952 struct drm_connector *connector;
8955 config->save_encoder_crtcs =
8956 kcalloc(dev->mode_config.num_encoder,
8957 sizeof(struct drm_crtc *), GFP_KERNEL);
8958 if (!config->save_encoder_crtcs)
8961 config->save_connector_encoders =
8962 kcalloc(dev->mode_config.num_connector,
8963 sizeof(struct drm_encoder *), GFP_KERNEL);
8964 if (!config->save_connector_encoders)
8967 /* Copy data. Note that driver private data is not affected.
8968 * Should anything bad happen only the expected state is
8969 * restored, not the drivers personal bookkeeping.
8972 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8973 config->save_encoder_crtcs[count++] = encoder->crtc;
8977 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8978 config->save_connector_encoders[count++] = connector->encoder;
8984 static void intel_set_config_restore_state(struct drm_device *dev,
8985 struct intel_set_config *config)
8987 struct intel_encoder *encoder;
8988 struct intel_connector *connector;
8992 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8994 to_intel_crtc(config->save_encoder_crtcs[count++]);
8998 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8999 connector->new_encoder =
9000 to_intel_encoder(config->save_connector_encoders[count++]);
9005 is_crtc_connector_off(struct drm_mode_set *set)
9009 if (set->num_connectors == 0)
9012 if (WARN_ON(set->connectors == NULL))
9015 for (i = 0; i < set->num_connectors; i++)
9016 if (set->connectors[i]->encoder &&
9017 set->connectors[i]->encoder->crtc == set->crtc &&
9018 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9025 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9026 struct intel_set_config *config)
9029 /* We should be able to check here if the fb has the same properties
9030 * and then just flip_or_move it */
9031 if (is_crtc_connector_off(set)) {
9032 config->mode_changed = true;
9033 } else if (set->crtc->fb != set->fb) {
9034 /* If we have no fb then treat it as a full mode set */
9035 if (set->crtc->fb == NULL) {
9036 struct intel_crtc *intel_crtc =
9037 to_intel_crtc(set->crtc);
9039 if (intel_crtc->active && i915_fastboot) {
9040 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9041 config->fb_changed = true;
9043 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9044 config->mode_changed = true;
9046 } else if (set->fb == NULL) {
9047 config->mode_changed = true;
9048 } else if (set->fb->pixel_format !=
9049 set->crtc->fb->pixel_format) {
9050 config->mode_changed = true;
9052 config->fb_changed = true;
9056 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9057 config->fb_changed = true;
9059 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9060 DRM_DEBUG_KMS("modes are different, full mode set\n");
9061 drm_mode_debug_printmodeline(&set->crtc->mode);
9062 drm_mode_debug_printmodeline(set->mode);
9063 config->mode_changed = true;
9066 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9067 set->crtc->base.id, config->mode_changed, config->fb_changed);
9071 intel_modeset_stage_output_state(struct drm_device *dev,
9072 struct drm_mode_set *set,
9073 struct intel_set_config *config)
9075 struct drm_crtc *new_crtc;
9076 struct intel_connector *connector;
9077 struct intel_encoder *encoder;
9080 /* The upper layers ensure that we either disable a crtc or have a list
9081 * of connectors. For paranoia, double-check this. */
9082 WARN_ON(!set->fb && (set->num_connectors != 0));
9083 WARN_ON(set->fb && (set->num_connectors == 0));
9085 list_for_each_entry(connector, &dev->mode_config.connector_list,
9087 /* Otherwise traverse passed in connector list and get encoders
9089 for (ro = 0; ro < set->num_connectors; ro++) {
9090 if (set->connectors[ro] == &connector->base) {
9091 connector->new_encoder = connector->encoder;
9096 /* If we disable the crtc, disable all its connectors. Also, if
9097 * the connector is on the changing crtc but not on the new
9098 * connector list, disable it. */
9099 if ((!set->fb || ro == set->num_connectors) &&
9100 connector->base.encoder &&
9101 connector->base.encoder->crtc == set->crtc) {
9102 connector->new_encoder = NULL;
9104 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9105 connector->base.base.id,
9106 drm_get_connector_name(&connector->base));
9110 if (&connector->new_encoder->base != connector->base.encoder) {
9111 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9112 config->mode_changed = true;
9115 /* connector->new_encoder is now updated for all connectors. */
9117 /* Update crtc of enabled connectors. */
9118 list_for_each_entry(connector, &dev->mode_config.connector_list,
9120 if (!connector->new_encoder)
9123 new_crtc = connector->new_encoder->base.crtc;
9125 for (ro = 0; ro < set->num_connectors; ro++) {
9126 if (set->connectors[ro] == &connector->base)
9127 new_crtc = set->crtc;
9130 /* Make sure the new CRTC will work with the encoder */
9131 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9135 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9138 connector->base.base.id,
9139 drm_get_connector_name(&connector->base),
9143 /* Check for any encoders that needs to be disabled. */
9144 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9146 list_for_each_entry(connector,
9147 &dev->mode_config.connector_list,
9149 if (connector->new_encoder == encoder) {
9150 WARN_ON(!connector->new_encoder->new_crtc);
9155 encoder->new_crtc = NULL;
9157 /* Only now check for crtc changes so we don't miss encoders
9158 * that will be disabled. */
9159 if (&encoder->new_crtc->base != encoder->base.crtc) {
9160 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9161 config->mode_changed = true;
9164 /* Now we've also updated encoder->new_crtc for all encoders. */
9169 static int intel_crtc_set_config(struct drm_mode_set *set)
9171 struct drm_device *dev;
9172 struct drm_mode_set save_set;
9173 struct intel_set_config *config;
9178 BUG_ON(!set->crtc->helper_private);
9180 /* Enforce sane interface api - has been abused by the fb helper. */
9181 BUG_ON(!set->mode && set->fb);
9182 BUG_ON(set->fb && set->num_connectors == 0);
9185 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9186 set->crtc->base.id, set->fb->base.id,
9187 (int)set->num_connectors, set->x, set->y);
9189 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9192 dev = set->crtc->dev;
9195 config = kzalloc(sizeof(*config), GFP_KERNEL);
9199 ret = intel_set_config_save_state(dev, config);
9203 save_set.crtc = set->crtc;
9204 save_set.mode = &set->crtc->mode;
9205 save_set.x = set->crtc->x;
9206 save_set.y = set->crtc->y;
9207 save_set.fb = set->crtc->fb;
9209 /* Compute whether we need a full modeset, only an fb base update or no
9210 * change at all. In the future we might also check whether only the
9211 * mode changed, e.g. for LVDS where we only change the panel fitter in
9213 intel_set_config_compute_mode_changes(set, config);
9215 ret = intel_modeset_stage_output_state(dev, set, config);
9219 if (config->mode_changed) {
9220 ret = intel_set_mode(set->crtc, set->mode,
9221 set->x, set->y, set->fb);
9222 } else if (config->fb_changed) {
9223 intel_crtc_wait_for_pending_flips(set->crtc);
9225 ret = intel_pipe_set_base(set->crtc,
9226 set->x, set->y, set->fb);
9230 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9231 set->crtc->base.id, ret);
9233 intel_set_config_restore_state(dev, config);
9235 /* Try to restore the config */
9236 if (config->mode_changed &&
9237 intel_set_mode(save_set.crtc, save_set.mode,
9238 save_set.x, save_set.y, save_set.fb))
9239 DRM_ERROR("failed to restore config after modeset failure\n");
9243 intel_set_config_free(config);
9247 static const struct drm_crtc_funcs intel_crtc_funcs = {
9248 .cursor_set = intel_crtc_cursor_set,
9249 .cursor_move = intel_crtc_cursor_move,
9250 .gamma_set = intel_crtc_gamma_set,
9251 .set_config = intel_crtc_set_config,
9252 .destroy = intel_crtc_destroy,
9253 .page_flip = intel_crtc_page_flip,
9256 static void intel_cpu_pll_init(struct drm_device *dev)
9259 intel_ddi_pll_init(dev);
9262 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9263 struct intel_shared_dpll *pll,
9264 struct intel_dpll_hw_state *hw_state)
9268 val = I915_READ(PCH_DPLL(pll->id));
9269 hw_state->dpll = val;
9270 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9271 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9273 return val & DPLL_VCO_ENABLE;
9276 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9277 struct intel_shared_dpll *pll)
9279 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9280 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9283 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9284 struct intel_shared_dpll *pll)
9286 /* PCH refclock must be enabled first */
9287 assert_pch_refclk_enabled(dev_priv);
9289 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9291 /* Wait for the clocks to stabilize. */
9292 POSTING_READ(PCH_DPLL(pll->id));
9295 /* The pixel multiplier can only be updated once the
9296 * DPLL is enabled and the clocks are stable.
9298 * So write it again.
9300 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9301 POSTING_READ(PCH_DPLL(pll->id));
9305 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9306 struct intel_shared_dpll *pll)
9308 struct drm_device *dev = dev_priv->dev;
9309 struct intel_crtc *crtc;
9311 /* Make sure no transcoder isn't still depending on us. */
9312 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9313 if (intel_crtc_to_shared_dpll(crtc) == pll)
9314 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9317 I915_WRITE(PCH_DPLL(pll->id), 0);
9318 POSTING_READ(PCH_DPLL(pll->id));
9322 static char *ibx_pch_dpll_names[] = {
9327 static void ibx_pch_dpll_init(struct drm_device *dev)
9329 struct drm_i915_private *dev_priv = dev->dev_private;
9332 dev_priv->num_shared_dpll = 2;
9334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9335 dev_priv->shared_dplls[i].id = i;
9336 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9337 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9338 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9339 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9340 dev_priv->shared_dplls[i].get_hw_state =
9341 ibx_pch_dpll_get_hw_state;
9345 static void intel_shared_dpll_init(struct drm_device *dev)
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9349 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9350 ibx_pch_dpll_init(dev);
9352 dev_priv->num_shared_dpll = 0;
9354 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9355 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9356 dev_priv->num_shared_dpll);
9359 static void intel_crtc_init(struct drm_device *dev, int pipe)
9361 drm_i915_private_t *dev_priv = dev->dev_private;
9362 struct intel_crtc *intel_crtc;
9365 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9366 if (intel_crtc == NULL)
9369 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9371 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9372 for (i = 0; i < 256; i++) {
9373 intel_crtc->lut_r[i] = i;
9374 intel_crtc->lut_g[i] = i;
9375 intel_crtc->lut_b[i] = i;
9378 /* Swap pipes & planes for FBC on pre-965 */
9379 intel_crtc->pipe = pipe;
9380 intel_crtc->plane = pipe;
9381 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9382 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9383 intel_crtc->plane = !pipe;
9386 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9387 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9388 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9389 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9391 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9394 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9395 struct drm_file *file)
9397 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9398 struct drm_mode_object *drmmode_obj;
9399 struct intel_crtc *crtc;
9401 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9404 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9405 DRM_MODE_OBJECT_CRTC);
9408 DRM_ERROR("no such CRTC id\n");
9412 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9413 pipe_from_crtc_id->pipe = crtc->pipe;
9418 static int intel_encoder_clones(struct intel_encoder *encoder)
9420 struct drm_device *dev = encoder->base.dev;
9421 struct intel_encoder *source_encoder;
9425 list_for_each_entry(source_encoder,
9426 &dev->mode_config.encoder_list, base.head) {
9428 if (encoder == source_encoder)
9429 index_mask |= (1 << entry);
9431 /* Intel hw has only one MUX where enocoders could be cloned. */
9432 if (encoder->cloneable && source_encoder->cloneable)
9433 index_mask |= (1 << entry);
9441 static bool has_edp_a(struct drm_device *dev)
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9445 if (!IS_MOBILE(dev))
9448 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9452 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9458 static void intel_setup_outputs(struct drm_device *dev)
9460 struct drm_i915_private *dev_priv = dev->dev_private;
9461 struct intel_encoder *encoder;
9462 bool dpd_is_edp = false;
9464 intel_lvds_init(dev);
9467 intel_crt_init(dev);
9472 /* Haswell uses DDI functions to detect digital outputs */
9473 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9474 /* DDI A only supports eDP */
9476 intel_ddi_init(dev, PORT_A);
9478 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9480 found = I915_READ(SFUSE_STRAP);
9482 if (found & SFUSE_STRAP_DDIB_DETECTED)
9483 intel_ddi_init(dev, PORT_B);
9484 if (found & SFUSE_STRAP_DDIC_DETECTED)
9485 intel_ddi_init(dev, PORT_C);
9486 if (found & SFUSE_STRAP_DDID_DETECTED)
9487 intel_ddi_init(dev, PORT_D);
9488 } else if (HAS_PCH_SPLIT(dev)) {
9490 dpd_is_edp = intel_dpd_is_edp(dev);
9493 intel_dp_init(dev, DP_A, PORT_A);
9495 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9496 /* PCH SDVOB multiplex with HDMIB */
9497 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9499 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9500 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9501 intel_dp_init(dev, PCH_DP_B, PORT_B);
9504 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9505 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9507 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9508 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9510 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9511 intel_dp_init(dev, PCH_DP_C, PORT_C);
9513 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9514 intel_dp_init(dev, PCH_DP_D, PORT_D);
9515 } else if (IS_VALLEYVIEW(dev)) {
9516 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9517 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9518 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9520 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9521 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9525 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9526 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9528 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9529 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9531 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9534 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9535 DRM_DEBUG_KMS("probing SDVOB\n");
9536 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9537 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9538 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9539 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9542 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9543 intel_dp_init(dev, DP_B, PORT_B);
9546 /* Before G4X SDVOC doesn't have its own detect register */
9548 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9549 DRM_DEBUG_KMS("probing SDVOC\n");
9550 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9553 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9555 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9556 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9557 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9559 if (SUPPORTS_INTEGRATED_DP(dev))
9560 intel_dp_init(dev, DP_C, PORT_C);
9563 if (SUPPORTS_INTEGRATED_DP(dev) &&
9564 (I915_READ(DP_D) & DP_DETECTED))
9565 intel_dp_init(dev, DP_D, PORT_D);
9566 } else if (IS_GEN2(dev))
9567 intel_dvo_init(dev);
9569 if (SUPPORTS_TV(dev))
9572 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9573 encoder->base.possible_crtcs = encoder->crtc_mask;
9574 encoder->base.possible_clones =
9575 intel_encoder_clones(encoder);
9578 intel_init_pch_refclk(dev);
9580 drm_helper_move_panel_connectors_to_head(dev);
9583 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9585 drm_framebuffer_cleanup(&fb->base);
9586 drm_gem_object_unreference_unlocked(&fb->obj->base);
9589 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9591 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9593 intel_framebuffer_fini(intel_fb);
9597 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9598 struct drm_file *file,
9599 unsigned int *handle)
9601 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9602 struct drm_i915_gem_object *obj = intel_fb->obj;
9604 return drm_gem_handle_create(file, &obj->base, handle);
9607 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9608 .destroy = intel_user_framebuffer_destroy,
9609 .create_handle = intel_user_framebuffer_create_handle,
9612 int intel_framebuffer_init(struct drm_device *dev,
9613 struct intel_framebuffer *intel_fb,
9614 struct drm_mode_fb_cmd2 *mode_cmd,
9615 struct drm_i915_gem_object *obj)
9620 if (obj->tiling_mode == I915_TILING_Y) {
9621 DRM_DEBUG("hardware does not support tiling Y\n");
9625 if (mode_cmd->pitches[0] & 63) {
9626 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9627 mode_cmd->pitches[0]);
9631 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9632 pitch_limit = 32*1024;
9633 } else if (INTEL_INFO(dev)->gen >= 4) {
9634 if (obj->tiling_mode)
9635 pitch_limit = 16*1024;
9637 pitch_limit = 32*1024;
9638 } else if (INTEL_INFO(dev)->gen >= 3) {
9639 if (obj->tiling_mode)
9640 pitch_limit = 8*1024;
9642 pitch_limit = 16*1024;
9644 /* XXX DSPC is limited to 4k tiled */
9645 pitch_limit = 8*1024;
9647 if (mode_cmd->pitches[0] > pitch_limit) {
9648 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9649 obj->tiling_mode ? "tiled" : "linear",
9650 mode_cmd->pitches[0], pitch_limit);
9654 if (obj->tiling_mode != I915_TILING_NONE &&
9655 mode_cmd->pitches[0] != obj->stride) {
9656 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9657 mode_cmd->pitches[0], obj->stride);
9661 /* Reject formats not supported by any plane early. */
9662 switch (mode_cmd->pixel_format) {
9664 case DRM_FORMAT_RGB565:
9665 case DRM_FORMAT_XRGB8888:
9666 case DRM_FORMAT_ARGB8888:
9668 case DRM_FORMAT_XRGB1555:
9669 case DRM_FORMAT_ARGB1555:
9670 if (INTEL_INFO(dev)->gen > 3) {
9671 DRM_DEBUG("unsupported pixel format: %s\n",
9672 drm_get_format_name(mode_cmd->pixel_format));
9676 case DRM_FORMAT_XBGR8888:
9677 case DRM_FORMAT_ABGR8888:
9678 case DRM_FORMAT_XRGB2101010:
9679 case DRM_FORMAT_ARGB2101010:
9680 case DRM_FORMAT_XBGR2101010:
9681 case DRM_FORMAT_ABGR2101010:
9682 if (INTEL_INFO(dev)->gen < 4) {
9683 DRM_DEBUG("unsupported pixel format: %s\n",
9684 drm_get_format_name(mode_cmd->pixel_format));
9688 case DRM_FORMAT_YUYV:
9689 case DRM_FORMAT_UYVY:
9690 case DRM_FORMAT_YVYU:
9691 case DRM_FORMAT_VYUY:
9692 if (INTEL_INFO(dev)->gen < 5) {
9693 DRM_DEBUG("unsupported pixel format: %s\n",
9694 drm_get_format_name(mode_cmd->pixel_format));
9699 DRM_DEBUG("unsupported pixel format: %s\n",
9700 drm_get_format_name(mode_cmd->pixel_format));
9704 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9705 if (mode_cmd->offsets[0] != 0)
9708 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9709 intel_fb->obj = obj;
9711 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9713 DRM_ERROR("framebuffer init failed %d\n", ret);
9720 static struct drm_framebuffer *
9721 intel_user_framebuffer_create(struct drm_device *dev,
9722 struct drm_file *filp,
9723 struct drm_mode_fb_cmd2 *mode_cmd)
9725 struct drm_i915_gem_object *obj;
9727 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9728 mode_cmd->handles[0]));
9729 if (&obj->base == NULL)
9730 return ERR_PTR(-ENOENT);
9732 return intel_framebuffer_create(dev, mode_cmd, obj);
9735 static const struct drm_mode_config_funcs intel_mode_funcs = {
9736 .fb_create = intel_user_framebuffer_create,
9737 .output_poll_changed = intel_fb_output_poll_changed,
9740 /* Set up chip specific display functions */
9741 static void intel_init_display(struct drm_device *dev)
9743 struct drm_i915_private *dev_priv = dev->dev_private;
9745 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9746 dev_priv->display.find_dpll = g4x_find_best_dpll;
9747 else if (IS_VALLEYVIEW(dev))
9748 dev_priv->display.find_dpll = vlv_find_best_dpll;
9749 else if (IS_PINEVIEW(dev))
9750 dev_priv->display.find_dpll = pnv_find_best_dpll;
9752 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9755 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9756 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9757 dev_priv->display.crtc_enable = haswell_crtc_enable;
9758 dev_priv->display.crtc_disable = haswell_crtc_disable;
9759 dev_priv->display.off = haswell_crtc_off;
9760 dev_priv->display.update_plane = ironlake_update_plane;
9761 } else if (HAS_PCH_SPLIT(dev)) {
9762 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9763 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9764 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9765 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9766 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9767 dev_priv->display.off = ironlake_crtc_off;
9768 dev_priv->display.update_plane = ironlake_update_plane;
9769 } else if (IS_VALLEYVIEW(dev)) {
9770 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9771 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9772 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9773 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9774 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9775 dev_priv->display.off = i9xx_crtc_off;
9776 dev_priv->display.update_plane = i9xx_update_plane;
9778 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9779 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9780 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9781 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9782 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9783 dev_priv->display.off = i9xx_crtc_off;
9784 dev_priv->display.update_plane = i9xx_update_plane;
9787 /* Returns the core display clock speed */
9788 if (IS_VALLEYVIEW(dev))
9789 dev_priv->display.get_display_clock_speed =
9790 valleyview_get_display_clock_speed;
9791 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9792 dev_priv->display.get_display_clock_speed =
9793 i945_get_display_clock_speed;
9794 else if (IS_I915G(dev))
9795 dev_priv->display.get_display_clock_speed =
9796 i915_get_display_clock_speed;
9797 else if (IS_I945GM(dev) || IS_845G(dev))
9798 dev_priv->display.get_display_clock_speed =
9799 i9xx_misc_get_display_clock_speed;
9800 else if (IS_PINEVIEW(dev))
9801 dev_priv->display.get_display_clock_speed =
9802 pnv_get_display_clock_speed;
9803 else if (IS_I915GM(dev))
9804 dev_priv->display.get_display_clock_speed =
9805 i915gm_get_display_clock_speed;
9806 else if (IS_I865G(dev))
9807 dev_priv->display.get_display_clock_speed =
9808 i865_get_display_clock_speed;
9809 else if (IS_I85X(dev))
9810 dev_priv->display.get_display_clock_speed =
9811 i855_get_display_clock_speed;
9813 dev_priv->display.get_display_clock_speed =
9814 i830_get_display_clock_speed;
9816 if (HAS_PCH_SPLIT(dev)) {
9818 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9819 dev_priv->display.write_eld = ironlake_write_eld;
9820 } else if (IS_GEN6(dev)) {
9821 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9822 dev_priv->display.write_eld = ironlake_write_eld;
9823 } else if (IS_IVYBRIDGE(dev)) {
9824 /* FIXME: detect B0+ stepping and use auto training */
9825 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9826 dev_priv->display.write_eld = ironlake_write_eld;
9827 dev_priv->display.modeset_global_resources =
9828 ivb_modeset_global_resources;
9829 } else if (IS_HASWELL(dev)) {
9830 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9831 dev_priv->display.write_eld = haswell_write_eld;
9832 dev_priv->display.modeset_global_resources =
9833 haswell_modeset_global_resources;
9835 } else if (IS_G4X(dev)) {
9836 dev_priv->display.write_eld = g4x_write_eld;
9839 /* Default just returns -ENODEV to indicate unsupported */
9840 dev_priv->display.queue_flip = intel_default_queue_flip;
9842 switch (INTEL_INFO(dev)->gen) {
9844 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9848 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9853 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9857 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9860 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9866 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9867 * resume, or other times. This quirk makes sure that's the case for
9870 static void quirk_pipea_force(struct drm_device *dev)
9872 struct drm_i915_private *dev_priv = dev->dev_private;
9874 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9875 DRM_INFO("applying pipe a force quirk\n");
9879 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9881 static void quirk_ssc_force_disable(struct drm_device *dev)
9883 struct drm_i915_private *dev_priv = dev->dev_private;
9884 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9885 DRM_INFO("applying lvds SSC disable quirk\n");
9889 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9892 static void quirk_invert_brightness(struct drm_device *dev)
9894 struct drm_i915_private *dev_priv = dev->dev_private;
9895 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9896 DRM_INFO("applying inverted panel brightness quirk\n");
9900 * Some machines (Dell XPS13) suffer broken backlight controls if
9901 * BLM_PCH_PWM_ENABLE is set.
9903 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9905 struct drm_i915_private *dev_priv = dev->dev_private;
9906 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9907 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9910 struct intel_quirk {
9912 int subsystem_vendor;
9913 int subsystem_device;
9914 void (*hook)(struct drm_device *dev);
9917 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9918 struct intel_dmi_quirk {
9919 void (*hook)(struct drm_device *dev);
9920 const struct dmi_system_id (*dmi_id_list)[];
9923 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9925 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9929 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9931 .dmi_id_list = &(const struct dmi_system_id[]) {
9933 .callback = intel_dmi_reverse_brightness,
9934 .ident = "NCR Corporation",
9935 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9936 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9939 { } /* terminating entry */
9941 .hook = quirk_invert_brightness,
9945 static struct intel_quirk intel_quirks[] = {
9946 /* HP Mini needs pipe A force quirk (LP: #322104) */
9947 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9949 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9950 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9952 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9953 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9955 /* 830/845 need to leave pipe A & dpll A up */
9956 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9957 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9959 /* Lenovo U160 cannot use SSC on LVDS */
9960 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9962 /* Sony Vaio Y cannot use SSC on LVDS */
9963 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9965 /* Acer Aspire 5734Z must invert backlight brightness */
9966 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9968 /* Acer/eMachines G725 */
9969 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9971 /* Acer/eMachines e725 */
9972 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9974 /* Acer/Packard Bell NCL20 */
9975 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9977 /* Acer Aspire 4736Z */
9978 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9980 /* Dell XPS13 HD Sandy Bridge */
9981 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9982 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9983 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9986 static void intel_init_quirks(struct drm_device *dev)
9988 struct pci_dev *d = dev->pdev;
9991 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9992 struct intel_quirk *q = &intel_quirks[i];
9994 if (d->device == q->device &&
9995 (d->subsystem_vendor == q->subsystem_vendor ||
9996 q->subsystem_vendor == PCI_ANY_ID) &&
9997 (d->subsystem_device == q->subsystem_device ||
9998 q->subsystem_device == PCI_ANY_ID))
10001 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10002 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10003 intel_dmi_quirks[i].hook(dev);
10007 /* Disable the VGA plane that we never use */
10008 static void i915_disable_vga(struct drm_device *dev)
10010 struct drm_i915_private *dev_priv = dev->dev_private;
10012 u32 vga_reg = i915_vgacntrl_reg(dev);
10014 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10015 outb(SR01, VGA_SR_INDEX);
10016 sr1 = inb(VGA_SR_DATA);
10017 outb(sr1 | 1<<5, VGA_SR_DATA);
10018 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10021 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10022 POSTING_READ(vga_reg);
10025 void intel_modeset_init_hw(struct drm_device *dev)
10027 intel_init_power_well(dev);
10029 intel_prepare_ddi(dev);
10031 intel_init_clock_gating(dev);
10033 mutex_lock(&dev->struct_mutex);
10034 intel_enable_gt_powersave(dev);
10035 mutex_unlock(&dev->struct_mutex);
10038 void intel_modeset_suspend_hw(struct drm_device *dev)
10040 intel_suspend_hw(dev);
10043 void intel_modeset_init(struct drm_device *dev)
10045 struct drm_i915_private *dev_priv = dev->dev_private;
10048 drm_mode_config_init(dev);
10050 dev->mode_config.min_width = 0;
10051 dev->mode_config.min_height = 0;
10053 dev->mode_config.preferred_depth = 24;
10054 dev->mode_config.prefer_shadow = 1;
10056 dev->mode_config.funcs = &intel_mode_funcs;
10058 intel_init_quirks(dev);
10060 intel_init_pm(dev);
10062 if (INTEL_INFO(dev)->num_pipes == 0)
10065 intel_init_display(dev);
10067 if (IS_GEN2(dev)) {
10068 dev->mode_config.max_width = 2048;
10069 dev->mode_config.max_height = 2048;
10070 } else if (IS_GEN3(dev)) {
10071 dev->mode_config.max_width = 4096;
10072 dev->mode_config.max_height = 4096;
10074 dev->mode_config.max_width = 8192;
10075 dev->mode_config.max_height = 8192;
10077 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10079 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10080 INTEL_INFO(dev)->num_pipes,
10081 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10084 intel_crtc_init(dev, i);
10085 for (j = 0; j < dev_priv->num_plane; j++) {
10086 ret = intel_plane_init(dev, i, j);
10088 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10089 pipe_name(i), sprite_name(i, j), ret);
10093 intel_cpu_pll_init(dev);
10094 intel_shared_dpll_init(dev);
10096 /* Just disable it once at startup */
10097 i915_disable_vga(dev);
10098 intel_setup_outputs(dev);
10100 /* Just in case the BIOS is doing something questionable. */
10101 intel_disable_fbc(dev);
10105 intel_connector_break_all_links(struct intel_connector *connector)
10107 connector->base.dpms = DRM_MODE_DPMS_OFF;
10108 connector->base.encoder = NULL;
10109 connector->encoder->connectors_active = false;
10110 connector->encoder->base.crtc = NULL;
10113 static void intel_enable_pipe_a(struct drm_device *dev)
10115 struct intel_connector *connector;
10116 struct drm_connector *crt = NULL;
10117 struct intel_load_detect_pipe load_detect_temp;
10119 /* We can't just switch on the pipe A, we need to set things up with a
10120 * proper mode and output configuration. As a gross hack, enable pipe A
10121 * by enabling the load detect pipe once. */
10122 list_for_each_entry(connector,
10123 &dev->mode_config.connector_list,
10125 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10126 crt = &connector->base;
10134 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10135 intel_release_load_detect_pipe(crt, &load_detect_temp);
10141 intel_check_plane_mapping(struct intel_crtc *crtc)
10143 struct drm_device *dev = crtc->base.dev;
10144 struct drm_i915_private *dev_priv = dev->dev_private;
10147 if (INTEL_INFO(dev)->num_pipes == 1)
10150 reg = DSPCNTR(!crtc->plane);
10151 val = I915_READ(reg);
10153 if ((val & DISPLAY_PLANE_ENABLE) &&
10154 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10160 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10162 struct drm_device *dev = crtc->base.dev;
10163 struct drm_i915_private *dev_priv = dev->dev_private;
10166 /* Clear any frame start delays used for debugging left by the BIOS */
10167 reg = PIPECONF(crtc->config.cpu_transcoder);
10168 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10170 /* We need to sanitize the plane -> pipe mapping first because this will
10171 * disable the crtc (and hence change the state) if it is wrong. Note
10172 * that gen4+ has a fixed plane -> pipe mapping. */
10173 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10174 struct intel_connector *connector;
10177 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10178 crtc->base.base.id);
10180 /* Pipe has the wrong plane attached and the plane is active.
10181 * Temporarily change the plane mapping and disable everything
10183 plane = crtc->plane;
10184 crtc->plane = !plane;
10185 dev_priv->display.crtc_disable(&crtc->base);
10186 crtc->plane = plane;
10188 /* ... and break all links. */
10189 list_for_each_entry(connector, &dev->mode_config.connector_list,
10191 if (connector->encoder->base.crtc != &crtc->base)
10194 intel_connector_break_all_links(connector);
10197 WARN_ON(crtc->active);
10198 crtc->base.enabled = false;
10201 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10202 crtc->pipe == PIPE_A && !crtc->active) {
10203 /* BIOS forgot to enable pipe A, this mostly happens after
10204 * resume. Force-enable the pipe to fix this, the update_dpms
10205 * call below we restore the pipe to the right state, but leave
10206 * the required bits on. */
10207 intel_enable_pipe_a(dev);
10210 /* Adjust the state of the output pipe according to whether we
10211 * have active connectors/encoders. */
10212 intel_crtc_update_dpms(&crtc->base);
10214 if (crtc->active != crtc->base.enabled) {
10215 struct intel_encoder *encoder;
10217 /* This can happen either due to bugs in the get_hw_state
10218 * functions or because the pipe is force-enabled due to the
10220 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10221 crtc->base.base.id,
10222 crtc->base.enabled ? "enabled" : "disabled",
10223 crtc->active ? "enabled" : "disabled");
10225 crtc->base.enabled = crtc->active;
10227 /* Because we only establish the connector -> encoder ->
10228 * crtc links if something is active, this means the
10229 * crtc is now deactivated. Break the links. connector
10230 * -> encoder links are only establish when things are
10231 * actually up, hence no need to break them. */
10232 WARN_ON(crtc->active);
10234 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10235 WARN_ON(encoder->connectors_active);
10236 encoder->base.crtc = NULL;
10241 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10243 struct intel_connector *connector;
10244 struct drm_device *dev = encoder->base.dev;
10246 /* We need to check both for a crtc link (meaning that the
10247 * encoder is active and trying to read from a pipe) and the
10248 * pipe itself being active. */
10249 bool has_active_crtc = encoder->base.crtc &&
10250 to_intel_crtc(encoder->base.crtc)->active;
10252 if (encoder->connectors_active && !has_active_crtc) {
10253 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10254 encoder->base.base.id,
10255 drm_get_encoder_name(&encoder->base));
10257 /* Connector is active, but has no active pipe. This is
10258 * fallout from our resume register restoring. Disable
10259 * the encoder manually again. */
10260 if (encoder->base.crtc) {
10261 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10262 encoder->base.base.id,
10263 drm_get_encoder_name(&encoder->base));
10264 encoder->disable(encoder);
10267 /* Inconsistent output/port/pipe state happens presumably due to
10268 * a bug in one of the get_hw_state functions. Or someplace else
10269 * in our code, like the register restore mess on resume. Clamp
10270 * things to off as a safer default. */
10271 list_for_each_entry(connector,
10272 &dev->mode_config.connector_list,
10274 if (connector->encoder != encoder)
10277 intel_connector_break_all_links(connector);
10280 /* Enabled encoders without active connectors will be fixed in
10281 * the crtc fixup. */
10284 void i915_redisable_vga(struct drm_device *dev)
10286 struct drm_i915_private *dev_priv = dev->dev_private;
10287 u32 vga_reg = i915_vgacntrl_reg(dev);
10289 /* This function can be called both from intel_modeset_setup_hw_state or
10290 * at a very early point in our resume sequence, where the power well
10291 * structures are not yet restored. Since this function is at a very
10292 * paranoid "someone might have enabled VGA while we were not looking"
10293 * level, just check if the power well is enabled instead of trying to
10294 * follow the "don't touch the power well if we don't need it" policy
10295 * the rest of the driver uses. */
10296 if (HAS_POWER_WELL(dev) &&
10297 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10300 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10301 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10302 i915_disable_vga(dev);
10306 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10308 struct drm_i915_private *dev_priv = dev->dev_private;
10310 struct intel_crtc *crtc;
10311 struct intel_encoder *encoder;
10312 struct intel_connector *connector;
10315 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10317 memset(&crtc->config, 0, sizeof(crtc->config));
10319 crtc->active = dev_priv->display.get_pipe_config(crtc,
10322 crtc->base.enabled = crtc->active;
10324 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10325 crtc->base.base.id,
10326 crtc->active ? "enabled" : "disabled");
10329 /* FIXME: Smash this into the new shared dpll infrastructure. */
10331 intel_ddi_setup_hw_pll_state(dev);
10333 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10334 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10336 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10338 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10340 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10343 pll->refcount = pll->active;
10345 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10346 pll->name, pll->refcount, pll->on);
10349 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10353 if (encoder->get_hw_state(encoder, &pipe)) {
10354 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10355 encoder->base.crtc = &crtc->base;
10356 if (encoder->get_config)
10357 encoder->get_config(encoder, &crtc->config);
10359 encoder->base.crtc = NULL;
10362 encoder->connectors_active = false;
10363 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10364 encoder->base.base.id,
10365 drm_get_encoder_name(&encoder->base),
10366 encoder->base.crtc ? "enabled" : "disabled",
10370 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10374 if (dev_priv->display.get_clock)
10375 dev_priv->display.get_clock(crtc,
10379 list_for_each_entry(connector, &dev->mode_config.connector_list,
10381 if (connector->get_hw_state(connector)) {
10382 connector->base.dpms = DRM_MODE_DPMS_ON;
10383 connector->encoder->connectors_active = true;
10384 connector->base.encoder = &connector->encoder->base;
10386 connector->base.dpms = DRM_MODE_DPMS_OFF;
10387 connector->base.encoder = NULL;
10389 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10390 connector->base.base.id,
10391 drm_get_connector_name(&connector->base),
10392 connector->base.encoder ? "enabled" : "disabled");
10396 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10397 * and i915 state tracking structures. */
10398 void intel_modeset_setup_hw_state(struct drm_device *dev,
10399 bool force_restore)
10401 struct drm_i915_private *dev_priv = dev->dev_private;
10403 struct drm_plane *plane;
10404 struct intel_crtc *crtc;
10405 struct intel_encoder *encoder;
10408 intel_modeset_readout_hw_state(dev);
10411 * Now that we have the config, copy it to each CRTC struct
10412 * Note that this could go away if we move to using crtc_config
10413 * checking everywhere.
10415 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10417 if (crtc->active && i915_fastboot) {
10418 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10420 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10421 crtc->base.base.id);
10422 drm_mode_debug_printmodeline(&crtc->base.mode);
10426 /* HW state is read out, now we need to sanitize this mess. */
10427 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10429 intel_sanitize_encoder(encoder);
10432 for_each_pipe(pipe) {
10433 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10434 intel_sanitize_crtc(crtc);
10435 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10438 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10439 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10441 if (!pll->on || pll->active)
10444 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10446 pll->disable(dev_priv, pll);
10450 if (force_restore) {
10452 * We need to use raw interfaces for restoring state to avoid
10453 * checking (bogus) intermediate states.
10455 for_each_pipe(pipe) {
10456 struct drm_crtc *crtc =
10457 dev_priv->pipe_to_crtc_mapping[pipe];
10459 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10462 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10463 intel_plane_restore(plane);
10465 i915_redisable_vga(dev);
10467 intel_modeset_update_staged_output_state(dev);
10470 intel_modeset_check_state(dev);
10472 drm_mode_config_reset(dev);
10475 void intel_modeset_gem_init(struct drm_device *dev)
10477 intel_modeset_init_hw(dev);
10479 intel_setup_overlay(dev);
10481 intel_modeset_setup_hw_state(dev, false);
10484 void intel_modeset_cleanup(struct drm_device *dev)
10486 struct drm_i915_private *dev_priv = dev->dev_private;
10487 struct drm_crtc *crtc;
10490 * Interrupts and polling as the first thing to avoid creating havoc.
10491 * Too much stuff here (turning of rps, connectors, ...) would
10492 * experience fancy races otherwise.
10494 drm_irq_uninstall(dev);
10495 cancel_work_sync(&dev_priv->hotplug_work);
10497 * Due to the hpd irq storm handling the hotplug work can re-arm the
10498 * poll handlers. Hence disable polling after hpd handling is shut down.
10500 drm_kms_helper_poll_fini(dev);
10502 mutex_lock(&dev->struct_mutex);
10504 intel_unregister_dsm_handler();
10506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10507 /* Skip inactive CRTCs */
10511 intel_increase_pllclock(crtc);
10514 intel_disable_fbc(dev);
10516 intel_disable_gt_powersave(dev);
10518 ironlake_teardown_rc6(dev);
10520 mutex_unlock(&dev->struct_mutex);
10522 /* flush any delayed tasks or pending work */
10523 flush_scheduled_work();
10525 /* destroy backlight, if any, before the connectors */
10526 intel_panel_destroy_backlight(dev);
10528 drm_mode_config_cleanup(dev);
10530 intel_cleanup_overlay(dev);
10534 * Return which encoder is currently attached for connector.
10536 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10538 return &intel_attached_encoder(connector)->base;
10541 void intel_connector_attach_encoder(struct intel_connector *connector,
10542 struct intel_encoder *encoder)
10544 connector->encoder = encoder;
10545 drm_mode_connector_attach_encoder(&connector->base,
10550 * set vga decode state - true == enable VGA decode
10552 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10554 struct drm_i915_private *dev_priv = dev->dev_private;
10557 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10559 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10561 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10562 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10566 struct intel_display_error_state {
10568 u32 power_well_driver;
10570 int num_transcoders;
10572 struct intel_cursor_error_state {
10577 } cursor[I915_MAX_PIPES];
10579 struct intel_pipe_error_state {
10581 } pipe[I915_MAX_PIPES];
10583 struct intel_plane_error_state {
10591 } plane[I915_MAX_PIPES];
10593 struct intel_transcoder_error_state {
10594 enum transcoder cpu_transcoder;
10607 struct intel_display_error_state *
10608 intel_display_capture_error_state(struct drm_device *dev)
10610 drm_i915_private_t *dev_priv = dev->dev_private;
10611 struct intel_display_error_state *error;
10612 int transcoders[] = {
10620 if (INTEL_INFO(dev)->num_pipes == 0)
10623 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10627 if (HAS_POWER_WELL(dev))
10628 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10631 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10632 error->cursor[i].control = I915_READ(CURCNTR(i));
10633 error->cursor[i].position = I915_READ(CURPOS(i));
10634 error->cursor[i].base = I915_READ(CURBASE(i));
10636 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10637 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10638 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10641 error->plane[i].control = I915_READ(DSPCNTR(i));
10642 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10643 if (INTEL_INFO(dev)->gen <= 3) {
10644 error->plane[i].size = I915_READ(DSPSIZE(i));
10645 error->plane[i].pos = I915_READ(DSPPOS(i));
10647 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10648 error->plane[i].addr = I915_READ(DSPADDR(i));
10649 if (INTEL_INFO(dev)->gen >= 4) {
10650 error->plane[i].surface = I915_READ(DSPSURF(i));
10651 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10654 error->pipe[i].source = I915_READ(PIPESRC(i));
10657 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10658 if (HAS_DDI(dev_priv->dev))
10659 error->num_transcoders++; /* Account for eDP. */
10661 for (i = 0; i < error->num_transcoders; i++) {
10662 enum transcoder cpu_transcoder = transcoders[i];
10664 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10666 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10667 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10668 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10669 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10670 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10671 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10672 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10675 /* In the code above we read the registers without checking if the power
10676 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10677 * prevent the next I915_WRITE from detecting it and printing an error
10679 intel_uncore_clear_errors(dev);
10684 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10687 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10688 struct drm_device *dev,
10689 struct intel_display_error_state *error)
10696 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10697 if (HAS_POWER_WELL(dev))
10698 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10699 error->power_well_driver);
10701 err_printf(m, "Pipe [%d]:\n", i);
10702 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10704 err_printf(m, "Plane [%d]:\n", i);
10705 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10706 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10707 if (INTEL_INFO(dev)->gen <= 3) {
10708 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10709 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10711 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10712 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10713 if (INTEL_INFO(dev)->gen >= 4) {
10714 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10715 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10718 err_printf(m, "Cursor [%d]:\n", i);
10719 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10720 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10721 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10724 for (i = 0; i < error->num_transcoders; i++) {
10725 err_printf(m, " CPU transcoder: %c\n",
10726 transcoder_name(error->transcoder[i].cpu_transcoder));
10727 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10728 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10729 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10730 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10731 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10732 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10733 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);