drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 /* FDI */
  73 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  74
  75 int
  76 intel_pch_rawclk(struct drm_device *dev)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         WARN_ON(!HAS_PCH_SPLIT(dev));
  81
  82         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  83 }
  84
  85 static inline u32 /* units of 100MHz */
  86 intel_fdi_link_freq(struct drm_device *dev)
  87 {
  88         if (IS_GEN5(dev)) {
  89                 struct drm_i915_private *dev_priv = dev->dev_private;
  90                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  91         } else
  92                 return 27;
  93 }
  94
  95 static const intel_limit_t intel_limits_i8xx_dac = {
  96         .dot = { .min = 25000, .max = 350000 },
  97         .vco = { .min = 930000, .max = 1400000 },
  98         .n = { .min = 3, .max = 16 },
  99         .m = { .min = 96, .max = 140 },
 100         .m1 = { .min = 18, .max = 26 },
 101         .m2 = { .min = 6, .max = 16 },
 102         .p = { .min = 4, .max = 128 },
 103         .p1 = { .min = 2, .max = 33 },
 104         .p2 = { .dot_limit = 165000,
 105                 .p2_slow = 4, .p2_fast = 2 },
 106 };
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 4 },
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 8, .max = 18 },
 140         .m2 = { .min = 3, .max = 7 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_lvds = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 7, .max = 98 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 112000,
 157                 .p2_slow = 14, .p2_fast = 7 },
 158 };
 159
 160
 161 static const intel_limit_t intel_limits_g4x_sdvo = {
 162         .dot = { .min = 25000, .max = 270000 },
 163         .vco = { .min = 1750000, .max = 3500000},
 164         .n = { .min = 1, .max = 4 },
 165         .m = { .min = 104, .max = 138 },
 166         .m1 = { .min = 17, .max = 23 },
 167         .m2 = { .min = 5, .max = 11 },
 168         .p = { .min = 10, .max = 30 },
 169         .p1 = { .min = 1, .max = 3},
 170         .p2 = { .dot_limit = 270000,
 171                 .p2_slow = 10,
 172                 .p2_fast = 10
 173         },
 174 };
 175
 176 static const intel_limit_t intel_limits_g4x_hdmi = {
 177         .dot = { .min = 22000, .max = 400000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 16, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 5, .max = 80 },
 184         .p1 = { .min = 1, .max = 8},
 185         .p2 = { .dot_limit = 165000,
 186                 .p2_slow = 10, .p2_fast = 5 },
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 190         .dot = { .min = 20000, .max = 115000 },
 191         .vco = { .min = 1750000, .max = 3500000 },
 192         .n = { .min = 1, .max = 3 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 17, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 28, .max = 112 },
 197         .p1 = { .min = 2, .max = 8 },
 198         .p2 = { .dot_limit = 0,
 199                 .p2_slow = 14, .p2_fast = 14
 200         },
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 204         .dot = { .min = 80000, .max = 224000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 14, .max = 42 },
 211         .p1 = { .min = 2, .max = 6 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 7, .p2_fast = 7
 214         },
 215 };
 216
 217 static const intel_limit_t intel_limits_pineview_sdvo = {
 218         .dot = { .min = 20000, .max = 400000},
 219         .vco = { .min = 1700000, .max = 3500000 },
 220         /* Pineview's Ncounter is a ring counter */
 221         .n = { .min = 3, .max = 6 },
 222         .m = { .min = 2, .max = 256 },
 223         /* Pineview only has one combined m divider, which we treat as m2. */
 224         .m1 = { .min = 0, .max = 0 },
 225         .m2 = { .min = 0, .max = 254 },
 226         .p = { .min = 5, .max = 80 },
 227         .p1 = { .min = 1, .max = 8 },
 228         .p2 = { .dot_limit = 200000,
 229                 .p2_slow = 10, .p2_fast = 5 },
 230 };
 231
 232 static const intel_limit_t intel_limits_pineview_lvds = {
 233         .dot = { .min = 20000, .max = 400000 },
 234         .vco = { .min = 1700000, .max = 3500000 },
 235         .n = { .min = 3, .max = 6 },
 236         .m = { .min = 2, .max = 256 },
 237         .m1 = { .min = 0, .max = 0 },
 238         .m2 = { .min = 0, .max = 254 },
 239         .p = { .min = 7, .max = 112 },
 240         .p1 = { .min = 1, .max = 8 },
 241         .p2 = { .dot_limit = 112000,
 242                 .p2_slow = 14, .p2_fast = 14 },
 243 };
 244
 245 /* Ironlake / Sandybridge
 246  *
 247  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 248  * the range value for them is (actual_value - 2).
 249  */
 250 static const intel_limit_t intel_limits_ironlake_dac = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 1760000, .max = 3510000 },
 253         .n = { .min = 1, .max = 5 },
 254         .m = { .min = 79, .max = 127 },
 255         .m1 = { .min = 12, .max = 22 },
 256         .m2 = { .min = 5, .max = 9 },
 257         .p = { .min = 5, .max = 80 },
 258         .p1 = { .min = 1, .max = 8 },
 259         .p2 = { .dot_limit = 225000,
 260                 .p2_slow = 10, .p2_fast = 5 },
 261 };
 262
 263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 1760000, .max = 3510000 },
 266         .n = { .min = 1, .max = 3 },
 267         .m = { .min = 79, .max = 118 },
 268         .m1 = { .min = 12, .max = 22 },
 269         .m2 = { .min = 5, .max = 9 },
 270         .p = { .min = 28, .max = 112 },
 271         .p1 = { .min = 2, .max = 8 },
 272         .p2 = { .dot_limit = 225000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274 };
 275
 276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 1760000, .max = 3510000 },
 279         .n = { .min = 1, .max = 3 },
 280         .m = { .min = 79, .max = 127 },
 281         .m1 = { .min = 12, .max = 22 },
 282         .m2 = { .min = 5, .max = 9 },
 283         .p = { .min = 14, .max = 56 },
 284         .p1 = { .min = 2, .max = 8 },
 285         .p2 = { .dot_limit = 225000,
 286                 .p2_slow = 7, .p2_fast = 7 },
 287 };
 288
 289 /* LVDS 100mhz refclk limits. */
 290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 2 },
 294         .m = { .min = 79, .max = 126 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 28, .max = 112 },
 298         .p1 = { .min = 2, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 14, .p2_fast = 14 },
 301 };
 302
 303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 3 },
 307         .m = { .min = 79, .max = 126 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 14, .max = 42 },
 311         .p1 = { .min = 2, .max = 6 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 7, .p2_fast = 7 },
 314 };
 315
 316 static const intel_limit_t intel_limits_vlv_dac = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 4000000, .max = 6000000 },
 319         .n = { .min = 1, .max = 7 },
 320         .m = { .min = 22, .max = 450 }, /* guess */
 321         .m1 = { .min = 2, .max = 3 },
 322         .m2 = { .min = 11, .max = 156 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3 },
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 2, .p2_fast = 20 },
 327 };
 328
 329 static const intel_limit_t intel_limits_vlv_hdmi = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 4000000, .max = 6000000 },
 332         .n = { .min = 1, .max = 7 },
 333         .m = { .min = 60, .max = 300 }, /* guess */
 334         .m1 = { .min = 2, .max = 3 },
 335         .m2 = { .min = 11, .max = 156 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 2, .max = 3 },
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 2, .p2_fast = 20 },
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dp = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 },
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353 };
 354
 355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 356                                                 int refclk)
 357 {
 358         struct drm_device *dev = crtc->dev;
 359         const intel_limit_t *limit;
 360
 361         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 362                 if (intel_is_dual_link_lvds(dev)) {
 363                         if (refclk == 100000)
 364                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 365                         else
 366                                 limit = &intel_limits_ironlake_dual_lvds;
 367                 } else {
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_single_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_single_lvds;
 372                 }
 373         } else
 374                 limit = &intel_limits_ironlake_dac;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 385                 if (intel_is_dual_link_lvds(dev))
 386                         limit = &intel_limits_g4x_dual_channel_lvds;
 387                 else
 388                         limit = &intel_limits_g4x_single_channel_lvds;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 390                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 391                 limit = &intel_limits_g4x_hdmi;
 392         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 393                 limit = &intel_limits_g4x_sdvo;
 394         } else /* The option is for other outputs */
 395                 limit = &intel_limits_i9xx_sdvo;
 396
 397         return limit;
 398 }
 399
 400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 401 {
 402         struct drm_device *dev = crtc->dev;
 403         const intel_limit_t *limit;
 404
 405         if (HAS_PCH_SPLIT(dev))
 406                 limit = intel_ironlake_limit(crtc, refclk);
 407         else if (IS_G4X(dev)) {
 408                 limit = intel_g4x_limit(crtc);
 409         } else if (IS_PINEVIEW(dev)) {
 410                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 411                         limit = &intel_limits_pineview_lvds;
 412                 else
 413                         limit = &intel_limits_pineview_sdvo;
 414         } else if (IS_VALLEYVIEW(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 416                         limit = &intel_limits_vlv_dac;
 417                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 418                         limit = &intel_limits_vlv_hdmi;
 419                 else
 420                         limit = &intel_limits_vlv_dp;
 421         } else if (!IS_GEN2(dev)) {
 422                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 423                         limit = &intel_limits_i9xx_lvds;
 424                 else
 425                         limit = &intel_limits_i9xx_sdvo;
 426         } else {
 427                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 428                         limit = &intel_limits_i8xx_lvds;
 429                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 430                         limit = &intel_limits_i8xx_dvo;
 431                 else
 432                         limit = &intel_limits_i8xx_dac;
 433         }
 434         return limit;
 435 }
 436
 437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 438 static void pineview_clock(int refclk, intel_clock_t *clock)
 439 {
 440         clock->m = clock->m2 + 2;
 441         clock->p = clock->p1 * clock->p2;
 442         clock->vco = refclk * clock->m / clock->n;
 443         clock->dot = clock->vco / clock->p;
 444 }
 445
 446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 447 {
 448         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 449 }
 450
 451 static void i9xx_clock(int refclk, intel_clock_t *clock)
 452 {
 453         clock->m = i9xx_dpll_compute_m(clock);
 454         clock->p = clock->p1 * clock->p2;
 455         clock->vco = refclk * clock->m / (clock->n + 2);
 456         clock->dot = clock->vco / clock->p;
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 463 {
 464         struct drm_device *dev = crtc->dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, crtc, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 475 /**
 476  * Returns whether the given set of divisors are valid for a given refclk with
 477  * the given connectors.
 478  */
 479
 480 static bool intel_PLL_is_valid(struct drm_device *dev,
 481                                const intel_limit_t *limit,
 482                                const intel_clock_t *clock)
 483 {
 484         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 485                 INTELPllInvalid("p1 out of range\n");
 486         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 487                 INTELPllInvalid("p out of range\n");
 488         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 489                 INTELPllInvalid("m2 out of range\n");
 490         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 491                 INTELPllInvalid("m1 out of range\n");
 492         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 493                 INTELPllInvalid("m1 <= m2\n");
 494         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 495                 INTELPllInvalid("m out of range\n");
 496         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 497                 INTELPllInvalid("n out of range\n");
 498         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 499                 INTELPllInvalid("vco out of range\n");
 500         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 501          * connector, etc., rather than just a single range.
 502          */
 503         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 504                 INTELPllInvalid("dot out of range\n");
 505
 506         return true;
 507 }
 508
 509 static bool
 510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 511                     int target, int refclk, intel_clock_t *match_clock,
 512                     intel_clock_t *best_clock)
 513 {
 514         struct drm_device *dev = crtc->dev;
 515         intel_clock_t clock;
 516         int err = target;
 517
 518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 519                 /*
 520                  * For LVDS just rely on its current settings for dual-channel.
 521                  * We haven't figured out how to reliably set up different
 522                  * single/dual channel state, if we even can.
 523                  */
 524                 if (intel_is_dual_link_lvds(dev))
 525                         clock.p2 = limit->p2.p2_fast;
 526                 else
 527                         clock.p2 = limit->p2.p2_slow;
 528         } else {
 529                 if (target < limit->p2.dot_limit)
 530                         clock.p2 = limit->p2.p2_slow;
 531                 else
 532                         clock.p2 = limit->p2.p2_fast;
 533         }
 534
 535         memset(best_clock, 0, sizeof(*best_clock));
 536
 537         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 538              clock.m1++) {
 539                 for (clock.m2 = limit->m2.min;
 540                      clock.m2 <= limit->m2.max; clock.m2++) {
 541                         if (clock.m2 >= clock.m1)
 542                                 break;
 543                         for (clock.n = limit->n.min;
 544                              clock.n <= limit->n.max; clock.n++) {
 545                                 for (clock.p1 = limit->p1.min;
 546                                         clock.p1 <= limit->p1.max; clock.p1++) {
 547                                         int this_err;
 548
 549                                         i9xx_clock(refclk, &clock);
 550                                         if (!intel_PLL_is_valid(dev, limit,
 551                                                                 &clock))
 552                                                 continue;
 553                                         if (match_clock &&
 554                                             clock.p != match_clock->p)
 555                                                 continue;
 556
 557                                         this_err = abs(clock.dot - target);
 558                                         if (this_err < err) {
 559                                                 *best_clock = clock;
 560                                                 err = this_err;
 561                                         }
 562                                 }
 563                         }
 564                 }
 565         }
 566
 567         return (err != target);
 568 }
 569
 570 static bool
 571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 572                    int target, int refclk, intel_clock_t *match_clock,
 573                    intel_clock_t *best_clock)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         intel_clock_t clock;
 577         int err = target;
 578
 579         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 580                 /*
 581                  * For LVDS just rely on its current settings for dual-channel.
 582                  * We haven't figured out how to reliably set up different
 583                  * single/dual channel state, if we even can.
 584                  */
 585                 if (intel_is_dual_link_lvds(dev))
 586                         clock.p2 = limit->p2.p2_fast;
 587                 else
 588                         clock.p2 = limit->p2.p2_slow;
 589         } else {
 590                 if (target < limit->p2.dot_limit)
 591                         clock.p2 = limit->p2.p2_slow;
 592                 else
 593                         clock.p2 = limit->p2.p2_fast;
 594         }
 595
 596         memset(best_clock, 0, sizeof(*best_clock));
 597
 598         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 599              clock.m1++) {
 600                 for (clock.m2 = limit->m2.min;
 601                      clock.m2 <= limit->m2.max; clock.m2++) {
 602                         for (clock.n = limit->n.min;
 603                              clock.n <= limit->n.max; clock.n++) {
 604                                 for (clock.p1 = limit->p1.min;
 605                                         clock.p1 <= limit->p1.max; clock.p1++) {
 606                                         int this_err;
 607
 608                                         pineview_clock(refclk, &clock);
 609                                         if (!intel_PLL_is_valid(dev, limit,
 610                                                                 &clock))
 611                                                 continue;
 612                                         if (match_clock &&
 613                                             clock.p != match_clock->p)
 614                                                 continue;
 615
 616                                         this_err = abs(clock.dot - target);
 617                                         if (this_err < err) {
 618                                                 *best_clock = clock;
 619                                                 err = this_err;
 620                                         }
 621                                 }
 622                         }
 623                 }
 624         }
 625
 626         return (err != target);
 627 }
 628
 629 static bool
 630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 631                    int target, int refclk, intel_clock_t *match_clock,
 632                    intel_clock_t *best_clock)
 633 {
 634         struct drm_device *dev = crtc->dev;
 635         intel_clock_t clock;
 636         int max_n;
 637         bool found;
 638         /* approximately equals target * 0.00585 */
 639         int err_most = (target >> 8) + (target >> 9);
 640         found = false;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (intel_is_dual_link_lvds(dev))
 644                         clock.p2 = limit->p2.p2_fast;
 645                 else
 646                         clock.p2 = limit->p2.p2_slow;
 647         } else {
 648                 if (target < limit->p2.dot_limit)
 649                         clock.p2 = limit->p2.p2_slow;
 650                 else
 651                         clock.p2 = limit->p2.p2_fast;
 652         }
 653
 654         memset(best_clock, 0, sizeof(*best_clock));
 655         max_n = limit->n.max;
 656         /* based on hardware requirement, prefer smaller n to precision */
 657         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 658                 /* based on hardware requirement, prefere larger m1,m2 */
 659                 for (clock.m1 = limit->m1.max;
 660                      clock.m1 >= limit->m1.min; clock.m1--) {
 661                         for (clock.m2 = limit->m2.max;
 662                              clock.m2 >= limit->m2.min; clock.m2--) {
 663                                 for (clock.p1 = limit->p1.max;
 664                                      clock.p1 >= limit->p1.min; clock.p1--) {
 665                                         int this_err;
 666
 667                                         i9xx_clock(refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671
 672                                         this_err = abs(clock.dot - target);
 673                                         if (this_err < err_most) {
 674                                                 *best_clock = clock;
 675                                                 err_most = this_err;
 676                                                 max_n = clock.n;
 677                                                 found = true;
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683         return found;
 684 }
 685
 686 static bool
 687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 688                    int target, int refclk, intel_clock_t *match_clock,
 689                    intel_clock_t *best_clock)
 690 {
 691         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 692         u32 m, n, fastclk;
 693         u32 updrate, minupdate, fracbits, p;
 694         unsigned long bestppm, ppm, absppm;
 695         int dotclk, flag;
 696
 697         flag = 0;
 698         dotclk = target * 1000;
 699         bestppm = 1000000;
 700         ppm = absppm = 0;
 701         fastclk = dotclk / (2*100);
 702         updrate = 0;
 703         minupdate = 19200;
 704         fracbits = 1;
 705         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 706         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 707
 708         /* based on hardware requirement, prefer smaller n to precision */
 709         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 710                 updrate = refclk / n;
 711                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 712                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 713                                 if (p2 > 10)
 714                                         p2 = p2 - 1;
 715                                 p = p1 * p2;
 716                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 717                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 718                                         m2 = (((2*(fastclk * p * n / m1 )) +
 719                                                refclk) / (2*refclk));
 720                                         m = m1 * m2;
 721                                         vco = updrate * m;
 722                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 723                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 724                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 725                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 726                                                         bestppm = 0;
 727                                                         flag = 1;
 728                                                 }
 729                                                 if (absppm < bestppm - 10) {
 730                                                         bestppm = absppm;
 731                                                         flag = 1;
 732                                                 }
 733                                                 if (flag) {
 734                                                         bestn = n;
 735                                                         bestm1 = m1;
 736                                                         bestm2 = m2;
 737                                                         bestp1 = p1;
 738                                                         bestp2 = p2;
 739                                                         flag = 0;
 740                                                 }
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746         best_clock->n = bestn;
 747         best_clock->m1 = bestm1;
 748         best_clock->m2 = bestm2;
 749         best_clock->p1 = bestp1;
 750         best_clock->p2 = bestp2;
 751
 752         return true;
 753 }
 754
 755 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 756                                              enum pipe pipe)
 757 {
 758         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 760
 761         return intel_crtc->config.cpu_transcoder;
 762 }
 763
 764 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         u32 frame, frame_reg = PIPEFRAME(pipe);
 768
 769         frame = I915_READ(frame_reg);
 770
 771         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 772                 DRM_DEBUG_KMS("vblank wait timed out\n");
 773 }
 774
 775 /**
 776  * intel_wait_for_vblank - wait for vblank on a given pipe
 777  * @dev: drm device
 778  * @pipe: pipe to wait for
 779  *
 780  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 781  * mode setting code.
 782  */
 783 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         int pipestat_reg = PIPESTAT(pipe);
 787
 788         if (INTEL_INFO(dev)->gen >= 5) {
 789                 ironlake_wait_for_vblank(dev, pipe);
 790                 return;
 791         }
 792
 793         /* Clear existing vblank status. Note this will clear any other
 794          * sticky status fields as well.
 795          *
 796          * This races with i915_driver_irq_handler() with the result
 797          * that either function could miss a vblank event.  Here it is not
 798          * fatal, as we will either wait upon the next vblank interrupt or
 799          * timeout.  Generally speaking intel_wait_for_vblank() is only
 800          * called during modeset at which time the GPU should be idle and
 801          * should *not* be performing page flips and thus not waiting on
 802          * vblanks...
 803          * Currently, the result of us stealing a vblank from the irq
 804          * handler is that a single frame will be skipped during swapbuffers.
 805          */
 806         I915_WRITE(pipestat_reg,
 807                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 808
 809         /* Wait for vblank interrupt bit to set */
 810         if (wait_for(I915_READ(pipestat_reg) &
 811                      PIPE_VBLANK_INTERRUPT_STATUS,
 812                      50))
 813                 DRM_DEBUG_KMS("vblank wait timed out\n");
 814 }
 815
 816 /*
 817  * intel_wait_for_pipe_off - wait for pipe to turn off
 818  * @dev: drm device
 819  * @pipe: pipe to wait for
 820  *
 821  * After disabling a pipe, we can't wait for vblank in the usual way,
 822  * spinning on the vblank interrupt status bit, since we won't actually
 823  * see an interrupt when the pipe is disabled.
 824  *
 825  * On Gen4 and above:
 826  *   wait for the pipe register state bit to turn off
 827  *
 828  * Otherwise:
 829  *   wait for the display line value to settle (it usually
 830  *   ends up stopping at the start of the next frame).
 831  *
 832  */
 833 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 837                                                                       pipe);
 838
 839         if (INTEL_INFO(dev)->gen >= 4) {
 840                 int reg = PIPECONF(cpu_transcoder);
 841
 842                 /* Wait for the Pipe State to go off */
 843                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 844                              100))
 845                         WARN(1, "pipe_off wait timed out\n");
 846         } else {
 847                 u32 last_line, line_mask;
 848                 int reg = PIPEDSL(pipe);
 849                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 850
 851                 if (IS_GEN2(dev))
 852                         line_mask = DSL_LINEMASK_GEN2;
 853                 else
 854                         line_mask = DSL_LINEMASK_GEN3;
 855
 856                 /* Wait for the display line to settle */
 857                 do {
 858                         last_line = I915_READ(reg) & line_mask;
 859                         mdelay(5);
 860                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 861                          time_after(timeout, jiffies));
 862                 if (time_after(jiffies, timeout))
 863                         WARN(1, "pipe_off wait timed out\n");
 864         }
 865 }
 866
 867 /*
 868  * ibx_digital_port_connected - is the specified port connected?
 869  * @dev_priv: i915 private structure
 870  * @port: the port to test
 871  *
 872  * Returns true if @port is connected, false otherwise.
 873  */
 874 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 875                                 struct intel_digital_port *port)
 876 {
 877         u32 bit;
 878
 879         if (HAS_PCH_IBX(dev_priv->dev)) {
 880                 switch(port->port) {
 881                 case PORT_B:
 882                         bit = SDE_PORTB_HOTPLUG;
 883                         break;
 884                 case PORT_C:
 885                         bit = SDE_PORTC_HOTPLUG;
 886                         break;
 887                 case PORT_D:
 888                         bit = SDE_PORTD_HOTPLUG;
 889                         break;
 890                 default:
 891                         return true;
 892                 }
 893         } else {
 894                 switch(port->port) {
 895                 case PORT_B:
 896                         bit = SDE_PORTB_HOTPLUG_CPT;
 897                         break;
 898                 case PORT_C:
 899                         bit = SDE_PORTC_HOTPLUG_CPT;
 900                         break;
 901                 case PORT_D:
 902                         bit = SDE_PORTD_HOTPLUG_CPT;
 903                         break;
 904                 default:
 905                         return true;
 906                 }
 907         }
 908
 909         return I915_READ(SDEISR) & bit;
 910 }
 911
 912 static const char *state_string(bool enabled)
 913 {
 914         return enabled ? "on" : "off";
 915 }
 916
 917 /* Only for pre-ILK configs */
 918 void assert_pll(struct drm_i915_private *dev_priv,
 919                 enum pipe pipe, bool state)
 920 {
 921         int reg;
 922         u32 val;
 923         bool cur_state;
 924
 925         reg = DPLL(pipe);
 926         val = I915_READ(reg);
 927         cur_state = !!(val & DPLL_VCO_ENABLE);
 928         WARN(cur_state != state,
 929              "PLL state assertion failure (expected %s, current %s)\n",
 930              state_string(state), state_string(cur_state));
 931 }
 932
 933 struct intel_shared_dpll *
 934 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 935 {
 936         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 937
 938         if (crtc->config.shared_dpll < 0)
 939                 return NULL;
 940
 941         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 942 }
 943
 944 /* For ILK+ */
 945 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 946                         struct intel_shared_dpll *pll,
 947                         bool state)
 948 {
 949         bool cur_state;
 950         struct intel_dpll_hw_state hw_state;
 951
 952         if (HAS_PCH_LPT(dev_priv->dev)) {
 953                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 954                 return;
 955         }
 956
 957         if (WARN (!pll,
 958                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 959                 return;
 960
 961         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 962         WARN(cur_state != state,
 963              "%s assertion failure (expected %s, current %s)\n",
 964              pll->name, state_string(state), state_string(cur_state));
 965 }
 966
 967 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 968                           enum pipe pipe, bool state)
 969 {
 970         int reg;
 971         u32 val;
 972         bool cur_state;
 973         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 974                                                                       pipe);
 975
 976         if (HAS_DDI(dev_priv->dev)) {
 977                 /* DDI does not have a specific FDI_TX register */
 978                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 981         } else {
 982                 reg = FDI_TX_CTL(pipe);
 983                 val = I915_READ(reg);
 984                 cur_state = !!(val & FDI_TX_ENABLE);
 985         }
 986         WARN(cur_state != state,
 987              "FDI TX state assertion failure (expected %s, current %s)\n",
 988              state_string(state), state_string(cur_state));
 989 }
 990 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 991 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 992
 993 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 994                           enum pipe pipe, bool state)
 995 {
 996         int reg;
 997         u32 val;
 998         bool cur_state;
 999
1000         reg = FDI_RX_CTL(pipe);
1001         val = I915_READ(reg);
1002         cur_state = !!(val & FDI_RX_ENABLE);
1003         WARN(cur_state != state,
1004              "FDI RX state assertion failure (expected %s, current %s)\n",
1005              state_string(state), state_string(cur_state));
1006 }
1007 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1008 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009
1010 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1011                                       enum pipe pipe)
1012 {
1013         int reg;
1014         u32 val;
1015
1016         /* ILK FDI PLL is always enabled */
1017         if (dev_priv->info->gen == 5)
1018                 return;
1019
1020         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1021         if (HAS_DDI(dev_priv->dev))
1022                 return;
1023
1024         reg = FDI_TX_CTL(pipe);
1025         val = I915_READ(reg);
1026         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1027 }
1028
1029 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1030                        enum pipe pipe, bool state)
1031 {
1032         int reg;
1033         u32 val;
1034         bool cur_state;
1035
1036         reg = FDI_RX_CTL(pipe);
1037         val = I915_READ(reg);
1038         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1039         WARN(cur_state != state,
1040              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1041              state_string(state), state_string(cur_state));
1042 }
1043
1044 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1045                                   enum pipe pipe)
1046 {
1047         int pp_reg, lvds_reg;
1048         u32 val;
1049         enum pipe panel_pipe = PIPE_A;
1050         bool locked = true;
1051
1052         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1053                 pp_reg = PCH_PP_CONTROL;
1054                 lvds_reg = PCH_LVDS;
1055         } else {
1056                 pp_reg = PP_CONTROL;
1057                 lvds_reg = LVDS;
1058         }
1059
1060         val = I915_READ(pp_reg);
1061         if (!(val & PANEL_POWER_ON) ||
1062             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1063                 locked = false;
1064
1065         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1066                 panel_pipe = PIPE_B;
1067
1068         WARN(panel_pipe == pipe && locked,
1069              "panel assertion failure, pipe %c regs locked\n",
1070              pipe_name(pipe));
1071 }
1072
1073 void assert_pipe(struct drm_i915_private *dev_priv,
1074                  enum pipe pipe, bool state)
1075 {
1076         int reg;
1077         u32 val;
1078         bool cur_state;
1079         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1080                                                                       pipe);
1081
1082         /* if we need the pipe A quirk it must be always on */
1083         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1084                 state = true;
1085
1086         if (!intel_display_power_enabled(dev_priv->dev,
1087                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1088                 cur_state = false;
1089         } else {
1090                 reg = PIPECONF(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & PIPECONF_ENABLE);
1093         }
1094
1095         WARN(cur_state != state,
1096              "pipe %c assertion failure (expected %s, current %s)\n",
1097              pipe_name(pipe), state_string(state), state_string(cur_state));
1098 }
1099
1100 static void assert_plane(struct drm_i915_private *dev_priv,
1101                          enum plane plane, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         reg = DSPCNTR(plane);
1108         val = I915_READ(reg);
1109         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1110         WARN(cur_state != state,
1111              "plane %c assertion failure (expected %s, current %s)\n",
1112              plane_name(plane), state_string(state), state_string(cur_state));
1113 }
1114
1115 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1116 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1117
1118 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1119                                    enum pipe pipe)
1120 {
1121         struct drm_device *dev = dev_priv->dev;
1122         int reg, i;
1123         u32 val;
1124         int cur_pipe;
1125
1126         /* Primary planes are fixed to pipes on gen4+ */
1127         if (INTEL_INFO(dev)->gen >= 4) {
1128                 reg = DSPCNTR(pipe);
1129                 val = I915_READ(reg);
1130                 WARN((val & DISPLAY_PLANE_ENABLE),
1131                      "plane %c assertion failure, should be disabled but not\n",
1132                      plane_name(pipe));
1133                 return;
1134         }
1135
1136         /* Need to check both planes against the pipe */
1137         for_each_pipe(i) {
1138                 reg = DSPCNTR(i);
1139                 val = I915_READ(reg);
1140                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1141                         DISPPLANE_SEL_PIPE_SHIFT;
1142                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1143                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1144                      plane_name(i), pipe_name(pipe));
1145         }
1146 }
1147
1148 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1149                                     enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154
1155         if (IS_VALLEYVIEW(dev)) {
1156                 for (i = 0; i < dev_priv->num_plane; i++) {
1157                         reg = SPCNTR(pipe, i);
1158                         val = I915_READ(reg);
1159                         WARN((val & SP_ENABLE),
1160                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1161                              sprite_name(pipe, i), pipe_name(pipe));
1162                 }
1163         } else if (INTEL_INFO(dev)->gen >= 7) {
1164                 reg = SPRCTL(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & SPRITE_ENABLE),
1167                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1168                      plane_name(pipe), pipe_name(pipe));
1169         } else if (INTEL_INFO(dev)->gen >= 5) {
1170                 reg = DVSCNTR(pipe);
1171                 val = I915_READ(reg);
1172                 WARN((val & DVS_ENABLE),
1173                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(pipe), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1179 {
1180         u32 val;
1181         bool enabled;
1182
1183         if (HAS_PCH_LPT(dev_priv->dev)) {
1184                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1185                 return;
1186         }
1187
1188         val = I915_READ(PCH_DREF_CONTROL);
1189         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1190                             DREF_SUPERSPREAD_SOURCE_MASK));
1191         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1192 }
1193
1194 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1195                                            enum pipe pipe)
1196 {
1197         int reg;
1198         u32 val;
1199         bool enabled;
1200
1201         reg = PCH_TRANSCONF(pipe);
1202         val = I915_READ(reg);
1203         enabled = !!(val & TRANS_ENABLE);
1204         WARN(enabled,
1205              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1206              pipe_name(pipe));
1207 }
1208
1209 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1210                             enum pipe pipe, u32 port_sel, u32 val)
1211 {
1212         if ((val & DP_PORT_EN) == 0)
1213                 return false;
1214
1215         if (HAS_PCH_CPT(dev_priv->dev)) {
1216                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1217                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1218                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1219                         return false;
1220         } else {
1221                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1222                         return false;
1223         }
1224         return true;
1225 }
1226
1227 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1228                               enum pipe pipe, u32 val)
1229 {
1230         if ((val & SDVO_ENABLE) == 0)
1231                 return false;
1232
1233         if (HAS_PCH_CPT(dev_priv->dev)) {
1234                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1235                         return false;
1236         } else {
1237                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1238                         return false;
1239         }
1240         return true;
1241 }
1242
1243 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1244                               enum pipe pipe, u32 val)
1245 {
1246         if ((val & LVDS_PORT_EN) == 0)
1247                 return false;
1248
1249         if (HAS_PCH_CPT(dev_priv->dev)) {
1250                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1251                         return false;
1252         } else {
1253                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1254                         return false;
1255         }
1256         return true;
1257 }
1258
1259 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1260                               enum pipe pipe, u32 val)
1261 {
1262         if ((val & ADPA_DAC_ENABLE) == 0)
1263                 return false;
1264         if (HAS_PCH_CPT(dev_priv->dev)) {
1265                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266                         return false;
1267         } else {
1268                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1269                         return false;
1270         }
1271         return true;
1272 }
1273
1274 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1275                                    enum pipe pipe, int reg, u32 port_sel)
1276 {
1277         u32 val = I915_READ(reg);
1278         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1279              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1280              reg, pipe_name(pipe));
1281
1282         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1283              && (val & DP_PIPEB_SELECT),
1284              "IBX PCH dp port still using transcoder B\n");
1285 }
1286
1287 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1288                                      enum pipe pipe, int reg)
1289 {
1290         u32 val = I915_READ(reg);
1291         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1292              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1293              reg, pipe_name(pipe));
1294
1295         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1296              && (val & SDVO_PIPE_B_SELECT),
1297              "IBX PCH hdmi port still using transcoder B\n");
1298 }
1299
1300 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1301                                       enum pipe pipe)
1302 {
1303         int reg;
1304         u32 val;
1305
1306         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1307         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1308         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1309
1310         reg = PCH_ADPA;
1311         val = I915_READ(reg);
1312         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1313              "PCH VGA enabled on transcoder %c, should be disabled\n",
1314              pipe_name(pipe));
1315
1316         reg = PCH_LVDS;
1317         val = I915_READ(reg);
1318         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1319              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1320              pipe_name(pipe));
1321
1322         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1323         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1324         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1325 }
1326
1327 static void vlv_enable_pll(struct intel_crtc *crtc)
1328 {
1329         struct drm_device *dev = crtc->base.dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         int reg = DPLL(crtc->pipe);
1332         u32 dpll = crtc->config.dpll_hw_state.dpll;
1333
1334         assert_pipe_disabled(dev_priv, crtc->pipe);
1335
1336         /* No really, not for ILK+ */
1337         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1338
1339         /* PLL is protected by panel, make sure we can write it */
1340         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1341                 assert_panel_unlocked(dev_priv, crtc->pipe);
1342
1343         I915_WRITE(reg, dpll);
1344         POSTING_READ(reg);
1345         udelay(150);
1346
1347         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1348                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1349
1350         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1351         POSTING_READ(DPLL_MD(crtc->pipe));
1352
1353         /* We do this three times for luck */
1354         I915_WRITE(reg, dpll);
1355         POSTING_READ(reg);
1356         udelay(150); /* wait for warmup */
1357         I915_WRITE(reg, dpll);
1358         POSTING_READ(reg);
1359         udelay(150); /* wait for warmup */
1360         I915_WRITE(reg, dpll);
1361         POSTING_READ(reg);
1362         udelay(150); /* wait for warmup */
1363 }
1364
1365 static void i9xx_enable_pll(struct intel_crtc *crtc)
1366 {
1367         struct drm_device *dev = crtc->base.dev;
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         int reg = DPLL(crtc->pipe);
1370         u32 dpll = crtc->config.dpll_hw_state.dpll;
1371
1372         assert_pipe_disabled(dev_priv, crtc->pipe);
1373
1374         /* No really, not for ILK+ */
1375         BUG_ON(dev_priv->info->gen >= 5);
1376
1377         /* PLL is protected by panel, make sure we can write it */
1378         if (IS_MOBILE(dev) && !IS_I830(dev))
1379                 assert_panel_unlocked(dev_priv, crtc->pipe);
1380
1381         I915_WRITE(reg, dpll);
1382
1383         /* Wait for the clocks to stabilize. */
1384         POSTING_READ(reg);
1385         udelay(150);
1386
1387         if (INTEL_INFO(dev)->gen >= 4) {
1388                 I915_WRITE(DPLL_MD(crtc->pipe),
1389                            crtc->config.dpll_hw_state.dpll_md);
1390         } else {
1391                 /* The pixel multiplier can only be updated once the
1392                  * DPLL is enabled and the clocks are stable.
1393                  *
1394                  * So write it again.
1395                  */
1396                 I915_WRITE(reg, dpll);
1397         }
1398
1399         /* We do this three times for luck */
1400         I915_WRITE(reg, dpll);
1401         POSTING_READ(reg);
1402         udelay(150); /* wait for warmup */
1403         I915_WRITE(reg, dpll);
1404         POSTING_READ(reg);
1405         udelay(150); /* wait for warmup */
1406         I915_WRITE(reg, dpll);
1407         POSTING_READ(reg);
1408         udelay(150); /* wait for warmup */
1409 }
1410
1411 /**
1412  * i9xx_disable_pll - disable a PLL
1413  * @dev_priv: i915 private structure
1414  * @pipe: pipe PLL to disable
1415  *
1416  * Disable the PLL for @pipe, making sure the pipe is off first.
1417  *
1418  * Note!  This is for pre-ILK only.
1419  */
1420 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1421 {
1422         /* Don't disable pipe A or pipe A PLLs if needed */
1423         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1424                 return;
1425
1426         /* Make sure the pipe isn't still relying on us */
1427         assert_pipe_disabled(dev_priv, pipe);
1428
1429         I915_WRITE(DPLL(pipe), 0);
1430         POSTING_READ(DPLL(pipe));
1431 }
1432
1433 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1434 {
1435         u32 port_mask;
1436
1437         if (!port)
1438                 port_mask = DPLL_PORTB_READY_MASK;
1439         else
1440                 port_mask = DPLL_PORTC_READY_MASK;
1441
1442         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1443                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1444                      'B' + port, I915_READ(DPLL(0)));
1445 }
1446
1447 /**
1448  * ironlake_enable_shared_dpll - enable PCH PLL
1449  * @dev_priv: i915 private structure
1450  * @pipe: pipe PLL to enable
1451  *
1452  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1453  * drives the transcoder clock.
1454  */
1455 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1456 {
1457         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1458         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1459
1460         /* PCH PLLs only available on ILK, SNB and IVB */
1461         BUG_ON(dev_priv->info->gen < 5);
1462         if (WARN_ON(pll == NULL))
1463                 return;
1464
1465         if (WARN_ON(pll->refcount == 0))
1466                 return;
1467
1468         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1469                       pll->name, pll->active, pll->on,
1470                       crtc->base.base.id);
1471
1472         if (pll->active++) {
1473                 WARN_ON(!pll->on);
1474                 assert_shared_dpll_enabled(dev_priv, pll);
1475                 return;
1476         }
1477         WARN_ON(pll->on);
1478
1479         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1480         pll->enable(dev_priv, pll);
1481         pll->on = true;
1482 }
1483
1484 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1485 {
1486         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1487         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1488
1489         /* PCH only available on ILK+ */
1490         BUG_ON(dev_priv->info->gen < 5);
1491         if (WARN_ON(pll == NULL))
1492                return;
1493
1494         if (WARN_ON(pll->refcount == 0))
1495                 return;
1496
1497         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1498                       pll->name, pll->active, pll->on,
1499                       crtc->base.base.id);
1500
1501         if (WARN_ON(pll->active == 0)) {
1502                 assert_shared_dpll_disabled(dev_priv, pll);
1503                 return;
1504         }
1505
1506         assert_shared_dpll_enabled(dev_priv, pll);
1507         WARN_ON(!pll->on);
1508         if (--pll->active)
1509                 return;
1510
1511         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1512         pll->disable(dev_priv, pll);
1513         pll->on = false;
1514 }
1515
1516 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1517                                            enum pipe pipe)
1518 {
1519         struct drm_device *dev = dev_priv->dev;
1520         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1522         uint32_t reg, val, pipeconf_val;
1523
1524         /* PCH only available on ILK+ */
1525         BUG_ON(dev_priv->info->gen < 5);
1526
1527         /* Make sure PCH DPLL is enabled */
1528         assert_shared_dpll_enabled(dev_priv,
1529                                    intel_crtc_to_shared_dpll(intel_crtc));
1530
1531         /* FDI must be feeding us bits for PCH ports */
1532         assert_fdi_tx_enabled(dev_priv, pipe);
1533         assert_fdi_rx_enabled(dev_priv, pipe);
1534
1535         if (HAS_PCH_CPT(dev)) {
1536                 /* Workaround: Set the timing override bit before enabling the
1537                  * pch transcoder. */
1538                 reg = TRANS_CHICKEN2(pipe);
1539                 val = I915_READ(reg);
1540                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1541                 I915_WRITE(reg, val);
1542         }
1543
1544         reg = PCH_TRANSCONF(pipe);
1545         val = I915_READ(reg);
1546         pipeconf_val = I915_READ(PIPECONF(pipe));
1547
1548         if (HAS_PCH_IBX(dev_priv->dev)) {
1549                 /*
1550                  * make the BPC in transcoder be consistent with
1551                  * that in pipeconf reg.
1552                  */
1553                 val &= ~PIPECONF_BPC_MASK;
1554                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1555         }
1556
1557         val &= ~TRANS_INTERLACE_MASK;
1558         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1559                 if (HAS_PCH_IBX(dev_priv->dev) &&
1560                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1561                         val |= TRANS_LEGACY_INTERLACED_ILK;
1562                 else
1563                         val |= TRANS_INTERLACED;
1564         else
1565                 val |= TRANS_PROGRESSIVE;
1566
1567         I915_WRITE(reg, val | TRANS_ENABLE);
1568         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1569                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1570 }
1571
1572 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1573                                       enum transcoder cpu_transcoder)
1574 {
1575         u32 val, pipeconf_val;
1576
1577         /* PCH only available on ILK+ */
1578         BUG_ON(dev_priv->info->gen < 5);
1579
1580         /* FDI must be feeding us bits for PCH ports */
1581         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1582         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1583
1584         /* Workaround: set timing override bit. */
1585         val = I915_READ(_TRANSA_CHICKEN2);
1586         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1587         I915_WRITE(_TRANSA_CHICKEN2, val);
1588
1589         val = TRANS_ENABLE;
1590         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1591
1592         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1593             PIPECONF_INTERLACED_ILK)
1594                 val |= TRANS_INTERLACED;
1595         else
1596                 val |= TRANS_PROGRESSIVE;
1597
1598         I915_WRITE(LPT_TRANSCONF, val);
1599         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1600                 DRM_ERROR("Failed to enable PCH transcoder\n");
1601 }
1602
1603 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1604                                             enum pipe pipe)
1605 {
1606         struct drm_device *dev = dev_priv->dev;
1607         uint32_t reg, val;
1608
1609         /* FDI relies on the transcoder */
1610         assert_fdi_tx_disabled(dev_priv, pipe);
1611         assert_fdi_rx_disabled(dev_priv, pipe);
1612
1613         /* Ports must be off as well */
1614         assert_pch_ports_disabled(dev_priv, pipe);
1615
1616         reg = PCH_TRANSCONF(pipe);
1617         val = I915_READ(reg);
1618         val &= ~TRANS_ENABLE;
1619         I915_WRITE(reg, val);
1620         /* wait for PCH transcoder off, transcoder state */
1621         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1622                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1623
1624         if (!HAS_PCH_IBX(dev)) {
1625                 /* Workaround: Clear the timing override chicken bit again. */
1626                 reg = TRANS_CHICKEN2(pipe);
1627                 val = I915_READ(reg);
1628                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1629                 I915_WRITE(reg, val);
1630         }
1631 }
1632
1633 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1634 {
1635         u32 val;
1636
1637         val = I915_READ(LPT_TRANSCONF);
1638         val &= ~TRANS_ENABLE;
1639         I915_WRITE(LPT_TRANSCONF, val);
1640         /* wait for PCH transcoder off, transcoder state */
1641         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1642                 DRM_ERROR("Failed to disable PCH transcoder\n");
1643
1644         /* Workaround: clear timing override bit. */
1645         val = I915_READ(_TRANSA_CHICKEN2);
1646         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1647         I915_WRITE(_TRANSA_CHICKEN2, val);
1648 }
1649
1650 /**
1651  * intel_enable_pipe - enable a pipe, asserting requirements
1652  * @dev_priv: i915 private structure
1653  * @pipe: pipe to enable
1654  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1655  *
1656  * Enable @pipe, making sure that various hardware specific requirements
1657  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1658  *
1659  * @pipe should be %PIPE_A or %PIPE_B.
1660  *
1661  * Will wait until the pipe is actually running (i.e. first vblank) before
1662  * returning.
1663  */
1664 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1665                               bool pch_port)
1666 {
1667         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1668                                                                       pipe);
1669         enum pipe pch_transcoder;
1670         int reg;
1671         u32 val;
1672
1673         assert_planes_disabled(dev_priv, pipe);
1674         assert_sprites_disabled(dev_priv, pipe);
1675
1676         if (HAS_PCH_LPT(dev_priv->dev))
1677                 pch_transcoder = TRANSCODER_A;
1678         else
1679                 pch_transcoder = pipe;
1680
1681         /*
1682          * A pipe without a PLL won't actually be able to drive bits from
1683          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1684          * need the check.
1685          */
1686         if (!HAS_PCH_SPLIT(dev_priv->dev))
1687                 assert_pll_enabled(dev_priv, pipe);
1688         else {
1689                 if (pch_port) {
1690                         /* if driving the PCH, we need FDI enabled */
1691                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1692                         assert_fdi_tx_pll_enabled(dev_priv,
1693                                                   (enum pipe) cpu_transcoder);
1694                 }
1695                 /* FIXME: assert CPU port conditions for SNB+ */
1696         }
1697
1698         reg = PIPECONF(cpu_transcoder);
1699         val = I915_READ(reg);
1700         if (val & PIPECONF_ENABLE)
1701                 return;
1702
1703         I915_WRITE(reg, val | PIPECONF_ENABLE);
1704         intel_wait_for_vblank(dev_priv->dev, pipe);
1705 }
1706
1707 /**
1708  * intel_disable_pipe - disable a pipe, asserting requirements
1709  * @dev_priv: i915 private structure
1710  * @pipe: pipe to disable
1711  *
1712  * Disable @pipe, making sure that various hardware specific requirements
1713  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1714  *
1715  * @pipe should be %PIPE_A or %PIPE_B.
1716  *
1717  * Will wait until the pipe has shut down before returning.
1718  */
1719 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1720                                enum pipe pipe)
1721 {
1722         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1723                                                                       pipe);
1724         int reg;
1725         u32 val;
1726
1727         /*
1728          * Make sure planes won't keep trying to pump pixels to us,
1729          * or we might hang the display.
1730          */
1731         assert_planes_disabled(dev_priv, pipe);
1732         assert_sprites_disabled(dev_priv, pipe);
1733
1734         /* Don't disable pipe A or pipe A PLLs if needed */
1735         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1736                 return;
1737
1738         reg = PIPECONF(cpu_transcoder);
1739         val = I915_READ(reg);
1740         if ((val & PIPECONF_ENABLE) == 0)
1741                 return;
1742
1743         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1744         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1745 }
1746
1747 /*
1748  * Plane regs are double buffered, going from enabled->disabled needs a
1749  * trigger in order to latch.  The display address reg provides this.
1750  */
1751 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1752                                       enum plane plane)
1753 {
1754         if (dev_priv->info->gen >= 4)
1755                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1756         else
1757                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1758 }
1759
1760 /**
1761  * intel_enable_plane - enable a display plane on a given pipe
1762  * @dev_priv: i915 private structure
1763  * @plane: plane to enable
1764  * @pipe: pipe being fed
1765  *
1766  * Enable @plane on @pipe, making sure that @pipe is running first.
1767  */
1768 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1769                                enum plane plane, enum pipe pipe)
1770 {
1771         int reg;
1772         u32 val;
1773
1774         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1775         assert_pipe_enabled(dev_priv, pipe);
1776
1777         reg = DSPCNTR(plane);
1778         val = I915_READ(reg);
1779         if (val & DISPLAY_PLANE_ENABLE)
1780                 return;
1781
1782         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1783         intel_flush_display_plane(dev_priv, plane);
1784         intel_wait_for_vblank(dev_priv->dev, pipe);
1785 }
1786
1787 /**
1788  * intel_disable_plane - disable a display plane
1789  * @dev_priv: i915 private structure
1790  * @plane: plane to disable
1791  * @pipe: pipe consuming the data
1792  *
1793  * Disable @plane; should be an independent operation.
1794  */
1795 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1796                                 enum plane plane, enum pipe pipe)
1797 {
1798         int reg;
1799         u32 val;
1800
1801         reg = DSPCNTR(plane);
1802         val = I915_READ(reg);
1803         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1804                 return;
1805
1806         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1807         intel_flush_display_plane(dev_priv, plane);
1808         intel_wait_for_vblank(dev_priv->dev, pipe);
1809 }
1810
1811 static bool need_vtd_wa(struct drm_device *dev)
1812 {
1813 #ifdef CONFIG_INTEL_IOMMU
1814         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1815                 return true;
1816 #endif
1817         return false;
1818 }
1819
1820 int
1821 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1822                            struct drm_i915_gem_object *obj,
1823                            struct intel_ring_buffer *pipelined)
1824 {
1825         struct drm_i915_private *dev_priv = dev->dev_private;
1826         u32 alignment;
1827         int ret;
1828
1829         switch (obj->tiling_mode) {
1830         case I915_TILING_NONE:
1831                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1832                         alignment = 128 * 1024;
1833                 else if (INTEL_INFO(dev)->gen >= 4)
1834                         alignment = 4 * 1024;
1835                 else
1836                         alignment = 64 * 1024;
1837                 break;
1838         case I915_TILING_X:
1839                 /* pin() will align the object as required by fence */
1840                 alignment = 0;
1841                 break;
1842         case I915_TILING_Y:
1843                 /* Despite that we check this in framebuffer_init userspace can
1844                  * screw us over and change the tiling after the fact. Only
1845                  * pinned buffers can't change their tiling. */
1846                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1847                 return -EINVAL;
1848         default:
1849                 BUG();
1850         }
1851
1852         /* Note that the w/a also requires 64 PTE of padding following the
1853          * bo. We currently fill all unused PTE with the shadow page and so
1854          * we should always have valid PTE following the scanout preventing
1855          * the VT-d warning.
1856          */
1857         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1858                 alignment = 256 * 1024;
1859
1860         dev_priv->mm.interruptible = false;
1861         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1862         if (ret)
1863                 goto err_interruptible;
1864
1865         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1866          * fence, whereas 965+ only requires a fence if using
1867          * framebuffer compression.  For simplicity, we always install
1868          * a fence as the cost is not that onerous.
1869          */
1870         ret = i915_gem_object_get_fence(obj);
1871         if (ret)
1872                 goto err_unpin;
1873
1874         i915_gem_object_pin_fence(obj);
1875
1876         dev_priv->mm.interruptible = true;
1877         return 0;
1878
1879 err_unpin:
1880         i915_gem_object_unpin(obj);
1881 err_interruptible:
1882         dev_priv->mm.interruptible = true;
1883         return ret;
1884 }
1885
1886 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1887 {
1888         i915_gem_object_unpin_fence(obj);
1889         i915_gem_object_unpin(obj);
1890 }
1891
1892 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1893  * is assumed to be a power-of-two. */
1894 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1895                                              unsigned int tiling_mode,
1896                                              unsigned int cpp,
1897                                              unsigned int pitch)
1898 {
1899         if (tiling_mode != I915_TILING_NONE) {
1900                 unsigned int tile_rows, tiles;
1901
1902                 tile_rows = *y / 8;
1903                 *y %= 8;
1904
1905                 tiles = *x / (512/cpp);
1906                 *x %= 512/cpp;
1907
1908                 return tile_rows * pitch * 8 + tiles * 4096;
1909         } else {
1910                 unsigned int offset;
1911
1912                 offset = *y * pitch + *x * cpp;
1913                 *y = 0;
1914                 *x = (offset & 4095) / cpp;
1915                 return offset & -4096;
1916         }
1917 }
1918
1919 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1920                              int x, int y)
1921 {
1922         struct drm_device *dev = crtc->dev;
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1925         struct intel_framebuffer *intel_fb;
1926         struct drm_i915_gem_object *obj;
1927         int plane = intel_crtc->plane;
1928         unsigned long linear_offset;
1929         u32 dspcntr;
1930         u32 reg;
1931
1932         switch (plane) {
1933         case 0:
1934         case 1:
1935                 break;
1936         default:
1937                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1938                 return -EINVAL;
1939         }
1940
1941         intel_fb = to_intel_framebuffer(fb);
1942         obj = intel_fb->obj;
1943
1944         reg = DSPCNTR(plane);
1945         dspcntr = I915_READ(reg);
1946         /* Mask out pixel format bits in case we change it */
1947         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948         switch (fb->pixel_format) {
1949         case DRM_FORMAT_C8:
1950                 dspcntr |= DISPPLANE_8BPP;
1951                 break;
1952         case DRM_FORMAT_XRGB1555:
1953         case DRM_FORMAT_ARGB1555:
1954                 dspcntr |= DISPPLANE_BGRX555;
1955                 break;
1956         case DRM_FORMAT_RGB565:
1957                 dspcntr |= DISPPLANE_BGRX565;
1958                 break;
1959         case DRM_FORMAT_XRGB8888:
1960         case DRM_FORMAT_ARGB8888:
1961                 dspcntr |= DISPPLANE_BGRX888;
1962                 break;
1963         case DRM_FORMAT_XBGR8888:
1964         case DRM_FORMAT_ABGR8888:
1965                 dspcntr |= DISPPLANE_RGBX888;
1966                 break;
1967         case DRM_FORMAT_XRGB2101010:
1968         case DRM_FORMAT_ARGB2101010:
1969                 dspcntr |= DISPPLANE_BGRX101010;
1970                 break;
1971         case DRM_FORMAT_XBGR2101010:
1972         case DRM_FORMAT_ABGR2101010:
1973                 dspcntr |= DISPPLANE_RGBX101010;
1974                 break;
1975         default:
1976                 BUG();
1977         }
1978
1979         if (INTEL_INFO(dev)->gen >= 4) {
1980                 if (obj->tiling_mode != I915_TILING_NONE)
1981                         dspcntr |= DISPPLANE_TILED;
1982                 else
1983                         dspcntr &= ~DISPPLANE_TILED;
1984         }
1985
1986         if (IS_G4X(dev))
1987                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1988
1989         I915_WRITE(reg, dspcntr);
1990
1991         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1992
1993         if (INTEL_INFO(dev)->gen >= 4) {
1994                 intel_crtc->dspaddr_offset =
1995                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1996                                                        fb->bits_per_pixel / 8,
1997                                                        fb->pitches[0]);
1998                 linear_offset -= intel_crtc->dspaddr_offset;
1999         } else {
2000                 intel_crtc->dspaddr_offset = linear_offset;
2001         }
2002
2003         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2004                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2005                       fb->pitches[0]);
2006         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2007         if (INTEL_INFO(dev)->gen >= 4) {
2008                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2009                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2010                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2011                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2012         } else
2013                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2014         POSTING_READ(reg);
2015
2016         return 0;
2017 }
2018
2019 static int ironlake_update_plane(struct drm_crtc *crtc,
2020                                  struct drm_framebuffer *fb, int x, int y)
2021 {
2022         struct drm_device *dev = crtc->dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025         struct intel_framebuffer *intel_fb;
2026         struct drm_i915_gem_object *obj;
2027         int plane = intel_crtc->plane;
2028         unsigned long linear_offset;
2029         u32 dspcntr;
2030         u32 reg;
2031
2032         switch (plane) {
2033         case 0:
2034         case 1:
2035         case 2:
2036                 break;
2037         default:
2038                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2039                 return -EINVAL;
2040         }
2041
2042         intel_fb = to_intel_framebuffer(fb);
2043         obj = intel_fb->obj;
2044
2045         reg = DSPCNTR(plane);
2046         dspcntr = I915_READ(reg);
2047         /* Mask out pixel format bits in case we change it */
2048         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2049         switch (fb->pixel_format) {
2050         case DRM_FORMAT_C8:
2051                 dspcntr |= DISPPLANE_8BPP;
2052                 break;
2053         case DRM_FORMAT_RGB565:
2054                 dspcntr |= DISPPLANE_BGRX565;
2055                 break;
2056         case DRM_FORMAT_XRGB8888:
2057         case DRM_FORMAT_ARGB8888:
2058                 dspcntr |= DISPPLANE_BGRX888;
2059                 break;
2060         case DRM_FORMAT_XBGR8888:
2061         case DRM_FORMAT_ABGR8888:
2062                 dspcntr |= DISPPLANE_RGBX888;
2063                 break;
2064         case DRM_FORMAT_XRGB2101010:
2065         case DRM_FORMAT_ARGB2101010:
2066                 dspcntr |= DISPPLANE_BGRX101010;
2067                 break;
2068         case DRM_FORMAT_XBGR2101010:
2069         case DRM_FORMAT_ABGR2101010:
2070                 dspcntr |= DISPPLANE_RGBX101010;
2071                 break;
2072         default:
2073                 BUG();
2074         }
2075
2076         if (obj->tiling_mode != I915_TILING_NONE)
2077                 dspcntr |= DISPPLANE_TILED;
2078         else
2079                 dspcntr &= ~DISPPLANE_TILED;
2080
2081         /* must disable */
2082         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2083
2084         I915_WRITE(reg, dspcntr);
2085
2086         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2087         intel_crtc->dspaddr_offset =
2088                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2089                                                fb->bits_per_pixel / 8,
2090                                                fb->pitches[0]);
2091         linear_offset -= intel_crtc->dspaddr_offset;
2092
2093         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2094                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2095                       fb->pitches[0]);
2096         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2097         I915_MODIFY_DISPBASE(DSPSURF(plane),
2098                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2099         if (IS_HASWELL(dev)) {
2100                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2101         } else {
2102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         }
2105         POSTING_READ(reg);
2106
2107         return 0;
2108 }
2109
2110 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 static int
2112 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2113                            int x, int y, enum mode_set_atomic state)
2114 {
2115         struct drm_device *dev = crtc->dev;
2116         struct drm_i915_private *dev_priv = dev->dev_private;
2117
2118         if (dev_priv->display.disable_fbc)
2119                 dev_priv->display.disable_fbc(dev);
2120         intel_increase_pllclock(crtc);
2121
2122         return dev_priv->display.update_plane(crtc, fb, x, y);
2123 }
2124
2125 void intel_display_handle_reset(struct drm_device *dev)
2126 {
2127         struct drm_i915_private *dev_priv = dev->dev_private;
2128         struct drm_crtc *crtc;
2129
2130         /*
2131          * Flips in the rings have been nuked by the reset,
2132          * so complete all pending flips so that user space
2133          * will get its events and not get stuck.
2134          *
2135          * Also update the base address of all primary
2136          * planes to the the last fb to make sure we're
2137          * showing the correct fb after a reset.
2138          *
2139          * Need to make two loops over the crtcs so that we
2140          * don't try to grab a crtc mutex before the
2141          * pending_flip_queue really got woken up.
2142          */
2143
2144         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2145                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146                 enum plane plane = intel_crtc->plane;
2147
2148                 intel_prepare_page_flip(dev, plane);
2149                 intel_finish_page_flip_plane(dev, plane);
2150         }
2151
2152         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2153                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154
2155                 mutex_lock(&crtc->mutex);
2156                 if (intel_crtc->active)
2157                         dev_priv->display.update_plane(crtc, crtc->fb,
2158                                                        crtc->x, crtc->y);
2159                 mutex_unlock(&crtc->mutex);
2160         }
2161 }
2162
2163 static int
2164 intel_finish_fb(struct drm_framebuffer *old_fb)
2165 {
2166         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2167         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2168         bool was_interruptible = dev_priv->mm.interruptible;
2169         int ret;
2170
2171         /* Big Hammer, we also need to ensure that any pending
2172          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2173          * current scanout is retired before unpinning the old
2174          * framebuffer.
2175          *
2176          * This should only fail upon a hung GPU, in which case we
2177          * can safely continue.
2178          */
2179         dev_priv->mm.interruptible = false;
2180         ret = i915_gem_object_finish_gpu(obj);
2181         dev_priv->mm.interruptible = was_interruptible;
2182
2183         return ret;
2184 }
2185
2186 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2187 {
2188         struct drm_device *dev = crtc->dev;
2189         struct drm_i915_master_private *master_priv;
2190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2191
2192         if (!dev->primary->master)
2193                 return;
2194
2195         master_priv = dev->primary->master->driver_priv;
2196         if (!master_priv->sarea_priv)
2197                 return;
2198
2199         switch (intel_crtc->pipe) {
2200         case 0:
2201                 master_priv->sarea_priv->pipeA_x = x;
2202                 master_priv->sarea_priv->pipeA_y = y;
2203                 break;
2204         case 1:
2205                 master_priv->sarea_priv->pipeB_x = x;
2206                 master_priv->sarea_priv->pipeB_y = y;
2207                 break;
2208         default:
2209                 break;
2210         }
2211 }
2212
2213 static int
2214 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2215                     struct drm_framebuffer *fb)
2216 {
2217         struct drm_device *dev = crtc->dev;
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2220         struct drm_framebuffer *old_fb;
2221         int ret;
2222
2223         /* no fb bound */
2224         if (!fb) {
2225                 DRM_ERROR("No FB bound\n");
2226                 return 0;
2227         }
2228
2229         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2230                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2231                           plane_name(intel_crtc->plane),
2232                           INTEL_INFO(dev)->num_pipes);
2233                 return -EINVAL;
2234         }
2235
2236         mutex_lock(&dev->struct_mutex);
2237         ret = intel_pin_and_fence_fb_obj(dev,
2238                                          to_intel_framebuffer(fb)->obj,
2239                                          NULL);
2240         if (ret != 0) {
2241                 mutex_unlock(&dev->struct_mutex);
2242                 DRM_ERROR("pin & fence failed\n");
2243                 return ret;
2244         }
2245
2246         /* Update pipe size and adjust fitter if needed */
2247         if (i915_fastboot) {
2248                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2249                            ((crtc->mode.hdisplay - 1) << 16) |
2250                            (crtc->mode.vdisplay - 1));
2251                 if (!intel_crtc->config.pch_pfit.size &&
2252                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2253                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2254                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2255                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2256                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2257                 }
2258         }
2259
2260         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2261         if (ret) {
2262                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2263                 mutex_unlock(&dev->struct_mutex);
2264                 DRM_ERROR("failed to update base address\n");
2265                 return ret;
2266         }
2267
2268         old_fb = crtc->fb;
2269         crtc->fb = fb;
2270         crtc->x = x;
2271         crtc->y = y;
2272
2273         if (old_fb) {
2274                 if (intel_crtc->active && old_fb != fb)
2275                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2276                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2277         }
2278
2279         intel_update_fbc(dev);
2280         intel_edp_psr_update(dev);
2281         mutex_unlock(&dev->struct_mutex);
2282
2283         intel_crtc_update_sarea_pos(crtc, x, y);
2284
2285         return 0;
2286 }
2287
2288 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2289 {
2290         struct drm_device *dev = crtc->dev;
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2293         int pipe = intel_crtc->pipe;
2294         u32 reg, temp;
2295
2296         /* enable normal train */
2297         reg = FDI_TX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         if (IS_IVYBRIDGE(dev)) {
2300                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2301                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2302         } else {
2303                 temp &= ~FDI_LINK_TRAIN_NONE;
2304                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2305         }
2306         I915_WRITE(reg, temp);
2307
2308         reg = FDI_RX_CTL(pipe);
2309         temp = I915_READ(reg);
2310         if (HAS_PCH_CPT(dev)) {
2311                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2312                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2313         } else {
2314                 temp &= ~FDI_LINK_TRAIN_NONE;
2315                 temp |= FDI_LINK_TRAIN_NONE;
2316         }
2317         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2318
2319         /* wait one idle pattern time */
2320         POSTING_READ(reg);
2321         udelay(1000);
2322
2323         /* IVB wants error correction enabled */
2324         if (IS_IVYBRIDGE(dev))
2325                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2326                            FDI_FE_ERRC_ENABLE);
2327 }
2328
2329 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2330 {
2331         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2332 }
2333
2334 static void ivb_modeset_global_resources(struct drm_device *dev)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct intel_crtc *pipe_B_crtc =
2338                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2339         struct intel_crtc *pipe_C_crtc =
2340                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2341         uint32_t temp;
2342
2343         /*
2344          * When everything is off disable fdi C so that we could enable fdi B
2345          * with all lanes. Note that we don't care about enabled pipes without
2346          * an enabled pch encoder.
2347          */
2348         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2349             !pipe_has_enabled_pch(pipe_C_crtc)) {
2350                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2351                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2352
2353                 temp = I915_READ(SOUTH_CHICKEN1);
2354                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2355                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2356                 I915_WRITE(SOUTH_CHICKEN1, temp);
2357         }
2358 }
2359
2360 /* The FDI link training functions for ILK/Ibexpeak. */
2361 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366         int pipe = intel_crtc->pipe;
2367         int plane = intel_crtc->plane;
2368         u32 reg, temp, tries;
2369
2370         /* FDI needs bits from pipe & plane first */
2371         assert_pipe_enabled(dev_priv, pipe);
2372         assert_plane_enabled(dev_priv, plane);
2373
2374         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375            for train result */
2376         reg = FDI_RX_IMR(pipe);
2377         temp = I915_READ(reg);
2378         temp &= ~FDI_RX_SYMBOL_LOCK;
2379         temp &= ~FDI_RX_BIT_LOCK;
2380         I915_WRITE(reg, temp);
2381         I915_READ(reg);
2382         udelay(150);
2383
2384         /* enable CPU FDI TX and PCH FDI RX */
2385         reg = FDI_TX_CTL(pipe);
2386         temp = I915_READ(reg);
2387         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2388         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_1;
2391         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2392
2393         reg = FDI_RX_CTL(pipe);
2394         temp = I915_READ(reg);
2395         temp &= ~FDI_LINK_TRAIN_NONE;
2396         temp |= FDI_LINK_TRAIN_PATTERN_1;
2397         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399         POSTING_READ(reg);
2400         udelay(150);
2401
2402         /* Ironlake workaround, enable clock pointer after FDI enable*/
2403         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2404         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2405                    FDI_RX_PHASE_SYNC_POINTER_EN);
2406
2407         reg = FDI_RX_IIR(pipe);
2408         for (tries = 0; tries < 5; tries++) {
2409                 temp = I915_READ(reg);
2410                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2411
2412                 if ((temp & FDI_RX_BIT_LOCK)) {
2413                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2414                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2415                         break;
2416                 }
2417         }
2418         if (tries == 5)
2419                 DRM_ERROR("FDI train 1 fail!\n");
2420
2421         /* Train 2 */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_LINK_TRAIN_NONE;
2425         temp |= FDI_LINK_TRAIN_PATTERN_2;
2426         I915_WRITE(reg, temp);
2427
2428         reg = FDI_RX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_LINK_TRAIN_NONE;
2431         temp |= FDI_LINK_TRAIN_PATTERN_2;
2432         I915_WRITE(reg, temp);
2433
2434         POSTING_READ(reg);
2435         udelay(150);
2436
2437         reg = FDI_RX_IIR(pipe);
2438         for (tries = 0; tries < 5; tries++) {
2439                 temp = I915_READ(reg);
2440                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2441
2442                 if (temp & FDI_RX_SYMBOL_LOCK) {
2443                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2444                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2445                         break;
2446                 }
2447         }
2448         if (tries == 5)
2449                 DRM_ERROR("FDI train 2 fail!\n");
2450
2451         DRM_DEBUG_KMS("FDI train done\n");
2452
2453 }
2454
2455 static const int snb_b_fdi_train_param[] = {
2456         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2457         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2458         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2459         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2460 };
2461
2462 /* The FDI link training functions for SNB/Cougarpoint. */
2463 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468         int pipe = intel_crtc->pipe;
2469         u32 reg, temp, i, retry;
2470
2471         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472            for train result */
2473         reg = FDI_RX_IMR(pipe);
2474         temp = I915_READ(reg);
2475         temp &= ~FDI_RX_SYMBOL_LOCK;
2476         temp &= ~FDI_RX_BIT_LOCK;
2477         I915_WRITE(reg, temp);
2478
2479         POSTING_READ(reg);
2480         udelay(150);
2481
2482         /* enable CPU FDI TX and PCH FDI RX */
2483         reg = FDI_TX_CTL(pipe);
2484         temp = I915_READ(reg);
2485         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2486         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2487         temp &= ~FDI_LINK_TRAIN_NONE;
2488         temp |= FDI_LINK_TRAIN_PATTERN_1;
2489         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2490         /* SNB-B */
2491         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2492         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2493
2494         I915_WRITE(FDI_RX_MISC(pipe),
2495                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2496
2497         reg = FDI_RX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         if (HAS_PCH_CPT(dev)) {
2500                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2501                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502         } else {
2503                 temp &= ~FDI_LINK_TRAIN_NONE;
2504                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505         }
2506         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507
2508         POSTING_READ(reg);
2509         udelay(150);
2510
2511         for (i = 0; i < 4; i++) {
2512                 reg = FDI_TX_CTL(pipe);
2513                 temp = I915_READ(reg);
2514                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2515                 temp |= snb_b_fdi_train_param[i];
2516                 I915_WRITE(reg, temp);
2517
2518                 POSTING_READ(reg);
2519                 udelay(500);
2520
2521                 for (retry = 0; retry < 5; retry++) {
2522                         reg = FDI_RX_IIR(pipe);
2523                         temp = I915_READ(reg);
2524                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525                         if (temp & FDI_RX_BIT_LOCK) {
2526                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2527                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2528                                 break;
2529                         }
2530                         udelay(50);
2531                 }
2532                 if (retry < 5)
2533                         break;
2534         }
2535         if (i == 4)
2536                 DRM_ERROR("FDI train 1 fail!\n");
2537
2538         /* Train 2 */
2539         reg = FDI_TX_CTL(pipe);
2540         temp = I915_READ(reg);
2541         temp &= ~FDI_LINK_TRAIN_NONE;
2542         temp |= FDI_LINK_TRAIN_PATTERN_2;
2543         if (IS_GEN6(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545                 /* SNB-B */
2546                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547         }
2548         I915_WRITE(reg, temp);
2549
2550         reg = FDI_RX_CTL(pipe);
2551         temp = I915_READ(reg);
2552         if (HAS_PCH_CPT(dev)) {
2553                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2554                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2555         } else {
2556                 temp &= ~FDI_LINK_TRAIN_NONE;
2557                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2558         }
2559         I915_WRITE(reg, temp);
2560
2561         POSTING_READ(reg);
2562         udelay(150);
2563
2564         for (i = 0; i < 4; i++) {
2565                 reg = FDI_TX_CTL(pipe);
2566                 temp = I915_READ(reg);
2567                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568                 temp |= snb_b_fdi_train_param[i];
2569                 I915_WRITE(reg, temp);
2570
2571                 POSTING_READ(reg);
2572                 udelay(500);
2573
2574                 for (retry = 0; retry < 5; retry++) {
2575                         reg = FDI_RX_IIR(pipe);
2576                         temp = I915_READ(reg);
2577                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2578                         if (temp & FDI_RX_SYMBOL_LOCK) {
2579                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2580                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2581                                 break;
2582                         }
2583                         udelay(50);
2584                 }
2585                 if (retry < 5)
2586                         break;
2587         }
2588         if (i == 4)
2589                 DRM_ERROR("FDI train 2 fail!\n");
2590
2591         DRM_DEBUG_KMS("FDI train done.\n");
2592 }
2593
2594 /* Manual link training for Ivy Bridge A0 parts */
2595 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2596 {
2597         struct drm_device *dev = crtc->dev;
2598         struct drm_i915_private *dev_priv = dev->dev_private;
2599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2600         int pipe = intel_crtc->pipe;
2601         u32 reg, temp, i;
2602
2603         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2604            for train result */
2605         reg = FDI_RX_IMR(pipe);
2606         temp = I915_READ(reg);
2607         temp &= ~FDI_RX_SYMBOL_LOCK;
2608         temp &= ~FDI_RX_BIT_LOCK;
2609         I915_WRITE(reg, temp);
2610
2611         POSTING_READ(reg);
2612         udelay(150);
2613
2614         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2615                       I915_READ(FDI_RX_IIR(pipe)));
2616
2617         /* enable CPU FDI TX and PCH FDI RX */
2618         reg = FDI_TX_CTL(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2621         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2622         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2623         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2624         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2626         temp |= FDI_COMPOSITE_SYNC;
2627         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2628
2629         I915_WRITE(FDI_RX_MISC(pipe),
2630                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2631
2632         reg = FDI_RX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_AUTO;
2635         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2636         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2637         temp |= FDI_COMPOSITE_SYNC;
2638         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2639
2640         POSTING_READ(reg);
2641         udelay(150);
2642
2643         for (i = 0; i < 4; i++) {
2644                 reg = FDI_TX_CTL(pipe);
2645                 temp = I915_READ(reg);
2646                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647                 temp |= snb_b_fdi_train_param[i];
2648                 I915_WRITE(reg, temp);
2649
2650                 POSTING_READ(reg);
2651                 udelay(500);
2652
2653                 reg = FDI_RX_IIR(pipe);
2654                 temp = I915_READ(reg);
2655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657                 if (temp & FDI_RX_BIT_LOCK ||
2658                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2659                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2661                         break;
2662                 }
2663         }
2664         if (i == 4)
2665                 DRM_ERROR("FDI train 1 fail!\n");
2666
2667         /* Train 2 */
2668         reg = FDI_TX_CTL(pipe);
2669         temp = I915_READ(reg);
2670         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2671         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2672         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674         I915_WRITE(reg, temp);
2675
2676         reg = FDI_RX_CTL(pipe);
2677         temp = I915_READ(reg);
2678         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2680         I915_WRITE(reg, temp);
2681
2682         POSTING_READ(reg);
2683         udelay(150);
2684
2685         for (i = 0; i < 4; i++) {
2686                 reg = FDI_TX_CTL(pipe);
2687                 temp = I915_READ(reg);
2688                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2689                 temp |= snb_b_fdi_train_param[i];
2690                 I915_WRITE(reg, temp);
2691
2692                 POSTING_READ(reg);
2693                 udelay(500);
2694
2695                 reg = FDI_RX_IIR(pipe);
2696                 temp = I915_READ(reg);
2697                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698
2699                 if (temp & FDI_RX_SYMBOL_LOCK) {
2700                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2701                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2702                         break;
2703                 }
2704         }
2705         if (i == 4)
2706                 DRM_ERROR("FDI train 2 fail!\n");
2707
2708         DRM_DEBUG_KMS("FDI train done.\n");
2709 }
2710
2711 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718
2719         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2720         reg = FDI_RX_CTL(pipe);
2721         temp = I915_READ(reg);
2722         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2723         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2724         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2725         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2726
2727         POSTING_READ(reg);
2728         udelay(200);
2729
2730         /* Switch from Rawclk to PCDclk */
2731         temp = I915_READ(reg);
2732         I915_WRITE(reg, temp | FDI_PCDCLK);
2733
2734         POSTING_READ(reg);
2735         udelay(200);
2736
2737         /* Enable CPU FDI TX PLL, always on for Ironlake */
2738         reg = FDI_TX_CTL(pipe);
2739         temp = I915_READ(reg);
2740         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2741                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2742
2743                 POSTING_READ(reg);
2744                 udelay(100);
2745         }
2746 }
2747
2748 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2749 {
2750         struct drm_device *dev = intel_crtc->base.dev;
2751         struct drm_i915_private *dev_priv = dev->dev_private;
2752         int pipe = intel_crtc->pipe;
2753         u32 reg, temp;
2754
2755         /* Switch from PCDclk to Rawclk */
2756         reg = FDI_RX_CTL(pipe);
2757         temp = I915_READ(reg);
2758         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2759
2760         /* Disable CPU FDI TX PLL */
2761         reg = FDI_TX_CTL(pipe);
2762         temp = I915_READ(reg);
2763         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2764
2765         POSTING_READ(reg);
2766         udelay(100);
2767
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2771
2772         /* Wait for the clocks to turn off. */
2773         POSTING_READ(reg);
2774         udelay(100);
2775 }
2776
2777 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         int pipe = intel_crtc->pipe;
2783         u32 reg, temp;
2784
2785         /* disable CPU FDI tx and PCH FDI rx */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2789         POSTING_READ(reg);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         temp &= ~(0x7 << 16);
2794         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2795         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2796
2797         POSTING_READ(reg);
2798         udelay(100);
2799
2800         /* Ironlake workaround, disable clock pointer after downing FDI */
2801         if (HAS_PCH_IBX(dev)) {
2802                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2803         }
2804
2805         /* still set train pattern 1 */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_LINK_TRAIN_NONE;
2809         temp |= FDI_LINK_TRAIN_PATTERN_1;
2810         I915_WRITE(reg, temp);
2811
2812         reg = FDI_RX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         if (HAS_PCH_CPT(dev)) {
2815                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2816                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2817         } else {
2818                 temp &= ~FDI_LINK_TRAIN_NONE;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2820         }
2821         /* BPC in FDI rx is consistent with that in PIPECONF */
2822         temp &= ~(0x07 << 16);
2823         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2824         I915_WRITE(reg, temp);
2825
2826         POSTING_READ(reg);
2827         udelay(100);
2828 }
2829
2830 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2831 {
2832         struct drm_device *dev = crtc->dev;
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2835         unsigned long flags;
2836         bool pending;
2837
2838         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2839             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2840                 return false;
2841
2842         spin_lock_irqsave(&dev->event_lock, flags);
2843         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2844         spin_unlock_irqrestore(&dev->event_lock, flags);
2845
2846         return pending;
2847 }
2848
2849 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2850 {
2851         struct drm_device *dev = crtc->dev;
2852         struct drm_i915_private *dev_priv = dev->dev_private;
2853
2854         if (crtc->fb == NULL)
2855                 return;
2856
2857         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2858
2859         wait_event(dev_priv->pending_flip_queue,
2860                    !intel_crtc_has_pending_flip(crtc));
2861
2862         mutex_lock(&dev->struct_mutex);
2863         intel_finish_fb(crtc->fb);
2864         mutex_unlock(&dev->struct_mutex);
2865 }
2866
2867 /* Program iCLKIP clock to the desired frequency */
2868 static void lpt_program_iclkip(struct drm_crtc *crtc)
2869 {
2870         struct drm_device *dev = crtc->dev;
2871         struct drm_i915_private *dev_priv = dev->dev_private;
2872         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2873         u32 temp;
2874
2875         mutex_lock(&dev_priv->dpio_lock);
2876
2877         /* It is necessary to ungate the pixclk gate prior to programming
2878          * the divisors, and gate it back when it is done.
2879          */
2880         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2881
2882         /* Disable SSCCTL */
2883         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2884                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2885                                 SBI_SSCCTL_DISABLE,
2886                         SBI_ICLK);
2887
2888         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2889         if (crtc->mode.clock == 20000) {
2890                 auxdiv = 1;
2891                 divsel = 0x41;
2892                 phaseinc = 0x20;
2893         } else {
2894                 /* The iCLK virtual clock root frequency is in MHz,
2895                  * but the crtc->mode.clock in in KHz. To get the divisors,
2896                  * it is necessary to divide one by another, so we
2897                  * convert the virtual clock precision to KHz here for higher
2898                  * precision.
2899                  */
2900                 u32 iclk_virtual_root_freq = 172800 * 1000;
2901                 u32 iclk_pi_range = 64;
2902                 u32 desired_divisor, msb_divisor_value, pi_value;
2903
2904                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2905                 msb_divisor_value = desired_divisor / iclk_pi_range;
2906                 pi_value = desired_divisor % iclk_pi_range;
2907
2908                 auxdiv = 0;
2909                 divsel = msb_divisor_value - 2;
2910                 phaseinc = pi_value;
2911         }
2912
2913         /* This should not happen with any sane values */
2914         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2915                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2916         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2917                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2918
2919         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2920                         crtc->mode.clock,
2921                         auxdiv,
2922                         divsel,
2923                         phasedir,
2924                         phaseinc);
2925
2926         /* Program SSCDIVINTPHASE6 */
2927         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2928         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2929         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2930         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2931         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2932         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2933         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2934         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2935
2936         /* Program SSCAUXDIV */
2937         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2938         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2939         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2940         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2941
2942         /* Enable modulator and associated divider */
2943         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2944         temp &= ~SBI_SSCCTL_DISABLE;
2945         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2946
2947         /* Wait for initialization time */
2948         udelay(24);
2949
2950         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2951
2952         mutex_unlock(&dev_priv->dpio_lock);
2953 }
2954
2955 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2956                                                 enum pipe pch_transcoder)
2957 {
2958         struct drm_device *dev = crtc->base.dev;
2959         struct drm_i915_private *dev_priv = dev->dev_private;
2960         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2961
2962         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2963                    I915_READ(HTOTAL(cpu_transcoder)));
2964         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2965                    I915_READ(HBLANK(cpu_transcoder)));
2966         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2967                    I915_READ(HSYNC(cpu_transcoder)));
2968
2969         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2970                    I915_READ(VTOTAL(cpu_transcoder)));
2971         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2972                    I915_READ(VBLANK(cpu_transcoder)));
2973         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2974                    I915_READ(VSYNC(cpu_transcoder)));
2975         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2976                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2977 }
2978
2979 /*
2980  * Enable PCH resources required for PCH ports:
2981  *   - PCH PLLs
2982  *   - FDI training & RX/TX
2983  *   - update transcoder timings
2984  *   - DP transcoding bits
2985  *   - transcoder
2986  */
2987 static void ironlake_pch_enable(struct drm_crtc *crtc)
2988 {
2989         struct drm_device *dev = crtc->dev;
2990         struct drm_i915_private *dev_priv = dev->dev_private;
2991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2992         int pipe = intel_crtc->pipe;
2993         u32 reg, temp;
2994
2995         assert_pch_transcoder_disabled(dev_priv, pipe);
2996
2997         /* Write the TU size bits before fdi link training, so that error
2998          * detection works. */
2999         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3000                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3001
3002         /* For PCH output, training FDI link */
3003         dev_priv->display.fdi_link_train(crtc);
3004
3005         /* We need to program the right clock selection before writing the pixel
3006          * mutliplier into the DPLL. */
3007         if (HAS_PCH_CPT(dev)) {
3008                 u32 sel;
3009
3010                 temp = I915_READ(PCH_DPLL_SEL);
3011                 temp |= TRANS_DPLL_ENABLE(pipe);
3012                 sel = TRANS_DPLLB_SEL(pipe);
3013                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3014                         temp |= sel;
3015                 else
3016                         temp &= ~sel;
3017                 I915_WRITE(PCH_DPLL_SEL, temp);
3018         }
3019
3020         /* XXX: pch pll's can be enabled any time before we enable the PCH
3021          * transcoder, and we actually should do this to not upset any PCH
3022          * transcoder that already use the clock when we share it.
3023          *
3024          * Note that enable_shared_dpll tries to do the right thing, but
3025          * get_shared_dpll unconditionally resets the pll - we need that to have
3026          * the right LVDS enable sequence. */
3027         ironlake_enable_shared_dpll(intel_crtc);
3028
3029         /* set transcoder timing, panel must allow it */
3030         assert_panel_unlocked(dev_priv, pipe);
3031         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3032
3033         intel_fdi_normal_train(crtc);
3034
3035         /* For PCH DP, enable TRANS_DP_CTL */
3036         if (HAS_PCH_CPT(dev) &&
3037             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3038              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3039                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3040                 reg = TRANS_DP_CTL(pipe);
3041                 temp = I915_READ(reg);
3042                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3043                           TRANS_DP_SYNC_MASK |
3044                           TRANS_DP_BPC_MASK);
3045                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3046                          TRANS_DP_ENH_FRAMING);
3047                 temp |= bpc << 9; /* same format but at 11:9 */
3048
3049                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3050                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3051                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3052                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3053
3054                 switch (intel_trans_dp_port_sel(crtc)) {
3055                 case PCH_DP_B:
3056                         temp |= TRANS_DP_PORT_SEL_B;
3057                         break;
3058                 case PCH_DP_C:
3059                         temp |= TRANS_DP_PORT_SEL_C;
3060                         break;
3061                 case PCH_DP_D:
3062                         temp |= TRANS_DP_PORT_SEL_D;
3063                         break;
3064                 default:
3065                         BUG();
3066                 }
3067
3068                 I915_WRITE(reg, temp);
3069         }
3070
3071         ironlake_enable_pch_transcoder(dev_priv, pipe);
3072 }
3073
3074 static void lpt_pch_enable(struct drm_crtc *crtc)
3075 {
3076         struct drm_device *dev = crtc->dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3080
3081         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3082
3083         lpt_program_iclkip(crtc);
3084
3085         /* Set transcoder timing. */
3086         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3087
3088         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3089 }
3090
3091 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3092 {
3093         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3094
3095         if (pll == NULL)
3096                 return;
3097
3098         if (pll->refcount == 0) {
3099                 WARN(1, "bad %s refcount\n", pll->name);
3100                 return;
3101         }
3102
3103         if (--pll->refcount == 0) {
3104                 WARN_ON(pll->on);
3105                 WARN_ON(pll->active);
3106         }
3107
3108         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3109 }
3110
3111 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3112 {
3113         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3114         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3115         enum intel_dpll_id i;
3116
3117         if (pll) {
3118                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3119                               crtc->base.base.id, pll->name);
3120                 intel_put_shared_dpll(crtc);
3121         }
3122
3123         if (HAS_PCH_IBX(dev_priv->dev)) {
3124                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3125                 i = (enum intel_dpll_id) crtc->pipe;
3126                 pll = &dev_priv->shared_dplls[i];
3127
3128                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3129                               crtc->base.base.id, pll->name);
3130
3131                 goto found;
3132         }
3133
3134         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3135                 pll = &dev_priv->shared_dplls[i];
3136
3137                 /* Only want to check enabled timings first */
3138                 if (pll->refcount == 0)
3139                         continue;
3140
3141                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3142                            sizeof(pll->hw_state)) == 0) {
3143                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3144                                       crtc->base.base.id,
3145                                       pll->name, pll->refcount, pll->active);
3146
3147                         goto found;
3148                 }
3149         }
3150
3151         /* Ok no matching timings, maybe there's a free one? */
3152         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3153                 pll = &dev_priv->shared_dplls[i];
3154                 if (pll->refcount == 0) {
3155                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3156                                       crtc->base.base.id, pll->name);
3157                         goto found;
3158                 }
3159         }
3160
3161         return NULL;
3162
3163 found:
3164         crtc->config.shared_dpll = i;
3165         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3166                          pipe_name(crtc->pipe));
3167
3168         if (pll->active == 0) {
3169                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3170                        sizeof(pll->hw_state));
3171
3172                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3173                 WARN_ON(pll->on);
3174                 assert_shared_dpll_disabled(dev_priv, pll);
3175
3176                 pll->mode_set(dev_priv, pll);
3177         }
3178         pll->refcount++;
3179
3180         return pll;
3181 }
3182
3183 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3184 {
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         int dslreg = PIPEDSL(pipe);
3187         u32 temp;
3188
3189         temp = I915_READ(dslreg);
3190         udelay(500);
3191         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3192                 if (wait_for(I915_READ(dslreg) != temp, 5))
3193                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3194         }
3195 }
3196
3197 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3198 {
3199         struct drm_device *dev = crtc->base.dev;
3200         struct drm_i915_private *dev_priv = dev->dev_private;
3201         int pipe = crtc->pipe;
3202
3203         if (crtc->config.pch_pfit.size) {
3204                 /* Force use of hard-coded filter coefficients
3205                  * as some pre-programmed values are broken,
3206                  * e.g. x201.
3207                  */
3208                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3209                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3210                                                  PF_PIPE_SEL_IVB(pipe));
3211                 else
3212                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3213                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3214                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3215         }
3216 }
3217
3218 static void intel_enable_planes(struct drm_crtc *crtc)
3219 {
3220         struct drm_device *dev = crtc->dev;
3221         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3222         struct intel_plane *intel_plane;
3223
3224         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3225                 if (intel_plane->pipe == pipe)
3226                         intel_plane_restore(&intel_plane->base);
3227 }
3228
3229 static void intel_disable_planes(struct drm_crtc *crtc)
3230 {
3231         struct drm_device *dev = crtc->dev;
3232         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3233         struct intel_plane *intel_plane;
3234
3235         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3236                 if (intel_plane->pipe == pipe)
3237                         intel_plane_disable(&intel_plane->base);
3238 }
3239
3240 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3241 {
3242         struct drm_device *dev = crtc->dev;
3243         struct drm_i915_private *dev_priv = dev->dev_private;
3244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3245         struct intel_encoder *encoder;
3246         int pipe = intel_crtc->pipe;
3247         int plane = intel_crtc->plane;
3248
3249         WARN_ON(!crtc->enabled);
3250
3251         if (intel_crtc->active)
3252                 return;
3253
3254         intel_crtc->active = true;
3255
3256         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3257         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3258
3259         intel_update_watermarks(dev);
3260
3261         for_each_encoder_on_crtc(dev, crtc, encoder)
3262                 if (encoder->pre_enable)
3263                         encoder->pre_enable(encoder);
3264
3265         if (intel_crtc->config.has_pch_encoder) {
3266                 /* Note: FDI PLL enabling _must_ be done before we enable the
3267                  * cpu pipes, hence this is separate from all the other fdi/pch
3268                  * enabling. */
3269                 ironlake_fdi_pll_enable(intel_crtc);
3270         } else {
3271                 assert_fdi_tx_disabled(dev_priv, pipe);
3272                 assert_fdi_rx_disabled(dev_priv, pipe);
3273         }
3274
3275         ironlake_pfit_enable(intel_crtc);
3276
3277         /*
3278          * On ILK+ LUT must be loaded before the pipe is running but with
3279          * clocks enabled
3280          */
3281         intel_crtc_load_lut(crtc);
3282
3283         intel_enable_pipe(dev_priv, pipe,
3284                           intel_crtc->config.has_pch_encoder);
3285         intel_enable_plane(dev_priv, plane, pipe);
3286         intel_enable_planes(crtc);
3287         intel_crtc_update_cursor(crtc, true);
3288
3289         if (intel_crtc->config.has_pch_encoder)
3290                 ironlake_pch_enable(crtc);
3291
3292         mutex_lock(&dev->struct_mutex);
3293         intel_update_fbc(dev);
3294         mutex_unlock(&dev->struct_mutex);
3295
3296         for_each_encoder_on_crtc(dev, crtc, encoder)
3297                 encoder->enable(encoder);
3298
3299         if (HAS_PCH_CPT(dev))
3300                 cpt_verify_modeset(dev, intel_crtc->pipe);
3301
3302         /*
3303          * There seems to be a race in PCH platform hw (at least on some
3304          * outputs) where an enabled pipe still completes any pageflip right
3305          * away (as if the pipe is off) instead of waiting for vblank. As soon
3306          * as the first vblank happend, everything works as expected. Hence just
3307          * wait for one vblank before returning to avoid strange things
3308          * happening.
3309          */
3310         intel_wait_for_vblank(dev, intel_crtc->pipe);
3311 }
3312
3313 /* IPS only exists on ULT machines and is tied to pipe A. */
3314 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3315 {
3316         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3317 }
3318
3319 static void hsw_enable_ips(struct intel_crtc *crtc)
3320 {
3321         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3322
3323         if (!crtc->config.ips_enabled)
3324                 return;
3325
3326         /* We can only enable IPS after we enable a plane and wait for a vblank.
3327          * We guarantee that the plane is enabled by calling intel_enable_ips
3328          * only after intel_enable_plane. And intel_enable_plane already waits
3329          * for a vblank, so all we need to do here is to enable the IPS bit. */
3330         assert_plane_enabled(dev_priv, crtc->plane);
3331         I915_WRITE(IPS_CTL, IPS_ENABLE);
3332 }
3333
3334 static void hsw_disable_ips(struct intel_crtc *crtc)
3335 {
3336         struct drm_device *dev = crtc->base.dev;
3337         struct drm_i915_private *dev_priv = dev->dev_private;
3338
3339         if (!crtc->config.ips_enabled)
3340                 return;
3341
3342         assert_plane_enabled(dev_priv, crtc->plane);
3343         I915_WRITE(IPS_CTL, 0);
3344
3345         /* We need to wait for a vblank before we can disable the plane. */
3346         intel_wait_for_vblank(dev, crtc->pipe);
3347 }
3348
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         struct intel_encoder *encoder;
3355         int pipe = intel_crtc->pipe;
3356         int plane = intel_crtc->plane;
3357
3358         WARN_ON(!crtc->enabled);
3359
3360         if (intel_crtc->active)
3361                 return;
3362
3363         intel_crtc->active = true;
3364
3365         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366         if (intel_crtc->config.has_pch_encoder)
3367                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368
3369         intel_update_watermarks(dev);
3370
3371         if (intel_crtc->config.has_pch_encoder)
3372                 dev_priv->display.fdi_link_train(crtc);
3373
3374         for_each_encoder_on_crtc(dev, crtc, encoder)
3375                 if (encoder->pre_enable)
3376                         encoder->pre_enable(encoder);
3377
3378         intel_ddi_enable_pipe_clock(intel_crtc);
3379
3380         ironlake_pfit_enable(intel_crtc);
3381
3382         /*
3383          * On ILK+ LUT must be loaded before the pipe is running but with
3384          * clocks enabled
3385          */
3386         intel_crtc_load_lut(crtc);
3387
3388         intel_ddi_set_pipe_settings(crtc);
3389         intel_ddi_enable_transcoder_func(crtc);
3390
3391         intel_enable_pipe(dev_priv, pipe,
3392                           intel_crtc->config.has_pch_encoder);
3393         intel_enable_plane(dev_priv, plane, pipe);
3394         intel_enable_planes(crtc);
3395         intel_crtc_update_cursor(crtc, true);
3396
3397         hsw_enable_ips(intel_crtc);
3398
3399         if (intel_crtc->config.has_pch_encoder)
3400                 lpt_pch_enable(crtc);
3401
3402         mutex_lock(&dev->struct_mutex);
3403         intel_update_fbc(dev);
3404         mutex_unlock(&dev->struct_mutex);
3405
3406         for_each_encoder_on_crtc(dev, crtc, encoder)
3407                 encoder->enable(encoder);
3408
3409         /*
3410          * There seems to be a race in PCH platform hw (at least on some
3411          * outputs) where an enabled pipe still completes any pageflip right
3412          * away (as if the pipe is off) instead of waiting for vblank. As soon
3413          * as the first vblank happend, everything works as expected. Hence just
3414          * wait for one vblank before returning to avoid strange things
3415          * happening.
3416          */
3417         intel_wait_for_vblank(dev, intel_crtc->pipe);
3418 }
3419
3420 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3421 {
3422         struct drm_device *dev = crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = crtc->pipe;
3425
3426         /* To avoid upsetting the power well on haswell only disable the pfit if
3427          * it's in use. The hw state code will make sure we get this right. */
3428         if (crtc->config.pch_pfit.size) {
3429                 I915_WRITE(PF_CTL(pipe), 0);
3430                 I915_WRITE(PF_WIN_POS(pipe), 0);
3431                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3432         }
3433 }
3434
3435 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         struct drm_i915_private *dev_priv = dev->dev_private;
3439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3440         struct intel_encoder *encoder;
3441         int pipe = intel_crtc->pipe;
3442         int plane = intel_crtc->plane;
3443         u32 reg, temp;
3444
3445
3446         if (!intel_crtc->active)
3447                 return;
3448
3449         for_each_encoder_on_crtc(dev, crtc, encoder)
3450                 encoder->disable(encoder);
3451
3452         intel_crtc_wait_for_pending_flips(crtc);
3453         drm_vblank_off(dev, pipe);
3454
3455         if (dev_priv->fbc.plane == plane)
3456                 intel_disable_fbc(dev);
3457
3458         intel_crtc_update_cursor(crtc, false);
3459         intel_disable_planes(crtc);
3460         intel_disable_plane(dev_priv, plane, pipe);
3461
3462         if (intel_crtc->config.has_pch_encoder)
3463                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3464
3465         intel_disable_pipe(dev_priv, pipe);
3466
3467         ironlake_pfit_disable(intel_crtc);
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 if (encoder->post_disable)
3471                         encoder->post_disable(encoder);
3472
3473         if (intel_crtc->config.has_pch_encoder) {
3474                 ironlake_fdi_disable(crtc);
3475
3476                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3477                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3478
3479                 if (HAS_PCH_CPT(dev)) {
3480                         /* disable TRANS_DP_CTL */
3481                         reg = TRANS_DP_CTL(pipe);
3482                         temp = I915_READ(reg);
3483                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3484                                   TRANS_DP_PORT_SEL_MASK);
3485                         temp |= TRANS_DP_PORT_SEL_NONE;
3486                         I915_WRITE(reg, temp);
3487
3488                         /* disable DPLL_SEL */
3489                         temp = I915_READ(PCH_DPLL_SEL);
3490                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3491                         I915_WRITE(PCH_DPLL_SEL, temp);
3492                 }
3493
3494                 /* disable PCH DPLL */
3495                 intel_disable_shared_dpll(intel_crtc);
3496
3497                 ironlake_fdi_pll_disable(intel_crtc);
3498         }
3499
3500         intel_crtc->active = false;
3501         intel_update_watermarks(dev);
3502
3503         mutex_lock(&dev->struct_mutex);
3504         intel_update_fbc(dev);
3505         mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void haswell_crtc_disable(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         struct intel_encoder *encoder;
3514         int pipe = intel_crtc->pipe;
3515         int plane = intel_crtc->plane;
3516         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3517
3518         if (!intel_crtc->active)
3519                 return;
3520
3521         for_each_encoder_on_crtc(dev, crtc, encoder)
3522                 encoder->disable(encoder);
3523
3524         intel_crtc_wait_for_pending_flips(crtc);
3525         drm_vblank_off(dev, pipe);
3526
3527         /* FBC must be disabled before disabling the plane on HSW. */
3528         if (dev_priv->fbc.plane == plane)
3529                 intel_disable_fbc(dev);
3530
3531         hsw_disable_ips(intel_crtc);
3532
3533         intel_crtc_update_cursor(crtc, false);
3534         intel_disable_planes(crtc);
3535         intel_disable_plane(dev_priv, plane, pipe);
3536
3537         if (intel_crtc->config.has_pch_encoder)
3538                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3539         intel_disable_pipe(dev_priv, pipe);
3540
3541         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3542
3543         ironlake_pfit_disable(intel_crtc);
3544
3545         intel_ddi_disable_pipe_clock(intel_crtc);
3546
3547         for_each_encoder_on_crtc(dev, crtc, encoder)
3548                 if (encoder->post_disable)
3549                         encoder->post_disable(encoder);
3550
3551         if (intel_crtc->config.has_pch_encoder) {
3552                 lpt_disable_pch_transcoder(dev_priv);
3553                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3554                 intel_ddi_fdi_disable(crtc);
3555         }
3556
3557         intel_crtc->active = false;
3558         intel_update_watermarks(dev);
3559
3560         mutex_lock(&dev->struct_mutex);
3561         intel_update_fbc(dev);
3562         mutex_unlock(&dev->struct_mutex);
3563 }
3564
3565 static void ironlake_crtc_off(struct drm_crtc *crtc)
3566 {
3567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568         intel_put_shared_dpll(intel_crtc);
3569 }
3570
3571 static void haswell_crtc_off(struct drm_crtc *crtc)
3572 {
3573         intel_ddi_put_crtc_pll(crtc);
3574 }
3575
3576 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3577 {
3578         if (!enable && intel_crtc->overlay) {
3579                 struct drm_device *dev = intel_crtc->base.dev;
3580                 struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582                 mutex_lock(&dev->struct_mutex);
3583                 dev_priv->mm.interruptible = false;
3584                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3585                 dev_priv->mm.interruptible = true;
3586                 mutex_unlock(&dev->struct_mutex);
3587         }
3588
3589         /* Let userspace switch the overlay on again. In most cases userspace
3590          * has to recompute where to put it anyway.
3591          */
3592 }
3593
3594 /**
3595  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3596  * cursor plane briefly if not already running after enabling the display
3597  * plane.
3598  * This workaround avoids occasional blank screens when self refresh is
3599  * enabled.
3600  */
3601 static void
3602 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3603 {
3604         u32 cntl = I915_READ(CURCNTR(pipe));
3605
3606         if ((cntl & CURSOR_MODE) == 0) {
3607                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3608
3609                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3610                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3611                 intel_wait_for_vblank(dev_priv->dev, pipe);
3612                 I915_WRITE(CURCNTR(pipe), cntl);
3613                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3614                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3615         }
3616 }
3617
3618 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3619 {
3620         struct drm_device *dev = crtc->base.dev;
3621         struct drm_i915_private *dev_priv = dev->dev_private;
3622         struct intel_crtc_config *pipe_config = &crtc->config;
3623
3624         if (!crtc->config.gmch_pfit.control)
3625                 return;
3626
3627         /*
3628          * The panel fitter should only be adjusted whilst the pipe is disabled,
3629          * according to register description and PRM.
3630          */
3631         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3632         assert_pipe_disabled(dev_priv, crtc->pipe);
3633
3634         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3635         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3636
3637         /* Border color in case we don't scale up to the full screen. Black by
3638          * default, change to something else for debugging. */
3639         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3640 }
3641
3642 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647         struct intel_encoder *encoder;
3648         int pipe = intel_crtc->pipe;
3649         int plane = intel_crtc->plane;
3650
3651         WARN_ON(!crtc->enabled);
3652
3653         if (intel_crtc->active)
3654                 return;
3655
3656         intel_crtc->active = true;
3657         intel_update_watermarks(dev);
3658
3659         for_each_encoder_on_crtc(dev, crtc, encoder)
3660                 if (encoder->pre_pll_enable)
3661                         encoder->pre_pll_enable(encoder);
3662
3663         vlv_enable_pll(intel_crtc);
3664
3665         for_each_encoder_on_crtc(dev, crtc, encoder)
3666                 if (encoder->pre_enable)
3667                         encoder->pre_enable(encoder);
3668
3669         i9xx_pfit_enable(intel_crtc);
3670
3671         intel_crtc_load_lut(crtc);
3672
3673         intel_enable_pipe(dev_priv, pipe, false);
3674         intel_enable_plane(dev_priv, plane, pipe);
3675         intel_enable_planes(crtc);
3676         intel_crtc_update_cursor(crtc, true);
3677
3678         intel_update_fbc(dev);
3679
3680         for_each_encoder_on_crtc(dev, crtc, encoder)
3681                 encoder->enable(encoder);
3682 }
3683
3684 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3685 {
3686         struct drm_device *dev = crtc->dev;
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689         struct intel_encoder *encoder;
3690         int pipe = intel_crtc->pipe;
3691         int plane = intel_crtc->plane;
3692
3693         WARN_ON(!crtc->enabled);
3694
3695         if (intel_crtc->active)
3696                 return;
3697
3698         intel_crtc->active = true;
3699         intel_update_watermarks(dev);
3700
3701         for_each_encoder_on_crtc(dev, crtc, encoder)
3702                 if (encoder->pre_enable)
3703                         encoder->pre_enable(encoder);
3704
3705         i9xx_enable_pll(intel_crtc);
3706
3707         i9xx_pfit_enable(intel_crtc);
3708
3709         intel_crtc_load_lut(crtc);
3710
3711         intel_enable_pipe(dev_priv, pipe, false);
3712         intel_enable_plane(dev_priv, plane, pipe);
3713         intel_enable_planes(crtc);
3714         /* The fixup needs to happen before cursor is enabled */
3715         if (IS_G4X(dev))
3716                 g4x_fixup_plane(dev_priv, pipe);
3717         intel_crtc_update_cursor(crtc, true);
3718
3719         /* Give the overlay scaler a chance to enable if it's on this pipe */
3720         intel_crtc_dpms_overlay(intel_crtc, true);
3721
3722         intel_update_fbc(dev);
3723
3724         for_each_encoder_on_crtc(dev, crtc, encoder)
3725                 encoder->enable(encoder);
3726 }
3727
3728 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3729 {
3730         struct drm_device *dev = crtc->base.dev;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732
3733         if (!crtc->config.gmch_pfit.control)
3734                 return;
3735
3736         assert_pipe_disabled(dev_priv, crtc->pipe);
3737
3738         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3739                          I915_READ(PFIT_CONTROL));
3740         I915_WRITE(PFIT_CONTROL, 0);
3741 }
3742
3743 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3744 {
3745         struct drm_device *dev = crtc->dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3748         struct intel_encoder *encoder;
3749         int pipe = intel_crtc->pipe;
3750         int plane = intel_crtc->plane;
3751
3752         if (!intel_crtc->active)
3753                 return;
3754
3755         for_each_encoder_on_crtc(dev, crtc, encoder)
3756                 encoder->disable(encoder);
3757
3758         /* Give the overlay scaler a chance to disable if it's on this pipe */
3759         intel_crtc_wait_for_pending_flips(crtc);
3760         drm_vblank_off(dev, pipe);
3761
3762         if (dev_priv->fbc.plane == plane)
3763                 intel_disable_fbc(dev);
3764
3765         intel_crtc_dpms_overlay(intel_crtc, false);
3766         intel_crtc_update_cursor(crtc, false);
3767         intel_disable_planes(crtc);
3768         intel_disable_plane(dev_priv, plane, pipe);
3769
3770         intel_disable_pipe(dev_priv, pipe);
3771
3772         i9xx_pfit_disable(intel_crtc);
3773
3774         for_each_encoder_on_crtc(dev, crtc, encoder)
3775                 if (encoder->post_disable)
3776                         encoder->post_disable(encoder);
3777
3778         i9xx_disable_pll(dev_priv, pipe);
3779
3780         intel_crtc->active = false;
3781         intel_update_fbc(dev);
3782         intel_update_watermarks(dev);
3783 }
3784
3785 static void i9xx_crtc_off(struct drm_crtc *crtc)
3786 {
3787 }
3788
3789 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3790                                     bool enabled)
3791 {
3792         struct drm_device *dev = crtc->dev;
3793         struct drm_i915_master_private *master_priv;
3794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795         int pipe = intel_crtc->pipe;
3796
3797         if (!dev->primary->master)
3798                 return;
3799
3800         master_priv = dev->primary->master->driver_priv;
3801         if (!master_priv->sarea_priv)
3802                 return;
3803
3804         switch (pipe) {
3805         case 0:
3806                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3807                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3808                 break;
3809         case 1:
3810                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3811                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3812                 break;
3813         default:
3814                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3815                 break;
3816         }
3817 }
3818
3819 /**
3820  * Sets the power management mode of the pipe and plane.
3821  */
3822 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3823 {
3824         struct drm_device *dev = crtc->dev;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826         struct intel_encoder *intel_encoder;
3827         bool enable = false;
3828
3829         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3830                 enable |= intel_encoder->connectors_active;
3831
3832         if (enable)
3833                 dev_priv->display.crtc_enable(crtc);
3834         else
3835                 dev_priv->display.crtc_disable(crtc);
3836
3837         intel_crtc_update_sarea(crtc, enable);
3838 }
3839
3840 static void intel_crtc_disable(struct drm_crtc *crtc)
3841 {
3842         struct drm_device *dev = crtc->dev;
3843         struct drm_connector *connector;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846
3847         /* crtc should still be enabled when we disable it. */
3848         WARN_ON(!crtc->enabled);
3849
3850         dev_priv->display.crtc_disable(crtc);
3851         intel_crtc->eld_vld = false;
3852         intel_crtc_update_sarea(crtc, false);
3853         dev_priv->display.off(crtc);
3854
3855         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3856         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3857
3858         if (crtc->fb) {
3859                 mutex_lock(&dev->struct_mutex);
3860                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3861                 mutex_unlock(&dev->struct_mutex);
3862                 crtc->fb = NULL;
3863         }
3864
3865         /* Update computed state. */
3866         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3867                 if (!connector->encoder || !connector->encoder->crtc)
3868                         continue;
3869
3870                 if (connector->encoder->crtc != crtc)
3871                         continue;
3872
3873                 connector->dpms = DRM_MODE_DPMS_OFF;
3874                 to_intel_encoder(connector->encoder)->connectors_active = false;
3875         }
3876 }
3877
3878 void intel_encoder_destroy(struct drm_encoder *encoder)
3879 {
3880         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3881
3882         drm_encoder_cleanup(encoder);
3883         kfree(intel_encoder);
3884 }
3885
3886 /* Simple dpms helper for encoders with just one connector, no cloning and only
3887  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3888  * state of the entire output pipe. */
3889 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3890 {
3891         if (mode == DRM_MODE_DPMS_ON) {
3892                 encoder->connectors_active = true;
3893
3894                 intel_crtc_update_dpms(encoder->base.crtc);
3895         } else {
3896                 encoder->connectors_active = false;
3897
3898                 intel_crtc_update_dpms(encoder->base.crtc);
3899         }
3900 }
3901
3902 /* Cross check the actual hw state with our own modeset state tracking (and it's
3903  * internal consistency). */
3904 static void intel_connector_check_state(struct intel_connector *connector)
3905 {
3906         if (connector->get_hw_state(connector)) {
3907                 struct intel_encoder *encoder = connector->encoder;
3908                 struct drm_crtc *crtc;
3909                 bool encoder_enabled;
3910                 enum pipe pipe;
3911
3912                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3913                               connector->base.base.id,
3914                               drm_get_connector_name(&connector->base));
3915
3916                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3917                      "wrong connector dpms state\n");
3918                 WARN(connector->base.encoder != &encoder->base,
3919                      "active connector not linked to encoder\n");
3920                 WARN(!encoder->connectors_active,
3921                      "encoder->connectors_active not set\n");
3922
3923                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3924                 WARN(!encoder_enabled, "encoder not enabled\n");
3925                 if (WARN_ON(!encoder->base.crtc))
3926                         return;
3927
3928                 crtc = encoder->base.crtc;
3929
3930                 WARN(!crtc->enabled, "crtc not enabled\n");
3931                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3932                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3933                      "encoder active on the wrong pipe\n");
3934         }
3935 }
3936
3937 /* Even simpler default implementation, if there's really no special case to
3938  * consider. */
3939 void intel_connector_dpms(struct drm_connector *connector, int mode)
3940 {
3941         struct intel_encoder *encoder = intel_attached_encoder(connector);
3942
3943         /* All the simple cases only support two dpms states. */
3944         if (mode != DRM_MODE_DPMS_ON)
3945                 mode = DRM_MODE_DPMS_OFF;
3946
3947         if (mode == connector->dpms)
3948                 return;
3949
3950         connector->dpms = mode;
3951
3952         /* Only need to change hw state when actually enabled */
3953         if (encoder->base.crtc)
3954                 intel_encoder_dpms(encoder, mode);
3955         else
3956                 WARN_ON(encoder->connectors_active != false);
3957
3958         intel_modeset_check_state(connector->dev);
3959 }
3960
3961 /* Simple connector->get_hw_state implementation for encoders that support only
3962  * one connector and no cloning and hence the encoder state determines the state
3963  * of the connector. */
3964 bool intel_connector_get_hw_state(struct intel_connector *connector)
3965 {
3966         enum pipe pipe = 0;
3967         struct intel_encoder *encoder = connector->encoder;
3968
3969         return encoder->get_hw_state(encoder, &pipe);
3970 }
3971
3972 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3973                                      struct intel_crtc_config *pipe_config)
3974 {
3975         struct drm_i915_private *dev_priv = dev->dev_private;
3976         struct intel_crtc *pipe_B_crtc =
3977                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3978
3979         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3980                       pipe_name(pipe), pipe_config->fdi_lanes);
3981         if (pipe_config->fdi_lanes > 4) {
3982                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3983                               pipe_name(pipe), pipe_config->fdi_lanes);
3984                 return false;
3985         }
3986
3987         if (IS_HASWELL(dev)) {
3988                 if (pipe_config->fdi_lanes > 2) {
3989                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3990                                       pipe_config->fdi_lanes);
3991                         return false;
3992                 } else {
3993                         return true;
3994                 }
3995         }
3996
3997         if (INTEL_INFO(dev)->num_pipes == 2)
3998                 return true;
3999
4000         /* Ivybridge 3 pipe is really complicated */
4001         switch (pipe) {
4002         case PIPE_A:
4003                 return true;
4004         case PIPE_B:
4005                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4006                     pipe_config->fdi_lanes > 2) {
4007                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4008                                       pipe_name(pipe), pipe_config->fdi_lanes);
4009                         return false;
4010                 }
4011                 return true;
4012         case PIPE_C:
4013                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4014                     pipe_B_crtc->config.fdi_lanes <= 2) {
4015                         if (pipe_config->fdi_lanes > 2) {
4016                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4017                                               pipe_name(pipe), pipe_config->fdi_lanes);
4018                                 return false;
4019                         }
4020                 } else {
4021                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4022                         return false;
4023                 }
4024                 return true;
4025         default:
4026                 BUG();
4027         }
4028 }
4029
4030 #define RETRY 1
4031 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4032                                        struct intel_crtc_config *pipe_config)
4033 {
4034         struct drm_device *dev = intel_crtc->base.dev;
4035         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4036         int lane, link_bw, fdi_dotclock;
4037         bool setup_ok, needs_recompute = false;
4038
4039 retry:
4040         /* FDI is a binary signal running at ~2.7GHz, encoding
4041          * each output octet as 10 bits. The actual frequency
4042          * is stored as a divider into a 100MHz clock, and the
4043          * mode pixel clock is stored in units of 1KHz.
4044          * Hence the bw of each lane in terms of the mode signal
4045          * is:
4046          */
4047         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4048
4049         fdi_dotclock = adjusted_mode->clock;
4050         fdi_dotclock /= pipe_config->pixel_multiplier;
4051
4052         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4053                                            pipe_config->pipe_bpp);
4054
4055         pipe_config->fdi_lanes = lane;
4056
4057         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4058                                link_bw, &pipe_config->fdi_m_n);
4059
4060         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4061                                             intel_crtc->pipe, pipe_config);
4062         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4063                 pipe_config->pipe_bpp -= 2*3;
4064                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4065                               pipe_config->pipe_bpp);
4066                 needs_recompute = true;
4067                 pipe_config->bw_constrained = true;
4068
4069                 goto retry;
4070         }
4071
4072         if (needs_recompute)
4073                 return RETRY;
4074
4075         return setup_ok ? 0 : -EINVAL;
4076 }
4077
4078 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4079                                    struct intel_crtc_config *pipe_config)
4080 {
4081         pipe_config->ips_enabled = i915_enable_ips &&
4082                                    hsw_crtc_supports_ips(crtc) &&
4083                                    pipe_config->pipe_bpp <= 24;
4084 }
4085
4086 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4087                                      struct intel_crtc_config *pipe_config)
4088 {
4089         struct drm_device *dev = crtc->base.dev;
4090         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4091
4092         if (HAS_PCH_SPLIT(dev)) {
4093                 /* FDI link clock is fixed at 2.7G */
4094                 if (pipe_config->requested_mode.clock * 3
4095                     > IRONLAKE_FDI_FREQ * 4)
4096                         return -EINVAL;
4097         }
4098
4099         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4100          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4101          */
4102         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4103                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4104                 return -EINVAL;
4105
4106         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4107                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4108         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4109                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4110                  * for lvds. */
4111                 pipe_config->pipe_bpp = 8*3;
4112         }
4113
4114         if (HAS_IPS(dev))
4115                 hsw_compute_ips_config(crtc, pipe_config);
4116
4117         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4118          * clock survives for now. */
4119         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4120                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4121
4122         if (pipe_config->has_pch_encoder)
4123                 return ironlake_fdi_compute_config(crtc, pipe_config);
4124
4125         return 0;
4126 }
4127
4128 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4129 {
4130         return 400000; /* FIXME */
4131 }
4132
4133 static int i945_get_display_clock_speed(struct drm_device *dev)
4134 {
4135         return 400000;
4136 }
4137
4138 static int i915_get_display_clock_speed(struct drm_device *dev)
4139 {
4140         return 333000;
4141 }
4142
4143 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4144 {
4145         return 200000;
4146 }
4147
4148 static int pnv_get_display_clock_speed(struct drm_device *dev)
4149 {
4150         u16 gcfgc = 0;
4151
4152         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4153
4154         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4155         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4156                 return 267000;
4157         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4158                 return 333000;
4159         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4160                 return 444000;
4161         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4162                 return 200000;
4163         default:
4164                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4165         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4166                 return 133000;
4167         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4168                 return 167000;
4169         }
4170 }
4171
4172 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4173 {
4174         u16 gcfgc = 0;
4175
4176         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4177
4178         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4179                 return 133000;
4180         else {
4181                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4182                 case GC_DISPLAY_CLOCK_333_MHZ:
4183                         return 333000;
4184                 default:
4185                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4186                         return 190000;
4187                 }
4188         }
4189 }
4190
4191 static int i865_get_display_clock_speed(struct drm_device *dev)
4192 {
4193         return 266000;
4194 }
4195
4196 static int i855_get_display_clock_speed(struct drm_device *dev)
4197 {
4198         u16 hpllcc = 0;
4199         /* Assume that the hardware is in the high speed state.  This
4200          * should be the default.
4201          */
4202         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4203         case GC_CLOCK_133_200:
4204         case GC_CLOCK_100_200:
4205                 return 200000;
4206         case GC_CLOCK_166_250:
4207                 return 250000;
4208         case GC_CLOCK_100_133:
4209                 return 133000;
4210         }
4211
4212         /* Shouldn't happen */
4213         return 0;
4214 }
4215
4216 static int i830_get_display_clock_speed(struct drm_device *dev)
4217 {
4218         return 133000;
4219 }
4220
4221 static void
4222 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4223 {
4224         while (*num > DATA_LINK_M_N_MASK ||
4225                *den > DATA_LINK_M_N_MASK) {
4226                 *num >>= 1;
4227                 *den >>= 1;
4228         }
4229 }
4230
4231 static void compute_m_n(unsigned int m, unsigned int n,
4232                         uint32_t *ret_m, uint32_t *ret_n)
4233 {
4234         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4235         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4236         intel_reduce_m_n_ratio(ret_m, ret_n);
4237 }
4238
4239 void
4240 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4241                        int pixel_clock, int link_clock,
4242                        struct intel_link_m_n *m_n)
4243 {
4244         m_n->tu = 64;
4245
4246         compute_m_n(bits_per_pixel * pixel_clock,
4247                     link_clock * nlanes * 8,
4248                     &m_n->gmch_m, &m_n->gmch_n);
4249
4250         compute_m_n(pixel_clock, link_clock,
4251                     &m_n->link_m, &m_n->link_n);
4252 }
4253
4254 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4255 {
4256         if (i915_panel_use_ssc >= 0)
4257                 return i915_panel_use_ssc != 0;
4258         return dev_priv->vbt.lvds_use_ssc
4259                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4260 }
4261
4262 static int vlv_get_refclk(struct drm_crtc *crtc)
4263 {
4264         struct drm_device *dev = crtc->dev;
4265         struct drm_i915_private *dev_priv = dev->dev_private;
4266         int refclk = 27000; /* for DP & HDMI */
4267
4268         return 100000; /* only one validated so far */
4269
4270         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4271                 refclk = 96000;
4272         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4273                 if (intel_panel_use_ssc(dev_priv))
4274                         refclk = 100000;
4275                 else
4276                         refclk = 96000;
4277         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4278                 refclk = 100000;
4279         }
4280
4281         return refclk;
4282 }
4283
4284 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4285 {
4286         struct drm_device *dev = crtc->dev;
4287         struct drm_i915_private *dev_priv = dev->dev_private;
4288         int refclk;
4289
4290         if (IS_VALLEYVIEW(dev)) {
4291                 refclk = vlv_get_refclk(crtc);
4292         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4293             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4294                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4295                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4296                               refclk / 1000);
4297         } else if (!IS_GEN2(dev)) {
4298                 refclk = 96000;
4299         } else {
4300                 refclk = 48000;
4301         }
4302
4303         return refclk;
4304 }
4305
4306 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4307 {
4308         return (1 << dpll->n) << 16 | dpll->m2;
4309 }
4310
4311 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4312 {
4313         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4314 }
4315
4316 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4317                                      intel_clock_t *reduced_clock)
4318 {
4319         struct drm_device *dev = crtc->base.dev;
4320         struct drm_i915_private *dev_priv = dev->dev_private;
4321         int pipe = crtc->pipe;
4322         u32 fp, fp2 = 0;
4323
4324         if (IS_PINEVIEW(dev)) {
4325                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4326                 if (reduced_clock)
4327                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4328         } else {
4329                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4330                 if (reduced_clock)
4331                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4332         }
4333
4334         I915_WRITE(FP0(pipe), fp);
4335         crtc->config.dpll_hw_state.fp0 = fp;
4336
4337         crtc->lowfreq_avail = false;
4338         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4339             reduced_clock && i915_powersave) {
4340                 I915_WRITE(FP1(pipe), fp2);
4341                 crtc->config.dpll_hw_state.fp1 = fp2;
4342                 crtc->lowfreq_avail = true;
4343         } else {
4344                 I915_WRITE(FP1(pipe), fp);
4345                 crtc->config.dpll_hw_state.fp1 = fp;
4346         }
4347 }
4348
4349 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4350 {
4351         u32 reg_val;
4352
4353         /*
4354          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4355          * and set it to a reasonable value instead.
4356          */
4357         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4358         reg_val &= 0xffffff00;
4359         reg_val |= 0x00000030;
4360         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4361
4362         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4363         reg_val &= 0x8cffffff;
4364         reg_val = 0x8c000000;
4365         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4366
4367         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4368         reg_val &= 0xffffff00;
4369         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4370
4371         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4372         reg_val &= 0x00ffffff;
4373         reg_val |= 0xb0000000;
4374         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4375 }
4376
4377 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4378                                          struct intel_link_m_n *m_n)
4379 {
4380         struct drm_device *dev = crtc->base.dev;
4381         struct drm_i915_private *dev_priv = dev->dev_private;
4382         int pipe = crtc->pipe;
4383
4384         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4385         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4386         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4387         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4388 }
4389
4390 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4391                                          struct intel_link_m_n *m_n)
4392 {
4393         struct drm_device *dev = crtc->base.dev;
4394         struct drm_i915_private *dev_priv = dev->dev_private;
4395         int pipe = crtc->pipe;
4396         enum transcoder transcoder = crtc->config.cpu_transcoder;
4397
4398         if (INTEL_INFO(dev)->gen >= 5) {
4399                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4400                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4401                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4402                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4403         } else {
4404                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4405                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4406                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4407                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4408         }
4409 }
4410
4411 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4412 {
4413         if (crtc->config.has_pch_encoder)
4414                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4415         else
4416                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4417 }
4418
4419 static void vlv_update_pll(struct intel_crtc *crtc)
4420 {
4421         struct drm_device *dev = crtc->base.dev;
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423         int pipe = crtc->pipe;
4424         u32 dpll, mdiv;
4425         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4426         bool is_hdmi;
4427         u32 coreclk, reg_val, dpll_md;
4428
4429         mutex_lock(&dev_priv->dpio_lock);
4430
4431         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4432
4433         bestn = crtc->config.dpll.n;
4434         bestm1 = crtc->config.dpll.m1;
4435         bestm2 = crtc->config.dpll.m2;
4436         bestp1 = crtc->config.dpll.p1;
4437         bestp2 = crtc->config.dpll.p2;
4438
4439         /* See eDP HDMI DPIO driver vbios notes doc */
4440
4441         /* PLL B needs special handling */
4442         if (pipe)
4443                 vlv_pllb_recal_opamp(dev_priv);
4444
4445         /* Set up Tx target for periodic Rcomp update */
4446         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4447
4448         /* Disable target IRef on PLL */
4449         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4450         reg_val &= 0x00ffffff;
4451         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4452
4453         /* Disable fast lock */
4454         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4455
4456         /* Set idtafcrecal before PLL is enabled */
4457         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4458         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4459         mdiv |= ((bestn << DPIO_N_SHIFT));
4460         mdiv |= (1 << DPIO_K_SHIFT);
4461
4462         /*
4463          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4464          * but we don't support that).
4465          * Note: don't use the DAC post divider as it seems unstable.
4466          */
4467         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4468         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4469
4470         mdiv |= DPIO_ENABLE_CALIBRATION;
4471         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4472
4473         /* Set HBR and RBR LPF coefficients */
4474         if (crtc->config.port_clock == 162000 ||
4475             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4476             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4477                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4478                                  0x009f0003);
4479         else
4480                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4481                                  0x00d0000f);
4482
4483         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4484             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4485                 /* Use SSC source */
4486                 if (!pipe)
4487                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488                                          0x0df40000);
4489                 else
4490                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4491                                          0x0df70000);
4492         } else { /* HDMI or VGA */
4493                 /* Use bend source */
4494                 if (!pipe)
4495                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4496                                          0x0df70000);
4497                 else
4498                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4499                                          0x0df40000);
4500         }
4501
4502         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4503         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4504         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4505             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4506                 coreclk |= 0x01000000;
4507         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4508
4509         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4510
4511         /* Enable DPIO clock input */
4512         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4513                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4514         if (pipe)
4515                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4516
4517         dpll |= DPLL_VCO_ENABLE;
4518         crtc->config.dpll_hw_state.dpll = dpll;
4519
4520         dpll_md = (crtc->config.pixel_multiplier - 1)
4521                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4522         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4523
4524         if (crtc->config.has_dp_encoder)
4525                 intel_dp_set_m_n(crtc);
4526
4527         mutex_unlock(&dev_priv->dpio_lock);
4528 }
4529
4530 static void i9xx_update_pll(struct intel_crtc *crtc,
4531                             intel_clock_t *reduced_clock,
4532                             int num_connectors)
4533 {
4534         struct drm_device *dev = crtc->base.dev;
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536         u32 dpll;
4537         bool is_sdvo;
4538         struct dpll *clock = &crtc->config.dpll;
4539
4540         i9xx_update_pll_dividers(crtc, reduced_clock);
4541
4542         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4543                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4544
4545         dpll = DPLL_VGA_MODE_DIS;
4546
4547         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4548                 dpll |= DPLLB_MODE_LVDS;
4549         else
4550                 dpll |= DPLLB_MODE_DAC_SERIAL;
4551
4552         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4553                 dpll |= (crtc->config.pixel_multiplier - 1)
4554                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4555         }
4556
4557         if (is_sdvo)
4558                 dpll |= DPLL_SDVO_HIGH_SPEED;
4559
4560         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4561                 dpll |= DPLL_SDVO_HIGH_SPEED;
4562
4563         /* compute bitmask from p1 value */
4564         if (IS_PINEVIEW(dev))
4565                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4566         else {
4567                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4568                 if (IS_G4X(dev) && reduced_clock)
4569                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4570         }
4571         switch (clock->p2) {
4572         case 5:
4573                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4574                 break;
4575         case 7:
4576                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4577                 break;
4578         case 10:
4579                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4580                 break;
4581         case 14:
4582                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4583                 break;
4584         }
4585         if (INTEL_INFO(dev)->gen >= 4)
4586                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4587
4588         if (crtc->config.sdvo_tv_clock)
4589                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4590         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4591                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4593         else
4594                 dpll |= PLL_REF_INPUT_DREFCLK;
4595
4596         dpll |= DPLL_VCO_ENABLE;
4597         crtc->config.dpll_hw_state.dpll = dpll;
4598
4599         if (INTEL_INFO(dev)->gen >= 4) {
4600                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4601                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4602                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4603         }
4604
4605         if (crtc->config.has_dp_encoder)
4606                 intel_dp_set_m_n(crtc);
4607 }
4608
4609 static void i8xx_update_pll(struct intel_crtc *crtc,
4610                             intel_clock_t *reduced_clock,
4611                             int num_connectors)
4612 {
4613         struct drm_device *dev = crtc->base.dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615         u32 dpll;
4616         struct dpll *clock = &crtc->config.dpll;
4617
4618         i9xx_update_pll_dividers(crtc, reduced_clock);
4619
4620         dpll = DPLL_VGA_MODE_DIS;
4621
4622         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4623                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4624         } else {
4625                 if (clock->p1 == 2)
4626                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4627                 else
4628                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4629                 if (clock->p2 == 4)
4630                         dpll |= PLL_P2_DIVIDE_BY_4;
4631         }
4632
4633         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4634                 dpll |= DPLL_DVO_2X_MODE;
4635
4636         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4637                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639         else
4640                 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642         dpll |= DPLL_VCO_ENABLE;
4643         crtc->config.dpll_hw_state.dpll = dpll;
4644 }
4645
4646 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4647 {
4648         struct drm_device *dev = intel_crtc->base.dev;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         enum pipe pipe = intel_crtc->pipe;
4651         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4652         struct drm_display_mode *adjusted_mode =
4653                 &intel_crtc->config.adjusted_mode;
4654         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4655         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4656
4657         /* We need to be careful not to changed the adjusted mode, for otherwise
4658          * the hw state checker will get angry at the mismatch. */
4659         crtc_vtotal = adjusted_mode->crtc_vtotal;
4660         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4661
4662         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4663                 /* the chip adds 2 halflines automatically */
4664                 crtc_vtotal -= 1;
4665                 crtc_vblank_end -= 1;
4666                 vsyncshift = adjusted_mode->crtc_hsync_start
4667                              - adjusted_mode->crtc_htotal / 2;
4668         } else {
4669                 vsyncshift = 0;
4670         }
4671
4672         if (INTEL_INFO(dev)->gen > 3)
4673                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4674
4675         I915_WRITE(HTOTAL(cpu_transcoder),
4676                    (adjusted_mode->crtc_hdisplay - 1) |
4677                    ((adjusted_mode->crtc_htotal - 1) << 16));
4678         I915_WRITE(HBLANK(cpu_transcoder),
4679                    (adjusted_mode->crtc_hblank_start - 1) |
4680                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4681         I915_WRITE(HSYNC(cpu_transcoder),
4682                    (adjusted_mode->crtc_hsync_start - 1) |
4683                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4684
4685         I915_WRITE(VTOTAL(cpu_transcoder),
4686                    (adjusted_mode->crtc_vdisplay - 1) |
4687                    ((crtc_vtotal - 1) << 16));
4688         I915_WRITE(VBLANK(cpu_transcoder),
4689                    (adjusted_mode->crtc_vblank_start - 1) |
4690                    ((crtc_vblank_end - 1) << 16));
4691         I915_WRITE(VSYNC(cpu_transcoder),
4692                    (adjusted_mode->crtc_vsync_start - 1) |
4693                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4694
4695         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4696          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4697          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4698          * bits. */
4699         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4700             (pipe == PIPE_B || pipe == PIPE_C))
4701                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4702
4703         /* pipesrc controls the size that is scaled from, which should
4704          * always be the user's requested size.
4705          */
4706         I915_WRITE(PIPESRC(pipe),
4707                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4708 }
4709
4710 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4711                                    struct intel_crtc_config *pipe_config)
4712 {
4713         struct drm_device *dev = crtc->base.dev;
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4716         uint32_t tmp;
4717
4718         tmp = I915_READ(HTOTAL(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4721         tmp = I915_READ(HBLANK(cpu_transcoder));
4722         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4723         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4724         tmp = I915_READ(HSYNC(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4727
4728         tmp = I915_READ(VTOTAL(cpu_transcoder));
4729         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4731         tmp = I915_READ(VBLANK(cpu_transcoder));
4732         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4733         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4734         tmp = I915_READ(VSYNC(cpu_transcoder));
4735         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4736         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4737
4738         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4739                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4740                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4741                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4742         }
4743
4744         tmp = I915_READ(PIPESRC(crtc->pipe));
4745         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4746         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4747 }
4748
4749 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4750                                              struct intel_crtc_config *pipe_config)
4751 {
4752         struct drm_crtc *crtc = &intel_crtc->base;
4753
4754         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4755         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4756         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4757         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4758
4759         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4760         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4761         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4762         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4763
4764         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4765
4766         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4767         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4768 }
4769
4770 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4771 {
4772         struct drm_device *dev = intel_crtc->base.dev;
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         uint32_t pipeconf;
4775
4776         pipeconf = 0;
4777
4778         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4779                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4780                  * core speed.
4781                  *
4782                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4783                  * pipe == 0 check?
4784                  */
4785                 if (intel_crtc->config.requested_mode.clock >
4786                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4787                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4788         }
4789
4790         /* only g4x and later have fancy bpc/dither controls */
4791         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4792                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4793                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4794                         pipeconf |= PIPECONF_DITHER_EN |
4795                                     PIPECONF_DITHER_TYPE_SP;
4796
4797                 switch (intel_crtc->config.pipe_bpp) {
4798                 case 18:
4799                         pipeconf |= PIPECONF_6BPC;
4800                         break;
4801                 case 24:
4802                         pipeconf |= PIPECONF_8BPC;
4803                         break;
4804                 case 30:
4805                         pipeconf |= PIPECONF_10BPC;
4806                         break;
4807                 default:
4808                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4809                         BUG();
4810                 }
4811         }
4812
4813         if (HAS_PIPE_CXSR(dev)) {
4814                 if (intel_crtc->lowfreq_avail) {
4815                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4816                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4817                 } else {
4818                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4819                 }
4820         }
4821
4822         if (!IS_GEN2(dev) &&
4823             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4824                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4825         else
4826                 pipeconf |= PIPECONF_PROGRESSIVE;
4827
4828         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4829                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4830
4831         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4832         POSTING_READ(PIPECONF(intel_crtc->pipe));
4833 }
4834
4835 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4836                               int x, int y,
4837                               struct drm_framebuffer *fb)
4838 {
4839         struct drm_device *dev = crtc->dev;
4840         struct drm_i915_private *dev_priv = dev->dev_private;
4841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4843         int pipe = intel_crtc->pipe;
4844         int plane = intel_crtc->plane;
4845         int refclk, num_connectors = 0;
4846         intel_clock_t clock, reduced_clock;
4847         u32 dspcntr;
4848         bool ok, has_reduced_clock = false;
4849         bool is_lvds = false;
4850         struct intel_encoder *encoder;
4851         const intel_limit_t *limit;
4852         int ret;
4853
4854         for_each_encoder_on_crtc(dev, crtc, encoder) {
4855                 switch (encoder->type) {
4856                 case INTEL_OUTPUT_LVDS:
4857                         is_lvds = true;
4858                         break;
4859                 }
4860
4861                 num_connectors++;
4862         }
4863
4864         refclk = i9xx_get_refclk(crtc, num_connectors);
4865
4866         /*
4867          * Returns a set of divisors for the desired target clock with the given
4868          * refclk, or FALSE.  The returned values represent the clock equation:
4869          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4870          */
4871         limit = intel_limit(crtc, refclk);
4872         ok = dev_priv->display.find_dpll(limit, crtc,
4873                                          intel_crtc->config.port_clock,
4874                                          refclk, NULL, &clock);
4875         if (!ok && !intel_crtc->config.clock_set) {
4876                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4877                 return -EINVAL;
4878         }
4879
4880         /* Ensure that the cursor is valid for the new mode before changing... */
4881         intel_crtc_update_cursor(crtc, true);
4882
4883         if (is_lvds && dev_priv->lvds_downclock_avail) {
4884                 /*
4885                  * Ensure we match the reduced clock's P to the target clock.
4886                  * If the clocks don't match, we can't switch the display clock
4887                  * by using the FP0/FP1. In such case we will disable the LVDS
4888                  * downclock feature.
4889                 */
4890                 has_reduced_clock =
4891                         dev_priv->display.find_dpll(limit, crtc,
4892                                                     dev_priv->lvds_downclock,
4893                                                     refclk, &clock,
4894                                                     &reduced_clock);
4895         }
4896         /* Compat-code for transition, will disappear. */
4897         if (!intel_crtc->config.clock_set) {
4898                 intel_crtc->config.dpll.n = clock.n;
4899                 intel_crtc->config.dpll.m1 = clock.m1;
4900                 intel_crtc->config.dpll.m2 = clock.m2;
4901                 intel_crtc->config.dpll.p1 = clock.p1;
4902                 intel_crtc->config.dpll.p2 = clock.p2;
4903         }
4904
4905         if (IS_GEN2(dev))
4906                 i8xx_update_pll(intel_crtc,
4907                                 has_reduced_clock ? &reduced_clock : NULL,
4908                                 num_connectors);
4909         else if (IS_VALLEYVIEW(dev))
4910                 vlv_update_pll(intel_crtc);
4911         else
4912                 i9xx_update_pll(intel_crtc,
4913                                 has_reduced_clock ? &reduced_clock : NULL,
4914                                 num_connectors);
4915
4916         /* Set up the display plane register */
4917         dspcntr = DISPPLANE_GAMMA_ENABLE;
4918
4919         if (!IS_VALLEYVIEW(dev)) {
4920                 if (pipe == 0)
4921                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4922                 else
4923                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4924         }
4925
4926         intel_set_pipe_timings(intel_crtc);
4927
4928         /* pipesrc and dspsize control the size that is scaled from,
4929          * which should always be the user's requested size.
4930          */
4931         I915_WRITE(DSPSIZE(plane),
4932                    ((mode->vdisplay - 1) << 16) |
4933                    (mode->hdisplay - 1));
4934         I915_WRITE(DSPPOS(plane), 0);
4935
4936         i9xx_set_pipeconf(intel_crtc);
4937
4938         I915_WRITE(DSPCNTR(plane), dspcntr);
4939         POSTING_READ(DSPCNTR(plane));
4940
4941         ret = intel_pipe_set_base(crtc, x, y, fb);
4942
4943         intel_update_watermarks(dev);
4944
4945         return ret;
4946 }
4947
4948 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4949                                  struct intel_crtc_config *pipe_config)
4950 {
4951         struct drm_device *dev = crtc->base.dev;
4952         struct drm_i915_private *dev_priv = dev->dev_private;
4953         uint32_t tmp;
4954
4955         tmp = I915_READ(PFIT_CONTROL);
4956         if (!(tmp & PFIT_ENABLE))
4957                 return;
4958
4959         /* Check whether the pfit is attached to our pipe. */
4960         if (INTEL_INFO(dev)->gen < 4) {
4961                 if (crtc->pipe != PIPE_B)
4962                         return;
4963         } else {
4964                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4965                         return;
4966         }
4967
4968         pipe_config->gmch_pfit.control = tmp;
4969         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4970         if (INTEL_INFO(dev)->gen < 5)
4971                 pipe_config->gmch_pfit.lvds_border_bits =
4972                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4973 }
4974
4975 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4976                                  struct intel_crtc_config *pipe_config)
4977 {
4978         struct drm_device *dev = crtc->base.dev;
4979         struct drm_i915_private *dev_priv = dev->dev_private;
4980         uint32_t tmp;
4981
4982         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4983         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4984
4985         tmp = I915_READ(PIPECONF(crtc->pipe));
4986         if (!(tmp & PIPECONF_ENABLE))
4987                 return false;
4988
4989         intel_get_pipe_timings(crtc, pipe_config);
4990
4991         i9xx_get_pfit_config(crtc, pipe_config);
4992
4993         if (INTEL_INFO(dev)->gen >= 4) {
4994                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4995                 pipe_config->pixel_multiplier =
4996                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4997                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4998                 pipe_config->dpll_hw_state.dpll_md = tmp;
4999         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5000                 tmp = I915_READ(DPLL(crtc->pipe));
5001                 pipe_config->pixel_multiplier =
5002                         ((tmp & SDVO_MULTIPLIER_MASK)
5003                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5004         } else {
5005                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5006                  * port and will be fixed up in the encoder->get_config
5007                  * function. */
5008                 pipe_config->pixel_multiplier = 1;
5009         }
5010         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5011         if (!IS_VALLEYVIEW(dev)) {
5012                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5013                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5014         } else {
5015                 /* Mask out read-only status bits. */
5016                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5017                                                      DPLL_PORTC_READY_MASK |
5018                                                      DPLL_PORTB_READY_MASK);
5019         }
5020
5021         return true;
5022 }
5023
5024 static void ironlake_init_pch_refclk(struct drm_device *dev)
5025 {
5026         struct drm_i915_private *dev_priv = dev->dev_private;
5027         struct drm_mode_config *mode_config = &dev->mode_config;
5028         struct intel_encoder *encoder;
5029         u32 val, final;
5030         bool has_lvds = false;
5031         bool has_cpu_edp = false;
5032         bool has_panel = false;
5033         bool has_ck505 = false;
5034         bool can_ssc = false;
5035
5036         /* We need to take the global config into account */
5037         list_for_each_entry(encoder, &mode_config->encoder_list,
5038                             base.head) {
5039                 switch (encoder->type) {
5040                 case INTEL_OUTPUT_LVDS:
5041                         has_panel = true;
5042                         has_lvds = true;
5043                         break;
5044                 case INTEL_OUTPUT_EDP:
5045                         has_panel = true;
5046                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5047                                 has_cpu_edp = true;
5048                         break;
5049                 }
5050         }
5051
5052         if (HAS_PCH_IBX(dev)) {
5053                 has_ck505 = dev_priv->vbt.display_clock_mode;
5054                 can_ssc = has_ck505;
5055         } else {
5056                 has_ck505 = false;
5057                 can_ssc = true;
5058         }
5059
5060         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5061                       has_panel, has_lvds, has_ck505);
5062
5063         /* Ironlake: try to setup display ref clock before DPLL
5064          * enabling. This is only under driver's control after
5065          * PCH B stepping, previous chipset stepping should be
5066          * ignoring this setting.
5067          */
5068         val = I915_READ(PCH_DREF_CONTROL);
5069
5070         /* As we must carefully and slowly disable/enable each source in turn,
5071          * compute the final state we want first and check if we need to
5072          * make any changes at all.
5073          */
5074         final = val;
5075         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5076         if (has_ck505)
5077                 final |= DREF_NONSPREAD_CK505_ENABLE;
5078         else
5079                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5080
5081         final &= ~DREF_SSC_SOURCE_MASK;
5082         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5083         final &= ~DREF_SSC1_ENABLE;
5084
5085         if (has_panel) {
5086                 final |= DREF_SSC_SOURCE_ENABLE;
5087
5088                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089                         final |= DREF_SSC1_ENABLE;
5090
5091                 if (has_cpu_edp) {
5092                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5093                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5094                         else
5095                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5096                 } else
5097                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098         } else {
5099                 final |= DREF_SSC_SOURCE_DISABLE;
5100                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101         }
5102
5103         if (final == val)
5104                 return;
5105
5106         /* Always enable nonspread source */
5107         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5108
5109         if (has_ck505)
5110                 val |= DREF_NONSPREAD_CK505_ENABLE;
5111         else
5112                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5113
5114         if (has_panel) {
5115                 val &= ~DREF_SSC_SOURCE_MASK;
5116                 val |= DREF_SSC_SOURCE_ENABLE;
5117
5118                 /* SSC must be turned on before enabling the CPU output  */
5119                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5120                         DRM_DEBUG_KMS("Using SSC on panel\n");
5121                         val |= DREF_SSC1_ENABLE;
5122                 } else
5123                         val &= ~DREF_SSC1_ENABLE;
5124
5125                 /* Get SSC going before enabling the outputs */
5126                 I915_WRITE(PCH_DREF_CONTROL, val);
5127                 POSTING_READ(PCH_DREF_CONTROL);
5128                 udelay(200);
5129
5130                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5131
5132                 /* Enable CPU source on CPU attached eDP */
5133                 if (has_cpu_edp) {
5134                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5135                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5136                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5137                         }
5138                         else
5139                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5140                 } else
5141                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5142
5143                 I915_WRITE(PCH_DREF_CONTROL, val);
5144                 POSTING_READ(PCH_DREF_CONTROL);
5145                 udelay(200);
5146         } else {
5147                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5148
5149                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5150
5151                 /* Turn off CPU output */
5152                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5153
5154                 I915_WRITE(PCH_DREF_CONTROL, val);
5155                 POSTING_READ(PCH_DREF_CONTROL);
5156                 udelay(200);
5157
5158                 /* Turn off the SSC source */
5159                 val &= ~DREF_SSC_SOURCE_MASK;
5160                 val |= DREF_SSC_SOURCE_DISABLE;
5161
5162                 /* Turn off SSC1 */
5163                 val &= ~DREF_SSC1_ENABLE;
5164
5165                 I915_WRITE(PCH_DREF_CONTROL, val);
5166                 POSTING_READ(PCH_DREF_CONTROL);
5167                 udelay(200);
5168         }
5169
5170         BUG_ON(val != final);
5171 }
5172
5173 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5174 {
5175         uint32_t tmp;
5176
5177         tmp = I915_READ(SOUTH_CHICKEN2);
5178         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5179         I915_WRITE(SOUTH_CHICKEN2, tmp);
5180
5181         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5182                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5183                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5184
5185         tmp = I915_READ(SOUTH_CHICKEN2);
5186         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5187         I915_WRITE(SOUTH_CHICKEN2, tmp);
5188
5189         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5190                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5191                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5192 }
5193
5194 /* WaMPhyProgramming:hsw */
5195 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5196 {
5197         uint32_t tmp;
5198
5199         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5200         tmp &= ~(0xFF << 24);
5201         tmp |= (0x12 << 24);
5202         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5203
5204         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5205         tmp |= (1 << 11);
5206         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5207
5208         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5209         tmp |= (1 << 11);
5210         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5211
5212         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5213         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5214         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5215
5216         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5217         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5218         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5219
5220         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5221         tmp &= ~(7 << 13);
5222         tmp |= (5 << 13);
5223         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5224
5225         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5226         tmp &= ~(7 << 13);
5227         tmp |= (5 << 13);
5228         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5229
5230         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5231         tmp &= ~0xFF;
5232         tmp |= 0x1C;
5233         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5234
5235         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5236         tmp &= ~0xFF;
5237         tmp |= 0x1C;
5238         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5239
5240         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5241         tmp &= ~(0xFF << 16);
5242         tmp |= (0x1C << 16);
5243         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5244
5245         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5246         tmp &= ~(0xFF << 16);
5247         tmp |= (0x1C << 16);
5248         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5249
5250         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5251         tmp |= (1 << 27);
5252         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5255         tmp |= (1 << 27);
5256         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5257
5258         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5259         tmp &= ~(0xF << 28);
5260         tmp |= (4 << 28);
5261         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5262
5263         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5264         tmp &= ~(0xF << 28);
5265         tmp |= (4 << 28);
5266         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5267 }
5268
5269 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5270  * Programming" based on the parameters passed:
5271  * - Sequence to enable CLKOUT_DP
5272  * - Sequence to enable CLKOUT_DP without spread
5273  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5274  */
5275 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5276                                  bool with_fdi)
5277 {
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279         uint32_t reg, tmp;
5280
5281         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5282                 with_spread = true;
5283         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5284                  with_fdi, "LP PCH doesn't have FDI\n"))
5285                 with_fdi = false;
5286
5287         mutex_lock(&dev_priv->dpio_lock);
5288
5289         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5290         tmp &= ~SBI_SSCCTL_DISABLE;
5291         tmp |= SBI_SSCCTL_PATHALT;
5292         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5293
5294         udelay(24);
5295
5296         if (with_spread) {
5297                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5298                 tmp &= ~SBI_SSCCTL_PATHALT;
5299                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5300
5301                 if (with_fdi) {
5302                         lpt_reset_fdi_mphy(dev_priv);
5303                         lpt_program_fdi_mphy(dev_priv);
5304                 }
5305         }
5306
5307         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5308                SBI_GEN0 : SBI_DBUFF0;
5309         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5310         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5311         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5312
5313         mutex_unlock(&dev_priv->dpio_lock);
5314 }
5315
5316 /* Sequence to disable CLKOUT_DP */
5317 static void lpt_disable_clkout_dp(struct drm_device *dev)
5318 {
5319         struct drm_i915_private *dev_priv = dev->dev_private;
5320         uint32_t reg, tmp;
5321
5322         mutex_lock(&dev_priv->dpio_lock);
5323
5324         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5325                SBI_GEN0 : SBI_DBUFF0;
5326         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5327         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5328         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5329
5330         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5331         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5332                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5333                         tmp |= SBI_SSCCTL_PATHALT;
5334                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5335                         udelay(32);
5336                 }
5337                 tmp |= SBI_SSCCTL_DISABLE;
5338                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5339         }
5340
5341         mutex_unlock(&dev_priv->dpio_lock);
5342 }
5343
5344 static void lpt_init_pch_refclk(struct drm_device *dev)
5345 {
5346         struct drm_mode_config *mode_config = &dev->mode_config;
5347         struct intel_encoder *encoder;
5348         bool has_vga = false;
5349
5350         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5351                 switch (encoder->type) {
5352                 case INTEL_OUTPUT_ANALOG:
5353                         has_vga = true;
5354                         break;
5355                 }
5356         }
5357
5358         if (has_vga)
5359                 lpt_enable_clkout_dp(dev, true, true);
5360         else
5361                 lpt_disable_clkout_dp(dev);
5362 }
5363
5364 /*
5365  * Initialize reference clocks when the driver loads
5366  */
5367 void intel_init_pch_refclk(struct drm_device *dev)
5368 {
5369         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5370                 ironlake_init_pch_refclk(dev);
5371         else if (HAS_PCH_LPT(dev))
5372                 lpt_init_pch_refclk(dev);
5373 }
5374
5375 static int ironlake_get_refclk(struct drm_crtc *crtc)
5376 {
5377         struct drm_device *dev = crtc->dev;
5378         struct drm_i915_private *dev_priv = dev->dev_private;
5379         struct intel_encoder *encoder;
5380         int num_connectors = 0;
5381         bool is_lvds = false;
5382
5383         for_each_encoder_on_crtc(dev, crtc, encoder) {
5384                 switch (encoder->type) {
5385                 case INTEL_OUTPUT_LVDS:
5386                         is_lvds = true;
5387                         break;
5388                 }
5389                 num_connectors++;
5390         }
5391
5392         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5393                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5394                               dev_priv->vbt.lvds_ssc_freq);
5395                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5396         }
5397
5398         return 120000;
5399 }
5400
5401 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5402 {
5403         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5405         int pipe = intel_crtc->pipe;
5406         uint32_t val;
5407
5408         val = 0;
5409
5410         switch (intel_crtc->config.pipe_bpp) {
5411         case 18:
5412                 val |= PIPECONF_6BPC;
5413                 break;
5414         case 24:
5415                 val |= PIPECONF_8BPC;
5416                 break;
5417         case 30:
5418                 val |= PIPECONF_10BPC;
5419                 break;
5420         case 36:
5421                 val |= PIPECONF_12BPC;
5422                 break;
5423         default:
5424                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5425                 BUG();
5426         }
5427
5428         if (intel_crtc->config.dither)
5429                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5430
5431         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5432                 val |= PIPECONF_INTERLACED_ILK;
5433         else
5434                 val |= PIPECONF_PROGRESSIVE;
5435
5436         if (intel_crtc->config.limited_color_range)
5437                 val |= PIPECONF_COLOR_RANGE_SELECT;
5438
5439         I915_WRITE(PIPECONF(pipe), val);
5440         POSTING_READ(PIPECONF(pipe));
5441 }
5442
5443 /*
5444  * Set up the pipe CSC unit.
5445  *
5446  * Currently only full range RGB to limited range RGB conversion
5447  * is supported, but eventually this should handle various
5448  * RGB<->YCbCr scenarios as well.
5449  */
5450 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5451 {
5452         struct drm_device *dev = crtc->dev;
5453         struct drm_i915_private *dev_priv = dev->dev_private;
5454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455         int pipe = intel_crtc->pipe;
5456         uint16_t coeff = 0x7800; /* 1.0 */
5457
5458         /*
5459          * TODO: Check what kind of values actually come out of the pipe
5460          * with these coeff/postoff values and adjust to get the best
5461          * accuracy. Perhaps we even need to take the bpc value into
5462          * consideration.
5463          */
5464
5465         if (intel_crtc->config.limited_color_range)
5466                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5467
5468         /*
5469          * GY/GU and RY/RU should be the other way around according
5470          * to BSpec, but reality doesn't agree. Just set them up in
5471          * a way that results in the correct picture.
5472          */
5473         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5474         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5475
5476         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5477         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5478
5479         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5480         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5481
5482         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5483         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5484         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5485
5486         if (INTEL_INFO(dev)->gen > 6) {
5487                 uint16_t postoff = 0;
5488
5489                 if (intel_crtc->config.limited_color_range)
5490                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5491
5492                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5493                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5494                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5495
5496                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5497         } else {
5498                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5499
5500                 if (intel_crtc->config.limited_color_range)
5501                         mode |= CSC_BLACK_SCREEN_OFFSET;
5502
5503                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5504         }
5505 }
5506
5507 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5508 {
5509         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5511         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5512         uint32_t val;
5513
5514         val = 0;
5515
5516         if (intel_crtc->config.dither)
5517                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5518
5519         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5520                 val |= PIPECONF_INTERLACED_ILK;
5521         else
5522                 val |= PIPECONF_PROGRESSIVE;
5523
5524         I915_WRITE(PIPECONF(cpu_transcoder), val);
5525         POSTING_READ(PIPECONF(cpu_transcoder));
5526
5527         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5528         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5529 }
5530
5531 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5532                                     intel_clock_t *clock,
5533                                     bool *has_reduced_clock,
5534                                     intel_clock_t *reduced_clock)
5535 {
5536         struct drm_device *dev = crtc->dev;
5537         struct drm_i915_private *dev_priv = dev->dev_private;
5538         struct intel_encoder *intel_encoder;
5539         int refclk;
5540         const intel_limit_t *limit;
5541         bool ret, is_lvds = false;
5542
5543         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5544                 switch (intel_encoder->type) {
5545                 case INTEL_OUTPUT_LVDS:
5546                         is_lvds = true;
5547                         break;
5548                 }
5549         }
5550
5551         refclk = ironlake_get_refclk(crtc);
5552
5553         /*
5554          * Returns a set of divisors for the desired target clock with the given
5555          * refclk, or FALSE.  The returned values represent the clock equation:
5556          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5557          */
5558         limit = intel_limit(crtc, refclk);
5559         ret = dev_priv->display.find_dpll(limit, crtc,
5560                                           to_intel_crtc(crtc)->config.port_clock,
5561                                           refclk, NULL, clock);
5562         if (!ret)
5563                 return false;
5564
5565         if (is_lvds && dev_priv->lvds_downclock_avail) {
5566                 /*
5567                  * Ensure we match the reduced clock's P to the target clock.
5568                  * If the clocks don't match, we can't switch the display clock
5569                  * by using the FP0/FP1. In such case we will disable the LVDS
5570                  * downclock feature.
5571                 */
5572                 *has_reduced_clock =
5573                         dev_priv->display.find_dpll(limit, crtc,
5574                                                     dev_priv->lvds_downclock,
5575                                                     refclk, clock,
5576                                                     reduced_clock);
5577         }
5578
5579         return true;
5580 }
5581
5582 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5583 {
5584         struct drm_i915_private *dev_priv = dev->dev_private;
5585         uint32_t temp;
5586
5587         temp = I915_READ(SOUTH_CHICKEN1);
5588         if (temp & FDI_BC_BIFURCATION_SELECT)
5589                 return;
5590
5591         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5592         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5593
5594         temp |= FDI_BC_BIFURCATION_SELECT;
5595         DRM_DEBUG_KMS("enabling fdi C rx\n");
5596         I915_WRITE(SOUTH_CHICKEN1, temp);
5597         POSTING_READ(SOUTH_CHICKEN1);
5598 }
5599
5600 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5601 {
5602         struct drm_device *dev = intel_crtc->base.dev;
5603         struct drm_i915_private *dev_priv = dev->dev_private;
5604
5605         switch (intel_crtc->pipe) {
5606         case PIPE_A:
5607                 break;
5608         case PIPE_B:
5609                 if (intel_crtc->config.fdi_lanes > 2)
5610                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5611                 else
5612                         cpt_enable_fdi_bc_bifurcation(dev);
5613
5614                 break;
5615         case PIPE_C:
5616                 cpt_enable_fdi_bc_bifurcation(dev);
5617
5618                 break;
5619         default:
5620                 BUG();
5621         }
5622 }
5623
5624 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5625 {
5626         /*
5627          * Account for spread spectrum to avoid
5628          * oversubscribing the link. Max center spread
5629          * is 2.5%; use 5% for safety's sake.
5630          */
5631         u32 bps = target_clock * bpp * 21 / 20;
5632         return bps / (link_bw * 8) + 1;
5633 }
5634
5635 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5636 {
5637         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5638 }
5639
5640 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5641                                       u32 *fp,
5642                                       intel_clock_t *reduced_clock, u32 *fp2)
5643 {
5644         struct drm_crtc *crtc = &intel_crtc->base;
5645         struct drm_device *dev = crtc->dev;
5646         struct drm_i915_private *dev_priv = dev->dev_private;
5647         struct intel_encoder *intel_encoder;
5648         uint32_t dpll;
5649         int factor, num_connectors = 0;
5650         bool is_lvds = false, is_sdvo = false;
5651
5652         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5653                 switch (intel_encoder->type) {
5654                 case INTEL_OUTPUT_LVDS:
5655                         is_lvds = true;
5656                         break;
5657                 case INTEL_OUTPUT_SDVO:
5658                 case INTEL_OUTPUT_HDMI:
5659                         is_sdvo = true;
5660                         break;
5661                 }
5662
5663                 num_connectors++;
5664         }
5665
5666         /* Enable autotuning of the PLL clock (if permissible) */
5667         factor = 21;
5668         if (is_lvds) {
5669                 if ((intel_panel_use_ssc(dev_priv) &&
5670                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5671                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5672                         factor = 25;
5673         } else if (intel_crtc->config.sdvo_tv_clock)
5674                 factor = 20;
5675
5676         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5677                 *fp |= FP_CB_TUNE;
5678
5679         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5680                 *fp2 |= FP_CB_TUNE;
5681
5682         dpll = 0;
5683
5684         if (is_lvds)
5685                 dpll |= DPLLB_MODE_LVDS;
5686         else
5687                 dpll |= DPLLB_MODE_DAC_SERIAL;
5688
5689         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5690                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5691
5692         if (is_sdvo)
5693                 dpll |= DPLL_SDVO_HIGH_SPEED;
5694         if (intel_crtc->config.has_dp_encoder)
5695                 dpll |= DPLL_SDVO_HIGH_SPEED;
5696
5697         /* compute bitmask from p1 value */
5698         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5699         /* also FPA1 */
5700         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5701
5702         switch (intel_crtc->config.dpll.p2) {
5703         case 5:
5704                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5705                 break;
5706         case 7:
5707                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5708                 break;
5709         case 10:
5710                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5711                 break;
5712         case 14:
5713                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5714                 break;
5715         }
5716
5717         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5718                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5719         else
5720                 dpll |= PLL_REF_INPUT_DREFCLK;
5721
5722         return dpll | DPLL_VCO_ENABLE;
5723 }
5724
5725 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5726                                   int x, int y,
5727                                   struct drm_framebuffer *fb)
5728 {
5729         struct drm_device *dev = crtc->dev;
5730         struct drm_i915_private *dev_priv = dev->dev_private;
5731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5732         int pipe = intel_crtc->pipe;
5733         int plane = intel_crtc->plane;
5734         int num_connectors = 0;
5735         intel_clock_t clock, reduced_clock;
5736         u32 dpll = 0, fp = 0, fp2 = 0;
5737         bool ok, has_reduced_clock = false;
5738         bool is_lvds = false;
5739         struct intel_encoder *encoder;
5740         struct intel_shared_dpll *pll;
5741         int ret;
5742
5743         for_each_encoder_on_crtc(dev, crtc, encoder) {
5744                 switch (encoder->type) {
5745                 case INTEL_OUTPUT_LVDS:
5746                         is_lvds = true;
5747                         break;
5748                 }
5749
5750                 num_connectors++;
5751         }
5752
5753         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5754              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5755
5756         ok = ironlake_compute_clocks(crtc, &clock,
5757                                      &has_reduced_clock, &reduced_clock);
5758         if (!ok && !intel_crtc->config.clock_set) {
5759                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5760                 return -EINVAL;
5761         }
5762         /* Compat-code for transition, will disappear. */
5763         if (!intel_crtc->config.clock_set) {
5764                 intel_crtc->config.dpll.n = clock.n;
5765                 intel_crtc->config.dpll.m1 = clock.m1;
5766                 intel_crtc->config.dpll.m2 = clock.m2;
5767                 intel_crtc->config.dpll.p1 = clock.p1;
5768                 intel_crtc->config.dpll.p2 = clock.p2;
5769         }
5770
5771         /* Ensure that the cursor is valid for the new mode before changing... */
5772         intel_crtc_update_cursor(crtc, true);
5773
5774         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5775         if (intel_crtc->config.has_pch_encoder) {
5776                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5777                 if (has_reduced_clock)
5778                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5779
5780                 dpll = ironlake_compute_dpll(intel_crtc,
5781                                              &fp, &reduced_clock,
5782                                              has_reduced_clock ? &fp2 : NULL);
5783
5784                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5785                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5786                 if (has_reduced_clock)
5787                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5788                 else
5789                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5790
5791                 pll = intel_get_shared_dpll(intel_crtc);
5792                 if (pll == NULL) {
5793                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5794                                          pipe_name(pipe));
5795                         return -EINVAL;
5796                 }
5797         } else
5798                 intel_put_shared_dpll(intel_crtc);
5799
5800         if (intel_crtc->config.has_dp_encoder)
5801                 intel_dp_set_m_n(intel_crtc);
5802
5803         if (is_lvds && has_reduced_clock && i915_powersave)
5804                 intel_crtc->lowfreq_avail = true;
5805         else
5806                 intel_crtc->lowfreq_avail = false;
5807
5808         if (intel_crtc->config.has_pch_encoder) {
5809                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5810
5811         }
5812
5813         intel_set_pipe_timings(intel_crtc);
5814
5815         if (intel_crtc->config.has_pch_encoder) {
5816                 intel_cpu_transcoder_set_m_n(intel_crtc,
5817                                              &intel_crtc->config.fdi_m_n);
5818         }
5819
5820         if (IS_IVYBRIDGE(dev))
5821                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5822
5823         ironlake_set_pipeconf(crtc);
5824
5825         /* Set up the display plane register */
5826         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5827         POSTING_READ(DSPCNTR(plane));
5828
5829         ret = intel_pipe_set_base(crtc, x, y, fb);
5830
5831         intel_update_watermarks(dev);
5832
5833         return ret;
5834 }
5835
5836 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5837                                         struct intel_crtc_config *pipe_config)
5838 {
5839         struct drm_device *dev = crtc->base.dev;
5840         struct drm_i915_private *dev_priv = dev->dev_private;
5841         enum transcoder transcoder = pipe_config->cpu_transcoder;
5842
5843         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5844         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5845         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5846                                         & ~TU_SIZE_MASK;
5847         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5848         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5849                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5850 }
5851
5852 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5853                                      struct intel_crtc_config *pipe_config)
5854 {
5855         struct drm_device *dev = crtc->base.dev;
5856         struct drm_i915_private *dev_priv = dev->dev_private;
5857         uint32_t tmp;
5858
5859         tmp = I915_READ(PF_CTL(crtc->pipe));
5860
5861         if (tmp & PF_ENABLE) {
5862                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5863                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5864
5865                 /* We currently do not free assignements of panel fitters on
5866                  * ivb/hsw (since we don't use the higher upscaling modes which
5867                  * differentiates them) so just WARN about this case for now. */
5868                 if (IS_GEN7(dev)) {
5869                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5870                                 PF_PIPE_SEL_IVB(crtc->pipe));
5871                 }
5872         }
5873 }
5874
5875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5876                                      struct intel_crtc_config *pipe_config)
5877 {
5878         struct drm_device *dev = crtc->base.dev;
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         uint32_t tmp;
5881
5882         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5883         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5884
5885         tmp = I915_READ(PIPECONF(crtc->pipe));
5886         if (!(tmp & PIPECONF_ENABLE))
5887                 return false;
5888
5889         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5890                 struct intel_shared_dpll *pll;
5891
5892                 pipe_config->has_pch_encoder = true;
5893
5894                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5895                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5896                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5897
5898                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5899
5900                 if (HAS_PCH_IBX(dev_priv->dev)) {
5901                         pipe_config->shared_dpll =
5902                                 (enum intel_dpll_id) crtc->pipe;
5903                 } else {
5904                         tmp = I915_READ(PCH_DPLL_SEL);
5905                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5906                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5907                         else
5908                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5909                 }
5910
5911                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5912
5913                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5914                                            &pipe_config->dpll_hw_state));
5915
5916                 tmp = pipe_config->dpll_hw_state.dpll;
5917                 pipe_config->pixel_multiplier =
5918                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5919                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5920         } else {
5921                 pipe_config->pixel_multiplier = 1;
5922         }
5923
5924         intel_get_pipe_timings(crtc, pipe_config);
5925
5926         ironlake_get_pfit_config(crtc, pipe_config);
5927
5928         return true;
5929 }
5930
5931 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5932 {
5933         struct drm_device *dev = dev_priv->dev;
5934         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5935         struct intel_crtc *crtc;
5936         unsigned long irqflags;
5937         uint32_t val, pch_hpd_mask;
5938
5939         pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5940         if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5941                 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5942
5943         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5944                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5945                      pipe_name(crtc->pipe));
5946
5947         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5948         WARN(plls->spll_refcount, "SPLL enabled\n");
5949         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5950         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5951         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5952         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5953              "CPU PWM1 enabled\n");
5954         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5955              "CPU PWM2 enabled\n");
5956         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5957              "PCH PWM1 enabled\n");
5958         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5959              "Utility pin enabled\n");
5960         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5961
5962         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5963         val = I915_READ(DEIMR);
5964         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5965              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5966         val = I915_READ(SDEIMR);
5967         WARN((val & ~pch_hpd_mask) != val,
5968              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5969         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5970 }
5971
5972 /*
5973  * This function implements pieces of two sequences from BSpec:
5974  * - Sequence for display software to disable LCPLL
5975  * - Sequence for display software to allow package C8+
5976  * The steps implemented here are just the steps that actually touch the LCPLL
5977  * register. Callers should take care of disabling all the display engine
5978  * functions, doing the mode unset, fixing interrupts, etc.
5979  */
5980 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5981                        bool switch_to_fclk, bool allow_power_down)
5982 {
5983         uint32_t val;
5984
5985         assert_can_disable_lcpll(dev_priv);
5986
5987         val = I915_READ(LCPLL_CTL);
5988
5989         if (switch_to_fclk) {
5990                 val |= LCPLL_CD_SOURCE_FCLK;
5991                 I915_WRITE(LCPLL_CTL, val);
5992
5993                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5994                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
5995                         DRM_ERROR("Switching to FCLK failed\n");
5996
5997                 val = I915_READ(LCPLL_CTL);
5998         }
5999
6000         val |= LCPLL_PLL_DISABLE;
6001         I915_WRITE(LCPLL_CTL, val);
6002         POSTING_READ(LCPLL_CTL);
6003
6004         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6005                 DRM_ERROR("LCPLL still locked\n");
6006
6007         val = I915_READ(D_COMP);
6008         val |= D_COMP_COMP_DISABLE;
6009         I915_WRITE(D_COMP, val);
6010         POSTING_READ(D_COMP);
6011         ndelay(100);
6012
6013         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6014                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6015
6016         if (allow_power_down) {
6017                 val = I915_READ(LCPLL_CTL);
6018                 val |= LCPLL_POWER_DOWN_ALLOW;
6019                 I915_WRITE(LCPLL_CTL, val);
6020                 POSTING_READ(LCPLL_CTL);
6021         }
6022 }
6023
6024 /*
6025  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6026  * source.
6027  */
6028 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6029 {
6030         uint32_t val;
6031
6032         val = I915_READ(LCPLL_CTL);
6033
6034         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6035                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6036                 return;
6037
6038         if (val & LCPLL_POWER_DOWN_ALLOW) {
6039                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6040                 I915_WRITE(LCPLL_CTL, val);
6041         }
6042
6043         val = I915_READ(D_COMP);
6044         val |= D_COMP_COMP_FORCE;
6045         val &= ~D_COMP_COMP_DISABLE;
6046         I915_WRITE(D_COMP, val);
6047         I915_READ(D_COMP);
6048
6049         val = I915_READ(LCPLL_CTL);
6050         val &= ~LCPLL_PLL_DISABLE;
6051         I915_WRITE(LCPLL_CTL, val);
6052
6053         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6054                 DRM_ERROR("LCPLL not locked yet\n");
6055
6056         if (val & LCPLL_CD_SOURCE_FCLK) {
6057                 val = I915_READ(LCPLL_CTL);
6058                 val &= ~LCPLL_CD_SOURCE_FCLK;
6059                 I915_WRITE(LCPLL_CTL, val);
6060
6061                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6062                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6063                         DRM_ERROR("Switching back to LCPLL failed\n");
6064         }
6065 }
6066
6067 static void haswell_modeset_global_resources(struct drm_device *dev)
6068 {
6069         bool enable = false;
6070         struct intel_crtc *crtc;
6071
6072         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6073                 if (!crtc->base.enabled)
6074                         continue;
6075
6076                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6077                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6078                         enable = true;
6079         }
6080
6081         intel_set_power_well(dev, enable);
6082 }
6083
6084 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6085                                  int x, int y,
6086                                  struct drm_framebuffer *fb)
6087 {
6088         struct drm_device *dev = crtc->dev;
6089         struct drm_i915_private *dev_priv = dev->dev_private;
6090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6091         int plane = intel_crtc->plane;
6092         int ret;
6093
6094         if (!intel_ddi_pll_mode_set(crtc))
6095                 return -EINVAL;
6096
6097         /* Ensure that the cursor is valid for the new mode before changing... */
6098         intel_crtc_update_cursor(crtc, true);
6099
6100         if (intel_crtc->config.has_dp_encoder)
6101                 intel_dp_set_m_n(intel_crtc);
6102
6103         intel_crtc->lowfreq_avail = false;
6104
6105         intel_set_pipe_timings(intel_crtc);
6106
6107         if (intel_crtc->config.has_pch_encoder) {
6108                 intel_cpu_transcoder_set_m_n(intel_crtc,
6109                                              &intel_crtc->config.fdi_m_n);
6110         }
6111
6112         haswell_set_pipeconf(crtc);
6113
6114         intel_set_pipe_csc(crtc);
6115
6116         /* Set up the display plane register */
6117         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6118         POSTING_READ(DSPCNTR(plane));
6119
6120         ret = intel_pipe_set_base(crtc, x, y, fb);
6121
6122         intel_update_watermarks(dev);
6123
6124         return ret;
6125 }
6126
6127 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6128                                     struct intel_crtc_config *pipe_config)
6129 {
6130         struct drm_device *dev = crtc->base.dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         enum intel_display_power_domain pfit_domain;
6133         uint32_t tmp;
6134
6135         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6136         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6137
6138         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6139         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6140                 enum pipe trans_edp_pipe;
6141                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6142                 default:
6143                         WARN(1, "unknown pipe linked to edp transcoder\n");
6144                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6145                 case TRANS_DDI_EDP_INPUT_A_ON:
6146                         trans_edp_pipe = PIPE_A;
6147                         break;
6148                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6149                         trans_edp_pipe = PIPE_B;
6150                         break;
6151                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6152                         trans_edp_pipe = PIPE_C;
6153                         break;
6154                 }
6155
6156                 if (trans_edp_pipe == crtc->pipe)
6157                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6158         }
6159
6160         if (!intel_display_power_enabled(dev,
6161                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6162                 return false;
6163
6164         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6165         if (!(tmp & PIPECONF_ENABLE))
6166                 return false;
6167
6168         /*
6169          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6170          * DDI E. So just check whether this pipe is wired to DDI E and whether
6171          * the PCH transcoder is on.
6172          */
6173         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6174         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6175             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6176                 pipe_config->has_pch_encoder = true;
6177
6178                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6179                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6180                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6181
6182                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6183         }
6184
6185         intel_get_pipe_timings(crtc, pipe_config);
6186
6187         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6188         if (intel_display_power_enabled(dev, pfit_domain))
6189                 ironlake_get_pfit_config(crtc, pipe_config);
6190
6191         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6192                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6193
6194         pipe_config->pixel_multiplier = 1;
6195
6196         return true;
6197 }
6198
6199 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6200                                int x, int y,
6201                                struct drm_framebuffer *fb)
6202 {
6203         struct drm_device *dev = crtc->dev;
6204         struct drm_i915_private *dev_priv = dev->dev_private;
6205         struct intel_encoder *encoder;
6206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6208         int pipe = intel_crtc->pipe;
6209         int ret;
6210
6211         drm_vblank_pre_modeset(dev, pipe);
6212
6213         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6214
6215         drm_vblank_post_modeset(dev, pipe);
6216
6217         if (ret != 0)
6218                 return ret;
6219
6220         for_each_encoder_on_crtc(dev, crtc, encoder) {
6221                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6222                         encoder->base.base.id,
6223                         drm_get_encoder_name(&encoder->base),
6224                         mode->base.id, mode->name);
6225                 encoder->mode_set(encoder);
6226         }
6227
6228         return 0;
6229 }
6230
6231 static bool intel_eld_uptodate(struct drm_connector *connector,
6232                                int reg_eldv, uint32_t bits_eldv,
6233                                int reg_elda, uint32_t bits_elda,
6234                                int reg_edid)
6235 {
6236         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6237         uint8_t *eld = connector->eld;
6238         uint32_t i;
6239
6240         i = I915_READ(reg_eldv);
6241         i &= bits_eldv;
6242
6243         if (!eld[0])
6244                 return !i;
6245
6246         if (!i)
6247                 return false;
6248
6249         i = I915_READ(reg_elda);
6250         i &= ~bits_elda;
6251         I915_WRITE(reg_elda, i);
6252
6253         for (i = 0; i < eld[2]; i++)
6254                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6255                         return false;
6256
6257         return true;
6258 }
6259
6260 static void g4x_write_eld(struct drm_connector *connector,
6261                           struct drm_crtc *crtc)
6262 {
6263         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6264         uint8_t *eld = connector->eld;
6265         uint32_t eldv;
6266         uint32_t len;
6267         uint32_t i;
6268
6269         i = I915_READ(G4X_AUD_VID_DID);
6270
6271         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6272                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6273         else
6274                 eldv = G4X_ELDV_DEVCTG;
6275
6276         if (intel_eld_uptodate(connector,
6277                                G4X_AUD_CNTL_ST, eldv,
6278                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6279                                G4X_HDMIW_HDMIEDID))
6280                 return;
6281
6282         i = I915_READ(G4X_AUD_CNTL_ST);
6283         i &= ~(eldv | G4X_ELD_ADDR);
6284         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6285         I915_WRITE(G4X_AUD_CNTL_ST, i);
6286
6287         if (!eld[0])
6288                 return;
6289
6290         len = min_t(uint8_t, eld[2], len);
6291         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6292         for (i = 0; i < len; i++)
6293                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6294
6295         i = I915_READ(G4X_AUD_CNTL_ST);
6296         i |= eldv;
6297         I915_WRITE(G4X_AUD_CNTL_ST, i);
6298 }
6299
6300 static void haswell_write_eld(struct drm_connector *connector,
6301                                      struct drm_crtc *crtc)
6302 {
6303         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6304         uint8_t *eld = connector->eld;
6305         struct drm_device *dev = crtc->dev;
6306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307         uint32_t eldv;
6308         uint32_t i;
6309         int len;
6310         int pipe = to_intel_crtc(crtc)->pipe;
6311         int tmp;
6312
6313         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6314         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6315         int aud_config = HSW_AUD_CFG(pipe);
6316         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6317
6318
6319         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6320
6321         /* Audio output enable */
6322         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6323         tmp = I915_READ(aud_cntrl_st2);
6324         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6325         I915_WRITE(aud_cntrl_st2, tmp);
6326
6327         /* Wait for 1 vertical blank */
6328         intel_wait_for_vblank(dev, pipe);
6329
6330         /* Set ELD valid state */
6331         tmp = I915_READ(aud_cntrl_st2);
6332         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6333         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6334         I915_WRITE(aud_cntrl_st2, tmp);
6335         tmp = I915_READ(aud_cntrl_st2);
6336         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6337
6338         /* Enable HDMI mode */
6339         tmp = I915_READ(aud_config);
6340         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6341         /* clear N_programing_enable and N_value_index */
6342         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6343         I915_WRITE(aud_config, tmp);
6344
6345         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6346
6347         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6348         intel_crtc->eld_vld = true;
6349
6350         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6351                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6352                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6353                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6354         } else
6355                 I915_WRITE(aud_config, 0);
6356
6357         if (intel_eld_uptodate(connector,
6358                                aud_cntrl_st2, eldv,
6359                                aud_cntl_st, IBX_ELD_ADDRESS,
6360                                hdmiw_hdmiedid))
6361                 return;
6362
6363         i = I915_READ(aud_cntrl_st2);
6364         i &= ~eldv;
6365         I915_WRITE(aud_cntrl_st2, i);
6366
6367         if (!eld[0])
6368                 return;
6369
6370         i = I915_READ(aud_cntl_st);
6371         i &= ~IBX_ELD_ADDRESS;
6372         I915_WRITE(aud_cntl_st, i);
6373         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6374         DRM_DEBUG_DRIVER("port num:%d\n", i);
6375
6376         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6377         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6378         for (i = 0; i < len; i++)
6379                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6380
6381         i = I915_READ(aud_cntrl_st2);
6382         i |= eldv;
6383         I915_WRITE(aud_cntrl_st2, i);
6384
6385 }
6386
6387 static void ironlake_write_eld(struct drm_connector *connector,
6388                                      struct drm_crtc *crtc)
6389 {
6390         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6391         uint8_t *eld = connector->eld;
6392         uint32_t eldv;
6393         uint32_t i;
6394         int len;
6395         int hdmiw_hdmiedid;
6396         int aud_config;
6397         int aud_cntl_st;
6398         int aud_cntrl_st2;
6399         int pipe = to_intel_crtc(crtc)->pipe;
6400
6401         if (HAS_PCH_IBX(connector->dev)) {
6402                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6403                 aud_config = IBX_AUD_CFG(pipe);
6404                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6405                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6406         } else {
6407                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6408                 aud_config = CPT_AUD_CFG(pipe);
6409                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6410                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6411         }
6412
6413         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6414
6415         i = I915_READ(aud_cntl_st);
6416         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6417         if (!i) {
6418                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6419                 /* operate blindly on all ports */
6420                 eldv = IBX_ELD_VALIDB;
6421                 eldv |= IBX_ELD_VALIDB << 4;
6422                 eldv |= IBX_ELD_VALIDB << 8;
6423         } else {
6424                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6425                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6426         }
6427
6428         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6429                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6430                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6431                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6432         } else
6433                 I915_WRITE(aud_config, 0);
6434
6435         if (intel_eld_uptodate(connector,
6436                                aud_cntrl_st2, eldv,
6437                                aud_cntl_st, IBX_ELD_ADDRESS,
6438                                hdmiw_hdmiedid))
6439                 return;
6440
6441         i = I915_READ(aud_cntrl_st2);
6442         i &= ~eldv;
6443         I915_WRITE(aud_cntrl_st2, i);
6444
6445         if (!eld[0])
6446                 return;
6447
6448         i = I915_READ(aud_cntl_st);
6449         i &= ~IBX_ELD_ADDRESS;
6450         I915_WRITE(aud_cntl_st, i);
6451
6452         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6453         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6454         for (i = 0; i < len; i++)
6455                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6456
6457         i = I915_READ(aud_cntrl_st2);
6458         i |= eldv;
6459         I915_WRITE(aud_cntrl_st2, i);
6460 }
6461
6462 void intel_write_eld(struct drm_encoder *encoder,
6463                      struct drm_display_mode *mode)
6464 {
6465         struct drm_crtc *crtc = encoder->crtc;
6466         struct drm_connector *connector;
6467         struct drm_device *dev = encoder->dev;
6468         struct drm_i915_private *dev_priv = dev->dev_private;
6469
6470         connector = drm_select_eld(encoder, mode);
6471         if (!connector)
6472                 return;
6473
6474         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6475                          connector->base.id,
6476                          drm_get_connector_name(connector),
6477                          connector->encoder->base.id,
6478                          drm_get_encoder_name(connector->encoder));
6479
6480         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6481
6482         if (dev_priv->display.write_eld)
6483                 dev_priv->display.write_eld(connector, crtc);
6484 }
6485
6486 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6487 void intel_crtc_load_lut(struct drm_crtc *crtc)
6488 {
6489         struct drm_device *dev = crtc->dev;
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492         enum pipe pipe = intel_crtc->pipe;
6493         int palreg = PALETTE(pipe);
6494         int i;
6495         bool reenable_ips = false;
6496
6497         /* The clocks have to be on to load the palette. */
6498         if (!crtc->enabled || !intel_crtc->active)
6499                 return;
6500
6501         if (!HAS_PCH_SPLIT(dev_priv->dev))
6502                 assert_pll_enabled(dev_priv, pipe);
6503
6504         /* use legacy palette for Ironlake */
6505         if (HAS_PCH_SPLIT(dev))
6506                 palreg = LGC_PALETTE(pipe);
6507
6508         /* Workaround : Do not read or write the pipe palette/gamma data while
6509          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6510          */
6511         if (intel_crtc->config.ips_enabled &&
6512             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6513              GAMMA_MODE_MODE_SPLIT)) {
6514                 hsw_disable_ips(intel_crtc);
6515                 reenable_ips = true;
6516         }
6517
6518         for (i = 0; i < 256; i++) {
6519                 I915_WRITE(palreg + 4 * i,
6520                            (intel_crtc->lut_r[i] << 16) |
6521                            (intel_crtc->lut_g[i] << 8) |
6522                            intel_crtc->lut_b[i]);
6523         }
6524
6525         if (reenable_ips)
6526                 hsw_enable_ips(intel_crtc);
6527 }
6528
6529 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6530 {
6531         struct drm_device *dev = crtc->dev;
6532         struct drm_i915_private *dev_priv = dev->dev_private;
6533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6534         bool visible = base != 0;
6535         u32 cntl;
6536
6537         if (intel_crtc->cursor_visible == visible)
6538                 return;
6539
6540         cntl = I915_READ(_CURACNTR);
6541         if (visible) {
6542                 /* On these chipsets we can only modify the base whilst
6543                  * the cursor is disabled.
6544                  */
6545                 I915_WRITE(_CURABASE, base);
6546
6547                 cntl &= ~(CURSOR_FORMAT_MASK);
6548                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6549                 cntl |= CURSOR_ENABLE |
6550                         CURSOR_GAMMA_ENABLE |
6551                         CURSOR_FORMAT_ARGB;
6552         } else
6553                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6554         I915_WRITE(_CURACNTR, cntl);
6555
6556         intel_crtc->cursor_visible = visible;
6557 }
6558
6559 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6560 {
6561         struct drm_device *dev = crtc->dev;
6562         struct drm_i915_private *dev_priv = dev->dev_private;
6563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6564         int pipe = intel_crtc->pipe;
6565         bool visible = base != 0;
6566
6567         if (intel_crtc->cursor_visible != visible) {
6568                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6569                 if (base) {
6570                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6571                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6572                         cntl |= pipe << 28; /* Connect to correct pipe */
6573                 } else {
6574                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6575                         cntl |= CURSOR_MODE_DISABLE;
6576                 }
6577                 I915_WRITE(CURCNTR(pipe), cntl);
6578
6579                 intel_crtc->cursor_visible = visible;
6580         }
6581         /* and commit changes on next vblank */
6582         I915_WRITE(CURBASE(pipe), base);
6583 }
6584
6585 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6586 {
6587         struct drm_device *dev = crtc->dev;
6588         struct drm_i915_private *dev_priv = dev->dev_private;
6589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590         int pipe = intel_crtc->pipe;
6591         bool visible = base != 0;
6592
6593         if (intel_crtc->cursor_visible != visible) {
6594                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6595                 if (base) {
6596                         cntl &= ~CURSOR_MODE;
6597                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6598                 } else {
6599                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6600                         cntl |= CURSOR_MODE_DISABLE;
6601                 }
6602                 if (IS_HASWELL(dev))
6603                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6604                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6605
6606                 intel_crtc->cursor_visible = visible;
6607         }
6608         /* and commit changes on next vblank */
6609         I915_WRITE(CURBASE_IVB(pipe), base);
6610 }
6611
6612 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6613 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6614                                      bool on)
6615 {
6616         struct drm_device *dev = crtc->dev;
6617         struct drm_i915_private *dev_priv = dev->dev_private;
6618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619         int pipe = intel_crtc->pipe;
6620         int x = intel_crtc->cursor_x;
6621         int y = intel_crtc->cursor_y;
6622         u32 base, pos;
6623         bool visible;
6624
6625         pos = 0;
6626
6627         if (on && crtc->enabled && crtc->fb) {
6628                 base = intel_crtc->cursor_addr;
6629                 if (x > (int) crtc->fb->width)
6630                         base = 0;
6631
6632                 if (y > (int) crtc->fb->height)
6633                         base = 0;
6634         } else
6635                 base = 0;
6636
6637         if (x < 0) {
6638                 if (x + intel_crtc->cursor_width < 0)
6639                         base = 0;
6640
6641                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6642                 x = -x;
6643         }
6644         pos |= x << CURSOR_X_SHIFT;
6645
6646         if (y < 0) {
6647                 if (y + intel_crtc->cursor_height < 0)
6648                         base = 0;
6649
6650                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6651                 y = -y;
6652         }
6653         pos |= y << CURSOR_Y_SHIFT;
6654
6655         visible = base != 0;
6656         if (!visible && !intel_crtc->cursor_visible)
6657                 return;
6658
6659         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6660                 I915_WRITE(CURPOS_IVB(pipe), pos);
6661                 ivb_update_cursor(crtc, base);
6662         } else {
6663                 I915_WRITE(CURPOS(pipe), pos);
6664                 if (IS_845G(dev) || IS_I865G(dev))
6665                         i845_update_cursor(crtc, base);
6666                 else
6667                         i9xx_update_cursor(crtc, base);
6668         }
6669 }
6670
6671 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6672                                  struct drm_file *file,
6673                                  uint32_t handle,
6674                                  uint32_t width, uint32_t height)
6675 {
6676         struct drm_device *dev = crtc->dev;
6677         struct drm_i915_private *dev_priv = dev->dev_private;
6678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6679         struct drm_i915_gem_object *obj;
6680         uint32_t addr;
6681         int ret;
6682
6683         /* if we want to turn off the cursor ignore width and height */
6684         if (!handle) {
6685                 DRM_DEBUG_KMS("cursor off\n");
6686                 addr = 0;
6687                 obj = NULL;
6688                 mutex_lock(&dev->struct_mutex);
6689                 goto finish;
6690         }
6691
6692         /* Currently we only support 64x64 cursors */
6693         if (width != 64 || height != 64) {
6694                 DRM_ERROR("we currently only support 64x64 cursors\n");
6695                 return -EINVAL;
6696         }
6697
6698         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6699         if (&obj->base == NULL)
6700                 return -ENOENT;
6701
6702         if (obj->base.size < width * height * 4) {
6703                 DRM_ERROR("buffer is to small\n");
6704                 ret = -ENOMEM;
6705                 goto fail;
6706         }
6707
6708         /* we only need to pin inside GTT if cursor is non-phy */
6709         mutex_lock(&dev->struct_mutex);
6710         if (!dev_priv->info->cursor_needs_physical) {
6711                 unsigned alignment;
6712
6713                 if (obj->tiling_mode) {
6714                         DRM_ERROR("cursor cannot be tiled\n");
6715                         ret = -EINVAL;
6716                         goto fail_locked;
6717                 }
6718
6719                 /* Note that the w/a also requires 2 PTE of padding following
6720                  * the bo. We currently fill all unused PTE with the shadow
6721                  * page and so we should always have valid PTE following the
6722                  * cursor preventing the VT-d warning.
6723                  */
6724                 alignment = 0;
6725                 if (need_vtd_wa(dev))
6726                         alignment = 64*1024;
6727
6728                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6729                 if (ret) {
6730                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6731                         goto fail_locked;
6732                 }
6733
6734                 ret = i915_gem_object_put_fence(obj);
6735                 if (ret) {
6736                         DRM_ERROR("failed to release fence for cursor");
6737                         goto fail_unpin;
6738                 }
6739
6740                 addr = i915_gem_obj_ggtt_offset(obj);
6741         } else {
6742                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6743                 ret = i915_gem_attach_phys_object(dev, obj,
6744                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6745                                                   align);
6746                 if (ret) {
6747                         DRM_ERROR("failed to attach phys object\n");
6748                         goto fail_locked;
6749                 }
6750                 addr = obj->phys_obj->handle->busaddr;
6751         }
6752
6753         if (IS_GEN2(dev))
6754                 I915_WRITE(CURSIZE, (height << 12) | width);
6755
6756  finish:
6757         if (intel_crtc->cursor_bo) {
6758                 if (dev_priv->info->cursor_needs_physical) {
6759                         if (intel_crtc->cursor_bo != obj)
6760                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6761                 } else
6762                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6763                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6764         }
6765
6766         mutex_unlock(&dev->struct_mutex);
6767
6768         intel_crtc->cursor_addr = addr;
6769         intel_crtc->cursor_bo = obj;
6770         intel_crtc->cursor_width = width;
6771         intel_crtc->cursor_height = height;
6772
6773         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6774
6775         return 0;
6776 fail_unpin:
6777         i915_gem_object_unpin(obj);
6778 fail_locked:
6779         mutex_unlock(&dev->struct_mutex);
6780 fail:
6781         drm_gem_object_unreference_unlocked(&obj->base);
6782         return ret;
6783 }
6784
6785 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6786 {
6787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788
6789         intel_crtc->cursor_x = x;
6790         intel_crtc->cursor_y = y;
6791
6792         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6793
6794         return 0;
6795 }
6796
6797 /** Sets the color ramps on behalf of RandR */
6798 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6799                                  u16 blue, int regno)
6800 {
6801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6802
6803         intel_crtc->lut_r[regno] = red >> 8;
6804         intel_crtc->lut_g[regno] = green >> 8;
6805         intel_crtc->lut_b[regno] = blue >> 8;
6806 }
6807
6808 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6809                              u16 *blue, int regno)
6810 {
6811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812
6813         *red = intel_crtc->lut_r[regno] << 8;
6814         *green = intel_crtc->lut_g[regno] << 8;
6815         *blue = intel_crtc->lut_b[regno] << 8;
6816 }
6817
6818 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6819                                  u16 *blue, uint32_t start, uint32_t size)
6820 {
6821         int end = (start + size > 256) ? 256 : start + size, i;
6822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6823
6824         for (i = start; i < end; i++) {
6825                 intel_crtc->lut_r[i] = red[i] >> 8;
6826                 intel_crtc->lut_g[i] = green[i] >> 8;
6827                 intel_crtc->lut_b[i] = blue[i] >> 8;
6828         }
6829
6830         intel_crtc_load_lut(crtc);
6831 }
6832
6833 /* VESA 640x480x72Hz mode to set on the pipe */
6834 static struct drm_display_mode load_detect_mode = {
6835         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6836                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6837 };
6838
6839 static struct drm_framebuffer *
6840 intel_framebuffer_create(struct drm_device *dev,
6841                          struct drm_mode_fb_cmd2 *mode_cmd,
6842                          struct drm_i915_gem_object *obj)
6843 {
6844         struct intel_framebuffer *intel_fb;
6845         int ret;
6846
6847         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6848         if (!intel_fb) {
6849                 drm_gem_object_unreference_unlocked(&obj->base);
6850                 return ERR_PTR(-ENOMEM);
6851         }
6852
6853         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6854         if (ret) {
6855                 drm_gem_object_unreference_unlocked(&obj->base);
6856                 kfree(intel_fb);
6857                 return ERR_PTR(ret);
6858         }
6859
6860         return &intel_fb->base;
6861 }
6862
6863 static u32
6864 intel_framebuffer_pitch_for_width(int width, int bpp)
6865 {
6866         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6867         return ALIGN(pitch, 64);
6868 }
6869
6870 static u32
6871 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6872 {
6873         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6874         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6875 }
6876
6877 static struct drm_framebuffer *
6878 intel_framebuffer_create_for_mode(struct drm_device *dev,
6879                                   struct drm_display_mode *mode,
6880                                   int depth, int bpp)
6881 {
6882         struct drm_i915_gem_object *obj;
6883         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6884
6885         obj = i915_gem_alloc_object(dev,
6886                                     intel_framebuffer_size_for_mode(mode, bpp));
6887         if (obj == NULL)
6888                 return ERR_PTR(-ENOMEM);
6889
6890         mode_cmd.width = mode->hdisplay;
6891         mode_cmd.height = mode->vdisplay;
6892         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6893                                                                 bpp);
6894         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6895
6896         return intel_framebuffer_create(dev, &mode_cmd, obj);
6897 }
6898
6899 static struct drm_framebuffer *
6900 mode_fits_in_fbdev(struct drm_device *dev,
6901                    struct drm_display_mode *mode)
6902 {
6903         struct drm_i915_private *dev_priv = dev->dev_private;
6904         struct drm_i915_gem_object *obj;
6905         struct drm_framebuffer *fb;
6906
6907         if (dev_priv->fbdev == NULL)
6908                 return NULL;
6909
6910         obj = dev_priv->fbdev->ifb.obj;
6911         if (obj == NULL)
6912                 return NULL;
6913
6914         fb = &dev_priv->fbdev->ifb.base;
6915         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6916                                                                fb->bits_per_pixel))
6917                 return NULL;
6918
6919         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6920                 return NULL;
6921
6922         return fb;
6923 }
6924
6925 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6926                                 struct drm_display_mode *mode,
6927                                 struct intel_load_detect_pipe *old)
6928 {
6929         struct intel_crtc *intel_crtc;
6930         struct intel_encoder *intel_encoder =
6931                 intel_attached_encoder(connector);
6932         struct drm_crtc *possible_crtc;
6933         struct drm_encoder *encoder = &intel_encoder->base;
6934         struct drm_crtc *crtc = NULL;
6935         struct drm_device *dev = encoder->dev;
6936         struct drm_framebuffer *fb;
6937         int i = -1;
6938
6939         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6940                       connector->base.id, drm_get_connector_name(connector),
6941                       encoder->base.id, drm_get_encoder_name(encoder));
6942
6943         /*
6944          * Algorithm gets a little messy:
6945          *
6946          *   - if the connector already has an assigned crtc, use it (but make
6947          *     sure it's on first)
6948          *
6949          *   - try to find the first unused crtc that can drive this connector,
6950          *     and use that if we find one
6951          */
6952
6953         /* See if we already have a CRTC for this connector */
6954         if (encoder->crtc) {
6955                 crtc = encoder->crtc;
6956
6957                 mutex_lock(&crtc->mutex);
6958
6959                 old->dpms_mode = connector->dpms;
6960                 old->load_detect_temp = false;
6961
6962                 /* Make sure the crtc and connector are running */
6963                 if (connector->dpms != DRM_MODE_DPMS_ON)
6964                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6965
6966                 return true;
6967         }
6968
6969         /* Find an unused one (if possible) */
6970         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6971                 i++;
6972                 if (!(encoder->possible_crtcs & (1 << i)))
6973                         continue;
6974                 if (!possible_crtc->enabled) {
6975                         crtc = possible_crtc;
6976                         break;
6977                 }
6978         }
6979
6980         /*
6981          * If we didn't find an unused CRTC, don't use any.
6982          */
6983         if (!crtc) {
6984                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6985                 return false;
6986         }
6987
6988         mutex_lock(&crtc->mutex);
6989         intel_encoder->new_crtc = to_intel_crtc(crtc);
6990         to_intel_connector(connector)->new_encoder = intel_encoder;
6991
6992         intel_crtc = to_intel_crtc(crtc);
6993         old->dpms_mode = connector->dpms;
6994         old->load_detect_temp = true;
6995         old->release_fb = NULL;
6996
6997         if (!mode)
6998                 mode = &load_detect_mode;
6999
7000         /* We need a framebuffer large enough to accommodate all accesses
7001          * that the plane may generate whilst we perform load detection.
7002          * We can not rely on the fbcon either being present (we get called
7003          * during its initialisation to detect all boot displays, or it may
7004          * not even exist) or that it is large enough to satisfy the
7005          * requested mode.
7006          */
7007         fb = mode_fits_in_fbdev(dev, mode);
7008         if (fb == NULL) {
7009                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7010                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7011                 old->release_fb = fb;
7012         } else
7013                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7014         if (IS_ERR(fb)) {
7015                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7016                 mutex_unlock(&crtc->mutex);
7017                 return false;
7018         }
7019
7020         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7021                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7022                 if (old->release_fb)
7023                         old->release_fb->funcs->destroy(old->release_fb);
7024                 mutex_unlock(&crtc->mutex);
7025                 return false;
7026         }
7027
7028         /* let the connector get through one full cycle before testing */
7029         intel_wait_for_vblank(dev, intel_crtc->pipe);
7030         return true;
7031 }
7032
7033 void intel_release_load_detect_pipe(struct drm_connector *connector,
7034                                     struct intel_load_detect_pipe *old)
7035 {
7036         struct intel_encoder *intel_encoder =
7037                 intel_attached_encoder(connector);
7038         struct drm_encoder *encoder = &intel_encoder->base;
7039         struct drm_crtc *crtc = encoder->crtc;
7040
7041         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7042                       connector->base.id, drm_get_connector_name(connector),
7043                       encoder->base.id, drm_get_encoder_name(encoder));
7044
7045         if (old->load_detect_temp) {
7046                 to_intel_connector(connector)->new_encoder = NULL;
7047                 intel_encoder->new_crtc = NULL;
7048                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7049
7050                 if (old->release_fb) {
7051                         drm_framebuffer_unregister_private(old->release_fb);
7052                         drm_framebuffer_unreference(old->release_fb);
7053                 }
7054
7055                 mutex_unlock(&crtc->mutex);
7056                 return;
7057         }
7058
7059         /* Switch crtc and encoder back off if necessary */
7060         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7061                 connector->funcs->dpms(connector, old->dpms_mode);
7062
7063         mutex_unlock(&crtc->mutex);
7064 }
7065
7066 /* Returns the clock of the currently programmed mode of the given pipe. */
7067 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7068                                 struct intel_crtc_config *pipe_config)
7069 {
7070         struct drm_device *dev = crtc->base.dev;
7071         struct drm_i915_private *dev_priv = dev->dev_private;
7072         int pipe = pipe_config->cpu_transcoder;
7073         u32 dpll = I915_READ(DPLL(pipe));
7074         u32 fp;
7075         intel_clock_t clock;
7076
7077         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7078                 fp = I915_READ(FP0(pipe));
7079         else
7080                 fp = I915_READ(FP1(pipe));
7081
7082         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7083         if (IS_PINEVIEW(dev)) {
7084                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7085                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7086         } else {
7087                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7088                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7089         }
7090
7091         if (!IS_GEN2(dev)) {
7092                 if (IS_PINEVIEW(dev))
7093                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7094                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7095                 else
7096                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7097                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7098
7099                 switch (dpll & DPLL_MODE_MASK) {
7100                 case DPLLB_MODE_DAC_SERIAL:
7101                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7102                                 5 : 10;
7103                         break;
7104                 case DPLLB_MODE_LVDS:
7105                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7106                                 7 : 14;
7107                         break;
7108                 default:
7109                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7110                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7111                         pipe_config->adjusted_mode.clock = 0;
7112                         return;
7113                 }
7114
7115                 if (IS_PINEVIEW(dev))
7116                         pineview_clock(96000, &clock);
7117                 else
7118                         i9xx_clock(96000, &clock);
7119         } else {
7120                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7121
7122                 if (is_lvds) {
7123                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7124                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7125                         clock.p2 = 14;
7126
7127                         if ((dpll & PLL_REF_INPUT_MASK) ==
7128                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7129                                 /* XXX: might not be 66MHz */
7130                                 i9xx_clock(66000, &clock);
7131                         } else
7132                                 i9xx_clock(48000, &clock);
7133                 } else {
7134                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7135                                 clock.p1 = 2;
7136                         else {
7137                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7138                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7139                         }
7140                         if (dpll & PLL_P2_DIVIDE_BY_4)
7141                                 clock.p2 = 4;
7142                         else
7143                                 clock.p2 = 2;
7144
7145                         i9xx_clock(48000, &clock);
7146                 }
7147         }
7148
7149         pipe_config->adjusted_mode.clock = clock.dot *
7150                 pipe_config->pixel_multiplier;
7151 }
7152
7153 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7154                                     struct intel_crtc_config *pipe_config)
7155 {
7156         struct drm_device *dev = crtc->base.dev;
7157         struct drm_i915_private *dev_priv = dev->dev_private;
7158         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7159         int link_freq, repeat;
7160         u64 clock;
7161         u32 link_m, link_n;
7162
7163         repeat = pipe_config->pixel_multiplier;
7164
7165         /*
7166          * The calculation for the data clock is:
7167          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7168          * But we want to avoid losing precison if possible, so:
7169          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7170          *
7171          * and the link clock is simpler:
7172          * link_clock = (m * link_clock * repeat) / n
7173          */
7174
7175         /*
7176          * We need to get the FDI or DP link clock here to derive
7177          * the M/N dividers.
7178          *
7179          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7180          * For DP, it's either 1.62GHz or 2.7GHz.
7181          * We do our calculations in 10*MHz since we don't need much precison.
7182          */
7183         if (pipe_config->has_pch_encoder)
7184                 link_freq = intel_fdi_link_freq(dev) * 10000;
7185         else
7186                 link_freq = pipe_config->port_clock;
7187
7188         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7189         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7190
7191         if (!link_m || !link_n)
7192                 return;
7193
7194         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7195         do_div(clock, link_n);
7196
7197         pipe_config->adjusted_mode.clock = clock;
7198 }
7199
7200 /** Returns the currently programmed mode of the given pipe. */
7201 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7202                                              struct drm_crtc *crtc)
7203 {
7204         struct drm_i915_private *dev_priv = dev->dev_private;
7205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7206         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7207         struct drm_display_mode *mode;
7208         struct intel_crtc_config pipe_config;
7209         int htot = I915_READ(HTOTAL(cpu_transcoder));
7210         int hsync = I915_READ(HSYNC(cpu_transcoder));
7211         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7212         int vsync = I915_READ(VSYNC(cpu_transcoder));
7213
7214         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7215         if (!mode)
7216                 return NULL;
7217
7218         /*
7219          * Construct a pipe_config sufficient for getting the clock info
7220          * back out of crtc_clock_get.
7221          *
7222          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7223          * to use a real value here instead.
7224          */
7225         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7226         pipe_config.pixel_multiplier = 1;
7227         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7228
7229         mode->clock = pipe_config.adjusted_mode.clock;
7230         mode->hdisplay = (htot & 0xffff) + 1;
7231         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7232         mode->hsync_start = (hsync & 0xffff) + 1;
7233         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7234         mode->vdisplay = (vtot & 0xffff) + 1;
7235         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7236         mode->vsync_start = (vsync & 0xffff) + 1;
7237         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7238
7239         drm_mode_set_name(mode);
7240
7241         return mode;
7242 }
7243
7244 static void intel_increase_pllclock(struct drm_crtc *crtc)
7245 {
7246         struct drm_device *dev = crtc->dev;
7247         drm_i915_private_t *dev_priv = dev->dev_private;
7248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7249         int pipe = intel_crtc->pipe;
7250         int dpll_reg = DPLL(pipe);
7251         int dpll;
7252
7253         if (HAS_PCH_SPLIT(dev))
7254                 return;
7255
7256         if (!dev_priv->lvds_downclock_avail)
7257                 return;
7258
7259         dpll = I915_READ(dpll_reg);
7260         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7261                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7262
7263                 assert_panel_unlocked(dev_priv, pipe);
7264
7265                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7266                 I915_WRITE(dpll_reg, dpll);
7267                 intel_wait_for_vblank(dev, pipe);
7268
7269                 dpll = I915_READ(dpll_reg);
7270                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7271                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7272         }
7273 }
7274
7275 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7276 {
7277         struct drm_device *dev = crtc->dev;
7278         drm_i915_private_t *dev_priv = dev->dev_private;
7279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280
7281         if (HAS_PCH_SPLIT(dev))
7282                 return;
7283
7284         if (!dev_priv->lvds_downclock_avail)
7285                 return;
7286
7287         /*
7288          * Since this is called by a timer, we should never get here in
7289          * the manual case.
7290          */
7291         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7292                 int pipe = intel_crtc->pipe;
7293                 int dpll_reg = DPLL(pipe);
7294                 int dpll;
7295
7296                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7297
7298                 assert_panel_unlocked(dev_priv, pipe);
7299
7300                 dpll = I915_READ(dpll_reg);
7301                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7302                 I915_WRITE(dpll_reg, dpll);
7303                 intel_wait_for_vblank(dev, pipe);
7304                 dpll = I915_READ(dpll_reg);
7305                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7306                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7307         }
7308
7309 }
7310
7311 void intel_mark_busy(struct drm_device *dev)
7312 {
7313         i915_update_gfx_val(dev->dev_private);
7314 }
7315
7316 void intel_mark_idle(struct drm_device *dev)
7317 {
7318         struct drm_crtc *crtc;
7319
7320         if (!i915_powersave)
7321                 return;
7322
7323         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7324                 if (!crtc->fb)
7325                         continue;
7326
7327                 intel_decrease_pllclock(crtc);
7328         }
7329 }
7330
7331 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7332                         struct intel_ring_buffer *ring)
7333 {
7334         struct drm_device *dev = obj->base.dev;
7335         struct drm_crtc *crtc;
7336
7337         if (!i915_powersave)
7338                 return;
7339
7340         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7341                 if (!crtc->fb)
7342                         continue;
7343
7344                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7345                         continue;
7346
7347                 intel_increase_pllclock(crtc);
7348                 if (ring && intel_fbc_enabled(dev))
7349                         ring->fbc_dirty = true;
7350         }
7351 }
7352
7353 static void intel_crtc_destroy(struct drm_crtc *crtc)
7354 {
7355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7356         struct drm_device *dev = crtc->dev;
7357         struct intel_unpin_work *work;
7358         unsigned long flags;
7359
7360         spin_lock_irqsave(&dev->event_lock, flags);
7361         work = intel_crtc->unpin_work;
7362         intel_crtc->unpin_work = NULL;
7363         spin_unlock_irqrestore(&dev->event_lock, flags);
7364
7365         if (work) {
7366                 cancel_work_sync(&work->work);
7367                 kfree(work);
7368         }
7369
7370         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7371
7372         drm_crtc_cleanup(crtc);
7373
7374         kfree(intel_crtc);
7375 }
7376
7377 static void intel_unpin_work_fn(struct work_struct *__work)
7378 {
7379         struct intel_unpin_work *work =
7380                 container_of(__work, struct intel_unpin_work, work);
7381         struct drm_device *dev = work->crtc->dev;
7382
7383         mutex_lock(&dev->struct_mutex);
7384         intel_unpin_fb_obj(work->old_fb_obj);
7385         drm_gem_object_unreference(&work->pending_flip_obj->base);
7386         drm_gem_object_unreference(&work->old_fb_obj->base);
7387
7388         intel_update_fbc(dev);
7389         mutex_unlock(&dev->struct_mutex);
7390
7391         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7392         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7393
7394         kfree(work);
7395 }
7396
7397 static void do_intel_finish_page_flip(struct drm_device *dev,
7398                                       struct drm_crtc *crtc)
7399 {
7400         drm_i915_private_t *dev_priv = dev->dev_private;
7401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402         struct intel_unpin_work *work;
7403         unsigned long flags;
7404
7405         /* Ignore early vblank irqs */
7406         if (intel_crtc == NULL)
7407                 return;
7408
7409         spin_lock_irqsave(&dev->event_lock, flags);
7410         work = intel_crtc->unpin_work;
7411
7412         /* Ensure we don't miss a work->pending update ... */
7413         smp_rmb();
7414
7415         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7416                 spin_unlock_irqrestore(&dev->event_lock, flags);
7417                 return;
7418         }
7419
7420         /* and that the unpin work is consistent wrt ->pending. */
7421         smp_rmb();
7422
7423         intel_crtc->unpin_work = NULL;
7424
7425         if (work->event)
7426                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7427
7428         drm_vblank_put(dev, intel_crtc->pipe);
7429
7430         spin_unlock_irqrestore(&dev->event_lock, flags);
7431
7432         wake_up_all(&dev_priv->pending_flip_queue);
7433
7434         queue_work(dev_priv->wq, &work->work);
7435
7436         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7437 }
7438
7439 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7440 {
7441         drm_i915_private_t *dev_priv = dev->dev_private;
7442         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7443
7444         do_intel_finish_page_flip(dev, crtc);
7445 }
7446
7447 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7448 {
7449         drm_i915_private_t *dev_priv = dev->dev_private;
7450         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7451
7452         do_intel_finish_page_flip(dev, crtc);
7453 }
7454
7455 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7456 {
7457         drm_i915_private_t *dev_priv = dev->dev_private;
7458         struct intel_crtc *intel_crtc =
7459                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7460         unsigned long flags;
7461
7462         /* NB: An MMIO update of the plane base pointer will also
7463          * generate a page-flip completion irq, i.e. every modeset
7464          * is also accompanied by a spurious intel_prepare_page_flip().
7465          */
7466         spin_lock_irqsave(&dev->event_lock, flags);
7467         if (intel_crtc->unpin_work)
7468                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7469         spin_unlock_irqrestore(&dev->event_lock, flags);
7470 }
7471
7472 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7473 {
7474         /* Ensure that the work item is consistent when activating it ... */
7475         smp_wmb();
7476         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7477         /* and that it is marked active as soon as the irq could fire. */
7478         smp_wmb();
7479 }
7480
7481 static int intel_gen2_queue_flip(struct drm_device *dev,
7482                                  struct drm_crtc *crtc,
7483                                  struct drm_framebuffer *fb,
7484                                  struct drm_i915_gem_object *obj)
7485 {
7486         struct drm_i915_private *dev_priv = dev->dev_private;
7487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7488         u32 flip_mask;
7489         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7490         int ret;
7491
7492         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7493         if (ret)
7494                 goto err;
7495
7496         ret = intel_ring_begin(ring, 6);
7497         if (ret)
7498                 goto err_unpin;
7499
7500         /* Can't queue multiple flips, so wait for the previous
7501          * one to finish before executing the next.
7502          */
7503         if (intel_crtc->plane)
7504                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7505         else
7506                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7507         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7508         intel_ring_emit(ring, MI_NOOP);
7509         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7510                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7511         intel_ring_emit(ring, fb->pitches[0]);
7512         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7513         intel_ring_emit(ring, 0); /* aux display base address, unused */
7514
7515         intel_mark_page_flip_active(intel_crtc);
7516         intel_ring_advance(ring);
7517         return 0;
7518
7519 err_unpin:
7520         intel_unpin_fb_obj(obj);
7521 err:
7522         return ret;
7523 }
7524
7525 static int intel_gen3_queue_flip(struct drm_device *dev,
7526                                  struct drm_crtc *crtc,
7527                                  struct drm_framebuffer *fb,
7528                                  struct drm_i915_gem_object *obj)
7529 {
7530         struct drm_i915_private *dev_priv = dev->dev_private;
7531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7532         u32 flip_mask;
7533         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7534         int ret;
7535
7536         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7537         if (ret)
7538                 goto err;
7539
7540         ret = intel_ring_begin(ring, 6);
7541         if (ret)
7542                 goto err_unpin;
7543
7544         if (intel_crtc->plane)
7545                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7546         else
7547                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7548         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7549         intel_ring_emit(ring, MI_NOOP);
7550         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7551                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7552         intel_ring_emit(ring, fb->pitches[0]);
7553         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7554         intel_ring_emit(ring, MI_NOOP);
7555
7556         intel_mark_page_flip_active(intel_crtc);
7557         intel_ring_advance(ring);
7558         return 0;
7559
7560 err_unpin:
7561         intel_unpin_fb_obj(obj);
7562 err:
7563         return ret;
7564 }
7565
7566 static int intel_gen4_queue_flip(struct drm_device *dev,
7567                                  struct drm_crtc *crtc,
7568                                  struct drm_framebuffer *fb,
7569                                  struct drm_i915_gem_object *obj)
7570 {
7571         struct drm_i915_private *dev_priv = dev->dev_private;
7572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7573         uint32_t pf, pipesrc;
7574         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7575         int ret;
7576
7577         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7578         if (ret)
7579                 goto err;
7580
7581         ret = intel_ring_begin(ring, 4);
7582         if (ret)
7583                 goto err_unpin;
7584
7585         /* i965+ uses the linear or tiled offsets from the
7586          * Display Registers (which do not change across a page-flip)
7587          * so we need only reprogram the base address.
7588          */
7589         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7590                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7591         intel_ring_emit(ring, fb->pitches[0]);
7592         intel_ring_emit(ring,
7593                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7594                         obj->tiling_mode);
7595
7596         /* XXX Enabling the panel-fitter across page-flip is so far
7597          * untested on non-native modes, so ignore it for now.
7598          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7599          */
7600         pf = 0;
7601         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7602         intel_ring_emit(ring, pf | pipesrc);
7603
7604         intel_mark_page_flip_active(intel_crtc);
7605         intel_ring_advance(ring);
7606         return 0;
7607
7608 err_unpin:
7609         intel_unpin_fb_obj(obj);
7610 err:
7611         return ret;
7612 }
7613
7614 static int intel_gen6_queue_flip(struct drm_device *dev,
7615                                  struct drm_crtc *crtc,
7616                                  struct drm_framebuffer *fb,
7617                                  struct drm_i915_gem_object *obj)
7618 {
7619         struct drm_i915_private *dev_priv = dev->dev_private;
7620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7621         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7622         uint32_t pf, pipesrc;
7623         int ret;
7624
7625         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7626         if (ret)
7627                 goto err;
7628
7629         ret = intel_ring_begin(ring, 4);
7630         if (ret)
7631                 goto err_unpin;
7632
7633         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7634                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7635         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7636         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7637
7638         /* Contrary to the suggestions in the documentation,
7639          * "Enable Panel Fitter" does not seem to be required when page
7640          * flipping with a non-native mode, and worse causes a normal
7641          * modeset to fail.
7642          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7643          */
7644         pf = 0;
7645         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7646         intel_ring_emit(ring, pf | pipesrc);
7647
7648         intel_mark_page_flip_active(intel_crtc);
7649         intel_ring_advance(ring);
7650         return 0;
7651
7652 err_unpin:
7653         intel_unpin_fb_obj(obj);
7654 err:
7655         return ret;
7656 }
7657
7658 /*
7659  * On gen7 we currently use the blit ring because (in early silicon at least)
7660  * the render ring doesn't give us interrpts for page flip completion, which
7661  * means clients will hang after the first flip is queued.  Fortunately the
7662  * blit ring generates interrupts properly, so use it instead.
7663  */
7664 static int intel_gen7_queue_flip(struct drm_device *dev,
7665                                  struct drm_crtc *crtc,
7666                                  struct drm_framebuffer *fb,
7667                                  struct drm_i915_gem_object *obj)
7668 {
7669         struct drm_i915_private *dev_priv = dev->dev_private;
7670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7671         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7672         uint32_t plane_bit = 0;
7673         int ret;
7674
7675         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7676         if (ret)
7677                 goto err;
7678
7679         switch(intel_crtc->plane) {
7680         case PLANE_A:
7681                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7682                 break;
7683         case PLANE_B:
7684                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7685                 break;
7686         case PLANE_C:
7687                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7688                 break;
7689         default:
7690                 WARN_ONCE(1, "unknown plane in flip command\n");
7691                 ret = -ENODEV;
7692                 goto err_unpin;
7693         }
7694
7695         ret = intel_ring_begin(ring, 4);
7696         if (ret)
7697                 goto err_unpin;
7698
7699         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7700         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7701         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7702         intel_ring_emit(ring, (MI_NOOP));
7703
7704         intel_mark_page_flip_active(intel_crtc);
7705         intel_ring_advance(ring);
7706         return 0;
7707
7708 err_unpin:
7709         intel_unpin_fb_obj(obj);
7710 err:
7711         return ret;
7712 }
7713
7714 static int intel_default_queue_flip(struct drm_device *dev,
7715                                     struct drm_crtc *crtc,
7716                                     struct drm_framebuffer *fb,
7717                                     struct drm_i915_gem_object *obj)
7718 {
7719         return -ENODEV;
7720 }
7721
7722 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7723                                 struct drm_framebuffer *fb,
7724                                 struct drm_pending_vblank_event *event)
7725 {
7726         struct drm_device *dev = crtc->dev;
7727         struct drm_i915_private *dev_priv = dev->dev_private;
7728         struct drm_framebuffer *old_fb = crtc->fb;
7729         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7731         struct intel_unpin_work *work;
7732         unsigned long flags;
7733         int ret;
7734
7735         /* Can't change pixel format via MI display flips. */
7736         if (fb->pixel_format != crtc->fb->pixel_format)
7737                 return -EINVAL;
7738
7739         /*
7740          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7741          * Note that pitch changes could also affect these register.
7742          */
7743         if (INTEL_INFO(dev)->gen > 3 &&
7744             (fb->offsets[0] != crtc->fb->offsets[0] ||
7745              fb->pitches[0] != crtc->fb->pitches[0]))
7746                 return -EINVAL;
7747
7748         work = kzalloc(sizeof *work, GFP_KERNEL);
7749         if (work == NULL)
7750                 return -ENOMEM;
7751
7752         work->event = event;
7753         work->crtc = crtc;
7754         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7755         INIT_WORK(&work->work, intel_unpin_work_fn);
7756
7757         ret = drm_vblank_get(dev, intel_crtc->pipe);
7758         if (ret)
7759                 goto free_work;
7760
7761         /* We borrow the event spin lock for protecting unpin_work */
7762         spin_lock_irqsave(&dev->event_lock, flags);
7763         if (intel_crtc->unpin_work) {
7764                 spin_unlock_irqrestore(&dev->event_lock, flags);
7765                 kfree(work);
7766                 drm_vblank_put(dev, intel_crtc->pipe);
7767
7768                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7769                 return -EBUSY;
7770         }
7771         intel_crtc->unpin_work = work;
7772         spin_unlock_irqrestore(&dev->event_lock, flags);
7773
7774         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7775                 flush_workqueue(dev_priv->wq);
7776
7777         ret = i915_mutex_lock_interruptible(dev);
7778         if (ret)
7779                 goto cleanup;
7780
7781         /* Reference the objects for the scheduled work. */
7782         drm_gem_object_reference(&work->old_fb_obj->base);
7783         drm_gem_object_reference(&obj->base);
7784
7785         crtc->fb = fb;
7786
7787         work->pending_flip_obj = obj;
7788
7789         work->enable_stall_check = true;
7790
7791         atomic_inc(&intel_crtc->unpin_work_count);
7792         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7793
7794         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7795         if (ret)
7796                 goto cleanup_pending;
7797
7798         intel_disable_fbc(dev);
7799         intel_mark_fb_busy(obj, NULL);
7800         mutex_unlock(&dev->struct_mutex);
7801
7802         trace_i915_flip_request(intel_crtc->plane, obj);
7803
7804         return 0;
7805
7806 cleanup_pending:
7807         atomic_dec(&intel_crtc->unpin_work_count);
7808         crtc->fb = old_fb;
7809         drm_gem_object_unreference(&work->old_fb_obj->base);
7810         drm_gem_object_unreference(&obj->base);
7811         mutex_unlock(&dev->struct_mutex);
7812
7813 cleanup:
7814         spin_lock_irqsave(&dev->event_lock, flags);
7815         intel_crtc->unpin_work = NULL;
7816         spin_unlock_irqrestore(&dev->event_lock, flags);
7817
7818         drm_vblank_put(dev, intel_crtc->pipe);
7819 free_work:
7820         kfree(work);
7821
7822         return ret;
7823 }
7824
7825 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7826         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7827         .load_lut = intel_crtc_load_lut,
7828 };
7829
7830 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7831                                   struct drm_crtc *crtc)
7832 {
7833         struct drm_device *dev;
7834         struct drm_crtc *tmp;
7835         int crtc_mask = 1;
7836
7837         WARN(!crtc, "checking null crtc?\n");
7838
7839         dev = crtc->dev;
7840
7841         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7842                 if (tmp == crtc)
7843                         break;
7844                 crtc_mask <<= 1;
7845         }
7846
7847         if (encoder->possible_crtcs & crtc_mask)
7848                 return true;
7849         return false;
7850 }
7851
7852 /**
7853  * intel_modeset_update_staged_output_state
7854  *
7855  * Updates the staged output configuration state, e.g. after we've read out the
7856  * current hw state.
7857  */
7858 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7859 {
7860         struct intel_encoder *encoder;
7861         struct intel_connector *connector;
7862
7863         list_for_each_entry(connector, &dev->mode_config.connector_list,
7864                             base.head) {
7865                 connector->new_encoder =
7866                         to_intel_encoder(connector->base.encoder);
7867         }
7868
7869         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7870                             base.head) {
7871                 encoder->new_crtc =
7872                         to_intel_crtc(encoder->base.crtc);
7873         }
7874 }
7875
7876 /**
7877  * intel_modeset_commit_output_state
7878  *
7879  * This function copies the stage display pipe configuration to the real one.
7880  */
7881 static void intel_modeset_commit_output_state(struct drm_device *dev)
7882 {
7883         struct intel_encoder *encoder;
7884         struct intel_connector *connector;
7885
7886         list_for_each_entry(connector, &dev->mode_config.connector_list,
7887                             base.head) {
7888                 connector->base.encoder = &connector->new_encoder->base;
7889         }
7890
7891         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892                             base.head) {
7893                 encoder->base.crtc = &encoder->new_crtc->base;
7894         }
7895 }
7896
7897 static void
7898 connected_sink_compute_bpp(struct intel_connector * connector,
7899                            struct intel_crtc_config *pipe_config)
7900 {
7901         int bpp = pipe_config->pipe_bpp;
7902
7903         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7904                 connector->base.base.id,
7905                 drm_get_connector_name(&connector->base));
7906
7907         /* Don't use an invalid EDID bpc value */
7908         if (connector->base.display_info.bpc &&
7909             connector->base.display_info.bpc * 3 < bpp) {
7910                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7911                               bpp, connector->base.display_info.bpc*3);
7912                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7913         }
7914
7915         /* Clamp bpp to 8 on screens without EDID 1.4 */
7916         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7917                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7918                               bpp);
7919                 pipe_config->pipe_bpp = 24;
7920         }
7921 }
7922
7923 static int
7924 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7925                           struct drm_framebuffer *fb,
7926                           struct intel_crtc_config *pipe_config)
7927 {
7928         struct drm_device *dev = crtc->base.dev;
7929         struct intel_connector *connector;
7930         int bpp;
7931
7932         switch (fb->pixel_format) {
7933         case DRM_FORMAT_C8:
7934                 bpp = 8*3; /* since we go through a colormap */
7935                 break;
7936         case DRM_FORMAT_XRGB1555:
7937         case DRM_FORMAT_ARGB1555:
7938                 /* checked in intel_framebuffer_init already */
7939                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7940                         return -EINVAL;
7941         case DRM_FORMAT_RGB565:
7942                 bpp = 6*3; /* min is 18bpp */
7943                 break;
7944         case DRM_FORMAT_XBGR8888:
7945         case DRM_FORMAT_ABGR8888:
7946                 /* checked in intel_framebuffer_init already */
7947                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7948                         return -EINVAL;
7949         case DRM_FORMAT_XRGB8888:
7950         case DRM_FORMAT_ARGB8888:
7951                 bpp = 8*3;
7952                 break;
7953         case DRM_FORMAT_XRGB2101010:
7954         case DRM_FORMAT_ARGB2101010:
7955         case DRM_FORMAT_XBGR2101010:
7956         case DRM_FORMAT_ABGR2101010:
7957                 /* checked in intel_framebuffer_init already */
7958                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7959                         return -EINVAL;
7960                 bpp = 10*3;
7961                 break;
7962         /* TODO: gen4+ supports 16 bpc floating point, too. */
7963         default:
7964                 DRM_DEBUG_KMS("unsupported depth\n");
7965                 return -EINVAL;
7966         }
7967
7968         pipe_config->pipe_bpp = bpp;
7969
7970         /* Clamp display bpp to EDID value */
7971         list_for_each_entry(connector, &dev->mode_config.connector_list,
7972                             base.head) {
7973                 if (!connector->new_encoder ||
7974                     connector->new_encoder->new_crtc != crtc)
7975                         continue;
7976
7977                 connected_sink_compute_bpp(connector, pipe_config);
7978         }
7979
7980         return bpp;
7981 }
7982
7983 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7984                                    struct intel_crtc_config *pipe_config,
7985                                    const char *context)
7986 {
7987         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7988                       context, pipe_name(crtc->pipe));
7989
7990         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7991         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7992                       pipe_config->pipe_bpp, pipe_config->dither);
7993         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7994                       pipe_config->has_pch_encoder,
7995                       pipe_config->fdi_lanes,
7996                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7997                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7998                       pipe_config->fdi_m_n.tu);
7999         DRM_DEBUG_KMS("requested mode:\n");
8000         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8001         DRM_DEBUG_KMS("adjusted mode:\n");
8002         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8003         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8004                       pipe_config->gmch_pfit.control,
8005                       pipe_config->gmch_pfit.pgm_ratios,
8006                       pipe_config->gmch_pfit.lvds_border_bits);
8007         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8008                       pipe_config->pch_pfit.pos,
8009                       pipe_config->pch_pfit.size);
8010         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8011 }
8012
8013 static bool check_encoder_cloning(struct drm_crtc *crtc)
8014 {
8015         int num_encoders = 0;
8016         bool uncloneable_encoders = false;
8017         struct intel_encoder *encoder;
8018
8019         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8020                             base.head) {
8021                 if (&encoder->new_crtc->base != crtc)
8022                         continue;
8023
8024                 num_encoders++;
8025                 if (!encoder->cloneable)
8026                         uncloneable_encoders = true;
8027         }
8028
8029         return !(num_encoders > 1 && uncloneable_encoders);
8030 }
8031
8032 static struct intel_crtc_config *
8033 intel_modeset_pipe_config(struct drm_crtc *crtc,
8034                           struct drm_framebuffer *fb,
8035                           struct drm_display_mode *mode)
8036 {
8037         struct drm_device *dev = crtc->dev;
8038         struct intel_encoder *encoder;
8039         struct intel_crtc_config *pipe_config;
8040         int plane_bpp, ret = -EINVAL;
8041         bool retry = true;
8042
8043         if (!check_encoder_cloning(crtc)) {
8044                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8045                 return ERR_PTR(-EINVAL);
8046         }
8047
8048         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8049         if (!pipe_config)
8050                 return ERR_PTR(-ENOMEM);
8051
8052         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8053         drm_mode_copy(&pipe_config->requested_mode, mode);
8054         pipe_config->cpu_transcoder =
8055                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8056         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8057
8058         /*
8059          * Sanitize sync polarity flags based on requested ones. If neither
8060          * positive or negative polarity is requested, treat this as meaning
8061          * negative polarity.
8062          */
8063         if (!(pipe_config->adjusted_mode.flags &
8064               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8065                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8066
8067         if (!(pipe_config->adjusted_mode.flags &
8068               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8069                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8070
8071         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8072          * plane pixel format and any sink constraints into account. Returns the
8073          * source plane bpp so that dithering can be selected on mismatches
8074          * after encoders and crtc also have had their say. */
8075         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8076                                               fb, pipe_config);
8077         if (plane_bpp < 0)
8078                 goto fail;
8079
8080 encoder_retry:
8081         /* Ensure the port clock defaults are reset when retrying. */
8082         pipe_config->port_clock = 0;
8083         pipe_config->pixel_multiplier = 1;
8084
8085         /* Fill in default crtc timings, allow encoders to overwrite them. */
8086         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8087
8088         /* Pass our mode to the connectors and the CRTC to give them a chance to
8089          * adjust it according to limitations or connector properties, and also
8090          * a chance to reject the mode entirely.
8091          */
8092         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8093                             base.head) {
8094
8095                 if (&encoder->new_crtc->base != crtc)
8096                         continue;
8097
8098                 if (!(encoder->compute_config(encoder, pipe_config))) {
8099                         DRM_DEBUG_KMS("Encoder config failure\n");
8100                         goto fail;
8101                 }
8102         }
8103
8104         /* Set default port clock if not overwritten by the encoder. Needs to be
8105          * done afterwards in case the encoder adjusts the mode. */
8106         if (!pipe_config->port_clock)
8107                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8108
8109         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8110         if (ret < 0) {
8111                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8112                 goto fail;
8113         }
8114
8115         if (ret == RETRY) {
8116                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8117                         ret = -EINVAL;
8118                         goto fail;
8119                 }
8120
8121                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8122                 retry = false;
8123                 goto encoder_retry;
8124         }
8125
8126         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8127         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8128                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8129
8130         return pipe_config;
8131 fail:
8132         kfree(pipe_config);
8133         return ERR_PTR(ret);
8134 }
8135
8136 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8137  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8138 static void
8139 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8140                              unsigned *prepare_pipes, unsigned *disable_pipes)
8141 {
8142         struct intel_crtc *intel_crtc;
8143         struct drm_device *dev = crtc->dev;
8144         struct intel_encoder *encoder;
8145         struct intel_connector *connector;
8146         struct drm_crtc *tmp_crtc;
8147
8148         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8149
8150         /* Check which crtcs have changed outputs connected to them, these need
8151          * to be part of the prepare_pipes mask. We don't (yet) support global
8152          * modeset across multiple crtcs, so modeset_pipes will only have one
8153          * bit set at most. */
8154         list_for_each_entry(connector, &dev->mode_config.connector_list,
8155                             base.head) {
8156                 if (connector->base.encoder == &connector->new_encoder->base)
8157                         continue;
8158
8159                 if (connector->base.encoder) {
8160                         tmp_crtc = connector->base.encoder->crtc;
8161
8162                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8163                 }
8164
8165                 if (connector->new_encoder)
8166                         *prepare_pipes |=
8167                                 1 << connector->new_encoder->new_crtc->pipe;
8168         }
8169
8170         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8171                             base.head) {
8172                 if (encoder->base.crtc == &encoder->new_crtc->base)
8173                         continue;
8174
8175                 if (encoder->base.crtc) {
8176                         tmp_crtc = encoder->base.crtc;
8177
8178                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8179                 }
8180
8181                 if (encoder->new_crtc)
8182                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8183         }
8184
8185         /* Check for any pipes that will be fully disabled ... */
8186         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8187                             base.head) {
8188                 bool used = false;
8189
8190                 /* Don't try to disable disabled crtcs. */
8191                 if (!intel_crtc->base.enabled)
8192                         continue;
8193
8194                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8195                                     base.head) {
8196                         if (encoder->new_crtc == intel_crtc)
8197                                 used = true;
8198                 }
8199
8200                 if (!used)
8201                         *disable_pipes |= 1 << intel_crtc->pipe;
8202         }
8203
8204
8205         /* set_mode is also used to update properties on life display pipes. */
8206         intel_crtc = to_intel_crtc(crtc);
8207         if (crtc->enabled)
8208                 *prepare_pipes |= 1 << intel_crtc->pipe;
8209
8210         /*
8211          * For simplicity do a full modeset on any pipe where the output routing
8212          * changed. We could be more clever, but that would require us to be
8213          * more careful with calling the relevant encoder->mode_set functions.
8214          */
8215         if (*prepare_pipes)
8216                 *modeset_pipes = *prepare_pipes;
8217
8218         /* ... and mask these out. */
8219         *modeset_pipes &= ~(*disable_pipes);
8220         *prepare_pipes &= ~(*disable_pipes);
8221
8222         /*
8223          * HACK: We don't (yet) fully support global modesets. intel_set_config
8224          * obies this rule, but the modeset restore mode of
8225          * intel_modeset_setup_hw_state does not.
8226          */
8227         *modeset_pipes &= 1 << intel_crtc->pipe;
8228         *prepare_pipes &= 1 << intel_crtc->pipe;
8229
8230         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8231                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8232 }
8233
8234 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8235 {
8236         struct drm_encoder *encoder;
8237         struct drm_device *dev = crtc->dev;
8238
8239         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8240                 if (encoder->crtc == crtc)
8241                         return true;
8242
8243         return false;
8244 }
8245
8246 static void
8247 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8248 {
8249         struct intel_encoder *intel_encoder;
8250         struct intel_crtc *intel_crtc;
8251         struct drm_connector *connector;
8252
8253         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8254                             base.head) {
8255                 if (!intel_encoder->base.crtc)
8256                         continue;
8257
8258                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8259
8260                 if (prepare_pipes & (1 << intel_crtc->pipe))
8261                         intel_encoder->connectors_active = false;
8262         }
8263
8264         intel_modeset_commit_output_state(dev);
8265
8266         /* Update computed state. */
8267         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8268                             base.head) {
8269                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8270         }
8271
8272         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8273                 if (!connector->encoder || !connector->encoder->crtc)
8274                         continue;
8275
8276                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8277
8278                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8279                         struct drm_property *dpms_property =
8280                                 dev->mode_config.dpms_property;
8281
8282                         connector->dpms = DRM_MODE_DPMS_ON;
8283                         drm_object_property_set_value(&connector->base,
8284                                                          dpms_property,
8285                                                          DRM_MODE_DPMS_ON);
8286
8287                         intel_encoder = to_intel_encoder(connector->encoder);
8288                         intel_encoder->connectors_active = true;
8289                 }
8290         }
8291
8292 }
8293
8294 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8295                                     struct intel_crtc_config *new)
8296 {
8297         int clock1, clock2, diff;
8298
8299         clock1 = cur->adjusted_mode.clock;
8300         clock2 = new->adjusted_mode.clock;
8301
8302         if (clock1 == clock2)
8303                 return true;
8304
8305         if (!clock1 || !clock2)
8306                 return false;
8307
8308         diff = abs(clock1 - clock2);
8309
8310         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8311                 return true;
8312
8313         return false;
8314 }
8315
8316 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8317         list_for_each_entry((intel_crtc), \
8318                             &(dev)->mode_config.crtc_list, \
8319                             base.head) \
8320                 if (mask & (1 <<(intel_crtc)->pipe))
8321
8322 static bool
8323 intel_pipe_config_compare(struct drm_device *dev,
8324                           struct intel_crtc_config *current_config,
8325                           struct intel_crtc_config *pipe_config)
8326 {
8327 #define PIPE_CONF_CHECK_X(name) \
8328         if (current_config->name != pipe_config->name) { \
8329                 DRM_ERROR("mismatch in " #name " " \
8330                           "(expected 0x%08x, found 0x%08x)\n", \
8331                           current_config->name, \
8332                           pipe_config->name); \
8333                 return false; \
8334         }
8335
8336 #define PIPE_CONF_CHECK_I(name) \
8337         if (current_config->name != pipe_config->name) { \
8338                 DRM_ERROR("mismatch in " #name " " \
8339                           "(expected %i, found %i)\n", \
8340                           current_config->name, \
8341                           pipe_config->name); \
8342                 return false; \
8343         }
8344
8345 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8346         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8347                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8348                           "(expected %i, found %i)\n", \
8349                           current_config->name & (mask), \
8350                           pipe_config->name & (mask)); \
8351                 return false; \
8352         }
8353
8354 #define PIPE_CONF_QUIRK(quirk)  \
8355         ((current_config->quirks | pipe_config->quirks) & (quirk))
8356
8357         PIPE_CONF_CHECK_I(cpu_transcoder);
8358
8359         PIPE_CONF_CHECK_I(has_pch_encoder);
8360         PIPE_CONF_CHECK_I(fdi_lanes);
8361         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8362         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8363         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8364         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8365         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8366
8367         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8368         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8369         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8370         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8371         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8372         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8373
8374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8375         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8376         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8377         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8378         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8379         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8380
8381         PIPE_CONF_CHECK_I(pixel_multiplier);
8382
8383         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8384                               DRM_MODE_FLAG_INTERLACE);
8385
8386         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8387                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8388                                       DRM_MODE_FLAG_PHSYNC);
8389                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390                                       DRM_MODE_FLAG_NHSYNC);
8391                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8392                                       DRM_MODE_FLAG_PVSYNC);
8393                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8394                                       DRM_MODE_FLAG_NVSYNC);
8395         }
8396
8397         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8398         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8399
8400         PIPE_CONF_CHECK_I(gmch_pfit.control);
8401         /* pfit ratios are autocomputed by the hw on gen4+ */
8402         if (INTEL_INFO(dev)->gen < 4)
8403                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8404         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8405         PIPE_CONF_CHECK_I(pch_pfit.pos);
8406         PIPE_CONF_CHECK_I(pch_pfit.size);
8407
8408         PIPE_CONF_CHECK_I(ips_enabled);
8409
8410         PIPE_CONF_CHECK_I(shared_dpll);
8411         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8412         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8413         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8414         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8415
8416 #undef PIPE_CONF_CHECK_X
8417 #undef PIPE_CONF_CHECK_I
8418 #undef PIPE_CONF_CHECK_FLAGS
8419 #undef PIPE_CONF_QUIRK
8420
8421         if (!IS_HASWELL(dev)) {
8422                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8423                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8424                                   current_config->adjusted_mode.clock,
8425                                   pipe_config->adjusted_mode.clock);
8426                         return false;
8427                 }
8428         }
8429
8430         return true;
8431 }
8432
8433 static void
8434 check_connector_state(struct drm_device *dev)
8435 {
8436         struct intel_connector *connector;
8437
8438         list_for_each_entry(connector, &dev->mode_config.connector_list,
8439                             base.head) {
8440                 /* This also checks the encoder/connector hw state with the
8441                  * ->get_hw_state callbacks. */
8442                 intel_connector_check_state(connector);
8443
8444                 WARN(&connector->new_encoder->base != connector->base.encoder,
8445                      "connector's staged encoder doesn't match current encoder\n");
8446         }
8447 }
8448
8449 static void
8450 check_encoder_state(struct drm_device *dev)
8451 {
8452         struct intel_encoder *encoder;
8453         struct intel_connector *connector;
8454
8455         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8456                             base.head) {
8457                 bool enabled = false;
8458                 bool active = false;
8459                 enum pipe pipe, tracked_pipe;
8460
8461                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8462                               encoder->base.base.id,
8463                               drm_get_encoder_name(&encoder->base));
8464
8465                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8466                      "encoder's stage crtc doesn't match current crtc\n");
8467                 WARN(encoder->connectors_active && !encoder->base.crtc,
8468                      "encoder's active_connectors set, but no crtc\n");
8469
8470                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8471                                     base.head) {
8472                         if (connector->base.encoder != &encoder->base)
8473                                 continue;
8474                         enabled = true;
8475                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8476                                 active = true;
8477                 }
8478                 WARN(!!encoder->base.crtc != enabled,
8479                      "encoder's enabled state mismatch "
8480                      "(expected %i, found %i)\n",
8481                      !!encoder->base.crtc, enabled);
8482                 WARN(active && !encoder->base.crtc,
8483                      "active encoder with no crtc\n");
8484
8485                 WARN(encoder->connectors_active != active,
8486                      "encoder's computed active state doesn't match tracked active state "
8487                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8488
8489                 active = encoder->get_hw_state(encoder, &pipe);
8490                 WARN(active != encoder->connectors_active,
8491                      "encoder's hw state doesn't match sw tracking "
8492                      "(expected %i, found %i)\n",
8493                      encoder->connectors_active, active);
8494
8495                 if (!encoder->base.crtc)
8496                         continue;
8497
8498                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8499                 WARN(active && pipe != tracked_pipe,
8500                      "active encoder's pipe doesn't match"
8501                      "(expected %i, found %i)\n",
8502                      tracked_pipe, pipe);
8503
8504         }
8505 }
8506
8507 static void
8508 check_crtc_state(struct drm_device *dev)
8509 {
8510         drm_i915_private_t *dev_priv = dev->dev_private;
8511         struct intel_crtc *crtc;
8512         struct intel_encoder *encoder;
8513         struct intel_crtc_config pipe_config;
8514
8515         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8516                             base.head) {
8517                 bool enabled = false;
8518                 bool active = false;
8519
8520                 memset(&pipe_config, 0, sizeof(pipe_config));
8521
8522                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8523                               crtc->base.base.id);
8524
8525                 WARN(crtc->active && !crtc->base.enabled,
8526                      "active crtc, but not enabled in sw tracking\n");
8527
8528                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8529                                     base.head) {
8530                         if (encoder->base.crtc != &crtc->base)
8531                                 continue;
8532                         enabled = true;
8533                         if (encoder->connectors_active)
8534                                 active = true;
8535                 }
8536
8537                 WARN(active != crtc->active,
8538                      "crtc's computed active state doesn't match tracked active state "
8539                      "(expected %i, found %i)\n", active, crtc->active);
8540                 WARN(enabled != crtc->base.enabled,
8541                      "crtc's computed enabled state doesn't match tracked enabled state "
8542                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8543
8544                 active = dev_priv->display.get_pipe_config(crtc,
8545                                                            &pipe_config);
8546
8547                 /* hw state is inconsistent with the pipe A quirk */
8548                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8549                         active = crtc->active;
8550
8551                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8552                                     base.head) {
8553                         if (encoder->base.crtc != &crtc->base)
8554                                 continue;
8555                         if (encoder->get_config)
8556                                 encoder->get_config(encoder, &pipe_config);
8557                 }
8558
8559                 if (dev_priv->display.get_clock)
8560                         dev_priv->display.get_clock(crtc, &pipe_config);
8561
8562                 WARN(crtc->active != active,
8563                      "crtc active state doesn't match with hw state "
8564                      "(expected %i, found %i)\n", crtc->active, active);
8565
8566                 if (active &&
8567                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8568                         WARN(1, "pipe state doesn't match!\n");
8569                         intel_dump_pipe_config(crtc, &pipe_config,
8570                                                "[hw state]");
8571                         intel_dump_pipe_config(crtc, &crtc->config,
8572                                                "[sw state]");
8573                 }
8574         }
8575 }
8576
8577 static void
8578 check_shared_dpll_state(struct drm_device *dev)
8579 {
8580         drm_i915_private_t *dev_priv = dev->dev_private;
8581         struct intel_crtc *crtc;
8582         struct intel_dpll_hw_state dpll_hw_state;
8583         int i;
8584
8585         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8586                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8587                 int enabled_crtcs = 0, active_crtcs = 0;
8588                 bool active;
8589
8590                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8591
8592                 DRM_DEBUG_KMS("%s\n", pll->name);
8593
8594                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8595
8596                 WARN(pll->active > pll->refcount,
8597                      "more active pll users than references: %i vs %i\n",
8598                      pll->active, pll->refcount);
8599                 WARN(pll->active && !pll->on,
8600                      "pll in active use but not on in sw tracking\n");
8601                 WARN(pll->on && !pll->active,
8602                      "pll in on but not on in use in sw tracking\n");
8603                 WARN(pll->on != active,
8604                      "pll on state mismatch (expected %i, found %i)\n",
8605                      pll->on, active);
8606
8607                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8608                                     base.head) {
8609                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8610                                 enabled_crtcs++;
8611                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8612                                 active_crtcs++;
8613                 }
8614                 WARN(pll->active != active_crtcs,
8615                      "pll active crtcs mismatch (expected %i, found %i)\n",
8616                      pll->active, active_crtcs);
8617                 WARN(pll->refcount != enabled_crtcs,
8618                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8619                      pll->refcount, enabled_crtcs);
8620
8621                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8622                                        sizeof(dpll_hw_state)),
8623                      "pll hw state mismatch\n");
8624         }
8625 }
8626
8627 void
8628 intel_modeset_check_state(struct drm_device *dev)
8629 {
8630         check_connector_state(dev);
8631         check_encoder_state(dev);
8632         check_crtc_state(dev);
8633         check_shared_dpll_state(dev);
8634 }
8635
8636 static int __intel_set_mode(struct drm_crtc *crtc,
8637                             struct drm_display_mode *mode,
8638                             int x, int y, struct drm_framebuffer *fb)
8639 {
8640         struct drm_device *dev = crtc->dev;
8641         drm_i915_private_t *dev_priv = dev->dev_private;
8642         struct drm_display_mode *saved_mode, *saved_hwmode;
8643         struct intel_crtc_config *pipe_config = NULL;
8644         struct intel_crtc *intel_crtc;
8645         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8646         int ret = 0;
8647
8648         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8649         if (!saved_mode)
8650                 return -ENOMEM;
8651         saved_hwmode = saved_mode + 1;
8652
8653         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8654                                      &prepare_pipes, &disable_pipes);
8655
8656         *saved_hwmode = crtc->hwmode;
8657         *saved_mode = crtc->mode;
8658
8659         /* Hack: Because we don't (yet) support global modeset on multiple
8660          * crtcs, we don't keep track of the new mode for more than one crtc.
8661          * Hence simply check whether any bit is set in modeset_pipes in all the
8662          * pieces of code that are not yet converted to deal with mutliple crtcs
8663          * changing their mode at the same time. */
8664         if (modeset_pipes) {
8665                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8666                 if (IS_ERR(pipe_config)) {
8667                         ret = PTR_ERR(pipe_config);
8668                         pipe_config = NULL;
8669
8670                         goto out;
8671                 }
8672                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8673                                        "[modeset]");
8674         }
8675
8676         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8677                 intel_crtc_disable(&intel_crtc->base);
8678
8679         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8680                 if (intel_crtc->base.enabled)
8681                         dev_priv->display.crtc_disable(&intel_crtc->base);
8682         }
8683
8684         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8685          * to set it here already despite that we pass it down the callchain.
8686          */
8687         if (modeset_pipes) {
8688                 crtc->mode = *mode;
8689                 /* mode_set/enable/disable functions rely on a correct pipe
8690                  * config. */
8691                 to_intel_crtc(crtc)->config = *pipe_config;
8692         }
8693
8694         /* Only after disabling all output pipelines that will be changed can we
8695          * update the the output configuration. */
8696         intel_modeset_update_state(dev, prepare_pipes);
8697
8698         if (dev_priv->display.modeset_global_resources)
8699                 dev_priv->display.modeset_global_resources(dev);
8700
8701         /* Set up the DPLL and any encoders state that needs to adjust or depend
8702          * on the DPLL.
8703          */
8704         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8705                 ret = intel_crtc_mode_set(&intel_crtc->base,
8706                                           x, y, fb);
8707                 if (ret)
8708                         goto done;
8709         }
8710
8711         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8712         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8713                 dev_priv->display.crtc_enable(&intel_crtc->base);
8714
8715         if (modeset_pipes) {
8716                 /* Store real post-adjustment hardware mode. */
8717                 crtc->hwmode = pipe_config->adjusted_mode;
8718
8719                 /* Calculate and store various constants which
8720                  * are later needed by vblank and swap-completion
8721                  * timestamping. They are derived from true hwmode.
8722                  */
8723                 drm_calc_timestamping_constants(crtc);
8724         }
8725
8726         /* FIXME: add subpixel order */
8727 done:
8728         if (ret && crtc->enabled) {
8729                 crtc->hwmode = *saved_hwmode;
8730                 crtc->mode = *saved_mode;
8731         }
8732
8733 out:
8734         kfree(pipe_config);
8735         kfree(saved_mode);
8736         return ret;
8737 }
8738
8739 static int intel_set_mode(struct drm_crtc *crtc,
8740                           struct drm_display_mode *mode,
8741                           int x, int y, struct drm_framebuffer *fb)
8742 {
8743         int ret;
8744
8745         ret = __intel_set_mode(crtc, mode, x, y, fb);
8746
8747         if (ret == 0)
8748                 intel_modeset_check_state(crtc->dev);
8749
8750         return ret;
8751 }
8752
8753 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8754 {
8755         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8756 }
8757
8758 #undef for_each_intel_crtc_masked
8759
8760 static void intel_set_config_free(struct intel_set_config *config)
8761 {
8762         if (!config)
8763                 return;
8764
8765         kfree(config->save_connector_encoders);
8766         kfree(config->save_encoder_crtcs);
8767         kfree(config);
8768 }
8769
8770 static int intel_set_config_save_state(struct drm_device *dev,
8771                                        struct intel_set_config *config)
8772 {
8773         struct drm_encoder *encoder;
8774         struct drm_connector *connector;
8775         int count;
8776
8777         config->save_encoder_crtcs =
8778                 kcalloc(dev->mode_config.num_encoder,
8779                         sizeof(struct drm_crtc *), GFP_KERNEL);
8780         if (!config->save_encoder_crtcs)
8781                 return -ENOMEM;
8782
8783         config->save_connector_encoders =
8784                 kcalloc(dev->mode_config.num_connector,
8785                         sizeof(struct drm_encoder *), GFP_KERNEL);
8786         if (!config->save_connector_encoders)
8787                 return -ENOMEM;
8788
8789         /* Copy data. Note that driver private data is not affected.
8790          * Should anything bad happen only the expected state is
8791          * restored, not the drivers personal bookkeeping.
8792          */
8793         count = 0;
8794         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8795                 config->save_encoder_crtcs[count++] = encoder->crtc;
8796         }
8797
8798         count = 0;
8799         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8800                 config->save_connector_encoders[count++] = connector->encoder;
8801         }
8802
8803         return 0;
8804 }
8805
8806 static void intel_set_config_restore_state(struct drm_device *dev,
8807                                            struct intel_set_config *config)
8808 {
8809         struct intel_encoder *encoder;
8810         struct intel_connector *connector;
8811         int count;
8812
8813         count = 0;
8814         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8815                 encoder->new_crtc =
8816                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8817         }
8818
8819         count = 0;
8820         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8821                 connector->new_encoder =
8822                         to_intel_encoder(config->save_connector_encoders[count++]);
8823         }
8824 }
8825
8826 static bool
8827 is_crtc_connector_off(struct drm_mode_set *set)
8828 {
8829         int i;
8830
8831         if (set->num_connectors == 0)
8832                 return false;
8833
8834         if (WARN_ON(set->connectors == NULL))
8835                 return false;
8836
8837         for (i = 0; i < set->num_connectors; i++)
8838                 if (set->connectors[i]->encoder &&
8839                     set->connectors[i]->encoder->crtc == set->crtc &&
8840                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8841                         return true;
8842
8843         return false;
8844 }
8845
8846 static void
8847 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8848                                       struct intel_set_config *config)
8849 {
8850
8851         /* We should be able to check here if the fb has the same properties
8852          * and then just flip_or_move it */
8853         if (is_crtc_connector_off(set)) {
8854                 config->mode_changed = true;
8855         } else if (set->crtc->fb != set->fb) {
8856                 /* If we have no fb then treat it as a full mode set */
8857                 if (set->crtc->fb == NULL) {
8858                         struct intel_crtc *intel_crtc =
8859                                 to_intel_crtc(set->crtc);
8860
8861                         if (intel_crtc->active && i915_fastboot) {
8862                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8863                                 config->fb_changed = true;
8864                         } else {
8865                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8866                                 config->mode_changed = true;
8867                         }
8868                 } else if (set->fb == NULL) {
8869                         config->mode_changed = true;
8870                 } else if (set->fb->pixel_format !=
8871                            set->crtc->fb->pixel_format) {
8872                         config->mode_changed = true;
8873                 } else {
8874                         config->fb_changed = true;
8875                 }
8876         }
8877
8878         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8879                 config->fb_changed = true;
8880
8881         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8882                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8883                 drm_mode_debug_printmodeline(&set->crtc->mode);
8884                 drm_mode_debug_printmodeline(set->mode);
8885                 config->mode_changed = true;
8886         }
8887 }
8888
8889 static int
8890 intel_modeset_stage_output_state(struct drm_device *dev,
8891                                  struct drm_mode_set *set,
8892                                  struct intel_set_config *config)
8893 {
8894         struct drm_crtc *new_crtc;
8895         struct intel_connector *connector;
8896         struct intel_encoder *encoder;
8897         int count, ro;
8898
8899         /* The upper layers ensure that we either disable a crtc or have a list
8900          * of connectors. For paranoia, double-check this. */
8901         WARN_ON(!set->fb && (set->num_connectors != 0));
8902         WARN_ON(set->fb && (set->num_connectors == 0));
8903
8904         count = 0;
8905         list_for_each_entry(connector, &dev->mode_config.connector_list,
8906                             base.head) {
8907                 /* Otherwise traverse passed in connector list and get encoders
8908                  * for them. */
8909                 for (ro = 0; ro < set->num_connectors; ro++) {
8910                         if (set->connectors[ro] == &connector->base) {
8911                                 connector->new_encoder = connector->encoder;
8912                                 break;
8913                         }
8914                 }
8915
8916                 /* If we disable the crtc, disable all its connectors. Also, if
8917                  * the connector is on the changing crtc but not on the new
8918                  * connector list, disable it. */
8919                 if ((!set->fb || ro == set->num_connectors) &&
8920                     connector->base.encoder &&
8921                     connector->base.encoder->crtc == set->crtc) {
8922                         connector->new_encoder = NULL;
8923
8924                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8925                                 connector->base.base.id,
8926                                 drm_get_connector_name(&connector->base));
8927                 }
8928
8929
8930                 if (&connector->new_encoder->base != connector->base.encoder) {
8931                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8932                         config->mode_changed = true;
8933                 }
8934         }
8935         /* connector->new_encoder is now updated for all connectors. */
8936
8937         /* Update crtc of enabled connectors. */
8938         count = 0;
8939         list_for_each_entry(connector, &dev->mode_config.connector_list,
8940                             base.head) {
8941                 if (!connector->new_encoder)
8942                         continue;
8943
8944                 new_crtc = connector->new_encoder->base.crtc;
8945
8946                 for (ro = 0; ro < set->num_connectors; ro++) {
8947                         if (set->connectors[ro] == &connector->base)
8948                                 new_crtc = set->crtc;
8949                 }
8950
8951                 /* Make sure the new CRTC will work with the encoder */
8952                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8953                                            new_crtc)) {
8954                         return -EINVAL;
8955                 }
8956                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8957
8958                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8959                         connector->base.base.id,
8960                         drm_get_connector_name(&connector->base),
8961                         new_crtc->base.id);
8962         }
8963
8964         /* Check for any encoders that needs to be disabled. */
8965         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8966                             base.head) {
8967                 list_for_each_entry(connector,
8968                                     &dev->mode_config.connector_list,
8969                                     base.head) {
8970                         if (connector->new_encoder == encoder) {
8971                                 WARN_ON(!connector->new_encoder->new_crtc);
8972
8973                                 goto next_encoder;
8974                         }
8975                 }
8976                 encoder->new_crtc = NULL;
8977 next_encoder:
8978                 /* Only now check for crtc changes so we don't miss encoders
8979                  * that will be disabled. */
8980                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8981                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8982                         config->mode_changed = true;
8983                 }
8984         }
8985         /* Now we've also updated encoder->new_crtc for all encoders. */
8986
8987         return 0;
8988 }
8989
8990 static int intel_crtc_set_config(struct drm_mode_set *set)
8991 {
8992         struct drm_device *dev;
8993         struct drm_mode_set save_set;
8994         struct intel_set_config *config;
8995         int ret;
8996
8997         BUG_ON(!set);
8998         BUG_ON(!set->crtc);
8999         BUG_ON(!set->crtc->helper_private);
9000
9001         /* Enforce sane interface api - has been abused by the fb helper. */
9002         BUG_ON(!set->mode && set->fb);
9003         BUG_ON(set->fb && set->num_connectors == 0);
9004
9005         if (set->fb) {
9006                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9007                                 set->crtc->base.id, set->fb->base.id,
9008                                 (int)set->num_connectors, set->x, set->y);
9009         } else {
9010                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9011         }
9012
9013         dev = set->crtc->dev;
9014
9015         ret = -ENOMEM;
9016         config = kzalloc(sizeof(*config), GFP_KERNEL);
9017         if (!config)
9018                 goto out_config;
9019
9020         ret = intel_set_config_save_state(dev, config);
9021         if (ret)
9022                 goto out_config;
9023
9024         save_set.crtc = set->crtc;
9025         save_set.mode = &set->crtc->mode;
9026         save_set.x = set->crtc->x;
9027         save_set.y = set->crtc->y;
9028         save_set.fb = set->crtc->fb;
9029
9030         /* Compute whether we need a full modeset, only an fb base update or no
9031          * change at all. In the future we might also check whether only the
9032          * mode changed, e.g. for LVDS where we only change the panel fitter in
9033          * such cases. */
9034         intel_set_config_compute_mode_changes(set, config);
9035
9036         ret = intel_modeset_stage_output_state(dev, set, config);
9037         if (ret)
9038                 goto fail;
9039
9040         if (config->mode_changed) {
9041                 ret = intel_set_mode(set->crtc, set->mode,
9042                                      set->x, set->y, set->fb);
9043         } else if (config->fb_changed) {
9044                 intel_crtc_wait_for_pending_flips(set->crtc);
9045
9046                 ret = intel_pipe_set_base(set->crtc,
9047                                           set->x, set->y, set->fb);
9048         }
9049
9050         if (ret) {
9051                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9052                               set->crtc->base.id, ret);
9053 fail:
9054                 intel_set_config_restore_state(dev, config);
9055
9056                 /* Try to restore the config */
9057                 if (config->mode_changed &&
9058                     intel_set_mode(save_set.crtc, save_set.mode,
9059                                    save_set.x, save_set.y, save_set.fb))
9060                         DRM_ERROR("failed to restore config after modeset failure\n");
9061         }
9062
9063 out_config:
9064         intel_set_config_free(config);
9065         return ret;
9066 }
9067
9068 static const struct drm_crtc_funcs intel_crtc_funcs = {
9069         .cursor_set = intel_crtc_cursor_set,
9070         .cursor_move = intel_crtc_cursor_move,
9071         .gamma_set = intel_crtc_gamma_set,
9072         .set_config = intel_crtc_set_config,
9073         .destroy = intel_crtc_destroy,
9074         .page_flip = intel_crtc_page_flip,
9075 };
9076
9077 static void intel_cpu_pll_init(struct drm_device *dev)
9078 {
9079         if (HAS_DDI(dev))
9080                 intel_ddi_pll_init(dev);
9081 }
9082
9083 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9084                                       struct intel_shared_dpll *pll,
9085                                       struct intel_dpll_hw_state *hw_state)
9086 {
9087         uint32_t val;
9088
9089         val = I915_READ(PCH_DPLL(pll->id));
9090         hw_state->dpll = val;
9091         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9092         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9093
9094         return val & DPLL_VCO_ENABLE;
9095 }
9096
9097 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9098                                   struct intel_shared_dpll *pll)
9099 {
9100         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9101         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9102 }
9103
9104 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9105                                 struct intel_shared_dpll *pll)
9106 {
9107         /* PCH refclock must be enabled first */
9108         assert_pch_refclk_enabled(dev_priv);
9109
9110         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9111
9112         /* Wait for the clocks to stabilize. */
9113         POSTING_READ(PCH_DPLL(pll->id));
9114         udelay(150);
9115
9116         /* The pixel multiplier can only be updated once the
9117          * DPLL is enabled and the clocks are stable.
9118          *
9119          * So write it again.
9120          */
9121         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9122         POSTING_READ(PCH_DPLL(pll->id));
9123         udelay(200);
9124 }
9125
9126 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9127                                  struct intel_shared_dpll *pll)
9128 {
9129         struct drm_device *dev = dev_priv->dev;
9130         struct intel_crtc *crtc;
9131
9132         /* Make sure no transcoder isn't still depending on us. */
9133         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9134                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9135                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9136         }
9137
9138         I915_WRITE(PCH_DPLL(pll->id), 0);
9139         POSTING_READ(PCH_DPLL(pll->id));
9140         udelay(200);
9141 }
9142
9143 static char *ibx_pch_dpll_names[] = {
9144         "PCH DPLL A",
9145         "PCH DPLL B",
9146 };
9147
9148 static void ibx_pch_dpll_init(struct drm_device *dev)
9149 {
9150         struct drm_i915_private *dev_priv = dev->dev_private;
9151         int i;
9152
9153         dev_priv->num_shared_dpll = 2;
9154
9155         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9156                 dev_priv->shared_dplls[i].id = i;
9157                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9158                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9159                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9160                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9161                 dev_priv->shared_dplls[i].get_hw_state =
9162                         ibx_pch_dpll_get_hw_state;
9163         }
9164 }
9165
9166 static void intel_shared_dpll_init(struct drm_device *dev)
9167 {
9168         struct drm_i915_private *dev_priv = dev->dev_private;
9169
9170         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9171                 ibx_pch_dpll_init(dev);
9172         else
9173                 dev_priv->num_shared_dpll = 0;
9174
9175         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9176         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9177                       dev_priv->num_shared_dpll);
9178 }
9179
9180 static void intel_crtc_init(struct drm_device *dev, int pipe)
9181 {
9182         drm_i915_private_t *dev_priv = dev->dev_private;
9183         struct intel_crtc *intel_crtc;
9184         int i;
9185
9186         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9187         if (intel_crtc == NULL)
9188                 return;
9189
9190         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9191
9192         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9193         for (i = 0; i < 256; i++) {
9194                 intel_crtc->lut_r[i] = i;
9195                 intel_crtc->lut_g[i] = i;
9196                 intel_crtc->lut_b[i] = i;
9197         }
9198
9199         /* Swap pipes & planes for FBC on pre-965 */
9200         intel_crtc->pipe = pipe;
9201         intel_crtc->plane = pipe;
9202         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9203                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9204                 intel_crtc->plane = !pipe;
9205         }
9206
9207         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9208                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9209         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9210         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9211
9212         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9213 }
9214
9215 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9216                                 struct drm_file *file)
9217 {
9218         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9219         struct drm_mode_object *drmmode_obj;
9220         struct intel_crtc *crtc;
9221
9222         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9223                 return -ENODEV;
9224
9225         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9226                         DRM_MODE_OBJECT_CRTC);
9227
9228         if (!drmmode_obj) {
9229                 DRM_ERROR("no such CRTC id\n");
9230                 return -EINVAL;
9231         }
9232
9233         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9234         pipe_from_crtc_id->pipe = crtc->pipe;
9235
9236         return 0;
9237 }
9238
9239 static int intel_encoder_clones(struct intel_encoder *encoder)
9240 {
9241         struct drm_device *dev = encoder->base.dev;
9242         struct intel_encoder *source_encoder;
9243         int index_mask = 0;
9244         int entry = 0;
9245
9246         list_for_each_entry(source_encoder,
9247                             &dev->mode_config.encoder_list, base.head) {
9248
9249                 if (encoder == source_encoder)
9250                         index_mask |= (1 << entry);
9251
9252                 /* Intel hw has only one MUX where enocoders could be cloned. */
9253                 if (encoder->cloneable && source_encoder->cloneable)
9254                         index_mask |= (1 << entry);
9255
9256                 entry++;
9257         }
9258
9259         return index_mask;
9260 }
9261
9262 static bool has_edp_a(struct drm_device *dev)
9263 {
9264         struct drm_i915_private *dev_priv = dev->dev_private;
9265
9266         if (!IS_MOBILE(dev))
9267                 return false;
9268
9269         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9270                 return false;
9271
9272         if (IS_GEN5(dev) &&
9273             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9274                 return false;
9275
9276         return true;
9277 }
9278
9279 static void intel_setup_outputs(struct drm_device *dev)
9280 {
9281         struct drm_i915_private *dev_priv = dev->dev_private;
9282         struct intel_encoder *encoder;
9283         bool dpd_is_edp = false;
9284
9285         intel_lvds_init(dev);
9286
9287         if (!IS_ULT(dev))
9288                 intel_crt_init(dev);
9289
9290         if (HAS_DDI(dev)) {
9291                 int found;
9292
9293                 /* Haswell uses DDI functions to detect digital outputs */
9294                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9295                 /* DDI A only supports eDP */
9296                 if (found)
9297                         intel_ddi_init(dev, PORT_A);
9298
9299                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9300                  * register */
9301                 found = I915_READ(SFUSE_STRAP);
9302
9303                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9304                         intel_ddi_init(dev, PORT_B);
9305                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9306                         intel_ddi_init(dev, PORT_C);
9307                 if (found & SFUSE_STRAP_DDID_DETECTED)
9308                         intel_ddi_init(dev, PORT_D);
9309         } else if (HAS_PCH_SPLIT(dev)) {
9310                 int found;
9311                 dpd_is_edp = intel_dpd_is_edp(dev);
9312
9313                 if (has_edp_a(dev))
9314                         intel_dp_init(dev, DP_A, PORT_A);
9315
9316                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9317                         /* PCH SDVOB multiplex with HDMIB */
9318                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9319                         if (!found)
9320                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9321                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9322                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9323                 }
9324
9325                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9326                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9327
9328                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9329                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9330
9331                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9332                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9333
9334                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9335                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9336         } else if (IS_VALLEYVIEW(dev)) {
9337                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9338                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9339                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9340                                         PORT_C);
9341                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9342                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9343                                               PORT_C);
9344                 }
9345
9346                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9347                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9348                                         PORT_B);
9349                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9350                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9351                 }
9352         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9353                 bool found = false;
9354
9355                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9356                         DRM_DEBUG_KMS("probing SDVOB\n");
9357                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9358                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9359                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9360                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9361                         }
9362
9363                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9364                                 intel_dp_init(dev, DP_B, PORT_B);
9365                 }
9366
9367                 /* Before G4X SDVOC doesn't have its own detect register */
9368
9369                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9370                         DRM_DEBUG_KMS("probing SDVOC\n");
9371                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9372                 }
9373
9374                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9375
9376                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9377                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9378                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9379                         }
9380                         if (SUPPORTS_INTEGRATED_DP(dev))
9381                                 intel_dp_init(dev, DP_C, PORT_C);
9382                 }
9383
9384                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9385                     (I915_READ(DP_D) & DP_DETECTED))
9386                         intel_dp_init(dev, DP_D, PORT_D);
9387         } else if (IS_GEN2(dev))
9388                 intel_dvo_init(dev);
9389
9390         if (SUPPORTS_TV(dev))
9391                 intel_tv_init(dev);
9392
9393         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9394                 encoder->base.possible_crtcs = encoder->crtc_mask;
9395                 encoder->base.possible_clones =
9396                         intel_encoder_clones(encoder);
9397         }
9398
9399         intel_init_pch_refclk(dev);
9400
9401         drm_helper_move_panel_connectors_to_head(dev);
9402 }
9403
9404 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9405 {
9406         drm_framebuffer_cleanup(&fb->base);
9407         drm_gem_object_unreference_unlocked(&fb->obj->base);
9408 }
9409
9410 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9411 {
9412         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9413
9414         intel_framebuffer_fini(intel_fb);
9415         kfree(intel_fb);
9416 }
9417
9418 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9419                                                 struct drm_file *file,
9420                                                 unsigned int *handle)
9421 {
9422         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9423         struct drm_i915_gem_object *obj = intel_fb->obj;
9424
9425         return drm_gem_handle_create(file, &obj->base, handle);
9426 }
9427
9428 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9429         .destroy = intel_user_framebuffer_destroy,
9430         .create_handle = intel_user_framebuffer_create_handle,
9431 };
9432
9433 int intel_framebuffer_init(struct drm_device *dev,
9434                            struct intel_framebuffer *intel_fb,
9435                            struct drm_mode_fb_cmd2 *mode_cmd,
9436                            struct drm_i915_gem_object *obj)
9437 {
9438         int pitch_limit;
9439         int ret;
9440
9441         if (obj->tiling_mode == I915_TILING_Y) {
9442                 DRM_DEBUG("hardware does not support tiling Y\n");
9443                 return -EINVAL;
9444         }
9445
9446         if (mode_cmd->pitches[0] & 63) {
9447                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9448                           mode_cmd->pitches[0]);
9449                 return -EINVAL;
9450         }
9451
9452         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9453                 pitch_limit = 32*1024;
9454         } else if (INTEL_INFO(dev)->gen >= 4) {
9455                 if (obj->tiling_mode)
9456                         pitch_limit = 16*1024;
9457                 else
9458                         pitch_limit = 32*1024;
9459         } else if (INTEL_INFO(dev)->gen >= 3) {
9460                 if (obj->tiling_mode)
9461                         pitch_limit = 8*1024;
9462                 else
9463                         pitch_limit = 16*1024;
9464         } else
9465                 /* XXX DSPC is limited to 4k tiled */
9466                 pitch_limit = 8*1024;
9467
9468         if (mode_cmd->pitches[0] > pitch_limit) {
9469                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9470                           obj->tiling_mode ? "tiled" : "linear",
9471                           mode_cmd->pitches[0], pitch_limit);
9472                 return -EINVAL;
9473         }
9474
9475         if (obj->tiling_mode != I915_TILING_NONE &&
9476             mode_cmd->pitches[0] != obj->stride) {
9477                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9478                           mode_cmd->pitches[0], obj->stride);
9479                 return -EINVAL;
9480         }
9481
9482         /* Reject formats not supported by any plane early. */
9483         switch (mode_cmd->pixel_format) {
9484         case DRM_FORMAT_C8:
9485         case DRM_FORMAT_RGB565:
9486         case DRM_FORMAT_XRGB8888:
9487         case DRM_FORMAT_ARGB8888:
9488                 break;
9489         case DRM_FORMAT_XRGB1555:
9490         case DRM_FORMAT_ARGB1555:
9491                 if (INTEL_INFO(dev)->gen > 3) {
9492                         DRM_DEBUG("unsupported pixel format: %s\n",
9493                                   drm_get_format_name(mode_cmd->pixel_format));
9494                         return -EINVAL;
9495                 }
9496                 break;
9497         case DRM_FORMAT_XBGR8888:
9498         case DRM_FORMAT_ABGR8888:
9499         case DRM_FORMAT_XRGB2101010:
9500         case DRM_FORMAT_ARGB2101010:
9501         case DRM_FORMAT_XBGR2101010:
9502         case DRM_FORMAT_ABGR2101010:
9503                 if (INTEL_INFO(dev)->gen < 4) {
9504                         DRM_DEBUG("unsupported pixel format: %s\n",
9505                                   drm_get_format_name(mode_cmd->pixel_format));
9506                         return -EINVAL;
9507                 }
9508                 break;
9509         case DRM_FORMAT_YUYV:
9510         case DRM_FORMAT_UYVY:
9511         case DRM_FORMAT_YVYU:
9512         case DRM_FORMAT_VYUY:
9513                 if (INTEL_INFO(dev)->gen < 5) {
9514                         DRM_DEBUG("unsupported pixel format: %s\n",
9515                                   drm_get_format_name(mode_cmd->pixel_format));
9516                         return -EINVAL;
9517                 }
9518                 break;
9519         default:
9520                 DRM_DEBUG("unsupported pixel format: %s\n",
9521                           drm_get_format_name(mode_cmd->pixel_format));
9522                 return -EINVAL;
9523         }
9524
9525         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9526         if (mode_cmd->offsets[0] != 0)
9527                 return -EINVAL;
9528
9529         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9530         intel_fb->obj = obj;
9531
9532         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9533         if (ret) {
9534                 DRM_ERROR("framebuffer init failed %d\n", ret);
9535                 return ret;
9536         }
9537
9538         return 0;
9539 }
9540
9541 static struct drm_framebuffer *
9542 intel_user_framebuffer_create(struct drm_device *dev,
9543                               struct drm_file *filp,
9544                               struct drm_mode_fb_cmd2 *mode_cmd)
9545 {
9546         struct drm_i915_gem_object *obj;
9547
9548         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9549                                                 mode_cmd->handles[0]));
9550         if (&obj->base == NULL)
9551                 return ERR_PTR(-ENOENT);
9552
9553         return intel_framebuffer_create(dev, mode_cmd, obj);
9554 }
9555
9556 static const struct drm_mode_config_funcs intel_mode_funcs = {
9557         .fb_create = intel_user_framebuffer_create,
9558         .output_poll_changed = intel_fb_output_poll_changed,
9559 };
9560
9561 /* Set up chip specific display functions */
9562 static void intel_init_display(struct drm_device *dev)
9563 {
9564         struct drm_i915_private *dev_priv = dev->dev_private;
9565
9566         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9567                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9568         else if (IS_VALLEYVIEW(dev))
9569                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9570         else if (IS_PINEVIEW(dev))
9571                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9572         else
9573                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9574
9575         if (HAS_DDI(dev)) {
9576                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9577                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9578                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9579                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9580                 dev_priv->display.off = haswell_crtc_off;
9581                 dev_priv->display.update_plane = ironlake_update_plane;
9582         } else if (HAS_PCH_SPLIT(dev)) {
9583                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9584                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9585                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9586                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9587                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9588                 dev_priv->display.off = ironlake_crtc_off;
9589                 dev_priv->display.update_plane = ironlake_update_plane;
9590         } else if (IS_VALLEYVIEW(dev)) {
9591                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9592                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9593                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9594                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9595                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9596                 dev_priv->display.off = i9xx_crtc_off;
9597                 dev_priv->display.update_plane = i9xx_update_plane;
9598         } else {
9599                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9600                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9601                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9602                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9603                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9604                 dev_priv->display.off = i9xx_crtc_off;
9605                 dev_priv->display.update_plane = i9xx_update_plane;
9606         }
9607
9608         /* Returns the core display clock speed */
9609         if (IS_VALLEYVIEW(dev))
9610                 dev_priv->display.get_display_clock_speed =
9611                         valleyview_get_display_clock_speed;
9612         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9613                 dev_priv->display.get_display_clock_speed =
9614                         i945_get_display_clock_speed;
9615         else if (IS_I915G(dev))
9616                 dev_priv->display.get_display_clock_speed =
9617                         i915_get_display_clock_speed;
9618         else if (IS_I945GM(dev) || IS_845G(dev))
9619                 dev_priv->display.get_display_clock_speed =
9620                         i9xx_misc_get_display_clock_speed;
9621         else if (IS_PINEVIEW(dev))
9622                 dev_priv->display.get_display_clock_speed =
9623                         pnv_get_display_clock_speed;
9624         else if (IS_I915GM(dev))
9625                 dev_priv->display.get_display_clock_speed =
9626                         i915gm_get_display_clock_speed;
9627         else if (IS_I865G(dev))
9628                 dev_priv->display.get_display_clock_speed =
9629                         i865_get_display_clock_speed;
9630         else if (IS_I85X(dev))
9631                 dev_priv->display.get_display_clock_speed =
9632                         i855_get_display_clock_speed;
9633         else /* 852, 830 */
9634                 dev_priv->display.get_display_clock_speed =
9635                         i830_get_display_clock_speed;
9636
9637         if (HAS_PCH_SPLIT(dev)) {
9638                 if (IS_GEN5(dev)) {
9639                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9640                         dev_priv->display.write_eld = ironlake_write_eld;
9641                 } else if (IS_GEN6(dev)) {
9642                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9643                         dev_priv->display.write_eld = ironlake_write_eld;
9644                 } else if (IS_IVYBRIDGE(dev)) {
9645                         /* FIXME: detect B0+ stepping and use auto training */
9646                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9647                         dev_priv->display.write_eld = ironlake_write_eld;
9648                         dev_priv->display.modeset_global_resources =
9649                                 ivb_modeset_global_resources;
9650                 } else if (IS_HASWELL(dev)) {
9651                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9652                         dev_priv->display.write_eld = haswell_write_eld;
9653                         dev_priv->display.modeset_global_resources =
9654                                 haswell_modeset_global_resources;
9655                 }
9656         } else if (IS_G4X(dev)) {
9657                 dev_priv->display.write_eld = g4x_write_eld;
9658         }
9659
9660         /* Default just returns -ENODEV to indicate unsupported */
9661         dev_priv->display.queue_flip = intel_default_queue_flip;
9662
9663         switch (INTEL_INFO(dev)->gen) {
9664         case 2:
9665                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9666                 break;
9667
9668         case 3:
9669                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9670                 break;
9671
9672         case 4:
9673         case 5:
9674                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9675                 break;
9676
9677         case 6:
9678                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9679                 break;
9680         case 7:
9681                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9682                 break;
9683         }
9684 }
9685
9686 /*
9687  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9688  * resume, or other times.  This quirk makes sure that's the case for
9689  * affected systems.
9690  */
9691 static void quirk_pipea_force(struct drm_device *dev)
9692 {
9693         struct drm_i915_private *dev_priv = dev->dev_private;
9694
9695         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9696         DRM_INFO("applying pipe a force quirk\n");
9697 }
9698
9699 /*
9700  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9701  */
9702 static void quirk_ssc_force_disable(struct drm_device *dev)
9703 {
9704         struct drm_i915_private *dev_priv = dev->dev_private;
9705         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9706         DRM_INFO("applying lvds SSC disable quirk\n");
9707 }
9708
9709 /*
9710  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9711  * brightness value
9712  */
9713 static void quirk_invert_brightness(struct drm_device *dev)
9714 {
9715         struct drm_i915_private *dev_priv = dev->dev_private;
9716         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9717         DRM_INFO("applying inverted panel brightness quirk\n");
9718 }
9719
9720 /*
9721  * Some machines (Dell XPS13) suffer broken backlight controls if
9722  * BLM_PCH_PWM_ENABLE is set.
9723  */
9724 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9725 {
9726         struct drm_i915_private *dev_priv = dev->dev_private;
9727         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9728         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9729 }
9730
9731 struct intel_quirk {
9732         int device;
9733         int subsystem_vendor;
9734         int subsystem_device;
9735         void (*hook)(struct drm_device *dev);
9736 };
9737
9738 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9739 struct intel_dmi_quirk {
9740         void (*hook)(struct drm_device *dev);
9741         const struct dmi_system_id (*dmi_id_list)[];
9742 };
9743
9744 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9745 {
9746         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9747         return 1;
9748 }
9749
9750 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9751         {
9752                 .dmi_id_list = &(const struct dmi_system_id[]) {
9753                         {
9754                                 .callback = intel_dmi_reverse_brightness,
9755                                 .ident = "NCR Corporation",
9756                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9757                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9758                                 },
9759                         },
9760                         { }  /* terminating entry */
9761                 },
9762                 .hook = quirk_invert_brightness,
9763         },
9764 };
9765
9766 static struct intel_quirk intel_quirks[] = {
9767         /* HP Mini needs pipe A force quirk (LP: #322104) */
9768         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9769
9770         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9771         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9772
9773         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9774         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9775
9776         /* 830/845 need to leave pipe A & dpll A up */
9777         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9778         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9779
9780         /* Lenovo U160 cannot use SSC on LVDS */
9781         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9782
9783         /* Sony Vaio Y cannot use SSC on LVDS */
9784         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9785
9786         /* Acer Aspire 5734Z must invert backlight brightness */
9787         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9788
9789         /* Acer/eMachines G725 */
9790         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9791
9792         /* Acer/eMachines e725 */
9793         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9794
9795         /* Acer/Packard Bell NCL20 */
9796         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9797
9798         /* Acer Aspire 4736Z */
9799         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9800
9801         /* Dell XPS13 HD Sandy Bridge */
9802         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9803         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9804         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9805 };
9806
9807 static void intel_init_quirks(struct drm_device *dev)
9808 {
9809         struct pci_dev *d = dev->pdev;
9810         int i;
9811
9812         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9813                 struct intel_quirk *q = &intel_quirks[i];
9814
9815                 if (d->device == q->device &&
9816                     (d->subsystem_vendor == q->subsystem_vendor ||
9817                      q->subsystem_vendor == PCI_ANY_ID) &&
9818                     (d->subsystem_device == q->subsystem_device ||
9819                      q->subsystem_device == PCI_ANY_ID))
9820                         q->hook(dev);
9821         }
9822         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9823                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9824                         intel_dmi_quirks[i].hook(dev);
9825         }
9826 }
9827
9828 /* Disable the VGA plane that we never use */
9829 static void i915_disable_vga(struct drm_device *dev)
9830 {
9831         struct drm_i915_private *dev_priv = dev->dev_private;
9832         u8 sr1;
9833         u32 vga_reg = i915_vgacntrl_reg(dev);
9834
9835         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9836         outb(SR01, VGA_SR_INDEX);
9837         sr1 = inb(VGA_SR_DATA);
9838         outb(sr1 | 1<<5, VGA_SR_DATA);
9839         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9840         udelay(300);
9841
9842         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9843         POSTING_READ(vga_reg);
9844 }
9845
9846 void intel_modeset_init_hw(struct drm_device *dev)
9847 {
9848         intel_init_power_well(dev);
9849
9850         intel_prepare_ddi(dev);
9851
9852         intel_init_clock_gating(dev);
9853
9854         mutex_lock(&dev->struct_mutex);
9855         intel_enable_gt_powersave(dev);
9856         mutex_unlock(&dev->struct_mutex);
9857 }
9858
9859 void intel_modeset_suspend_hw(struct drm_device *dev)
9860 {
9861         intel_suspend_hw(dev);
9862 }
9863
9864 void intel_modeset_init(struct drm_device *dev)
9865 {
9866         struct drm_i915_private *dev_priv = dev->dev_private;
9867         int i, j, ret;
9868
9869         drm_mode_config_init(dev);
9870
9871         dev->mode_config.min_width = 0;
9872         dev->mode_config.min_height = 0;
9873
9874         dev->mode_config.preferred_depth = 24;
9875         dev->mode_config.prefer_shadow = 1;
9876
9877         dev->mode_config.funcs = &intel_mode_funcs;
9878
9879         intel_init_quirks(dev);
9880
9881         intel_init_pm(dev);
9882
9883         if (INTEL_INFO(dev)->num_pipes == 0)
9884                 return;
9885
9886         intel_init_display(dev);
9887
9888         if (IS_GEN2(dev)) {
9889                 dev->mode_config.max_width = 2048;
9890                 dev->mode_config.max_height = 2048;
9891         } else if (IS_GEN3(dev)) {
9892                 dev->mode_config.max_width = 4096;
9893                 dev->mode_config.max_height = 4096;
9894         } else {
9895                 dev->mode_config.max_width = 8192;
9896                 dev->mode_config.max_height = 8192;
9897         }
9898         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9899
9900         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9901                       INTEL_INFO(dev)->num_pipes,
9902                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9903
9904         for_each_pipe(i) {
9905                 intel_crtc_init(dev, i);
9906                 for (j = 0; j < dev_priv->num_plane; j++) {
9907                         ret = intel_plane_init(dev, i, j);
9908                         if (ret)
9909                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9910                                               pipe_name(i), sprite_name(i, j), ret);
9911                 }
9912         }
9913
9914         intel_cpu_pll_init(dev);
9915         intel_shared_dpll_init(dev);
9916
9917         /* Just disable it once at startup */
9918         i915_disable_vga(dev);
9919         intel_setup_outputs(dev);
9920
9921         /* Just in case the BIOS is doing something questionable. */
9922         intel_disable_fbc(dev);
9923 }
9924
9925 static void
9926 intel_connector_break_all_links(struct intel_connector *connector)
9927 {
9928         connector->base.dpms = DRM_MODE_DPMS_OFF;
9929         connector->base.encoder = NULL;
9930         connector->encoder->connectors_active = false;
9931         connector->encoder->base.crtc = NULL;
9932 }
9933
9934 static void intel_enable_pipe_a(struct drm_device *dev)
9935 {
9936         struct intel_connector *connector;
9937         struct drm_connector *crt = NULL;
9938         struct intel_load_detect_pipe load_detect_temp;
9939
9940         /* We can't just switch on the pipe A, we need to set things up with a
9941          * proper mode and output configuration. As a gross hack, enable pipe A
9942          * by enabling the load detect pipe once. */
9943         list_for_each_entry(connector,
9944                             &dev->mode_config.connector_list,
9945                             base.head) {
9946                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9947                         crt = &connector->base;
9948                         break;
9949                 }
9950         }
9951
9952         if (!crt)
9953                 return;
9954
9955         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9956                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9957
9958
9959 }
9960
9961 static bool
9962 intel_check_plane_mapping(struct intel_crtc *crtc)
9963 {
9964         struct drm_device *dev = crtc->base.dev;
9965         struct drm_i915_private *dev_priv = dev->dev_private;
9966         u32 reg, val;
9967
9968         if (INTEL_INFO(dev)->num_pipes == 1)
9969                 return true;
9970
9971         reg = DSPCNTR(!crtc->plane);
9972         val = I915_READ(reg);
9973
9974         if ((val & DISPLAY_PLANE_ENABLE) &&
9975             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9976                 return false;
9977
9978         return true;
9979 }
9980
9981 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9982 {
9983         struct drm_device *dev = crtc->base.dev;
9984         struct drm_i915_private *dev_priv = dev->dev_private;
9985         u32 reg;
9986
9987         /* Clear any frame start delays used for debugging left by the BIOS */
9988         reg = PIPECONF(crtc->config.cpu_transcoder);
9989         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9990
9991         /* We need to sanitize the plane -> pipe mapping first because this will
9992          * disable the crtc (and hence change the state) if it is wrong. Note
9993          * that gen4+ has a fixed plane -> pipe mapping.  */
9994         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9995                 struct intel_connector *connector;
9996                 bool plane;
9997
9998                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9999                               crtc->base.base.id);
10000
10001                 /* Pipe has the wrong plane attached and the plane is active.
10002                  * Temporarily change the plane mapping and disable everything
10003                  * ...  */
10004                 plane = crtc->plane;
10005                 crtc->plane = !plane;
10006                 dev_priv->display.crtc_disable(&crtc->base);
10007                 crtc->plane = plane;
10008
10009                 /* ... and break all links. */
10010                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10011                                     base.head) {
10012                         if (connector->encoder->base.crtc != &crtc->base)
10013                                 continue;
10014
10015                         intel_connector_break_all_links(connector);
10016                 }
10017
10018                 WARN_ON(crtc->active);
10019                 crtc->base.enabled = false;
10020         }
10021
10022         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10023             crtc->pipe == PIPE_A && !crtc->active) {
10024                 /* BIOS forgot to enable pipe A, this mostly happens after
10025                  * resume. Force-enable the pipe to fix this, the update_dpms
10026                  * call below we restore the pipe to the right state, but leave
10027                  * the required bits on. */
10028                 intel_enable_pipe_a(dev);
10029         }
10030
10031         /* Adjust the state of the output pipe according to whether we
10032          * have active connectors/encoders. */
10033         intel_crtc_update_dpms(&crtc->base);
10034
10035         if (crtc->active != crtc->base.enabled) {
10036                 struct intel_encoder *encoder;
10037
10038                 /* This can happen either due to bugs in the get_hw_state
10039                  * functions or because the pipe is force-enabled due to the
10040                  * pipe A quirk. */
10041                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10042                               crtc->base.base.id,
10043                               crtc->base.enabled ? "enabled" : "disabled",
10044                               crtc->active ? "enabled" : "disabled");
10045
10046                 crtc->base.enabled = crtc->active;
10047
10048                 /* Because we only establish the connector -> encoder ->
10049                  * crtc links if something is active, this means the
10050                  * crtc is now deactivated. Break the links. connector
10051                  * -> encoder links are only establish when things are
10052                  *  actually up, hence no need to break them. */
10053                 WARN_ON(crtc->active);
10054
10055                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10056                         WARN_ON(encoder->connectors_active);
10057                         encoder->base.crtc = NULL;
10058                 }
10059         }
10060 }
10061
10062 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10063 {
10064         struct intel_connector *connector;
10065         struct drm_device *dev = encoder->base.dev;
10066
10067         /* We need to check both for a crtc link (meaning that the
10068          * encoder is active and trying to read from a pipe) and the
10069          * pipe itself being active. */
10070         bool has_active_crtc = encoder->base.crtc &&
10071                 to_intel_crtc(encoder->base.crtc)->active;
10072
10073         if (encoder->connectors_active && !has_active_crtc) {
10074                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10075                               encoder->base.base.id,
10076                               drm_get_encoder_name(&encoder->base));
10077
10078                 /* Connector is active, but has no active pipe. This is
10079                  * fallout from our resume register restoring. Disable
10080                  * the encoder manually again. */
10081                 if (encoder->base.crtc) {
10082                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10083                                       encoder->base.base.id,
10084                                       drm_get_encoder_name(&encoder->base));
10085                         encoder->disable(encoder);
10086                 }
10087
10088                 /* Inconsistent output/port/pipe state happens presumably due to
10089                  * a bug in one of the get_hw_state functions. Or someplace else
10090                  * in our code, like the register restore mess on resume. Clamp
10091                  * things to off as a safer default. */
10092                 list_for_each_entry(connector,
10093                                     &dev->mode_config.connector_list,
10094                                     base.head) {
10095                         if (connector->encoder != encoder)
10096                                 continue;
10097
10098                         intel_connector_break_all_links(connector);
10099                 }
10100         }
10101         /* Enabled encoders without active connectors will be fixed in
10102          * the crtc fixup. */
10103 }
10104
10105 void i915_redisable_vga(struct drm_device *dev)
10106 {
10107         struct drm_i915_private *dev_priv = dev->dev_private;
10108         u32 vga_reg = i915_vgacntrl_reg(dev);
10109
10110         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10111                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10112                 i915_disable_vga(dev);
10113         }
10114 }
10115
10116 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10117 {
10118         struct drm_i915_private *dev_priv = dev->dev_private;
10119         enum pipe pipe;
10120         struct intel_crtc *crtc;
10121         struct intel_encoder *encoder;
10122         struct intel_connector *connector;
10123         int i;
10124
10125         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10126                             base.head) {
10127                 memset(&crtc->config, 0, sizeof(crtc->config));
10128
10129                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10130                                                                  &crtc->config);
10131
10132                 crtc->base.enabled = crtc->active;
10133
10134                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10135                               crtc->base.base.id,
10136                               crtc->active ? "enabled" : "disabled");
10137         }
10138
10139         /* FIXME: Smash this into the new shared dpll infrastructure. */
10140         if (HAS_DDI(dev))
10141                 intel_ddi_setup_hw_pll_state(dev);
10142
10143         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10144                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10145
10146                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10147                 pll->active = 0;
10148                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10149                                     base.head) {
10150                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10151                                 pll->active++;
10152                 }
10153                 pll->refcount = pll->active;
10154
10155                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10156                               pll->name, pll->refcount, pll->on);
10157         }
10158
10159         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10160                             base.head) {
10161                 pipe = 0;
10162
10163                 if (encoder->get_hw_state(encoder, &pipe)) {
10164                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10165                         encoder->base.crtc = &crtc->base;
10166                         if (encoder->get_config)
10167                                 encoder->get_config(encoder, &crtc->config);
10168                 } else {
10169                         encoder->base.crtc = NULL;
10170                 }
10171
10172                 encoder->connectors_active = false;
10173                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10174                               encoder->base.base.id,
10175                               drm_get_encoder_name(&encoder->base),
10176                               encoder->base.crtc ? "enabled" : "disabled",
10177                               pipe);
10178         }
10179
10180         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10181                             base.head) {
10182                 if (!crtc->active)
10183                         continue;
10184                 if (dev_priv->display.get_clock)
10185                         dev_priv->display.get_clock(crtc,
10186                                                     &crtc->config);
10187         }
10188
10189         list_for_each_entry(connector, &dev->mode_config.connector_list,
10190                             base.head) {
10191                 if (connector->get_hw_state(connector)) {
10192                         connector->base.dpms = DRM_MODE_DPMS_ON;
10193                         connector->encoder->connectors_active = true;
10194                         connector->base.encoder = &connector->encoder->base;
10195                 } else {
10196                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10197                         connector->base.encoder = NULL;
10198                 }
10199                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10200                               connector->base.base.id,
10201                               drm_get_connector_name(&connector->base),
10202                               connector->base.encoder ? "enabled" : "disabled");
10203         }
10204 }
10205
10206 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10207  * and i915 state tracking structures. */
10208 void intel_modeset_setup_hw_state(struct drm_device *dev,
10209                                   bool force_restore)
10210 {
10211         struct drm_i915_private *dev_priv = dev->dev_private;
10212         enum pipe pipe;
10213         struct drm_plane *plane;
10214         struct intel_crtc *crtc;
10215         struct intel_encoder *encoder;
10216         int i;
10217
10218         intel_modeset_readout_hw_state(dev);
10219
10220         /*
10221          * Now that we have the config, copy it to each CRTC struct
10222          * Note that this could go away if we move to using crtc_config
10223          * checking everywhere.
10224          */
10225         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10226                             base.head) {
10227                 if (crtc->active && i915_fastboot) {
10228                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10229
10230                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10231                                       crtc->base.base.id);
10232                         drm_mode_debug_printmodeline(&crtc->base.mode);
10233                 }
10234         }
10235
10236         /* HW state is read out, now we need to sanitize this mess. */
10237         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10238                             base.head) {
10239                 intel_sanitize_encoder(encoder);
10240         }
10241
10242         for_each_pipe(pipe) {
10243                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10244                 intel_sanitize_crtc(crtc);
10245                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10246         }
10247
10248         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10249                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10250
10251                 if (!pll->on || pll->active)
10252                         continue;
10253
10254                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10255
10256                 pll->disable(dev_priv, pll);
10257                 pll->on = false;
10258         }
10259
10260         if (force_restore) {
10261                 /*
10262                  * We need to use raw interfaces for restoring state to avoid
10263                  * checking (bogus) intermediate states.
10264                  */
10265                 for_each_pipe(pipe) {
10266                         struct drm_crtc *crtc =
10267                                 dev_priv->pipe_to_crtc_mapping[pipe];
10268
10269                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10270                                          crtc->fb);
10271                 }
10272                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10273                         intel_plane_restore(plane);
10274
10275                 i915_redisable_vga(dev);
10276         } else {
10277                 intel_modeset_update_staged_output_state(dev);
10278         }
10279
10280         intel_modeset_check_state(dev);
10281
10282         drm_mode_config_reset(dev);
10283 }
10284
10285 void intel_modeset_gem_init(struct drm_device *dev)
10286 {
10287         intel_modeset_init_hw(dev);
10288
10289         intel_setup_overlay(dev);
10290
10291         intel_modeset_setup_hw_state(dev, false);
10292 }
10293
10294 void intel_modeset_cleanup(struct drm_device *dev)
10295 {
10296         struct drm_i915_private *dev_priv = dev->dev_private;
10297         struct drm_crtc *crtc;
10298         struct intel_crtc *intel_crtc;
10299
10300         /*
10301          * Interrupts and polling as the first thing to avoid creating havoc.
10302          * Too much stuff here (turning of rps, connectors, ...) would
10303          * experience fancy races otherwise.
10304          */
10305         drm_irq_uninstall(dev);
10306         cancel_work_sync(&dev_priv->hotplug_work);
10307         /*
10308          * Due to the hpd irq storm handling the hotplug work can re-arm the
10309          * poll handlers. Hence disable polling after hpd handling is shut down.
10310          */
10311         drm_kms_helper_poll_fini(dev);
10312
10313         mutex_lock(&dev->struct_mutex);
10314
10315         intel_unregister_dsm_handler();
10316
10317         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10318                 /* Skip inactive CRTCs */
10319                 if (!crtc->fb)
10320                         continue;
10321
10322                 intel_crtc = to_intel_crtc(crtc);
10323                 intel_increase_pllclock(crtc);
10324         }
10325
10326         intel_disable_fbc(dev);
10327
10328         intel_disable_gt_powersave(dev);
10329
10330         ironlake_teardown_rc6(dev);
10331
10332         mutex_unlock(&dev->struct_mutex);
10333
10334         /* flush any delayed tasks or pending work */
10335         flush_scheduled_work();
10336
10337         /* destroy backlight, if any, before the connectors */
10338         intel_panel_destroy_backlight(dev);
10339
10340         drm_mode_config_cleanup(dev);
10341
10342         intel_cleanup_overlay(dev);
10343 }
10344
10345 /*
10346  * Return which encoder is currently attached for connector.
10347  */
10348 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10349 {
10350         return &intel_attached_encoder(connector)->base;
10351 }
10352
10353 void intel_connector_attach_encoder(struct intel_connector *connector,
10354                                     struct intel_encoder *encoder)
10355 {
10356         connector->encoder = encoder;
10357         drm_mode_connector_attach_encoder(&connector->base,
10358                                           &encoder->base);
10359 }
10360
10361 /*
10362  * set vga decode state - true == enable VGA decode
10363  */
10364 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10365 {
10366         struct drm_i915_private *dev_priv = dev->dev_private;
10367         u16 gmch_ctrl;
10368
10369         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10370         if (state)
10371                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10372         else
10373                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10374         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10375         return 0;
10376 }
10377
10378 struct intel_display_error_state {
10379
10380         u32 power_well_driver;
10381
10382         struct intel_cursor_error_state {
10383                 u32 control;
10384                 u32 position;
10385                 u32 base;
10386                 u32 size;
10387         } cursor[I915_MAX_PIPES];
10388
10389         struct intel_pipe_error_state {
10390                 enum transcoder cpu_transcoder;
10391                 u32 conf;
10392                 u32 source;
10393
10394                 u32 htotal;
10395                 u32 hblank;
10396                 u32 hsync;
10397                 u32 vtotal;
10398                 u32 vblank;
10399                 u32 vsync;
10400         } pipe[I915_MAX_PIPES];
10401
10402         struct intel_plane_error_state {
10403                 u32 control;
10404                 u32 stride;
10405                 u32 size;
10406                 u32 pos;
10407                 u32 addr;
10408                 u32 surface;
10409                 u32 tile_offset;
10410         } plane[I915_MAX_PIPES];
10411 };
10412
10413 struct intel_display_error_state *
10414 intel_display_capture_error_state(struct drm_device *dev)
10415 {
10416         drm_i915_private_t *dev_priv = dev->dev_private;
10417         struct intel_display_error_state *error;
10418         enum transcoder cpu_transcoder;
10419         int i;
10420
10421         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10422         if (error == NULL)
10423                 return NULL;
10424
10425         if (HAS_POWER_WELL(dev))
10426                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10427
10428         for_each_pipe(i) {
10429                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10430                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10431
10432                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10433                         error->cursor[i].control = I915_READ(CURCNTR(i));
10434                         error->cursor[i].position = I915_READ(CURPOS(i));
10435                         error->cursor[i].base = I915_READ(CURBASE(i));
10436                 } else {
10437                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10438                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10439                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10440                 }
10441
10442                 error->plane[i].control = I915_READ(DSPCNTR(i));
10443                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10444                 if (INTEL_INFO(dev)->gen <= 3) {
10445                         error->plane[i].size = I915_READ(DSPSIZE(i));
10446                         error->plane[i].pos = I915_READ(DSPPOS(i));
10447                 }
10448                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10449                         error->plane[i].addr = I915_READ(DSPADDR(i));
10450                 if (INTEL_INFO(dev)->gen >= 4) {
10451                         error->plane[i].surface = I915_READ(DSPSURF(i));
10452                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10453                 }
10454
10455                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10456                 error->pipe[i].source = I915_READ(PIPESRC(i));
10457                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10458                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10459                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10460                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10461                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10462                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10463         }
10464
10465         /* In the code above we read the registers without checking if the power
10466          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10467          * prevent the next I915_WRITE from detecting it and printing an error
10468          * message. */
10469         intel_uncore_clear_errors(dev);
10470
10471         return error;
10472 }
10473
10474 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10475
10476 void
10477 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10478                                 struct drm_device *dev,
10479                                 struct intel_display_error_state *error)
10480 {
10481         int i;
10482
10483         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10484         if (HAS_POWER_WELL(dev))
10485                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10486                            error->power_well_driver);
10487         for_each_pipe(i) {
10488                 err_printf(m, "Pipe [%d]:\n", i);
10489                 err_printf(m, "  CPU transcoder: %c\n",
10490                            transcoder_name(error->pipe[i].cpu_transcoder));
10491                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10492                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10493                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10494                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10495                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10496                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10497                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10498                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10499
10500                 err_printf(m, "Plane [%d]:\n", i);
10501                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10502                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10503                 if (INTEL_INFO(dev)->gen <= 3) {
10504                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10505                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10506                 }
10507                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10508                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10509                 if (INTEL_INFO(dev)->gen >= 4) {
10510                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10511                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10512                 }
10513
10514                 err_printf(m, "Cursor [%d]:\n", i);
10515                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10516                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10517                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10518         }
10519 }