2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
65 typedef struct intel_limit intel_limit_t;
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 intel_pch_rawclk(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private;
76 WARN_ON(!HAS_PCH_SPLIT(dev));
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
312 static const intel_limit_t intel_limits_vlv = {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk, intel_clock_t *clock)
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
337 * Returns whether any output on the specified pipe is of the specified type
339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 struct drm_device *dev = crtc->dev;
355 const intel_limit_t *limit;
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
358 if (intel_is_dual_link_lvds(dev)) {
359 if (refclk == 100000)
360 limit = &intel_limits_ironlake_dual_lvds_100m;
362 limit = &intel_limits_ironlake_dual_lvds;
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_single_lvds_100m;
367 limit = &intel_limits_ironlake_single_lvds;
370 limit = &intel_limits_ironlake_dac;
375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
377 struct drm_device *dev = crtc->dev;
378 const intel_limit_t *limit;
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
381 if (intel_is_dual_link_lvds(dev))
382 limit = &intel_limits_g4x_dual_channel_lvds;
384 limit = &intel_limits_g4x_single_channel_lvds;
385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
387 limit = &intel_limits_g4x_hdmi;
388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
389 limit = &intel_limits_g4x_sdvo;
390 } else /* The option is for other outputs */
391 limit = &intel_limits_i9xx_sdvo;
396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
401 if (HAS_PCH_SPLIT(dev))
402 limit = intel_ironlake_limit(crtc, refclk);
403 else if (IS_G4X(dev)) {
404 limit = intel_g4x_limit(crtc);
405 } else if (IS_PINEVIEW(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_pineview_lvds;
409 limit = &intel_limits_pineview_sdvo;
410 } else if (IS_VALLEYVIEW(dev)) {
411 limit = &intel_limits_vlv;
412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
416 limit = &intel_limits_i9xx_sdvo;
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i8xx_lvds;
420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
421 limit = &intel_limits_i8xx_dvo;
423 limit = &intel_limits_i8xx_dac;
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk, intel_clock_t *clock)
431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
442 static void i9xx_clock(int refclk, intel_clock_t *clock)
444 clock->m = i9xx_dpll_compute_m(clock);
445 clock->p = clock->p1 * clock->p2;
446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
456 static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
467 INTELPllInvalid("m1 out of range\n");
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
496 struct drm_device *dev = crtc->dev;
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
509 clock.p2 = limit->p2.p2_slow;
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
514 clock.p2 = limit->p2.p2_fast;
517 memset(best_clock, 0, sizeof(*best_clock));
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
536 clock.p != match_clock->p)
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
549 return (err != target);
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
557 struct drm_device *dev = crtc->dev;
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
570 clock.p2 = limit->p2.p2_slow;
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
575 clock.p2 = limit->p2.p2_fast;
578 memset(best_clock, 0, sizeof(*best_clock));
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
595 clock.p != match_clock->p)
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
608 return (err != target);
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
616 struct drm_device *dev = crtc->dev;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
628 clock.p2 = limit->p2.p2_slow;
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
633 clock.p2 = limit->p2.p2_fast;
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
673 struct drm_device *dev = crtc->dev;
675 unsigned int bestppm = 1000000;
676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
680 target *= 5; /* fast clock */
682 memset(best_clock, 0, sizeof(*best_clock));
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
689 clock.p = clock.p1 * clock.p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
692 unsigned int ppm, diff;
694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
697 vlv_clock(refclk, &clock);
699 if (!intel_PLL_is_valid(dev, limit,
703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
706 if (ppm < 100 && clock.p > best_clock->p) {
712 if (bestppm >= 10 && ppm < bestppm - 10) {
725 bool intel_crtc_active(struct drm_crtc *crtc)
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
738 return intel_crtc->active && crtc->fb &&
739 intel_crtc->config.adjusted_mode.crtc_clock;
742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
748 return intel_crtc->config.cpu_transcoder;
751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
756 frame = I915_READ(frame_reg);
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_vblank - wait for vblank on a given pipe
765 * @pipe: pipe to wait for
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
772 struct drm_i915_private *dev_priv = dev->dev_private;
773 int pipestat_reg = PIPESTAT(pipe);
775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
800 DRM_DEBUG_KMS("vblank wait timed out\n");
803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
811 line_mask = DSL_LINEMASK_GEN2;
813 line_mask = DSL_LINEMASK_GEN3;
815 line1 = I915_READ(reg) & line_mask;
817 line2 = I915_READ(reg) & line_mask;
819 return line1 == line2;
823 * intel_wait_for_pipe_off - wait for pipe to turn off
825 * @pipe: pipe to wait for
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
832 * wait for the pipe register state bit to turn off
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
845 if (INTEL_INFO(dev)->gen >= 4) {
846 int reg = PIPECONF(cpu_transcoder);
848 /* Wait for the Pipe State to go off */
849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
851 WARN(1, "pipe_off wait timed out\n");
853 /* Wait for the display line to settle */
854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
855 WARN(1, "pipe_off wait timed out\n");
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
864 * Returns true if @port is connected, false otherwise.
866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
871 if (HAS_PCH_IBX(dev_priv->dev)) {
874 bit = SDE_PORTB_HOTPLUG;
877 bit = SDE_PORTC_HOTPLUG;
880 bit = SDE_PORTD_HOTPLUG;
888 bit = SDE_PORTB_HOTPLUG_CPT;
891 bit = SDE_PORTC_HOTPLUG_CPT;
894 bit = SDE_PORTD_HOTPLUG_CPT;
901 return I915_READ(SDEISR) & bit;
904 static const char *state_string(bool enabled)
906 return enabled ? "on" : "off";
909 /* Only for pre-ILK configs */
910 void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
925 /* XXX: the dsi pll is shared between MIPI DSI ports */
926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
943 struct intel_shared_dpll *
944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
948 if (crtc->config.shared_dpll < 0)
951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
960 struct intel_dpll_hw_state hw_state;
962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
968 "asserting DPLL %s with no DPLL\n", state_string(state)))
971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
972 WARN(cur_state != state,
973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
989 val = I915_READ(reg);
990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
1013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031 if (HAS_DDI(dev_priv->dev))
1034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1057 int pp_reg, lvds_reg;
1059 enum pipe panel_pipe = PIPE_A;
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1066 pp_reg = PP_CONTROL;
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1086 struct drm_device *dev = dev_priv->dev;
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
1127 pipe_name(pipe), state_string(state), state_string(cur_state));
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1151 struct drm_device *dev = dev_priv->dev;
1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
1158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1166 /* Need to check both planes against the pipe */
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1181 struct drm_device *dev = dev_priv->dev;
1185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1195 val = I915_READ(reg);
1196 WARN((val & SPRITE_ENABLE),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & DVS_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 reg = PCH_TRANSCONF(pipe);
1232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
1242 if ((val & DP_PORT_EN) == 0)
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1260 if ((val & SDVO_ENABLE) == 0)
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1276 if ((val & LVDS_PORT_EN) == 0)
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, int reg, u32 port_sel)
1307 u32 val = I915_READ(reg);
1308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310 reg, pipe_name(pipe));
1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
1314 "IBX PCH dp port still using transcoder B\n");
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1320 u32 val = I915_READ(reg);
1321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323 reg, pipe_name(pipe));
1325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326 && (val & SDVO_PIPE_B_SELECT),
1327 "IBX PCH hdmi port still using transcoder B\n");
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1341 val = I915_READ(reg);
1342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
1347 val = I915_READ(reg);
1348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1357 static void intel_init_dpio(struct drm_device *dev)
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1361 if (!IS_VALLEYVIEW(dev))
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
1384 assert_pipe_disabled(dev_priv, crtc->pipe);
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391 assert_panel_unlocked(dev_priv, crtc->pipe);
1393 I915_WRITE(reg, dpll);
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
1403 /* We do this three times for luck */
1404 I915_WRITE(reg, dpll);
1406 udelay(150); /* wait for warmup */
1407 I915_WRITE(reg, dpll);
1409 udelay(150); /* wait for warmup */
1410 I915_WRITE(reg, dpll);
1412 udelay(150); /* wait for warmup */
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
1422 assert_pipe_disabled(dev_priv, crtc->pipe);
1424 /* No really, not for ILK+ */
1425 BUG_ON(dev_priv->info->gen >= 5);
1427 /* PLL is protected by panel, make sure we can write it */
1428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
1431 I915_WRITE(reg, dpll);
1433 /* Wait for the clocks to stabilize. */
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1444 * So write it again.
1446 I915_WRITE(reg, dpll);
1449 /* We do this three times for luck */
1450 I915_WRITE(reg, dpll);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg, dpll);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg, dpll);
1458 udelay(150); /* wait for warmup */
1462 * i9xx_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 * Note! This is for pre-ILK only.
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1490 /* Leave integrated clock source enabled */
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1504 port_mask = DPLL_PORTC_READY_MASK;
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1512 * ironlake_enable_shared_dpll - enable PCH PLL
1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1524 /* PCH PLLs only available on ILK, SNB and IVB */
1525 BUG_ON(dev_priv->info->gen < 5);
1526 if (WARN_ON(pll == NULL))
1529 if (WARN_ON(pll->refcount == 0))
1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
1534 crtc->base.base.id);
1536 if (pll->active++) {
1538 assert_shared_dpll_enabled(dev_priv, pll);
1543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544 pll->enable(dev_priv, pll);
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
1555 if (WARN_ON(pll == NULL))
1558 if (WARN_ON(pll->refcount == 0))
1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
1563 crtc->base.base.id);
1565 if (WARN_ON(pll->active == 0)) {
1566 assert_shared_dpll_disabled(dev_priv, pll);
1570 assert_shared_dpll_enabled(dev_priv, pll);
1575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576 pll->disable(dev_priv, pll);
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1583 struct drm_device *dev = dev_priv->dev;
1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586 uint32_t reg, val, pipeconf_val;
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1591 /* Make sure PCH DPLL is enabled */
1592 assert_shared_dpll_enabled(dev_priv,
1593 intel_crtc_to_shared_dpll(intel_crtc));
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
1608 reg = PCH_TRANSCONF(pipe);
1609 val = I915_READ(reg);
1610 pipeconf_val = I915_READ(PIPECONF(pipe));
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1627 val |= TRANS_INTERLACED;
1629 val |= TRANS_PROGRESSIVE;
1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637 enum transcoder cpu_transcoder)
1639 u32 val, pipeconf_val;
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
1658 val |= TRANS_INTERLACED;
1660 val |= TRANS_PROGRESSIVE;
1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1670 struct drm_device *dev = dev_priv->dev;
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1680 reg = PCH_TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1701 val = I915_READ(LPT_TRANSCONF);
1702 val &= ~TRANS_ENABLE;
1703 I915_WRITE(LPT_TRANSCONF, val);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(_TRANSA_CHICKEN2, val);
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1723 * @pipe should be %PIPE_A or %PIPE_B.
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port, bool dsi)
1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1733 enum pipe pch_transcoder;
1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_cursor_disabled(dev_priv, pipe);
1739 assert_sprites_disabled(dev_priv, pipe);
1741 if (HAS_PCH_LPT(dev_priv->dev))
1742 pch_transcoder = TRANSCODER_A;
1744 pch_transcoder = pipe;
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
1753 assert_dsi_pll_enabled(dev_priv);
1755 assert_pll_enabled(dev_priv, pipe);
1758 /* if driving the PCH, we need FDI enabled */
1759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
1763 /* FIXME: assert CPU port conditions for SNB+ */
1766 reg = PIPECONF(cpu_transcoder);
1767 val = I915_READ(reg);
1768 if (val & PIPECONF_ENABLE)
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1776 * intel_disable_pipe - disable a pipe, asserting requirements
1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1783 * @pipe should be %PIPE_A or %PIPE_B.
1785 * Will wait until the pipe has shut down before returning.
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1799 assert_planes_disabled(dev_priv, pipe);
1800 assert_cursor_disabled(dev_priv, pipe);
1801 assert_sprites_disabled(dev_priv, pipe);
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1807 reg = PIPECONF(cpu_transcoder);
1808 val = I915_READ(reg);
1809 if ((val & PIPECONF_ENABLE) == 0)
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1825 I915_WRITE(reg, I915_READ(reg));
1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
1840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1850 intel_crtc->primary_enabled = true;
1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
1854 if (val & DISPLAY_PLANE_ENABLE)
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858 intel_flush_primary_plane(dev_priv, plane);
1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1863 * intel_disable_primary_plane - disable the primary plane
1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1868 * Disable @plane; should be an independent operation.
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
1873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1880 intel_crtc->primary_enabled = false;
1882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
1884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888 intel_flush_primary_plane(dev_priv, plane);
1889 intel_wait_for_vblank(dev_priv->dev, pipe);
1892 static bool need_vtd_wa(struct drm_device *dev)
1894 #ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903 struct drm_i915_gem_object *obj,
1904 struct intel_ring_buffer *pipelined)
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1910 switch (obj->tiling_mode) {
1911 case I915_TILING_NONE:
1912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
1914 else if (INTEL_INFO(dev)->gen >= 4)
1915 alignment = 4 * 1024;
1917 alignment = 64 * 1024;
1920 /* pin() will align the object as required by fence */
1924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1938 dev_priv->mm.interruptible = false;
1939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1941 goto err_interruptible;
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1948 ret = i915_gem_object_get_fence(obj);
1952 i915_gem_object_pin_fence(obj);
1954 dev_priv->mm.interruptible = true;
1958 i915_gem_object_unpin_from_display_plane(obj);
1960 dev_priv->mm.interruptible = true;
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1966 i915_gem_object_unpin_fence(obj);
1967 i915_gem_object_unpin_from_display_plane(obj);
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
1983 tiles = *x / (512/cpp);
1986 return tile_rows * pitch * 8 + tiles * 4096;
1988 unsigned int offset;
1990 offset = *y * pitch + *x * cpp;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
2004 struct drm_i915_gem_object *obj;
2005 int plane = intel_crtc->plane;
2006 unsigned long linear_offset;
2015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
2022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
2024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026 switch (fb->pixel_format) {
2028 dspcntr |= DISPPLANE_8BPP;
2030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
2034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
2057 if (INTEL_INFO(dev)->gen >= 4) {
2058 if (obj->tiling_mode != I915_TILING_NONE)
2059 dspcntr |= DISPPLANE_TILED;
2061 dspcntr &= ~DISPPLANE_TILED;
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2067 I915_WRITE(reg, dspcntr);
2069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
2073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2076 linear_offset -= intel_crtc->dspaddr_offset;
2078 intel_crtc->dspaddr_offset = linear_offset;
2081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085 if (INTEL_INFO(dev)->gen >= 4) {
2086 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
2091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
2106 unsigned long linear_offset;
2116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127 switch (fb->pixel_format) {
2129 dspcntr |= DISPPLANE_8BPP;
2131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2157 dspcntr &= ~DISPPLANE_TILED;
2159 if (IS_HASWELL(dev))
2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2164 I915_WRITE(reg, dspcntr);
2166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167 intel_crtc->dspaddr_offset =
2168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2171 linear_offset -= intel_crtc->dspaddr_offset;
2173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177 I915_MODIFY_DISPBASE(DSPSURF(plane),
2178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
2200 intel_increase_pllclock(crtc);
2202 return dev_priv->display.update_plane(crtc, fb, x, y);
2205 void intel_display_handle_reset(struct drm_device *dev)
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2239 mutex_unlock(&crtc->mutex);
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2272 if (!dev->primary->master)
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2279 switch (intel_crtc->pipe) {
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295 struct drm_framebuffer *fb)
2297 struct drm_device *dev = crtc->dev;
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300 struct drm_framebuffer *old_fb;
2305 DRM_ERROR("No FB bound\n");
2309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
2316 mutex_lock(&dev->struct_mutex);
2317 ret = intel_pin_and_fence_fb_obj(dev,
2318 to_intel_framebuffer(fb)->obj,
2321 mutex_unlock(&dev->struct_mutex);
2322 DRM_ERROR("pin & fence failed\n");
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2339 if (i915_fastboot) {
2340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2343 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
2346 if (!intel_crtc->config.pch_pfit.enabled &&
2347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358 mutex_unlock(&dev->struct_mutex);
2359 DRM_ERROR("failed to update base address\n");
2369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
2371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2374 intel_update_fbc(dev);
2375 intel_edp_psr_update(dev);
2376 mutex_unlock(&dev->struct_mutex);
2378 intel_crtc_update_sarea_pos(crtc, x, y);
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
2394 if (IS_IVYBRIDGE(dev)) {
2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2401 I915_WRITE(reg, temp);
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2414 /* wait one idle pattern time */
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
2424 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2426 return crtc->base.enabled && crtc->active &&
2427 crtc->config.has_pch_encoder;
2430 static void ivb_modeset_global_resources(struct drm_device *dev)
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *pipe_B_crtc =
2434 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435 struct intel_crtc *pipe_C_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2440 * When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. Note that we don't care about enabled pipes without
2442 * an enabled pch encoder.
2444 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445 !pipe_has_enabled_pch(pipe_C_crtc)) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2456 /* The FDI link training functions for ILK/Ibexpeak. */
2457 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
2463 int plane = intel_crtc->plane;
2464 u32 reg, temp, tries;
2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
2476 I915_WRITE(reg, temp);
2480 /* enable CPU FDI TX and PCH FDI RX */
2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
2503 reg = FDI_RX_IIR(pipe);
2504 for (tries = 0; tries < 5; tries++) {
2505 temp = I915_READ(reg);
2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2515 DRM_ERROR("FDI train 1 fail!\n");
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
2522 I915_WRITE(reg, temp);
2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
2528 I915_WRITE(reg, temp);
2533 reg = FDI_RX_IIR(pipe);
2534 for (tries = 0; tries < 5; tries++) {
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2545 DRM_ERROR("FDI train 2 fail!\n");
2547 DRM_DEBUG_KMS("FDI train done\n");
2551 static const int snb_b_fdi_train_param[] = {
2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2558 /* The FDI link training functions for SNB/Cougarpoint. */
2559 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
2565 u32 reg, temp, i, retry;
2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
2573 I915_WRITE(reg, temp);
2578 /* enable CPU FDI TX and PCH FDI RX */
2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
2581 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632 DRM_ERROR("FDI train 1 fail!\n");
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2644 I915_WRITE(reg, temp);
2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2655 I915_WRITE(reg, temp);
2660 for (i = 0; i < 4; i++) {
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
2665 I915_WRITE(reg, temp);
2670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685 DRM_ERROR("FDI train 2 fail!\n");
2687 DRM_DEBUG_KMS("FDI train done.\n");
2690 /* Manual link training for Ivy Bridge A0 parts */
2691 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
2697 u32 reg, temp, i, j;
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2713 /* Try each vswing and preemphasis setting twice before moving on */
2714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715 /* disable first in case we need to retry */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp &= ~FDI_TX_ENABLE;
2720 I915_WRITE(reg, temp);
2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_AUTO;
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp &= ~FDI_RX_ENABLE;
2727 I915_WRITE(reg, temp);
2729 /* enable CPU FDI TX and PCH FDI RX */
2730 reg = FDI_TX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[j/2];
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750 udelay(1); /* should be 0.5us */
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2764 udelay(1); /* should be 0.5us */
2767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 I915_WRITE(reg, temp);
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2782 I915_WRITE(reg, temp);
2785 udelay(2); /* should be 1.5us */
2787 for (i = 0; i < 4; i++) {
2788 reg = FDI_RX_IIR(pipe);
2789 temp = I915_READ(reg);
2790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792 if (temp & FDI_RX_SYMBOL_LOCK ||
2793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2799 udelay(2); /* should be 1.5us */
2802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2806 DRM_DEBUG_KMS("FDI train done.\n");
2809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2811 struct drm_device *dev = intel_crtc->base.dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 int pipe = intel_crtc->pipe;
2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2828 /* Switch from Rawclk to PCDclk */
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2835 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2870 /* Wait for the clocks to turn off. */
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2933 unsigned long flags;
2936 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2940 spin_lock_irqsave(&dev->event_lock, flags);
2941 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942 spin_unlock_irqrestore(&dev->event_lock, flags);
2947 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2949 struct drm_device *dev = crtc->dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2952 if (crtc->fb == NULL)
2955 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2957 wait_event(dev_priv->pending_flip_queue,
2958 !intel_crtc_has_pending_flip(crtc));
2960 mutex_lock(&dev->struct_mutex);
2961 intel_finish_fb(crtc->fb);
2962 mutex_unlock(&dev->struct_mutex);
2965 /* Program iCLKIP clock to the desired frequency */
2966 static void lpt_program_iclkip(struct drm_crtc *crtc)
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2971 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2974 mutex_lock(&dev_priv->dpio_lock);
2976 /* It is necessary to ungate the pixclk gate prior to programming
2977 * the divisors, and gate it back when it is done.
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2981 /* Disable SSCCTL */
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2983 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2987 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2988 if (clock == 20000) {
2993 /* The iCLK virtual clock root frequency is in MHz,
2994 * but the adjusted_mode->crtc_clock in in KHz. To get the
2995 * divisors, it is necessary to divide one by another, so we
2996 * convert the virtual clock precision to KHz here for higher
2999 u32 iclk_virtual_root_freq = 172800 * 1000;
3000 u32 iclk_pi_range = 64;
3001 u32 desired_divisor, msb_divisor_value, pi_value;
3003 desired_divisor = (iclk_virtual_root_freq / clock);
3004 msb_divisor_value = desired_divisor / iclk_pi_range;
3005 pi_value = desired_divisor % iclk_pi_range;
3008 divsel = msb_divisor_value - 2;
3009 phaseinc = pi_value;
3012 /* This should not happen with any sane values */
3013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3025 /* Program SSCDIVINTPHASE6 */
3026 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3027 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3033 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3035 /* Program SSCAUXDIV */
3036 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3037 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3039 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3046 /* Wait for initialization time */
3049 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3051 mutex_unlock(&dev_priv->dpio_lock);
3054 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055 enum pipe pch_transcoder)
3057 struct drm_device *dev = crtc->base.dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3061 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062 I915_READ(HTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064 I915_READ(HBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066 I915_READ(HSYNC(cpu_transcoder)));
3068 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069 I915_READ(VTOTAL(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071 I915_READ(VBLANK(cpu_transcoder)));
3072 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073 I915_READ(VSYNC(cpu_transcoder)));
3074 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3078 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3083 temp = I915_READ(SOUTH_CHICKEN1);
3084 if (temp & FDI_BC_BIFURCATION_SELECT)
3087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3090 temp |= FDI_BC_BIFURCATION_SELECT;
3091 DRM_DEBUG_KMS("enabling fdi C rx\n");
3092 I915_WRITE(SOUTH_CHICKEN1, temp);
3093 POSTING_READ(SOUTH_CHICKEN1);
3096 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3098 struct drm_device *dev = intel_crtc->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3101 switch (intel_crtc->pipe) {
3105 if (intel_crtc->config.fdi_lanes > 2)
3106 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3108 cpt_enable_fdi_bc_bifurcation(dev);
3112 cpt_enable_fdi_bc_bifurcation(dev);
3121 * Enable PCH resources required for PCH ports:
3123 * - FDI training & RX/TX
3124 * - update transcoder timings
3125 * - DP transcoding bits
3128 static void ironlake_pch_enable(struct drm_crtc *crtc)
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
3136 assert_pch_transcoder_disabled(dev_priv, pipe);
3138 if (IS_IVYBRIDGE(dev))
3139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3146 /* For PCH output, training FDI link */
3147 dev_priv->display.fdi_link_train(crtc);
3149 /* We need to program the right clock selection before writing the pixel
3150 * mutliplier into the DPLL. */
3151 if (HAS_PCH_CPT(dev)) {
3154 temp = I915_READ(PCH_DPLL_SEL);
3155 temp |= TRANS_DPLL_ENABLE(pipe);
3156 sel = TRANS_DPLLB_SEL(pipe);
3157 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3161 I915_WRITE(PCH_DPLL_SEL, temp);
3164 /* XXX: pch pll's can be enabled any time before we enable the PCH
3165 * transcoder, and we actually should do this to not upset any PCH
3166 * transcoder that already use the clock when we share it.
3168 * Note that enable_shared_dpll tries to do the right thing, but
3169 * get_shared_dpll unconditionally resets the pll - we need that to have
3170 * the right LVDS enable sequence. */
3171 ironlake_enable_shared_dpll(intel_crtc);
3173 /* set transcoder timing, panel must allow it */
3174 assert_panel_unlocked(dev_priv, pipe);
3175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3177 intel_fdi_normal_train(crtc);
3179 /* For PCH DP, enable TRANS_DP_CTL */
3180 if (HAS_PCH_CPT(dev) &&
3181 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3184 reg = TRANS_DP_CTL(pipe);
3185 temp = I915_READ(reg);
3186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3187 TRANS_DP_SYNC_MASK |
3189 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190 TRANS_DP_ENH_FRAMING);
3191 temp |= bpc << 9; /* same format but at 11:9 */
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3198 switch (intel_trans_dp_port_sel(crtc)) {
3200 temp |= TRANS_DP_PORT_SEL_B;
3203 temp |= TRANS_DP_PORT_SEL_C;
3206 temp |= TRANS_DP_PORT_SEL_D;
3212 I915_WRITE(reg, temp);
3215 ironlake_enable_pch_transcoder(dev_priv, pipe);
3218 static void lpt_pch_enable(struct drm_crtc *crtc)
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3227 lpt_program_iclkip(crtc);
3229 /* Set transcoder timing. */
3230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3235 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3237 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3242 if (pll->refcount == 0) {
3243 WARN(1, "bad %s refcount\n", pll->name);
3247 if (--pll->refcount == 0) {
3249 WARN_ON(pll->active);
3252 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3255 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259 enum intel_dpll_id i;
3262 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263 crtc->base.base.id, pll->name);
3264 intel_put_shared_dpll(crtc);
3267 if (HAS_PCH_IBX(dev_priv->dev)) {
3268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3269 i = (enum intel_dpll_id) crtc->pipe;
3270 pll = &dev_priv->shared_dplls[i];
3272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273 crtc->base.base.id, pll->name);
3278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279 pll = &dev_priv->shared_dplls[i];
3281 /* Only want to check enabled timings first */
3282 if (pll->refcount == 0)
3285 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286 sizeof(pll->hw_state)) == 0) {
3287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3289 pll->name, pll->refcount, pll->active);
3295 /* Ok no matching timings, maybe there's a free one? */
3296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297 pll = &dev_priv->shared_dplls[i];
3298 if (pll->refcount == 0) {
3299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300 crtc->base.base.id, pll->name);
3308 crtc->config.shared_dpll = i;
3309 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310 pipe_name(crtc->pipe));
3312 if (pll->active == 0) {
3313 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314 sizeof(pll->hw_state));
3316 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3318 assert_shared_dpll_disabled(dev_priv, pll);
3320 pll->mode_set(dev_priv, pll);
3327 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 int dslreg = PIPEDSL(pipe);
3333 temp = I915_READ(dslreg);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336 if (wait_for(I915_READ(dslreg) != temp, 5))
3337 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3341 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe = crtc->pipe;
3347 if (crtc->config.pch_pfit.enabled) {
3348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3352 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354 PF_PIPE_SEL_IVB(pipe));
3356 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3362 static void intel_enable_planes(struct drm_crtc *crtc)
3364 struct drm_device *dev = crtc->dev;
3365 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366 struct intel_plane *intel_plane;
3368 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369 if (intel_plane->pipe == pipe)
3370 intel_plane_restore(&intel_plane->base);
3373 static void intel_disable_planes(struct drm_crtc *crtc)
3375 struct drm_device *dev = crtc->dev;
3376 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377 struct intel_plane *intel_plane;
3379 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380 if (intel_plane->pipe == pipe)
3381 intel_plane_disable(&intel_plane->base);
3384 void hsw_enable_ips(struct intel_crtc *crtc)
3386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3388 if (!crtc->config.ips_enabled)
3391 /* We can only enable IPS after we enable a plane and wait for a vblank.
3392 * We guarantee that the plane is enabled by calling intel_enable_ips
3393 * only after intel_enable_plane. And intel_enable_plane already waits
3394 * for a vblank, so all we need to do here is to enable the IPS bit. */
3395 assert_plane_enabled(dev_priv, crtc->plane);
3396 if (IS_BROADWELL(crtc->base.dev)) {
3397 mutex_lock(&dev_priv->rps.hw_lock);
3398 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3399 mutex_unlock(&dev_priv->rps.hw_lock);
3400 /* Quoting Art Runyan: "its not safe to expect any particular
3401 * value in IPS_CTL bit 31 after enabling IPS through the
3402 * mailbox." Therefore we need to defer waiting on the state
3404 * TODO: need to fix this for state checker
3407 I915_WRITE(IPS_CTL, IPS_ENABLE);
3408 /* The bit only becomes 1 in the next vblank, so this wait here
3409 * is essentially intel_wait_for_vblank. If we don't have this
3410 * and don't wait for vblanks until the end of crtc_enable, then
3411 * the HW state readout code will complain that the expected
3412 * IPS_CTL value is not the one we read. */
3413 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3414 DRM_ERROR("Timed out waiting for IPS enable\n");
3418 void hsw_disable_ips(struct intel_crtc *crtc)
3420 struct drm_device *dev = crtc->base.dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3423 if (!crtc->config.ips_enabled)
3426 assert_plane_enabled(dev_priv, crtc->plane);
3427 if (IS_BROADWELL(crtc->base.dev)) {
3428 mutex_lock(&dev_priv->rps.hw_lock);
3429 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3430 mutex_unlock(&dev_priv->rps.hw_lock);
3432 I915_WRITE(IPS_CTL, 0);
3433 POSTING_READ(IPS_CTL);
3435 /* We need to wait for a vblank before we can disable the plane. */
3436 intel_wait_for_vblank(dev, crtc->pipe);
3439 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3440 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3442 struct drm_device *dev = crtc->dev;
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445 enum pipe pipe = intel_crtc->pipe;
3446 int palreg = PALETTE(pipe);
3448 bool reenable_ips = false;
3450 /* The clocks have to be on to load the palette. */
3451 if (!crtc->enabled || !intel_crtc->active)
3454 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3456 assert_dsi_pll_enabled(dev_priv);
3458 assert_pll_enabled(dev_priv, pipe);
3461 /* use legacy palette for Ironlake */
3462 if (HAS_PCH_SPLIT(dev))
3463 palreg = LGC_PALETTE(pipe);
3465 /* Workaround : Do not read or write the pipe palette/gamma data while
3466 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3468 if (intel_crtc->config.ips_enabled &&
3469 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3470 GAMMA_MODE_MODE_SPLIT)) {
3471 hsw_disable_ips(intel_crtc);
3472 reenable_ips = true;
3475 for (i = 0; i < 256; i++) {
3476 I915_WRITE(palreg + 4 * i,
3477 (intel_crtc->lut_r[i] << 16) |
3478 (intel_crtc->lut_g[i] << 8) |
3479 intel_crtc->lut_b[i]);
3483 hsw_enable_ips(intel_crtc);
3486 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3488 struct drm_device *dev = crtc->dev;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491 struct intel_encoder *encoder;
3492 int pipe = intel_crtc->pipe;
3493 int plane = intel_crtc->plane;
3495 WARN_ON(!crtc->enabled);
3497 if (intel_crtc->active)
3500 intel_crtc->active = true;
3502 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3503 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 if (encoder->pre_enable)
3507 encoder->pre_enable(encoder);
3509 if (intel_crtc->config.has_pch_encoder) {
3510 /* Note: FDI PLL enabling _must_ be done before we enable the
3511 * cpu pipes, hence this is separate from all the other fdi/pch
3513 ironlake_fdi_pll_enable(intel_crtc);
3515 assert_fdi_tx_disabled(dev_priv, pipe);
3516 assert_fdi_rx_disabled(dev_priv, pipe);
3519 ironlake_pfit_enable(intel_crtc);
3522 * On ILK+ LUT must be loaded before the pipe is running but with
3525 intel_crtc_load_lut(crtc);
3527 intel_update_watermarks(crtc);
3528 intel_enable_pipe(dev_priv, pipe,
3529 intel_crtc->config.has_pch_encoder, false);
3530 intel_enable_primary_plane(dev_priv, plane, pipe);
3531 intel_enable_planes(crtc);
3532 intel_crtc_update_cursor(crtc, true);
3534 if (intel_crtc->config.has_pch_encoder)
3535 ironlake_pch_enable(crtc);
3537 mutex_lock(&dev->struct_mutex);
3538 intel_update_fbc(dev);
3539 mutex_unlock(&dev->struct_mutex);
3541 for_each_encoder_on_crtc(dev, crtc, encoder)
3542 encoder->enable(encoder);
3544 if (HAS_PCH_CPT(dev))
3545 cpt_verify_modeset(dev, intel_crtc->pipe);
3548 * There seems to be a race in PCH platform hw (at least on some
3549 * outputs) where an enabled pipe still completes any pageflip right
3550 * away (as if the pipe is off) instead of waiting for vblank. As soon
3551 * as the first vblank happend, everything works as expected. Hence just
3552 * wait for one vblank before returning to avoid strange things
3555 intel_wait_for_vblank(dev, intel_crtc->pipe);
3558 /* IPS only exists on ULT machines and is tied to pipe A. */
3559 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3561 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3564 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3566 struct drm_device *dev = crtc->dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 int pipe = intel_crtc->pipe;
3570 int plane = intel_crtc->plane;
3572 intel_enable_primary_plane(dev_priv, plane, pipe);
3573 intel_enable_planes(crtc);
3574 intel_crtc_update_cursor(crtc, true);
3576 hsw_enable_ips(intel_crtc);
3578 mutex_lock(&dev->struct_mutex);
3579 intel_update_fbc(dev);
3580 mutex_unlock(&dev->struct_mutex);
3583 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
3591 intel_crtc_wait_for_pending_flips(crtc);
3592 drm_vblank_off(dev, pipe);
3594 /* FBC must be disabled before disabling the plane on HSW. */
3595 if (dev_priv->fbc.plane == plane)
3596 intel_disable_fbc(dev);
3598 hsw_disable_ips(intel_crtc);
3600 intel_crtc_update_cursor(crtc, false);
3601 intel_disable_planes(crtc);
3602 intel_disable_primary_plane(dev_priv, plane, pipe);
3606 * This implements the workaround described in the "notes" section of the mode
3607 * set sequence documentation. When going from no pipes or single pipe to
3608 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3609 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3611 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3613 struct drm_device *dev = crtc->base.dev;
3614 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3616 /* We want to get the other_active_crtc only if there's only 1 other
3618 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3619 if (!crtc_it->active || crtc_it == crtc)
3622 if (other_active_crtc)
3625 other_active_crtc = crtc_it;
3627 if (!other_active_crtc)
3630 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3631 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3634 static void haswell_crtc_enable(struct drm_crtc *crtc)
3636 struct drm_device *dev = crtc->dev;
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 struct intel_encoder *encoder;
3640 int pipe = intel_crtc->pipe;
3642 WARN_ON(!crtc->enabled);
3644 if (intel_crtc->active)
3647 intel_crtc->active = true;
3649 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3650 if (intel_crtc->config.has_pch_encoder)
3651 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3653 if (intel_crtc->config.has_pch_encoder)
3654 dev_priv->display.fdi_link_train(crtc);
3656 for_each_encoder_on_crtc(dev, crtc, encoder)
3657 if (encoder->pre_enable)
3658 encoder->pre_enable(encoder);
3660 intel_ddi_enable_pipe_clock(intel_crtc);
3662 ironlake_pfit_enable(intel_crtc);
3665 * On ILK+ LUT must be loaded before the pipe is running but with
3668 intel_crtc_load_lut(crtc);
3670 intel_ddi_set_pipe_settings(crtc);
3671 intel_ddi_enable_transcoder_func(crtc);
3673 intel_update_watermarks(crtc);
3674 intel_enable_pipe(dev_priv, pipe,
3675 intel_crtc->config.has_pch_encoder, false);
3677 if (intel_crtc->config.has_pch_encoder)
3678 lpt_pch_enable(crtc);
3680 for_each_encoder_on_crtc(dev, crtc, encoder) {
3681 encoder->enable(encoder);
3682 intel_opregion_notify_encoder(encoder, true);
3685 /* If we change the relative order between pipe/planes enabling, we need
3686 * to change the workaround. */
3687 haswell_mode_set_planes_workaround(intel_crtc);
3688 haswell_crtc_enable_planes(crtc);
3691 * There seems to be a race in PCH platform hw (at least on some
3692 * outputs) where an enabled pipe still completes any pageflip right
3693 * away (as if the pipe is off) instead of waiting for vblank. As soon
3694 * as the first vblank happend, everything works as expected. Hence just
3695 * wait for one vblank before returning to avoid strange things
3698 intel_wait_for_vblank(dev, intel_crtc->pipe);
3701 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3703 struct drm_device *dev = crtc->base.dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 int pipe = crtc->pipe;
3707 /* To avoid upsetting the power well on haswell only disable the pfit if
3708 * it's in use. The hw state code will make sure we get this right. */
3709 if (crtc->config.pch_pfit.enabled) {
3710 I915_WRITE(PF_CTL(pipe), 0);
3711 I915_WRITE(PF_WIN_POS(pipe), 0);
3712 I915_WRITE(PF_WIN_SZ(pipe), 0);
3716 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721 struct intel_encoder *encoder;
3722 int pipe = intel_crtc->pipe;
3723 int plane = intel_crtc->plane;
3727 if (!intel_crtc->active)
3730 for_each_encoder_on_crtc(dev, crtc, encoder)
3731 encoder->disable(encoder);
3733 intel_crtc_wait_for_pending_flips(crtc);
3734 drm_vblank_off(dev, pipe);
3736 if (dev_priv->fbc.plane == plane)
3737 intel_disable_fbc(dev);
3739 intel_crtc_update_cursor(crtc, false);
3740 intel_disable_planes(crtc);
3741 intel_disable_primary_plane(dev_priv, plane, pipe);
3743 if (intel_crtc->config.has_pch_encoder)
3744 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3746 intel_disable_pipe(dev_priv, pipe);
3748 ironlake_pfit_disable(intel_crtc);
3750 for_each_encoder_on_crtc(dev, crtc, encoder)
3751 if (encoder->post_disable)
3752 encoder->post_disable(encoder);
3754 if (intel_crtc->config.has_pch_encoder) {
3755 ironlake_fdi_disable(crtc);
3757 ironlake_disable_pch_transcoder(dev_priv, pipe);
3758 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3760 if (HAS_PCH_CPT(dev)) {
3761 /* disable TRANS_DP_CTL */
3762 reg = TRANS_DP_CTL(pipe);
3763 temp = I915_READ(reg);
3764 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3765 TRANS_DP_PORT_SEL_MASK);
3766 temp |= TRANS_DP_PORT_SEL_NONE;
3767 I915_WRITE(reg, temp);
3769 /* disable DPLL_SEL */
3770 temp = I915_READ(PCH_DPLL_SEL);
3771 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3772 I915_WRITE(PCH_DPLL_SEL, temp);
3775 /* disable PCH DPLL */
3776 intel_disable_shared_dpll(intel_crtc);
3778 ironlake_fdi_pll_disable(intel_crtc);
3781 intel_crtc->active = false;
3782 intel_update_watermarks(crtc);
3784 mutex_lock(&dev->struct_mutex);
3785 intel_update_fbc(dev);
3786 mutex_unlock(&dev->struct_mutex);
3789 static void haswell_crtc_disable(struct drm_crtc *crtc)
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3794 struct intel_encoder *encoder;
3795 int pipe = intel_crtc->pipe;
3796 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3798 if (!intel_crtc->active)
3801 haswell_crtc_disable_planes(crtc);
3803 for_each_encoder_on_crtc(dev, crtc, encoder) {
3804 intel_opregion_notify_encoder(encoder, false);
3805 encoder->disable(encoder);
3808 if (intel_crtc->config.has_pch_encoder)
3809 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3810 intel_disable_pipe(dev_priv, pipe);
3812 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3814 ironlake_pfit_disable(intel_crtc);
3816 intel_ddi_disable_pipe_clock(intel_crtc);
3818 for_each_encoder_on_crtc(dev, crtc, encoder)
3819 if (encoder->post_disable)
3820 encoder->post_disable(encoder);
3822 if (intel_crtc->config.has_pch_encoder) {
3823 lpt_disable_pch_transcoder(dev_priv);
3824 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3825 intel_ddi_fdi_disable(crtc);
3828 intel_crtc->active = false;
3829 intel_update_watermarks(crtc);
3831 mutex_lock(&dev->struct_mutex);
3832 intel_update_fbc(dev);
3833 mutex_unlock(&dev->struct_mutex);
3836 static void ironlake_crtc_off(struct drm_crtc *crtc)
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839 intel_put_shared_dpll(intel_crtc);
3842 static void haswell_crtc_off(struct drm_crtc *crtc)
3844 intel_ddi_put_crtc_pll(crtc);
3847 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3849 if (!enable && intel_crtc->overlay) {
3850 struct drm_device *dev = intel_crtc->base.dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3853 mutex_lock(&dev->struct_mutex);
3854 dev_priv->mm.interruptible = false;
3855 (void) intel_overlay_switch_off(intel_crtc->overlay);
3856 dev_priv->mm.interruptible = true;
3857 mutex_unlock(&dev->struct_mutex);
3860 /* Let userspace switch the overlay on again. In most cases userspace
3861 * has to recompute where to put it anyway.
3866 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3867 * cursor plane briefly if not already running after enabling the display
3869 * This workaround avoids occasional blank screens when self refresh is
3873 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3875 u32 cntl = I915_READ(CURCNTR(pipe));
3877 if ((cntl & CURSOR_MODE) == 0) {
3878 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3880 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3881 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3882 intel_wait_for_vblank(dev_priv->dev, pipe);
3883 I915_WRITE(CURCNTR(pipe), cntl);
3884 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3885 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3889 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3891 struct drm_device *dev = crtc->base.dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893 struct intel_crtc_config *pipe_config = &crtc->config;
3895 if (!crtc->config.gmch_pfit.control)
3899 * The panel fitter should only be adjusted whilst the pipe is disabled,
3900 * according to register description and PRM.
3902 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3903 assert_pipe_disabled(dev_priv, crtc->pipe);
3905 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3906 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3908 /* Border color in case we don't scale up to the full screen. Black by
3909 * default, change to something else for debugging. */
3910 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3913 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918 struct intel_encoder *encoder;
3919 int pipe = intel_crtc->pipe;
3920 int plane = intel_crtc->plane;
3923 WARN_ON(!crtc->enabled);
3925 if (intel_crtc->active)
3928 intel_crtc->active = true;
3930 for_each_encoder_on_crtc(dev, crtc, encoder)
3931 if (encoder->pre_pll_enable)
3932 encoder->pre_pll_enable(encoder);
3934 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3937 vlv_enable_pll(intel_crtc);
3939 for_each_encoder_on_crtc(dev, crtc, encoder)
3940 if (encoder->pre_enable)
3941 encoder->pre_enable(encoder);
3943 i9xx_pfit_enable(intel_crtc);
3945 intel_crtc_load_lut(crtc);
3947 intel_update_watermarks(crtc);
3948 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3949 intel_enable_primary_plane(dev_priv, plane, pipe);
3950 intel_enable_planes(crtc);
3951 intel_crtc_update_cursor(crtc, true);
3953 intel_update_fbc(dev);
3955 for_each_encoder_on_crtc(dev, crtc, encoder)
3956 encoder->enable(encoder);
3959 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964 struct intel_encoder *encoder;
3965 int pipe = intel_crtc->pipe;
3966 int plane = intel_crtc->plane;
3968 WARN_ON(!crtc->enabled);
3970 if (intel_crtc->active)
3973 intel_crtc->active = true;
3975 for_each_encoder_on_crtc(dev, crtc, encoder)
3976 if (encoder->pre_enable)
3977 encoder->pre_enable(encoder);
3979 i9xx_enable_pll(intel_crtc);
3981 i9xx_pfit_enable(intel_crtc);
3983 intel_crtc_load_lut(crtc);
3985 intel_update_watermarks(crtc);
3986 intel_enable_pipe(dev_priv, pipe, false, false);
3987 intel_enable_primary_plane(dev_priv, plane, pipe);
3988 intel_enable_planes(crtc);
3989 /* The fixup needs to happen before cursor is enabled */
3991 g4x_fixup_plane(dev_priv, pipe);
3992 intel_crtc_update_cursor(crtc, true);
3994 /* Give the overlay scaler a chance to enable if it's on this pipe */
3995 intel_crtc_dpms_overlay(intel_crtc, true);
3997 intel_update_fbc(dev);
3999 for_each_encoder_on_crtc(dev, crtc, encoder)
4000 encoder->enable(encoder);
4003 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
4008 if (!crtc->config.gmch_pfit.control)
4011 assert_pipe_disabled(dev_priv, crtc->pipe);
4013 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4014 I915_READ(PFIT_CONTROL));
4015 I915_WRITE(PFIT_CONTROL, 0);
4018 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4020 struct drm_device *dev = crtc->dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4023 struct intel_encoder *encoder;
4024 int pipe = intel_crtc->pipe;
4025 int plane = intel_crtc->plane;
4027 if (!intel_crtc->active)
4030 for_each_encoder_on_crtc(dev, crtc, encoder)
4031 encoder->disable(encoder);
4033 /* Give the overlay scaler a chance to disable if it's on this pipe */
4034 intel_crtc_wait_for_pending_flips(crtc);
4035 drm_vblank_off(dev, pipe);
4037 if (dev_priv->fbc.plane == plane)
4038 intel_disable_fbc(dev);
4040 intel_crtc_dpms_overlay(intel_crtc, false);
4041 intel_crtc_update_cursor(crtc, false);
4042 intel_disable_planes(crtc);
4043 intel_disable_primary_plane(dev_priv, plane, pipe);
4045 intel_disable_pipe(dev_priv, pipe);
4047 i9xx_pfit_disable(intel_crtc);
4049 for_each_encoder_on_crtc(dev, crtc, encoder)
4050 if (encoder->post_disable)
4051 encoder->post_disable(encoder);
4053 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4054 vlv_disable_pll(dev_priv, pipe);
4055 else if (!IS_VALLEYVIEW(dev))
4056 i9xx_disable_pll(dev_priv, pipe);
4058 intel_crtc->active = false;
4059 intel_update_watermarks(crtc);
4061 intel_update_fbc(dev);
4064 static void i9xx_crtc_off(struct drm_crtc *crtc)
4068 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4071 struct drm_device *dev = crtc->dev;
4072 struct drm_i915_master_private *master_priv;
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074 int pipe = intel_crtc->pipe;
4076 if (!dev->primary->master)
4079 master_priv = dev->primary->master->driver_priv;
4080 if (!master_priv->sarea_priv)
4085 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4086 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4089 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4090 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4093 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4099 * Sets the power management mode of the pipe and plane.
4101 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4103 struct drm_device *dev = crtc->dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 struct intel_encoder *intel_encoder;
4106 bool enable = false;
4108 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4109 enable |= intel_encoder->connectors_active;
4112 dev_priv->display.crtc_enable(crtc);
4114 dev_priv->display.crtc_disable(crtc);
4116 intel_crtc_update_sarea(crtc, enable);
4119 static void intel_crtc_disable(struct drm_crtc *crtc)
4121 struct drm_device *dev = crtc->dev;
4122 struct drm_connector *connector;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4126 /* crtc should still be enabled when we disable it. */
4127 WARN_ON(!crtc->enabled);
4129 dev_priv->display.crtc_disable(crtc);
4130 intel_crtc->eld_vld = false;
4131 intel_crtc_update_sarea(crtc, false);
4132 dev_priv->display.off(crtc);
4134 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4135 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4136 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4139 mutex_lock(&dev->struct_mutex);
4140 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4141 mutex_unlock(&dev->struct_mutex);
4145 /* Update computed state. */
4146 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4147 if (!connector->encoder || !connector->encoder->crtc)
4150 if (connector->encoder->crtc != crtc)
4153 connector->dpms = DRM_MODE_DPMS_OFF;
4154 to_intel_encoder(connector->encoder)->connectors_active = false;
4158 void intel_encoder_destroy(struct drm_encoder *encoder)
4160 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4162 drm_encoder_cleanup(encoder);
4163 kfree(intel_encoder);
4166 /* Simple dpms helper for encoders with just one connector, no cloning and only
4167 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4168 * state of the entire output pipe. */
4169 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4171 if (mode == DRM_MODE_DPMS_ON) {
4172 encoder->connectors_active = true;
4174 intel_crtc_update_dpms(encoder->base.crtc);
4176 encoder->connectors_active = false;
4178 intel_crtc_update_dpms(encoder->base.crtc);
4182 /* Cross check the actual hw state with our own modeset state tracking (and it's
4183 * internal consistency). */
4184 static void intel_connector_check_state(struct intel_connector *connector)
4186 if (connector->get_hw_state(connector)) {
4187 struct intel_encoder *encoder = connector->encoder;
4188 struct drm_crtc *crtc;
4189 bool encoder_enabled;
4192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4193 connector->base.base.id,
4194 drm_get_connector_name(&connector->base));
4196 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4197 "wrong connector dpms state\n");
4198 WARN(connector->base.encoder != &encoder->base,
4199 "active connector not linked to encoder\n");
4200 WARN(!encoder->connectors_active,
4201 "encoder->connectors_active not set\n");
4203 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4204 WARN(!encoder_enabled, "encoder not enabled\n");
4205 if (WARN_ON(!encoder->base.crtc))
4208 crtc = encoder->base.crtc;
4210 WARN(!crtc->enabled, "crtc not enabled\n");
4211 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4212 WARN(pipe != to_intel_crtc(crtc)->pipe,
4213 "encoder active on the wrong pipe\n");
4217 /* Even simpler default implementation, if there's really no special case to
4219 void intel_connector_dpms(struct drm_connector *connector, int mode)
4221 /* All the simple cases only support two dpms states. */
4222 if (mode != DRM_MODE_DPMS_ON)
4223 mode = DRM_MODE_DPMS_OFF;
4225 if (mode == connector->dpms)
4228 connector->dpms = mode;
4230 /* Only need to change hw state when actually enabled */
4231 if (connector->encoder)
4232 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4234 intel_modeset_check_state(connector->dev);
4237 /* Simple connector->get_hw_state implementation for encoders that support only
4238 * one connector and no cloning and hence the encoder state determines the state
4239 * of the connector. */
4240 bool intel_connector_get_hw_state(struct intel_connector *connector)
4243 struct intel_encoder *encoder = connector->encoder;
4245 return encoder->get_hw_state(encoder, &pipe);
4248 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4249 struct intel_crtc_config *pipe_config)
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *pipe_B_crtc =
4253 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4255 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4256 pipe_name(pipe), pipe_config->fdi_lanes);
4257 if (pipe_config->fdi_lanes > 4) {
4258 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4259 pipe_name(pipe), pipe_config->fdi_lanes);
4263 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4264 if (pipe_config->fdi_lanes > 2) {
4265 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4266 pipe_config->fdi_lanes);
4273 if (INTEL_INFO(dev)->num_pipes == 2)
4276 /* Ivybridge 3 pipe is really complicated */
4281 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4282 pipe_config->fdi_lanes > 2) {
4283 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4284 pipe_name(pipe), pipe_config->fdi_lanes);
4289 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4290 pipe_B_crtc->config.fdi_lanes <= 2) {
4291 if (pipe_config->fdi_lanes > 2) {
4292 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4293 pipe_name(pipe), pipe_config->fdi_lanes);
4297 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4307 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4308 struct intel_crtc_config *pipe_config)
4310 struct drm_device *dev = intel_crtc->base.dev;
4311 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4312 int lane, link_bw, fdi_dotclock;
4313 bool setup_ok, needs_recompute = false;
4316 /* FDI is a binary signal running at ~2.7GHz, encoding
4317 * each output octet as 10 bits. The actual frequency
4318 * is stored as a divider into a 100MHz clock, and the
4319 * mode pixel clock is stored in units of 1KHz.
4320 * Hence the bw of each lane in terms of the mode signal
4323 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4325 fdi_dotclock = adjusted_mode->crtc_clock;
4327 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4328 pipe_config->pipe_bpp);
4330 pipe_config->fdi_lanes = lane;
4332 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4333 link_bw, &pipe_config->fdi_m_n);
4335 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4336 intel_crtc->pipe, pipe_config);
4337 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4338 pipe_config->pipe_bpp -= 2*3;
4339 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4340 pipe_config->pipe_bpp);
4341 needs_recompute = true;
4342 pipe_config->bw_constrained = true;
4347 if (needs_recompute)
4350 return setup_ok ? 0 : -EINVAL;
4353 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4354 struct intel_crtc_config *pipe_config)
4356 pipe_config->ips_enabled = i915_enable_ips &&
4357 hsw_crtc_supports_ips(crtc) &&
4358 pipe_config->pipe_bpp <= 24;
4361 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4362 struct intel_crtc_config *pipe_config)
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4367 /* FIXME should check pixel clock limits on all platforms */
4368 if (INTEL_INFO(dev)->gen < 4) {
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4371 dev_priv->display.get_display_clock_speed(dev);
4374 * Enable pixel doubling when the dot clock
4375 * is > 90% of the (display) core speed.
4377 * GDG double wide on either pipe,
4378 * otherwise pipe A only.
4380 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4381 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4383 pipe_config->double_wide = true;
4386 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4391 * Pipe horizontal size must be even in:
4393 * - LVDS dual channel mode
4394 * - Double wide pipe
4396 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4397 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4398 pipe_config->pipe_src_w &= ~1;
4400 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4401 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4403 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4404 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4407 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4408 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4409 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4410 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4412 pipe_config->pipe_bpp = 8*3;
4416 hsw_compute_ips_config(crtc, pipe_config);
4418 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4419 * clock survives for now. */
4420 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4421 pipe_config->shared_dpll = crtc->config.shared_dpll;
4423 if (pipe_config->has_pch_encoder)
4424 return ironlake_fdi_compute_config(crtc, pipe_config);
4429 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4431 return 400000; /* FIXME */
4434 static int i945_get_display_clock_speed(struct drm_device *dev)
4439 static int i915_get_display_clock_speed(struct drm_device *dev)
4444 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4449 static int pnv_get_display_clock_speed(struct drm_device *dev)
4453 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4455 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4456 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4458 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4460 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4462 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4465 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4466 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4468 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4473 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4477 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4479 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4482 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4483 case GC_DISPLAY_CLOCK_333_MHZ:
4486 case GC_DISPLAY_CLOCK_190_200_MHZ:
4492 static int i865_get_display_clock_speed(struct drm_device *dev)
4497 static int i855_get_display_clock_speed(struct drm_device *dev)
4500 /* Assume that the hardware is in the high speed state. This
4501 * should be the default.
4503 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4504 case GC_CLOCK_133_200:
4505 case GC_CLOCK_100_200:
4507 case GC_CLOCK_166_250:
4509 case GC_CLOCK_100_133:
4513 /* Shouldn't happen */
4517 static int i830_get_display_clock_speed(struct drm_device *dev)
4523 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4525 while (*num > DATA_LINK_M_N_MASK ||
4526 *den > DATA_LINK_M_N_MASK) {
4532 static void compute_m_n(unsigned int m, unsigned int n,
4533 uint32_t *ret_m, uint32_t *ret_n)
4535 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4536 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4537 intel_reduce_m_n_ratio(ret_m, ret_n);
4541 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4542 int pixel_clock, int link_clock,
4543 struct intel_link_m_n *m_n)
4547 compute_m_n(bits_per_pixel * pixel_clock,
4548 link_clock * nlanes * 8,
4549 &m_n->gmch_m, &m_n->gmch_n);
4551 compute_m_n(pixel_clock, link_clock,
4552 &m_n->link_m, &m_n->link_n);
4555 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4557 if (i915_panel_use_ssc >= 0)
4558 return i915_panel_use_ssc != 0;
4559 return dev_priv->vbt.lvds_use_ssc
4560 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4563 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4569 if (IS_VALLEYVIEW(dev)) {
4571 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4572 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4573 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4574 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4576 } else if (!IS_GEN2(dev)) {
4585 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4587 return (1 << dpll->n) << 16 | dpll->m2;
4590 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4592 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4595 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4596 intel_clock_t *reduced_clock)
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 int pipe = crtc->pipe;
4603 if (IS_PINEVIEW(dev)) {
4604 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4606 fp2 = pnv_dpll_compute_fp(reduced_clock);
4608 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4610 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4613 I915_WRITE(FP0(pipe), fp);
4614 crtc->config.dpll_hw_state.fp0 = fp;
4616 crtc->lowfreq_avail = false;
4617 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4618 reduced_clock && i915_powersave) {
4619 I915_WRITE(FP1(pipe), fp2);
4620 crtc->config.dpll_hw_state.fp1 = fp2;
4621 crtc->lowfreq_avail = true;
4623 I915_WRITE(FP1(pipe), fp);
4624 crtc->config.dpll_hw_state.fp1 = fp;
4628 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4634 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4635 * and set it to a reasonable value instead.
4637 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4638 reg_val &= 0xffffff00;
4639 reg_val |= 0x00000030;
4640 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4642 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4643 reg_val &= 0x8cffffff;
4644 reg_val = 0x8c000000;
4645 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4647 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4648 reg_val &= 0xffffff00;
4649 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4651 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4652 reg_val &= 0x00ffffff;
4653 reg_val |= 0xb0000000;
4654 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4657 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4658 struct intel_link_m_n *m_n)
4660 struct drm_device *dev = crtc->base.dev;
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 int pipe = crtc->pipe;
4664 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4665 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4666 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4667 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4670 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4671 struct intel_link_m_n *m_n)
4673 struct drm_device *dev = crtc->base.dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 int pipe = crtc->pipe;
4676 enum transcoder transcoder = crtc->config.cpu_transcoder;
4678 if (INTEL_INFO(dev)->gen >= 5) {
4679 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4680 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4681 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4682 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4684 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4685 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4686 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4687 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4691 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4693 if (crtc->config.has_pch_encoder)
4694 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4696 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4699 static void vlv_update_pll(struct intel_crtc *crtc)
4701 struct drm_device *dev = crtc->base.dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 int pipe = crtc->pipe;
4705 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4706 u32 coreclk, reg_val, dpll_md;
4708 mutex_lock(&dev_priv->dpio_lock);
4710 bestn = crtc->config.dpll.n;
4711 bestm1 = crtc->config.dpll.m1;
4712 bestm2 = crtc->config.dpll.m2;
4713 bestp1 = crtc->config.dpll.p1;
4714 bestp2 = crtc->config.dpll.p2;
4716 /* See eDP HDMI DPIO driver vbios notes doc */
4718 /* PLL B needs special handling */
4720 vlv_pllb_recal_opamp(dev_priv, pipe);
4722 /* Set up Tx target for periodic Rcomp update */
4723 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4725 /* Disable target IRef on PLL */
4726 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4727 reg_val &= 0x00ffffff;
4728 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4730 /* Disable fast lock */
4731 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4733 /* Set idtafcrecal before PLL is enabled */
4734 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4735 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4736 mdiv |= ((bestn << DPIO_N_SHIFT));
4737 mdiv |= (1 << DPIO_K_SHIFT);
4740 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4741 * but we don't support that).
4742 * Note: don't use the DAC post divider as it seems unstable.
4744 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4745 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4747 mdiv |= DPIO_ENABLE_CALIBRATION;
4748 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4750 /* Set HBR and RBR LPF coefficients */
4751 if (crtc->config.port_clock == 162000 ||
4752 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4753 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4754 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4757 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4760 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4761 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4762 /* Use SSC source */
4764 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4767 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4769 } else { /* HDMI or VGA */
4770 /* Use bend source */
4772 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4775 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4779 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4780 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4781 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4782 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4783 coreclk |= 0x01000000;
4784 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4786 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4788 /* Enable DPIO clock input */
4789 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4790 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4791 /* We should never disable this, set it here for state tracking */
4793 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4794 dpll |= DPLL_VCO_ENABLE;
4795 crtc->config.dpll_hw_state.dpll = dpll;
4797 dpll_md = (crtc->config.pixel_multiplier - 1)
4798 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4799 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4801 if (crtc->config.has_dp_encoder)
4802 intel_dp_set_m_n(crtc);
4804 mutex_unlock(&dev_priv->dpio_lock);
4807 static void i9xx_update_pll(struct intel_crtc *crtc,
4808 intel_clock_t *reduced_clock,
4811 struct drm_device *dev = crtc->base.dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct dpll *clock = &crtc->config.dpll;
4817 i9xx_update_pll_dividers(crtc, reduced_clock);
4819 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4820 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4822 dpll = DPLL_VGA_MODE_DIS;
4824 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4825 dpll |= DPLLB_MODE_LVDS;
4827 dpll |= DPLLB_MODE_DAC_SERIAL;
4829 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4830 dpll |= (crtc->config.pixel_multiplier - 1)
4831 << SDVO_MULTIPLIER_SHIFT_HIRES;
4835 dpll |= DPLL_SDVO_HIGH_SPEED;
4837 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4838 dpll |= DPLL_SDVO_HIGH_SPEED;
4840 /* compute bitmask from p1 value */
4841 if (IS_PINEVIEW(dev))
4842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4845 if (IS_G4X(dev) && reduced_clock)
4846 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4848 switch (clock->p2) {
4850 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4853 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4856 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4859 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4862 if (INTEL_INFO(dev)->gen >= 4)
4863 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4865 if (crtc->config.sdvo_tv_clock)
4866 dpll |= PLL_REF_INPUT_TVCLKINBC;
4867 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4868 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4871 dpll |= PLL_REF_INPUT_DREFCLK;
4873 dpll |= DPLL_VCO_ENABLE;
4874 crtc->config.dpll_hw_state.dpll = dpll;
4876 if (INTEL_INFO(dev)->gen >= 4) {
4877 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4878 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4879 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4882 if (crtc->config.has_dp_encoder)
4883 intel_dp_set_m_n(crtc);
4886 static void i8xx_update_pll(struct intel_crtc *crtc,
4887 intel_clock_t *reduced_clock,
4890 struct drm_device *dev = crtc->base.dev;
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4893 struct dpll *clock = &crtc->config.dpll;
4895 i9xx_update_pll_dividers(crtc, reduced_clock);
4897 dpll = DPLL_VGA_MODE_DIS;
4899 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4900 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4903 dpll |= PLL_P1_DIVIDE_BY_TWO;
4905 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4907 dpll |= PLL_P2_DIVIDE_BY_4;
4910 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4911 dpll |= DPLL_DVO_2X_MODE;
4913 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4914 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4915 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4917 dpll |= PLL_REF_INPUT_DREFCLK;
4919 dpll |= DPLL_VCO_ENABLE;
4920 crtc->config.dpll_hw_state.dpll = dpll;
4923 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4925 struct drm_device *dev = intel_crtc->base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 enum pipe pipe = intel_crtc->pipe;
4928 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4929 struct drm_display_mode *adjusted_mode =
4930 &intel_crtc->config.adjusted_mode;
4931 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4933 /* We need to be careful not to changed the adjusted mode, for otherwise
4934 * the hw state checker will get angry at the mismatch. */
4935 crtc_vtotal = adjusted_mode->crtc_vtotal;
4936 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4938 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4939 /* the chip adds 2 halflines automatically */
4941 crtc_vblank_end -= 1;
4942 vsyncshift = adjusted_mode->crtc_hsync_start
4943 - adjusted_mode->crtc_htotal / 2;
4948 if (INTEL_INFO(dev)->gen > 3)
4949 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4951 I915_WRITE(HTOTAL(cpu_transcoder),
4952 (adjusted_mode->crtc_hdisplay - 1) |
4953 ((adjusted_mode->crtc_htotal - 1) << 16));
4954 I915_WRITE(HBLANK(cpu_transcoder),
4955 (adjusted_mode->crtc_hblank_start - 1) |
4956 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4957 I915_WRITE(HSYNC(cpu_transcoder),
4958 (adjusted_mode->crtc_hsync_start - 1) |
4959 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4961 I915_WRITE(VTOTAL(cpu_transcoder),
4962 (adjusted_mode->crtc_vdisplay - 1) |
4963 ((crtc_vtotal - 1) << 16));
4964 I915_WRITE(VBLANK(cpu_transcoder),
4965 (adjusted_mode->crtc_vblank_start - 1) |
4966 ((crtc_vblank_end - 1) << 16));
4967 I915_WRITE(VSYNC(cpu_transcoder),
4968 (adjusted_mode->crtc_vsync_start - 1) |
4969 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4971 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4972 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4973 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4975 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4976 (pipe == PIPE_B || pipe == PIPE_C))
4977 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4979 /* pipesrc controls the size that is scaled from, which should
4980 * always be the user's requested size.
4982 I915_WRITE(PIPESRC(pipe),
4983 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4984 (intel_crtc->config.pipe_src_h - 1));
4987 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4988 struct intel_crtc_config *pipe_config)
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4995 tmp = I915_READ(HTOTAL(cpu_transcoder));
4996 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4997 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4998 tmp = I915_READ(HBLANK(cpu_transcoder));
4999 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5000 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5001 tmp = I915_READ(HSYNC(cpu_transcoder));
5002 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5003 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5005 tmp = I915_READ(VTOTAL(cpu_transcoder));
5006 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5007 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5008 tmp = I915_READ(VBLANK(cpu_transcoder));
5009 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5010 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5011 tmp = I915_READ(VSYNC(cpu_transcoder));
5012 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5013 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5015 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5016 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5017 pipe_config->adjusted_mode.crtc_vtotal += 1;
5018 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5021 tmp = I915_READ(PIPESRC(crtc->pipe));
5022 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5023 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5025 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5026 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5029 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5030 struct intel_crtc_config *pipe_config)
5032 struct drm_crtc *crtc = &intel_crtc->base;
5034 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5035 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5036 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5037 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5039 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5040 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5041 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5042 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5044 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5046 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5047 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5050 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5052 struct drm_device *dev = intel_crtc->base.dev;
5053 struct drm_i915_private *dev_priv = dev->dev_private;
5058 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5059 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5060 pipeconf |= PIPECONF_ENABLE;
5062 if (intel_crtc->config.double_wide)
5063 pipeconf |= PIPECONF_DOUBLE_WIDE;
5065 /* only g4x and later have fancy bpc/dither controls */
5066 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5067 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5068 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5069 pipeconf |= PIPECONF_DITHER_EN |
5070 PIPECONF_DITHER_TYPE_SP;
5072 switch (intel_crtc->config.pipe_bpp) {
5074 pipeconf |= PIPECONF_6BPC;
5077 pipeconf |= PIPECONF_8BPC;
5080 pipeconf |= PIPECONF_10BPC;
5083 /* Case prevented by intel_choose_pipe_bpp_dither. */
5088 if (HAS_PIPE_CXSR(dev)) {
5089 if (intel_crtc->lowfreq_avail) {
5090 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5091 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5093 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5097 if (!IS_GEN2(dev) &&
5098 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5099 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5101 pipeconf |= PIPECONF_PROGRESSIVE;
5103 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5104 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5106 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5107 POSTING_READ(PIPECONF(intel_crtc->pipe));
5110 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5112 struct drm_framebuffer *fb)
5114 struct drm_device *dev = crtc->dev;
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117 int pipe = intel_crtc->pipe;
5118 int plane = intel_crtc->plane;
5119 int refclk, num_connectors = 0;
5120 intel_clock_t clock, reduced_clock;
5122 bool ok, has_reduced_clock = false;
5123 bool is_lvds = false, is_dsi = false;
5124 struct intel_encoder *encoder;
5125 const intel_limit_t *limit;
5128 for_each_encoder_on_crtc(dev, crtc, encoder) {
5129 switch (encoder->type) {
5130 case INTEL_OUTPUT_LVDS:
5133 case INTEL_OUTPUT_DSI:
5144 if (!intel_crtc->config.clock_set) {
5145 refclk = i9xx_get_refclk(crtc, num_connectors);
5148 * Returns a set of divisors for the desired target clock with
5149 * the given refclk, or FALSE. The returned values represent
5150 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5153 limit = intel_limit(crtc, refclk);
5154 ok = dev_priv->display.find_dpll(limit, crtc,
5155 intel_crtc->config.port_clock,
5156 refclk, NULL, &clock);
5158 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5162 if (is_lvds && dev_priv->lvds_downclock_avail) {
5164 * Ensure we match the reduced clock's P to the target
5165 * clock. If the clocks don't match, we can't switch
5166 * the display clock by using the FP0/FP1. In such case
5167 * we will disable the LVDS downclock feature.
5170 dev_priv->display.find_dpll(limit, crtc,
5171 dev_priv->lvds_downclock,
5175 /* Compat-code for transition, will disappear. */
5176 intel_crtc->config.dpll.n = clock.n;
5177 intel_crtc->config.dpll.m1 = clock.m1;
5178 intel_crtc->config.dpll.m2 = clock.m2;
5179 intel_crtc->config.dpll.p1 = clock.p1;
5180 intel_crtc->config.dpll.p2 = clock.p2;
5184 i8xx_update_pll(intel_crtc,
5185 has_reduced_clock ? &reduced_clock : NULL,
5187 } else if (IS_VALLEYVIEW(dev)) {
5188 vlv_update_pll(intel_crtc);
5190 i9xx_update_pll(intel_crtc,
5191 has_reduced_clock ? &reduced_clock : NULL,
5196 /* Set up the display plane register */
5197 dspcntr = DISPPLANE_GAMMA_ENABLE;
5199 if (!IS_VALLEYVIEW(dev)) {
5201 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5203 dspcntr |= DISPPLANE_SEL_PIPE_B;
5206 intel_set_pipe_timings(intel_crtc);
5208 /* pipesrc and dspsize control the size that is scaled from,
5209 * which should always be the user's requested size.
5211 I915_WRITE(DSPSIZE(plane),
5212 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5213 (intel_crtc->config.pipe_src_w - 1));
5214 I915_WRITE(DSPPOS(plane), 0);
5216 i9xx_set_pipeconf(intel_crtc);
5218 I915_WRITE(DSPCNTR(plane), dspcntr);
5219 POSTING_READ(DSPCNTR(plane));
5221 ret = intel_pipe_set_base(crtc, x, y, fb);
5226 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5227 struct intel_crtc_config *pipe_config)
5229 struct drm_device *dev = crtc->base.dev;
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5233 tmp = I915_READ(PFIT_CONTROL);
5234 if (!(tmp & PFIT_ENABLE))
5237 /* Check whether the pfit is attached to our pipe. */
5238 if (INTEL_INFO(dev)->gen < 4) {
5239 if (crtc->pipe != PIPE_B)
5242 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5246 pipe_config->gmch_pfit.control = tmp;
5247 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5248 if (INTEL_INFO(dev)->gen < 5)
5249 pipe_config->gmch_pfit.lvds_border_bits =
5250 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5253 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5254 struct intel_crtc_config *pipe_config)
5256 struct drm_device *dev = crtc->base.dev;
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258 int pipe = pipe_config->cpu_transcoder;
5259 intel_clock_t clock;
5261 int refclk = 100000;
5263 mutex_lock(&dev_priv->dpio_lock);
5264 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5265 mutex_unlock(&dev_priv->dpio_lock);
5267 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5268 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5269 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5270 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5271 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5273 vlv_clock(refclk, &clock);
5275 /* clock.dot is the fast clock */
5276 pipe_config->port_clock = clock.dot / 5;
5279 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5280 struct intel_crtc_config *pipe_config)
5282 struct drm_device *dev = crtc->base.dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5286 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5287 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5289 tmp = I915_READ(PIPECONF(crtc->pipe));
5290 if (!(tmp & PIPECONF_ENABLE))
5293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5294 switch (tmp & PIPECONF_BPC_MASK) {
5296 pipe_config->pipe_bpp = 18;
5299 pipe_config->pipe_bpp = 24;
5301 case PIPECONF_10BPC:
5302 pipe_config->pipe_bpp = 30;
5309 if (INTEL_INFO(dev)->gen < 4)
5310 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5312 intel_get_pipe_timings(crtc, pipe_config);
5314 i9xx_get_pfit_config(crtc, pipe_config);
5316 if (INTEL_INFO(dev)->gen >= 4) {
5317 tmp = I915_READ(DPLL_MD(crtc->pipe));
5318 pipe_config->pixel_multiplier =
5319 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5320 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5321 pipe_config->dpll_hw_state.dpll_md = tmp;
5322 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5323 tmp = I915_READ(DPLL(crtc->pipe));
5324 pipe_config->pixel_multiplier =
5325 ((tmp & SDVO_MULTIPLIER_MASK)
5326 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5328 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5329 * port and will be fixed up in the encoder->get_config
5331 pipe_config->pixel_multiplier = 1;
5333 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5334 if (!IS_VALLEYVIEW(dev)) {
5335 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5336 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5338 /* Mask out read-only status bits. */
5339 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5340 DPLL_PORTC_READY_MASK |
5341 DPLL_PORTB_READY_MASK);
5344 if (IS_VALLEYVIEW(dev))
5345 vlv_crtc_clock_get(crtc, pipe_config);
5347 i9xx_crtc_clock_get(crtc, pipe_config);
5352 static void ironlake_init_pch_refclk(struct drm_device *dev)
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 struct drm_mode_config *mode_config = &dev->mode_config;
5356 struct intel_encoder *encoder;
5358 bool has_lvds = false;
5359 bool has_cpu_edp = false;
5360 bool has_panel = false;
5361 bool has_ck505 = false;
5362 bool can_ssc = false;
5364 /* We need to take the global config into account */
5365 list_for_each_entry(encoder, &mode_config->encoder_list,
5367 switch (encoder->type) {
5368 case INTEL_OUTPUT_LVDS:
5372 case INTEL_OUTPUT_EDP:
5374 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5380 if (HAS_PCH_IBX(dev)) {
5381 has_ck505 = dev_priv->vbt.display_clock_mode;
5382 can_ssc = has_ck505;
5388 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5389 has_panel, has_lvds, has_ck505);
5391 /* Ironlake: try to setup display ref clock before DPLL
5392 * enabling. This is only under driver's control after
5393 * PCH B stepping, previous chipset stepping should be
5394 * ignoring this setting.
5396 val = I915_READ(PCH_DREF_CONTROL);
5398 /* As we must carefully and slowly disable/enable each source in turn,
5399 * compute the final state we want first and check if we need to
5400 * make any changes at all.
5403 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5405 final |= DREF_NONSPREAD_CK505_ENABLE;
5407 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5409 final &= ~DREF_SSC_SOURCE_MASK;
5410 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5411 final &= ~DREF_SSC1_ENABLE;
5414 final |= DREF_SSC_SOURCE_ENABLE;
5416 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5417 final |= DREF_SSC1_ENABLE;
5420 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5421 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5423 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5425 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5427 final |= DREF_SSC_SOURCE_DISABLE;
5428 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5434 /* Always enable nonspread source */
5435 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5438 val |= DREF_NONSPREAD_CK505_ENABLE;
5440 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5443 val &= ~DREF_SSC_SOURCE_MASK;
5444 val |= DREF_SSC_SOURCE_ENABLE;
5446 /* SSC must be turned on before enabling the CPU output */
5447 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5448 DRM_DEBUG_KMS("Using SSC on panel\n");
5449 val |= DREF_SSC1_ENABLE;
5451 val &= ~DREF_SSC1_ENABLE;
5453 /* Get SSC going before enabling the outputs */
5454 I915_WRITE(PCH_DREF_CONTROL, val);
5455 POSTING_READ(PCH_DREF_CONTROL);
5458 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5460 /* Enable CPU source on CPU attached eDP */
5462 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5463 DRM_DEBUG_KMS("Using SSC on eDP\n");
5464 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5467 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5469 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5471 I915_WRITE(PCH_DREF_CONTROL, val);
5472 POSTING_READ(PCH_DREF_CONTROL);
5475 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5477 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5479 /* Turn off CPU output */
5480 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5482 I915_WRITE(PCH_DREF_CONTROL, val);
5483 POSTING_READ(PCH_DREF_CONTROL);
5486 /* Turn off the SSC source */
5487 val &= ~DREF_SSC_SOURCE_MASK;
5488 val |= DREF_SSC_SOURCE_DISABLE;
5491 val &= ~DREF_SSC1_ENABLE;
5493 I915_WRITE(PCH_DREF_CONTROL, val);
5494 POSTING_READ(PCH_DREF_CONTROL);
5498 BUG_ON(val != final);
5501 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5505 tmp = I915_READ(SOUTH_CHICKEN2);
5506 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5507 I915_WRITE(SOUTH_CHICKEN2, tmp);
5509 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5510 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5511 DRM_ERROR("FDI mPHY reset assert timeout\n");
5513 tmp = I915_READ(SOUTH_CHICKEN2);
5514 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5515 I915_WRITE(SOUTH_CHICKEN2, tmp);
5517 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5518 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5519 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5522 /* WaMPhyProgramming:hsw */
5523 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5527 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5528 tmp &= ~(0xFF << 24);
5529 tmp |= (0x12 << 24);
5530 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5532 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5534 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5536 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5538 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5540 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5541 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5542 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5544 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5545 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5546 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5548 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5551 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5553 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5556 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5558 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5561 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5563 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5566 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5568 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5569 tmp &= ~(0xFF << 16);
5570 tmp |= (0x1C << 16);
5571 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5573 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5574 tmp &= ~(0xFF << 16);
5575 tmp |= (0x1C << 16);
5576 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5578 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5580 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5582 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5584 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5586 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5587 tmp &= ~(0xF << 28);
5589 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5591 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5592 tmp &= ~(0xF << 28);
5594 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5597 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5598 * Programming" based on the parameters passed:
5599 * - Sequence to enable CLKOUT_DP
5600 * - Sequence to enable CLKOUT_DP without spread
5601 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5603 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5606 struct drm_i915_private *dev_priv = dev->dev_private;
5609 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5611 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5612 with_fdi, "LP PCH doesn't have FDI\n"))
5615 mutex_lock(&dev_priv->dpio_lock);
5617 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5618 tmp &= ~SBI_SSCCTL_DISABLE;
5619 tmp |= SBI_SSCCTL_PATHALT;
5620 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5625 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5626 tmp &= ~SBI_SSCCTL_PATHALT;
5627 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5630 lpt_reset_fdi_mphy(dev_priv);
5631 lpt_program_fdi_mphy(dev_priv);
5635 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5636 SBI_GEN0 : SBI_DBUFF0;
5637 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5638 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5639 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5641 mutex_unlock(&dev_priv->dpio_lock);
5644 /* Sequence to disable CLKOUT_DP */
5645 static void lpt_disable_clkout_dp(struct drm_device *dev)
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5650 mutex_lock(&dev_priv->dpio_lock);
5652 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5653 SBI_GEN0 : SBI_DBUFF0;
5654 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5655 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5656 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5658 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5659 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5660 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5661 tmp |= SBI_SSCCTL_PATHALT;
5662 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5665 tmp |= SBI_SSCCTL_DISABLE;
5666 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5669 mutex_unlock(&dev_priv->dpio_lock);
5672 static void lpt_init_pch_refclk(struct drm_device *dev)
5674 struct drm_mode_config *mode_config = &dev->mode_config;
5675 struct intel_encoder *encoder;
5676 bool has_vga = false;
5678 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5679 switch (encoder->type) {
5680 case INTEL_OUTPUT_ANALOG:
5687 lpt_enable_clkout_dp(dev, true, true);
5689 lpt_disable_clkout_dp(dev);
5693 * Initialize reference clocks when the driver loads
5695 void intel_init_pch_refclk(struct drm_device *dev)
5697 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5698 ironlake_init_pch_refclk(dev);
5699 else if (HAS_PCH_LPT(dev))
5700 lpt_init_pch_refclk(dev);
5703 static int ironlake_get_refclk(struct drm_crtc *crtc)
5705 struct drm_device *dev = crtc->dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct intel_encoder *encoder;
5708 int num_connectors = 0;
5709 bool is_lvds = false;
5711 for_each_encoder_on_crtc(dev, crtc, encoder) {
5712 switch (encoder->type) {
5713 case INTEL_OUTPUT_LVDS:
5720 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5721 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5722 dev_priv->vbt.lvds_ssc_freq);
5723 return dev_priv->vbt.lvds_ssc_freq * 1000;
5729 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5731 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733 int pipe = intel_crtc->pipe;
5738 switch (intel_crtc->config.pipe_bpp) {
5740 val |= PIPECONF_6BPC;
5743 val |= PIPECONF_8BPC;
5746 val |= PIPECONF_10BPC;
5749 val |= PIPECONF_12BPC;
5752 /* Case prevented by intel_choose_pipe_bpp_dither. */
5756 if (intel_crtc->config.dither)
5757 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5759 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5760 val |= PIPECONF_INTERLACED_ILK;
5762 val |= PIPECONF_PROGRESSIVE;
5764 if (intel_crtc->config.limited_color_range)
5765 val |= PIPECONF_COLOR_RANGE_SELECT;
5767 I915_WRITE(PIPECONF(pipe), val);
5768 POSTING_READ(PIPECONF(pipe));
5772 * Set up the pipe CSC unit.
5774 * Currently only full range RGB to limited range RGB conversion
5775 * is supported, but eventually this should handle various
5776 * RGB<->YCbCr scenarios as well.
5778 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5780 struct drm_device *dev = crtc->dev;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5783 int pipe = intel_crtc->pipe;
5784 uint16_t coeff = 0x7800; /* 1.0 */
5787 * TODO: Check what kind of values actually come out of the pipe
5788 * with these coeff/postoff values and adjust to get the best
5789 * accuracy. Perhaps we even need to take the bpc value into
5793 if (intel_crtc->config.limited_color_range)
5794 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5797 * GY/GU and RY/RU should be the other way around according
5798 * to BSpec, but reality doesn't agree. Just set them up in
5799 * a way that results in the correct picture.
5801 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5802 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5804 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5805 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5807 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5808 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5810 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5811 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5812 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5814 if (INTEL_INFO(dev)->gen > 6) {
5815 uint16_t postoff = 0;
5817 if (intel_crtc->config.limited_color_range)
5818 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5820 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5821 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5822 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5824 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5826 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5828 if (intel_crtc->config.limited_color_range)
5829 mode |= CSC_BLACK_SCREEN_OFFSET;
5831 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5835 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5837 struct drm_device *dev = crtc->dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5840 enum pipe pipe = intel_crtc->pipe;
5841 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5846 if (IS_HASWELL(dev) && intel_crtc->config.dither)
5847 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5849 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5850 val |= PIPECONF_INTERLACED_ILK;
5852 val |= PIPECONF_PROGRESSIVE;
5854 I915_WRITE(PIPECONF(cpu_transcoder), val);
5855 POSTING_READ(PIPECONF(cpu_transcoder));
5857 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5858 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5860 if (IS_BROADWELL(dev)) {
5863 switch (intel_crtc->config.pipe_bpp) {
5865 val |= PIPEMISC_DITHER_6_BPC;
5868 val |= PIPEMISC_DITHER_8_BPC;
5871 val |= PIPEMISC_DITHER_10_BPC;
5874 val |= PIPEMISC_DITHER_12_BPC;
5877 /* Case prevented by pipe_config_set_bpp. */
5881 if (intel_crtc->config.dither)
5882 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5884 I915_WRITE(PIPEMISC(pipe), val);
5888 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5889 intel_clock_t *clock,
5890 bool *has_reduced_clock,
5891 intel_clock_t *reduced_clock)
5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 struct intel_encoder *intel_encoder;
5897 const intel_limit_t *limit;
5898 bool ret, is_lvds = false;
5900 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5901 switch (intel_encoder->type) {
5902 case INTEL_OUTPUT_LVDS:
5908 refclk = ironlake_get_refclk(crtc);
5911 * Returns a set of divisors for the desired target clock with the given
5912 * refclk, or FALSE. The returned values represent the clock equation:
5913 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5915 limit = intel_limit(crtc, refclk);
5916 ret = dev_priv->display.find_dpll(limit, crtc,
5917 to_intel_crtc(crtc)->config.port_clock,
5918 refclk, NULL, clock);
5922 if (is_lvds && dev_priv->lvds_downclock_avail) {
5924 * Ensure we match the reduced clock's P to the target clock.
5925 * If the clocks don't match, we can't switch the display clock
5926 * by using the FP0/FP1. In such case we will disable the LVDS
5927 * downclock feature.
5929 *has_reduced_clock =
5930 dev_priv->display.find_dpll(limit, crtc,
5931 dev_priv->lvds_downclock,
5939 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5942 * Account for spread spectrum to avoid
5943 * oversubscribing the link. Max center spread
5944 * is 2.5%; use 5% for safety's sake.
5946 u32 bps = target_clock * bpp * 21 / 20;
5947 return bps / (link_bw * 8) + 1;
5950 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5952 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5955 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5957 intel_clock_t *reduced_clock, u32 *fp2)
5959 struct drm_crtc *crtc = &intel_crtc->base;
5960 struct drm_device *dev = crtc->dev;
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 struct intel_encoder *intel_encoder;
5964 int factor, num_connectors = 0;
5965 bool is_lvds = false, is_sdvo = false;
5967 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5968 switch (intel_encoder->type) {
5969 case INTEL_OUTPUT_LVDS:
5972 case INTEL_OUTPUT_SDVO:
5973 case INTEL_OUTPUT_HDMI:
5981 /* Enable autotuning of the PLL clock (if permissible) */
5984 if ((intel_panel_use_ssc(dev_priv) &&
5985 dev_priv->vbt.lvds_ssc_freq == 100) ||
5986 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5988 } else if (intel_crtc->config.sdvo_tv_clock)
5991 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5994 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6000 dpll |= DPLLB_MODE_LVDS;
6002 dpll |= DPLLB_MODE_DAC_SERIAL;
6004 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6005 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6008 dpll |= DPLL_SDVO_HIGH_SPEED;
6009 if (intel_crtc->config.has_dp_encoder)
6010 dpll |= DPLL_SDVO_HIGH_SPEED;
6012 /* compute bitmask from p1 value */
6013 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6015 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6017 switch (intel_crtc->config.dpll.p2) {
6019 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6022 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6025 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6028 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6032 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6033 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6035 dpll |= PLL_REF_INPUT_DREFCLK;
6037 return dpll | DPLL_VCO_ENABLE;
6040 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6042 struct drm_framebuffer *fb)
6044 struct drm_device *dev = crtc->dev;
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047 int pipe = intel_crtc->pipe;
6048 int plane = intel_crtc->plane;
6049 int num_connectors = 0;
6050 intel_clock_t clock, reduced_clock;
6051 u32 dpll = 0, fp = 0, fp2 = 0;
6052 bool ok, has_reduced_clock = false;
6053 bool is_lvds = false;
6054 struct intel_encoder *encoder;
6055 struct intel_shared_dpll *pll;
6058 for_each_encoder_on_crtc(dev, crtc, encoder) {
6059 switch (encoder->type) {
6060 case INTEL_OUTPUT_LVDS:
6068 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6069 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6071 ok = ironlake_compute_clocks(crtc, &clock,
6072 &has_reduced_clock, &reduced_clock);
6073 if (!ok && !intel_crtc->config.clock_set) {
6074 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6077 /* Compat-code for transition, will disappear. */
6078 if (!intel_crtc->config.clock_set) {
6079 intel_crtc->config.dpll.n = clock.n;
6080 intel_crtc->config.dpll.m1 = clock.m1;
6081 intel_crtc->config.dpll.m2 = clock.m2;
6082 intel_crtc->config.dpll.p1 = clock.p1;
6083 intel_crtc->config.dpll.p2 = clock.p2;
6086 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6087 if (intel_crtc->config.has_pch_encoder) {
6088 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6089 if (has_reduced_clock)
6090 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6092 dpll = ironlake_compute_dpll(intel_crtc,
6093 &fp, &reduced_clock,
6094 has_reduced_clock ? &fp2 : NULL);
6096 intel_crtc->config.dpll_hw_state.dpll = dpll;
6097 intel_crtc->config.dpll_hw_state.fp0 = fp;
6098 if (has_reduced_clock)
6099 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6101 intel_crtc->config.dpll_hw_state.fp1 = fp;
6103 pll = intel_get_shared_dpll(intel_crtc);
6105 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6110 intel_put_shared_dpll(intel_crtc);
6112 if (intel_crtc->config.has_dp_encoder)
6113 intel_dp_set_m_n(intel_crtc);
6115 if (is_lvds && has_reduced_clock && i915_powersave)
6116 intel_crtc->lowfreq_avail = true;
6118 intel_crtc->lowfreq_avail = false;
6120 intel_set_pipe_timings(intel_crtc);
6122 if (intel_crtc->config.has_pch_encoder) {
6123 intel_cpu_transcoder_set_m_n(intel_crtc,
6124 &intel_crtc->config.fdi_m_n);
6127 ironlake_set_pipeconf(crtc);
6129 /* Set up the display plane register */
6130 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6131 POSTING_READ(DSPCNTR(plane));
6133 ret = intel_pipe_set_base(crtc, x, y, fb);
6138 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6139 struct intel_link_m_n *m_n)
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 enum pipe pipe = crtc->pipe;
6145 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6146 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6147 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6149 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6150 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6151 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6154 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6155 enum transcoder transcoder,
6156 struct intel_link_m_n *m_n)
6158 struct drm_device *dev = crtc->base.dev;
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160 enum pipe pipe = crtc->pipe;
6162 if (INTEL_INFO(dev)->gen >= 5) {
6163 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6164 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6165 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6167 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6168 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6169 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6171 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6172 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6173 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6175 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6176 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6177 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6181 void intel_dp_get_m_n(struct intel_crtc *crtc,
6182 struct intel_crtc_config *pipe_config)
6184 if (crtc->config.has_pch_encoder)
6185 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6187 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6188 &pipe_config->dp_m_n);
6191 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6192 struct intel_crtc_config *pipe_config)
6194 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6195 &pipe_config->fdi_m_n);
6198 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6199 struct intel_crtc_config *pipe_config)
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6205 tmp = I915_READ(PF_CTL(crtc->pipe));
6207 if (tmp & PF_ENABLE) {
6208 pipe_config->pch_pfit.enabled = true;
6209 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6210 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6212 /* We currently do not free assignements of panel fitters on
6213 * ivb/hsw (since we don't use the higher upscaling modes which
6214 * differentiates them) so just WARN about this case for now. */
6216 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6217 PF_PIPE_SEL_IVB(crtc->pipe));
6222 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6223 struct intel_crtc_config *pipe_config)
6225 struct drm_device *dev = crtc->base.dev;
6226 struct drm_i915_private *dev_priv = dev->dev_private;
6229 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6230 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6232 tmp = I915_READ(PIPECONF(crtc->pipe));
6233 if (!(tmp & PIPECONF_ENABLE))
6236 switch (tmp & PIPECONF_BPC_MASK) {
6238 pipe_config->pipe_bpp = 18;
6241 pipe_config->pipe_bpp = 24;
6243 case PIPECONF_10BPC:
6244 pipe_config->pipe_bpp = 30;
6246 case PIPECONF_12BPC:
6247 pipe_config->pipe_bpp = 36;
6253 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6254 struct intel_shared_dpll *pll;
6256 pipe_config->has_pch_encoder = true;
6258 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6259 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6260 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6262 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6264 if (HAS_PCH_IBX(dev_priv->dev)) {
6265 pipe_config->shared_dpll =
6266 (enum intel_dpll_id) crtc->pipe;
6268 tmp = I915_READ(PCH_DPLL_SEL);
6269 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6270 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6272 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6275 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6277 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6278 &pipe_config->dpll_hw_state));
6280 tmp = pipe_config->dpll_hw_state.dpll;
6281 pipe_config->pixel_multiplier =
6282 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6283 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6285 ironlake_pch_clock_get(crtc, pipe_config);
6287 pipe_config->pixel_multiplier = 1;
6290 intel_get_pipe_timings(crtc, pipe_config);
6292 ironlake_get_pfit_config(crtc, pipe_config);
6297 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6299 struct drm_device *dev = dev_priv->dev;
6300 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6301 struct intel_crtc *crtc;
6302 unsigned long irqflags;
6305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6306 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6307 pipe_name(crtc->pipe));
6309 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6310 WARN(plls->spll_refcount, "SPLL enabled\n");
6311 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6312 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6313 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6314 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6315 "CPU PWM1 enabled\n");
6316 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6317 "CPU PWM2 enabled\n");
6318 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6319 "PCH PWM1 enabled\n");
6320 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6321 "Utility pin enabled\n");
6322 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6324 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6325 val = I915_READ(DEIMR);
6326 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6327 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6328 val = I915_READ(SDEIMR);
6329 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6330 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6331 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6335 * This function implements pieces of two sequences from BSpec:
6336 * - Sequence for display software to disable LCPLL
6337 * - Sequence for display software to allow package C8+
6338 * The steps implemented here are just the steps that actually touch the LCPLL
6339 * register. Callers should take care of disabling all the display engine
6340 * functions, doing the mode unset, fixing interrupts, etc.
6342 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6343 bool switch_to_fclk, bool allow_power_down)
6347 assert_can_disable_lcpll(dev_priv);
6349 val = I915_READ(LCPLL_CTL);
6351 if (switch_to_fclk) {
6352 val |= LCPLL_CD_SOURCE_FCLK;
6353 I915_WRITE(LCPLL_CTL, val);
6355 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6356 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6357 DRM_ERROR("Switching to FCLK failed\n");
6359 val = I915_READ(LCPLL_CTL);
6362 val |= LCPLL_PLL_DISABLE;
6363 I915_WRITE(LCPLL_CTL, val);
6364 POSTING_READ(LCPLL_CTL);
6366 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6367 DRM_ERROR("LCPLL still locked\n");
6369 val = I915_READ(D_COMP);
6370 val |= D_COMP_COMP_DISABLE;
6371 mutex_lock(&dev_priv->rps.hw_lock);
6372 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6373 DRM_ERROR("Failed to disable D_COMP\n");
6374 mutex_unlock(&dev_priv->rps.hw_lock);
6375 POSTING_READ(D_COMP);
6378 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6379 DRM_ERROR("D_COMP RCOMP still in progress\n");
6381 if (allow_power_down) {
6382 val = I915_READ(LCPLL_CTL);
6383 val |= LCPLL_POWER_DOWN_ALLOW;
6384 I915_WRITE(LCPLL_CTL, val);
6385 POSTING_READ(LCPLL_CTL);
6390 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6393 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6397 val = I915_READ(LCPLL_CTL);
6399 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6400 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6403 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6404 * we'll hang the machine! */
6405 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6407 if (val & LCPLL_POWER_DOWN_ALLOW) {
6408 val &= ~LCPLL_POWER_DOWN_ALLOW;
6409 I915_WRITE(LCPLL_CTL, val);
6410 POSTING_READ(LCPLL_CTL);
6413 val = I915_READ(D_COMP);
6414 val |= D_COMP_COMP_FORCE;
6415 val &= ~D_COMP_COMP_DISABLE;
6416 mutex_lock(&dev_priv->rps.hw_lock);
6417 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6418 DRM_ERROR("Failed to enable D_COMP\n");
6419 mutex_unlock(&dev_priv->rps.hw_lock);
6420 POSTING_READ(D_COMP);
6422 val = I915_READ(LCPLL_CTL);
6423 val &= ~LCPLL_PLL_DISABLE;
6424 I915_WRITE(LCPLL_CTL, val);
6426 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6427 DRM_ERROR("LCPLL not locked yet\n");
6429 if (val & LCPLL_CD_SOURCE_FCLK) {
6430 val = I915_READ(LCPLL_CTL);
6431 val &= ~LCPLL_CD_SOURCE_FCLK;
6432 I915_WRITE(LCPLL_CTL, val);
6434 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6435 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6436 DRM_ERROR("Switching back to LCPLL failed\n");
6439 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6442 void hsw_enable_pc8_work(struct work_struct *__work)
6444 struct drm_i915_private *dev_priv =
6445 container_of(to_delayed_work(__work), struct drm_i915_private,
6447 struct drm_device *dev = dev_priv->dev;
6450 if (dev_priv->pc8.enabled)
6453 DRM_DEBUG_KMS("Enabling package C8+\n");
6455 dev_priv->pc8.enabled = true;
6457 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6459 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6463 lpt_disable_clkout_dp(dev);
6464 hsw_pc8_disable_interrupts(dev);
6465 hsw_disable_lcpll(dev_priv, true, true);
6468 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6470 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6471 WARN(dev_priv->pc8.disable_count < 1,
6472 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6474 dev_priv->pc8.disable_count--;
6475 if (dev_priv->pc8.disable_count != 0)
6478 schedule_delayed_work(&dev_priv->pc8.enable_work,
6479 msecs_to_jiffies(i915_pc8_timeout));
6482 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6484 struct drm_device *dev = dev_priv->dev;
6487 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6488 WARN(dev_priv->pc8.disable_count < 0,
6489 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6491 dev_priv->pc8.disable_count++;
6492 if (dev_priv->pc8.disable_count != 1)
6495 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6496 if (!dev_priv->pc8.enabled)
6499 DRM_DEBUG_KMS("Disabling package C8+\n");
6501 hsw_restore_lcpll(dev_priv);
6502 hsw_pc8_restore_interrupts(dev);
6503 lpt_init_pch_refclk(dev);
6505 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6506 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6507 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6508 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6511 intel_prepare_ddi(dev);
6512 i915_gem_init_swizzling(dev);
6513 mutex_lock(&dev_priv->rps.hw_lock);
6514 gen6_update_ring_freq(dev);
6515 mutex_unlock(&dev_priv->rps.hw_lock);
6516 dev_priv->pc8.enabled = false;
6519 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6521 mutex_lock(&dev_priv->pc8.lock);
6522 __hsw_enable_package_c8(dev_priv);
6523 mutex_unlock(&dev_priv->pc8.lock);
6526 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6528 mutex_lock(&dev_priv->pc8.lock);
6529 __hsw_disable_package_c8(dev_priv);
6530 mutex_unlock(&dev_priv->pc8.lock);
6533 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6535 struct drm_device *dev = dev_priv->dev;
6536 struct intel_crtc *crtc;
6539 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6540 if (crtc->base.enabled)
6543 /* This case is still possible since we have the i915.disable_power_well
6544 * parameter and also the KVMr or something else might be requesting the
6546 val = I915_READ(HSW_PWR_WELL_DRIVER);
6548 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6555 /* Since we're called from modeset_global_resources there's no way to
6556 * symmetrically increase and decrease the refcount, so we use
6557 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6560 static void hsw_update_package_c8(struct drm_device *dev)
6562 struct drm_i915_private *dev_priv = dev->dev_private;
6565 if (!i915_enable_pc8)
6568 mutex_lock(&dev_priv->pc8.lock);
6570 allow = hsw_can_enable_package_c8(dev_priv);
6572 if (allow == dev_priv->pc8.requirements_met)
6575 dev_priv->pc8.requirements_met = allow;
6578 __hsw_enable_package_c8(dev_priv);
6580 __hsw_disable_package_c8(dev_priv);
6583 mutex_unlock(&dev_priv->pc8.lock);
6586 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6588 if (!dev_priv->pc8.gpu_idle) {
6589 dev_priv->pc8.gpu_idle = true;
6590 hsw_enable_package_c8(dev_priv);
6594 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6596 if (dev_priv->pc8.gpu_idle) {
6597 dev_priv->pc8.gpu_idle = false;
6598 hsw_disable_package_c8(dev_priv);
6602 #define for_each_power_domain(domain, mask) \
6603 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6604 if ((1 << (domain)) & (mask))
6606 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6607 enum pipe pipe, bool pfit_enabled)
6610 enum transcoder transcoder;
6612 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6614 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6615 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6617 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6622 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6624 struct drm_i915_private *dev_priv = dev->dev_private;
6626 if (dev_priv->power_domains.init_power_on == enable)
6630 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6632 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6634 dev_priv->power_domains.init_power_on = enable;
6637 static void modeset_update_power_wells(struct drm_device *dev)
6639 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6640 struct intel_crtc *crtc;
6643 * First get all needed power domains, then put all unneeded, to avoid
6644 * any unnecessary toggling of the power wells.
6646 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6647 enum intel_display_power_domain domain;
6649 if (!crtc->base.enabled)
6652 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6654 crtc->config.pch_pfit.enabled);
6656 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6657 intel_display_power_get(dev, domain);
6660 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6661 enum intel_display_power_domain domain;
6663 for_each_power_domain(domain, crtc->enabled_power_domains)
6664 intel_display_power_put(dev, domain);
6666 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6669 intel_display_set_init_power(dev, false);
6672 static void haswell_modeset_global_resources(struct drm_device *dev)
6674 modeset_update_power_wells(dev);
6675 hsw_update_package_c8(dev);
6678 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6680 struct drm_framebuffer *fb)
6682 struct drm_device *dev = crtc->dev;
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685 int plane = intel_crtc->plane;
6688 if (!intel_ddi_pll_mode_set(crtc))
6691 if (intel_crtc->config.has_dp_encoder)
6692 intel_dp_set_m_n(intel_crtc);
6694 intel_crtc->lowfreq_avail = false;
6696 intel_set_pipe_timings(intel_crtc);
6698 if (intel_crtc->config.has_pch_encoder) {
6699 intel_cpu_transcoder_set_m_n(intel_crtc,
6700 &intel_crtc->config.fdi_m_n);
6703 haswell_set_pipeconf(crtc);
6705 intel_set_pipe_csc(crtc);
6707 /* Set up the display plane register */
6708 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6709 POSTING_READ(DSPCNTR(plane));
6711 ret = intel_pipe_set_base(crtc, x, y, fb);
6716 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6717 struct intel_crtc_config *pipe_config)
6719 struct drm_device *dev = crtc->base.dev;
6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 enum intel_display_power_domain pfit_domain;
6724 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6725 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6727 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6728 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6729 enum pipe trans_edp_pipe;
6730 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6732 WARN(1, "unknown pipe linked to edp transcoder\n");
6733 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6734 case TRANS_DDI_EDP_INPUT_A_ON:
6735 trans_edp_pipe = PIPE_A;
6737 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6738 trans_edp_pipe = PIPE_B;
6740 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6741 trans_edp_pipe = PIPE_C;
6745 if (trans_edp_pipe == crtc->pipe)
6746 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6749 if (!intel_display_power_enabled(dev,
6750 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6753 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6754 if (!(tmp & PIPECONF_ENABLE))
6758 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6759 * DDI E. So just check whether this pipe is wired to DDI E and whether
6760 * the PCH transcoder is on.
6762 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6763 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6764 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6765 pipe_config->has_pch_encoder = true;
6767 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6768 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6769 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6771 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6774 intel_get_pipe_timings(crtc, pipe_config);
6776 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6777 if (intel_display_power_enabled(dev, pfit_domain))
6778 ironlake_get_pfit_config(crtc, pipe_config);
6780 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6781 (I915_READ(IPS_CTL) & IPS_ENABLE);
6783 pipe_config->pixel_multiplier = 1;
6788 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6790 struct drm_framebuffer *fb)
6792 struct drm_device *dev = crtc->dev;
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 struct intel_encoder *encoder;
6795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6796 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6797 int pipe = intel_crtc->pipe;
6800 drm_vblank_pre_modeset(dev, pipe);
6802 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6804 drm_vblank_post_modeset(dev, pipe);
6809 for_each_encoder_on_crtc(dev, crtc, encoder) {
6810 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6811 encoder->base.base.id,
6812 drm_get_encoder_name(&encoder->base),
6813 mode->base.id, mode->name);
6814 encoder->mode_set(encoder);
6823 } hdmi_audio_clock[] = {
6824 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6825 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6826 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6827 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6828 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6829 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6830 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6831 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6832 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6833 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6836 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6837 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6841 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6842 if (mode->clock == hdmi_audio_clock[i].clock)
6846 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6847 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6851 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6852 hdmi_audio_clock[i].clock,
6853 hdmi_audio_clock[i].config);
6855 return hdmi_audio_clock[i].config;
6858 static bool intel_eld_uptodate(struct drm_connector *connector,
6859 int reg_eldv, uint32_t bits_eldv,
6860 int reg_elda, uint32_t bits_elda,
6863 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6864 uint8_t *eld = connector->eld;
6867 i = I915_READ(reg_eldv);
6876 i = I915_READ(reg_elda);
6878 I915_WRITE(reg_elda, i);
6880 for (i = 0; i < eld[2]; i++)
6881 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6887 static void g4x_write_eld(struct drm_connector *connector,
6888 struct drm_crtc *crtc,
6889 struct drm_display_mode *mode)
6891 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6892 uint8_t *eld = connector->eld;
6897 i = I915_READ(G4X_AUD_VID_DID);
6899 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6900 eldv = G4X_ELDV_DEVCL_DEVBLC;
6902 eldv = G4X_ELDV_DEVCTG;
6904 if (intel_eld_uptodate(connector,
6905 G4X_AUD_CNTL_ST, eldv,
6906 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6907 G4X_HDMIW_HDMIEDID))
6910 i = I915_READ(G4X_AUD_CNTL_ST);
6911 i &= ~(eldv | G4X_ELD_ADDR);
6912 len = (i >> 9) & 0x1f; /* ELD buffer size */
6913 I915_WRITE(G4X_AUD_CNTL_ST, i);
6918 len = min_t(uint8_t, eld[2], len);
6919 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6920 for (i = 0; i < len; i++)
6921 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6923 i = I915_READ(G4X_AUD_CNTL_ST);
6925 I915_WRITE(G4X_AUD_CNTL_ST, i);
6928 static void haswell_write_eld(struct drm_connector *connector,
6929 struct drm_crtc *crtc,
6930 struct drm_display_mode *mode)
6932 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6933 uint8_t *eld = connector->eld;
6934 struct drm_device *dev = crtc->dev;
6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6939 int pipe = to_intel_crtc(crtc)->pipe;
6942 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6943 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6944 int aud_config = HSW_AUD_CFG(pipe);
6945 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6948 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6950 /* Audio output enable */
6951 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6952 tmp = I915_READ(aud_cntrl_st2);
6953 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6954 I915_WRITE(aud_cntrl_st2, tmp);
6956 /* Wait for 1 vertical blank */
6957 intel_wait_for_vblank(dev, pipe);
6959 /* Set ELD valid state */
6960 tmp = I915_READ(aud_cntrl_st2);
6961 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6962 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6963 I915_WRITE(aud_cntrl_st2, tmp);
6964 tmp = I915_READ(aud_cntrl_st2);
6965 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6967 /* Enable HDMI mode */
6968 tmp = I915_READ(aud_config);
6969 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6970 /* clear N_programing_enable and N_value_index */
6971 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6972 I915_WRITE(aud_config, tmp);
6974 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6976 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6977 intel_crtc->eld_vld = true;
6979 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6980 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6981 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6982 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6984 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6987 if (intel_eld_uptodate(connector,
6988 aud_cntrl_st2, eldv,
6989 aud_cntl_st, IBX_ELD_ADDRESS,
6993 i = I915_READ(aud_cntrl_st2);
6995 I915_WRITE(aud_cntrl_st2, i);
7000 i = I915_READ(aud_cntl_st);
7001 i &= ~IBX_ELD_ADDRESS;
7002 I915_WRITE(aud_cntl_st, i);
7003 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7004 DRM_DEBUG_DRIVER("port num:%d\n", i);
7006 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7007 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7008 for (i = 0; i < len; i++)
7009 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7011 i = I915_READ(aud_cntrl_st2);
7013 I915_WRITE(aud_cntrl_st2, i);
7017 static void ironlake_write_eld(struct drm_connector *connector,
7018 struct drm_crtc *crtc,
7019 struct drm_display_mode *mode)
7021 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7022 uint8_t *eld = connector->eld;
7030 int pipe = to_intel_crtc(crtc)->pipe;
7032 if (HAS_PCH_IBX(connector->dev)) {
7033 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7034 aud_config = IBX_AUD_CFG(pipe);
7035 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7036 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7038 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7039 aud_config = CPT_AUD_CFG(pipe);
7040 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7041 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7044 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7046 i = I915_READ(aud_cntl_st);
7047 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7049 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7050 /* operate blindly on all ports */
7051 eldv = IBX_ELD_VALIDB;
7052 eldv |= IBX_ELD_VALIDB << 4;
7053 eldv |= IBX_ELD_VALIDB << 8;
7055 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7056 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7059 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7060 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7061 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7062 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7064 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7067 if (intel_eld_uptodate(connector,
7068 aud_cntrl_st2, eldv,
7069 aud_cntl_st, IBX_ELD_ADDRESS,
7073 i = I915_READ(aud_cntrl_st2);
7075 I915_WRITE(aud_cntrl_st2, i);
7080 i = I915_READ(aud_cntl_st);
7081 i &= ~IBX_ELD_ADDRESS;
7082 I915_WRITE(aud_cntl_st, i);
7084 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7085 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7086 for (i = 0; i < len; i++)
7087 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7089 i = I915_READ(aud_cntrl_st2);
7091 I915_WRITE(aud_cntrl_st2, i);
7094 void intel_write_eld(struct drm_encoder *encoder,
7095 struct drm_display_mode *mode)
7097 struct drm_crtc *crtc = encoder->crtc;
7098 struct drm_connector *connector;
7099 struct drm_device *dev = encoder->dev;
7100 struct drm_i915_private *dev_priv = dev->dev_private;
7102 connector = drm_select_eld(encoder, mode);
7106 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7108 drm_get_connector_name(connector),
7109 connector->encoder->base.id,
7110 drm_get_encoder_name(connector->encoder));
7112 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7114 if (dev_priv->display.write_eld)
7115 dev_priv->display.write_eld(connector, crtc, mode);
7118 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7120 struct drm_device *dev = crtc->dev;
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7123 bool visible = base != 0;
7126 if (intel_crtc->cursor_visible == visible)
7129 cntl = I915_READ(_CURACNTR);
7131 /* On these chipsets we can only modify the base whilst
7132 * the cursor is disabled.
7134 I915_WRITE(_CURABASE, base);
7136 cntl &= ~(CURSOR_FORMAT_MASK);
7137 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7138 cntl |= CURSOR_ENABLE |
7139 CURSOR_GAMMA_ENABLE |
7142 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7143 I915_WRITE(_CURACNTR, cntl);
7145 intel_crtc->cursor_visible = visible;
7148 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7150 struct drm_device *dev = crtc->dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7153 int pipe = intel_crtc->pipe;
7154 bool visible = base != 0;
7156 if (intel_crtc->cursor_visible != visible) {
7157 uint32_t cntl = I915_READ(CURCNTR(pipe));
7159 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7160 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7161 cntl |= pipe << 28; /* Connect to correct pipe */
7163 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7164 cntl |= CURSOR_MODE_DISABLE;
7166 I915_WRITE(CURCNTR(pipe), cntl);
7168 intel_crtc->cursor_visible = visible;
7170 /* and commit changes on next vblank */
7171 I915_WRITE(CURBASE(pipe), base);
7174 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7176 struct drm_device *dev = crtc->dev;
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 int pipe = intel_crtc->pipe;
7180 bool visible = base != 0;
7182 if (intel_crtc->cursor_visible != visible) {
7183 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7185 cntl &= ~CURSOR_MODE;
7186 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7188 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7189 cntl |= CURSOR_MODE_DISABLE;
7191 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7192 cntl |= CURSOR_PIPE_CSC_ENABLE;
7193 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7195 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7197 intel_crtc->cursor_visible = visible;
7199 /* and commit changes on next vblank */
7200 I915_WRITE(CURBASE_IVB(pipe), base);
7203 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7204 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7207 struct drm_device *dev = crtc->dev;
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7210 int pipe = intel_crtc->pipe;
7211 int x = intel_crtc->cursor_x;
7212 int y = intel_crtc->cursor_y;
7213 u32 base = 0, pos = 0;
7217 base = intel_crtc->cursor_addr;
7219 if (x >= intel_crtc->config.pipe_src_w)
7222 if (y >= intel_crtc->config.pipe_src_h)
7226 if (x + intel_crtc->cursor_width <= 0)
7229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7232 pos |= x << CURSOR_X_SHIFT;
7235 if (y + intel_crtc->cursor_height <= 0)
7238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7241 pos |= y << CURSOR_Y_SHIFT;
7243 visible = base != 0;
7244 if (!visible && !intel_crtc->cursor_visible)
7247 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7248 I915_WRITE(CURPOS_IVB(pipe), pos);
7249 ivb_update_cursor(crtc, base);
7251 I915_WRITE(CURPOS(pipe), pos);
7252 if (IS_845G(dev) || IS_I865G(dev))
7253 i845_update_cursor(crtc, base);
7255 i9xx_update_cursor(crtc, base);
7259 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7260 struct drm_file *file,
7262 uint32_t width, uint32_t height)
7264 struct drm_device *dev = crtc->dev;
7265 struct drm_i915_private *dev_priv = dev->dev_private;
7266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7267 struct drm_i915_gem_object *obj;
7271 /* if we want to turn off the cursor ignore width and height */
7273 DRM_DEBUG_KMS("cursor off\n");
7276 mutex_lock(&dev->struct_mutex);
7280 /* Currently we only support 64x64 cursors */
7281 if (width != 64 || height != 64) {
7282 DRM_ERROR("we currently only support 64x64 cursors\n");
7286 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7287 if (&obj->base == NULL)
7290 if (obj->base.size < width * height * 4) {
7291 DRM_ERROR("buffer is to small\n");
7296 /* we only need to pin inside GTT if cursor is non-phy */
7297 mutex_lock(&dev->struct_mutex);
7298 if (!dev_priv->info->cursor_needs_physical) {
7301 if (obj->tiling_mode) {
7302 DRM_ERROR("cursor cannot be tiled\n");
7307 /* Note that the w/a also requires 2 PTE of padding following
7308 * the bo. We currently fill all unused PTE with the shadow
7309 * page and so we should always have valid PTE following the
7310 * cursor preventing the VT-d warning.
7313 if (need_vtd_wa(dev))
7314 alignment = 64*1024;
7316 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7318 DRM_ERROR("failed to move cursor bo into the GTT\n");
7322 ret = i915_gem_object_put_fence(obj);
7324 DRM_ERROR("failed to release fence for cursor");
7328 addr = i915_gem_obj_ggtt_offset(obj);
7330 int align = IS_I830(dev) ? 16 * 1024 : 256;
7331 ret = i915_gem_attach_phys_object(dev, obj,
7332 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7335 DRM_ERROR("failed to attach phys object\n");
7338 addr = obj->phys_obj->handle->busaddr;
7342 I915_WRITE(CURSIZE, (height << 12) | width);
7345 if (intel_crtc->cursor_bo) {
7346 if (dev_priv->info->cursor_needs_physical) {
7347 if (intel_crtc->cursor_bo != obj)
7348 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7350 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7351 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7354 mutex_unlock(&dev->struct_mutex);
7356 intel_crtc->cursor_addr = addr;
7357 intel_crtc->cursor_bo = obj;
7358 intel_crtc->cursor_width = width;
7359 intel_crtc->cursor_height = height;
7361 if (intel_crtc->active)
7362 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7366 i915_gem_object_unpin_from_display_plane(obj);
7368 mutex_unlock(&dev->struct_mutex);
7370 drm_gem_object_unreference_unlocked(&obj->base);
7374 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7378 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7379 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7381 if (intel_crtc->active)
7382 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7387 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7388 u16 *blue, uint32_t start, uint32_t size)
7390 int end = (start + size > 256) ? 256 : start + size, i;
7391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7393 for (i = start; i < end; i++) {
7394 intel_crtc->lut_r[i] = red[i] >> 8;
7395 intel_crtc->lut_g[i] = green[i] >> 8;
7396 intel_crtc->lut_b[i] = blue[i] >> 8;
7399 intel_crtc_load_lut(crtc);
7402 /* VESA 640x480x72Hz mode to set on the pipe */
7403 static struct drm_display_mode load_detect_mode = {
7404 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7405 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7408 static struct drm_framebuffer *
7409 intel_framebuffer_create(struct drm_device *dev,
7410 struct drm_mode_fb_cmd2 *mode_cmd,
7411 struct drm_i915_gem_object *obj)
7413 struct intel_framebuffer *intel_fb;
7416 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7418 drm_gem_object_unreference_unlocked(&obj->base);
7419 return ERR_PTR(-ENOMEM);
7422 ret = i915_mutex_lock_interruptible(dev);
7426 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7427 mutex_unlock(&dev->struct_mutex);
7431 return &intel_fb->base;
7433 drm_gem_object_unreference_unlocked(&obj->base);
7436 return ERR_PTR(ret);
7440 intel_framebuffer_pitch_for_width(int width, int bpp)
7442 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7443 return ALIGN(pitch, 64);
7447 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7449 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7450 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7453 static struct drm_framebuffer *
7454 intel_framebuffer_create_for_mode(struct drm_device *dev,
7455 struct drm_display_mode *mode,
7458 struct drm_i915_gem_object *obj;
7459 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7461 obj = i915_gem_alloc_object(dev,
7462 intel_framebuffer_size_for_mode(mode, bpp));
7464 return ERR_PTR(-ENOMEM);
7466 mode_cmd.width = mode->hdisplay;
7467 mode_cmd.height = mode->vdisplay;
7468 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7470 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7472 return intel_framebuffer_create(dev, &mode_cmd, obj);
7475 static struct drm_framebuffer *
7476 mode_fits_in_fbdev(struct drm_device *dev,
7477 struct drm_display_mode *mode)
7479 #ifdef CONFIG_DRM_I915_FBDEV
7480 struct drm_i915_private *dev_priv = dev->dev_private;
7481 struct drm_i915_gem_object *obj;
7482 struct drm_framebuffer *fb;
7484 if (dev_priv->fbdev == NULL)
7487 obj = dev_priv->fbdev->ifb.obj;
7491 fb = &dev_priv->fbdev->ifb.base;
7492 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7493 fb->bits_per_pixel))
7496 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7505 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7506 struct drm_display_mode *mode,
7507 struct intel_load_detect_pipe *old)
7509 struct intel_crtc *intel_crtc;
7510 struct intel_encoder *intel_encoder =
7511 intel_attached_encoder(connector);
7512 struct drm_crtc *possible_crtc;
7513 struct drm_encoder *encoder = &intel_encoder->base;
7514 struct drm_crtc *crtc = NULL;
7515 struct drm_device *dev = encoder->dev;
7516 struct drm_framebuffer *fb;
7519 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7520 connector->base.id, drm_get_connector_name(connector),
7521 encoder->base.id, drm_get_encoder_name(encoder));
7524 * Algorithm gets a little messy:
7526 * - if the connector already has an assigned crtc, use it (but make
7527 * sure it's on first)
7529 * - try to find the first unused crtc that can drive this connector,
7530 * and use that if we find one
7533 /* See if we already have a CRTC for this connector */
7534 if (encoder->crtc) {
7535 crtc = encoder->crtc;
7537 mutex_lock(&crtc->mutex);
7539 old->dpms_mode = connector->dpms;
7540 old->load_detect_temp = false;
7542 /* Make sure the crtc and connector are running */
7543 if (connector->dpms != DRM_MODE_DPMS_ON)
7544 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7549 /* Find an unused one (if possible) */
7550 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7552 if (!(encoder->possible_crtcs & (1 << i)))
7554 if (!possible_crtc->enabled) {
7555 crtc = possible_crtc;
7561 * If we didn't find an unused CRTC, don't use any.
7564 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7568 mutex_lock(&crtc->mutex);
7569 intel_encoder->new_crtc = to_intel_crtc(crtc);
7570 to_intel_connector(connector)->new_encoder = intel_encoder;
7572 intel_crtc = to_intel_crtc(crtc);
7573 old->dpms_mode = connector->dpms;
7574 old->load_detect_temp = true;
7575 old->release_fb = NULL;
7578 mode = &load_detect_mode;
7580 /* We need a framebuffer large enough to accommodate all accesses
7581 * that the plane may generate whilst we perform load detection.
7582 * We can not rely on the fbcon either being present (we get called
7583 * during its initialisation to detect all boot displays, or it may
7584 * not even exist) or that it is large enough to satisfy the
7587 fb = mode_fits_in_fbdev(dev, mode);
7589 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7590 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7591 old->release_fb = fb;
7593 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7595 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7596 mutex_unlock(&crtc->mutex);
7600 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7601 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7602 if (old->release_fb)
7603 old->release_fb->funcs->destroy(old->release_fb);
7604 mutex_unlock(&crtc->mutex);
7608 /* let the connector get through one full cycle before testing */
7609 intel_wait_for_vblank(dev, intel_crtc->pipe);
7613 void intel_release_load_detect_pipe(struct drm_connector *connector,
7614 struct intel_load_detect_pipe *old)
7616 struct intel_encoder *intel_encoder =
7617 intel_attached_encoder(connector);
7618 struct drm_encoder *encoder = &intel_encoder->base;
7619 struct drm_crtc *crtc = encoder->crtc;
7621 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7622 connector->base.id, drm_get_connector_name(connector),
7623 encoder->base.id, drm_get_encoder_name(encoder));
7625 if (old->load_detect_temp) {
7626 to_intel_connector(connector)->new_encoder = NULL;
7627 intel_encoder->new_crtc = NULL;
7628 intel_set_mode(crtc, NULL, 0, 0, NULL);
7630 if (old->release_fb) {
7631 drm_framebuffer_unregister_private(old->release_fb);
7632 drm_framebuffer_unreference(old->release_fb);
7635 mutex_unlock(&crtc->mutex);
7639 /* Switch crtc and encoder back off if necessary */
7640 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7641 connector->funcs->dpms(connector, old->dpms_mode);
7643 mutex_unlock(&crtc->mutex);
7646 static int i9xx_pll_refclk(struct drm_device *dev,
7647 const struct intel_crtc_config *pipe_config)
7649 struct drm_i915_private *dev_priv = dev->dev_private;
7650 u32 dpll = pipe_config->dpll_hw_state.dpll;
7652 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7653 return dev_priv->vbt.lvds_ssc_freq * 1000;
7654 else if (HAS_PCH_SPLIT(dev))
7656 else if (!IS_GEN2(dev))
7662 /* Returns the clock of the currently programmed mode of the given pipe. */
7663 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7664 struct intel_crtc_config *pipe_config)
7666 struct drm_device *dev = crtc->base.dev;
7667 struct drm_i915_private *dev_priv = dev->dev_private;
7668 int pipe = pipe_config->cpu_transcoder;
7669 u32 dpll = pipe_config->dpll_hw_state.dpll;
7671 intel_clock_t clock;
7672 int refclk = i9xx_pll_refclk(dev, pipe_config);
7674 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7675 fp = pipe_config->dpll_hw_state.fp0;
7677 fp = pipe_config->dpll_hw_state.fp1;
7679 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7680 if (IS_PINEVIEW(dev)) {
7681 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7682 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7684 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7685 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7688 if (!IS_GEN2(dev)) {
7689 if (IS_PINEVIEW(dev))
7690 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7691 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7694 DPLL_FPA01_P1_POST_DIV_SHIFT);
7696 switch (dpll & DPLL_MODE_MASK) {
7697 case DPLLB_MODE_DAC_SERIAL:
7698 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7701 case DPLLB_MODE_LVDS:
7702 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7706 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7707 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7711 if (IS_PINEVIEW(dev))
7712 pineview_clock(refclk, &clock);
7714 i9xx_clock(refclk, &clock);
7716 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7719 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7720 DPLL_FPA01_P1_POST_DIV_SHIFT);
7723 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7726 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7727 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7729 if (dpll & PLL_P2_DIVIDE_BY_4)
7735 i9xx_clock(refclk, &clock);
7739 * This value includes pixel_multiplier. We will use
7740 * port_clock to compute adjusted_mode.crtc_clock in the
7741 * encoder's get_config() function.
7743 pipe_config->port_clock = clock.dot;
7746 int intel_dotclock_calculate(int link_freq,
7747 const struct intel_link_m_n *m_n)
7750 * The calculation for the data clock is:
7751 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7752 * But we want to avoid losing precison if possible, so:
7753 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7755 * and the link clock is simpler:
7756 * link_clock = (m * link_clock) / n
7762 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7765 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7766 struct intel_crtc_config *pipe_config)
7768 struct drm_device *dev = crtc->base.dev;
7770 /* read out port_clock from the DPLL */
7771 i9xx_crtc_clock_get(crtc, pipe_config);
7774 * This value does not include pixel_multiplier.
7775 * We will check that port_clock and adjusted_mode.crtc_clock
7776 * agree once we know their relationship in the encoder's
7777 * get_config() function.
7779 pipe_config->adjusted_mode.crtc_clock =
7780 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7781 &pipe_config->fdi_m_n);
7784 /** Returns the currently programmed mode of the given pipe. */
7785 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7786 struct drm_crtc *crtc)
7788 struct drm_i915_private *dev_priv = dev->dev_private;
7789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7790 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7791 struct drm_display_mode *mode;
7792 struct intel_crtc_config pipe_config;
7793 int htot = I915_READ(HTOTAL(cpu_transcoder));
7794 int hsync = I915_READ(HSYNC(cpu_transcoder));
7795 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7796 int vsync = I915_READ(VSYNC(cpu_transcoder));
7797 enum pipe pipe = intel_crtc->pipe;
7799 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7804 * Construct a pipe_config sufficient for getting the clock info
7805 * back out of crtc_clock_get.
7807 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7808 * to use a real value here instead.
7810 pipe_config.cpu_transcoder = (enum transcoder) pipe;
7811 pipe_config.pixel_multiplier = 1;
7812 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7813 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7814 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7815 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7817 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7818 mode->hdisplay = (htot & 0xffff) + 1;
7819 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7820 mode->hsync_start = (hsync & 0xffff) + 1;
7821 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7822 mode->vdisplay = (vtot & 0xffff) + 1;
7823 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7824 mode->vsync_start = (vsync & 0xffff) + 1;
7825 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7827 drm_mode_set_name(mode);
7832 static void intel_increase_pllclock(struct drm_crtc *crtc)
7834 struct drm_device *dev = crtc->dev;
7835 drm_i915_private_t *dev_priv = dev->dev_private;
7836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7837 int pipe = intel_crtc->pipe;
7838 int dpll_reg = DPLL(pipe);
7841 if (HAS_PCH_SPLIT(dev))
7844 if (!dev_priv->lvds_downclock_avail)
7847 dpll = I915_READ(dpll_reg);
7848 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7849 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7851 assert_panel_unlocked(dev_priv, pipe);
7853 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7854 I915_WRITE(dpll_reg, dpll);
7855 intel_wait_for_vblank(dev, pipe);
7857 dpll = I915_READ(dpll_reg);
7858 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7859 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7863 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7865 struct drm_device *dev = crtc->dev;
7866 drm_i915_private_t *dev_priv = dev->dev_private;
7867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7869 if (HAS_PCH_SPLIT(dev))
7872 if (!dev_priv->lvds_downclock_avail)
7876 * Since this is called by a timer, we should never get here in
7879 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7880 int pipe = intel_crtc->pipe;
7881 int dpll_reg = DPLL(pipe);
7884 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7886 assert_panel_unlocked(dev_priv, pipe);
7888 dpll = I915_READ(dpll_reg);
7889 dpll |= DISPLAY_RATE_SELECT_FPA1;
7890 I915_WRITE(dpll_reg, dpll);
7891 intel_wait_for_vblank(dev, pipe);
7892 dpll = I915_READ(dpll_reg);
7893 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7894 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7899 void intel_mark_busy(struct drm_device *dev)
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7903 hsw_package_c8_gpu_busy(dev_priv);
7904 i915_update_gfx_val(dev_priv);
7907 void intel_mark_idle(struct drm_device *dev)
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 struct drm_crtc *crtc;
7912 hsw_package_c8_gpu_idle(dev_priv);
7914 if (!i915_powersave)
7917 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7921 intel_decrease_pllclock(crtc);
7924 if (dev_priv->info->gen >= 6)
7925 gen6_rps_idle(dev->dev_private);
7928 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7929 struct intel_ring_buffer *ring)
7931 struct drm_device *dev = obj->base.dev;
7932 struct drm_crtc *crtc;
7934 if (!i915_powersave)
7937 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7941 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7944 intel_increase_pllclock(crtc);
7945 if (ring && intel_fbc_enabled(dev))
7946 ring->fbc_dirty = true;
7950 static void intel_crtc_destroy(struct drm_crtc *crtc)
7952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7953 struct drm_device *dev = crtc->dev;
7954 struct intel_unpin_work *work;
7955 unsigned long flags;
7957 spin_lock_irqsave(&dev->event_lock, flags);
7958 work = intel_crtc->unpin_work;
7959 intel_crtc->unpin_work = NULL;
7960 spin_unlock_irqrestore(&dev->event_lock, flags);
7963 cancel_work_sync(&work->work);
7967 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7969 drm_crtc_cleanup(crtc);
7974 static void intel_unpin_work_fn(struct work_struct *__work)
7976 struct intel_unpin_work *work =
7977 container_of(__work, struct intel_unpin_work, work);
7978 struct drm_device *dev = work->crtc->dev;
7980 mutex_lock(&dev->struct_mutex);
7981 intel_unpin_fb_obj(work->old_fb_obj);
7982 drm_gem_object_unreference(&work->pending_flip_obj->base);
7983 drm_gem_object_unreference(&work->old_fb_obj->base);
7985 intel_update_fbc(dev);
7986 mutex_unlock(&dev->struct_mutex);
7988 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7989 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7994 static void do_intel_finish_page_flip(struct drm_device *dev,
7995 struct drm_crtc *crtc)
7997 drm_i915_private_t *dev_priv = dev->dev_private;
7998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7999 struct intel_unpin_work *work;
8000 unsigned long flags;
8002 /* Ignore early vblank irqs */
8003 if (intel_crtc == NULL)
8006 spin_lock_irqsave(&dev->event_lock, flags);
8007 work = intel_crtc->unpin_work;
8009 /* Ensure we don't miss a work->pending update ... */
8012 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8013 spin_unlock_irqrestore(&dev->event_lock, flags);
8017 /* and that the unpin work is consistent wrt ->pending. */
8020 intel_crtc->unpin_work = NULL;
8023 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8025 drm_vblank_put(dev, intel_crtc->pipe);
8027 spin_unlock_irqrestore(&dev->event_lock, flags);
8029 wake_up_all(&dev_priv->pending_flip_queue);
8031 queue_work(dev_priv->wq, &work->work);
8033 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8036 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8038 drm_i915_private_t *dev_priv = dev->dev_private;
8039 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8041 do_intel_finish_page_flip(dev, crtc);
8044 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8046 drm_i915_private_t *dev_priv = dev->dev_private;
8047 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8049 do_intel_finish_page_flip(dev, crtc);
8052 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8054 drm_i915_private_t *dev_priv = dev->dev_private;
8055 struct intel_crtc *intel_crtc =
8056 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8057 unsigned long flags;
8059 /* NB: An MMIO update of the plane base pointer will also
8060 * generate a page-flip completion irq, i.e. every modeset
8061 * is also accompanied by a spurious intel_prepare_page_flip().
8063 spin_lock_irqsave(&dev->event_lock, flags);
8064 if (intel_crtc->unpin_work)
8065 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8066 spin_unlock_irqrestore(&dev->event_lock, flags);
8069 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8071 /* Ensure that the work item is consistent when activating it ... */
8073 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8074 /* and that it is marked active as soon as the irq could fire. */
8078 static int intel_gen2_queue_flip(struct drm_device *dev,
8079 struct drm_crtc *crtc,
8080 struct drm_framebuffer *fb,
8081 struct drm_i915_gem_object *obj,
8084 struct drm_i915_private *dev_priv = dev->dev_private;
8085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8087 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8090 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8094 ret = intel_ring_begin(ring, 6);
8098 /* Can't queue multiple flips, so wait for the previous
8099 * one to finish before executing the next.
8101 if (intel_crtc->plane)
8102 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8104 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8105 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8106 intel_ring_emit(ring, MI_NOOP);
8107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8109 intel_ring_emit(ring, fb->pitches[0]);
8110 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8111 intel_ring_emit(ring, 0); /* aux display base address, unused */
8113 intel_mark_page_flip_active(intel_crtc);
8114 __intel_ring_advance(ring);
8118 intel_unpin_fb_obj(obj);
8123 static int intel_gen3_queue_flip(struct drm_device *dev,
8124 struct drm_crtc *crtc,
8125 struct drm_framebuffer *fb,
8126 struct drm_i915_gem_object *obj,
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8132 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8135 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8139 ret = intel_ring_begin(ring, 6);
8143 if (intel_crtc->plane)
8144 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8146 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8147 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8148 intel_ring_emit(ring, MI_NOOP);
8149 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8151 intel_ring_emit(ring, fb->pitches[0]);
8152 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8153 intel_ring_emit(ring, MI_NOOP);
8155 intel_mark_page_flip_active(intel_crtc);
8156 __intel_ring_advance(ring);
8160 intel_unpin_fb_obj(obj);
8165 static int intel_gen4_queue_flip(struct drm_device *dev,
8166 struct drm_crtc *crtc,
8167 struct drm_framebuffer *fb,
8168 struct drm_i915_gem_object *obj,
8171 struct drm_i915_private *dev_priv = dev->dev_private;
8172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8173 uint32_t pf, pipesrc;
8174 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8177 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8181 ret = intel_ring_begin(ring, 4);
8185 /* i965+ uses the linear or tiled offsets from the
8186 * Display Registers (which do not change across a page-flip)
8187 * so we need only reprogram the base address.
8189 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8190 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8191 intel_ring_emit(ring, fb->pitches[0]);
8192 intel_ring_emit(ring,
8193 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8196 /* XXX Enabling the panel-fitter across page-flip is so far
8197 * untested on non-native modes, so ignore it for now.
8198 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8201 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8202 intel_ring_emit(ring, pf | pipesrc);
8204 intel_mark_page_flip_active(intel_crtc);
8205 __intel_ring_advance(ring);
8209 intel_unpin_fb_obj(obj);
8214 static int intel_gen6_queue_flip(struct drm_device *dev,
8215 struct drm_crtc *crtc,
8216 struct drm_framebuffer *fb,
8217 struct drm_i915_gem_object *obj,
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8222 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8223 uint32_t pf, pipesrc;
8226 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8230 ret = intel_ring_begin(ring, 4);
8234 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8235 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8236 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8237 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8239 /* Contrary to the suggestions in the documentation,
8240 * "Enable Panel Fitter" does not seem to be required when page
8241 * flipping with a non-native mode, and worse causes a normal
8243 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8246 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8247 intel_ring_emit(ring, pf | pipesrc);
8249 intel_mark_page_flip_active(intel_crtc);
8250 __intel_ring_advance(ring);
8254 intel_unpin_fb_obj(obj);
8259 static int intel_gen7_queue_flip(struct drm_device *dev,
8260 struct drm_crtc *crtc,
8261 struct drm_framebuffer *fb,
8262 struct drm_i915_gem_object *obj,
8265 struct drm_i915_private *dev_priv = dev->dev_private;
8266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8267 struct intel_ring_buffer *ring;
8268 uint32_t plane_bit = 0;
8272 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8273 ring = &dev_priv->ring[BCS];
8275 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8279 switch(intel_crtc->plane) {
8281 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8284 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8287 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8290 WARN_ONCE(1, "unknown plane in flip command\n");
8296 if (ring->id == RCS)
8299 ret = intel_ring_begin(ring, len);
8303 /* Unmask the flip-done completion message. Note that the bspec says that
8304 * we should do this for both the BCS and RCS, and that we must not unmask
8305 * more than one flip event at any time (or ensure that one flip message
8306 * can be sent by waiting for flip-done prior to queueing new flips).
8307 * Experimentation says that BCS works despite DERRMR masking all
8308 * flip-done completion events and that unmasking all planes at once
8309 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8310 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8312 if (ring->id == RCS) {
8313 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8314 intel_ring_emit(ring, DERRMR);
8315 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8316 DERRMR_PIPEB_PRI_FLIP_DONE |
8317 DERRMR_PIPEC_PRI_FLIP_DONE));
8318 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8319 intel_ring_emit(ring, DERRMR);
8320 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8323 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8324 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8325 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8326 intel_ring_emit(ring, (MI_NOOP));
8328 intel_mark_page_flip_active(intel_crtc);
8329 __intel_ring_advance(ring);
8333 intel_unpin_fb_obj(obj);
8338 static int intel_default_queue_flip(struct drm_device *dev,
8339 struct drm_crtc *crtc,
8340 struct drm_framebuffer *fb,
8341 struct drm_i915_gem_object *obj,
8347 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8348 struct drm_framebuffer *fb,
8349 struct drm_pending_vblank_event *event,
8350 uint32_t page_flip_flags)
8352 struct drm_device *dev = crtc->dev;
8353 struct drm_i915_private *dev_priv = dev->dev_private;
8354 struct drm_framebuffer *old_fb = crtc->fb;
8355 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8357 struct intel_unpin_work *work;
8358 unsigned long flags;
8361 /* Can't change pixel format via MI display flips. */
8362 if (fb->pixel_format != crtc->fb->pixel_format)
8366 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8367 * Note that pitch changes could also affect these register.
8369 if (INTEL_INFO(dev)->gen > 3 &&
8370 (fb->offsets[0] != crtc->fb->offsets[0] ||
8371 fb->pitches[0] != crtc->fb->pitches[0]))
8374 work = kzalloc(sizeof(*work), GFP_KERNEL);
8378 work->event = event;
8380 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8381 INIT_WORK(&work->work, intel_unpin_work_fn);
8383 ret = drm_vblank_get(dev, intel_crtc->pipe);
8387 /* We borrow the event spin lock for protecting unpin_work */
8388 spin_lock_irqsave(&dev->event_lock, flags);
8389 if (intel_crtc->unpin_work) {
8390 spin_unlock_irqrestore(&dev->event_lock, flags);
8392 drm_vblank_put(dev, intel_crtc->pipe);
8394 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8397 intel_crtc->unpin_work = work;
8398 spin_unlock_irqrestore(&dev->event_lock, flags);
8400 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8401 flush_workqueue(dev_priv->wq);
8403 ret = i915_mutex_lock_interruptible(dev);
8407 /* Reference the objects for the scheduled work. */
8408 drm_gem_object_reference(&work->old_fb_obj->base);
8409 drm_gem_object_reference(&obj->base);
8413 work->pending_flip_obj = obj;
8415 work->enable_stall_check = true;
8417 atomic_inc(&intel_crtc->unpin_work_count);
8418 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8420 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8422 goto cleanup_pending;
8424 intel_disable_fbc(dev);
8425 intel_mark_fb_busy(obj, NULL);
8426 mutex_unlock(&dev->struct_mutex);
8428 trace_i915_flip_request(intel_crtc->plane, obj);
8433 atomic_dec(&intel_crtc->unpin_work_count);
8435 drm_gem_object_unreference(&work->old_fb_obj->base);
8436 drm_gem_object_unreference(&obj->base);
8437 mutex_unlock(&dev->struct_mutex);
8440 spin_lock_irqsave(&dev->event_lock, flags);
8441 intel_crtc->unpin_work = NULL;
8442 spin_unlock_irqrestore(&dev->event_lock, flags);
8444 drm_vblank_put(dev, intel_crtc->pipe);
8451 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8452 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8453 .load_lut = intel_crtc_load_lut,
8456 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8457 struct drm_crtc *crtc)
8459 struct drm_device *dev;
8460 struct drm_crtc *tmp;
8463 WARN(!crtc, "checking null crtc?\n");
8467 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8473 if (encoder->possible_crtcs & crtc_mask)
8479 * intel_modeset_update_staged_output_state
8481 * Updates the staged output configuration state, e.g. after we've read out the
8484 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8486 struct intel_encoder *encoder;
8487 struct intel_connector *connector;
8489 list_for_each_entry(connector, &dev->mode_config.connector_list,
8491 connector->new_encoder =
8492 to_intel_encoder(connector->base.encoder);
8495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8498 to_intel_crtc(encoder->base.crtc);
8503 * intel_modeset_commit_output_state
8505 * This function copies the stage display pipe configuration to the real one.
8507 static void intel_modeset_commit_output_state(struct drm_device *dev)
8509 struct intel_encoder *encoder;
8510 struct intel_connector *connector;
8512 list_for_each_entry(connector, &dev->mode_config.connector_list,
8514 connector->base.encoder = &connector->new_encoder->base;
8517 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8519 encoder->base.crtc = &encoder->new_crtc->base;
8524 connected_sink_compute_bpp(struct intel_connector * connector,
8525 struct intel_crtc_config *pipe_config)
8527 int bpp = pipe_config->pipe_bpp;
8529 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8530 connector->base.base.id,
8531 drm_get_connector_name(&connector->base));
8533 /* Don't use an invalid EDID bpc value */
8534 if (connector->base.display_info.bpc &&
8535 connector->base.display_info.bpc * 3 < bpp) {
8536 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8537 bpp, connector->base.display_info.bpc*3);
8538 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8541 /* Clamp bpp to 8 on screens without EDID 1.4 */
8542 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8543 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8545 pipe_config->pipe_bpp = 24;
8550 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8551 struct drm_framebuffer *fb,
8552 struct intel_crtc_config *pipe_config)
8554 struct drm_device *dev = crtc->base.dev;
8555 struct intel_connector *connector;
8558 switch (fb->pixel_format) {
8560 bpp = 8*3; /* since we go through a colormap */
8562 case DRM_FORMAT_XRGB1555:
8563 case DRM_FORMAT_ARGB1555:
8564 /* checked in intel_framebuffer_init already */
8565 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8567 case DRM_FORMAT_RGB565:
8568 bpp = 6*3; /* min is 18bpp */
8570 case DRM_FORMAT_XBGR8888:
8571 case DRM_FORMAT_ABGR8888:
8572 /* checked in intel_framebuffer_init already */
8573 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8575 case DRM_FORMAT_XRGB8888:
8576 case DRM_FORMAT_ARGB8888:
8579 case DRM_FORMAT_XRGB2101010:
8580 case DRM_FORMAT_ARGB2101010:
8581 case DRM_FORMAT_XBGR2101010:
8582 case DRM_FORMAT_ABGR2101010:
8583 /* checked in intel_framebuffer_init already */
8584 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8588 /* TODO: gen4+ supports 16 bpc floating point, too. */
8590 DRM_DEBUG_KMS("unsupported depth\n");
8594 pipe_config->pipe_bpp = bpp;
8596 /* Clamp display bpp to EDID value */
8597 list_for_each_entry(connector, &dev->mode_config.connector_list,
8599 if (!connector->new_encoder ||
8600 connector->new_encoder->new_crtc != crtc)
8603 connected_sink_compute_bpp(connector, pipe_config);
8609 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8611 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8612 "type: 0x%x flags: 0x%x\n",
8614 mode->crtc_hdisplay, mode->crtc_hsync_start,
8615 mode->crtc_hsync_end, mode->crtc_htotal,
8616 mode->crtc_vdisplay, mode->crtc_vsync_start,
8617 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8620 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8621 struct intel_crtc_config *pipe_config,
8622 const char *context)
8624 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8625 context, pipe_name(crtc->pipe));
8627 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8628 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8629 pipe_config->pipe_bpp, pipe_config->dither);
8630 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8631 pipe_config->has_pch_encoder,
8632 pipe_config->fdi_lanes,
8633 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8634 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8635 pipe_config->fdi_m_n.tu);
8636 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8637 pipe_config->has_dp_encoder,
8638 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8639 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8640 pipe_config->dp_m_n.tu);
8641 DRM_DEBUG_KMS("requested mode:\n");
8642 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8643 DRM_DEBUG_KMS("adjusted mode:\n");
8644 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8645 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8646 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8647 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8648 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8649 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8650 pipe_config->gmch_pfit.control,
8651 pipe_config->gmch_pfit.pgm_ratios,
8652 pipe_config->gmch_pfit.lvds_border_bits);
8653 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8654 pipe_config->pch_pfit.pos,
8655 pipe_config->pch_pfit.size,
8656 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8657 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8658 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8661 static bool check_encoder_cloning(struct drm_crtc *crtc)
8663 int num_encoders = 0;
8664 bool uncloneable_encoders = false;
8665 struct intel_encoder *encoder;
8667 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8669 if (&encoder->new_crtc->base != crtc)
8673 if (!encoder->cloneable)
8674 uncloneable_encoders = true;
8677 return !(num_encoders > 1 && uncloneable_encoders);
8680 static struct intel_crtc_config *
8681 intel_modeset_pipe_config(struct drm_crtc *crtc,
8682 struct drm_framebuffer *fb,
8683 struct drm_display_mode *mode)
8685 struct drm_device *dev = crtc->dev;
8686 struct intel_encoder *encoder;
8687 struct intel_crtc_config *pipe_config;
8688 int plane_bpp, ret = -EINVAL;
8691 if (!check_encoder_cloning(crtc)) {
8692 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8693 return ERR_PTR(-EINVAL);
8696 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8698 return ERR_PTR(-ENOMEM);
8700 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8701 drm_mode_copy(&pipe_config->requested_mode, mode);
8703 pipe_config->cpu_transcoder =
8704 (enum transcoder) to_intel_crtc(crtc)->pipe;
8705 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8708 * Sanitize sync polarity flags based on requested ones. If neither
8709 * positive or negative polarity is requested, treat this as meaning
8710 * negative polarity.
8712 if (!(pipe_config->adjusted_mode.flags &
8713 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8714 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8716 if (!(pipe_config->adjusted_mode.flags &
8717 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8718 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8720 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8721 * plane pixel format and any sink constraints into account. Returns the
8722 * source plane bpp so that dithering can be selected on mismatches
8723 * after encoders and crtc also have had their say. */
8724 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8730 * Determine the real pipe dimensions. Note that stereo modes can
8731 * increase the actual pipe size due to the frame doubling and
8732 * insertion of additional space for blanks between the frame. This
8733 * is stored in the crtc timings. We use the requested mode to do this
8734 * computation to clearly distinguish it from the adjusted mode, which
8735 * can be changed by the connectors in the below retry loop.
8737 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8738 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8739 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8742 /* Ensure the port clock defaults are reset when retrying. */
8743 pipe_config->port_clock = 0;
8744 pipe_config->pixel_multiplier = 1;
8746 /* Fill in default crtc timings, allow encoders to overwrite them. */
8747 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8749 /* Pass our mode to the connectors and the CRTC to give them a chance to
8750 * adjust it according to limitations or connector properties, and also
8751 * a chance to reject the mode entirely.
8753 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8756 if (&encoder->new_crtc->base != crtc)
8759 if (!(encoder->compute_config(encoder, pipe_config))) {
8760 DRM_DEBUG_KMS("Encoder config failure\n");
8765 /* Set default port clock if not overwritten by the encoder. Needs to be
8766 * done afterwards in case the encoder adjusts the mode. */
8767 if (!pipe_config->port_clock)
8768 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8769 * pipe_config->pixel_multiplier;
8771 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8773 DRM_DEBUG_KMS("CRTC fixup failed\n");
8778 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8783 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8788 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8789 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8790 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8795 return ERR_PTR(ret);
8798 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8799 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8801 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8802 unsigned *prepare_pipes, unsigned *disable_pipes)
8804 struct intel_crtc *intel_crtc;
8805 struct drm_device *dev = crtc->dev;
8806 struct intel_encoder *encoder;
8807 struct intel_connector *connector;
8808 struct drm_crtc *tmp_crtc;
8810 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8812 /* Check which crtcs have changed outputs connected to them, these need
8813 * to be part of the prepare_pipes mask. We don't (yet) support global
8814 * modeset across multiple crtcs, so modeset_pipes will only have one
8815 * bit set at most. */
8816 list_for_each_entry(connector, &dev->mode_config.connector_list,
8818 if (connector->base.encoder == &connector->new_encoder->base)
8821 if (connector->base.encoder) {
8822 tmp_crtc = connector->base.encoder->crtc;
8824 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8827 if (connector->new_encoder)
8829 1 << connector->new_encoder->new_crtc->pipe;
8832 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8834 if (encoder->base.crtc == &encoder->new_crtc->base)
8837 if (encoder->base.crtc) {
8838 tmp_crtc = encoder->base.crtc;
8840 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8843 if (encoder->new_crtc)
8844 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8847 /* Check for any pipes that will be fully disabled ... */
8848 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8852 /* Don't try to disable disabled crtcs. */
8853 if (!intel_crtc->base.enabled)
8856 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8858 if (encoder->new_crtc == intel_crtc)
8863 *disable_pipes |= 1 << intel_crtc->pipe;
8867 /* set_mode is also used to update properties on life display pipes. */
8868 intel_crtc = to_intel_crtc(crtc);
8870 *prepare_pipes |= 1 << intel_crtc->pipe;
8873 * For simplicity do a full modeset on any pipe where the output routing
8874 * changed. We could be more clever, but that would require us to be
8875 * more careful with calling the relevant encoder->mode_set functions.
8878 *modeset_pipes = *prepare_pipes;
8880 /* ... and mask these out. */
8881 *modeset_pipes &= ~(*disable_pipes);
8882 *prepare_pipes &= ~(*disable_pipes);
8885 * HACK: We don't (yet) fully support global modesets. intel_set_config
8886 * obies this rule, but the modeset restore mode of
8887 * intel_modeset_setup_hw_state does not.
8889 *modeset_pipes &= 1 << intel_crtc->pipe;
8890 *prepare_pipes &= 1 << intel_crtc->pipe;
8892 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8893 *modeset_pipes, *prepare_pipes, *disable_pipes);
8896 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8898 struct drm_encoder *encoder;
8899 struct drm_device *dev = crtc->dev;
8901 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8902 if (encoder->crtc == crtc)
8909 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8911 struct intel_encoder *intel_encoder;
8912 struct intel_crtc *intel_crtc;
8913 struct drm_connector *connector;
8915 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8917 if (!intel_encoder->base.crtc)
8920 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8922 if (prepare_pipes & (1 << intel_crtc->pipe))
8923 intel_encoder->connectors_active = false;
8926 intel_modeset_commit_output_state(dev);
8928 /* Update computed state. */
8929 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8931 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8934 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8935 if (!connector->encoder || !connector->encoder->crtc)
8938 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8940 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8941 struct drm_property *dpms_property =
8942 dev->mode_config.dpms_property;
8944 connector->dpms = DRM_MODE_DPMS_ON;
8945 drm_object_property_set_value(&connector->base,
8949 intel_encoder = to_intel_encoder(connector->encoder);
8950 intel_encoder->connectors_active = true;
8956 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8960 if (clock1 == clock2)
8963 if (!clock1 || !clock2)
8966 diff = abs(clock1 - clock2);
8968 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8974 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8975 list_for_each_entry((intel_crtc), \
8976 &(dev)->mode_config.crtc_list, \
8978 if (mask & (1 <<(intel_crtc)->pipe))
8981 intel_pipe_config_compare(struct drm_device *dev,
8982 struct intel_crtc_config *current_config,
8983 struct intel_crtc_config *pipe_config)
8985 #define PIPE_CONF_CHECK_X(name) \
8986 if (current_config->name != pipe_config->name) { \
8987 DRM_ERROR("mismatch in " #name " " \
8988 "(expected 0x%08x, found 0x%08x)\n", \
8989 current_config->name, \
8990 pipe_config->name); \
8994 #define PIPE_CONF_CHECK_I(name) \
8995 if (current_config->name != pipe_config->name) { \
8996 DRM_ERROR("mismatch in " #name " " \
8997 "(expected %i, found %i)\n", \
8998 current_config->name, \
8999 pipe_config->name); \
9003 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9004 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9005 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9006 "(expected %i, found %i)\n", \
9007 current_config->name & (mask), \
9008 pipe_config->name & (mask)); \
9012 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9013 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9014 DRM_ERROR("mismatch in " #name " " \
9015 "(expected %i, found %i)\n", \
9016 current_config->name, \
9017 pipe_config->name); \
9021 #define PIPE_CONF_QUIRK(quirk) \
9022 ((current_config->quirks | pipe_config->quirks) & (quirk))
9024 PIPE_CONF_CHECK_I(cpu_transcoder);
9026 PIPE_CONF_CHECK_I(has_pch_encoder);
9027 PIPE_CONF_CHECK_I(fdi_lanes);
9028 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9029 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9030 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9031 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9032 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9034 PIPE_CONF_CHECK_I(has_dp_encoder);
9035 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9036 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9037 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9038 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9039 PIPE_CONF_CHECK_I(dp_m_n.tu);
9041 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9042 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9043 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9044 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9045 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9046 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9048 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9049 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9050 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9052 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9055 PIPE_CONF_CHECK_I(pixel_multiplier);
9057 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9058 DRM_MODE_FLAG_INTERLACE);
9060 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9061 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9062 DRM_MODE_FLAG_PHSYNC);
9063 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9064 DRM_MODE_FLAG_NHSYNC);
9065 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9066 DRM_MODE_FLAG_PVSYNC);
9067 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9068 DRM_MODE_FLAG_NVSYNC);
9071 PIPE_CONF_CHECK_I(pipe_src_w);
9072 PIPE_CONF_CHECK_I(pipe_src_h);
9074 PIPE_CONF_CHECK_I(gmch_pfit.control);
9075 /* pfit ratios are autocomputed by the hw on gen4+ */
9076 if (INTEL_INFO(dev)->gen < 4)
9077 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9078 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9079 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9080 if (current_config->pch_pfit.enabled) {
9081 PIPE_CONF_CHECK_I(pch_pfit.pos);
9082 PIPE_CONF_CHECK_I(pch_pfit.size);
9085 PIPE_CONF_CHECK_I(ips_enabled);
9087 PIPE_CONF_CHECK_I(double_wide);
9089 PIPE_CONF_CHECK_I(shared_dpll);
9090 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9091 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9092 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9093 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9095 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9096 PIPE_CONF_CHECK_I(pipe_bpp);
9098 if (!IS_HASWELL(dev)) {
9099 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9100 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9103 #undef PIPE_CONF_CHECK_X
9104 #undef PIPE_CONF_CHECK_I
9105 #undef PIPE_CONF_CHECK_FLAGS
9106 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9107 #undef PIPE_CONF_QUIRK
9113 check_connector_state(struct drm_device *dev)
9115 struct intel_connector *connector;
9117 list_for_each_entry(connector, &dev->mode_config.connector_list,
9119 /* This also checks the encoder/connector hw state with the
9120 * ->get_hw_state callbacks. */
9121 intel_connector_check_state(connector);
9123 WARN(&connector->new_encoder->base != connector->base.encoder,
9124 "connector's staged encoder doesn't match current encoder\n");
9129 check_encoder_state(struct drm_device *dev)
9131 struct intel_encoder *encoder;
9132 struct intel_connector *connector;
9134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9136 bool enabled = false;
9137 bool active = false;
9138 enum pipe pipe, tracked_pipe;
9140 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9141 encoder->base.base.id,
9142 drm_get_encoder_name(&encoder->base));
9144 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9145 "encoder's stage crtc doesn't match current crtc\n");
9146 WARN(encoder->connectors_active && !encoder->base.crtc,
9147 "encoder's active_connectors set, but no crtc\n");
9149 list_for_each_entry(connector, &dev->mode_config.connector_list,
9151 if (connector->base.encoder != &encoder->base)
9154 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9157 WARN(!!encoder->base.crtc != enabled,
9158 "encoder's enabled state mismatch "
9159 "(expected %i, found %i)\n",
9160 !!encoder->base.crtc, enabled);
9161 WARN(active && !encoder->base.crtc,
9162 "active encoder with no crtc\n");
9164 WARN(encoder->connectors_active != active,
9165 "encoder's computed active state doesn't match tracked active state "
9166 "(expected %i, found %i)\n", active, encoder->connectors_active);
9168 active = encoder->get_hw_state(encoder, &pipe);
9169 WARN(active != encoder->connectors_active,
9170 "encoder's hw state doesn't match sw tracking "
9171 "(expected %i, found %i)\n",
9172 encoder->connectors_active, active);
9174 if (!encoder->base.crtc)
9177 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9178 WARN(active && pipe != tracked_pipe,
9179 "active encoder's pipe doesn't match"
9180 "(expected %i, found %i)\n",
9181 tracked_pipe, pipe);
9187 check_crtc_state(struct drm_device *dev)
9189 drm_i915_private_t *dev_priv = dev->dev_private;
9190 struct intel_crtc *crtc;
9191 struct intel_encoder *encoder;
9192 struct intel_crtc_config pipe_config;
9194 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9196 bool enabled = false;
9197 bool active = false;
9199 memset(&pipe_config, 0, sizeof(pipe_config));
9201 DRM_DEBUG_KMS("[CRTC:%d]\n",
9202 crtc->base.base.id);
9204 WARN(crtc->active && !crtc->base.enabled,
9205 "active crtc, but not enabled in sw tracking\n");
9207 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9209 if (encoder->base.crtc != &crtc->base)
9212 if (encoder->connectors_active)
9216 WARN(active != crtc->active,
9217 "crtc's computed active state doesn't match tracked active state "
9218 "(expected %i, found %i)\n", active, crtc->active);
9219 WARN(enabled != crtc->base.enabled,
9220 "crtc's computed enabled state doesn't match tracked enabled state "
9221 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9223 active = dev_priv->display.get_pipe_config(crtc,
9226 /* hw state is inconsistent with the pipe A quirk */
9227 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9228 active = crtc->active;
9230 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9233 if (encoder->base.crtc != &crtc->base)
9235 if (encoder->get_config &&
9236 encoder->get_hw_state(encoder, &pipe))
9237 encoder->get_config(encoder, &pipe_config);
9240 WARN(crtc->active != active,
9241 "crtc active state doesn't match with hw state "
9242 "(expected %i, found %i)\n", crtc->active, active);
9245 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9246 WARN(1, "pipe state doesn't match!\n");
9247 intel_dump_pipe_config(crtc, &pipe_config,
9249 intel_dump_pipe_config(crtc, &crtc->config,
9256 check_shared_dpll_state(struct drm_device *dev)
9258 drm_i915_private_t *dev_priv = dev->dev_private;
9259 struct intel_crtc *crtc;
9260 struct intel_dpll_hw_state dpll_hw_state;
9263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9264 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9265 int enabled_crtcs = 0, active_crtcs = 0;
9268 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9270 DRM_DEBUG_KMS("%s\n", pll->name);
9272 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9274 WARN(pll->active > pll->refcount,
9275 "more active pll users than references: %i vs %i\n",
9276 pll->active, pll->refcount);
9277 WARN(pll->active && !pll->on,
9278 "pll in active use but not on in sw tracking\n");
9279 WARN(pll->on && !pll->active,
9280 "pll in on but not on in use in sw tracking\n");
9281 WARN(pll->on != active,
9282 "pll on state mismatch (expected %i, found %i)\n",
9285 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9287 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9289 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9292 WARN(pll->active != active_crtcs,
9293 "pll active crtcs mismatch (expected %i, found %i)\n",
9294 pll->active, active_crtcs);
9295 WARN(pll->refcount != enabled_crtcs,
9296 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9297 pll->refcount, enabled_crtcs);
9299 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9300 sizeof(dpll_hw_state)),
9301 "pll hw state mismatch\n");
9306 intel_modeset_check_state(struct drm_device *dev)
9308 check_connector_state(dev);
9309 check_encoder_state(dev);
9310 check_crtc_state(dev);
9311 check_shared_dpll_state(dev);
9314 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9318 * FDI already provided one idea for the dotclock.
9319 * Yell if the encoder disagrees.
9321 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9322 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9323 pipe_config->adjusted_mode.crtc_clock, dotclock);
9326 static int __intel_set_mode(struct drm_crtc *crtc,
9327 struct drm_display_mode *mode,
9328 int x, int y, struct drm_framebuffer *fb)
9330 struct drm_device *dev = crtc->dev;
9331 drm_i915_private_t *dev_priv = dev->dev_private;
9332 struct drm_display_mode *saved_mode, *saved_hwmode;
9333 struct intel_crtc_config *pipe_config = NULL;
9334 struct intel_crtc *intel_crtc;
9335 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9338 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9341 saved_hwmode = saved_mode + 1;
9343 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9344 &prepare_pipes, &disable_pipes);
9346 *saved_hwmode = crtc->hwmode;
9347 *saved_mode = crtc->mode;
9349 /* Hack: Because we don't (yet) support global modeset on multiple
9350 * crtcs, we don't keep track of the new mode for more than one crtc.
9351 * Hence simply check whether any bit is set in modeset_pipes in all the
9352 * pieces of code that are not yet converted to deal with mutliple crtcs
9353 * changing their mode at the same time. */
9354 if (modeset_pipes) {
9355 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9356 if (IS_ERR(pipe_config)) {
9357 ret = PTR_ERR(pipe_config);
9362 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9366 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9367 intel_crtc_disable(&intel_crtc->base);
9369 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9370 if (intel_crtc->base.enabled)
9371 dev_priv->display.crtc_disable(&intel_crtc->base);
9374 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9375 * to set it here already despite that we pass it down the callchain.
9377 if (modeset_pipes) {
9379 /* mode_set/enable/disable functions rely on a correct pipe
9381 to_intel_crtc(crtc)->config = *pipe_config;
9384 /* Only after disabling all output pipelines that will be changed can we
9385 * update the the output configuration. */
9386 intel_modeset_update_state(dev, prepare_pipes);
9388 if (dev_priv->display.modeset_global_resources)
9389 dev_priv->display.modeset_global_resources(dev);
9391 /* Set up the DPLL and any encoders state that needs to adjust or depend
9394 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9395 ret = intel_crtc_mode_set(&intel_crtc->base,
9401 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9402 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9403 dev_priv->display.crtc_enable(&intel_crtc->base);
9405 if (modeset_pipes) {
9406 /* Store real post-adjustment hardware mode. */
9407 crtc->hwmode = pipe_config->adjusted_mode;
9409 /* Calculate and store various constants which
9410 * are later needed by vblank and swap-completion
9411 * timestamping. They are derived from true hwmode.
9413 drm_calc_timestamping_constants(crtc);
9416 /* FIXME: add subpixel order */
9418 if (ret && crtc->enabled) {
9419 crtc->hwmode = *saved_hwmode;
9420 crtc->mode = *saved_mode;
9429 static int intel_set_mode(struct drm_crtc *crtc,
9430 struct drm_display_mode *mode,
9431 int x, int y, struct drm_framebuffer *fb)
9435 ret = __intel_set_mode(crtc, mode, x, y, fb);
9438 intel_modeset_check_state(crtc->dev);
9443 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9445 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9448 #undef for_each_intel_crtc_masked
9450 static void intel_set_config_free(struct intel_set_config *config)
9455 kfree(config->save_connector_encoders);
9456 kfree(config->save_encoder_crtcs);
9460 static int intel_set_config_save_state(struct drm_device *dev,
9461 struct intel_set_config *config)
9463 struct drm_encoder *encoder;
9464 struct drm_connector *connector;
9467 config->save_encoder_crtcs =
9468 kcalloc(dev->mode_config.num_encoder,
9469 sizeof(struct drm_crtc *), GFP_KERNEL);
9470 if (!config->save_encoder_crtcs)
9473 config->save_connector_encoders =
9474 kcalloc(dev->mode_config.num_connector,
9475 sizeof(struct drm_encoder *), GFP_KERNEL);
9476 if (!config->save_connector_encoders)
9479 /* Copy data. Note that driver private data is not affected.
9480 * Should anything bad happen only the expected state is
9481 * restored, not the drivers personal bookkeeping.
9484 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9485 config->save_encoder_crtcs[count++] = encoder->crtc;
9489 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9490 config->save_connector_encoders[count++] = connector->encoder;
9496 static void intel_set_config_restore_state(struct drm_device *dev,
9497 struct intel_set_config *config)
9499 struct intel_encoder *encoder;
9500 struct intel_connector *connector;
9504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9506 to_intel_crtc(config->save_encoder_crtcs[count++]);
9510 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9511 connector->new_encoder =
9512 to_intel_encoder(config->save_connector_encoders[count++]);
9517 is_crtc_connector_off(struct drm_mode_set *set)
9521 if (set->num_connectors == 0)
9524 if (WARN_ON(set->connectors == NULL))
9527 for (i = 0; i < set->num_connectors; i++)
9528 if (set->connectors[i]->encoder &&
9529 set->connectors[i]->encoder->crtc == set->crtc &&
9530 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9537 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9538 struct intel_set_config *config)
9541 /* We should be able to check here if the fb has the same properties
9542 * and then just flip_or_move it */
9543 if (is_crtc_connector_off(set)) {
9544 config->mode_changed = true;
9545 } else if (set->crtc->fb != set->fb) {
9546 /* If we have no fb then treat it as a full mode set */
9547 if (set->crtc->fb == NULL) {
9548 struct intel_crtc *intel_crtc =
9549 to_intel_crtc(set->crtc);
9551 if (intel_crtc->active && i915_fastboot) {
9552 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9553 config->fb_changed = true;
9555 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9556 config->mode_changed = true;
9558 } else if (set->fb == NULL) {
9559 config->mode_changed = true;
9560 } else if (set->fb->pixel_format !=
9561 set->crtc->fb->pixel_format) {
9562 config->mode_changed = true;
9564 config->fb_changed = true;
9568 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9569 config->fb_changed = true;
9571 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9572 DRM_DEBUG_KMS("modes are different, full mode set\n");
9573 drm_mode_debug_printmodeline(&set->crtc->mode);
9574 drm_mode_debug_printmodeline(set->mode);
9575 config->mode_changed = true;
9578 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9579 set->crtc->base.id, config->mode_changed, config->fb_changed);
9583 intel_modeset_stage_output_state(struct drm_device *dev,
9584 struct drm_mode_set *set,
9585 struct intel_set_config *config)
9587 struct drm_crtc *new_crtc;
9588 struct intel_connector *connector;
9589 struct intel_encoder *encoder;
9592 /* The upper layers ensure that we either disable a crtc or have a list
9593 * of connectors. For paranoia, double-check this. */
9594 WARN_ON(!set->fb && (set->num_connectors != 0));
9595 WARN_ON(set->fb && (set->num_connectors == 0));
9597 list_for_each_entry(connector, &dev->mode_config.connector_list,
9599 /* Otherwise traverse passed in connector list and get encoders
9601 for (ro = 0; ro < set->num_connectors; ro++) {
9602 if (set->connectors[ro] == &connector->base) {
9603 connector->new_encoder = connector->encoder;
9608 /* If we disable the crtc, disable all its connectors. Also, if
9609 * the connector is on the changing crtc but not on the new
9610 * connector list, disable it. */
9611 if ((!set->fb || ro == set->num_connectors) &&
9612 connector->base.encoder &&
9613 connector->base.encoder->crtc == set->crtc) {
9614 connector->new_encoder = NULL;
9616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9617 connector->base.base.id,
9618 drm_get_connector_name(&connector->base));
9622 if (&connector->new_encoder->base != connector->base.encoder) {
9623 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9624 config->mode_changed = true;
9627 /* connector->new_encoder is now updated for all connectors. */
9629 /* Update crtc of enabled connectors. */
9630 list_for_each_entry(connector, &dev->mode_config.connector_list,
9632 if (!connector->new_encoder)
9635 new_crtc = connector->new_encoder->base.crtc;
9637 for (ro = 0; ro < set->num_connectors; ro++) {
9638 if (set->connectors[ro] == &connector->base)
9639 new_crtc = set->crtc;
9642 /* Make sure the new CRTC will work with the encoder */
9643 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9647 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9650 connector->base.base.id,
9651 drm_get_connector_name(&connector->base),
9655 /* Check for any encoders that needs to be disabled. */
9656 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9658 list_for_each_entry(connector,
9659 &dev->mode_config.connector_list,
9661 if (connector->new_encoder == encoder) {
9662 WARN_ON(!connector->new_encoder->new_crtc);
9667 encoder->new_crtc = NULL;
9669 /* Only now check for crtc changes so we don't miss encoders
9670 * that will be disabled. */
9671 if (&encoder->new_crtc->base != encoder->base.crtc) {
9672 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9673 config->mode_changed = true;
9676 /* Now we've also updated encoder->new_crtc for all encoders. */
9681 static int intel_crtc_set_config(struct drm_mode_set *set)
9683 struct drm_device *dev;
9684 struct drm_mode_set save_set;
9685 struct intel_set_config *config;
9690 BUG_ON(!set->crtc->helper_private);
9692 /* Enforce sane interface api - has been abused by the fb helper. */
9693 BUG_ON(!set->mode && set->fb);
9694 BUG_ON(set->fb && set->num_connectors == 0);
9697 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9698 set->crtc->base.id, set->fb->base.id,
9699 (int)set->num_connectors, set->x, set->y);
9701 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9704 dev = set->crtc->dev;
9707 config = kzalloc(sizeof(*config), GFP_KERNEL);
9711 ret = intel_set_config_save_state(dev, config);
9715 save_set.crtc = set->crtc;
9716 save_set.mode = &set->crtc->mode;
9717 save_set.x = set->crtc->x;
9718 save_set.y = set->crtc->y;
9719 save_set.fb = set->crtc->fb;
9721 /* Compute whether we need a full modeset, only an fb base update or no
9722 * change at all. In the future we might also check whether only the
9723 * mode changed, e.g. for LVDS where we only change the panel fitter in
9725 intel_set_config_compute_mode_changes(set, config);
9727 ret = intel_modeset_stage_output_state(dev, set, config);
9731 if (config->mode_changed) {
9732 ret = intel_set_mode(set->crtc, set->mode,
9733 set->x, set->y, set->fb);
9734 } else if (config->fb_changed) {
9735 intel_crtc_wait_for_pending_flips(set->crtc);
9737 ret = intel_pipe_set_base(set->crtc,
9738 set->x, set->y, set->fb);
9742 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9743 set->crtc->base.id, ret);
9745 intel_set_config_restore_state(dev, config);
9747 /* Try to restore the config */
9748 if (config->mode_changed &&
9749 intel_set_mode(save_set.crtc, save_set.mode,
9750 save_set.x, save_set.y, save_set.fb))
9751 DRM_ERROR("failed to restore config after modeset failure\n");
9755 intel_set_config_free(config);
9759 static const struct drm_crtc_funcs intel_crtc_funcs = {
9760 .cursor_set = intel_crtc_cursor_set,
9761 .cursor_move = intel_crtc_cursor_move,
9762 .gamma_set = intel_crtc_gamma_set,
9763 .set_config = intel_crtc_set_config,
9764 .destroy = intel_crtc_destroy,
9765 .page_flip = intel_crtc_page_flip,
9768 static void intel_cpu_pll_init(struct drm_device *dev)
9771 intel_ddi_pll_init(dev);
9774 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9775 struct intel_shared_dpll *pll,
9776 struct intel_dpll_hw_state *hw_state)
9780 val = I915_READ(PCH_DPLL(pll->id));
9781 hw_state->dpll = val;
9782 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9783 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9785 return val & DPLL_VCO_ENABLE;
9788 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9789 struct intel_shared_dpll *pll)
9791 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9792 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9795 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9796 struct intel_shared_dpll *pll)
9798 /* PCH refclock must be enabled first */
9799 assert_pch_refclk_enabled(dev_priv);
9801 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9803 /* Wait for the clocks to stabilize. */
9804 POSTING_READ(PCH_DPLL(pll->id));
9807 /* The pixel multiplier can only be updated once the
9808 * DPLL is enabled and the clocks are stable.
9810 * So write it again.
9812 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9813 POSTING_READ(PCH_DPLL(pll->id));
9817 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9818 struct intel_shared_dpll *pll)
9820 struct drm_device *dev = dev_priv->dev;
9821 struct intel_crtc *crtc;
9823 /* Make sure no transcoder isn't still depending on us. */
9824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9825 if (intel_crtc_to_shared_dpll(crtc) == pll)
9826 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9829 I915_WRITE(PCH_DPLL(pll->id), 0);
9830 POSTING_READ(PCH_DPLL(pll->id));
9834 static char *ibx_pch_dpll_names[] = {
9839 static void ibx_pch_dpll_init(struct drm_device *dev)
9841 struct drm_i915_private *dev_priv = dev->dev_private;
9844 dev_priv->num_shared_dpll = 2;
9846 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9847 dev_priv->shared_dplls[i].id = i;
9848 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9849 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9850 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9851 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9852 dev_priv->shared_dplls[i].get_hw_state =
9853 ibx_pch_dpll_get_hw_state;
9857 static void intel_shared_dpll_init(struct drm_device *dev)
9859 struct drm_i915_private *dev_priv = dev->dev_private;
9861 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9862 ibx_pch_dpll_init(dev);
9864 dev_priv->num_shared_dpll = 0;
9866 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9867 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9868 dev_priv->num_shared_dpll);
9871 static void intel_crtc_init(struct drm_device *dev, int pipe)
9873 drm_i915_private_t *dev_priv = dev->dev_private;
9874 struct intel_crtc *intel_crtc;
9877 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9878 if (intel_crtc == NULL)
9881 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9883 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9884 for (i = 0; i < 256; i++) {
9885 intel_crtc->lut_r[i] = i;
9886 intel_crtc->lut_g[i] = i;
9887 intel_crtc->lut_b[i] = i;
9890 /* Swap pipes & planes for FBC on pre-965 */
9891 intel_crtc->pipe = pipe;
9892 intel_crtc->plane = pipe;
9893 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9894 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9895 intel_crtc->plane = !pipe;
9898 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9899 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9900 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9901 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9903 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9906 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9907 struct drm_file *file)
9909 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9910 struct drm_mode_object *drmmode_obj;
9911 struct intel_crtc *crtc;
9913 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9916 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9917 DRM_MODE_OBJECT_CRTC);
9920 DRM_ERROR("no such CRTC id\n");
9924 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9925 pipe_from_crtc_id->pipe = crtc->pipe;
9930 static int intel_encoder_clones(struct intel_encoder *encoder)
9932 struct drm_device *dev = encoder->base.dev;
9933 struct intel_encoder *source_encoder;
9937 list_for_each_entry(source_encoder,
9938 &dev->mode_config.encoder_list, base.head) {
9940 if (encoder == source_encoder)
9941 index_mask |= (1 << entry);
9943 /* Intel hw has only one MUX where enocoders could be cloned. */
9944 if (encoder->cloneable && source_encoder->cloneable)
9945 index_mask |= (1 << entry);
9953 static bool has_edp_a(struct drm_device *dev)
9955 struct drm_i915_private *dev_priv = dev->dev_private;
9957 if (!IS_MOBILE(dev))
9960 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9964 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9970 static void intel_setup_outputs(struct drm_device *dev)
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9973 struct intel_encoder *encoder;
9974 bool dpd_is_edp = false;
9976 intel_lvds_init(dev);
9979 intel_crt_init(dev);
9984 /* Haswell uses DDI functions to detect digital outputs */
9985 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9986 /* DDI A only supports eDP */
9988 intel_ddi_init(dev, PORT_A);
9990 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9992 found = I915_READ(SFUSE_STRAP);
9994 if (found & SFUSE_STRAP_DDIB_DETECTED)
9995 intel_ddi_init(dev, PORT_B);
9996 if (found & SFUSE_STRAP_DDIC_DETECTED)
9997 intel_ddi_init(dev, PORT_C);
9998 if (found & SFUSE_STRAP_DDID_DETECTED)
9999 intel_ddi_init(dev, PORT_D);
10000 } else if (HAS_PCH_SPLIT(dev)) {
10002 dpd_is_edp = intel_dpd_is_edp(dev);
10004 if (has_edp_a(dev))
10005 intel_dp_init(dev, DP_A, PORT_A);
10007 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10008 /* PCH SDVOB multiplex with HDMIB */
10009 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10011 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10012 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10013 intel_dp_init(dev, PCH_DP_B, PORT_B);
10016 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10017 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10019 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10020 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10022 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10023 intel_dp_init(dev, PCH_DP_C, PORT_C);
10025 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10026 intel_dp_init(dev, PCH_DP_D, PORT_D);
10027 } else if (IS_VALLEYVIEW(dev)) {
10028 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10029 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10031 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10032 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10035 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10036 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10038 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10039 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10043 intel_dsi_init(dev);
10044 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10045 bool found = false;
10047 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10048 DRM_DEBUG_KMS("probing SDVOB\n");
10049 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10050 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10051 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10052 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10055 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10056 intel_dp_init(dev, DP_B, PORT_B);
10059 /* Before G4X SDVOC doesn't have its own detect register */
10061 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10062 DRM_DEBUG_KMS("probing SDVOC\n");
10063 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10066 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10068 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10069 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10070 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10072 if (SUPPORTS_INTEGRATED_DP(dev))
10073 intel_dp_init(dev, DP_C, PORT_C);
10076 if (SUPPORTS_INTEGRATED_DP(dev) &&
10077 (I915_READ(DP_D) & DP_DETECTED))
10078 intel_dp_init(dev, DP_D, PORT_D);
10079 } else if (IS_GEN2(dev))
10080 intel_dvo_init(dev);
10082 if (SUPPORTS_TV(dev))
10083 intel_tv_init(dev);
10085 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10086 encoder->base.possible_crtcs = encoder->crtc_mask;
10087 encoder->base.possible_clones =
10088 intel_encoder_clones(encoder);
10091 intel_init_pch_refclk(dev);
10093 drm_helper_move_panel_connectors_to_head(dev);
10096 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10098 drm_framebuffer_cleanup(&fb->base);
10099 WARN_ON(!fb->obj->framebuffer_references--);
10100 drm_gem_object_unreference_unlocked(&fb->obj->base);
10103 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10105 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10107 intel_framebuffer_fini(intel_fb);
10111 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10112 struct drm_file *file,
10113 unsigned int *handle)
10115 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10116 struct drm_i915_gem_object *obj = intel_fb->obj;
10118 return drm_gem_handle_create(file, &obj->base, handle);
10121 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10122 .destroy = intel_user_framebuffer_destroy,
10123 .create_handle = intel_user_framebuffer_create_handle,
10126 int intel_framebuffer_init(struct drm_device *dev,
10127 struct intel_framebuffer *intel_fb,
10128 struct drm_mode_fb_cmd2 *mode_cmd,
10129 struct drm_i915_gem_object *obj)
10131 int aligned_height, tile_height;
10135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10137 if (obj->tiling_mode == I915_TILING_Y) {
10138 DRM_DEBUG("hardware does not support tiling Y\n");
10142 if (mode_cmd->pitches[0] & 63) {
10143 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10144 mode_cmd->pitches[0]);
10148 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10149 pitch_limit = 32*1024;
10150 } else if (INTEL_INFO(dev)->gen >= 4) {
10151 if (obj->tiling_mode)
10152 pitch_limit = 16*1024;
10154 pitch_limit = 32*1024;
10155 } else if (INTEL_INFO(dev)->gen >= 3) {
10156 if (obj->tiling_mode)
10157 pitch_limit = 8*1024;
10159 pitch_limit = 16*1024;
10161 /* XXX DSPC is limited to 4k tiled */
10162 pitch_limit = 8*1024;
10164 if (mode_cmd->pitches[0] > pitch_limit) {
10165 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10166 obj->tiling_mode ? "tiled" : "linear",
10167 mode_cmd->pitches[0], pitch_limit);
10171 if (obj->tiling_mode != I915_TILING_NONE &&
10172 mode_cmd->pitches[0] != obj->stride) {
10173 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10174 mode_cmd->pitches[0], obj->stride);
10178 /* Reject formats not supported by any plane early. */
10179 switch (mode_cmd->pixel_format) {
10180 case DRM_FORMAT_C8:
10181 case DRM_FORMAT_RGB565:
10182 case DRM_FORMAT_XRGB8888:
10183 case DRM_FORMAT_ARGB8888:
10185 case DRM_FORMAT_XRGB1555:
10186 case DRM_FORMAT_ARGB1555:
10187 if (INTEL_INFO(dev)->gen > 3) {
10188 DRM_DEBUG("unsupported pixel format: %s\n",
10189 drm_get_format_name(mode_cmd->pixel_format));
10193 case DRM_FORMAT_XBGR8888:
10194 case DRM_FORMAT_ABGR8888:
10195 case DRM_FORMAT_XRGB2101010:
10196 case DRM_FORMAT_ARGB2101010:
10197 case DRM_FORMAT_XBGR2101010:
10198 case DRM_FORMAT_ABGR2101010:
10199 if (INTEL_INFO(dev)->gen < 4) {
10200 DRM_DEBUG("unsupported pixel format: %s\n",
10201 drm_get_format_name(mode_cmd->pixel_format));
10205 case DRM_FORMAT_YUYV:
10206 case DRM_FORMAT_UYVY:
10207 case DRM_FORMAT_YVYU:
10208 case DRM_FORMAT_VYUY:
10209 if (INTEL_INFO(dev)->gen < 5) {
10210 DRM_DEBUG("unsupported pixel format: %s\n",
10211 drm_get_format_name(mode_cmd->pixel_format));
10216 DRM_DEBUG("unsupported pixel format: %s\n",
10217 drm_get_format_name(mode_cmd->pixel_format));
10221 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10222 if (mode_cmd->offsets[0] != 0)
10225 tile_height = IS_GEN2(dev) ? 16 : 8;
10226 aligned_height = ALIGN(mode_cmd->height,
10227 obj->tiling_mode ? tile_height : 1);
10228 /* FIXME drm helper for size checks (especially planar formats)? */
10229 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10232 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10233 intel_fb->obj = obj;
10234 intel_fb->obj->framebuffer_references++;
10236 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10238 DRM_ERROR("framebuffer init failed %d\n", ret);
10245 static struct drm_framebuffer *
10246 intel_user_framebuffer_create(struct drm_device *dev,
10247 struct drm_file *filp,
10248 struct drm_mode_fb_cmd2 *mode_cmd)
10250 struct drm_i915_gem_object *obj;
10252 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10253 mode_cmd->handles[0]));
10254 if (&obj->base == NULL)
10255 return ERR_PTR(-ENOENT);
10257 return intel_framebuffer_create(dev, mode_cmd, obj);
10260 #ifndef CONFIG_DRM_I915_FBDEV
10261 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10266 static const struct drm_mode_config_funcs intel_mode_funcs = {
10267 .fb_create = intel_user_framebuffer_create,
10268 .output_poll_changed = intel_fbdev_output_poll_changed,
10271 /* Set up chip specific display functions */
10272 static void intel_init_display(struct drm_device *dev)
10274 struct drm_i915_private *dev_priv = dev->dev_private;
10276 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10277 dev_priv->display.find_dpll = g4x_find_best_dpll;
10278 else if (IS_VALLEYVIEW(dev))
10279 dev_priv->display.find_dpll = vlv_find_best_dpll;
10280 else if (IS_PINEVIEW(dev))
10281 dev_priv->display.find_dpll = pnv_find_best_dpll;
10283 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10285 if (HAS_DDI(dev)) {
10286 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10287 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10288 dev_priv->display.crtc_enable = haswell_crtc_enable;
10289 dev_priv->display.crtc_disable = haswell_crtc_disable;
10290 dev_priv->display.off = haswell_crtc_off;
10291 dev_priv->display.update_plane = ironlake_update_plane;
10292 } else if (HAS_PCH_SPLIT(dev)) {
10293 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10294 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10295 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10296 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10297 dev_priv->display.off = ironlake_crtc_off;
10298 dev_priv->display.update_plane = ironlake_update_plane;
10299 } else if (IS_VALLEYVIEW(dev)) {
10300 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10301 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10302 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10303 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10304 dev_priv->display.off = i9xx_crtc_off;
10305 dev_priv->display.update_plane = i9xx_update_plane;
10307 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10308 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10309 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10310 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10311 dev_priv->display.off = i9xx_crtc_off;
10312 dev_priv->display.update_plane = i9xx_update_plane;
10315 /* Returns the core display clock speed */
10316 if (IS_VALLEYVIEW(dev))
10317 dev_priv->display.get_display_clock_speed =
10318 valleyview_get_display_clock_speed;
10319 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10320 dev_priv->display.get_display_clock_speed =
10321 i945_get_display_clock_speed;
10322 else if (IS_I915G(dev))
10323 dev_priv->display.get_display_clock_speed =
10324 i915_get_display_clock_speed;
10325 else if (IS_I945GM(dev) || IS_845G(dev))
10326 dev_priv->display.get_display_clock_speed =
10327 i9xx_misc_get_display_clock_speed;
10328 else if (IS_PINEVIEW(dev))
10329 dev_priv->display.get_display_clock_speed =
10330 pnv_get_display_clock_speed;
10331 else if (IS_I915GM(dev))
10332 dev_priv->display.get_display_clock_speed =
10333 i915gm_get_display_clock_speed;
10334 else if (IS_I865G(dev))
10335 dev_priv->display.get_display_clock_speed =
10336 i865_get_display_clock_speed;
10337 else if (IS_I85X(dev))
10338 dev_priv->display.get_display_clock_speed =
10339 i855_get_display_clock_speed;
10340 else /* 852, 830 */
10341 dev_priv->display.get_display_clock_speed =
10342 i830_get_display_clock_speed;
10344 if (HAS_PCH_SPLIT(dev)) {
10345 if (IS_GEN5(dev)) {
10346 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10347 dev_priv->display.write_eld = ironlake_write_eld;
10348 } else if (IS_GEN6(dev)) {
10349 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10350 dev_priv->display.write_eld = ironlake_write_eld;
10351 } else if (IS_IVYBRIDGE(dev)) {
10352 /* FIXME: detect B0+ stepping and use auto training */
10353 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10354 dev_priv->display.write_eld = ironlake_write_eld;
10355 dev_priv->display.modeset_global_resources =
10356 ivb_modeset_global_resources;
10357 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10358 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10359 dev_priv->display.write_eld = haswell_write_eld;
10360 dev_priv->display.modeset_global_resources =
10361 haswell_modeset_global_resources;
10363 } else if (IS_G4X(dev)) {
10364 dev_priv->display.write_eld = g4x_write_eld;
10367 /* Default just returns -ENODEV to indicate unsupported */
10368 dev_priv->display.queue_flip = intel_default_queue_flip;
10370 switch (INTEL_INFO(dev)->gen) {
10372 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10376 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10381 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10385 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10388 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10389 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10395 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10396 * resume, or other times. This quirk makes sure that's the case for
10397 * affected systems.
10399 static void quirk_pipea_force(struct drm_device *dev)
10401 struct drm_i915_private *dev_priv = dev->dev_private;
10403 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10404 DRM_INFO("applying pipe a force quirk\n");
10408 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10410 static void quirk_ssc_force_disable(struct drm_device *dev)
10412 struct drm_i915_private *dev_priv = dev->dev_private;
10413 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10414 DRM_INFO("applying lvds SSC disable quirk\n");
10418 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10421 static void quirk_invert_brightness(struct drm_device *dev)
10423 struct drm_i915_private *dev_priv = dev->dev_private;
10424 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10425 DRM_INFO("applying inverted panel brightness quirk\n");
10429 * Some machines (Dell XPS13) suffer broken backlight controls if
10430 * BLM_PCH_PWM_ENABLE is set.
10432 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10434 struct drm_i915_private *dev_priv = dev->dev_private;
10435 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10436 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10439 struct intel_quirk {
10441 int subsystem_vendor;
10442 int subsystem_device;
10443 void (*hook)(struct drm_device *dev);
10446 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10447 struct intel_dmi_quirk {
10448 void (*hook)(struct drm_device *dev);
10449 const struct dmi_system_id (*dmi_id_list)[];
10452 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10454 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10458 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10460 .dmi_id_list = &(const struct dmi_system_id[]) {
10462 .callback = intel_dmi_reverse_brightness,
10463 .ident = "NCR Corporation",
10464 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10465 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10468 { } /* terminating entry */
10470 .hook = quirk_invert_brightness,
10474 static struct intel_quirk intel_quirks[] = {
10475 /* HP Mini needs pipe A force quirk (LP: #322104) */
10476 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10478 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10479 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10481 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10482 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10484 /* 830 needs to leave pipe A & dpll A up */
10485 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10487 /* Lenovo U160 cannot use SSC on LVDS */
10488 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10490 /* Sony Vaio Y cannot use SSC on LVDS */
10491 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10494 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10495 * seem to use inverted backlight PWM.
10497 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10499 /* Dell XPS13 HD Sandy Bridge */
10500 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10501 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10502 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10505 static void intel_init_quirks(struct drm_device *dev)
10507 struct pci_dev *d = dev->pdev;
10510 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10511 struct intel_quirk *q = &intel_quirks[i];
10513 if (d->device == q->device &&
10514 (d->subsystem_vendor == q->subsystem_vendor ||
10515 q->subsystem_vendor == PCI_ANY_ID) &&
10516 (d->subsystem_device == q->subsystem_device ||
10517 q->subsystem_device == PCI_ANY_ID))
10520 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10521 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10522 intel_dmi_quirks[i].hook(dev);
10526 /* Disable the VGA plane that we never use */
10527 static void i915_disable_vga(struct drm_device *dev)
10529 struct drm_i915_private *dev_priv = dev->dev_private;
10531 u32 vga_reg = i915_vgacntrl_reg(dev);
10533 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10534 outb(SR01, VGA_SR_INDEX);
10535 sr1 = inb(VGA_SR_DATA);
10536 outb(sr1 | 1<<5, VGA_SR_DATA);
10537 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10540 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10541 POSTING_READ(vga_reg);
10544 void intel_modeset_init_hw(struct drm_device *dev)
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10548 intel_prepare_ddi(dev);
10550 intel_init_clock_gating(dev);
10552 /* Enable the CRI clock source so we can get at the display */
10553 if (IS_VALLEYVIEW(dev))
10554 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10555 DPLL_INTEGRATED_CRI_CLK_VLV);
10557 intel_init_dpio(dev);
10559 mutex_lock(&dev->struct_mutex);
10560 intel_enable_gt_powersave(dev);
10561 mutex_unlock(&dev->struct_mutex);
10564 void intel_modeset_suspend_hw(struct drm_device *dev)
10566 intel_suspend_hw(dev);
10569 void intel_modeset_init(struct drm_device *dev)
10571 struct drm_i915_private *dev_priv = dev->dev_private;
10574 drm_mode_config_init(dev);
10576 dev->mode_config.min_width = 0;
10577 dev->mode_config.min_height = 0;
10579 dev->mode_config.preferred_depth = 24;
10580 dev->mode_config.prefer_shadow = 1;
10582 dev->mode_config.funcs = &intel_mode_funcs;
10584 intel_init_quirks(dev);
10586 intel_init_pm(dev);
10588 if (INTEL_INFO(dev)->num_pipes == 0)
10591 intel_init_display(dev);
10593 if (IS_GEN2(dev)) {
10594 dev->mode_config.max_width = 2048;
10595 dev->mode_config.max_height = 2048;
10596 } else if (IS_GEN3(dev)) {
10597 dev->mode_config.max_width = 4096;
10598 dev->mode_config.max_height = 4096;
10600 dev->mode_config.max_width = 8192;
10601 dev->mode_config.max_height = 8192;
10603 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10605 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10606 INTEL_INFO(dev)->num_pipes,
10607 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10610 intel_crtc_init(dev, i);
10611 for (j = 0; j < dev_priv->num_plane; j++) {
10612 ret = intel_plane_init(dev, i, j);
10614 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10615 pipe_name(i), sprite_name(i, j), ret);
10619 intel_cpu_pll_init(dev);
10620 intel_shared_dpll_init(dev);
10622 /* Just disable it once at startup */
10623 i915_disable_vga(dev);
10624 intel_setup_outputs(dev);
10626 /* Just in case the BIOS is doing something questionable. */
10627 intel_disable_fbc(dev);
10631 intel_connector_break_all_links(struct intel_connector *connector)
10633 connector->base.dpms = DRM_MODE_DPMS_OFF;
10634 connector->base.encoder = NULL;
10635 connector->encoder->connectors_active = false;
10636 connector->encoder->base.crtc = NULL;
10639 static void intel_enable_pipe_a(struct drm_device *dev)
10641 struct intel_connector *connector;
10642 struct drm_connector *crt = NULL;
10643 struct intel_load_detect_pipe load_detect_temp;
10645 /* We can't just switch on the pipe A, we need to set things up with a
10646 * proper mode and output configuration. As a gross hack, enable pipe A
10647 * by enabling the load detect pipe once. */
10648 list_for_each_entry(connector,
10649 &dev->mode_config.connector_list,
10651 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10652 crt = &connector->base;
10660 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10661 intel_release_load_detect_pipe(crt, &load_detect_temp);
10667 intel_check_plane_mapping(struct intel_crtc *crtc)
10669 struct drm_device *dev = crtc->base.dev;
10670 struct drm_i915_private *dev_priv = dev->dev_private;
10673 if (INTEL_INFO(dev)->num_pipes == 1)
10676 reg = DSPCNTR(!crtc->plane);
10677 val = I915_READ(reg);
10679 if ((val & DISPLAY_PLANE_ENABLE) &&
10680 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10686 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10688 struct drm_device *dev = crtc->base.dev;
10689 struct drm_i915_private *dev_priv = dev->dev_private;
10692 /* Clear any frame start delays used for debugging left by the BIOS */
10693 reg = PIPECONF(crtc->config.cpu_transcoder);
10694 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10696 /* We need to sanitize the plane -> pipe mapping first because this will
10697 * disable the crtc (and hence change the state) if it is wrong. Note
10698 * that gen4+ has a fixed plane -> pipe mapping. */
10699 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10700 struct intel_connector *connector;
10703 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10704 crtc->base.base.id);
10706 /* Pipe has the wrong plane attached and the plane is active.
10707 * Temporarily change the plane mapping and disable everything
10709 plane = crtc->plane;
10710 crtc->plane = !plane;
10711 dev_priv->display.crtc_disable(&crtc->base);
10712 crtc->plane = plane;
10714 /* ... and break all links. */
10715 list_for_each_entry(connector, &dev->mode_config.connector_list,
10717 if (connector->encoder->base.crtc != &crtc->base)
10720 intel_connector_break_all_links(connector);
10723 WARN_ON(crtc->active);
10724 crtc->base.enabled = false;
10727 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10728 crtc->pipe == PIPE_A && !crtc->active) {
10729 /* BIOS forgot to enable pipe A, this mostly happens after
10730 * resume. Force-enable the pipe to fix this, the update_dpms
10731 * call below we restore the pipe to the right state, but leave
10732 * the required bits on. */
10733 intel_enable_pipe_a(dev);
10736 /* Adjust the state of the output pipe according to whether we
10737 * have active connectors/encoders. */
10738 intel_crtc_update_dpms(&crtc->base);
10740 if (crtc->active != crtc->base.enabled) {
10741 struct intel_encoder *encoder;
10743 /* This can happen either due to bugs in the get_hw_state
10744 * functions or because the pipe is force-enabled due to the
10746 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10747 crtc->base.base.id,
10748 crtc->base.enabled ? "enabled" : "disabled",
10749 crtc->active ? "enabled" : "disabled");
10751 crtc->base.enabled = crtc->active;
10753 /* Because we only establish the connector -> encoder ->
10754 * crtc links if something is active, this means the
10755 * crtc is now deactivated. Break the links. connector
10756 * -> encoder links are only establish when things are
10757 * actually up, hence no need to break them. */
10758 WARN_ON(crtc->active);
10760 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10761 WARN_ON(encoder->connectors_active);
10762 encoder->base.crtc = NULL;
10767 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10769 struct intel_connector *connector;
10770 struct drm_device *dev = encoder->base.dev;
10772 /* We need to check both for a crtc link (meaning that the
10773 * encoder is active and trying to read from a pipe) and the
10774 * pipe itself being active. */
10775 bool has_active_crtc = encoder->base.crtc &&
10776 to_intel_crtc(encoder->base.crtc)->active;
10778 if (encoder->connectors_active && !has_active_crtc) {
10779 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10780 encoder->base.base.id,
10781 drm_get_encoder_name(&encoder->base));
10783 /* Connector is active, but has no active pipe. This is
10784 * fallout from our resume register restoring. Disable
10785 * the encoder manually again. */
10786 if (encoder->base.crtc) {
10787 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10788 encoder->base.base.id,
10789 drm_get_encoder_name(&encoder->base));
10790 encoder->disable(encoder);
10793 /* Inconsistent output/port/pipe state happens presumably due to
10794 * a bug in one of the get_hw_state functions. Or someplace else
10795 * in our code, like the register restore mess on resume. Clamp
10796 * things to off as a safer default. */
10797 list_for_each_entry(connector,
10798 &dev->mode_config.connector_list,
10800 if (connector->encoder != encoder)
10803 intel_connector_break_all_links(connector);
10806 /* Enabled encoders without active connectors will be fixed in
10807 * the crtc fixup. */
10810 void i915_redisable_vga(struct drm_device *dev)
10812 struct drm_i915_private *dev_priv = dev->dev_private;
10813 u32 vga_reg = i915_vgacntrl_reg(dev);
10815 /* This function can be called both from intel_modeset_setup_hw_state or
10816 * at a very early point in our resume sequence, where the power well
10817 * structures are not yet restored. Since this function is at a very
10818 * paranoid "someone might have enabled VGA while we were not looking"
10819 * level, just check if the power well is enabled instead of trying to
10820 * follow the "don't touch the power well if we don't need it" policy
10821 * the rest of the driver uses. */
10822 if (HAS_POWER_WELL(dev) &&
10823 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10826 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10827 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10828 i915_disable_vga(dev);
10832 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10834 struct drm_i915_private *dev_priv = dev->dev_private;
10836 struct intel_crtc *crtc;
10837 struct intel_encoder *encoder;
10838 struct intel_connector *connector;
10841 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10843 memset(&crtc->config, 0, sizeof(crtc->config));
10845 crtc->active = dev_priv->display.get_pipe_config(crtc,
10848 crtc->base.enabled = crtc->active;
10849 crtc->primary_enabled = crtc->active;
10851 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10852 crtc->base.base.id,
10853 crtc->active ? "enabled" : "disabled");
10856 /* FIXME: Smash this into the new shared dpll infrastructure. */
10858 intel_ddi_setup_hw_pll_state(dev);
10860 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10861 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10863 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10865 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10867 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10870 pll->refcount = pll->active;
10872 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10873 pll->name, pll->refcount, pll->on);
10876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10880 if (encoder->get_hw_state(encoder, &pipe)) {
10881 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10882 encoder->base.crtc = &crtc->base;
10883 if (encoder->get_config)
10884 encoder->get_config(encoder, &crtc->config);
10886 encoder->base.crtc = NULL;
10889 encoder->connectors_active = false;
10890 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10891 encoder->base.base.id,
10892 drm_get_encoder_name(&encoder->base),
10893 encoder->base.crtc ? "enabled" : "disabled",
10897 list_for_each_entry(connector, &dev->mode_config.connector_list,
10899 if (connector->get_hw_state(connector)) {
10900 connector->base.dpms = DRM_MODE_DPMS_ON;
10901 connector->encoder->connectors_active = true;
10902 connector->base.encoder = &connector->encoder->base;
10904 connector->base.dpms = DRM_MODE_DPMS_OFF;
10905 connector->base.encoder = NULL;
10907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10908 connector->base.base.id,
10909 drm_get_connector_name(&connector->base),
10910 connector->base.encoder ? "enabled" : "disabled");
10914 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10915 * and i915 state tracking structures. */
10916 void intel_modeset_setup_hw_state(struct drm_device *dev,
10917 bool force_restore)
10919 struct drm_i915_private *dev_priv = dev->dev_private;
10921 struct intel_crtc *crtc;
10922 struct intel_encoder *encoder;
10925 intel_modeset_readout_hw_state(dev);
10928 * Now that we have the config, copy it to each CRTC struct
10929 * Note that this could go away if we move to using crtc_config
10930 * checking everywhere.
10932 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10934 if (crtc->active && i915_fastboot) {
10935 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10937 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10938 crtc->base.base.id);
10939 drm_mode_debug_printmodeline(&crtc->base.mode);
10943 /* HW state is read out, now we need to sanitize this mess. */
10944 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10946 intel_sanitize_encoder(encoder);
10949 for_each_pipe(pipe) {
10950 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10951 intel_sanitize_crtc(crtc);
10952 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10955 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10956 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10958 if (!pll->on || pll->active)
10961 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10963 pll->disable(dev_priv, pll);
10967 if (IS_HASWELL(dev))
10968 ilk_wm_get_hw_state(dev);
10970 if (force_restore) {
10971 i915_redisable_vga(dev);
10974 * We need to use raw interfaces for restoring state to avoid
10975 * checking (bogus) intermediate states.
10977 for_each_pipe(pipe) {
10978 struct drm_crtc *crtc =
10979 dev_priv->pipe_to_crtc_mapping[pipe];
10981 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10985 intel_modeset_update_staged_output_state(dev);
10988 intel_modeset_check_state(dev);
10990 drm_mode_config_reset(dev);
10993 void intel_modeset_gem_init(struct drm_device *dev)
10995 intel_modeset_init_hw(dev);
10997 intel_setup_overlay(dev);
10999 intel_modeset_setup_hw_state(dev, false);
11002 void intel_modeset_cleanup(struct drm_device *dev)
11004 struct drm_i915_private *dev_priv = dev->dev_private;
11005 struct drm_crtc *crtc;
11006 struct drm_connector *connector;
11009 * Interrupts and polling as the first thing to avoid creating havoc.
11010 * Too much stuff here (turning of rps, connectors, ...) would
11011 * experience fancy races otherwise.
11013 drm_irq_uninstall(dev);
11014 cancel_work_sync(&dev_priv->hotplug_work);
11016 * Due to the hpd irq storm handling the hotplug work can re-arm the
11017 * poll handlers. Hence disable polling after hpd handling is shut down.
11019 drm_kms_helper_poll_fini(dev);
11021 mutex_lock(&dev->struct_mutex);
11023 intel_unregister_dsm_handler();
11025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11026 /* Skip inactive CRTCs */
11030 intel_increase_pllclock(crtc);
11033 intel_disable_fbc(dev);
11035 intel_disable_gt_powersave(dev);
11037 ironlake_teardown_rc6(dev);
11039 mutex_unlock(&dev->struct_mutex);
11041 /* flush any delayed tasks or pending work */
11042 flush_scheduled_work();
11044 /* destroy backlight, if any, before the connectors */
11045 intel_panel_destroy_backlight(dev);
11047 /* destroy the sysfs files before encoders/connectors */
11048 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11049 drm_sysfs_connector_remove(connector);
11051 drm_mode_config_cleanup(dev);
11053 intel_cleanup_overlay(dev);
11057 * Return which encoder is currently attached for connector.
11059 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11061 return &intel_attached_encoder(connector)->base;
11064 void intel_connector_attach_encoder(struct intel_connector *connector,
11065 struct intel_encoder *encoder)
11067 connector->encoder = encoder;
11068 drm_mode_connector_attach_encoder(&connector->base,
11073 * set vga decode state - true == enable VGA decode
11075 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11077 struct drm_i915_private *dev_priv = dev->dev_private;
11080 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11082 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11084 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11085 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11089 struct intel_display_error_state {
11091 u32 power_well_driver;
11093 int num_transcoders;
11095 struct intel_cursor_error_state {
11100 } cursor[I915_MAX_PIPES];
11102 struct intel_pipe_error_state {
11104 } pipe[I915_MAX_PIPES];
11106 struct intel_plane_error_state {
11114 } plane[I915_MAX_PIPES];
11116 struct intel_transcoder_error_state {
11117 enum transcoder cpu_transcoder;
11130 struct intel_display_error_state *
11131 intel_display_capture_error_state(struct drm_device *dev)
11133 drm_i915_private_t *dev_priv = dev->dev_private;
11134 struct intel_display_error_state *error;
11135 int transcoders[] = {
11143 if (INTEL_INFO(dev)->num_pipes == 0)
11146 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11150 if (HAS_POWER_WELL(dev))
11151 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11154 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11157 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11158 error->cursor[i].control = I915_READ(CURCNTR(i));
11159 error->cursor[i].position = I915_READ(CURPOS(i));
11160 error->cursor[i].base = I915_READ(CURBASE(i));
11162 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11163 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11164 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11167 error->plane[i].control = I915_READ(DSPCNTR(i));
11168 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11169 if (INTEL_INFO(dev)->gen <= 3) {
11170 error->plane[i].size = I915_READ(DSPSIZE(i));
11171 error->plane[i].pos = I915_READ(DSPPOS(i));
11173 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11174 error->plane[i].addr = I915_READ(DSPADDR(i));
11175 if (INTEL_INFO(dev)->gen >= 4) {
11176 error->plane[i].surface = I915_READ(DSPSURF(i));
11177 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11180 error->pipe[i].source = I915_READ(PIPESRC(i));
11183 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11184 if (HAS_DDI(dev_priv->dev))
11185 error->num_transcoders++; /* Account for eDP. */
11187 for (i = 0; i < error->num_transcoders; i++) {
11188 enum transcoder cpu_transcoder = transcoders[i];
11190 if (!intel_display_power_enabled(dev,
11191 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11194 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11196 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11197 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11198 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11199 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11200 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11201 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11202 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11208 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11211 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11212 struct drm_device *dev,
11213 struct intel_display_error_state *error)
11220 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11221 if (HAS_POWER_WELL(dev))
11222 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11223 error->power_well_driver);
11225 err_printf(m, "Pipe [%d]:\n", i);
11226 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11228 err_printf(m, "Plane [%d]:\n", i);
11229 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11230 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11231 if (INTEL_INFO(dev)->gen <= 3) {
11232 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11233 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11235 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11236 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11237 if (INTEL_INFO(dev)->gen >= 4) {
11238 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11239 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11242 err_printf(m, "Cursor [%d]:\n", i);
11243 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11244 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11245 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11248 for (i = 0; i < error->num_transcoders; i++) {
11249 err_printf(m, "CPU transcoder: %c\n",
11250 transcoder_name(error->transcoder[i].cpu_transcoder));
11251 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11252 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11253 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11254 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11255 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11256 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11257 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);