drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 #define INTEL_P2_NUM                  2
  63 typedef struct intel_limit intel_limit_t;
  64 struct intel_limit {
  65         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  66         intel_p2_t          p2;
  67 };
  68
  69 /* FDI */
  70 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t intel_limits_vlv_dp = {
 340         .dot = { .min = 25000, .max = 270000 },
 341         .vco = { .min = 4000000, .max = 6000000 },
 342         .n = { .min = 1, .max = 7 },
 343         .m = { .min = 22, .max = 450 },
 344         .m1 = { .min = 2, .max = 3 },
 345         .m2 = { .min = 11, .max = 156 },
 346         .p = { .min = 10, .max = 30 },
 347         .p1 = { .min = 1, .max = 3 },
 348         .p2 = { .dot_limit = 270000,
 349                 .p2_slow = 2, .p2_fast = 20 },
 350 };
 351
 352 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 353                                                 int refclk)
 354 {
 355         struct drm_device *dev = crtc->dev;
 356         const intel_limit_t *limit;
 357
 358         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 359                 if (intel_is_dual_link_lvds(dev)) {
 360                         if (refclk == 100000)
 361                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 362                         else
 363                                 limit = &intel_limits_ironlake_dual_lvds;
 364                 } else {
 365                         if (refclk == 100000)
 366                                 limit = &intel_limits_ironlake_single_lvds_100m;
 367                         else
 368                                 limit = &intel_limits_ironlake_single_lvds;
 369                 }
 370         } else
 371                 limit = &intel_limits_ironlake_dac;
 372
 373         return limit;
 374 }
 375
 376 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev))
 383                         limit = &intel_limits_g4x_dual_channel_lvds;
 384                 else
 385                         limit = &intel_limits_g4x_single_channel_lvds;
 386         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 387                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 388                 limit = &intel_limits_g4x_hdmi;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 390                 limit = &intel_limits_g4x_sdvo;
 391         } else /* The option is for other outputs */
 392                 limit = &intel_limits_i9xx_sdvo;
 393
 394         return limit;
 395 }
 396
 397 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 398 {
 399         struct drm_device *dev = crtc->dev;
 400         const intel_limit_t *limit;
 401
 402         if (HAS_PCH_SPLIT(dev))
 403                 limit = intel_ironlake_limit(crtc, refclk);
 404         else if (IS_G4X(dev)) {
 405                 limit = intel_g4x_limit(crtc);
 406         } else if (IS_PINEVIEW(dev)) {
 407                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 408                         limit = &intel_limits_pineview_lvds;
 409                 else
 410                         limit = &intel_limits_pineview_sdvo;
 411         } else if (IS_VALLEYVIEW(dev)) {
 412                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 413                         limit = &intel_limits_vlv_dac;
 414                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 415                         limit = &intel_limits_vlv_hdmi;
 416                 else
 417                         limit = &intel_limits_vlv_dp;
 418         } else if (!IS_GEN2(dev)) {
 419                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 420                         limit = &intel_limits_i9xx_lvds;
 421                 else
 422                         limit = &intel_limits_i9xx_sdvo;
 423         } else {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_i8xx_lvds;
 426                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 427                         limit = &intel_limits_i8xx_dvo;
 428                 else
 429                         limit = &intel_limits_i8xx_dac;
 430         }
 431         return limit;
 432 }
 433
 434 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 435 static void pineview_clock(int refclk, intel_clock_t *clock)
 436 {
 437         clock->m = clock->m2 + 2;
 438         clock->p = clock->p1 * clock->p2;
 439         clock->vco = refclk * clock->m / clock->n;
 440         clock->dot = clock->vco / clock->p;
 441 }
 442
 443 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 444 {
 445         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 446 }
 447
 448 static void i9xx_clock(int refclk, intel_clock_t *clock)
 449 {
 450         clock->m = i9xx_dpll_compute_m(clock);
 451         clock->p = clock->p1 * clock->p2;
 452         clock->vco = refclk * clock->m / (clock->n + 2);
 453         clock->dot = clock->vco / clock->p;
 454 }
 455
 456 /**
 457  * Returns whether any output on the specified pipe is of the specified type
 458  */
 459 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 460 {
 461         struct drm_device *dev = crtc->dev;
 462         struct intel_encoder *encoder;
 463
 464         for_each_encoder_on_crtc(dev, crtc, encoder)
 465                 if (encoder->type == type)
 466                         return true;
 467
 468         return false;
 469 }
 470
 471 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 472 /**
 473  * Returns whether the given set of divisors are valid for a given refclk with
 474  * the given connectors.
 475  */
 476
 477 static bool intel_PLL_is_valid(struct drm_device *dev,
 478                                const intel_limit_t *limit,
 479                                const intel_clock_t *clock)
 480 {
 481         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 482                 INTELPllInvalid("p1 out of range\n");
 483         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 484                 INTELPllInvalid("p out of range\n");
 485         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 486                 INTELPllInvalid("m2 out of range\n");
 487         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 488                 INTELPllInvalid("m1 out of range\n");
 489         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 490                 INTELPllInvalid("m1 <= m2\n");
 491         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 492                 INTELPllInvalid("m out of range\n");
 493         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 494                 INTELPllInvalid("n out of range\n");
 495         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 496                 INTELPllInvalid("vco out of range\n");
 497         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 498          * connector, etc., rather than just a single range.
 499          */
 500         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 501                 INTELPllInvalid("dot out of range\n");
 502
 503         return true;
 504 }
 505
 506 static bool
 507 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 508                     int target, int refclk, intel_clock_t *match_clock,
 509                     intel_clock_t *best_clock)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         intel_clock_t clock;
 513         int err = target;
 514
 515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 516                 /*
 517                  * For LVDS just rely on its current settings for dual-channel.
 518                  * We haven't figured out how to reliably set up different
 519                  * single/dual channel state, if we even can.
 520                  */
 521                 if (intel_is_dual_link_lvds(dev))
 522                         clock.p2 = limit->p2.p2_fast;
 523                 else
 524                         clock.p2 = limit->p2.p2_slow;
 525         } else {
 526                 if (target < limit->p2.dot_limit)
 527                         clock.p2 = limit->p2.p2_slow;
 528                 else
 529                         clock.p2 = limit->p2.p2_fast;
 530         }
 531
 532         memset(best_clock, 0, sizeof(*best_clock));
 533
 534         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 535              clock.m1++) {
 536                 for (clock.m2 = limit->m2.min;
 537                      clock.m2 <= limit->m2.max; clock.m2++) {
 538                         if (clock.m2 >= clock.m1)
 539                                 break;
 540                         for (clock.n = limit->n.min;
 541                              clock.n <= limit->n.max; clock.n++) {
 542                                 for (clock.p1 = limit->p1.min;
 543                                         clock.p1 <= limit->p1.max; clock.p1++) {
 544                                         int this_err;
 545
 546                                         i9xx_clock(refclk, &clock);
 547                                         if (!intel_PLL_is_valid(dev, limit,
 548                                                                 &clock))
 549                                                 continue;
 550                                         if (match_clock &&
 551                                             clock.p != match_clock->p)
 552                                                 continue;
 553
 554                                         this_err = abs(clock.dot - target);
 555                                         if (this_err < err) {
 556                                                 *best_clock = clock;
 557                                                 err = this_err;
 558                                         }
 559                                 }
 560                         }
 561                 }
 562         }
 563
 564         return (err != target);
 565 }
 566
 567 static bool
 568 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 569                    int target, int refclk, intel_clock_t *match_clock,
 570                    intel_clock_t *best_clock)
 571 {
 572         struct drm_device *dev = crtc->dev;
 573         intel_clock_t clock;
 574         int err = target;
 575
 576         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 577                 /*
 578                  * For LVDS just rely on its current settings for dual-channel.
 579                  * We haven't figured out how to reliably set up different
 580                  * single/dual channel state, if we even can.
 581                  */
 582                 if (intel_is_dual_link_lvds(dev))
 583                         clock.p2 = limit->p2.p2_fast;
 584                 else
 585                         clock.p2 = limit->p2.p2_slow;
 586         } else {
 587                 if (target < limit->p2.dot_limit)
 588                         clock.p2 = limit->p2.p2_slow;
 589                 else
 590                         clock.p2 = limit->p2.p2_fast;
 591         }
 592
 593         memset(best_clock, 0, sizeof(*best_clock));
 594
 595         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 596              clock.m1++) {
 597                 for (clock.m2 = limit->m2.min;
 598                      clock.m2 <= limit->m2.max; clock.m2++) {
 599                         for (clock.n = limit->n.min;
 600                              clock.n <= limit->n.max; clock.n++) {
 601                                 for (clock.p1 = limit->p1.min;
 602                                         clock.p1 <= limit->p1.max; clock.p1++) {
 603                                         int this_err;
 604
 605                                         pineview_clock(refclk, &clock);
 606                                         if (!intel_PLL_is_valid(dev, limit,
 607                                                                 &clock))
 608                                                 continue;
 609                                         if (match_clock &&
 610                                             clock.p != match_clock->p)
 611                                                 continue;
 612
 613                                         this_err = abs(clock.dot - target);
 614                                         if (this_err < err) {
 615                                                 *best_clock = clock;
 616                                                 err = this_err;
 617                                         }
 618                                 }
 619                         }
 620                 }
 621         }
 622
 623         return (err != target);
 624 }
 625
 626 static bool
 627 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 628                    int target, int refclk, intel_clock_t *match_clock,
 629                    intel_clock_t *best_clock)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int max_n;
 634         bool found;
 635         /* approximately equals target * 0.00585 */
 636         int err_most = (target >> 8) + (target >> 9);
 637         found = false;
 638
 639         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 640                 if (intel_is_dual_link_lvds(dev))
 641                         clock.p2 = limit->p2.p2_fast;
 642                 else
 643                         clock.p2 = limit->p2.p2_slow;
 644         } else {
 645                 if (target < limit->p2.dot_limit)
 646                         clock.p2 = limit->p2.p2_slow;
 647                 else
 648                         clock.p2 = limit->p2.p2_fast;
 649         }
 650
 651         memset(best_clock, 0, sizeof(*best_clock));
 652         max_n = limit->n.max;
 653         /* based on hardware requirement, prefer smaller n to precision */
 654         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 655                 /* based on hardware requirement, prefere larger m1,m2 */
 656                 for (clock.m1 = limit->m1.max;
 657                      clock.m1 >= limit->m1.min; clock.m1--) {
 658                         for (clock.m2 = limit->m2.max;
 659                              clock.m2 >= limit->m2.min; clock.m2--) {
 660                                 for (clock.p1 = limit->p1.max;
 661                                      clock.p1 >= limit->p1.min; clock.p1--) {
 662                                         int this_err;
 663
 664                                         i9xx_clock(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(dev, limit,
 666                                                                 &clock))
 667                                                 continue;
 668
 669                                         this_err = abs(clock.dot - target);
 670                                         if (this_err < err_most) {
 671                                                 *best_clock = clock;
 672                                                 err_most = this_err;
 673                                                 max_n = clock.n;
 674                                                 found = true;
 675                                         }
 676                                 }
 677                         }
 678                 }
 679         }
 680         return found;
 681 }
 682
 683 static bool
 684 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 685                    int target, int refclk, intel_clock_t *match_clock,
 686                    intel_clock_t *best_clock)
 687 {
 688         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 689         u32 m, n, fastclk;
 690         u32 updrate, minupdate, fracbits, p;
 691         unsigned long bestppm, ppm, absppm;
 692         int dotclk, flag;
 693
 694         flag = 0;
 695         dotclk = target * 1000;
 696         bestppm = 1000000;
 697         ppm = absppm = 0;
 698         fastclk = dotclk / (2*100);
 699         updrate = 0;
 700         minupdate = 19200;
 701         fracbits = 1;
 702         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 703         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 704
 705         /* based on hardware requirement, prefer smaller n to precision */
 706         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 707                 updrate = refclk / n;
 708                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 709                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 710                                 if (p2 > 10)
 711                                         p2 = p2 - 1;
 712                                 p = p1 * p2;
 713                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 714                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 715                                         m2 = (((2*(fastclk * p * n / m1 )) +
 716                                                refclk) / (2*refclk));
 717                                         m = m1 * m2;
 718                                         vco = updrate * m;
 719                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 720                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 721                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 722                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 723                                                         bestppm = 0;
 724                                                         flag = 1;
 725                                                 }
 726                                                 if (absppm < bestppm - 10) {
 727                                                         bestppm = absppm;
 728                                                         flag = 1;
 729                                                 }
 730                                                 if (flag) {
 731                                                         bestn = n;
 732                                                         bestm1 = m1;
 733                                                         bestm2 = m2;
 734                                                         bestp1 = p1;
 735                                                         bestp2 = p2;
 736                                                         flag = 0;
 737                                                 }
 738                                         }
 739                                 }
 740                         }
 741                 }
 742         }
 743         best_clock->n = bestn;
 744         best_clock->m1 = bestm1;
 745         best_clock->m2 = bestm2;
 746         best_clock->p1 = bestp1;
 747         best_clock->p2 = bestp2;
 748
 749         return true;
 750 }
 751
 752 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 753                                              enum pipe pipe)
 754 {
 755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757
 758         return intel_crtc->config.cpu_transcoder;
 759 }
 760
 761 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 762 {
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         u32 frame, frame_reg = PIPEFRAME(pipe);
 765
 766         frame = I915_READ(frame_reg);
 767
 768         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 769                 DRM_DEBUG_KMS("vblank wait timed out\n");
 770 }
 771
 772 /**
 773  * intel_wait_for_vblank - wait for vblank on a given pipe
 774  * @dev: drm device
 775  * @pipe: pipe to wait for
 776  *
 777  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 778  * mode setting code.
 779  */
 780 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 781 {
 782         struct drm_i915_private *dev_priv = dev->dev_private;
 783         int pipestat_reg = PIPESTAT(pipe);
 784
 785         if (INTEL_INFO(dev)->gen >= 5) {
 786                 ironlake_wait_for_vblank(dev, pipe);
 787                 return;
 788         }
 789
 790         /* Clear existing vblank status. Note this will clear any other
 791          * sticky status fields as well.
 792          *
 793          * This races with i915_driver_irq_handler() with the result
 794          * that either function could miss a vblank event.  Here it is not
 795          * fatal, as we will either wait upon the next vblank interrupt or
 796          * timeout.  Generally speaking intel_wait_for_vblank() is only
 797          * called during modeset at which time the GPU should be idle and
 798          * should *not* be performing page flips and thus not waiting on
 799          * vblanks...
 800          * Currently, the result of us stealing a vblank from the irq
 801          * handler is that a single frame will be skipped during swapbuffers.
 802          */
 803         I915_WRITE(pipestat_reg,
 804                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 805
 806         /* Wait for vblank interrupt bit to set */
 807         if (wait_for(I915_READ(pipestat_reg) &
 808                      PIPE_VBLANK_INTERRUPT_STATUS,
 809                      50))
 810                 DRM_DEBUG_KMS("vblank wait timed out\n");
 811 }
 812
 813 /*
 814  * intel_wait_for_pipe_off - wait for pipe to turn off
 815  * @dev: drm device
 816  * @pipe: pipe to wait for
 817  *
 818  * After disabling a pipe, we can't wait for vblank in the usual way,
 819  * spinning on the vblank interrupt status bit, since we won't actually
 820  * see an interrupt when the pipe is disabled.
 821  *
 822  * On Gen4 and above:
 823  *   wait for the pipe register state bit to turn off
 824  *
 825  * Otherwise:
 826  *   wait for the display line value to settle (it usually
 827  *   ends up stopping at the start of the next frame).
 828  *
 829  */
 830 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 834                                                                       pipe);
 835
 836         if (INTEL_INFO(dev)->gen >= 4) {
 837                 int reg = PIPECONF(cpu_transcoder);
 838
 839                 /* Wait for the Pipe State to go off */
 840                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 841                              100))
 842                         WARN(1, "pipe_off wait timed out\n");
 843         } else {
 844                 u32 last_line, line_mask;
 845                 int reg = PIPEDSL(pipe);
 846                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 847
 848                 if (IS_GEN2(dev))
 849                         line_mask = DSL_LINEMASK_GEN2;
 850                 else
 851                         line_mask = DSL_LINEMASK_GEN3;
 852
 853                 /* Wait for the display line to settle */
 854                 do {
 855                         last_line = I915_READ(reg) & line_mask;
 856                         mdelay(5);
 857                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 858                          time_after(timeout, jiffies));
 859                 if (time_after(jiffies, timeout))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         }
 862 }
 863
 864 /*
 865  * ibx_digital_port_connected - is the specified port connected?
 866  * @dev_priv: i915 private structure
 867  * @port: the port to test
 868  *
 869  * Returns true if @port is connected, false otherwise.
 870  */
 871 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 872                                 struct intel_digital_port *port)
 873 {
 874         u32 bit;
 875
 876         if (HAS_PCH_IBX(dev_priv->dev)) {
 877                 switch(port->port) {
 878                 case PORT_B:
 879                         bit = SDE_PORTB_HOTPLUG;
 880                         break;
 881                 case PORT_C:
 882                         bit = SDE_PORTC_HOTPLUG;
 883                         break;
 884                 case PORT_D:
 885                         bit = SDE_PORTD_HOTPLUG;
 886                         break;
 887                 default:
 888                         return true;
 889                 }
 890         } else {
 891                 switch(port->port) {
 892                 case PORT_B:
 893                         bit = SDE_PORTB_HOTPLUG_CPT;
 894                         break;
 895                 case PORT_C:
 896                         bit = SDE_PORTC_HOTPLUG_CPT;
 897                         break;
 898                 case PORT_D:
 899                         bit = SDE_PORTD_HOTPLUG_CPT;
 900                         break;
 901                 default:
 902                         return true;
 903                 }
 904         }
 905
 906         return I915_READ(SDEISR) & bit;
 907 }
 908
 909 static const char *state_string(bool enabled)
 910 {
 911         return enabled ? "on" : "off";
 912 }
 913
 914 /* Only for pre-ILK configs */
 915 void assert_pll(struct drm_i915_private *dev_priv,
 916                 enum pipe pipe, bool state)
 917 {
 918         int reg;
 919         u32 val;
 920         bool cur_state;
 921
 922         reg = DPLL(pipe);
 923         val = I915_READ(reg);
 924         cur_state = !!(val & DPLL_VCO_ENABLE);
 925         WARN(cur_state != state,
 926              "PLL state assertion failure (expected %s, current %s)\n",
 927              state_string(state), state_string(cur_state));
 928 }
 929
 930 struct intel_shared_dpll *
 931 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 932 {
 933         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 934
 935         if (crtc->config.shared_dpll < 0)
 936                 return NULL;
 937
 938         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 939 }
 940
 941 /* For ILK+ */
 942 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 943                         struct intel_shared_dpll *pll,
 944                         bool state)
 945 {
 946         bool cur_state;
 947         struct intel_dpll_hw_state hw_state;
 948
 949         if (HAS_PCH_LPT(dev_priv->dev)) {
 950                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 951                 return;
 952         }
 953
 954         if (WARN (!pll,
 955                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 956                 return;
 957
 958         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 959         WARN(cur_state != state,
 960              "%s assertion failure (expected %s, current %s)\n",
 961              pll->name, state_string(state), state_string(cur_state));
 962 }
 963
 964 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 965                           enum pipe pipe, bool state)
 966 {
 967         int reg;
 968         u32 val;
 969         bool cur_state;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (HAS_DDI(dev_priv->dev)) {
 974                 /* DDI does not have a specific FDI_TX register */
 975                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 976                 val = I915_READ(reg);
 977                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 978         } else {
 979                 reg = FDI_TX_CTL(pipe);
 980                 val = I915_READ(reg);
 981                 cur_state = !!(val & FDI_TX_ENABLE);
 982         }
 983         WARN(cur_state != state,
 984              "FDI TX state assertion failure (expected %s, current %s)\n",
 985              state_string(state), state_string(cur_state));
 986 }
 987 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 988 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 989
 990 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 991                           enum pipe pipe, bool state)
 992 {
 993         int reg;
 994         u32 val;
 995         bool cur_state;
 996
 997         reg = FDI_RX_CTL(pipe);
 998         val = I915_READ(reg);
 999         cur_state = !!(val & FDI_RX_ENABLE);
1000         WARN(cur_state != state,
1001              "FDI RX state assertion failure (expected %s, current %s)\n",
1002              state_string(state), state_string(cur_state));
1003 }
1004 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008                                       enum pipe pipe)
1009 {
1010         int reg;
1011         u32 val;
1012
1013         /* ILK FDI PLL is always enabled */
1014         if (dev_priv->info->gen == 5)
1015                 return;
1016
1017         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1018         if (HAS_DDI(dev_priv->dev))
1019                 return;
1020
1021         reg = FDI_TX_CTL(pipe);
1022         val = I915_READ(reg);
1023         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024 }
1025
1026 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027                        enum pipe pipe, bool state)
1028 {
1029         int reg;
1030         u32 val;
1031         bool cur_state;
1032
1033         reg = FDI_RX_CTL(pipe);
1034         val = I915_READ(reg);
1035         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036         WARN(cur_state != state,
1037              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038              state_string(state), state_string(cur_state));
1039 }
1040
1041 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042                                   enum pipe pipe)
1043 {
1044         int pp_reg, lvds_reg;
1045         u32 val;
1046         enum pipe panel_pipe = PIPE_A;
1047         bool locked = true;
1048
1049         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050                 pp_reg = PCH_PP_CONTROL;
1051                 lvds_reg = PCH_LVDS;
1052         } else {
1053                 pp_reg = PP_CONTROL;
1054                 lvds_reg = LVDS;
1055         }
1056
1057         val = I915_READ(pp_reg);
1058         if (!(val & PANEL_POWER_ON) ||
1059             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060                 locked = false;
1061
1062         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063                 panel_pipe = PIPE_B;
1064
1065         WARN(panel_pipe == pipe && locked,
1066              "panel assertion failure, pipe %c regs locked\n",
1067              pipe_name(pipe));
1068 }
1069
1070 void assert_pipe(struct drm_i915_private *dev_priv,
1071                  enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         /* if we need the pipe A quirk it must be always on */
1080         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081                 state = true;
1082
1083         if (!intel_display_power_enabled(dev_priv->dev,
1084                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1085                 cur_state = false;
1086         } else {
1087                 reg = PIPECONF(cpu_transcoder);
1088                 val = I915_READ(reg);
1089                 cur_state = !!(val & PIPECONF_ENABLE);
1090         }
1091
1092         WARN(cur_state != state,
1093              "pipe %c assertion failure (expected %s, current %s)\n",
1094              pipe_name(pipe), state_string(state), state_string(cur_state));
1095 }
1096
1097 static void assert_plane(struct drm_i915_private *dev_priv,
1098                          enum plane plane, bool state)
1099 {
1100         int reg;
1101         u32 val;
1102         bool cur_state;
1103
1104         reg = DSPCNTR(plane);
1105         val = I915_READ(reg);
1106         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107         WARN(cur_state != state,
1108              "plane %c assertion failure (expected %s, current %s)\n",
1109              plane_name(plane), state_string(state), state_string(cur_state));
1110 }
1111
1112 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
1115 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116                                    enum pipe pipe)
1117 {
1118         struct drm_device *dev = dev_priv->dev;
1119         int reg, i;
1120         u32 val;
1121         int cur_pipe;
1122
1123         /* Primary planes are fixed to pipes on gen4+ */
1124         if (INTEL_INFO(dev)->gen >= 4) {
1125                 reg = DSPCNTR(pipe);
1126                 val = I915_READ(reg);
1127                 WARN((val & DISPLAY_PLANE_ENABLE),
1128                      "plane %c assertion failure, should be disabled but not\n",
1129                      plane_name(pipe));
1130                 return;
1131         }
1132
1133         /* Need to check both planes against the pipe */
1134         for_each_pipe(i) {
1135                 reg = DSPCNTR(i);
1136                 val = I915_READ(reg);
1137                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138                         DISPPLANE_SEL_PIPE_SHIFT;
1139                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1140                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141                      plane_name(i), pipe_name(pipe));
1142         }
1143 }
1144
1145 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146                                     enum pipe pipe)
1147 {
1148         struct drm_device *dev = dev_priv->dev;
1149         int reg, i;
1150         u32 val;
1151
1152         if (IS_VALLEYVIEW(dev)) {
1153                 for (i = 0; i < dev_priv->num_plane; i++) {
1154                         reg = SPCNTR(pipe, i);
1155                         val = I915_READ(reg);
1156                         WARN((val & SP_ENABLE),
1157                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158                              sprite_name(pipe, i), pipe_name(pipe));
1159                 }
1160         } else if (INTEL_INFO(dev)->gen >= 7) {
1161                 reg = SPRCTL(pipe);
1162                 val = I915_READ(reg);
1163                 WARN((val & SPRITE_ENABLE),
1164                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1165                      plane_name(pipe), pipe_name(pipe));
1166         } else if (INTEL_INFO(dev)->gen >= 5) {
1167                 reg = DVSCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN((val & DVS_ENABLE),
1170                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1171                      plane_name(pipe), pipe_name(pipe));
1172         }
1173 }
1174
1175 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176 {
1177         u32 val;
1178         bool enabled;
1179
1180         if (HAS_PCH_LPT(dev_priv->dev)) {
1181                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182                 return;
1183         }
1184
1185         val = I915_READ(PCH_DREF_CONTROL);
1186         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187                             DREF_SUPERSPREAD_SOURCE_MASK));
1188         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189 }
1190
1191 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192                                            enum pipe pipe)
1193 {
1194         int reg;
1195         u32 val;
1196         bool enabled;
1197
1198         reg = PCH_TRANSCONF(pipe);
1199         val = I915_READ(reg);
1200         enabled = !!(val & TRANS_ENABLE);
1201         WARN(enabled,
1202              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203              pipe_name(pipe));
1204 }
1205
1206 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207                             enum pipe pipe, u32 port_sel, u32 val)
1208 {
1209         if ((val & DP_PORT_EN) == 0)
1210                 return false;
1211
1212         if (HAS_PCH_CPT(dev_priv->dev)) {
1213                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216                         return false;
1217         } else {
1218                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219                         return false;
1220         }
1221         return true;
1222 }
1223
1224 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225                               enum pipe pipe, u32 val)
1226 {
1227         if ((val & SDVO_ENABLE) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1232                         return false;
1233         } else {
1234                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1235                         return false;
1236         }
1237         return true;
1238 }
1239
1240 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241                               enum pipe pipe, u32 val)
1242 {
1243         if ((val & LVDS_PORT_EN) == 0)
1244                 return false;
1245
1246         if (HAS_PCH_CPT(dev_priv->dev)) {
1247                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248                         return false;
1249         } else {
1250                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251                         return false;
1252         }
1253         return true;
1254 }
1255
1256 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257                               enum pipe pipe, u32 val)
1258 {
1259         if ((val & ADPA_DAC_ENABLE) == 0)
1260                 return false;
1261         if (HAS_PCH_CPT(dev_priv->dev)) {
1262                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263                         return false;
1264         } else {
1265                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266                         return false;
1267         }
1268         return true;
1269 }
1270
1271 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe, int reg, u32 port_sel)
1273 {
1274         u32 val = I915_READ(reg);
1275         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1276              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1277              reg, pipe_name(pipe));
1278
1279         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280              && (val & DP_PIPEB_SELECT),
1281              "IBX PCH dp port still using transcoder B\n");
1282 }
1283
1284 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285                                      enum pipe pipe, int reg)
1286 {
1287         u32 val = I915_READ(reg);
1288         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1289              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290              reg, pipe_name(pipe));
1291
1292         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1293              && (val & SDVO_PIPE_B_SELECT),
1294              "IBX PCH hdmi port still using transcoder B\n");
1295 }
1296
1297 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298                                       enum pipe pipe)
1299 {
1300         int reg;
1301         u32 val;
1302
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1306
1307         reg = PCH_ADPA;
1308         val = I915_READ(reg);
1309         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1310              "PCH VGA enabled on transcoder %c, should be disabled\n",
1311              pipe_name(pipe));
1312
1313         reg = PCH_LVDS;
1314         val = I915_READ(reg);
1315         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1316              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1317              pipe_name(pipe));
1318
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1322 }
1323
1324 static void vlv_enable_pll(struct intel_crtc *crtc)
1325 {
1326         struct drm_device *dev = crtc->base.dev;
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         int reg = DPLL(crtc->pipe);
1329         u32 dpll = crtc->config.dpll_hw_state.dpll;
1330
1331         assert_pipe_disabled(dev_priv, crtc->pipe);
1332
1333         /* No really, not for ILK+ */
1334         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1335
1336         /* PLL is protected by panel, make sure we can write it */
1337         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1338                 assert_panel_unlocked(dev_priv, crtc->pipe);
1339
1340         I915_WRITE(reg, dpll);
1341         POSTING_READ(reg);
1342         udelay(150);
1343
1344         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1345                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1346
1347         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1348         POSTING_READ(DPLL_MD(crtc->pipe));
1349
1350         /* We do this three times for luck */
1351         I915_WRITE(reg, dpll);
1352         POSTING_READ(reg);
1353         udelay(150); /* wait for warmup */
1354         I915_WRITE(reg, dpll);
1355         POSTING_READ(reg);
1356         udelay(150); /* wait for warmup */
1357         I915_WRITE(reg, dpll);
1358         POSTING_READ(reg);
1359         udelay(150); /* wait for warmup */
1360 }
1361
1362 static void i9xx_enable_pll(struct intel_crtc *crtc)
1363 {
1364         struct drm_device *dev = crtc->base.dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         int reg = DPLL(crtc->pipe);
1367         u32 dpll = crtc->config.dpll_hw_state.dpll;
1368
1369         assert_pipe_disabled(dev_priv, crtc->pipe);
1370
1371         /* No really, not for ILK+ */
1372         BUG_ON(dev_priv->info->gen >= 5);
1373
1374         /* PLL is protected by panel, make sure we can write it */
1375         if (IS_MOBILE(dev) && !IS_I830(dev))
1376                 assert_panel_unlocked(dev_priv, crtc->pipe);
1377
1378         I915_WRITE(reg, dpll);
1379
1380         /* Wait for the clocks to stabilize. */
1381         POSTING_READ(reg);
1382         udelay(150);
1383
1384         if (INTEL_INFO(dev)->gen >= 4) {
1385                 I915_WRITE(DPLL_MD(crtc->pipe),
1386                            crtc->config.dpll_hw_state.dpll_md);
1387         } else {
1388                 /* The pixel multiplier can only be updated once the
1389                  * DPLL is enabled and the clocks are stable.
1390                  *
1391                  * So write it again.
1392                  */
1393                 I915_WRITE(reg, dpll);
1394         }
1395
1396         /* We do this three times for luck */
1397         I915_WRITE(reg, dpll);
1398         POSTING_READ(reg);
1399         udelay(150); /* wait for warmup */
1400         I915_WRITE(reg, dpll);
1401         POSTING_READ(reg);
1402         udelay(150); /* wait for warmup */
1403         I915_WRITE(reg, dpll);
1404         POSTING_READ(reg);
1405         udelay(150); /* wait for warmup */
1406 }
1407
1408 /**
1409  * i9xx_disable_pll - disable a PLL
1410  * @dev_priv: i915 private structure
1411  * @pipe: pipe PLL to disable
1412  *
1413  * Disable the PLL for @pipe, making sure the pipe is off first.
1414  *
1415  * Note!  This is for pre-ILK only.
1416  */
1417 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1418 {
1419         /* Don't disable pipe A or pipe A PLLs if needed */
1420         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1421                 return;
1422
1423         /* Make sure the pipe isn't still relying on us */
1424         assert_pipe_disabled(dev_priv, pipe);
1425
1426         I915_WRITE(DPLL(pipe), 0);
1427         POSTING_READ(DPLL(pipe));
1428 }
1429
1430 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431 {
1432         u32 port_mask;
1433
1434         if (!port)
1435                 port_mask = DPLL_PORTB_READY_MASK;
1436         else
1437                 port_mask = DPLL_PORTC_READY_MASK;
1438
1439         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441                      'B' + port, I915_READ(DPLL(0)));
1442 }
1443
1444 /**
1445  * ironlake_enable_shared_dpll - enable PCH PLL
1446  * @dev_priv: i915 private structure
1447  * @pipe: pipe PLL to enable
1448  *
1449  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450  * drives the transcoder clock.
1451  */
1452 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1453 {
1454         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1455         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1456
1457         /* PCH PLLs only available on ILK, SNB and IVB */
1458         BUG_ON(dev_priv->info->gen < 5);
1459         if (WARN_ON(pll == NULL))
1460                 return;
1461
1462         if (WARN_ON(pll->refcount == 0))
1463                 return;
1464
1465         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466                       pll->name, pll->active, pll->on,
1467                       crtc->base.base.id);
1468
1469         if (pll->active++) {
1470                 WARN_ON(!pll->on);
1471                 assert_shared_dpll_enabled(dev_priv, pll);
1472                 return;
1473         }
1474         WARN_ON(pll->on);
1475
1476         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1477         pll->enable(dev_priv, pll);
1478         pll->on = true;
1479 }
1480
1481 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1482 {
1483         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1484         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1485
1486         /* PCH only available on ILK+ */
1487         BUG_ON(dev_priv->info->gen < 5);
1488         if (WARN_ON(pll == NULL))
1489                return;
1490
1491         if (WARN_ON(pll->refcount == 0))
1492                 return;
1493
1494         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495                       pll->name, pll->active, pll->on,
1496                       crtc->base.base.id);
1497
1498         if (WARN_ON(pll->active == 0)) {
1499                 assert_shared_dpll_disabled(dev_priv, pll);
1500                 return;
1501         }
1502
1503         assert_shared_dpll_enabled(dev_priv, pll);
1504         WARN_ON(!pll->on);
1505         if (--pll->active)
1506                 return;
1507
1508         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1509         pll->disable(dev_priv, pll);
1510         pll->on = false;
1511 }
1512
1513 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1514                                            enum pipe pipe)
1515 {
1516         struct drm_device *dev = dev_priv->dev;
1517         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519         uint32_t reg, val, pipeconf_val;
1520
1521         /* PCH only available on ILK+ */
1522         BUG_ON(dev_priv->info->gen < 5);
1523
1524         /* Make sure PCH DPLL is enabled */
1525         assert_shared_dpll_enabled(dev_priv,
1526                                    intel_crtc_to_shared_dpll(intel_crtc));
1527
1528         /* FDI must be feeding us bits for PCH ports */
1529         assert_fdi_tx_enabled(dev_priv, pipe);
1530         assert_fdi_rx_enabled(dev_priv, pipe);
1531
1532         if (HAS_PCH_CPT(dev)) {
1533                 /* Workaround: Set the timing override bit before enabling the
1534                  * pch transcoder. */
1535                 reg = TRANS_CHICKEN2(pipe);
1536                 val = I915_READ(reg);
1537                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1538                 I915_WRITE(reg, val);
1539         }
1540
1541         reg = PCH_TRANSCONF(pipe);
1542         val = I915_READ(reg);
1543         pipeconf_val = I915_READ(PIPECONF(pipe));
1544
1545         if (HAS_PCH_IBX(dev_priv->dev)) {
1546                 /*
1547                  * make the BPC in transcoder be consistent with
1548                  * that in pipeconf reg.
1549                  */
1550                 val &= ~PIPECONF_BPC_MASK;
1551                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1552         }
1553
1554         val &= ~TRANS_INTERLACE_MASK;
1555         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1556                 if (HAS_PCH_IBX(dev_priv->dev) &&
1557                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1558                         val |= TRANS_LEGACY_INTERLACED_ILK;
1559                 else
1560                         val |= TRANS_INTERLACED;
1561         else
1562                 val |= TRANS_PROGRESSIVE;
1563
1564         I915_WRITE(reg, val | TRANS_ENABLE);
1565         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1566                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1567 }
1568
1569 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1570                                       enum transcoder cpu_transcoder)
1571 {
1572         u32 val, pipeconf_val;
1573
1574         /* PCH only available on ILK+ */
1575         BUG_ON(dev_priv->info->gen < 5);
1576
1577         /* FDI must be feeding us bits for PCH ports */
1578         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1579         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1580
1581         /* Workaround: set timing override bit. */
1582         val = I915_READ(_TRANSA_CHICKEN2);
1583         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1584         I915_WRITE(_TRANSA_CHICKEN2, val);
1585
1586         val = TRANS_ENABLE;
1587         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1588
1589         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1590             PIPECONF_INTERLACED_ILK)
1591                 val |= TRANS_INTERLACED;
1592         else
1593                 val |= TRANS_PROGRESSIVE;
1594
1595         I915_WRITE(LPT_TRANSCONF, val);
1596         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1597                 DRM_ERROR("Failed to enable PCH transcoder\n");
1598 }
1599
1600 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1601                                             enum pipe pipe)
1602 {
1603         struct drm_device *dev = dev_priv->dev;
1604         uint32_t reg, val;
1605
1606         /* FDI relies on the transcoder */
1607         assert_fdi_tx_disabled(dev_priv, pipe);
1608         assert_fdi_rx_disabled(dev_priv, pipe);
1609
1610         /* Ports must be off as well */
1611         assert_pch_ports_disabled(dev_priv, pipe);
1612
1613         reg = PCH_TRANSCONF(pipe);
1614         val = I915_READ(reg);
1615         val &= ~TRANS_ENABLE;
1616         I915_WRITE(reg, val);
1617         /* wait for PCH transcoder off, transcoder state */
1618         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1619                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1620
1621         if (!HAS_PCH_IBX(dev)) {
1622                 /* Workaround: Clear the timing override chicken bit again. */
1623                 reg = TRANS_CHICKEN2(pipe);
1624                 val = I915_READ(reg);
1625                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1626                 I915_WRITE(reg, val);
1627         }
1628 }
1629
1630 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1631 {
1632         u32 val;
1633
1634         val = I915_READ(LPT_TRANSCONF);
1635         val &= ~TRANS_ENABLE;
1636         I915_WRITE(LPT_TRANSCONF, val);
1637         /* wait for PCH transcoder off, transcoder state */
1638         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1639                 DRM_ERROR("Failed to disable PCH transcoder\n");
1640
1641         /* Workaround: clear timing override bit. */
1642         val = I915_READ(_TRANSA_CHICKEN2);
1643         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1644         I915_WRITE(_TRANSA_CHICKEN2, val);
1645 }
1646
1647 /**
1648  * intel_enable_pipe - enable a pipe, asserting requirements
1649  * @dev_priv: i915 private structure
1650  * @pipe: pipe to enable
1651  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1652  *
1653  * Enable @pipe, making sure that various hardware specific requirements
1654  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1655  *
1656  * @pipe should be %PIPE_A or %PIPE_B.
1657  *
1658  * Will wait until the pipe is actually running (i.e. first vblank) before
1659  * returning.
1660  */
1661 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1662                               bool pch_port)
1663 {
1664         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665                                                                       pipe);
1666         enum pipe pch_transcoder;
1667         int reg;
1668         u32 val;
1669
1670         assert_planes_disabled(dev_priv, pipe);
1671         assert_sprites_disabled(dev_priv, pipe);
1672
1673         if (HAS_PCH_LPT(dev_priv->dev))
1674                 pch_transcoder = TRANSCODER_A;
1675         else
1676                 pch_transcoder = pipe;
1677
1678         /*
1679          * A pipe without a PLL won't actually be able to drive bits from
1680          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1681          * need the check.
1682          */
1683         if (!HAS_PCH_SPLIT(dev_priv->dev))
1684                 assert_pll_enabled(dev_priv, pipe);
1685         else {
1686                 if (pch_port) {
1687                         /* if driving the PCH, we need FDI enabled */
1688                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1689                         assert_fdi_tx_pll_enabled(dev_priv,
1690                                                   (enum pipe) cpu_transcoder);
1691                 }
1692                 /* FIXME: assert CPU port conditions for SNB+ */
1693         }
1694
1695         reg = PIPECONF(cpu_transcoder);
1696         val = I915_READ(reg);
1697         if (val & PIPECONF_ENABLE)
1698                 return;
1699
1700         I915_WRITE(reg, val | PIPECONF_ENABLE);
1701         intel_wait_for_vblank(dev_priv->dev, pipe);
1702 }
1703
1704 /**
1705  * intel_disable_pipe - disable a pipe, asserting requirements
1706  * @dev_priv: i915 private structure
1707  * @pipe: pipe to disable
1708  *
1709  * Disable @pipe, making sure that various hardware specific requirements
1710  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1711  *
1712  * @pipe should be %PIPE_A or %PIPE_B.
1713  *
1714  * Will wait until the pipe has shut down before returning.
1715  */
1716 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1717                                enum pipe pipe)
1718 {
1719         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1720                                                                       pipe);
1721         int reg;
1722         u32 val;
1723
1724         /*
1725          * Make sure planes won't keep trying to pump pixels to us,
1726          * or we might hang the display.
1727          */
1728         assert_planes_disabled(dev_priv, pipe);
1729         assert_sprites_disabled(dev_priv, pipe);
1730
1731         /* Don't disable pipe A or pipe A PLLs if needed */
1732         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1733                 return;
1734
1735         reg = PIPECONF(cpu_transcoder);
1736         val = I915_READ(reg);
1737         if ((val & PIPECONF_ENABLE) == 0)
1738                 return;
1739
1740         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1741         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1742 }
1743
1744 /*
1745  * Plane regs are double buffered, going from enabled->disabled needs a
1746  * trigger in order to latch.  The display address reg provides this.
1747  */
1748 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1749                                       enum plane plane)
1750 {
1751         if (dev_priv->info->gen >= 4)
1752                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1753         else
1754                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1755 }
1756
1757 /**
1758  * intel_enable_plane - enable a display plane on a given pipe
1759  * @dev_priv: i915 private structure
1760  * @plane: plane to enable
1761  * @pipe: pipe being fed
1762  *
1763  * Enable @plane on @pipe, making sure that @pipe is running first.
1764  */
1765 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1766                                enum plane plane, enum pipe pipe)
1767 {
1768         int reg;
1769         u32 val;
1770
1771         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772         assert_pipe_enabled(dev_priv, pipe);
1773
1774         reg = DSPCNTR(plane);
1775         val = I915_READ(reg);
1776         if (val & DISPLAY_PLANE_ENABLE)
1777                 return;
1778
1779         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1780         intel_flush_display_plane(dev_priv, plane);
1781         intel_wait_for_vblank(dev_priv->dev, pipe);
1782 }
1783
1784 /**
1785  * intel_disable_plane - disable a display plane
1786  * @dev_priv: i915 private structure
1787  * @plane: plane to disable
1788  * @pipe: pipe consuming the data
1789  *
1790  * Disable @plane; should be an independent operation.
1791  */
1792 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1793                                 enum plane plane, enum pipe pipe)
1794 {
1795         int reg;
1796         u32 val;
1797
1798         reg = DSPCNTR(plane);
1799         val = I915_READ(reg);
1800         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1801                 return;
1802
1803         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1804         intel_flush_display_plane(dev_priv, plane);
1805         intel_wait_for_vblank(dev_priv->dev, pipe);
1806 }
1807
1808 static bool need_vtd_wa(struct drm_device *dev)
1809 {
1810 #ifdef CONFIG_INTEL_IOMMU
1811         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1812                 return true;
1813 #endif
1814         return false;
1815 }
1816
1817 int
1818 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1819                            struct drm_i915_gem_object *obj,
1820                            struct intel_ring_buffer *pipelined)
1821 {
1822         struct drm_i915_private *dev_priv = dev->dev_private;
1823         u32 alignment;
1824         int ret;
1825
1826         switch (obj->tiling_mode) {
1827         case I915_TILING_NONE:
1828                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1829                         alignment = 128 * 1024;
1830                 else if (INTEL_INFO(dev)->gen >= 4)
1831                         alignment = 4 * 1024;
1832                 else
1833                         alignment = 64 * 1024;
1834                 break;
1835         case I915_TILING_X:
1836                 /* pin() will align the object as required by fence */
1837                 alignment = 0;
1838                 break;
1839         case I915_TILING_Y:
1840                 /* Despite that we check this in framebuffer_init userspace can
1841                  * screw us over and change the tiling after the fact. Only
1842                  * pinned buffers can't change their tiling. */
1843                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1844                 return -EINVAL;
1845         default:
1846                 BUG();
1847         }
1848
1849         /* Note that the w/a also requires 64 PTE of padding following the
1850          * bo. We currently fill all unused PTE with the shadow page and so
1851          * we should always have valid PTE following the scanout preventing
1852          * the VT-d warning.
1853          */
1854         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1855                 alignment = 256 * 1024;
1856
1857         dev_priv->mm.interruptible = false;
1858         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1859         if (ret)
1860                 goto err_interruptible;
1861
1862         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863          * fence, whereas 965+ only requires a fence if using
1864          * framebuffer compression.  For simplicity, we always install
1865          * a fence as the cost is not that onerous.
1866          */
1867         ret = i915_gem_object_get_fence(obj);
1868         if (ret)
1869                 goto err_unpin;
1870
1871         i915_gem_object_pin_fence(obj);
1872
1873         dev_priv->mm.interruptible = true;
1874         return 0;
1875
1876 err_unpin:
1877         i915_gem_object_unpin(obj);
1878 err_interruptible:
1879         dev_priv->mm.interruptible = true;
1880         return ret;
1881 }
1882
1883 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1884 {
1885         i915_gem_object_unpin_fence(obj);
1886         i915_gem_object_unpin(obj);
1887 }
1888
1889 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890  * is assumed to be a power-of-two. */
1891 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1892                                              unsigned int tiling_mode,
1893                                              unsigned int cpp,
1894                                              unsigned int pitch)
1895 {
1896         if (tiling_mode != I915_TILING_NONE) {
1897                 unsigned int tile_rows, tiles;
1898
1899                 tile_rows = *y / 8;
1900                 *y %= 8;
1901
1902                 tiles = *x / (512/cpp);
1903                 *x %= 512/cpp;
1904
1905                 return tile_rows * pitch * 8 + tiles * 4096;
1906         } else {
1907                 unsigned int offset;
1908
1909                 offset = *y * pitch + *x * cpp;
1910                 *y = 0;
1911                 *x = (offset & 4095) / cpp;
1912                 return offset & -4096;
1913         }
1914 }
1915
1916 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1917                              int x, int y)
1918 {
1919         struct drm_device *dev = crtc->dev;
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922         struct intel_framebuffer *intel_fb;
1923         struct drm_i915_gem_object *obj;
1924         int plane = intel_crtc->plane;
1925         unsigned long linear_offset;
1926         u32 dspcntr;
1927         u32 reg;
1928
1929         switch (plane) {
1930         case 0:
1931         case 1:
1932                 break;
1933         default:
1934                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1935                 return -EINVAL;
1936         }
1937
1938         intel_fb = to_intel_framebuffer(fb);
1939         obj = intel_fb->obj;
1940
1941         reg = DSPCNTR(plane);
1942         dspcntr = I915_READ(reg);
1943         /* Mask out pixel format bits in case we change it */
1944         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1945         switch (fb->pixel_format) {
1946         case DRM_FORMAT_C8:
1947                 dspcntr |= DISPPLANE_8BPP;
1948                 break;
1949         case DRM_FORMAT_XRGB1555:
1950         case DRM_FORMAT_ARGB1555:
1951                 dspcntr |= DISPPLANE_BGRX555;
1952                 break;
1953         case DRM_FORMAT_RGB565:
1954                 dspcntr |= DISPPLANE_BGRX565;
1955                 break;
1956         case DRM_FORMAT_XRGB8888:
1957         case DRM_FORMAT_ARGB8888:
1958                 dspcntr |= DISPPLANE_BGRX888;
1959                 break;
1960         case DRM_FORMAT_XBGR8888:
1961         case DRM_FORMAT_ABGR8888:
1962                 dspcntr |= DISPPLANE_RGBX888;
1963                 break;
1964         case DRM_FORMAT_XRGB2101010:
1965         case DRM_FORMAT_ARGB2101010:
1966                 dspcntr |= DISPPLANE_BGRX101010;
1967                 break;
1968         case DRM_FORMAT_XBGR2101010:
1969         case DRM_FORMAT_ABGR2101010:
1970                 dspcntr |= DISPPLANE_RGBX101010;
1971                 break;
1972         default:
1973                 BUG();
1974         }
1975
1976         if (INTEL_INFO(dev)->gen >= 4) {
1977                 if (obj->tiling_mode != I915_TILING_NONE)
1978                         dspcntr |= DISPPLANE_TILED;
1979                 else
1980                         dspcntr &= ~DISPPLANE_TILED;
1981         }
1982
1983         if (IS_G4X(dev))
1984                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1985
1986         I915_WRITE(reg, dspcntr);
1987
1988         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1989
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 intel_crtc->dspaddr_offset =
1992                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1993                                                        fb->bits_per_pixel / 8,
1994                                                        fb->pitches[0]);
1995                 linear_offset -= intel_crtc->dspaddr_offset;
1996         } else {
1997                 intel_crtc->dspaddr_offset = linear_offset;
1998         }
1999
2000         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2002                       fb->pitches[0]);
2003         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2004         if (INTEL_INFO(dev)->gen >= 4) {
2005                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2006                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2007                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2009         } else
2010                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2011         POSTING_READ(reg);
2012
2013         return 0;
2014 }
2015
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017                                  struct drm_framebuffer *fb, int x, int y)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022         struct intel_framebuffer *intel_fb;
2023         struct drm_i915_gem_object *obj;
2024         int plane = intel_crtc->plane;
2025         unsigned long linear_offset;
2026         u32 dspcntr;
2027         u32 reg;
2028
2029         switch (plane) {
2030         case 0:
2031         case 1:
2032         case 2:
2033                 break;
2034         default:
2035                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2036                 return -EINVAL;
2037         }
2038
2039         intel_fb = to_intel_framebuffer(fb);
2040         obj = intel_fb->obj;
2041
2042         reg = DSPCNTR(plane);
2043         dspcntr = I915_READ(reg);
2044         /* Mask out pixel format bits in case we change it */
2045         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2046         switch (fb->pixel_format) {
2047         case DRM_FORMAT_C8:
2048                 dspcntr |= DISPPLANE_8BPP;
2049                 break;
2050         case DRM_FORMAT_RGB565:
2051                 dspcntr |= DISPPLANE_BGRX565;
2052                 break;
2053         case DRM_FORMAT_XRGB8888:
2054         case DRM_FORMAT_ARGB8888:
2055                 dspcntr |= DISPPLANE_BGRX888;
2056                 break;
2057         case DRM_FORMAT_XBGR8888:
2058         case DRM_FORMAT_ABGR8888:
2059                 dspcntr |= DISPPLANE_RGBX888;
2060                 break;
2061         case DRM_FORMAT_XRGB2101010:
2062         case DRM_FORMAT_ARGB2101010:
2063                 dspcntr |= DISPPLANE_BGRX101010;
2064                 break;
2065         case DRM_FORMAT_XBGR2101010:
2066         case DRM_FORMAT_ABGR2101010:
2067                 dspcntr |= DISPPLANE_RGBX101010;
2068                 break;
2069         default:
2070                 BUG();
2071         }
2072
2073         if (obj->tiling_mode != I915_TILING_NONE)
2074                 dspcntr |= DISPPLANE_TILED;
2075         else
2076                 dspcntr &= ~DISPPLANE_TILED;
2077
2078         /* must disable */
2079         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2084         intel_crtc->dspaddr_offset =
2085                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2086                                                fb->bits_per_pixel / 8,
2087                                                fb->pitches[0]);
2088         linear_offset -= intel_crtc->dspaddr_offset;
2089
2090         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2092                       fb->pitches[0]);
2093         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2094         I915_MODIFY_DISPBASE(DSPSURF(plane),
2095                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2096         if (IS_HASWELL(dev)) {
2097                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2098         } else {
2099                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2100                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2101         }
2102         POSTING_READ(reg);
2103
2104         return 0;
2105 }
2106
2107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2108 static int
2109 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110                            int x, int y, enum mode_set_atomic state)
2111 {
2112         struct drm_device *dev = crtc->dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115         if (dev_priv->display.disable_fbc)
2116                 dev_priv->display.disable_fbc(dev);
2117         intel_increase_pllclock(crtc);
2118
2119         return dev_priv->display.update_plane(crtc, fb, x, y);
2120 }
2121
2122 void intel_display_handle_reset(struct drm_device *dev)
2123 {
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         struct drm_crtc *crtc;
2126
2127         /*
2128          * Flips in the rings have been nuked by the reset,
2129          * so complete all pending flips so that user space
2130          * will get its events and not get stuck.
2131          *
2132          * Also update the base address of all primary
2133          * planes to the the last fb to make sure we're
2134          * showing the correct fb after a reset.
2135          *
2136          * Need to make two loops over the crtcs so that we
2137          * don't try to grab a crtc mutex before the
2138          * pending_flip_queue really got woken up.
2139          */
2140
2141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2142                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143                 enum plane plane = intel_crtc->plane;
2144
2145                 intel_prepare_page_flip(dev, plane);
2146                 intel_finish_page_flip_plane(dev, plane);
2147         }
2148
2149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151
2152                 mutex_lock(&crtc->mutex);
2153                 if (intel_crtc->active)
2154                         dev_priv->display.update_plane(crtc, crtc->fb,
2155                                                        crtc->x, crtc->y);
2156                 mutex_unlock(&crtc->mutex);
2157         }
2158 }
2159
2160 static int
2161 intel_finish_fb(struct drm_framebuffer *old_fb)
2162 {
2163         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2164         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2165         bool was_interruptible = dev_priv->mm.interruptible;
2166         int ret;
2167
2168         /* Big Hammer, we also need to ensure that any pending
2169          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170          * current scanout is retired before unpinning the old
2171          * framebuffer.
2172          *
2173          * This should only fail upon a hung GPU, in which case we
2174          * can safely continue.
2175          */
2176         dev_priv->mm.interruptible = false;
2177         ret = i915_gem_object_finish_gpu(obj);
2178         dev_priv->mm.interruptible = was_interruptible;
2179
2180         return ret;
2181 }
2182
2183 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2184 {
2185         struct drm_device *dev = crtc->dev;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188
2189         if (!dev->primary->master)
2190                 return;
2191
2192         master_priv = dev->primary->master->driver_priv;
2193         if (!master_priv->sarea_priv)
2194                 return;
2195
2196         switch (intel_crtc->pipe) {
2197         case 0:
2198                 master_priv->sarea_priv->pipeA_x = x;
2199                 master_priv->sarea_priv->pipeA_y = y;
2200                 break;
2201         case 1:
2202                 master_priv->sarea_priv->pipeB_x = x;
2203                 master_priv->sarea_priv->pipeB_y = y;
2204                 break;
2205         default:
2206                 break;
2207         }
2208 }
2209
2210 static int
2211 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2212                     struct drm_framebuffer *fb)
2213 {
2214         struct drm_device *dev = crtc->dev;
2215         struct drm_i915_private *dev_priv = dev->dev_private;
2216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217         struct drm_framebuffer *old_fb;
2218         int ret;
2219
2220         /* no fb bound */
2221         if (!fb) {
2222                 DRM_ERROR("No FB bound\n");
2223                 return 0;
2224         }
2225
2226         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2227                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228                           plane_name(intel_crtc->plane),
2229                           INTEL_INFO(dev)->num_pipes);
2230                 return -EINVAL;
2231         }
2232
2233         mutex_lock(&dev->struct_mutex);
2234         ret = intel_pin_and_fence_fb_obj(dev,
2235                                          to_intel_framebuffer(fb)->obj,
2236                                          NULL);
2237         if (ret != 0) {
2238                 mutex_unlock(&dev->struct_mutex);
2239                 DRM_ERROR("pin & fence failed\n");
2240                 return ret;
2241         }
2242
2243         /* Update pipe size and adjust fitter if needed */
2244         if (i915_fastboot) {
2245                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2246                            ((crtc->mode.hdisplay - 1) << 16) |
2247                            (crtc->mode.vdisplay - 1));
2248                 if (!intel_crtc->config.pch_pfit.size &&
2249                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2250                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2251                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2253                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2254                 }
2255         }
2256
2257         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2258         if (ret) {
2259                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2260                 mutex_unlock(&dev->struct_mutex);
2261                 DRM_ERROR("failed to update base address\n");
2262                 return ret;
2263         }
2264
2265         old_fb = crtc->fb;
2266         crtc->fb = fb;
2267         crtc->x = x;
2268         crtc->y = y;
2269
2270         if (old_fb) {
2271                 if (intel_crtc->active && old_fb != fb)
2272                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2273                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2274         }
2275
2276         intel_update_fbc(dev);
2277         intel_edp_psr_update(dev);
2278         mutex_unlock(&dev->struct_mutex);
2279
2280         intel_crtc_update_sarea_pos(crtc, x, y);
2281
2282         return 0;
2283 }
2284
2285 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290         int pipe = intel_crtc->pipe;
2291         u32 reg, temp;
2292
2293         /* enable normal train */
2294         reg = FDI_TX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (IS_IVYBRIDGE(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2302         }
2303         I915_WRITE(reg, temp);
2304
2305         reg = FDI_RX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         if (HAS_PCH_CPT(dev)) {
2308                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310         } else {
2311                 temp &= ~FDI_LINK_TRAIN_NONE;
2312                 temp |= FDI_LINK_TRAIN_NONE;
2313         }
2314         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316         /* wait one idle pattern time */
2317         POSTING_READ(reg);
2318         udelay(1000);
2319
2320         /* IVB wants error correction enabled */
2321         if (IS_IVYBRIDGE(dev))
2322                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323                            FDI_FE_ERRC_ENABLE);
2324 }
2325
2326 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2327 {
2328         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2329 }
2330
2331 static void ivb_modeset_global_resources(struct drm_device *dev)
2332 {
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *pipe_B_crtc =
2335                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2336         struct intel_crtc *pipe_C_crtc =
2337                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2338         uint32_t temp;
2339
2340         /*
2341          * When everything is off disable fdi C so that we could enable fdi B
2342          * with all lanes. Note that we don't care about enabled pipes without
2343          * an enabled pch encoder.
2344          */
2345         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2346             !pipe_has_enabled_pch(pipe_C_crtc)) {
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2348                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2349
2350                 temp = I915_READ(SOUTH_CHICKEN1);
2351                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2352                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2353                 I915_WRITE(SOUTH_CHICKEN1, temp);
2354         }
2355 }
2356
2357 /* The FDI link training functions for ILK/Ibexpeak. */
2358 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2359 {
2360         struct drm_device *dev = crtc->dev;
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2363         int pipe = intel_crtc->pipe;
2364         int plane = intel_crtc->plane;
2365         u32 reg, temp, tries;
2366
2367         /* FDI needs bits from pipe & plane first */
2368         assert_pipe_enabled(dev_priv, pipe);
2369         assert_plane_enabled(dev_priv, plane);
2370
2371         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2372            for train result */
2373         reg = FDI_RX_IMR(pipe);
2374         temp = I915_READ(reg);
2375         temp &= ~FDI_RX_SYMBOL_LOCK;
2376         temp &= ~FDI_RX_BIT_LOCK;
2377         I915_WRITE(reg, temp);
2378         I915_READ(reg);
2379         udelay(150);
2380
2381         /* enable CPU FDI TX and PCH FDI RX */
2382         reg = FDI_TX_CTL(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2385         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2386         temp &= ~FDI_LINK_TRAIN_NONE;
2387         temp |= FDI_LINK_TRAIN_PATTERN_1;
2388         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2389
2390         reg = FDI_RX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         temp &= ~FDI_LINK_TRAIN_NONE;
2393         temp |= FDI_LINK_TRAIN_PATTERN_1;
2394         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2395
2396         POSTING_READ(reg);
2397         udelay(150);
2398
2399         /* Ironlake workaround, enable clock pointer after FDI enable*/
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2401         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2402                    FDI_RX_PHASE_SYNC_POINTER_EN);
2403
2404         reg = FDI_RX_IIR(pipe);
2405         for (tries = 0; tries < 5; tries++) {
2406                 temp = I915_READ(reg);
2407                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409                 if ((temp & FDI_RX_BIT_LOCK)) {
2410                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2411                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2412                         break;
2413                 }
2414         }
2415         if (tries == 5)
2416                 DRM_ERROR("FDI train 1 fail!\n");
2417
2418         /* Train 2 */
2419         reg = FDI_TX_CTL(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_LINK_TRAIN_NONE;
2422         temp |= FDI_LINK_TRAIN_PATTERN_2;
2423         I915_WRITE(reg, temp);
2424
2425         reg = FDI_RX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2;
2429         I915_WRITE(reg, temp);
2430
2431         POSTING_READ(reg);
2432         udelay(150);
2433
2434         reg = FDI_RX_IIR(pipe);
2435         for (tries = 0; tries < 5; tries++) {
2436                 temp = I915_READ(reg);
2437                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439                 if (temp & FDI_RX_SYMBOL_LOCK) {
2440                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2441                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2442                         break;
2443                 }
2444         }
2445         if (tries == 5)
2446                 DRM_ERROR("FDI train 2 fail!\n");
2447
2448         DRM_DEBUG_KMS("FDI train done\n");
2449
2450 }
2451
2452 static const int snb_b_fdi_train_param[] = {
2453         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2454         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2455         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2456         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2457 };
2458
2459 /* The FDI link training functions for SNB/Cougarpoint. */
2460 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461 {
2462         struct drm_device *dev = crtc->dev;
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465         int pipe = intel_crtc->pipe;
2466         u32 reg, temp, i, retry;
2467
2468         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469            for train result */
2470         reg = FDI_RX_IMR(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_RX_SYMBOL_LOCK;
2473         temp &= ~FDI_RX_BIT_LOCK;
2474         I915_WRITE(reg, temp);
2475
2476         POSTING_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487         /* SNB-B */
2488         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2490
2491         I915_WRITE(FDI_RX_MISC(pipe),
2492                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2493
2494         reg = FDI_RX_CTL(pipe);
2495         temp = I915_READ(reg);
2496         if (HAS_PCH_CPT(dev)) {
2497                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2499         } else {
2500                 temp &= ~FDI_LINK_TRAIN_NONE;
2501                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         }
2503         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2504
2505         POSTING_READ(reg);
2506         udelay(150);
2507
2508         for (i = 0; i < 4; i++) {
2509                 reg = FDI_TX_CTL(pipe);
2510                 temp = I915_READ(reg);
2511                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512                 temp |= snb_b_fdi_train_param[i];
2513                 I915_WRITE(reg, temp);
2514
2515                 POSTING_READ(reg);
2516                 udelay(500);
2517
2518                 for (retry = 0; retry < 5; retry++) {
2519                         reg = FDI_RX_IIR(pipe);
2520                         temp = I915_READ(reg);
2521                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522                         if (temp & FDI_RX_BIT_LOCK) {
2523                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525                                 break;
2526                         }
2527                         udelay(50);
2528                 }
2529                 if (retry < 5)
2530                         break;
2531         }
2532         if (i == 4)
2533                 DRM_ERROR("FDI train 1 fail!\n");
2534
2535         /* Train 2 */
2536         reg = FDI_TX_CTL(pipe);
2537         temp = I915_READ(reg);
2538         temp &= ~FDI_LINK_TRAIN_NONE;
2539         temp |= FDI_LINK_TRAIN_PATTERN_2;
2540         if (IS_GEN6(dev)) {
2541                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542                 /* SNB-B */
2543                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544         }
2545         I915_WRITE(reg, temp);
2546
2547         reg = FDI_RX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         if (HAS_PCH_CPT(dev)) {
2550                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552         } else {
2553                 temp &= ~FDI_LINK_TRAIN_NONE;
2554                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555         }
2556         I915_WRITE(reg, temp);
2557
2558         POSTING_READ(reg);
2559         udelay(150);
2560
2561         for (i = 0; i < 4; i++) {
2562                 reg = FDI_TX_CTL(pipe);
2563                 temp = I915_READ(reg);
2564                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565                 temp |= snb_b_fdi_train_param[i];
2566                 I915_WRITE(reg, temp);
2567
2568                 POSTING_READ(reg);
2569                 udelay(500);
2570
2571                 for (retry = 0; retry < 5; retry++) {
2572                         reg = FDI_RX_IIR(pipe);
2573                         temp = I915_READ(reg);
2574                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575                         if (temp & FDI_RX_SYMBOL_LOCK) {
2576                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578                                 break;
2579                         }
2580                         udelay(50);
2581                 }
2582                 if (retry < 5)
2583                         break;
2584         }
2585         if (i == 4)
2586                 DRM_ERROR("FDI train 2 fail!\n");
2587
2588         DRM_DEBUG_KMS("FDI train done.\n");
2589 }
2590
2591 /* Manual link training for Ivy Bridge A0 parts */
2592 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         int pipe = intel_crtc->pipe;
2598         u32 reg, temp, i;
2599
2600         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601            for train result */
2602         reg = FDI_RX_IMR(pipe);
2603         temp = I915_READ(reg);
2604         temp &= ~FDI_RX_SYMBOL_LOCK;
2605         temp &= ~FDI_RX_BIT_LOCK;
2606         I915_WRITE(reg, temp);
2607
2608         POSTING_READ(reg);
2609         udelay(150);
2610
2611         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2612                       I915_READ(FDI_RX_IIR(pipe)));
2613
2614         /* enable CPU FDI TX and PCH FDI RX */
2615         reg = FDI_TX_CTL(pipe);
2616         temp = I915_READ(reg);
2617         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2618         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2619         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2620         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2621         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623         temp |= FDI_COMPOSITE_SYNC;
2624         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2625
2626         I915_WRITE(FDI_RX_MISC(pipe),
2627                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2628
2629         reg = FDI_RX_CTL(pipe);
2630         temp = I915_READ(reg);
2631         temp &= ~FDI_LINK_TRAIN_AUTO;
2632         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2634         temp |= FDI_COMPOSITE_SYNC;
2635         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2636
2637         POSTING_READ(reg);
2638         udelay(150);
2639
2640         for (i = 0; i < 4; i++) {
2641                 reg = FDI_TX_CTL(pipe);
2642                 temp = I915_READ(reg);
2643                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644                 temp |= snb_b_fdi_train_param[i];
2645                 I915_WRITE(reg, temp);
2646
2647                 POSTING_READ(reg);
2648                 udelay(500);
2649
2650                 reg = FDI_RX_IIR(pipe);
2651                 temp = I915_READ(reg);
2652                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654                 if (temp & FDI_RX_BIT_LOCK ||
2655                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2656                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 1 fail!\n");
2663
2664         /* Train 2 */
2665         reg = FDI_TX_CTL(pipe);
2666         temp = I915_READ(reg);
2667         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2668         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2669         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2671         I915_WRITE(reg, temp);
2672
2673         reg = FDI_RX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2677         I915_WRITE(reg, temp);
2678
2679         POSTING_READ(reg);
2680         udelay(150);
2681
2682         for (i = 0; i < 4; i++) {
2683                 reg = FDI_TX_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686                 temp |= snb_b_fdi_train_param[i];
2687                 I915_WRITE(reg, temp);
2688
2689                 POSTING_READ(reg);
2690                 udelay(500);
2691
2692                 reg = FDI_RX_IIR(pipe);
2693                 temp = I915_READ(reg);
2694                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695
2696                 if (temp & FDI_RX_SYMBOL_LOCK) {
2697                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2698                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2699                         break;
2700                 }
2701         }
2702         if (i == 4)
2703                 DRM_ERROR("FDI train 2 fail!\n");
2704
2705         DRM_DEBUG_KMS("FDI train done.\n");
2706 }
2707
2708 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2709 {
2710         struct drm_device *dev = intel_crtc->base.dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         int pipe = intel_crtc->pipe;
2713         u32 reg, temp;
2714
2715
2716         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2717         reg = FDI_RX_CTL(pipe);
2718         temp = I915_READ(reg);
2719         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2720         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2721         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2722         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2723
2724         POSTING_READ(reg);
2725         udelay(200);
2726
2727         /* Switch from Rawclk to PCDclk */
2728         temp = I915_READ(reg);
2729         I915_WRITE(reg, temp | FDI_PCDCLK);
2730
2731         POSTING_READ(reg);
2732         udelay(200);
2733
2734         /* Enable CPU FDI TX PLL, always on for Ironlake */
2735         reg = FDI_TX_CTL(pipe);
2736         temp = I915_READ(reg);
2737         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2738                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2739
2740                 POSTING_READ(reg);
2741                 udelay(100);
2742         }
2743 }
2744
2745 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2746 {
2747         struct drm_device *dev = intel_crtc->base.dev;
2748         struct drm_i915_private *dev_priv = dev->dev_private;
2749         int pipe = intel_crtc->pipe;
2750         u32 reg, temp;
2751
2752         /* Switch from PCDclk to Rawclk */
2753         reg = FDI_RX_CTL(pipe);
2754         temp = I915_READ(reg);
2755         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2756
2757         /* Disable CPU FDI TX PLL */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2761
2762         POSTING_READ(reg);
2763         udelay(100);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2768
2769         /* Wait for the clocks to turn off. */
2770         POSTING_READ(reg);
2771         udelay(100);
2772 }
2773
2774 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2779         int pipe = intel_crtc->pipe;
2780         u32 reg, temp;
2781
2782         /* disable CPU FDI tx and PCH FDI rx */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2786         POSTING_READ(reg);
2787
2788         reg = FDI_RX_CTL(pipe);
2789         temp = I915_READ(reg);
2790         temp &= ~(0x7 << 16);
2791         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2792         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2793
2794         POSTING_READ(reg);
2795         udelay(100);
2796
2797         /* Ironlake workaround, disable clock pointer after downing FDI */
2798         if (HAS_PCH_IBX(dev)) {
2799                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2800         }
2801
2802         /* still set train pattern 1 */
2803         reg = FDI_TX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         temp &= ~FDI_LINK_TRAIN_NONE;
2806         temp |= FDI_LINK_TRAIN_PATTERN_1;
2807         I915_WRITE(reg, temp);
2808
2809         reg = FDI_RX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         if (HAS_PCH_CPT(dev)) {
2812                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2814         } else {
2815                 temp &= ~FDI_LINK_TRAIN_NONE;
2816                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2817         }
2818         /* BPC in FDI rx is consistent with that in PIPECONF */
2819         temp &= ~(0x07 << 16);
2820         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2821         I915_WRITE(reg, temp);
2822
2823         POSTING_READ(reg);
2824         udelay(100);
2825 }
2826
2827 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2828 {
2829         struct drm_device *dev = crtc->dev;
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832         unsigned long flags;
2833         bool pending;
2834
2835         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2836             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2837                 return false;
2838
2839         spin_lock_irqsave(&dev->event_lock, flags);
2840         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2841         spin_unlock_irqrestore(&dev->event_lock, flags);
2842
2843         return pending;
2844 }
2845
2846 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2847 {
2848         struct drm_device *dev = crtc->dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850
2851         if (crtc->fb == NULL)
2852                 return;
2853
2854         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2855
2856         wait_event(dev_priv->pending_flip_queue,
2857                    !intel_crtc_has_pending_flip(crtc));
2858
2859         mutex_lock(&dev->struct_mutex);
2860         intel_finish_fb(crtc->fb);
2861         mutex_unlock(&dev->struct_mutex);
2862 }
2863
2864 /* Program iCLKIP clock to the desired frequency */
2865 static void lpt_program_iclkip(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2870         u32 temp;
2871
2872         mutex_lock(&dev_priv->dpio_lock);
2873
2874         /* It is necessary to ungate the pixclk gate prior to programming
2875          * the divisors, and gate it back when it is done.
2876          */
2877         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2878
2879         /* Disable SSCCTL */
2880         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2881                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2882                                 SBI_SSCCTL_DISABLE,
2883                         SBI_ICLK);
2884
2885         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2886         if (crtc->mode.clock == 20000) {
2887                 auxdiv = 1;
2888                 divsel = 0x41;
2889                 phaseinc = 0x20;
2890         } else {
2891                 /* The iCLK virtual clock root frequency is in MHz,
2892                  * but the crtc->mode.clock in in KHz. To get the divisors,
2893                  * it is necessary to divide one by another, so we
2894                  * convert the virtual clock precision to KHz here for higher
2895                  * precision.
2896                  */
2897                 u32 iclk_virtual_root_freq = 172800 * 1000;
2898                 u32 iclk_pi_range = 64;
2899                 u32 desired_divisor, msb_divisor_value, pi_value;
2900
2901                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2902                 msb_divisor_value = desired_divisor / iclk_pi_range;
2903                 pi_value = desired_divisor % iclk_pi_range;
2904
2905                 auxdiv = 0;
2906                 divsel = msb_divisor_value - 2;
2907                 phaseinc = pi_value;
2908         }
2909
2910         /* This should not happen with any sane values */
2911         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2912                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2913         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2914                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2915
2916         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2917                         crtc->mode.clock,
2918                         auxdiv,
2919                         divsel,
2920                         phasedir,
2921                         phaseinc);
2922
2923         /* Program SSCDIVINTPHASE6 */
2924         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2925         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2926         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2927         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2928         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2929         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2930         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2931         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2932
2933         /* Program SSCAUXDIV */
2934         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2935         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2936         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2937         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2938
2939         /* Enable modulator and associated divider */
2940         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2941         temp &= ~SBI_SSCCTL_DISABLE;
2942         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2943
2944         /* Wait for initialization time */
2945         udelay(24);
2946
2947         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948
2949         mutex_unlock(&dev_priv->dpio_lock);
2950 }
2951
2952 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2953                                                 enum pipe pch_transcoder)
2954 {
2955         struct drm_device *dev = crtc->base.dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2958
2959         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2960                    I915_READ(HTOTAL(cpu_transcoder)));
2961         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2962                    I915_READ(HBLANK(cpu_transcoder)));
2963         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2964                    I915_READ(HSYNC(cpu_transcoder)));
2965
2966         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2967                    I915_READ(VTOTAL(cpu_transcoder)));
2968         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2969                    I915_READ(VBLANK(cpu_transcoder)));
2970         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2971                    I915_READ(VSYNC(cpu_transcoder)));
2972         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2973                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2974 }
2975
2976 /*
2977  * Enable PCH resources required for PCH ports:
2978  *   - PCH PLLs
2979  *   - FDI training & RX/TX
2980  *   - update transcoder timings
2981  *   - DP transcoding bits
2982  *   - transcoder
2983  */
2984 static void ironlake_pch_enable(struct drm_crtc *crtc)
2985 {
2986         struct drm_device *dev = crtc->dev;
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2989         int pipe = intel_crtc->pipe;
2990         u32 reg, temp;
2991
2992         assert_pch_transcoder_disabled(dev_priv, pipe);
2993
2994         /* Write the TU size bits before fdi link training, so that error
2995          * detection works. */
2996         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2997                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2998
2999         /* For PCH output, training FDI link */
3000         dev_priv->display.fdi_link_train(crtc);
3001
3002         /* We need to program the right clock selection before writing the pixel
3003          * mutliplier into the DPLL. */
3004         if (HAS_PCH_CPT(dev)) {
3005                 u32 sel;
3006
3007                 temp = I915_READ(PCH_DPLL_SEL);
3008                 temp |= TRANS_DPLL_ENABLE(pipe);
3009                 sel = TRANS_DPLLB_SEL(pipe);
3010                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3011                         temp |= sel;
3012                 else
3013                         temp &= ~sel;
3014                 I915_WRITE(PCH_DPLL_SEL, temp);
3015         }
3016
3017         /* XXX: pch pll's can be enabled any time before we enable the PCH
3018          * transcoder, and we actually should do this to not upset any PCH
3019          * transcoder that already use the clock when we share it.
3020          *
3021          * Note that enable_shared_dpll tries to do the right thing, but
3022          * get_shared_dpll unconditionally resets the pll - we need that to have
3023          * the right LVDS enable sequence. */
3024         ironlake_enable_shared_dpll(intel_crtc);
3025
3026         /* set transcoder timing, panel must allow it */
3027         assert_panel_unlocked(dev_priv, pipe);
3028         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3029
3030         intel_fdi_normal_train(crtc);
3031
3032         /* For PCH DP, enable TRANS_DP_CTL */
3033         if (HAS_PCH_CPT(dev) &&
3034             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3035              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3036                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3037                 reg = TRANS_DP_CTL(pipe);
3038                 temp = I915_READ(reg);
3039                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3040                           TRANS_DP_SYNC_MASK |
3041                           TRANS_DP_BPC_MASK);
3042                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3043                          TRANS_DP_ENH_FRAMING);
3044                 temp |= bpc << 9; /* same format but at 11:9 */
3045
3046                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3047                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3048                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3049                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3050
3051                 switch (intel_trans_dp_port_sel(crtc)) {
3052                 case PCH_DP_B:
3053                         temp |= TRANS_DP_PORT_SEL_B;
3054                         break;
3055                 case PCH_DP_C:
3056                         temp |= TRANS_DP_PORT_SEL_C;
3057                         break;
3058                 case PCH_DP_D:
3059                         temp |= TRANS_DP_PORT_SEL_D;
3060                         break;
3061                 default:
3062                         BUG();
3063                 }
3064
3065                 I915_WRITE(reg, temp);
3066         }
3067
3068         ironlake_enable_pch_transcoder(dev_priv, pipe);
3069 }
3070
3071 static void lpt_pch_enable(struct drm_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3077
3078         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3079
3080         lpt_program_iclkip(crtc);
3081
3082         /* Set transcoder timing. */
3083         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3084
3085         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3086 }
3087
3088 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3089 {
3090         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3091
3092         if (pll == NULL)
3093                 return;
3094
3095         if (pll->refcount == 0) {
3096                 WARN(1, "bad %s refcount\n", pll->name);
3097                 return;
3098         }
3099
3100         if (--pll->refcount == 0) {
3101                 WARN_ON(pll->on);
3102                 WARN_ON(pll->active);
3103         }
3104
3105         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3106 }
3107
3108 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3109 {
3110         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3111         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3112         enum intel_dpll_id i;
3113
3114         if (pll) {
3115                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3116                               crtc->base.base.id, pll->name);
3117                 intel_put_shared_dpll(crtc);
3118         }
3119
3120         if (HAS_PCH_IBX(dev_priv->dev)) {
3121                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3122                 i = (enum intel_dpll_id) crtc->pipe;
3123                 pll = &dev_priv->shared_dplls[i];
3124
3125                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3126                               crtc->base.base.id, pll->name);
3127
3128                 goto found;
3129         }
3130
3131         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3132                 pll = &dev_priv->shared_dplls[i];
3133
3134                 /* Only want to check enabled timings first */
3135                 if (pll->refcount == 0)
3136                         continue;
3137
3138                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3139                            sizeof(pll->hw_state)) == 0) {
3140                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3141                                       crtc->base.base.id,
3142                                       pll->name, pll->refcount, pll->active);
3143
3144                         goto found;
3145                 }
3146         }
3147
3148         /* Ok no matching timings, maybe there's a free one? */
3149         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3150                 pll = &dev_priv->shared_dplls[i];
3151                 if (pll->refcount == 0) {
3152                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3153                                       crtc->base.base.id, pll->name);
3154                         goto found;
3155                 }
3156         }
3157
3158         return NULL;
3159
3160 found:
3161         crtc->config.shared_dpll = i;
3162         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3163                          pipe_name(crtc->pipe));
3164
3165         if (pll->active == 0) {
3166                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3167                        sizeof(pll->hw_state));
3168
3169                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3170                 WARN_ON(pll->on);
3171                 assert_shared_dpll_disabled(dev_priv, pll);
3172
3173                 pll->mode_set(dev_priv, pll);
3174         }
3175         pll->refcount++;
3176
3177         return pll;
3178 }
3179
3180 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3181 {
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         int dslreg = PIPEDSL(pipe);
3184         u32 temp;
3185
3186         temp = I915_READ(dslreg);
3187         udelay(500);
3188         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3189                 if (wait_for(I915_READ(dslreg) != temp, 5))
3190                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3191         }
3192 }
3193
3194 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3195 {
3196         struct drm_device *dev = crtc->base.dev;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         int pipe = crtc->pipe;
3199
3200         if (crtc->config.pch_pfit.size) {
3201                 /* Force use of hard-coded filter coefficients
3202                  * as some pre-programmed values are broken,
3203                  * e.g. x201.
3204                  */
3205                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3206                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3207                                                  PF_PIPE_SEL_IVB(pipe));
3208                 else
3209                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3210                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3211                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3212         }
3213 }
3214
3215 static void intel_enable_planes(struct drm_crtc *crtc)
3216 {
3217         struct drm_device *dev = crtc->dev;
3218         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3219         struct intel_plane *intel_plane;
3220
3221         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3222                 if (intel_plane->pipe == pipe)
3223                         intel_plane_restore(&intel_plane->base);
3224 }
3225
3226 static void intel_disable_planes(struct drm_crtc *crtc)
3227 {
3228         struct drm_device *dev = crtc->dev;
3229         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3230         struct intel_plane *intel_plane;
3231
3232         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3233                 if (intel_plane->pipe == pipe)
3234                         intel_plane_disable(&intel_plane->base);
3235 }
3236
3237 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         struct intel_encoder *encoder;
3243         int pipe = intel_crtc->pipe;
3244         int plane = intel_crtc->plane;
3245
3246         WARN_ON(!crtc->enabled);
3247
3248         if (intel_crtc->active)
3249                 return;
3250
3251         intel_crtc->active = true;
3252
3253         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3254         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3255
3256         intel_update_watermarks(dev);
3257
3258         for_each_encoder_on_crtc(dev, crtc, encoder)
3259                 if (encoder->pre_enable)
3260                         encoder->pre_enable(encoder);
3261
3262         if (intel_crtc->config.has_pch_encoder) {
3263                 /* Note: FDI PLL enabling _must_ be done before we enable the
3264                  * cpu pipes, hence this is separate from all the other fdi/pch
3265                  * enabling. */
3266                 ironlake_fdi_pll_enable(intel_crtc);
3267         } else {
3268                 assert_fdi_tx_disabled(dev_priv, pipe);
3269                 assert_fdi_rx_disabled(dev_priv, pipe);
3270         }
3271
3272         ironlake_pfit_enable(intel_crtc);
3273
3274         /*
3275          * On ILK+ LUT must be loaded before the pipe is running but with
3276          * clocks enabled
3277          */
3278         intel_crtc_load_lut(crtc);
3279
3280         intel_enable_pipe(dev_priv, pipe,
3281                           intel_crtc->config.has_pch_encoder);
3282         intel_enable_plane(dev_priv, plane, pipe);
3283         intel_enable_planes(crtc);
3284         intel_crtc_update_cursor(crtc, true);
3285
3286         if (intel_crtc->config.has_pch_encoder)
3287                 ironlake_pch_enable(crtc);
3288
3289         mutex_lock(&dev->struct_mutex);
3290         intel_update_fbc(dev);
3291         mutex_unlock(&dev->struct_mutex);
3292
3293         for_each_encoder_on_crtc(dev, crtc, encoder)
3294                 encoder->enable(encoder);
3295
3296         if (HAS_PCH_CPT(dev))
3297                 cpt_verify_modeset(dev, intel_crtc->pipe);
3298
3299         /*
3300          * There seems to be a race in PCH platform hw (at least on some
3301          * outputs) where an enabled pipe still completes any pageflip right
3302          * away (as if the pipe is off) instead of waiting for vblank. As soon
3303          * as the first vblank happend, everything works as expected. Hence just
3304          * wait for one vblank before returning to avoid strange things
3305          * happening.
3306          */
3307         intel_wait_for_vblank(dev, intel_crtc->pipe);
3308 }
3309
3310 /* IPS only exists on ULT machines and is tied to pipe A. */
3311 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3312 {
3313         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3314 }
3315
3316 static void hsw_enable_ips(struct intel_crtc *crtc)
3317 {
3318         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3319
3320         if (!crtc->config.ips_enabled)
3321                 return;
3322
3323         /* We can only enable IPS after we enable a plane and wait for a vblank.
3324          * We guarantee that the plane is enabled by calling intel_enable_ips
3325          * only after intel_enable_plane. And intel_enable_plane already waits
3326          * for a vblank, so all we need to do here is to enable the IPS bit. */
3327         assert_plane_enabled(dev_priv, crtc->plane);
3328         I915_WRITE(IPS_CTL, IPS_ENABLE);
3329 }
3330
3331 static void hsw_disable_ips(struct intel_crtc *crtc)
3332 {
3333         struct drm_device *dev = crtc->base.dev;
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336         if (!crtc->config.ips_enabled)
3337                 return;
3338
3339         assert_plane_enabled(dev_priv, crtc->plane);
3340         I915_WRITE(IPS_CTL, 0);
3341
3342         /* We need to wait for a vblank before we can disable the plane. */
3343         intel_wait_for_vblank(dev, crtc->pipe);
3344 }
3345
3346 static void haswell_crtc_enable(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         struct intel_encoder *encoder;
3352         int pipe = intel_crtc->pipe;
3353         int plane = intel_crtc->plane;
3354
3355         WARN_ON(!crtc->enabled);
3356
3357         if (intel_crtc->active)
3358                 return;
3359
3360         intel_crtc->active = true;
3361
3362         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3363         if (intel_crtc->config.has_pch_encoder)
3364                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3365
3366         intel_update_watermarks(dev);
3367
3368         if (intel_crtc->config.has_pch_encoder)
3369                 dev_priv->display.fdi_link_train(crtc);
3370
3371         for_each_encoder_on_crtc(dev, crtc, encoder)
3372                 if (encoder->pre_enable)
3373                         encoder->pre_enable(encoder);
3374
3375         intel_ddi_enable_pipe_clock(intel_crtc);
3376
3377         ironlake_pfit_enable(intel_crtc);
3378
3379         /*
3380          * On ILK+ LUT must be loaded before the pipe is running but with
3381          * clocks enabled
3382          */
3383         intel_crtc_load_lut(crtc);
3384
3385         intel_ddi_set_pipe_settings(crtc);
3386         intel_ddi_enable_transcoder_func(crtc);
3387
3388         intel_enable_pipe(dev_priv, pipe,
3389                           intel_crtc->config.has_pch_encoder);
3390         intel_enable_plane(dev_priv, plane, pipe);
3391         intel_enable_planes(crtc);
3392         intel_crtc_update_cursor(crtc, true);
3393
3394         hsw_enable_ips(intel_crtc);
3395
3396         if (intel_crtc->config.has_pch_encoder)
3397                 lpt_pch_enable(crtc);
3398
3399         mutex_lock(&dev->struct_mutex);
3400         intel_update_fbc(dev);
3401         mutex_unlock(&dev->struct_mutex);
3402
3403         for_each_encoder_on_crtc(dev, crtc, encoder)
3404                 encoder->enable(encoder);
3405
3406         /*
3407          * There seems to be a race in PCH platform hw (at least on some
3408          * outputs) where an enabled pipe still completes any pageflip right
3409          * away (as if the pipe is off) instead of waiting for vblank. As soon
3410          * as the first vblank happend, everything works as expected. Hence just
3411          * wait for one vblank before returning to avoid strange things
3412          * happening.
3413          */
3414         intel_wait_for_vblank(dev, intel_crtc->pipe);
3415 }
3416
3417 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3418 {
3419         struct drm_device *dev = crtc->base.dev;
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         int pipe = crtc->pipe;
3422
3423         /* To avoid upsetting the power well on haswell only disable the pfit if
3424          * it's in use. The hw state code will make sure we get this right. */
3425         if (crtc->config.pch_pfit.size) {
3426                 I915_WRITE(PF_CTL(pipe), 0);
3427                 I915_WRITE(PF_WIN_POS(pipe), 0);
3428                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3429         }
3430 }
3431
3432 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3433 {
3434         struct drm_device *dev = crtc->dev;
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437         struct intel_encoder *encoder;
3438         int pipe = intel_crtc->pipe;
3439         int plane = intel_crtc->plane;
3440         u32 reg, temp;
3441
3442
3443         if (!intel_crtc->active)
3444                 return;
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 encoder->disable(encoder);
3448
3449         intel_crtc_wait_for_pending_flips(crtc);
3450         drm_vblank_off(dev, pipe);
3451
3452         if (dev_priv->fbc.plane == plane)
3453                 intel_disable_fbc(dev);
3454
3455         intel_crtc_update_cursor(crtc, false);
3456         intel_disable_planes(crtc);
3457         intel_disable_plane(dev_priv, plane, pipe);
3458
3459         if (intel_crtc->config.has_pch_encoder)
3460                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3461
3462         intel_disable_pipe(dev_priv, pipe);
3463
3464         ironlake_pfit_disable(intel_crtc);
3465
3466         for_each_encoder_on_crtc(dev, crtc, encoder)
3467                 if (encoder->post_disable)
3468                         encoder->post_disable(encoder);
3469
3470         if (intel_crtc->config.has_pch_encoder) {
3471                 ironlake_fdi_disable(crtc);
3472
3473                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3474                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3475
3476                 if (HAS_PCH_CPT(dev)) {
3477                         /* disable TRANS_DP_CTL */
3478                         reg = TRANS_DP_CTL(pipe);
3479                         temp = I915_READ(reg);
3480                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3481                                   TRANS_DP_PORT_SEL_MASK);
3482                         temp |= TRANS_DP_PORT_SEL_NONE;
3483                         I915_WRITE(reg, temp);
3484
3485                         /* disable DPLL_SEL */
3486                         temp = I915_READ(PCH_DPLL_SEL);
3487                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3488                         I915_WRITE(PCH_DPLL_SEL, temp);
3489                 }
3490
3491                 /* disable PCH DPLL */
3492                 intel_disable_shared_dpll(intel_crtc);
3493
3494                 ironlake_fdi_pll_disable(intel_crtc);
3495         }
3496
3497         intel_crtc->active = false;
3498         intel_update_watermarks(dev);
3499
3500         mutex_lock(&dev->struct_mutex);
3501         intel_update_fbc(dev);
3502         mutex_unlock(&dev->struct_mutex);
3503 }
3504
3505 static void haswell_crtc_disable(struct drm_crtc *crtc)
3506 {
3507         struct drm_device *dev = crtc->dev;
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510         struct intel_encoder *encoder;
3511         int pipe = intel_crtc->pipe;
3512         int plane = intel_crtc->plane;
3513         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3514
3515         if (!intel_crtc->active)
3516                 return;
3517
3518         for_each_encoder_on_crtc(dev, crtc, encoder)
3519                 encoder->disable(encoder);
3520
3521         intel_crtc_wait_for_pending_flips(crtc);
3522         drm_vblank_off(dev, pipe);
3523
3524         /* FBC must be disabled before disabling the plane on HSW. */
3525         if (dev_priv->fbc.plane == plane)
3526                 intel_disable_fbc(dev);
3527
3528         hsw_disable_ips(intel_crtc);
3529
3530         intel_crtc_update_cursor(crtc, false);
3531         intel_disable_planes(crtc);
3532         intel_disable_plane(dev_priv, plane, pipe);
3533
3534         if (intel_crtc->config.has_pch_encoder)
3535                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536         intel_disable_pipe(dev_priv, pipe);
3537
3538         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539
3540         ironlake_pfit_disable(intel_crtc);
3541
3542         intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         if (intel_crtc->config.has_pch_encoder) {
3549                 lpt_disable_pch_transcoder(dev_priv);
3550                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551                 intel_ddi_fdi_disable(crtc);
3552         }
3553
3554         intel_crtc->active = false;
3555         intel_update_watermarks(dev);
3556
3557         mutex_lock(&dev->struct_mutex);
3558         intel_update_fbc(dev);
3559         mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565         intel_put_shared_dpll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570         intel_ddi_put_crtc_pll(crtc);
3571 }
3572
3573 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3574 {
3575         if (!enable && intel_crtc->overlay) {
3576                 struct drm_device *dev = intel_crtc->base.dev;
3577                 struct drm_i915_private *dev_priv = dev->dev_private;
3578
3579                 mutex_lock(&dev->struct_mutex);
3580                 dev_priv->mm.interruptible = false;
3581                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3582                 dev_priv->mm.interruptible = true;
3583                 mutex_unlock(&dev->struct_mutex);
3584         }
3585
3586         /* Let userspace switch the overlay on again. In most cases userspace
3587          * has to recompute where to put it anyway.
3588          */
3589 }
3590
3591 /**
3592  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593  * cursor plane briefly if not already running after enabling the display
3594  * plane.
3595  * This workaround avoids occasional blank screens when self refresh is
3596  * enabled.
3597  */
3598 static void
3599 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3600 {
3601         u32 cntl = I915_READ(CURCNTR(pipe));
3602
3603         if ((cntl & CURSOR_MODE) == 0) {
3604                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3605
3606                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3607                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3608                 intel_wait_for_vblank(dev_priv->dev, pipe);
3609                 I915_WRITE(CURCNTR(pipe), cntl);
3610                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3611                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3612         }
3613 }
3614
3615 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3616 {
3617         struct drm_device *dev = crtc->base.dev;
3618         struct drm_i915_private *dev_priv = dev->dev_private;
3619         struct intel_crtc_config *pipe_config = &crtc->config;
3620
3621         if (!crtc->config.gmch_pfit.control)
3622                 return;
3623
3624         /*
3625          * The panel fitter should only be adjusted whilst the pipe is disabled,
3626          * according to register description and PRM.
3627          */
3628         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3629         assert_pipe_disabled(dev_priv, crtc->pipe);
3630
3631         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3632         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3633
3634         /* Border color in case we don't scale up to the full screen. Black by
3635          * default, change to something else for debugging. */
3636         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3637 }
3638
3639 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         struct intel_encoder *encoder;
3645         int pipe = intel_crtc->pipe;
3646         int plane = intel_crtc->plane;
3647
3648         WARN_ON(!crtc->enabled);
3649
3650         if (intel_crtc->active)
3651                 return;
3652
3653         intel_crtc->active = true;
3654         intel_update_watermarks(dev);
3655
3656         mutex_lock(&dev_priv->dpio_lock);
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 if (encoder->pre_pll_enable)
3660                         encoder->pre_pll_enable(encoder);
3661
3662         vlv_enable_pll(intel_crtc);
3663
3664         for_each_encoder_on_crtc(dev, crtc, encoder)
3665                 if (encoder->pre_enable)
3666                         encoder->pre_enable(encoder);
3667
3668         /* VLV wants encoder enabling _before_ the pipe is up. */
3669         for_each_encoder_on_crtc(dev, crtc, encoder)
3670                 encoder->enable(encoder);
3671
3672         i9xx_pfit_enable(intel_crtc);
3673
3674         intel_crtc_load_lut(crtc);
3675
3676         intel_enable_pipe(dev_priv, pipe, false);
3677         intel_enable_plane(dev_priv, plane, pipe);
3678         intel_enable_planes(crtc);
3679         intel_crtc_update_cursor(crtc, true);
3680
3681         intel_update_fbc(dev);
3682
3683         mutex_unlock(&dev_priv->dpio_lock);
3684 }
3685
3686 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3687 {
3688         struct drm_device *dev = crtc->dev;
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3691         struct intel_encoder *encoder;
3692         int pipe = intel_crtc->pipe;
3693         int plane = intel_crtc->plane;
3694
3695         WARN_ON(!crtc->enabled);
3696
3697         if (intel_crtc->active)
3698                 return;
3699
3700         intel_crtc->active = true;
3701         intel_update_watermarks(dev);
3702
3703         for_each_encoder_on_crtc(dev, crtc, encoder)
3704                 if (encoder->pre_enable)
3705                         encoder->pre_enable(encoder);
3706
3707         i9xx_enable_pll(intel_crtc);
3708
3709         i9xx_pfit_enable(intel_crtc);
3710
3711         intel_crtc_load_lut(crtc);
3712
3713         intel_enable_pipe(dev_priv, pipe, false);
3714         intel_enable_plane(dev_priv, plane, pipe);
3715         intel_enable_planes(crtc);
3716         /* The fixup needs to happen before cursor is enabled */
3717         if (IS_G4X(dev))
3718                 g4x_fixup_plane(dev_priv, pipe);
3719         intel_crtc_update_cursor(crtc, true);
3720
3721         /* Give the overlay scaler a chance to enable if it's on this pipe */
3722         intel_crtc_dpms_overlay(intel_crtc, true);
3723
3724         intel_update_fbc(dev);
3725
3726         for_each_encoder_on_crtc(dev, crtc, encoder)
3727                 encoder->enable(encoder);
3728 }
3729
3730 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3731 {
3732         struct drm_device *dev = crtc->base.dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734
3735         if (!crtc->config.gmch_pfit.control)
3736                 return;
3737
3738         assert_pipe_disabled(dev_priv, crtc->pipe);
3739
3740         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3741                          I915_READ(PFIT_CONTROL));
3742         I915_WRITE(PFIT_CONTROL, 0);
3743 }
3744
3745 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         struct intel_encoder *encoder;
3751         int pipe = intel_crtc->pipe;
3752         int plane = intel_crtc->plane;
3753
3754         if (!intel_crtc->active)
3755                 return;
3756
3757         for_each_encoder_on_crtc(dev, crtc, encoder)
3758                 encoder->disable(encoder);
3759
3760         /* Give the overlay scaler a chance to disable if it's on this pipe */
3761         intel_crtc_wait_for_pending_flips(crtc);
3762         drm_vblank_off(dev, pipe);
3763
3764         if (dev_priv->fbc.plane == plane)
3765                 intel_disable_fbc(dev);
3766
3767         intel_crtc_dpms_overlay(intel_crtc, false);
3768         intel_crtc_update_cursor(crtc, false);
3769         intel_disable_planes(crtc);
3770         intel_disable_plane(dev_priv, plane, pipe);
3771
3772         intel_disable_pipe(dev_priv, pipe);
3773
3774         i9xx_pfit_disable(intel_crtc);
3775
3776         for_each_encoder_on_crtc(dev, crtc, encoder)
3777                 if (encoder->post_disable)
3778                         encoder->post_disable(encoder);
3779
3780         i9xx_disable_pll(dev_priv, pipe);
3781
3782         intel_crtc->active = false;
3783         intel_update_fbc(dev);
3784         intel_update_watermarks(dev);
3785 }
3786
3787 static void i9xx_crtc_off(struct drm_crtc *crtc)
3788 {
3789 }
3790
3791 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3792                                     bool enabled)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795         struct drm_i915_master_private *master_priv;
3796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797         int pipe = intel_crtc->pipe;
3798
3799         if (!dev->primary->master)
3800                 return;
3801
3802         master_priv = dev->primary->master->driver_priv;
3803         if (!master_priv->sarea_priv)
3804                 return;
3805
3806         switch (pipe) {
3807         case 0:
3808                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3809                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3810                 break;
3811         case 1:
3812                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3813                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3814                 break;
3815         default:
3816                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3817                 break;
3818         }
3819 }
3820
3821 /**
3822  * Sets the power management mode of the pipe and plane.
3823  */
3824 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         struct intel_encoder *intel_encoder;
3829         bool enable = false;
3830
3831         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3832                 enable |= intel_encoder->connectors_active;
3833
3834         if (enable)
3835                 dev_priv->display.crtc_enable(crtc);
3836         else
3837                 dev_priv->display.crtc_disable(crtc);
3838
3839         intel_crtc_update_sarea(crtc, enable);
3840 }
3841
3842 static void intel_crtc_disable(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         struct drm_connector *connector;
3846         struct drm_i915_private *dev_priv = dev->dev_private;
3847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848
3849         /* crtc should still be enabled when we disable it. */
3850         WARN_ON(!crtc->enabled);
3851
3852         dev_priv->display.crtc_disable(crtc);
3853         intel_crtc->eld_vld = false;
3854         intel_crtc_update_sarea(crtc, false);
3855         dev_priv->display.off(crtc);
3856
3857         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3858         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3859
3860         if (crtc->fb) {
3861                 mutex_lock(&dev->struct_mutex);
3862                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3863                 mutex_unlock(&dev->struct_mutex);
3864                 crtc->fb = NULL;
3865         }
3866
3867         /* Update computed state. */
3868         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3869                 if (!connector->encoder || !connector->encoder->crtc)
3870                         continue;
3871
3872                 if (connector->encoder->crtc != crtc)
3873                         continue;
3874
3875                 connector->dpms = DRM_MODE_DPMS_OFF;
3876                 to_intel_encoder(connector->encoder)->connectors_active = false;
3877         }
3878 }
3879
3880 void intel_modeset_disable(struct drm_device *dev)
3881 {
3882         struct drm_crtc *crtc;
3883
3884         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3885                 if (crtc->enabled)
3886                         intel_crtc_disable(crtc);
3887         }
3888 }
3889
3890 void intel_encoder_destroy(struct drm_encoder *encoder)
3891 {
3892         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3893
3894         drm_encoder_cleanup(encoder);
3895         kfree(intel_encoder);
3896 }
3897
3898 /* Simple dpms helper for encodres with just one connector, no cloning and only
3899  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3900  * state of the entire output pipe. */
3901 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3902 {
3903         if (mode == DRM_MODE_DPMS_ON) {
3904                 encoder->connectors_active = true;
3905
3906                 intel_crtc_update_dpms(encoder->base.crtc);
3907         } else {
3908                 encoder->connectors_active = false;
3909
3910                 intel_crtc_update_dpms(encoder->base.crtc);
3911         }
3912 }
3913
3914 /* Cross check the actual hw state with our own modeset state tracking (and it's
3915  * internal consistency). */
3916 static void intel_connector_check_state(struct intel_connector *connector)
3917 {
3918         if (connector->get_hw_state(connector)) {
3919                 struct intel_encoder *encoder = connector->encoder;
3920                 struct drm_crtc *crtc;
3921                 bool encoder_enabled;
3922                 enum pipe pipe;
3923
3924                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3925                               connector->base.base.id,
3926                               drm_get_connector_name(&connector->base));
3927
3928                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3929                      "wrong connector dpms state\n");
3930                 WARN(connector->base.encoder != &encoder->base,
3931                      "active connector not linked to encoder\n");
3932                 WARN(!encoder->connectors_active,
3933                      "encoder->connectors_active not set\n");
3934
3935                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3936                 WARN(!encoder_enabled, "encoder not enabled\n");
3937                 if (WARN_ON(!encoder->base.crtc))
3938                         return;
3939
3940                 crtc = encoder->base.crtc;
3941
3942                 WARN(!crtc->enabled, "crtc not enabled\n");
3943                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3944                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3945                      "encoder active on the wrong pipe\n");
3946         }
3947 }
3948
3949 /* Even simpler default implementation, if there's really no special case to
3950  * consider. */
3951 void intel_connector_dpms(struct drm_connector *connector, int mode)
3952 {
3953         struct intel_encoder *encoder = intel_attached_encoder(connector);
3954
3955         /* All the simple cases only support two dpms states. */
3956         if (mode != DRM_MODE_DPMS_ON)
3957                 mode = DRM_MODE_DPMS_OFF;
3958
3959         if (mode == connector->dpms)
3960                 return;
3961
3962         connector->dpms = mode;
3963
3964         /* Only need to change hw state when actually enabled */
3965         if (encoder->base.crtc)
3966                 intel_encoder_dpms(encoder, mode);
3967         else
3968                 WARN_ON(encoder->connectors_active != false);
3969
3970         intel_modeset_check_state(connector->dev);
3971 }
3972
3973 /* Simple connector->get_hw_state implementation for encoders that support only
3974  * one connector and no cloning and hence the encoder state determines the state
3975  * of the connector. */
3976 bool intel_connector_get_hw_state(struct intel_connector *connector)
3977 {
3978         enum pipe pipe = 0;
3979         struct intel_encoder *encoder = connector->encoder;
3980
3981         return encoder->get_hw_state(encoder, &pipe);
3982 }
3983
3984 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3985                                      struct intel_crtc_config *pipe_config)
3986 {
3987         struct drm_i915_private *dev_priv = dev->dev_private;
3988         struct intel_crtc *pipe_B_crtc =
3989                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3990
3991         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3992                       pipe_name(pipe), pipe_config->fdi_lanes);
3993         if (pipe_config->fdi_lanes > 4) {
3994                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3995                               pipe_name(pipe), pipe_config->fdi_lanes);
3996                 return false;
3997         }
3998
3999         if (IS_HASWELL(dev)) {
4000                 if (pipe_config->fdi_lanes > 2) {
4001                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4002                                       pipe_config->fdi_lanes);
4003                         return false;
4004                 } else {
4005                         return true;
4006                 }
4007         }
4008
4009         if (INTEL_INFO(dev)->num_pipes == 2)
4010                 return true;
4011
4012         /* Ivybridge 3 pipe is really complicated */
4013         switch (pipe) {
4014         case PIPE_A:
4015                 return true;
4016         case PIPE_B:
4017                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4018                     pipe_config->fdi_lanes > 2) {
4019                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020                                       pipe_name(pipe), pipe_config->fdi_lanes);
4021                         return false;
4022                 }
4023                 return true;
4024         case PIPE_C:
4025                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4026                     pipe_B_crtc->config.fdi_lanes <= 2) {
4027                         if (pipe_config->fdi_lanes > 2) {
4028                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4029                                               pipe_name(pipe), pipe_config->fdi_lanes);
4030                                 return false;
4031                         }
4032                 } else {
4033                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4034                         return false;
4035                 }
4036                 return true;
4037         default:
4038                 BUG();
4039         }
4040 }
4041
4042 #define RETRY 1
4043 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4044                                        struct intel_crtc_config *pipe_config)
4045 {
4046         struct drm_device *dev = intel_crtc->base.dev;
4047         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4048         int lane, link_bw, fdi_dotclock;
4049         bool setup_ok, needs_recompute = false;
4050
4051 retry:
4052         /* FDI is a binary signal running at ~2.7GHz, encoding
4053          * each output octet as 10 bits. The actual frequency
4054          * is stored as a divider into a 100MHz clock, and the
4055          * mode pixel clock is stored in units of 1KHz.
4056          * Hence the bw of each lane in terms of the mode signal
4057          * is:
4058          */
4059         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4060
4061         fdi_dotclock = adjusted_mode->clock;
4062         fdi_dotclock /= pipe_config->pixel_multiplier;
4063
4064         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4065                                            pipe_config->pipe_bpp);
4066
4067         pipe_config->fdi_lanes = lane;
4068
4069         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4070                                link_bw, &pipe_config->fdi_m_n);
4071
4072         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4073                                             intel_crtc->pipe, pipe_config);
4074         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4075                 pipe_config->pipe_bpp -= 2*3;
4076                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4077                               pipe_config->pipe_bpp);
4078                 needs_recompute = true;
4079                 pipe_config->bw_constrained = true;
4080
4081                 goto retry;
4082         }
4083
4084         if (needs_recompute)
4085                 return RETRY;
4086
4087         return setup_ok ? 0 : -EINVAL;
4088 }
4089
4090 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4091                                    struct intel_crtc_config *pipe_config)
4092 {
4093         pipe_config->ips_enabled = i915_enable_ips &&
4094                                    hsw_crtc_supports_ips(crtc) &&
4095                                    pipe_config->pipe_bpp == 24;
4096 }
4097
4098 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4099                                      struct intel_crtc_config *pipe_config)
4100 {
4101         struct drm_device *dev = crtc->base.dev;
4102         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4103
4104         if (HAS_PCH_SPLIT(dev)) {
4105                 /* FDI link clock is fixed at 2.7G */
4106                 if (pipe_config->requested_mode.clock * 3
4107                     > IRONLAKE_FDI_FREQ * 4)
4108                         return -EINVAL;
4109         }
4110
4111         /* All interlaced capable intel hw wants timings in frames. Note though
4112          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4113          * timings, so we need to be careful not to clobber these.*/
4114         if (!pipe_config->timings_set)
4115                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4116
4117         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4118          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4119          */
4120         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4121                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4122                 return -EINVAL;
4123
4124         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4125                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4126         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4127                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4128                  * for lvds. */
4129                 pipe_config->pipe_bpp = 8*3;
4130         }
4131
4132         if (HAS_IPS(dev))
4133                 hsw_compute_ips_config(crtc, pipe_config);
4134
4135         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4136          * clock survives for now. */
4137         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4138                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4139
4140         if (pipe_config->has_pch_encoder)
4141                 return ironlake_fdi_compute_config(crtc, pipe_config);
4142
4143         return 0;
4144 }
4145
4146 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4147 {
4148         return 400000; /* FIXME */
4149 }
4150
4151 static int i945_get_display_clock_speed(struct drm_device *dev)
4152 {
4153         return 400000;
4154 }
4155
4156 static int i915_get_display_clock_speed(struct drm_device *dev)
4157 {
4158         return 333000;
4159 }
4160
4161 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4162 {
4163         return 200000;
4164 }
4165
4166 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4167 {
4168         u16 gcfgc = 0;
4169
4170         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4171
4172         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4173                 return 133000;
4174         else {
4175                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4176                 case GC_DISPLAY_CLOCK_333_MHZ:
4177                         return 333000;
4178                 default:
4179                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4180                         return 190000;
4181                 }
4182         }
4183 }
4184
4185 static int i865_get_display_clock_speed(struct drm_device *dev)
4186 {
4187         return 266000;
4188 }
4189
4190 static int i855_get_display_clock_speed(struct drm_device *dev)
4191 {
4192         u16 hpllcc = 0;
4193         /* Assume that the hardware is in the high speed state.  This
4194          * should be the default.
4195          */
4196         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4197         case GC_CLOCK_133_200:
4198         case GC_CLOCK_100_200:
4199                 return 200000;
4200         case GC_CLOCK_166_250:
4201                 return 250000;
4202         case GC_CLOCK_100_133:
4203                 return 133000;
4204         }
4205
4206         /* Shouldn't happen */
4207         return 0;
4208 }
4209
4210 static int i830_get_display_clock_speed(struct drm_device *dev)
4211 {
4212         return 133000;
4213 }
4214
4215 static void
4216 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4217 {
4218         while (*num > DATA_LINK_M_N_MASK ||
4219                *den > DATA_LINK_M_N_MASK) {
4220                 *num >>= 1;
4221                 *den >>= 1;
4222         }
4223 }
4224
4225 static void compute_m_n(unsigned int m, unsigned int n,
4226                         uint32_t *ret_m, uint32_t *ret_n)
4227 {
4228         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4229         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4230         intel_reduce_m_n_ratio(ret_m, ret_n);
4231 }
4232
4233 void
4234 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4235                        int pixel_clock, int link_clock,
4236                        struct intel_link_m_n *m_n)
4237 {
4238         m_n->tu = 64;
4239
4240         compute_m_n(bits_per_pixel * pixel_clock,
4241                     link_clock * nlanes * 8,
4242                     &m_n->gmch_m, &m_n->gmch_n);
4243
4244         compute_m_n(pixel_clock, link_clock,
4245                     &m_n->link_m, &m_n->link_n);
4246 }
4247
4248 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4249 {
4250         if (i915_panel_use_ssc >= 0)
4251                 return i915_panel_use_ssc != 0;
4252         return dev_priv->vbt.lvds_use_ssc
4253                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4254 }
4255
4256 static int vlv_get_refclk(struct drm_crtc *crtc)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct drm_i915_private *dev_priv = dev->dev_private;
4260         int refclk = 27000; /* for DP & HDMI */
4261
4262         return 100000; /* only one validated so far */
4263
4264         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4265                 refclk = 96000;
4266         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4267                 if (intel_panel_use_ssc(dev_priv))
4268                         refclk = 100000;
4269                 else
4270                         refclk = 96000;
4271         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4272                 refclk = 100000;
4273         }
4274
4275         return refclk;
4276 }
4277
4278 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4279 {
4280         struct drm_device *dev = crtc->dev;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         int refclk;
4283
4284         if (IS_VALLEYVIEW(dev)) {
4285                 refclk = vlv_get_refclk(crtc);
4286         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4287             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4288                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4289                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4290                               refclk / 1000);
4291         } else if (!IS_GEN2(dev)) {
4292                 refclk = 96000;
4293         } else {
4294                 refclk = 48000;
4295         }
4296
4297         return refclk;
4298 }
4299
4300 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4301 {
4302         return (1 << dpll->n) << 16 | dpll->m2;
4303 }
4304
4305 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4306 {
4307         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4308 }
4309
4310 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4311                                      intel_clock_t *reduced_clock)
4312 {
4313         struct drm_device *dev = crtc->base.dev;
4314         struct drm_i915_private *dev_priv = dev->dev_private;
4315         int pipe = crtc->pipe;
4316         u32 fp, fp2 = 0;
4317
4318         if (IS_PINEVIEW(dev)) {
4319                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4320                 if (reduced_clock)
4321                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4322         } else {
4323                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4324                 if (reduced_clock)
4325                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4326         }
4327
4328         I915_WRITE(FP0(pipe), fp);
4329         crtc->config.dpll_hw_state.fp0 = fp;
4330
4331         crtc->lowfreq_avail = false;
4332         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4333             reduced_clock && i915_powersave) {
4334                 I915_WRITE(FP1(pipe), fp2);
4335                 crtc->config.dpll_hw_state.fp1 = fp2;
4336                 crtc->lowfreq_avail = true;
4337         } else {
4338                 I915_WRITE(FP1(pipe), fp);
4339                 crtc->config.dpll_hw_state.fp1 = fp;
4340         }
4341 }
4342
4343 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4344 {
4345         u32 reg_val;
4346
4347         /*
4348          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4349          * and set it to a reasonable value instead.
4350          */
4351         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4352         reg_val &= 0xffffff00;
4353         reg_val |= 0x00000030;
4354         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4355
4356         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4357         reg_val &= 0x8cffffff;
4358         reg_val = 0x8c000000;
4359         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4360
4361         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4362         reg_val &= 0xffffff00;
4363         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4364
4365         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4366         reg_val &= 0x00ffffff;
4367         reg_val |= 0xb0000000;
4368         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4369 }
4370
4371 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4372                                          struct intel_link_m_n *m_n)
4373 {
4374         struct drm_device *dev = crtc->base.dev;
4375         struct drm_i915_private *dev_priv = dev->dev_private;
4376         int pipe = crtc->pipe;
4377
4378         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4380         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4381         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4382 }
4383
4384 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4385                                          struct intel_link_m_n *m_n)
4386 {
4387         struct drm_device *dev = crtc->base.dev;
4388         struct drm_i915_private *dev_priv = dev->dev_private;
4389         int pipe = crtc->pipe;
4390         enum transcoder transcoder = crtc->config.cpu_transcoder;
4391
4392         if (INTEL_INFO(dev)->gen >= 5) {
4393                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4395                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4396                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4397         } else {
4398                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4399                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4400                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4401                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4402         }
4403 }
4404
4405 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4406 {
4407         if (crtc->config.has_pch_encoder)
4408                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4409         else
4410                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4411 }
4412
4413 static void vlv_update_pll(struct intel_crtc *crtc)
4414 {
4415         struct drm_device *dev = crtc->base.dev;
4416         struct drm_i915_private *dev_priv = dev->dev_private;
4417         int pipe = crtc->pipe;
4418         u32 dpll, mdiv;
4419         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4420         bool is_hdmi;
4421         u32 coreclk, reg_val, dpll_md;
4422
4423         mutex_lock(&dev_priv->dpio_lock);
4424
4425         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4426
4427         bestn = crtc->config.dpll.n;
4428         bestm1 = crtc->config.dpll.m1;
4429         bestm2 = crtc->config.dpll.m2;
4430         bestp1 = crtc->config.dpll.p1;
4431         bestp2 = crtc->config.dpll.p2;
4432
4433         /* See eDP HDMI DPIO driver vbios notes doc */
4434
4435         /* PLL B needs special handling */
4436         if (pipe)
4437                 vlv_pllb_recal_opamp(dev_priv);
4438
4439         /* Set up Tx target for periodic Rcomp update */
4440         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4441
4442         /* Disable target IRef on PLL */
4443         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4444         reg_val &= 0x00ffffff;
4445         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4446
4447         /* Disable fast lock */
4448         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4449
4450         /* Set idtafcrecal before PLL is enabled */
4451         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4452         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4453         mdiv |= ((bestn << DPIO_N_SHIFT));
4454         mdiv |= (1 << DPIO_K_SHIFT);
4455
4456         /*
4457          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4458          * but we don't support that).
4459          * Note: don't use the DAC post divider as it seems unstable.
4460          */
4461         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4462         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4463
4464         mdiv |= DPIO_ENABLE_CALIBRATION;
4465         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4466
4467         /* Set HBR and RBR LPF coefficients */
4468         if (crtc->config.port_clock == 162000 ||
4469             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4470             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4471                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4472                                  0x009f0003);
4473         else
4474                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4475                                  0x00d0000f);
4476
4477         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4478             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4479                 /* Use SSC source */
4480                 if (!pipe)
4481                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4482                                          0x0df40000);
4483                 else
4484                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4485                                          0x0df70000);
4486         } else { /* HDMI or VGA */
4487                 /* Use bend source */
4488                 if (!pipe)
4489                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4490                                          0x0df70000);
4491                 else
4492                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4493                                          0x0df40000);
4494         }
4495
4496         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4497         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4498         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4499             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4500                 coreclk |= 0x01000000;
4501         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4502
4503         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4504
4505         /* Enable DPIO clock input */
4506         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4507                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4508         if (pipe)
4509                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4510
4511         dpll |= DPLL_VCO_ENABLE;
4512         crtc->config.dpll_hw_state.dpll = dpll;
4513
4514         dpll_md = (crtc->config.pixel_multiplier - 1)
4515                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4516         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4517
4518         if (crtc->config.has_dp_encoder)
4519                 intel_dp_set_m_n(crtc);
4520
4521         mutex_unlock(&dev_priv->dpio_lock);
4522 }
4523
4524 static void i9xx_update_pll(struct intel_crtc *crtc,
4525                             intel_clock_t *reduced_clock,
4526                             int num_connectors)
4527 {
4528         struct drm_device *dev = crtc->base.dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         u32 dpll;
4531         bool is_sdvo;
4532         struct dpll *clock = &crtc->config.dpll;
4533
4534         i9xx_update_pll_dividers(crtc, reduced_clock);
4535
4536         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4537                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4538
4539         dpll = DPLL_VGA_MODE_DIS;
4540
4541         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4542                 dpll |= DPLLB_MODE_LVDS;
4543         else
4544                 dpll |= DPLLB_MODE_DAC_SERIAL;
4545
4546         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4547                 dpll |= (crtc->config.pixel_multiplier - 1)
4548                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4549         }
4550
4551         if (is_sdvo)
4552                 dpll |= DPLL_SDVO_HIGH_SPEED;
4553
4554         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4555                 dpll |= DPLL_SDVO_HIGH_SPEED;
4556
4557         /* compute bitmask from p1 value */
4558         if (IS_PINEVIEW(dev))
4559                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4560         else {
4561                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4562                 if (IS_G4X(dev) && reduced_clock)
4563                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4564         }
4565         switch (clock->p2) {
4566         case 5:
4567                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4568                 break;
4569         case 7:
4570                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4571                 break;
4572         case 10:
4573                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4574                 break;
4575         case 14:
4576                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4577                 break;
4578         }
4579         if (INTEL_INFO(dev)->gen >= 4)
4580                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4581
4582         if (crtc->config.sdvo_tv_clock)
4583                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4584         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4585                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4586                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4587         else
4588                 dpll |= PLL_REF_INPUT_DREFCLK;
4589
4590         dpll |= DPLL_VCO_ENABLE;
4591         crtc->config.dpll_hw_state.dpll = dpll;
4592
4593         if (INTEL_INFO(dev)->gen >= 4) {
4594                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4595                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4596                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4597         }
4598
4599         if (crtc->config.has_dp_encoder)
4600                 intel_dp_set_m_n(crtc);
4601 }
4602
4603 static void i8xx_update_pll(struct intel_crtc *crtc,
4604                             intel_clock_t *reduced_clock,
4605                             int num_connectors)
4606 {
4607         struct drm_device *dev = crtc->base.dev;
4608         struct drm_i915_private *dev_priv = dev->dev_private;
4609         u32 dpll;
4610         struct dpll *clock = &crtc->config.dpll;
4611
4612         i9xx_update_pll_dividers(crtc, reduced_clock);
4613
4614         dpll = DPLL_VGA_MODE_DIS;
4615
4616         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4617                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4618         } else {
4619                 if (clock->p1 == 2)
4620                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4621                 else
4622                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4623                 if (clock->p2 == 4)
4624                         dpll |= PLL_P2_DIVIDE_BY_4;
4625         }
4626
4627         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4628                 dpll |= DPLL_DVO_2X_MODE;
4629
4630         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4631                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4632                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4633         else
4634                 dpll |= PLL_REF_INPUT_DREFCLK;
4635
4636         dpll |= DPLL_VCO_ENABLE;
4637         crtc->config.dpll_hw_state.dpll = dpll;
4638 }
4639
4640 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4641 {
4642         struct drm_device *dev = intel_crtc->base.dev;
4643         struct drm_i915_private *dev_priv = dev->dev_private;
4644         enum pipe pipe = intel_crtc->pipe;
4645         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4646         struct drm_display_mode *adjusted_mode =
4647                 &intel_crtc->config.adjusted_mode;
4648         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4649         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4650
4651         /* We need to be careful not to changed the adjusted mode, for otherwise
4652          * the hw state checker will get angry at the mismatch. */
4653         crtc_vtotal = adjusted_mode->crtc_vtotal;
4654         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4655
4656         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4657                 /* the chip adds 2 halflines automatically */
4658                 crtc_vtotal -= 1;
4659                 crtc_vblank_end -= 1;
4660                 vsyncshift = adjusted_mode->crtc_hsync_start
4661                              - adjusted_mode->crtc_htotal / 2;
4662         } else {
4663                 vsyncshift = 0;
4664         }
4665
4666         if (INTEL_INFO(dev)->gen > 3)
4667                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4668
4669         I915_WRITE(HTOTAL(cpu_transcoder),
4670                    (adjusted_mode->crtc_hdisplay - 1) |
4671                    ((adjusted_mode->crtc_htotal - 1) << 16));
4672         I915_WRITE(HBLANK(cpu_transcoder),
4673                    (adjusted_mode->crtc_hblank_start - 1) |
4674                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4675         I915_WRITE(HSYNC(cpu_transcoder),
4676                    (adjusted_mode->crtc_hsync_start - 1) |
4677                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4678
4679         I915_WRITE(VTOTAL(cpu_transcoder),
4680                    (adjusted_mode->crtc_vdisplay - 1) |
4681                    ((crtc_vtotal - 1) << 16));
4682         I915_WRITE(VBLANK(cpu_transcoder),
4683                    (adjusted_mode->crtc_vblank_start - 1) |
4684                    ((crtc_vblank_end - 1) << 16));
4685         I915_WRITE(VSYNC(cpu_transcoder),
4686                    (adjusted_mode->crtc_vsync_start - 1) |
4687                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4688
4689         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4690          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4691          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4692          * bits. */
4693         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4694             (pipe == PIPE_B || pipe == PIPE_C))
4695                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4696
4697         /* pipesrc controls the size that is scaled from, which should
4698          * always be the user's requested size.
4699          */
4700         I915_WRITE(PIPESRC(pipe),
4701                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4702 }
4703
4704 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4705                                    struct intel_crtc_config *pipe_config)
4706 {
4707         struct drm_device *dev = crtc->base.dev;
4708         struct drm_i915_private *dev_priv = dev->dev_private;
4709         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4710         uint32_t tmp;
4711
4712         tmp = I915_READ(HTOTAL(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4715         tmp = I915_READ(HBLANK(cpu_transcoder));
4716         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4717         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4718         tmp = I915_READ(HSYNC(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722         tmp = I915_READ(VTOTAL(cpu_transcoder));
4723         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4724         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4725         tmp = I915_READ(VBLANK(cpu_transcoder));
4726         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4727         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4728         tmp = I915_READ(VSYNC(cpu_transcoder));
4729         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4730         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4731
4732         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4733                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4734                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4735                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4736         }
4737
4738         tmp = I915_READ(PIPESRC(crtc->pipe));
4739         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4740         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4741 }
4742
4743 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4744                                              struct intel_crtc_config *pipe_config)
4745 {
4746         struct drm_crtc *crtc = &intel_crtc->base;
4747
4748         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4749         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4750         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4751         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4752
4753         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4754         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4755         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4756         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4757
4758         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4759
4760         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4761         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4762 }
4763
4764 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4765 {
4766         struct drm_device *dev = intel_crtc->base.dev;
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768         uint32_t pipeconf;
4769
4770         pipeconf = 0;
4771
4772         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4773                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4774                  * core speed.
4775                  *
4776                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4777                  * pipe == 0 check?
4778                  */
4779                 if (intel_crtc->config.requested_mode.clock >
4780                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4781                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4782         }
4783
4784         /* only g4x and later have fancy bpc/dither controls */
4785         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4786                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4787                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4788                         pipeconf |= PIPECONF_DITHER_EN |
4789                                     PIPECONF_DITHER_TYPE_SP;
4790
4791                 switch (intel_crtc->config.pipe_bpp) {
4792                 case 18:
4793                         pipeconf |= PIPECONF_6BPC;
4794                         break;
4795                 case 24:
4796                         pipeconf |= PIPECONF_8BPC;
4797                         break;
4798                 case 30:
4799                         pipeconf |= PIPECONF_10BPC;
4800                         break;
4801                 default:
4802                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4803                         BUG();
4804                 }
4805         }
4806
4807         if (HAS_PIPE_CXSR(dev)) {
4808                 if (intel_crtc->lowfreq_avail) {
4809                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4810                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4811                 } else {
4812                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4813                 }
4814         }
4815
4816         if (!IS_GEN2(dev) &&
4817             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4818                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4819         else
4820                 pipeconf |= PIPECONF_PROGRESSIVE;
4821
4822         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4823                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4824
4825         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4826         POSTING_READ(PIPECONF(intel_crtc->pipe));
4827 }
4828
4829 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4830                               int x, int y,
4831                               struct drm_framebuffer *fb)
4832 {
4833         struct drm_device *dev = crtc->dev;
4834         struct drm_i915_private *dev_priv = dev->dev_private;
4835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4837         int pipe = intel_crtc->pipe;
4838         int plane = intel_crtc->plane;
4839         int refclk, num_connectors = 0;
4840         intel_clock_t clock, reduced_clock;
4841         u32 dspcntr;
4842         bool ok, has_reduced_clock = false;
4843         bool is_lvds = false;
4844         struct intel_encoder *encoder;
4845         const intel_limit_t *limit;
4846         int ret;
4847
4848         for_each_encoder_on_crtc(dev, crtc, encoder) {
4849                 switch (encoder->type) {
4850                 case INTEL_OUTPUT_LVDS:
4851                         is_lvds = true;
4852                         break;
4853                 }
4854
4855                 num_connectors++;
4856         }
4857
4858         refclk = i9xx_get_refclk(crtc, num_connectors);
4859
4860         /*
4861          * Returns a set of divisors for the desired target clock with the given
4862          * refclk, or FALSE.  The returned values represent the clock equation:
4863          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4864          */
4865         limit = intel_limit(crtc, refclk);
4866         ok = dev_priv->display.find_dpll(limit, crtc,
4867                                          intel_crtc->config.port_clock,
4868                                          refclk, NULL, &clock);
4869         if (!ok && !intel_crtc->config.clock_set) {
4870                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4871                 return -EINVAL;
4872         }
4873
4874         /* Ensure that the cursor is valid for the new mode before changing... */
4875         intel_crtc_update_cursor(crtc, true);
4876
4877         if (is_lvds && dev_priv->lvds_downclock_avail) {
4878                 /*
4879                  * Ensure we match the reduced clock's P to the target clock.
4880                  * If the clocks don't match, we can't switch the display clock
4881                  * by using the FP0/FP1. In such case we will disable the LVDS
4882                  * downclock feature.
4883                 */
4884                 has_reduced_clock =
4885                         dev_priv->display.find_dpll(limit, crtc,
4886                                                     dev_priv->lvds_downclock,
4887                                                     refclk, &clock,
4888                                                     &reduced_clock);
4889         }
4890         /* Compat-code for transition, will disappear. */
4891         if (!intel_crtc->config.clock_set) {
4892                 intel_crtc->config.dpll.n = clock.n;
4893                 intel_crtc->config.dpll.m1 = clock.m1;
4894                 intel_crtc->config.dpll.m2 = clock.m2;
4895                 intel_crtc->config.dpll.p1 = clock.p1;
4896                 intel_crtc->config.dpll.p2 = clock.p2;
4897         }
4898
4899         if (IS_GEN2(dev))
4900                 i8xx_update_pll(intel_crtc,
4901                                 has_reduced_clock ? &reduced_clock : NULL,
4902                                 num_connectors);
4903         else if (IS_VALLEYVIEW(dev))
4904                 vlv_update_pll(intel_crtc);
4905         else
4906                 i9xx_update_pll(intel_crtc,
4907                                 has_reduced_clock ? &reduced_clock : NULL,
4908                                 num_connectors);
4909
4910         /* Set up the display plane register */
4911         dspcntr = DISPPLANE_GAMMA_ENABLE;
4912
4913         if (!IS_VALLEYVIEW(dev)) {
4914                 if (pipe == 0)
4915                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4916                 else
4917                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4918         }
4919
4920         intel_set_pipe_timings(intel_crtc);
4921
4922         /* pipesrc and dspsize control the size that is scaled from,
4923          * which should always be the user's requested size.
4924          */
4925         I915_WRITE(DSPSIZE(plane),
4926                    ((mode->vdisplay - 1) << 16) |
4927                    (mode->hdisplay - 1));
4928         I915_WRITE(DSPPOS(plane), 0);
4929
4930         i9xx_set_pipeconf(intel_crtc);
4931
4932         I915_WRITE(DSPCNTR(plane), dspcntr);
4933         POSTING_READ(DSPCNTR(plane));
4934
4935         ret = intel_pipe_set_base(crtc, x, y, fb);
4936
4937         intel_update_watermarks(dev);
4938
4939         return ret;
4940 }
4941
4942 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4943                                  struct intel_crtc_config *pipe_config)
4944 {
4945         struct drm_device *dev = crtc->base.dev;
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         uint32_t tmp;
4948
4949         tmp = I915_READ(PFIT_CONTROL);
4950
4951         if (INTEL_INFO(dev)->gen < 4) {
4952                 if (crtc->pipe != PIPE_B)
4953                         return;
4954
4955                 /* gen2/3 store dither state in pfit control, needs to match */
4956                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4957         } else {
4958                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4959                         return;
4960         }
4961
4962         if (!(tmp & PFIT_ENABLE))
4963                 return;
4964
4965         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4966         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4967         if (INTEL_INFO(dev)->gen < 5)
4968                 pipe_config->gmch_pfit.lvds_border_bits =
4969                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4970 }
4971
4972 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4973                                  struct intel_crtc_config *pipe_config)
4974 {
4975         struct drm_device *dev = crtc->base.dev;
4976         struct drm_i915_private *dev_priv = dev->dev_private;
4977         uint32_t tmp;
4978
4979         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4980         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4981
4982         tmp = I915_READ(PIPECONF(crtc->pipe));
4983         if (!(tmp & PIPECONF_ENABLE))
4984                 return false;
4985
4986         intel_get_pipe_timings(crtc, pipe_config);
4987
4988         i9xx_get_pfit_config(crtc, pipe_config);
4989
4990         if (INTEL_INFO(dev)->gen >= 4) {
4991                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4992                 pipe_config->pixel_multiplier =
4993                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4994                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4995                 pipe_config->dpll_hw_state.dpll_md = tmp;
4996         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4997                 tmp = I915_READ(DPLL(crtc->pipe));
4998                 pipe_config->pixel_multiplier =
4999                         ((tmp & SDVO_MULTIPLIER_MASK)
5000                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5001         } else {
5002                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5003                  * port and will be fixed up in the encoder->get_config
5004                  * function. */
5005                 pipe_config->pixel_multiplier = 1;
5006         }
5007         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5008         if (!IS_VALLEYVIEW(dev)) {
5009                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5010                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5011         } else {
5012                 /* Mask out read-only status bits. */
5013                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5014                                                      DPLL_PORTC_READY_MASK |
5015                                                      DPLL_PORTB_READY_MASK);
5016         }
5017
5018         return true;
5019 }
5020
5021 static void ironlake_init_pch_refclk(struct drm_device *dev)
5022 {
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct drm_mode_config *mode_config = &dev->mode_config;
5025         struct intel_encoder *encoder;
5026         u32 val, final;
5027         bool has_lvds = false;
5028         bool has_cpu_edp = false;
5029         bool has_panel = false;
5030         bool has_ck505 = false;
5031         bool can_ssc = false;
5032
5033         /* We need to take the global config into account */
5034         list_for_each_entry(encoder, &mode_config->encoder_list,
5035                             base.head) {
5036                 switch (encoder->type) {
5037                 case INTEL_OUTPUT_LVDS:
5038                         has_panel = true;
5039                         has_lvds = true;
5040                         break;
5041                 case INTEL_OUTPUT_EDP:
5042                         has_panel = true;
5043                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5044                                 has_cpu_edp = true;
5045                         break;
5046                 }
5047         }
5048
5049         if (HAS_PCH_IBX(dev)) {
5050                 has_ck505 = dev_priv->vbt.display_clock_mode;
5051                 can_ssc = has_ck505;
5052         } else {
5053                 has_ck505 = false;
5054                 can_ssc = true;
5055         }
5056
5057         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5058                       has_panel, has_lvds, has_ck505);
5059
5060         /* Ironlake: try to setup display ref clock before DPLL
5061          * enabling. This is only under driver's control after
5062          * PCH B stepping, previous chipset stepping should be
5063          * ignoring this setting.
5064          */
5065         val = I915_READ(PCH_DREF_CONTROL);
5066
5067         /* As we must carefully and slowly disable/enable each source in turn,
5068          * compute the final state we want first and check if we need to
5069          * make any changes at all.
5070          */
5071         final = val;
5072         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5073         if (has_ck505)
5074                 final |= DREF_NONSPREAD_CK505_ENABLE;
5075         else
5076                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5077
5078         final &= ~DREF_SSC_SOURCE_MASK;
5079         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5080         final &= ~DREF_SSC1_ENABLE;
5081
5082         if (has_panel) {
5083                 final |= DREF_SSC_SOURCE_ENABLE;
5084
5085                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5086                         final |= DREF_SSC1_ENABLE;
5087
5088                 if (has_cpu_edp) {
5089                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5090                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091                         else
5092                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5093                 } else
5094                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095         } else {
5096                 final |= DREF_SSC_SOURCE_DISABLE;
5097                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098         }
5099
5100         if (final == val)
5101                 return;
5102
5103         /* Always enable nonspread source */
5104         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5105
5106         if (has_ck505)
5107                 val |= DREF_NONSPREAD_CK505_ENABLE;
5108         else
5109                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5110
5111         if (has_panel) {
5112                 val &= ~DREF_SSC_SOURCE_MASK;
5113                 val |= DREF_SSC_SOURCE_ENABLE;
5114
5115                 /* SSC must be turned on before enabling the CPU output  */
5116                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5117                         DRM_DEBUG_KMS("Using SSC on panel\n");
5118                         val |= DREF_SSC1_ENABLE;
5119                 } else
5120                         val &= ~DREF_SSC1_ENABLE;
5121
5122                 /* Get SSC going before enabling the outputs */
5123                 I915_WRITE(PCH_DREF_CONTROL, val);
5124                 POSTING_READ(PCH_DREF_CONTROL);
5125                 udelay(200);
5126
5127                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5128
5129                 /* Enable CPU source on CPU attached eDP */
5130                 if (has_cpu_edp) {
5131                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5132                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5133                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5134                         }
5135                         else
5136                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5137                 } else
5138                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5139
5140                 I915_WRITE(PCH_DREF_CONTROL, val);
5141                 POSTING_READ(PCH_DREF_CONTROL);
5142                 udelay(200);
5143         } else {
5144                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5145
5146                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5147
5148                 /* Turn off CPU output */
5149                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5150
5151                 I915_WRITE(PCH_DREF_CONTROL, val);
5152                 POSTING_READ(PCH_DREF_CONTROL);
5153                 udelay(200);
5154
5155                 /* Turn off the SSC source */
5156                 val &= ~DREF_SSC_SOURCE_MASK;
5157                 val |= DREF_SSC_SOURCE_DISABLE;
5158
5159                 /* Turn off SSC1 */
5160                 val &= ~DREF_SSC1_ENABLE;
5161
5162                 I915_WRITE(PCH_DREF_CONTROL, val);
5163                 POSTING_READ(PCH_DREF_CONTROL);
5164                 udelay(200);
5165         }
5166
5167         BUG_ON(val != final);
5168 }
5169
5170 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5171 {
5172         uint32_t tmp;
5173
5174         tmp = I915_READ(SOUTH_CHICKEN2);
5175         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5176         I915_WRITE(SOUTH_CHICKEN2, tmp);
5177
5178         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5179                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5180                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5181
5182         tmp = I915_READ(SOUTH_CHICKEN2);
5183         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5184         I915_WRITE(SOUTH_CHICKEN2, tmp);
5185
5186         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5187                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5188                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5189 }
5190
5191 /* WaMPhyProgramming:hsw */
5192 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5193 {
5194         uint32_t tmp;
5195
5196         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5197         tmp &= ~(0xFF << 24);
5198         tmp |= (0x12 << 24);
5199         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5200
5201         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5202         tmp |= (1 << 11);
5203         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5204
5205         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5206         tmp |= (1 << 11);
5207         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5208
5209         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5210         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5211         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212
5213         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5214         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216
5217         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5218         tmp &= ~(7 << 13);
5219         tmp |= (5 << 13);
5220         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5221
5222         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5223         tmp &= ~(7 << 13);
5224         tmp |= (5 << 13);
5225         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5226
5227         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5228         tmp &= ~0xFF;
5229         tmp |= 0x1C;
5230         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5231
5232         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5233         tmp &= ~0xFF;
5234         tmp |= 0x1C;
5235         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5236
5237         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5238         tmp &= ~(0xFF << 16);
5239         tmp |= (0x1C << 16);
5240         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5241
5242         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5243         tmp &= ~(0xFF << 16);
5244         tmp |= (0x1C << 16);
5245         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5246
5247         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5248         tmp |= (1 << 27);
5249         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5252         tmp |= (1 << 27);
5253         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5254
5255         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5256         tmp &= ~(0xF << 28);
5257         tmp |= (4 << 28);
5258         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5259
5260         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5261         tmp &= ~(0xF << 28);
5262         tmp |= (4 << 28);
5263         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5264 }
5265
5266 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5267  * Programming" based on the parameters passed:
5268  * - Sequence to enable CLKOUT_DP
5269  * - Sequence to enable CLKOUT_DP without spread
5270  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5271  */
5272 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5273                                  bool with_fdi)
5274 {
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276         uint32_t reg, tmp;
5277
5278         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5279                 with_spread = true;
5280         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5281                  with_fdi, "LP PCH doesn't have FDI\n"))
5282                 with_fdi = false;
5283
5284         mutex_lock(&dev_priv->dpio_lock);
5285
5286         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5287         tmp &= ~SBI_SSCCTL_DISABLE;
5288         tmp |= SBI_SSCCTL_PATHALT;
5289         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5290
5291         udelay(24);
5292
5293         if (with_spread) {
5294                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5295                 tmp &= ~SBI_SSCCTL_PATHALT;
5296                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5297
5298                 if (with_fdi) {
5299                         lpt_reset_fdi_mphy(dev_priv);
5300                         lpt_program_fdi_mphy(dev_priv);
5301                 }
5302         }
5303
5304         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5305                SBI_GEN0 : SBI_DBUFF0;
5306         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5307         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5308         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5309
5310         mutex_unlock(&dev_priv->dpio_lock);
5311 }
5312
5313 static void lpt_init_pch_refclk(struct drm_device *dev)
5314 {
5315         struct drm_mode_config *mode_config = &dev->mode_config;
5316         struct intel_encoder *encoder;
5317         bool has_vga = false;
5318
5319         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5320                 switch (encoder->type) {
5321                 case INTEL_OUTPUT_ANALOG:
5322                         has_vga = true;
5323                         break;
5324                 }
5325         }
5326
5327         if (!has_vga)
5328                 return;
5329
5330         lpt_enable_clkout_dp(dev, true, true);
5331 }
5332
5333 /*
5334  * Initialize reference clocks when the driver loads
5335  */
5336 void intel_init_pch_refclk(struct drm_device *dev)
5337 {
5338         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5339                 ironlake_init_pch_refclk(dev);
5340         else if (HAS_PCH_LPT(dev))
5341                 lpt_init_pch_refclk(dev);
5342 }
5343
5344 static int ironlake_get_refclk(struct drm_crtc *crtc)
5345 {
5346         struct drm_device *dev = crtc->dev;
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         struct intel_encoder *encoder;
5349         int num_connectors = 0;
5350         bool is_lvds = false;
5351
5352         for_each_encoder_on_crtc(dev, crtc, encoder) {
5353                 switch (encoder->type) {
5354                 case INTEL_OUTPUT_LVDS:
5355                         is_lvds = true;
5356                         break;
5357                 }
5358                 num_connectors++;
5359         }
5360
5361         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5362                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5363                               dev_priv->vbt.lvds_ssc_freq);
5364                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5365         }
5366
5367         return 120000;
5368 }
5369
5370 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5371 {
5372         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374         int pipe = intel_crtc->pipe;
5375         uint32_t val;
5376
5377         val = 0;
5378
5379         switch (intel_crtc->config.pipe_bpp) {
5380         case 18:
5381                 val |= PIPECONF_6BPC;
5382                 break;
5383         case 24:
5384                 val |= PIPECONF_8BPC;
5385                 break;
5386         case 30:
5387                 val |= PIPECONF_10BPC;
5388                 break;
5389         case 36:
5390                 val |= PIPECONF_12BPC;
5391                 break;
5392         default:
5393                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5394                 BUG();
5395         }
5396
5397         if (intel_crtc->config.dither)
5398                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5399
5400         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5401                 val |= PIPECONF_INTERLACED_ILK;
5402         else
5403                 val |= PIPECONF_PROGRESSIVE;
5404
5405         if (intel_crtc->config.limited_color_range)
5406                 val |= PIPECONF_COLOR_RANGE_SELECT;
5407
5408         I915_WRITE(PIPECONF(pipe), val);
5409         POSTING_READ(PIPECONF(pipe));
5410 }
5411
5412 /*
5413  * Set up the pipe CSC unit.
5414  *
5415  * Currently only full range RGB to limited range RGB conversion
5416  * is supported, but eventually this should handle various
5417  * RGB<->YCbCr scenarios as well.
5418  */
5419 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5420 {
5421         struct drm_device *dev = crtc->dev;
5422         struct drm_i915_private *dev_priv = dev->dev_private;
5423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5424         int pipe = intel_crtc->pipe;
5425         uint16_t coeff = 0x7800; /* 1.0 */
5426
5427         /*
5428          * TODO: Check what kind of values actually come out of the pipe
5429          * with these coeff/postoff values and adjust to get the best
5430          * accuracy. Perhaps we even need to take the bpc value into
5431          * consideration.
5432          */
5433
5434         if (intel_crtc->config.limited_color_range)
5435                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5436
5437         /*
5438          * GY/GU and RY/RU should be the other way around according
5439          * to BSpec, but reality doesn't agree. Just set them up in
5440          * a way that results in the correct picture.
5441          */
5442         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5443         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5444
5445         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5446         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5447
5448         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5449         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5450
5451         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5452         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5453         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5454
5455         if (INTEL_INFO(dev)->gen > 6) {
5456                 uint16_t postoff = 0;
5457
5458                 if (intel_crtc->config.limited_color_range)
5459                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5460
5461                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5462                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5463                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5464
5465                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5466         } else {
5467                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5468
5469                 if (intel_crtc->config.limited_color_range)
5470                         mode |= CSC_BLACK_SCREEN_OFFSET;
5471
5472                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5473         }
5474 }
5475
5476 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5477 {
5478         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5481         uint32_t val;
5482
5483         val = 0;
5484
5485         if (intel_crtc->config.dither)
5486                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5487
5488         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5489                 val |= PIPECONF_INTERLACED_ILK;
5490         else
5491                 val |= PIPECONF_PROGRESSIVE;
5492
5493         I915_WRITE(PIPECONF(cpu_transcoder), val);
5494         POSTING_READ(PIPECONF(cpu_transcoder));
5495
5496         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5497         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5498 }
5499
5500 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5501                                     intel_clock_t *clock,
5502                                     bool *has_reduced_clock,
5503                                     intel_clock_t *reduced_clock)
5504 {
5505         struct drm_device *dev = crtc->dev;
5506         struct drm_i915_private *dev_priv = dev->dev_private;
5507         struct intel_encoder *intel_encoder;
5508         int refclk;
5509         const intel_limit_t *limit;
5510         bool ret, is_lvds = false;
5511
5512         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5513                 switch (intel_encoder->type) {
5514                 case INTEL_OUTPUT_LVDS:
5515                         is_lvds = true;
5516                         break;
5517                 }
5518         }
5519
5520         refclk = ironlake_get_refclk(crtc);
5521
5522         /*
5523          * Returns a set of divisors for the desired target clock with the given
5524          * refclk, or FALSE.  The returned values represent the clock equation:
5525          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5526          */
5527         limit = intel_limit(crtc, refclk);
5528         ret = dev_priv->display.find_dpll(limit, crtc,
5529                                           to_intel_crtc(crtc)->config.port_clock,
5530                                           refclk, NULL, clock);
5531         if (!ret)
5532                 return false;
5533
5534         if (is_lvds && dev_priv->lvds_downclock_avail) {
5535                 /*
5536                  * Ensure we match the reduced clock's P to the target clock.
5537                  * If the clocks don't match, we can't switch the display clock
5538                  * by using the FP0/FP1. In such case we will disable the LVDS
5539                  * downclock feature.
5540                 */
5541                 *has_reduced_clock =
5542                         dev_priv->display.find_dpll(limit, crtc,
5543                                                     dev_priv->lvds_downclock,
5544                                                     refclk, clock,
5545                                                     reduced_clock);
5546         }
5547
5548         return true;
5549 }
5550
5551 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5552 {
5553         struct drm_i915_private *dev_priv = dev->dev_private;
5554         uint32_t temp;
5555
5556         temp = I915_READ(SOUTH_CHICKEN1);
5557         if (temp & FDI_BC_BIFURCATION_SELECT)
5558                 return;
5559
5560         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5561         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5562
5563         temp |= FDI_BC_BIFURCATION_SELECT;
5564         DRM_DEBUG_KMS("enabling fdi C rx\n");
5565         I915_WRITE(SOUTH_CHICKEN1, temp);
5566         POSTING_READ(SOUTH_CHICKEN1);
5567 }
5568
5569 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5570 {
5571         struct drm_device *dev = intel_crtc->base.dev;
5572         struct drm_i915_private *dev_priv = dev->dev_private;
5573
5574         switch (intel_crtc->pipe) {
5575         case PIPE_A:
5576                 break;
5577         case PIPE_B:
5578                 if (intel_crtc->config.fdi_lanes > 2)
5579                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5580                 else
5581                         cpt_enable_fdi_bc_bifurcation(dev);
5582
5583                 break;
5584         case PIPE_C:
5585                 cpt_enable_fdi_bc_bifurcation(dev);
5586
5587                 break;
5588         default:
5589                 BUG();
5590         }
5591 }
5592
5593 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5594 {
5595         /*
5596          * Account for spread spectrum to avoid
5597          * oversubscribing the link. Max center spread
5598          * is 2.5%; use 5% for safety's sake.
5599          */
5600         u32 bps = target_clock * bpp * 21 / 20;
5601         return bps / (link_bw * 8) + 1;
5602 }
5603
5604 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5605 {
5606         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5607 }
5608
5609 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5610                                       u32 *fp,
5611                                       intel_clock_t *reduced_clock, u32 *fp2)
5612 {
5613         struct drm_crtc *crtc = &intel_crtc->base;
5614         struct drm_device *dev = crtc->dev;
5615         struct drm_i915_private *dev_priv = dev->dev_private;
5616         struct intel_encoder *intel_encoder;
5617         uint32_t dpll;
5618         int factor, num_connectors = 0;
5619         bool is_lvds = false, is_sdvo = false;
5620
5621         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5622                 switch (intel_encoder->type) {
5623                 case INTEL_OUTPUT_LVDS:
5624                         is_lvds = true;
5625                         break;
5626                 case INTEL_OUTPUT_SDVO:
5627                 case INTEL_OUTPUT_HDMI:
5628                         is_sdvo = true;
5629                         break;
5630                 }
5631
5632                 num_connectors++;
5633         }
5634
5635         /* Enable autotuning of the PLL clock (if permissible) */
5636         factor = 21;
5637         if (is_lvds) {
5638                 if ((intel_panel_use_ssc(dev_priv) &&
5639                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5640                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5641                         factor = 25;
5642         } else if (intel_crtc->config.sdvo_tv_clock)
5643                 factor = 20;
5644
5645         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5646                 *fp |= FP_CB_TUNE;
5647
5648         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5649                 *fp2 |= FP_CB_TUNE;
5650
5651         dpll = 0;
5652
5653         if (is_lvds)
5654                 dpll |= DPLLB_MODE_LVDS;
5655         else
5656                 dpll |= DPLLB_MODE_DAC_SERIAL;
5657
5658         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5659                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5660
5661         if (is_sdvo)
5662                 dpll |= DPLL_SDVO_HIGH_SPEED;
5663         if (intel_crtc->config.has_dp_encoder)
5664                 dpll |= DPLL_SDVO_HIGH_SPEED;
5665
5666         /* compute bitmask from p1 value */
5667         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5668         /* also FPA1 */
5669         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5670
5671         switch (intel_crtc->config.dpll.p2) {
5672         case 5:
5673                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5674                 break;
5675         case 7:
5676                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5677                 break;
5678         case 10:
5679                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5680                 break;
5681         case 14:
5682                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5683                 break;
5684         }
5685
5686         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5687                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5688         else
5689                 dpll |= PLL_REF_INPUT_DREFCLK;
5690
5691         return dpll | DPLL_VCO_ENABLE;
5692 }
5693
5694 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5695                                   int x, int y,
5696                                   struct drm_framebuffer *fb)
5697 {
5698         struct drm_device *dev = crtc->dev;
5699         struct drm_i915_private *dev_priv = dev->dev_private;
5700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5701         int pipe = intel_crtc->pipe;
5702         int plane = intel_crtc->plane;
5703         int num_connectors = 0;
5704         intel_clock_t clock, reduced_clock;
5705         u32 dpll = 0, fp = 0, fp2 = 0;
5706         bool ok, has_reduced_clock = false;
5707         bool is_lvds = false;
5708         struct intel_encoder *encoder;
5709         struct intel_shared_dpll *pll;
5710         int ret;
5711
5712         for_each_encoder_on_crtc(dev, crtc, encoder) {
5713                 switch (encoder->type) {
5714                 case INTEL_OUTPUT_LVDS:
5715                         is_lvds = true;
5716                         break;
5717                 }
5718
5719                 num_connectors++;
5720         }
5721
5722         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5723              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5724
5725         ok = ironlake_compute_clocks(crtc, &clock,
5726                                      &has_reduced_clock, &reduced_clock);
5727         if (!ok && !intel_crtc->config.clock_set) {
5728                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5729                 return -EINVAL;
5730         }
5731         /* Compat-code for transition, will disappear. */
5732         if (!intel_crtc->config.clock_set) {
5733                 intel_crtc->config.dpll.n = clock.n;
5734                 intel_crtc->config.dpll.m1 = clock.m1;
5735                 intel_crtc->config.dpll.m2 = clock.m2;
5736                 intel_crtc->config.dpll.p1 = clock.p1;
5737                 intel_crtc->config.dpll.p2 = clock.p2;
5738         }
5739
5740         /* Ensure that the cursor is valid for the new mode before changing... */
5741         intel_crtc_update_cursor(crtc, true);
5742
5743         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5744         if (intel_crtc->config.has_pch_encoder) {
5745                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5746                 if (has_reduced_clock)
5747                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5748
5749                 dpll = ironlake_compute_dpll(intel_crtc,
5750                                              &fp, &reduced_clock,
5751                                              has_reduced_clock ? &fp2 : NULL);
5752
5753                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5754                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5755                 if (has_reduced_clock)
5756                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5757                 else
5758                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5759
5760                 pll = intel_get_shared_dpll(intel_crtc);
5761                 if (pll == NULL) {
5762                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5763                                          pipe_name(pipe));
5764                         return -EINVAL;
5765                 }
5766         } else
5767                 intel_put_shared_dpll(intel_crtc);
5768
5769         if (intel_crtc->config.has_dp_encoder)
5770                 intel_dp_set_m_n(intel_crtc);
5771
5772         if (is_lvds && has_reduced_clock && i915_powersave)
5773                 intel_crtc->lowfreq_avail = true;
5774         else
5775                 intel_crtc->lowfreq_avail = false;
5776
5777         if (intel_crtc->config.has_pch_encoder) {
5778                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5779
5780         }
5781
5782         intel_set_pipe_timings(intel_crtc);
5783
5784         if (intel_crtc->config.has_pch_encoder) {
5785                 intel_cpu_transcoder_set_m_n(intel_crtc,
5786                                              &intel_crtc->config.fdi_m_n);
5787         }
5788
5789         if (IS_IVYBRIDGE(dev))
5790                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5791
5792         ironlake_set_pipeconf(crtc);
5793
5794         /* Set up the display plane register */
5795         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5796         POSTING_READ(DSPCNTR(plane));
5797
5798         ret = intel_pipe_set_base(crtc, x, y, fb);
5799
5800         intel_update_watermarks(dev);
5801
5802         return ret;
5803 }
5804
5805 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5806                                         struct intel_crtc_config *pipe_config)
5807 {
5808         struct drm_device *dev = crtc->base.dev;
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         enum transcoder transcoder = pipe_config->cpu_transcoder;
5811
5812         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5813         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5814         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5815                                         & ~TU_SIZE_MASK;
5816         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5817         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5818                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5819 }
5820
5821 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5822                                      struct intel_crtc_config *pipe_config)
5823 {
5824         struct drm_device *dev = crtc->base.dev;
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         uint32_t tmp;
5827
5828         tmp = I915_READ(PF_CTL(crtc->pipe));
5829
5830         if (tmp & PF_ENABLE) {
5831                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5832                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5833
5834                 /* We currently do not free assignements of panel fitters on
5835                  * ivb/hsw (since we don't use the higher upscaling modes which
5836                  * differentiates them) so just WARN about this case for now. */
5837                 if (IS_GEN7(dev)) {
5838                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5839                                 PF_PIPE_SEL_IVB(crtc->pipe));
5840                 }
5841         }
5842 }
5843
5844 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5845                                      struct intel_crtc_config *pipe_config)
5846 {
5847         struct drm_device *dev = crtc->base.dev;
5848         struct drm_i915_private *dev_priv = dev->dev_private;
5849         uint32_t tmp;
5850
5851         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5852         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5853
5854         tmp = I915_READ(PIPECONF(crtc->pipe));
5855         if (!(tmp & PIPECONF_ENABLE))
5856                 return false;
5857
5858         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5859                 struct intel_shared_dpll *pll;
5860
5861                 pipe_config->has_pch_encoder = true;
5862
5863                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5864                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5865                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5866
5867                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5868
5869                 if (HAS_PCH_IBX(dev_priv->dev)) {
5870                         pipe_config->shared_dpll =
5871                                 (enum intel_dpll_id) crtc->pipe;
5872                 } else {
5873                         tmp = I915_READ(PCH_DPLL_SEL);
5874                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5875                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5876                         else
5877                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5878                 }
5879
5880                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5881
5882                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5883                                            &pipe_config->dpll_hw_state));
5884
5885                 tmp = pipe_config->dpll_hw_state.dpll;
5886                 pipe_config->pixel_multiplier =
5887                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5888                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5889         } else {
5890                 pipe_config->pixel_multiplier = 1;
5891         }
5892
5893         intel_get_pipe_timings(crtc, pipe_config);
5894
5895         ironlake_get_pfit_config(crtc, pipe_config);
5896
5897         return true;
5898 }
5899
5900 static void haswell_modeset_global_resources(struct drm_device *dev)
5901 {
5902         bool enable = false;
5903         struct intel_crtc *crtc;
5904
5905         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5906                 if (!crtc->base.enabled)
5907                         continue;
5908
5909                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5910                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5911                         enable = true;
5912         }
5913
5914         intel_set_power_well(dev, enable);
5915 }
5916
5917 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5918                                  int x, int y,
5919                                  struct drm_framebuffer *fb)
5920 {
5921         struct drm_device *dev = crtc->dev;
5922         struct drm_i915_private *dev_priv = dev->dev_private;
5923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5924         int plane = intel_crtc->plane;
5925         int ret;
5926
5927         if (!intel_ddi_pll_mode_set(crtc))
5928                 return -EINVAL;
5929
5930         /* Ensure that the cursor is valid for the new mode before changing... */
5931         intel_crtc_update_cursor(crtc, true);
5932
5933         if (intel_crtc->config.has_dp_encoder)
5934                 intel_dp_set_m_n(intel_crtc);
5935
5936         intel_crtc->lowfreq_avail = false;
5937
5938         intel_set_pipe_timings(intel_crtc);
5939
5940         if (intel_crtc->config.has_pch_encoder) {
5941                 intel_cpu_transcoder_set_m_n(intel_crtc,
5942                                              &intel_crtc->config.fdi_m_n);
5943         }
5944
5945         haswell_set_pipeconf(crtc);
5946
5947         intel_set_pipe_csc(crtc);
5948
5949         /* Set up the display plane register */
5950         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5951         POSTING_READ(DSPCNTR(plane));
5952
5953         ret = intel_pipe_set_base(crtc, x, y, fb);
5954
5955         intel_update_watermarks(dev);
5956
5957         return ret;
5958 }
5959
5960 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5961                                     struct intel_crtc_config *pipe_config)
5962 {
5963         struct drm_device *dev = crtc->base.dev;
5964         struct drm_i915_private *dev_priv = dev->dev_private;
5965         enum intel_display_power_domain pfit_domain;
5966         uint32_t tmp;
5967
5968         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5969         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5970
5971         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5972         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5973                 enum pipe trans_edp_pipe;
5974                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5975                 default:
5976                         WARN(1, "unknown pipe linked to edp transcoder\n");
5977                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5978                 case TRANS_DDI_EDP_INPUT_A_ON:
5979                         trans_edp_pipe = PIPE_A;
5980                         break;
5981                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5982                         trans_edp_pipe = PIPE_B;
5983                         break;
5984                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5985                         trans_edp_pipe = PIPE_C;
5986                         break;
5987                 }
5988
5989                 if (trans_edp_pipe == crtc->pipe)
5990                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5991         }
5992
5993         if (!intel_display_power_enabled(dev,
5994                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5995                 return false;
5996
5997         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5998         if (!(tmp & PIPECONF_ENABLE))
5999                 return false;
6000
6001         /*
6002          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6003          * DDI E. So just check whether this pipe is wired to DDI E and whether
6004          * the PCH transcoder is on.
6005          */
6006         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6007         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6008             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6009                 pipe_config->has_pch_encoder = true;
6010
6011                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6012                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6013                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6014
6015                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6016         }
6017
6018         intel_get_pipe_timings(crtc, pipe_config);
6019
6020         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6021         if (intel_display_power_enabled(dev, pfit_domain))
6022                 ironlake_get_pfit_config(crtc, pipe_config);
6023
6024         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6025                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6026
6027         pipe_config->pixel_multiplier = 1;
6028
6029         return true;
6030 }
6031
6032 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6033                                int x, int y,
6034                                struct drm_framebuffer *fb)
6035 {
6036         struct drm_device *dev = crtc->dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         struct drm_encoder_helper_funcs *encoder_funcs;
6039         struct intel_encoder *encoder;
6040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6041         struct drm_display_mode *adjusted_mode =
6042                 &intel_crtc->config.adjusted_mode;
6043         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6044         int pipe = intel_crtc->pipe;
6045         int ret;
6046
6047         drm_vblank_pre_modeset(dev, pipe);
6048
6049         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6050
6051         drm_vblank_post_modeset(dev, pipe);
6052
6053         if (ret != 0)
6054                 return ret;
6055
6056         for_each_encoder_on_crtc(dev, crtc, encoder) {
6057                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6058                         encoder->base.base.id,
6059                         drm_get_encoder_name(&encoder->base),
6060                         mode->base.id, mode->name);
6061                 if (encoder->mode_set) {
6062                         encoder->mode_set(encoder);
6063                 } else {
6064                         encoder_funcs = encoder->base.helper_private;
6065                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6066                 }
6067         }
6068
6069         return 0;
6070 }
6071
6072 static bool intel_eld_uptodate(struct drm_connector *connector,
6073                                int reg_eldv, uint32_t bits_eldv,
6074                                int reg_elda, uint32_t bits_elda,
6075                                int reg_edid)
6076 {
6077         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078         uint8_t *eld = connector->eld;
6079         uint32_t i;
6080
6081         i = I915_READ(reg_eldv);
6082         i &= bits_eldv;
6083
6084         if (!eld[0])
6085                 return !i;
6086
6087         if (!i)
6088                 return false;
6089
6090         i = I915_READ(reg_elda);
6091         i &= ~bits_elda;
6092         I915_WRITE(reg_elda, i);
6093
6094         for (i = 0; i < eld[2]; i++)
6095                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6096                         return false;
6097
6098         return true;
6099 }
6100
6101 static void g4x_write_eld(struct drm_connector *connector,
6102                           struct drm_crtc *crtc)
6103 {
6104         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6105         uint8_t *eld = connector->eld;
6106         uint32_t eldv;
6107         uint32_t len;
6108         uint32_t i;
6109
6110         i = I915_READ(G4X_AUD_VID_DID);
6111
6112         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6113                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6114         else
6115                 eldv = G4X_ELDV_DEVCTG;
6116
6117         if (intel_eld_uptodate(connector,
6118                                G4X_AUD_CNTL_ST, eldv,
6119                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6120                                G4X_HDMIW_HDMIEDID))
6121                 return;
6122
6123         i = I915_READ(G4X_AUD_CNTL_ST);
6124         i &= ~(eldv | G4X_ELD_ADDR);
6125         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6126         I915_WRITE(G4X_AUD_CNTL_ST, i);
6127
6128         if (!eld[0])
6129                 return;
6130
6131         len = min_t(uint8_t, eld[2], len);
6132         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6133         for (i = 0; i < len; i++)
6134                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6135
6136         i = I915_READ(G4X_AUD_CNTL_ST);
6137         i |= eldv;
6138         I915_WRITE(G4X_AUD_CNTL_ST, i);
6139 }
6140
6141 static void haswell_write_eld(struct drm_connector *connector,
6142                                      struct drm_crtc *crtc)
6143 {
6144         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6145         uint8_t *eld = connector->eld;
6146         struct drm_device *dev = crtc->dev;
6147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148         uint32_t eldv;
6149         uint32_t i;
6150         int len;
6151         int pipe = to_intel_crtc(crtc)->pipe;
6152         int tmp;
6153
6154         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6155         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6156         int aud_config = HSW_AUD_CFG(pipe);
6157         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6158
6159
6160         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6161
6162         /* Audio output enable */
6163         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6164         tmp = I915_READ(aud_cntrl_st2);
6165         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6166         I915_WRITE(aud_cntrl_st2, tmp);
6167
6168         /* Wait for 1 vertical blank */
6169         intel_wait_for_vblank(dev, pipe);
6170
6171         /* Set ELD valid state */
6172         tmp = I915_READ(aud_cntrl_st2);
6173         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6174         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6175         I915_WRITE(aud_cntrl_st2, tmp);
6176         tmp = I915_READ(aud_cntrl_st2);
6177         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6178
6179         /* Enable HDMI mode */
6180         tmp = I915_READ(aud_config);
6181         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6182         /* clear N_programing_enable and N_value_index */
6183         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6184         I915_WRITE(aud_config, tmp);
6185
6186         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6187
6188         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6189         intel_crtc->eld_vld = true;
6190
6191         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6192                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6193                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6194                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6195         } else
6196                 I915_WRITE(aud_config, 0);
6197
6198         if (intel_eld_uptodate(connector,
6199                                aud_cntrl_st2, eldv,
6200                                aud_cntl_st, IBX_ELD_ADDRESS,
6201                                hdmiw_hdmiedid))
6202                 return;
6203
6204         i = I915_READ(aud_cntrl_st2);
6205         i &= ~eldv;
6206         I915_WRITE(aud_cntrl_st2, i);
6207
6208         if (!eld[0])
6209                 return;
6210
6211         i = I915_READ(aud_cntl_st);
6212         i &= ~IBX_ELD_ADDRESS;
6213         I915_WRITE(aud_cntl_st, i);
6214         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6215         DRM_DEBUG_DRIVER("port num:%d\n", i);
6216
6217         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6218         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6219         for (i = 0; i < len; i++)
6220                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6221
6222         i = I915_READ(aud_cntrl_st2);
6223         i |= eldv;
6224         I915_WRITE(aud_cntrl_st2, i);
6225
6226 }
6227
6228 static void ironlake_write_eld(struct drm_connector *connector,
6229                                      struct drm_crtc *crtc)
6230 {
6231         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6232         uint8_t *eld = connector->eld;
6233         uint32_t eldv;
6234         uint32_t i;
6235         int len;
6236         int hdmiw_hdmiedid;
6237         int aud_config;
6238         int aud_cntl_st;
6239         int aud_cntrl_st2;
6240         int pipe = to_intel_crtc(crtc)->pipe;
6241
6242         if (HAS_PCH_IBX(connector->dev)) {
6243                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6244                 aud_config = IBX_AUD_CFG(pipe);
6245                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6246                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6247         } else {
6248                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6249                 aud_config = CPT_AUD_CFG(pipe);
6250                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6251                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6252         }
6253
6254         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6255
6256         i = I915_READ(aud_cntl_st);
6257         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6258         if (!i) {
6259                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6260                 /* operate blindly on all ports */
6261                 eldv = IBX_ELD_VALIDB;
6262                 eldv |= IBX_ELD_VALIDB << 4;
6263                 eldv |= IBX_ELD_VALIDB << 8;
6264         } else {
6265                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6266                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6267         }
6268
6269         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6270                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6271                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6272                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6273         } else
6274                 I915_WRITE(aud_config, 0);
6275
6276         if (intel_eld_uptodate(connector,
6277                                aud_cntrl_st2, eldv,
6278                                aud_cntl_st, IBX_ELD_ADDRESS,
6279                                hdmiw_hdmiedid))
6280                 return;
6281
6282         i = I915_READ(aud_cntrl_st2);
6283         i &= ~eldv;
6284         I915_WRITE(aud_cntrl_st2, i);
6285
6286         if (!eld[0])
6287                 return;
6288
6289         i = I915_READ(aud_cntl_st);
6290         i &= ~IBX_ELD_ADDRESS;
6291         I915_WRITE(aud_cntl_st, i);
6292
6293         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6294         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6295         for (i = 0; i < len; i++)
6296                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6297
6298         i = I915_READ(aud_cntrl_st2);
6299         i |= eldv;
6300         I915_WRITE(aud_cntrl_st2, i);
6301 }
6302
6303 void intel_write_eld(struct drm_encoder *encoder,
6304                      struct drm_display_mode *mode)
6305 {
6306         struct drm_crtc *crtc = encoder->crtc;
6307         struct drm_connector *connector;
6308         struct drm_device *dev = encoder->dev;
6309         struct drm_i915_private *dev_priv = dev->dev_private;
6310
6311         connector = drm_select_eld(encoder, mode);
6312         if (!connector)
6313                 return;
6314
6315         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6316                          connector->base.id,
6317                          drm_get_connector_name(connector),
6318                          connector->encoder->base.id,
6319                          drm_get_encoder_name(connector->encoder));
6320
6321         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6322
6323         if (dev_priv->display.write_eld)
6324                 dev_priv->display.write_eld(connector, crtc);
6325 }
6326
6327 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6328 void intel_crtc_load_lut(struct drm_crtc *crtc)
6329 {
6330         struct drm_device *dev = crtc->dev;
6331         struct drm_i915_private *dev_priv = dev->dev_private;
6332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6333         enum pipe pipe = intel_crtc->pipe;
6334         int palreg = PALETTE(pipe);
6335         int i;
6336         bool reenable_ips = false;
6337
6338         /* The clocks have to be on to load the palette. */
6339         if (!crtc->enabled || !intel_crtc->active)
6340                 return;
6341
6342         if (!HAS_PCH_SPLIT(dev_priv->dev))
6343                 assert_pll_enabled(dev_priv, pipe);
6344
6345         /* use legacy palette for Ironlake */
6346         if (HAS_PCH_SPLIT(dev))
6347                 palreg = LGC_PALETTE(pipe);
6348
6349         /* Workaround : Do not read or write the pipe palette/gamma data while
6350          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6351          */
6352         if (intel_crtc->config.ips_enabled &&
6353             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6354              GAMMA_MODE_MODE_SPLIT)) {
6355                 hsw_disable_ips(intel_crtc);
6356                 reenable_ips = true;
6357         }
6358
6359         for (i = 0; i < 256; i++) {
6360                 I915_WRITE(palreg + 4 * i,
6361                            (intel_crtc->lut_r[i] << 16) |
6362                            (intel_crtc->lut_g[i] << 8) |
6363                            intel_crtc->lut_b[i]);
6364         }
6365
6366         if (reenable_ips)
6367                 hsw_enable_ips(intel_crtc);
6368 }
6369
6370 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6371 {
6372         struct drm_device *dev = crtc->dev;
6373         struct drm_i915_private *dev_priv = dev->dev_private;
6374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375         bool visible = base != 0;
6376         u32 cntl;
6377
6378         if (intel_crtc->cursor_visible == visible)
6379                 return;
6380
6381         cntl = I915_READ(_CURACNTR);
6382         if (visible) {
6383                 /* On these chipsets we can only modify the base whilst
6384                  * the cursor is disabled.
6385                  */
6386                 I915_WRITE(_CURABASE, base);
6387
6388                 cntl &= ~(CURSOR_FORMAT_MASK);
6389                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6390                 cntl |= CURSOR_ENABLE |
6391                         CURSOR_GAMMA_ENABLE |
6392                         CURSOR_FORMAT_ARGB;
6393         } else
6394                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6395         I915_WRITE(_CURACNTR, cntl);
6396
6397         intel_crtc->cursor_visible = visible;
6398 }
6399
6400 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6401 {
6402         struct drm_device *dev = crtc->dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405         int pipe = intel_crtc->pipe;
6406         bool visible = base != 0;
6407
6408         if (intel_crtc->cursor_visible != visible) {
6409                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6410                 if (base) {
6411                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6412                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6413                         cntl |= pipe << 28; /* Connect to correct pipe */
6414                 } else {
6415                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6416                         cntl |= CURSOR_MODE_DISABLE;
6417                 }
6418                 I915_WRITE(CURCNTR(pipe), cntl);
6419
6420                 intel_crtc->cursor_visible = visible;
6421         }
6422         /* and commit changes on next vblank */
6423         I915_WRITE(CURBASE(pipe), base);
6424 }
6425
6426 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6427 {
6428         struct drm_device *dev = crtc->dev;
6429         struct drm_i915_private *dev_priv = dev->dev_private;
6430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431         int pipe = intel_crtc->pipe;
6432         bool visible = base != 0;
6433
6434         if (intel_crtc->cursor_visible != visible) {
6435                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6436                 if (base) {
6437                         cntl &= ~CURSOR_MODE;
6438                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6439                 } else {
6440                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6441                         cntl |= CURSOR_MODE_DISABLE;
6442                 }
6443                 if (IS_HASWELL(dev))
6444                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6445                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6446
6447                 intel_crtc->cursor_visible = visible;
6448         }
6449         /* and commit changes on next vblank */
6450         I915_WRITE(CURBASE_IVB(pipe), base);
6451 }
6452
6453 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6454 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6455                                      bool on)
6456 {
6457         struct drm_device *dev = crtc->dev;
6458         struct drm_i915_private *dev_priv = dev->dev_private;
6459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6460         int pipe = intel_crtc->pipe;
6461         int x = intel_crtc->cursor_x;
6462         int y = intel_crtc->cursor_y;
6463         u32 base, pos;
6464         bool visible;
6465
6466         pos = 0;
6467
6468         if (on && crtc->enabled && crtc->fb) {
6469                 base = intel_crtc->cursor_addr;
6470                 if (x > (int) crtc->fb->width)
6471                         base = 0;
6472
6473                 if (y > (int) crtc->fb->height)
6474                         base = 0;
6475         } else
6476                 base = 0;
6477
6478         if (x < 0) {
6479                 if (x + intel_crtc->cursor_width < 0)
6480                         base = 0;
6481
6482                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6483                 x = -x;
6484         }
6485         pos |= x << CURSOR_X_SHIFT;
6486
6487         if (y < 0) {
6488                 if (y + intel_crtc->cursor_height < 0)
6489                         base = 0;
6490
6491                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6492                 y = -y;
6493         }
6494         pos |= y << CURSOR_Y_SHIFT;
6495
6496         visible = base != 0;
6497         if (!visible && !intel_crtc->cursor_visible)
6498                 return;
6499
6500         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6501                 I915_WRITE(CURPOS_IVB(pipe), pos);
6502                 ivb_update_cursor(crtc, base);
6503         } else {
6504                 I915_WRITE(CURPOS(pipe), pos);
6505                 if (IS_845G(dev) || IS_I865G(dev))
6506                         i845_update_cursor(crtc, base);
6507                 else
6508                         i9xx_update_cursor(crtc, base);
6509         }
6510 }
6511
6512 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6513                                  struct drm_file *file,
6514                                  uint32_t handle,
6515                                  uint32_t width, uint32_t height)
6516 {
6517         struct drm_device *dev = crtc->dev;
6518         struct drm_i915_private *dev_priv = dev->dev_private;
6519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6520         struct drm_i915_gem_object *obj;
6521         uint32_t addr;
6522         int ret;
6523
6524         /* if we want to turn off the cursor ignore width and height */
6525         if (!handle) {
6526                 DRM_DEBUG_KMS("cursor off\n");
6527                 addr = 0;
6528                 obj = NULL;
6529                 mutex_lock(&dev->struct_mutex);
6530                 goto finish;
6531         }
6532
6533         /* Currently we only support 64x64 cursors */
6534         if (width != 64 || height != 64) {
6535                 DRM_ERROR("we currently only support 64x64 cursors\n");
6536                 return -EINVAL;
6537         }
6538
6539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6540         if (&obj->base == NULL)
6541                 return -ENOENT;
6542
6543         if (obj->base.size < width * height * 4) {
6544                 DRM_ERROR("buffer is to small\n");
6545                 ret = -ENOMEM;
6546                 goto fail;
6547         }
6548
6549         /* we only need to pin inside GTT if cursor is non-phy */
6550         mutex_lock(&dev->struct_mutex);
6551         if (!dev_priv->info->cursor_needs_physical) {
6552                 unsigned alignment;
6553
6554                 if (obj->tiling_mode) {
6555                         DRM_ERROR("cursor cannot be tiled\n");
6556                         ret = -EINVAL;
6557                         goto fail_locked;
6558                 }
6559
6560                 /* Note that the w/a also requires 2 PTE of padding following
6561                  * the bo. We currently fill all unused PTE with the shadow
6562                  * page and so we should always have valid PTE following the
6563                  * cursor preventing the VT-d warning.
6564                  */
6565                 alignment = 0;
6566                 if (need_vtd_wa(dev))
6567                         alignment = 64*1024;
6568
6569                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6570                 if (ret) {
6571                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6572                         goto fail_locked;
6573                 }
6574
6575                 ret = i915_gem_object_put_fence(obj);
6576                 if (ret) {
6577                         DRM_ERROR("failed to release fence for cursor");
6578                         goto fail_unpin;
6579                 }
6580
6581                 addr = i915_gem_obj_ggtt_offset(obj);
6582         } else {
6583                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6584                 ret = i915_gem_attach_phys_object(dev, obj,
6585                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6586                                                   align);
6587                 if (ret) {
6588                         DRM_ERROR("failed to attach phys object\n");
6589                         goto fail_locked;
6590                 }
6591                 addr = obj->phys_obj->handle->busaddr;
6592         }
6593
6594         if (IS_GEN2(dev))
6595                 I915_WRITE(CURSIZE, (height << 12) | width);
6596
6597  finish:
6598         if (intel_crtc->cursor_bo) {
6599                 if (dev_priv->info->cursor_needs_physical) {
6600                         if (intel_crtc->cursor_bo != obj)
6601                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6602                 } else
6603                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6604                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6605         }
6606
6607         mutex_unlock(&dev->struct_mutex);
6608
6609         intel_crtc->cursor_addr = addr;
6610         intel_crtc->cursor_bo = obj;
6611         intel_crtc->cursor_width = width;
6612         intel_crtc->cursor_height = height;
6613
6614         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6615
6616         return 0;
6617 fail_unpin:
6618         i915_gem_object_unpin(obj);
6619 fail_locked:
6620         mutex_unlock(&dev->struct_mutex);
6621 fail:
6622         drm_gem_object_unreference_unlocked(&obj->base);
6623         return ret;
6624 }
6625
6626 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6627 {
6628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6629
6630         intel_crtc->cursor_x = x;
6631         intel_crtc->cursor_y = y;
6632
6633         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6634
6635         return 0;
6636 }
6637
6638 /** Sets the color ramps on behalf of RandR */
6639 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6640                                  u16 blue, int regno)
6641 {
6642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643
6644         intel_crtc->lut_r[regno] = red >> 8;
6645         intel_crtc->lut_g[regno] = green >> 8;
6646         intel_crtc->lut_b[regno] = blue >> 8;
6647 }
6648
6649 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6650                              u16 *blue, int regno)
6651 {
6652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6653
6654         *red = intel_crtc->lut_r[regno] << 8;
6655         *green = intel_crtc->lut_g[regno] << 8;
6656         *blue = intel_crtc->lut_b[regno] << 8;
6657 }
6658
6659 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6660                                  u16 *blue, uint32_t start, uint32_t size)
6661 {
6662         int end = (start + size > 256) ? 256 : start + size, i;
6663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664
6665         for (i = start; i < end; i++) {
6666                 intel_crtc->lut_r[i] = red[i] >> 8;
6667                 intel_crtc->lut_g[i] = green[i] >> 8;
6668                 intel_crtc->lut_b[i] = blue[i] >> 8;
6669         }
6670
6671         intel_crtc_load_lut(crtc);
6672 }
6673
6674 /* VESA 640x480x72Hz mode to set on the pipe */
6675 static struct drm_display_mode load_detect_mode = {
6676         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6677                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6678 };
6679
6680 static struct drm_framebuffer *
6681 intel_framebuffer_create(struct drm_device *dev,
6682                          struct drm_mode_fb_cmd2 *mode_cmd,
6683                          struct drm_i915_gem_object *obj)
6684 {
6685         struct intel_framebuffer *intel_fb;
6686         int ret;
6687
6688         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6689         if (!intel_fb) {
6690                 drm_gem_object_unreference_unlocked(&obj->base);
6691                 return ERR_PTR(-ENOMEM);
6692         }
6693
6694         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6695         if (ret) {
6696                 drm_gem_object_unreference_unlocked(&obj->base);
6697                 kfree(intel_fb);
6698                 return ERR_PTR(ret);
6699         }
6700
6701         return &intel_fb->base;
6702 }
6703
6704 static u32
6705 intel_framebuffer_pitch_for_width(int width, int bpp)
6706 {
6707         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6708         return ALIGN(pitch, 64);
6709 }
6710
6711 static u32
6712 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6713 {
6714         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6715         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6716 }
6717
6718 static struct drm_framebuffer *
6719 intel_framebuffer_create_for_mode(struct drm_device *dev,
6720                                   struct drm_display_mode *mode,
6721                                   int depth, int bpp)
6722 {
6723         struct drm_i915_gem_object *obj;
6724         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6725
6726         obj = i915_gem_alloc_object(dev,
6727                                     intel_framebuffer_size_for_mode(mode, bpp));
6728         if (obj == NULL)
6729                 return ERR_PTR(-ENOMEM);
6730
6731         mode_cmd.width = mode->hdisplay;
6732         mode_cmd.height = mode->vdisplay;
6733         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6734                                                                 bpp);
6735         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6736
6737         return intel_framebuffer_create(dev, &mode_cmd, obj);
6738 }
6739
6740 static struct drm_framebuffer *
6741 mode_fits_in_fbdev(struct drm_device *dev,
6742                    struct drm_display_mode *mode)
6743 {
6744         struct drm_i915_private *dev_priv = dev->dev_private;
6745         struct drm_i915_gem_object *obj;
6746         struct drm_framebuffer *fb;
6747
6748         if (dev_priv->fbdev == NULL)
6749                 return NULL;
6750
6751         obj = dev_priv->fbdev->ifb.obj;
6752         if (obj == NULL)
6753                 return NULL;
6754
6755         fb = &dev_priv->fbdev->ifb.base;
6756         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6757                                                                fb->bits_per_pixel))
6758                 return NULL;
6759
6760         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6761                 return NULL;
6762
6763         return fb;
6764 }
6765
6766 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6767                                 struct drm_display_mode *mode,
6768                                 struct intel_load_detect_pipe *old)
6769 {
6770         struct intel_crtc *intel_crtc;
6771         struct intel_encoder *intel_encoder =
6772                 intel_attached_encoder(connector);
6773         struct drm_crtc *possible_crtc;
6774         struct drm_encoder *encoder = &intel_encoder->base;
6775         struct drm_crtc *crtc = NULL;
6776         struct drm_device *dev = encoder->dev;
6777         struct drm_framebuffer *fb;
6778         int i = -1;
6779
6780         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6781                       connector->base.id, drm_get_connector_name(connector),
6782                       encoder->base.id, drm_get_encoder_name(encoder));
6783
6784         /*
6785          * Algorithm gets a little messy:
6786          *
6787          *   - if the connector already has an assigned crtc, use it (but make
6788          *     sure it's on first)
6789          *
6790          *   - try to find the first unused crtc that can drive this connector,
6791          *     and use that if we find one
6792          */
6793
6794         /* See if we already have a CRTC for this connector */
6795         if (encoder->crtc) {
6796                 crtc = encoder->crtc;
6797
6798                 mutex_lock(&crtc->mutex);
6799
6800                 old->dpms_mode = connector->dpms;
6801                 old->load_detect_temp = false;
6802
6803                 /* Make sure the crtc and connector are running */
6804                 if (connector->dpms != DRM_MODE_DPMS_ON)
6805                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6806
6807                 return true;
6808         }
6809
6810         /* Find an unused one (if possible) */
6811         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6812                 i++;
6813                 if (!(encoder->possible_crtcs & (1 << i)))
6814                         continue;
6815                 if (!possible_crtc->enabled) {
6816                         crtc = possible_crtc;
6817                         break;
6818                 }
6819         }
6820
6821         /*
6822          * If we didn't find an unused CRTC, don't use any.
6823          */
6824         if (!crtc) {
6825                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6826                 return false;
6827         }
6828
6829         mutex_lock(&crtc->mutex);
6830         intel_encoder->new_crtc = to_intel_crtc(crtc);
6831         to_intel_connector(connector)->new_encoder = intel_encoder;
6832
6833         intel_crtc = to_intel_crtc(crtc);
6834         old->dpms_mode = connector->dpms;
6835         old->load_detect_temp = true;
6836         old->release_fb = NULL;
6837
6838         if (!mode)
6839                 mode = &load_detect_mode;
6840
6841         /* We need a framebuffer large enough to accommodate all accesses
6842          * that the plane may generate whilst we perform load detection.
6843          * We can not rely on the fbcon either being present (we get called
6844          * during its initialisation to detect all boot displays, or it may
6845          * not even exist) or that it is large enough to satisfy the
6846          * requested mode.
6847          */
6848         fb = mode_fits_in_fbdev(dev, mode);
6849         if (fb == NULL) {
6850                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6851                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6852                 old->release_fb = fb;
6853         } else
6854                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6855         if (IS_ERR(fb)) {
6856                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6857                 mutex_unlock(&crtc->mutex);
6858                 return false;
6859         }
6860
6861         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6862                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6863                 if (old->release_fb)
6864                         old->release_fb->funcs->destroy(old->release_fb);
6865                 mutex_unlock(&crtc->mutex);
6866                 return false;
6867         }
6868
6869         /* let the connector get through one full cycle before testing */
6870         intel_wait_for_vblank(dev, intel_crtc->pipe);
6871         return true;
6872 }
6873
6874 void intel_release_load_detect_pipe(struct drm_connector *connector,
6875                                     struct intel_load_detect_pipe *old)
6876 {
6877         struct intel_encoder *intel_encoder =
6878                 intel_attached_encoder(connector);
6879         struct drm_encoder *encoder = &intel_encoder->base;
6880         struct drm_crtc *crtc = encoder->crtc;
6881
6882         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6883                       connector->base.id, drm_get_connector_name(connector),
6884                       encoder->base.id, drm_get_encoder_name(encoder));
6885
6886         if (old->load_detect_temp) {
6887                 to_intel_connector(connector)->new_encoder = NULL;
6888                 intel_encoder->new_crtc = NULL;
6889                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6890
6891                 if (old->release_fb) {
6892                         drm_framebuffer_unregister_private(old->release_fb);
6893                         drm_framebuffer_unreference(old->release_fb);
6894                 }
6895
6896                 mutex_unlock(&crtc->mutex);
6897                 return;
6898         }
6899
6900         /* Switch crtc and encoder back off if necessary */
6901         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6902                 connector->funcs->dpms(connector, old->dpms_mode);
6903
6904         mutex_unlock(&crtc->mutex);
6905 }
6906
6907 /* Returns the clock of the currently programmed mode of the given pipe. */
6908 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6909                                 struct intel_crtc_config *pipe_config)
6910 {
6911         struct drm_device *dev = crtc->base.dev;
6912         struct drm_i915_private *dev_priv = dev->dev_private;
6913         int pipe = pipe_config->cpu_transcoder;
6914         u32 dpll = I915_READ(DPLL(pipe));
6915         u32 fp;
6916         intel_clock_t clock;
6917
6918         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6919                 fp = I915_READ(FP0(pipe));
6920         else
6921                 fp = I915_READ(FP1(pipe));
6922
6923         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6924         if (IS_PINEVIEW(dev)) {
6925                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6926                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6927         } else {
6928                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6929                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6930         }
6931
6932         if (!IS_GEN2(dev)) {
6933                 if (IS_PINEVIEW(dev))
6934                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6935                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6936                 else
6937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6938                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6939
6940                 switch (dpll & DPLL_MODE_MASK) {
6941                 case DPLLB_MODE_DAC_SERIAL:
6942                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6943                                 5 : 10;
6944                         break;
6945                 case DPLLB_MODE_LVDS:
6946                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6947                                 7 : 14;
6948                         break;
6949                 default:
6950                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6951                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6952                         pipe_config->adjusted_mode.clock = 0;
6953                         return;
6954                 }
6955
6956                 if (IS_PINEVIEW(dev))
6957                         pineview_clock(96000, &clock);
6958                 else
6959                         i9xx_clock(96000, &clock);
6960         } else {
6961                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6962
6963                 if (is_lvds) {
6964                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6965                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6966                         clock.p2 = 14;
6967
6968                         if ((dpll & PLL_REF_INPUT_MASK) ==
6969                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6970                                 /* XXX: might not be 66MHz */
6971                                 i9xx_clock(66000, &clock);
6972                         } else
6973                                 i9xx_clock(48000, &clock);
6974                 } else {
6975                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6976                                 clock.p1 = 2;
6977                         else {
6978                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6979                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6980                         }
6981                         if (dpll & PLL_P2_DIVIDE_BY_4)
6982                                 clock.p2 = 4;
6983                         else
6984                                 clock.p2 = 2;
6985
6986                         i9xx_clock(48000, &clock);
6987                 }
6988         }
6989
6990         pipe_config->adjusted_mode.clock = clock.dot *
6991                 pipe_config->pixel_multiplier;
6992 }
6993
6994 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6995                                     struct intel_crtc_config *pipe_config)
6996 {
6997         struct drm_device *dev = crtc->base.dev;
6998         struct drm_i915_private *dev_priv = dev->dev_private;
6999         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7000         int link_freq, repeat;
7001         u64 clock;
7002         u32 link_m, link_n;
7003
7004         repeat = pipe_config->pixel_multiplier;
7005
7006         /*
7007          * The calculation for the data clock is:
7008          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7009          * But we want to avoid losing precison if possible, so:
7010          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7011          *
7012          * and the link clock is simpler:
7013          * link_clock = (m * link_clock * repeat) / n
7014          */
7015
7016         /*
7017          * We need to get the FDI or DP link clock here to derive
7018          * the M/N dividers.
7019          *
7020          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7021          * For DP, it's either 1.62GHz or 2.7GHz.
7022          * We do our calculations in 10*MHz since we don't need much precison.
7023          */
7024         if (pipe_config->has_pch_encoder)
7025                 link_freq = intel_fdi_link_freq(dev) * 10000;
7026         else
7027                 link_freq = pipe_config->port_clock;
7028
7029         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7030         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7031
7032         if (!link_m || !link_n)
7033                 return;
7034
7035         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7036         do_div(clock, link_n);
7037
7038         pipe_config->adjusted_mode.clock = clock;
7039 }
7040
7041 /** Returns the currently programmed mode of the given pipe. */
7042 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7043                                              struct drm_crtc *crtc)
7044 {
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7048         struct drm_display_mode *mode;
7049         struct intel_crtc_config pipe_config;
7050         int htot = I915_READ(HTOTAL(cpu_transcoder));
7051         int hsync = I915_READ(HSYNC(cpu_transcoder));
7052         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7053         int vsync = I915_READ(VSYNC(cpu_transcoder));
7054
7055         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7056         if (!mode)
7057                 return NULL;
7058
7059         /*
7060          * Construct a pipe_config sufficient for getting the clock info
7061          * back out of crtc_clock_get.
7062          *
7063          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7064          * to use a real value here instead.
7065          */
7066         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7067         pipe_config.pixel_multiplier = 1;
7068         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7069
7070         mode->clock = pipe_config.adjusted_mode.clock;
7071         mode->hdisplay = (htot & 0xffff) + 1;
7072         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7073         mode->hsync_start = (hsync & 0xffff) + 1;
7074         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7075         mode->vdisplay = (vtot & 0xffff) + 1;
7076         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7077         mode->vsync_start = (vsync & 0xffff) + 1;
7078         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7079
7080         drm_mode_set_name(mode);
7081
7082         return mode;
7083 }
7084
7085 static void intel_increase_pllclock(struct drm_crtc *crtc)
7086 {
7087         struct drm_device *dev = crtc->dev;
7088         drm_i915_private_t *dev_priv = dev->dev_private;
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090         int pipe = intel_crtc->pipe;
7091         int dpll_reg = DPLL(pipe);
7092         int dpll;
7093
7094         if (HAS_PCH_SPLIT(dev))
7095                 return;
7096
7097         if (!dev_priv->lvds_downclock_avail)
7098                 return;
7099
7100         dpll = I915_READ(dpll_reg);
7101         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7102                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7103
7104                 assert_panel_unlocked(dev_priv, pipe);
7105
7106                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7107                 I915_WRITE(dpll_reg, dpll);
7108                 intel_wait_for_vblank(dev, pipe);
7109
7110                 dpll = I915_READ(dpll_reg);
7111                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7112                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7113         }
7114 }
7115
7116 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7117 {
7118         struct drm_device *dev = crtc->dev;
7119         drm_i915_private_t *dev_priv = dev->dev_private;
7120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7121
7122         if (HAS_PCH_SPLIT(dev))
7123                 return;
7124
7125         if (!dev_priv->lvds_downclock_avail)
7126                 return;
7127
7128         /*
7129          * Since this is called by a timer, we should never get here in
7130          * the manual case.
7131          */
7132         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7133                 int pipe = intel_crtc->pipe;
7134                 int dpll_reg = DPLL(pipe);
7135                 int dpll;
7136
7137                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7138
7139                 assert_panel_unlocked(dev_priv, pipe);
7140
7141                 dpll = I915_READ(dpll_reg);
7142                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7143                 I915_WRITE(dpll_reg, dpll);
7144                 intel_wait_for_vblank(dev, pipe);
7145                 dpll = I915_READ(dpll_reg);
7146                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7147                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7148         }
7149
7150 }
7151
7152 void intel_mark_busy(struct drm_device *dev)
7153 {
7154         i915_update_gfx_val(dev->dev_private);
7155 }
7156
7157 void intel_mark_idle(struct drm_device *dev)
7158 {
7159         struct drm_crtc *crtc;
7160
7161         if (!i915_powersave)
7162                 return;
7163
7164         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7165                 if (!crtc->fb)
7166                         continue;
7167
7168                 intel_decrease_pllclock(crtc);
7169         }
7170 }
7171
7172 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7173                         struct intel_ring_buffer *ring)
7174 {
7175         struct drm_device *dev = obj->base.dev;
7176         struct drm_crtc *crtc;
7177
7178         if (!i915_powersave)
7179                 return;
7180
7181         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7182                 if (!crtc->fb)
7183                         continue;
7184
7185                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7186                         continue;
7187
7188                 intel_increase_pllclock(crtc);
7189                 if (ring && intel_fbc_enabled(dev))
7190                         ring->fbc_dirty = true;
7191         }
7192 }
7193
7194 static void intel_crtc_destroy(struct drm_crtc *crtc)
7195 {
7196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7197         struct drm_device *dev = crtc->dev;
7198         struct intel_unpin_work *work;
7199         unsigned long flags;
7200
7201         spin_lock_irqsave(&dev->event_lock, flags);
7202         work = intel_crtc->unpin_work;
7203         intel_crtc->unpin_work = NULL;
7204         spin_unlock_irqrestore(&dev->event_lock, flags);
7205
7206         if (work) {
7207                 cancel_work_sync(&work->work);
7208                 kfree(work);
7209         }
7210
7211         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7212
7213         drm_crtc_cleanup(crtc);
7214
7215         kfree(intel_crtc);
7216 }
7217
7218 static void intel_unpin_work_fn(struct work_struct *__work)
7219 {
7220         struct intel_unpin_work *work =
7221                 container_of(__work, struct intel_unpin_work, work);
7222         struct drm_device *dev = work->crtc->dev;
7223
7224         mutex_lock(&dev->struct_mutex);
7225         intel_unpin_fb_obj(work->old_fb_obj);
7226         drm_gem_object_unreference(&work->pending_flip_obj->base);
7227         drm_gem_object_unreference(&work->old_fb_obj->base);
7228
7229         intel_update_fbc(dev);
7230         mutex_unlock(&dev->struct_mutex);
7231
7232         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7233         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7234
7235         kfree(work);
7236 }
7237
7238 static void do_intel_finish_page_flip(struct drm_device *dev,
7239                                       struct drm_crtc *crtc)
7240 {
7241         drm_i915_private_t *dev_priv = dev->dev_private;
7242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243         struct intel_unpin_work *work;
7244         unsigned long flags;
7245
7246         /* Ignore early vblank irqs */
7247         if (intel_crtc == NULL)
7248                 return;
7249
7250         spin_lock_irqsave(&dev->event_lock, flags);
7251         work = intel_crtc->unpin_work;
7252
7253         /* Ensure we don't miss a work->pending update ... */
7254         smp_rmb();
7255
7256         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7257                 spin_unlock_irqrestore(&dev->event_lock, flags);
7258                 return;
7259         }
7260
7261         /* and that the unpin work is consistent wrt ->pending. */
7262         smp_rmb();
7263
7264         intel_crtc->unpin_work = NULL;
7265
7266         if (work->event)
7267                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7268
7269         drm_vblank_put(dev, intel_crtc->pipe);
7270
7271         spin_unlock_irqrestore(&dev->event_lock, flags);
7272
7273         wake_up_all(&dev_priv->pending_flip_queue);
7274
7275         queue_work(dev_priv->wq, &work->work);
7276
7277         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7278 }
7279
7280 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7281 {
7282         drm_i915_private_t *dev_priv = dev->dev_private;
7283         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7284
7285         do_intel_finish_page_flip(dev, crtc);
7286 }
7287
7288 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7289 {
7290         drm_i915_private_t *dev_priv = dev->dev_private;
7291         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7292
7293         do_intel_finish_page_flip(dev, crtc);
7294 }
7295
7296 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7297 {
7298         drm_i915_private_t *dev_priv = dev->dev_private;
7299         struct intel_crtc *intel_crtc =
7300                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7301         unsigned long flags;
7302
7303         /* NB: An MMIO update of the plane base pointer will also
7304          * generate a page-flip completion irq, i.e. every modeset
7305          * is also accompanied by a spurious intel_prepare_page_flip().
7306          */
7307         spin_lock_irqsave(&dev->event_lock, flags);
7308         if (intel_crtc->unpin_work)
7309                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7310         spin_unlock_irqrestore(&dev->event_lock, flags);
7311 }
7312
7313 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7314 {
7315         /* Ensure that the work item is consistent when activating it ... */
7316         smp_wmb();
7317         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7318         /* and that it is marked active as soon as the irq could fire. */
7319         smp_wmb();
7320 }
7321
7322 static int intel_gen2_queue_flip(struct drm_device *dev,
7323                                  struct drm_crtc *crtc,
7324                                  struct drm_framebuffer *fb,
7325                                  struct drm_i915_gem_object *obj)
7326 {
7327         struct drm_i915_private *dev_priv = dev->dev_private;
7328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329         u32 flip_mask;
7330         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7331         int ret;
7332
7333         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7334         if (ret)
7335                 goto err;
7336
7337         ret = intel_ring_begin(ring, 6);
7338         if (ret)
7339                 goto err_unpin;
7340
7341         /* Can't queue multiple flips, so wait for the previous
7342          * one to finish before executing the next.
7343          */
7344         if (intel_crtc->plane)
7345                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7346         else
7347                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7348         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7349         intel_ring_emit(ring, MI_NOOP);
7350         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7351                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7352         intel_ring_emit(ring, fb->pitches[0]);
7353         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7354         intel_ring_emit(ring, 0); /* aux display base address, unused */
7355
7356         intel_mark_page_flip_active(intel_crtc);
7357         intel_ring_advance(ring);
7358         return 0;
7359
7360 err_unpin:
7361         intel_unpin_fb_obj(obj);
7362 err:
7363         return ret;
7364 }
7365
7366 static int intel_gen3_queue_flip(struct drm_device *dev,
7367                                  struct drm_crtc *crtc,
7368                                  struct drm_framebuffer *fb,
7369                                  struct drm_i915_gem_object *obj)
7370 {
7371         struct drm_i915_private *dev_priv = dev->dev_private;
7372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7373         u32 flip_mask;
7374         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7375         int ret;
7376
7377         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7378         if (ret)
7379                 goto err;
7380
7381         ret = intel_ring_begin(ring, 6);
7382         if (ret)
7383                 goto err_unpin;
7384
7385         if (intel_crtc->plane)
7386                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7387         else
7388                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7389         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7390         intel_ring_emit(ring, MI_NOOP);
7391         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7392                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7393         intel_ring_emit(ring, fb->pitches[0]);
7394         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7395         intel_ring_emit(ring, MI_NOOP);
7396
7397         intel_mark_page_flip_active(intel_crtc);
7398         intel_ring_advance(ring);
7399         return 0;
7400
7401 err_unpin:
7402         intel_unpin_fb_obj(obj);
7403 err:
7404         return ret;
7405 }
7406
7407 static int intel_gen4_queue_flip(struct drm_device *dev,
7408                                  struct drm_crtc *crtc,
7409                                  struct drm_framebuffer *fb,
7410                                  struct drm_i915_gem_object *obj)
7411 {
7412         struct drm_i915_private *dev_priv = dev->dev_private;
7413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7414         uint32_t pf, pipesrc;
7415         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7416         int ret;
7417
7418         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7419         if (ret)
7420                 goto err;
7421
7422         ret = intel_ring_begin(ring, 4);
7423         if (ret)
7424                 goto err_unpin;
7425
7426         /* i965+ uses the linear or tiled offsets from the
7427          * Display Registers (which do not change across a page-flip)
7428          * so we need only reprogram the base address.
7429          */
7430         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7431                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7432         intel_ring_emit(ring, fb->pitches[0]);
7433         intel_ring_emit(ring,
7434                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7435                         obj->tiling_mode);
7436
7437         /* XXX Enabling the panel-fitter across page-flip is so far
7438          * untested on non-native modes, so ignore it for now.
7439          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7440          */
7441         pf = 0;
7442         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7443         intel_ring_emit(ring, pf | pipesrc);
7444
7445         intel_mark_page_flip_active(intel_crtc);
7446         intel_ring_advance(ring);
7447         return 0;
7448
7449 err_unpin:
7450         intel_unpin_fb_obj(obj);
7451 err:
7452         return ret;
7453 }
7454
7455 static int intel_gen6_queue_flip(struct drm_device *dev,
7456                                  struct drm_crtc *crtc,
7457                                  struct drm_framebuffer *fb,
7458                                  struct drm_i915_gem_object *obj)
7459 {
7460         struct drm_i915_private *dev_priv = dev->dev_private;
7461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7462         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7463         uint32_t pf, pipesrc;
7464         int ret;
7465
7466         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7467         if (ret)
7468                 goto err;
7469
7470         ret = intel_ring_begin(ring, 4);
7471         if (ret)
7472                 goto err_unpin;
7473
7474         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7475                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7476         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7477         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7478
7479         /* Contrary to the suggestions in the documentation,
7480          * "Enable Panel Fitter" does not seem to be required when page
7481          * flipping with a non-native mode, and worse causes a normal
7482          * modeset to fail.
7483          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7484          */
7485         pf = 0;
7486         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7487         intel_ring_emit(ring, pf | pipesrc);
7488
7489         intel_mark_page_flip_active(intel_crtc);
7490         intel_ring_advance(ring);
7491         return 0;
7492
7493 err_unpin:
7494         intel_unpin_fb_obj(obj);
7495 err:
7496         return ret;
7497 }
7498
7499 /*
7500  * On gen7 we currently use the blit ring because (in early silicon at least)
7501  * the render ring doesn't give us interrpts for page flip completion, which
7502  * means clients will hang after the first flip is queued.  Fortunately the
7503  * blit ring generates interrupts properly, so use it instead.
7504  */
7505 static int intel_gen7_queue_flip(struct drm_device *dev,
7506                                  struct drm_crtc *crtc,
7507                                  struct drm_framebuffer *fb,
7508                                  struct drm_i915_gem_object *obj)
7509 {
7510         struct drm_i915_private *dev_priv = dev->dev_private;
7511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7512         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7513         uint32_t plane_bit = 0;
7514         int ret;
7515
7516         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7517         if (ret)
7518                 goto err;
7519
7520         switch(intel_crtc->plane) {
7521         case PLANE_A:
7522                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7523                 break;
7524         case PLANE_B:
7525                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7526                 break;
7527         case PLANE_C:
7528                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7529                 break;
7530         default:
7531                 WARN_ONCE(1, "unknown plane in flip command\n");
7532                 ret = -ENODEV;
7533                 goto err_unpin;
7534         }
7535
7536         ret = intel_ring_begin(ring, 4);
7537         if (ret)
7538                 goto err_unpin;
7539
7540         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7541         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7542         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7543         intel_ring_emit(ring, (MI_NOOP));
7544
7545         intel_mark_page_flip_active(intel_crtc);
7546         intel_ring_advance(ring);
7547         return 0;
7548
7549 err_unpin:
7550         intel_unpin_fb_obj(obj);
7551 err:
7552         return ret;
7553 }
7554
7555 static int intel_default_queue_flip(struct drm_device *dev,
7556                                     struct drm_crtc *crtc,
7557                                     struct drm_framebuffer *fb,
7558                                     struct drm_i915_gem_object *obj)
7559 {
7560         return -ENODEV;
7561 }
7562
7563 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7564                                 struct drm_framebuffer *fb,
7565                                 struct drm_pending_vblank_event *event)
7566 {
7567         struct drm_device *dev = crtc->dev;
7568         struct drm_i915_private *dev_priv = dev->dev_private;
7569         struct drm_framebuffer *old_fb = crtc->fb;
7570         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7572         struct intel_unpin_work *work;
7573         unsigned long flags;
7574         int ret;
7575
7576         /* Can't change pixel format via MI display flips. */
7577         if (fb->pixel_format != crtc->fb->pixel_format)
7578                 return -EINVAL;
7579
7580         /*
7581          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7582          * Note that pitch changes could also affect these register.
7583          */
7584         if (INTEL_INFO(dev)->gen > 3 &&
7585             (fb->offsets[0] != crtc->fb->offsets[0] ||
7586              fb->pitches[0] != crtc->fb->pitches[0]))
7587                 return -EINVAL;
7588
7589         work = kzalloc(sizeof *work, GFP_KERNEL);
7590         if (work == NULL)
7591                 return -ENOMEM;
7592
7593         work->event = event;
7594         work->crtc = crtc;
7595         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7596         INIT_WORK(&work->work, intel_unpin_work_fn);
7597
7598         ret = drm_vblank_get(dev, intel_crtc->pipe);
7599         if (ret)
7600                 goto free_work;
7601
7602         /* We borrow the event spin lock for protecting unpin_work */
7603         spin_lock_irqsave(&dev->event_lock, flags);
7604         if (intel_crtc->unpin_work) {
7605                 spin_unlock_irqrestore(&dev->event_lock, flags);
7606                 kfree(work);
7607                 drm_vblank_put(dev, intel_crtc->pipe);
7608
7609                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7610                 return -EBUSY;
7611         }
7612         intel_crtc->unpin_work = work;
7613         spin_unlock_irqrestore(&dev->event_lock, flags);
7614
7615         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7616                 flush_workqueue(dev_priv->wq);
7617
7618         ret = i915_mutex_lock_interruptible(dev);
7619         if (ret)
7620                 goto cleanup;
7621
7622         /* Reference the objects for the scheduled work. */
7623         drm_gem_object_reference(&work->old_fb_obj->base);
7624         drm_gem_object_reference(&obj->base);
7625
7626         crtc->fb = fb;
7627
7628         work->pending_flip_obj = obj;
7629
7630         work->enable_stall_check = true;
7631
7632         atomic_inc(&intel_crtc->unpin_work_count);
7633         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7634
7635         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7636         if (ret)
7637                 goto cleanup_pending;
7638
7639         intel_disable_fbc(dev);
7640         intel_mark_fb_busy(obj, NULL);
7641         mutex_unlock(&dev->struct_mutex);
7642
7643         trace_i915_flip_request(intel_crtc->plane, obj);
7644
7645         return 0;
7646
7647 cleanup_pending:
7648         atomic_dec(&intel_crtc->unpin_work_count);
7649         crtc->fb = old_fb;
7650         drm_gem_object_unreference(&work->old_fb_obj->base);
7651         drm_gem_object_unreference(&obj->base);
7652         mutex_unlock(&dev->struct_mutex);
7653
7654 cleanup:
7655         spin_lock_irqsave(&dev->event_lock, flags);
7656         intel_crtc->unpin_work = NULL;
7657         spin_unlock_irqrestore(&dev->event_lock, flags);
7658
7659         drm_vblank_put(dev, intel_crtc->pipe);
7660 free_work:
7661         kfree(work);
7662
7663         return ret;
7664 }
7665
7666 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7667         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7668         .load_lut = intel_crtc_load_lut,
7669 };
7670
7671 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7672                                   struct drm_crtc *crtc)
7673 {
7674         struct drm_device *dev;
7675         struct drm_crtc *tmp;
7676         int crtc_mask = 1;
7677
7678         WARN(!crtc, "checking null crtc?\n");
7679
7680         dev = crtc->dev;
7681
7682         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7683                 if (tmp == crtc)
7684                         break;
7685                 crtc_mask <<= 1;
7686         }
7687
7688         if (encoder->possible_crtcs & crtc_mask)
7689                 return true;
7690         return false;
7691 }
7692
7693 /**
7694  * intel_modeset_update_staged_output_state
7695  *
7696  * Updates the staged output configuration state, e.g. after we've read out the
7697  * current hw state.
7698  */
7699 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7700 {
7701         struct intel_encoder *encoder;
7702         struct intel_connector *connector;
7703
7704         list_for_each_entry(connector, &dev->mode_config.connector_list,
7705                             base.head) {
7706                 connector->new_encoder =
7707                         to_intel_encoder(connector->base.encoder);
7708         }
7709
7710         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7711                             base.head) {
7712                 encoder->new_crtc =
7713                         to_intel_crtc(encoder->base.crtc);
7714         }
7715 }
7716
7717 /**
7718  * intel_modeset_commit_output_state
7719  *
7720  * This function copies the stage display pipe configuration to the real one.
7721  */
7722 static void intel_modeset_commit_output_state(struct drm_device *dev)
7723 {
7724         struct intel_encoder *encoder;
7725         struct intel_connector *connector;
7726
7727         list_for_each_entry(connector, &dev->mode_config.connector_list,
7728                             base.head) {
7729                 connector->base.encoder = &connector->new_encoder->base;
7730         }
7731
7732         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7733                             base.head) {
7734                 encoder->base.crtc = &encoder->new_crtc->base;
7735         }
7736 }
7737
7738 static void
7739 connected_sink_compute_bpp(struct intel_connector * connector,
7740                            struct intel_crtc_config *pipe_config)
7741 {
7742         int bpp = pipe_config->pipe_bpp;
7743
7744         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7745                 connector->base.base.id,
7746                 drm_get_connector_name(&connector->base));
7747
7748         /* Don't use an invalid EDID bpc value */
7749         if (connector->base.display_info.bpc &&
7750             connector->base.display_info.bpc * 3 < bpp) {
7751                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7752                               bpp, connector->base.display_info.bpc*3);
7753                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7754         }
7755
7756         /* Clamp bpp to 8 on screens without EDID 1.4 */
7757         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7758                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7759                               bpp);
7760                 pipe_config->pipe_bpp = 24;
7761         }
7762 }
7763
7764 static int
7765 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7766                           struct drm_framebuffer *fb,
7767                           struct intel_crtc_config *pipe_config)
7768 {
7769         struct drm_device *dev = crtc->base.dev;
7770         struct intel_connector *connector;
7771         int bpp;
7772
7773         switch (fb->pixel_format) {
7774         case DRM_FORMAT_C8:
7775                 bpp = 8*3; /* since we go through a colormap */
7776                 break;
7777         case DRM_FORMAT_XRGB1555:
7778         case DRM_FORMAT_ARGB1555:
7779                 /* checked in intel_framebuffer_init already */
7780                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7781                         return -EINVAL;
7782         case DRM_FORMAT_RGB565:
7783                 bpp = 6*3; /* min is 18bpp */
7784                 break;
7785         case DRM_FORMAT_XBGR8888:
7786         case DRM_FORMAT_ABGR8888:
7787                 /* checked in intel_framebuffer_init already */
7788                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7789                         return -EINVAL;
7790         case DRM_FORMAT_XRGB8888:
7791         case DRM_FORMAT_ARGB8888:
7792                 bpp = 8*3;
7793                 break;
7794         case DRM_FORMAT_XRGB2101010:
7795         case DRM_FORMAT_ARGB2101010:
7796         case DRM_FORMAT_XBGR2101010:
7797         case DRM_FORMAT_ABGR2101010:
7798                 /* checked in intel_framebuffer_init already */
7799                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7800                         return -EINVAL;
7801                 bpp = 10*3;
7802                 break;
7803         /* TODO: gen4+ supports 16 bpc floating point, too. */
7804         default:
7805                 DRM_DEBUG_KMS("unsupported depth\n");
7806                 return -EINVAL;
7807         }
7808
7809         pipe_config->pipe_bpp = bpp;
7810
7811         /* Clamp display bpp to EDID value */
7812         list_for_each_entry(connector, &dev->mode_config.connector_list,
7813                             base.head) {
7814                 if (!connector->new_encoder ||
7815                     connector->new_encoder->new_crtc != crtc)
7816                         continue;
7817
7818                 connected_sink_compute_bpp(connector, pipe_config);
7819         }
7820
7821         return bpp;
7822 }
7823
7824 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7825                                    struct intel_crtc_config *pipe_config,
7826                                    const char *context)
7827 {
7828         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7829                       context, pipe_name(crtc->pipe));
7830
7831         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7832         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7833                       pipe_config->pipe_bpp, pipe_config->dither);
7834         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7835                       pipe_config->has_pch_encoder,
7836                       pipe_config->fdi_lanes,
7837                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7838                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7839                       pipe_config->fdi_m_n.tu);
7840         DRM_DEBUG_KMS("requested mode:\n");
7841         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7842         DRM_DEBUG_KMS("adjusted mode:\n");
7843         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7844         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7845                       pipe_config->gmch_pfit.control,
7846                       pipe_config->gmch_pfit.pgm_ratios,
7847                       pipe_config->gmch_pfit.lvds_border_bits);
7848         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7849                       pipe_config->pch_pfit.pos,
7850                       pipe_config->pch_pfit.size);
7851         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7852 }
7853
7854 static bool check_encoder_cloning(struct drm_crtc *crtc)
7855 {
7856         int num_encoders = 0;
7857         bool uncloneable_encoders = false;
7858         struct intel_encoder *encoder;
7859
7860         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7861                             base.head) {
7862                 if (&encoder->new_crtc->base != crtc)
7863                         continue;
7864
7865                 num_encoders++;
7866                 if (!encoder->cloneable)
7867                         uncloneable_encoders = true;
7868         }
7869
7870         return !(num_encoders > 1 && uncloneable_encoders);
7871 }
7872
7873 static struct intel_crtc_config *
7874 intel_modeset_pipe_config(struct drm_crtc *crtc,
7875                           struct drm_framebuffer *fb,
7876                           struct drm_display_mode *mode)
7877 {
7878         struct drm_device *dev = crtc->dev;
7879         struct drm_encoder_helper_funcs *encoder_funcs;
7880         struct intel_encoder *encoder;
7881         struct intel_crtc_config *pipe_config;
7882         int plane_bpp, ret = -EINVAL;
7883         bool retry = true;
7884
7885         if (!check_encoder_cloning(crtc)) {
7886                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7887                 return ERR_PTR(-EINVAL);
7888         }
7889
7890         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7891         if (!pipe_config)
7892                 return ERR_PTR(-ENOMEM);
7893
7894         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7895         drm_mode_copy(&pipe_config->requested_mode, mode);
7896         pipe_config->cpu_transcoder =
7897                 (enum transcoder) to_intel_crtc(crtc)->pipe;
7898         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7899
7900         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7901          * plane pixel format and any sink constraints into account. Returns the
7902          * source plane bpp so that dithering can be selected on mismatches
7903          * after encoders and crtc also have had their say. */
7904         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7905                                               fb, pipe_config);
7906         if (plane_bpp < 0)
7907                 goto fail;
7908
7909 encoder_retry:
7910         /* Ensure the port clock defaults are reset when retrying. */
7911         pipe_config->port_clock = 0;
7912         pipe_config->pixel_multiplier = 1;
7913
7914         /* Pass our mode to the connectors and the CRTC to give them a chance to
7915          * adjust it according to limitations or connector properties, and also
7916          * a chance to reject the mode entirely.
7917          */
7918         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7919                             base.head) {
7920
7921                 if (&encoder->new_crtc->base != crtc)
7922                         continue;
7923
7924                 if (encoder->compute_config) {
7925                         if (!(encoder->compute_config(encoder, pipe_config))) {
7926                                 DRM_DEBUG_KMS("Encoder config failure\n");
7927                                 goto fail;
7928                         }
7929
7930                         continue;
7931                 }
7932
7933                 encoder_funcs = encoder->base.helper_private;
7934                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7935                                                 &pipe_config->requested_mode,
7936                                                 &pipe_config->adjusted_mode))) {
7937                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7938                         goto fail;
7939                 }
7940         }
7941
7942         /* Set default port clock if not overwritten by the encoder. Needs to be
7943          * done afterwards in case the encoder adjusts the mode. */
7944         if (!pipe_config->port_clock)
7945                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7946
7947         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7948         if (ret < 0) {
7949                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7950                 goto fail;
7951         }
7952
7953         if (ret == RETRY) {
7954                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7955                         ret = -EINVAL;
7956                         goto fail;
7957                 }
7958
7959                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7960                 retry = false;
7961                 goto encoder_retry;
7962         }
7963
7964         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7965         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7966                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7967
7968         return pipe_config;
7969 fail:
7970         kfree(pipe_config);
7971         return ERR_PTR(ret);
7972 }
7973
7974 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7975  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7976 static void
7977 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7978                              unsigned *prepare_pipes, unsigned *disable_pipes)
7979 {
7980         struct intel_crtc *intel_crtc;
7981         struct drm_device *dev = crtc->dev;
7982         struct intel_encoder *encoder;
7983         struct intel_connector *connector;
7984         struct drm_crtc *tmp_crtc;
7985
7986         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7987
7988         /* Check which crtcs have changed outputs connected to them, these need
7989          * to be part of the prepare_pipes mask. We don't (yet) support global
7990          * modeset across multiple crtcs, so modeset_pipes will only have one
7991          * bit set at most. */
7992         list_for_each_entry(connector, &dev->mode_config.connector_list,
7993                             base.head) {
7994                 if (connector->base.encoder == &connector->new_encoder->base)
7995                         continue;
7996
7997                 if (connector->base.encoder) {
7998                         tmp_crtc = connector->base.encoder->crtc;
7999
8000                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8001                 }
8002
8003                 if (connector->new_encoder)
8004                         *prepare_pipes |=
8005                                 1 << connector->new_encoder->new_crtc->pipe;
8006         }
8007
8008         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8009                             base.head) {
8010                 if (encoder->base.crtc == &encoder->new_crtc->base)
8011                         continue;
8012
8013                 if (encoder->base.crtc) {
8014                         tmp_crtc = encoder->base.crtc;
8015
8016                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8017                 }
8018
8019                 if (encoder->new_crtc)
8020                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8021         }
8022
8023         /* Check for any pipes that will be fully disabled ... */
8024         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8025                             base.head) {
8026                 bool used = false;
8027
8028                 /* Don't try to disable disabled crtcs. */
8029                 if (!intel_crtc->base.enabled)
8030                         continue;
8031
8032                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8033                                     base.head) {
8034                         if (encoder->new_crtc == intel_crtc)
8035                                 used = true;
8036                 }
8037
8038                 if (!used)
8039                         *disable_pipes |= 1 << intel_crtc->pipe;
8040         }
8041
8042
8043         /* set_mode is also used to update properties on life display pipes. */
8044         intel_crtc = to_intel_crtc(crtc);
8045         if (crtc->enabled)
8046                 *prepare_pipes |= 1 << intel_crtc->pipe;
8047
8048         /*
8049          * For simplicity do a full modeset on any pipe where the output routing
8050          * changed. We could be more clever, but that would require us to be
8051          * more careful with calling the relevant encoder->mode_set functions.
8052          */
8053         if (*prepare_pipes)
8054                 *modeset_pipes = *prepare_pipes;
8055
8056         /* ... and mask these out. */
8057         *modeset_pipes &= ~(*disable_pipes);
8058         *prepare_pipes &= ~(*disable_pipes);
8059
8060         /*
8061          * HACK: We don't (yet) fully support global modesets. intel_set_config
8062          * obies this rule, but the modeset restore mode of
8063          * intel_modeset_setup_hw_state does not.
8064          */
8065         *modeset_pipes &= 1 << intel_crtc->pipe;
8066         *prepare_pipes &= 1 << intel_crtc->pipe;
8067
8068         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8069                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8070 }
8071
8072 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8073 {
8074         struct drm_encoder *encoder;
8075         struct drm_device *dev = crtc->dev;
8076
8077         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8078                 if (encoder->crtc == crtc)
8079                         return true;
8080
8081         return false;
8082 }
8083
8084 static void
8085 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8086 {
8087         struct intel_encoder *intel_encoder;
8088         struct intel_crtc *intel_crtc;
8089         struct drm_connector *connector;
8090
8091         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8092                             base.head) {
8093                 if (!intel_encoder->base.crtc)
8094                         continue;
8095
8096                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8097
8098                 if (prepare_pipes & (1 << intel_crtc->pipe))
8099                         intel_encoder->connectors_active = false;
8100         }
8101
8102         intel_modeset_commit_output_state(dev);
8103
8104         /* Update computed state. */
8105         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8106                             base.head) {
8107                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8108         }
8109
8110         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8111                 if (!connector->encoder || !connector->encoder->crtc)
8112                         continue;
8113
8114                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8115
8116                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8117                         struct drm_property *dpms_property =
8118                                 dev->mode_config.dpms_property;
8119
8120                         connector->dpms = DRM_MODE_DPMS_ON;
8121                         drm_object_property_set_value(&connector->base,
8122                                                          dpms_property,
8123                                                          DRM_MODE_DPMS_ON);
8124
8125                         intel_encoder = to_intel_encoder(connector->encoder);
8126                         intel_encoder->connectors_active = true;
8127                 }
8128         }
8129
8130 }
8131
8132 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8133                                     struct intel_crtc_config *new)
8134 {
8135         int clock1, clock2, diff;
8136
8137         clock1 = cur->adjusted_mode.clock;
8138         clock2 = new->adjusted_mode.clock;
8139
8140         if (clock1 == clock2)
8141                 return true;
8142
8143         if (!clock1 || !clock2)
8144                 return false;
8145
8146         diff = abs(clock1 - clock2);
8147
8148         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8149                 return true;
8150
8151         return false;
8152 }
8153
8154 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8155         list_for_each_entry((intel_crtc), \
8156                             &(dev)->mode_config.crtc_list, \
8157                             base.head) \
8158                 if (mask & (1 <<(intel_crtc)->pipe))
8159
8160 static bool
8161 intel_pipe_config_compare(struct drm_device *dev,
8162                           struct intel_crtc_config *current_config,
8163                           struct intel_crtc_config *pipe_config)
8164 {
8165 #define PIPE_CONF_CHECK_X(name) \
8166         if (current_config->name != pipe_config->name) { \
8167                 DRM_ERROR("mismatch in " #name " " \
8168                           "(expected 0x%08x, found 0x%08x)\n", \
8169                           current_config->name, \
8170                           pipe_config->name); \
8171                 return false; \
8172         }
8173
8174 #define PIPE_CONF_CHECK_I(name) \
8175         if (current_config->name != pipe_config->name) { \
8176                 DRM_ERROR("mismatch in " #name " " \
8177                           "(expected %i, found %i)\n", \
8178                           current_config->name, \
8179                           pipe_config->name); \
8180                 return false; \
8181         }
8182
8183 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8184         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8185                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8186                           "(expected %i, found %i)\n", \
8187                           current_config->name & (mask), \
8188                           pipe_config->name & (mask)); \
8189                 return false; \
8190         }
8191
8192 #define PIPE_CONF_QUIRK(quirk)  \
8193         ((current_config->quirks | pipe_config->quirks) & (quirk))
8194
8195         PIPE_CONF_CHECK_I(cpu_transcoder);
8196
8197         PIPE_CONF_CHECK_I(has_pch_encoder);
8198         PIPE_CONF_CHECK_I(fdi_lanes);
8199         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8200         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8201         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8202         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8203         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8204
8205         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8206         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8207         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8208         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8209         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8210         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8211
8212         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8213         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8214         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8215         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8216         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8217         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8218
8219         PIPE_CONF_CHECK_I(pixel_multiplier);
8220
8221         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8222                               DRM_MODE_FLAG_INTERLACE);
8223
8224         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8225                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8226                                       DRM_MODE_FLAG_PHSYNC);
8227                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8228                                       DRM_MODE_FLAG_NHSYNC);
8229                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8230                                       DRM_MODE_FLAG_PVSYNC);
8231                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8232                                       DRM_MODE_FLAG_NVSYNC);
8233         }
8234
8235         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8236         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8237
8238         PIPE_CONF_CHECK_I(gmch_pfit.control);
8239         /* pfit ratios are autocomputed by the hw on gen4+ */
8240         if (INTEL_INFO(dev)->gen < 4)
8241                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8242         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8243         PIPE_CONF_CHECK_I(pch_pfit.pos);
8244         PIPE_CONF_CHECK_I(pch_pfit.size);
8245
8246         PIPE_CONF_CHECK_I(ips_enabled);
8247
8248         PIPE_CONF_CHECK_I(shared_dpll);
8249         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8250         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8251         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8252         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8253
8254 #undef PIPE_CONF_CHECK_X
8255 #undef PIPE_CONF_CHECK_I
8256 #undef PIPE_CONF_CHECK_FLAGS
8257 #undef PIPE_CONF_QUIRK
8258
8259         if (!IS_HASWELL(dev)) {
8260                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8261                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8262                                   current_config->adjusted_mode.clock,
8263                                   pipe_config->adjusted_mode.clock);
8264                         return false;
8265                 }
8266         }
8267
8268         return true;
8269 }
8270
8271 static void
8272 check_connector_state(struct drm_device *dev)
8273 {
8274         struct intel_connector *connector;
8275
8276         list_for_each_entry(connector, &dev->mode_config.connector_list,
8277                             base.head) {
8278                 /* This also checks the encoder/connector hw state with the
8279                  * ->get_hw_state callbacks. */
8280                 intel_connector_check_state(connector);
8281
8282                 WARN(&connector->new_encoder->base != connector->base.encoder,
8283                      "connector's staged encoder doesn't match current encoder\n");
8284         }
8285 }
8286
8287 static void
8288 check_encoder_state(struct drm_device *dev)
8289 {
8290         struct intel_encoder *encoder;
8291         struct intel_connector *connector;
8292
8293         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8294                             base.head) {
8295                 bool enabled = false;
8296                 bool active = false;
8297                 enum pipe pipe, tracked_pipe;
8298
8299                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8300                               encoder->base.base.id,
8301                               drm_get_encoder_name(&encoder->base));
8302
8303                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8304                      "encoder's stage crtc doesn't match current crtc\n");
8305                 WARN(encoder->connectors_active && !encoder->base.crtc,
8306                      "encoder's active_connectors set, but no crtc\n");
8307
8308                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8309                                     base.head) {
8310                         if (connector->base.encoder != &encoder->base)
8311                                 continue;
8312                         enabled = true;
8313                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8314                                 active = true;
8315                 }
8316                 WARN(!!encoder->base.crtc != enabled,
8317                      "encoder's enabled state mismatch "
8318                      "(expected %i, found %i)\n",
8319                      !!encoder->base.crtc, enabled);
8320                 WARN(active && !encoder->base.crtc,
8321                      "active encoder with no crtc\n");
8322
8323                 WARN(encoder->connectors_active != active,
8324                      "encoder's computed active state doesn't match tracked active state "
8325                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8326
8327                 active = encoder->get_hw_state(encoder, &pipe);
8328                 WARN(active != encoder->connectors_active,
8329                      "encoder's hw state doesn't match sw tracking "
8330                      "(expected %i, found %i)\n",
8331                      encoder->connectors_active, active);
8332
8333                 if (!encoder->base.crtc)
8334                         continue;
8335
8336                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8337                 WARN(active && pipe != tracked_pipe,
8338                      "active encoder's pipe doesn't match"
8339                      "(expected %i, found %i)\n",
8340                      tracked_pipe, pipe);
8341
8342         }
8343 }
8344
8345 static void
8346 check_crtc_state(struct drm_device *dev)
8347 {
8348         drm_i915_private_t *dev_priv = dev->dev_private;
8349         struct intel_crtc *crtc;
8350         struct intel_encoder *encoder;
8351         struct intel_crtc_config pipe_config;
8352
8353         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8354                             base.head) {
8355                 bool enabled = false;
8356                 bool active = false;
8357
8358                 memset(&pipe_config, 0, sizeof(pipe_config));
8359
8360                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8361                               crtc->base.base.id);
8362
8363                 WARN(crtc->active && !crtc->base.enabled,
8364                      "active crtc, but not enabled in sw tracking\n");
8365
8366                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8367                                     base.head) {
8368                         if (encoder->base.crtc != &crtc->base)
8369                                 continue;
8370                         enabled = true;
8371                         if (encoder->connectors_active)
8372                                 active = true;
8373                 }
8374
8375                 WARN(active != crtc->active,
8376                      "crtc's computed active state doesn't match tracked active state "
8377                      "(expected %i, found %i)\n", active, crtc->active);
8378                 WARN(enabled != crtc->base.enabled,
8379                      "crtc's computed enabled state doesn't match tracked enabled state "
8380                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8381
8382                 active = dev_priv->display.get_pipe_config(crtc,
8383                                                            &pipe_config);
8384
8385                 /* hw state is inconsistent with the pipe A quirk */
8386                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8387                         active = crtc->active;
8388
8389                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8390                                     base.head) {
8391                         if (encoder->base.crtc != &crtc->base)
8392                                 continue;
8393                         if (encoder->get_config)
8394                                 encoder->get_config(encoder, &pipe_config);
8395                 }
8396
8397                 if (dev_priv->display.get_clock)
8398                         dev_priv->display.get_clock(crtc, &pipe_config);
8399
8400                 WARN(crtc->active != active,
8401                      "crtc active state doesn't match with hw state "
8402                      "(expected %i, found %i)\n", crtc->active, active);
8403
8404                 if (active &&
8405                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8406                         WARN(1, "pipe state doesn't match!\n");
8407                         intel_dump_pipe_config(crtc, &pipe_config,
8408                                                "[hw state]");
8409                         intel_dump_pipe_config(crtc, &crtc->config,
8410                                                "[sw state]");
8411                 }
8412         }
8413 }
8414
8415 static void
8416 check_shared_dpll_state(struct drm_device *dev)
8417 {
8418         drm_i915_private_t *dev_priv = dev->dev_private;
8419         struct intel_crtc *crtc;
8420         struct intel_dpll_hw_state dpll_hw_state;
8421         int i;
8422
8423         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8424                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8425                 int enabled_crtcs = 0, active_crtcs = 0;
8426                 bool active;
8427
8428                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8429
8430                 DRM_DEBUG_KMS("%s\n", pll->name);
8431
8432                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8433
8434                 WARN(pll->active > pll->refcount,
8435                      "more active pll users than references: %i vs %i\n",
8436                      pll->active, pll->refcount);
8437                 WARN(pll->active && !pll->on,
8438                      "pll in active use but not on in sw tracking\n");
8439                 WARN(pll->on != active,
8440                      "pll on state mismatch (expected %i, found %i)\n",
8441                      pll->on, active);
8442
8443                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8444                                     base.head) {
8445                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8446                                 enabled_crtcs++;
8447                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8448                                 active_crtcs++;
8449                 }
8450                 WARN(pll->active != active_crtcs,
8451                      "pll active crtcs mismatch (expected %i, found %i)\n",
8452                      pll->active, active_crtcs);
8453                 WARN(pll->refcount != enabled_crtcs,
8454                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8455                      pll->refcount, enabled_crtcs);
8456
8457                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8458                                        sizeof(dpll_hw_state)),
8459                      "pll hw state mismatch\n");
8460         }
8461 }
8462
8463 void
8464 intel_modeset_check_state(struct drm_device *dev)
8465 {
8466         check_connector_state(dev);
8467         check_encoder_state(dev);
8468         check_crtc_state(dev);
8469         check_shared_dpll_state(dev);
8470 }
8471
8472 static int __intel_set_mode(struct drm_crtc *crtc,
8473                             struct drm_display_mode *mode,
8474                             int x, int y, struct drm_framebuffer *fb)
8475 {
8476         struct drm_device *dev = crtc->dev;
8477         drm_i915_private_t *dev_priv = dev->dev_private;
8478         struct drm_display_mode *saved_mode, *saved_hwmode;
8479         struct intel_crtc_config *pipe_config = NULL;
8480         struct intel_crtc *intel_crtc;
8481         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8482         int ret = 0;
8483
8484         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8485         if (!saved_mode)
8486                 return -ENOMEM;
8487         saved_hwmode = saved_mode + 1;
8488
8489         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8490                                      &prepare_pipes, &disable_pipes);
8491
8492         *saved_hwmode = crtc->hwmode;
8493         *saved_mode = crtc->mode;
8494
8495         /* Hack: Because we don't (yet) support global modeset on multiple
8496          * crtcs, we don't keep track of the new mode for more than one crtc.
8497          * Hence simply check whether any bit is set in modeset_pipes in all the
8498          * pieces of code that are not yet converted to deal with mutliple crtcs
8499          * changing their mode at the same time. */
8500         if (modeset_pipes) {
8501                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8502                 if (IS_ERR(pipe_config)) {
8503                         ret = PTR_ERR(pipe_config);
8504                         pipe_config = NULL;
8505
8506                         goto out;
8507                 }
8508                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8509                                        "[modeset]");
8510         }
8511
8512         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8513                 intel_crtc_disable(&intel_crtc->base);
8514
8515         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8516                 if (intel_crtc->base.enabled)
8517                         dev_priv->display.crtc_disable(&intel_crtc->base);
8518         }
8519
8520         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8521          * to set it here already despite that we pass it down the callchain.
8522          */
8523         if (modeset_pipes) {
8524                 crtc->mode = *mode;
8525                 /* mode_set/enable/disable functions rely on a correct pipe
8526                  * config. */
8527                 to_intel_crtc(crtc)->config = *pipe_config;
8528         }
8529
8530         /* Only after disabling all output pipelines that will be changed can we
8531          * update the the output configuration. */
8532         intel_modeset_update_state(dev, prepare_pipes);
8533
8534         if (dev_priv->display.modeset_global_resources)
8535                 dev_priv->display.modeset_global_resources(dev);
8536
8537         /* Set up the DPLL and any encoders state that needs to adjust or depend
8538          * on the DPLL.
8539          */
8540         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8541                 ret = intel_crtc_mode_set(&intel_crtc->base,
8542                                           x, y, fb);
8543                 if (ret)
8544                         goto done;
8545         }
8546
8547         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8548         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8549                 dev_priv->display.crtc_enable(&intel_crtc->base);
8550
8551         if (modeset_pipes) {
8552                 /* Store real post-adjustment hardware mode. */
8553                 crtc->hwmode = pipe_config->adjusted_mode;
8554
8555                 /* Calculate and store various constants which
8556                  * are later needed by vblank and swap-completion
8557                  * timestamping. They are derived from true hwmode.
8558                  */
8559                 drm_calc_timestamping_constants(crtc);
8560         }
8561
8562         /* FIXME: add subpixel order */
8563 done:
8564         if (ret && crtc->enabled) {
8565                 crtc->hwmode = *saved_hwmode;
8566                 crtc->mode = *saved_mode;
8567         }
8568
8569 out:
8570         kfree(pipe_config);
8571         kfree(saved_mode);
8572         return ret;
8573 }
8574
8575 int intel_set_mode(struct drm_crtc *crtc,
8576                      struct drm_display_mode *mode,
8577                      int x, int y, struct drm_framebuffer *fb)
8578 {
8579         int ret;
8580
8581         ret = __intel_set_mode(crtc, mode, x, y, fb);
8582
8583         if (ret == 0)
8584                 intel_modeset_check_state(crtc->dev);
8585
8586         return ret;
8587 }
8588
8589 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8590 {
8591         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8592 }
8593
8594 #undef for_each_intel_crtc_masked
8595
8596 static void intel_set_config_free(struct intel_set_config *config)
8597 {
8598         if (!config)
8599                 return;
8600
8601         kfree(config->save_connector_encoders);
8602         kfree(config->save_encoder_crtcs);
8603         kfree(config);
8604 }
8605
8606 static int intel_set_config_save_state(struct drm_device *dev,
8607                                        struct intel_set_config *config)
8608 {
8609         struct drm_encoder *encoder;
8610         struct drm_connector *connector;
8611         int count;
8612
8613         config->save_encoder_crtcs =
8614                 kcalloc(dev->mode_config.num_encoder,
8615                         sizeof(struct drm_crtc *), GFP_KERNEL);
8616         if (!config->save_encoder_crtcs)
8617                 return -ENOMEM;
8618
8619         config->save_connector_encoders =
8620                 kcalloc(dev->mode_config.num_connector,
8621                         sizeof(struct drm_encoder *), GFP_KERNEL);
8622         if (!config->save_connector_encoders)
8623                 return -ENOMEM;
8624
8625         /* Copy data. Note that driver private data is not affected.
8626          * Should anything bad happen only the expected state is
8627          * restored, not the drivers personal bookkeeping.
8628          */
8629         count = 0;
8630         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8631                 config->save_encoder_crtcs[count++] = encoder->crtc;
8632         }
8633
8634         count = 0;
8635         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8636                 config->save_connector_encoders[count++] = connector->encoder;
8637         }
8638
8639         return 0;
8640 }
8641
8642 static void intel_set_config_restore_state(struct drm_device *dev,
8643                                            struct intel_set_config *config)
8644 {
8645         struct intel_encoder *encoder;
8646         struct intel_connector *connector;
8647         int count;
8648
8649         count = 0;
8650         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8651                 encoder->new_crtc =
8652                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8653         }
8654
8655         count = 0;
8656         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8657                 connector->new_encoder =
8658                         to_intel_encoder(config->save_connector_encoders[count++]);
8659         }
8660 }
8661
8662 static bool
8663 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8664                       int num_connectors)
8665 {
8666         int i;
8667
8668         for (i = 0; i < num_connectors; i++)
8669                 if (connectors[i].encoder &&
8670                     connectors[i].encoder->crtc == crtc &&
8671                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8672                         return true;
8673
8674         return false;
8675 }
8676
8677 static void
8678 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8679                                       struct intel_set_config *config)
8680 {
8681
8682         /* We should be able to check here if the fb has the same properties
8683          * and then just flip_or_move it */
8684         if (set->connectors != NULL &&
8685             is_crtc_connector_off(set->crtc, *set->connectors,
8686                                   set->num_connectors)) {
8687                         config->mode_changed = true;
8688         } else if (set->crtc->fb != set->fb) {
8689                 /* If we have no fb then treat it as a full mode set */
8690                 if (set->crtc->fb == NULL) {
8691                         struct intel_crtc *intel_crtc =
8692                                 to_intel_crtc(set->crtc);
8693
8694                         if (intel_crtc->active && i915_fastboot) {
8695                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8696                                 config->fb_changed = true;
8697                         } else {
8698                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8699                                 config->mode_changed = true;
8700                         }
8701                 } else if (set->fb == NULL) {
8702                         config->mode_changed = true;
8703                 } else if (set->fb->pixel_format !=
8704                            set->crtc->fb->pixel_format) {
8705                         config->mode_changed = true;
8706                 } else {
8707                         config->fb_changed = true;
8708                 }
8709         }
8710
8711         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8712                 config->fb_changed = true;
8713
8714         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8715                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8716                 drm_mode_debug_printmodeline(&set->crtc->mode);
8717                 drm_mode_debug_printmodeline(set->mode);
8718                 config->mode_changed = true;
8719         }
8720 }
8721
8722 static int
8723 intel_modeset_stage_output_state(struct drm_device *dev,
8724                                  struct drm_mode_set *set,
8725                                  struct intel_set_config *config)
8726 {
8727         struct drm_crtc *new_crtc;
8728         struct intel_connector *connector;
8729         struct intel_encoder *encoder;
8730         int count, ro;
8731
8732         /* The upper layers ensure that we either disable a crtc or have a list
8733          * of connectors. For paranoia, double-check this. */
8734         WARN_ON(!set->fb && (set->num_connectors != 0));
8735         WARN_ON(set->fb && (set->num_connectors == 0));
8736
8737         count = 0;
8738         list_for_each_entry(connector, &dev->mode_config.connector_list,
8739                             base.head) {
8740                 /* Otherwise traverse passed in connector list and get encoders
8741                  * for them. */
8742                 for (ro = 0; ro < set->num_connectors; ro++) {
8743                         if (set->connectors[ro] == &connector->base) {
8744                                 connector->new_encoder = connector->encoder;
8745                                 break;
8746                         }
8747                 }
8748
8749                 /* If we disable the crtc, disable all its connectors. Also, if
8750                  * the connector is on the changing crtc but not on the new
8751                  * connector list, disable it. */
8752                 if ((!set->fb || ro == set->num_connectors) &&
8753                     connector->base.encoder &&
8754                     connector->base.encoder->crtc == set->crtc) {
8755                         connector->new_encoder = NULL;
8756
8757                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8758                                 connector->base.base.id,
8759                                 drm_get_connector_name(&connector->base));
8760                 }
8761
8762
8763                 if (&connector->new_encoder->base != connector->base.encoder) {
8764                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8765                         config->mode_changed = true;
8766                 }
8767         }
8768         /* connector->new_encoder is now updated for all connectors. */
8769
8770         /* Update crtc of enabled connectors. */
8771         count = 0;
8772         list_for_each_entry(connector, &dev->mode_config.connector_list,
8773                             base.head) {
8774                 if (!connector->new_encoder)
8775                         continue;
8776
8777                 new_crtc = connector->new_encoder->base.crtc;
8778
8779                 for (ro = 0; ro < set->num_connectors; ro++) {
8780                         if (set->connectors[ro] == &connector->base)
8781                                 new_crtc = set->crtc;
8782                 }
8783
8784                 /* Make sure the new CRTC will work with the encoder */
8785                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8786                                            new_crtc)) {
8787                         return -EINVAL;
8788                 }
8789                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8790
8791                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8792                         connector->base.base.id,
8793                         drm_get_connector_name(&connector->base),
8794                         new_crtc->base.id);
8795         }
8796
8797         /* Check for any encoders that needs to be disabled. */
8798         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8799                             base.head) {
8800                 list_for_each_entry(connector,
8801                                     &dev->mode_config.connector_list,
8802                                     base.head) {
8803                         if (connector->new_encoder == encoder) {
8804                                 WARN_ON(!connector->new_encoder->new_crtc);
8805
8806                                 goto next_encoder;
8807                         }
8808                 }
8809                 encoder->new_crtc = NULL;
8810 next_encoder:
8811                 /* Only now check for crtc changes so we don't miss encoders
8812                  * that will be disabled. */
8813                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8814                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8815                         config->mode_changed = true;
8816                 }
8817         }
8818         /* Now we've also updated encoder->new_crtc for all encoders. */
8819
8820         return 0;
8821 }
8822
8823 static int intel_crtc_set_config(struct drm_mode_set *set)
8824 {
8825         struct drm_device *dev;
8826         struct drm_mode_set save_set;
8827         struct intel_set_config *config;
8828         int ret;
8829
8830         BUG_ON(!set);
8831         BUG_ON(!set->crtc);
8832         BUG_ON(!set->crtc->helper_private);
8833
8834         /* Enforce sane interface api - has been abused by the fb helper. */
8835         BUG_ON(!set->mode && set->fb);
8836         BUG_ON(set->fb && set->num_connectors == 0);
8837
8838         if (set->fb) {
8839                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8840                                 set->crtc->base.id, set->fb->base.id,
8841                                 (int)set->num_connectors, set->x, set->y);
8842         } else {
8843                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8844         }
8845
8846         dev = set->crtc->dev;
8847
8848         ret = -ENOMEM;
8849         config = kzalloc(sizeof(*config), GFP_KERNEL);
8850         if (!config)
8851                 goto out_config;
8852
8853         ret = intel_set_config_save_state(dev, config);
8854         if (ret)
8855                 goto out_config;
8856
8857         save_set.crtc = set->crtc;
8858         save_set.mode = &set->crtc->mode;
8859         save_set.x = set->crtc->x;
8860         save_set.y = set->crtc->y;
8861         save_set.fb = set->crtc->fb;
8862
8863         /* Compute whether we need a full modeset, only an fb base update or no
8864          * change at all. In the future we might also check whether only the
8865          * mode changed, e.g. for LVDS where we only change the panel fitter in
8866          * such cases. */
8867         intel_set_config_compute_mode_changes(set, config);
8868
8869         ret = intel_modeset_stage_output_state(dev, set, config);
8870         if (ret)
8871                 goto fail;
8872
8873         if (config->mode_changed) {
8874                 ret = intel_set_mode(set->crtc, set->mode,
8875                                      set->x, set->y, set->fb);
8876         } else if (config->fb_changed) {
8877                 intel_crtc_wait_for_pending_flips(set->crtc);
8878
8879                 ret = intel_pipe_set_base(set->crtc,
8880                                           set->x, set->y, set->fb);
8881         }
8882
8883         if (ret) {
8884                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8885                               set->crtc->base.id, ret);
8886 fail:
8887                 intel_set_config_restore_state(dev, config);
8888
8889                 /* Try to restore the config */
8890                 if (config->mode_changed &&
8891                     intel_set_mode(save_set.crtc, save_set.mode,
8892                                    save_set.x, save_set.y, save_set.fb))
8893                         DRM_ERROR("failed to restore config after modeset failure\n");
8894         }
8895
8896 out_config:
8897         intel_set_config_free(config);
8898         return ret;
8899 }
8900
8901 static const struct drm_crtc_funcs intel_crtc_funcs = {
8902         .cursor_set = intel_crtc_cursor_set,
8903         .cursor_move = intel_crtc_cursor_move,
8904         .gamma_set = intel_crtc_gamma_set,
8905         .set_config = intel_crtc_set_config,
8906         .destroy = intel_crtc_destroy,
8907         .page_flip = intel_crtc_page_flip,
8908 };
8909
8910 static void intel_cpu_pll_init(struct drm_device *dev)
8911 {
8912         if (HAS_DDI(dev))
8913                 intel_ddi_pll_init(dev);
8914 }
8915
8916 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8917                                       struct intel_shared_dpll *pll,
8918                                       struct intel_dpll_hw_state *hw_state)
8919 {
8920         uint32_t val;
8921
8922         val = I915_READ(PCH_DPLL(pll->id));
8923         hw_state->dpll = val;
8924         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8925         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8926
8927         return val & DPLL_VCO_ENABLE;
8928 }
8929
8930 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8931                                   struct intel_shared_dpll *pll)
8932 {
8933         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8934         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8935 }
8936
8937 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8938                                 struct intel_shared_dpll *pll)
8939 {
8940         /* PCH refclock must be enabled first */
8941         assert_pch_refclk_enabled(dev_priv);
8942
8943         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8944
8945         /* Wait for the clocks to stabilize. */
8946         POSTING_READ(PCH_DPLL(pll->id));
8947         udelay(150);
8948
8949         /* The pixel multiplier can only be updated once the
8950          * DPLL is enabled and the clocks are stable.
8951          *
8952          * So write it again.
8953          */
8954         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8955         POSTING_READ(PCH_DPLL(pll->id));
8956         udelay(200);
8957 }
8958
8959 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8960                                  struct intel_shared_dpll *pll)
8961 {
8962         struct drm_device *dev = dev_priv->dev;
8963         struct intel_crtc *crtc;
8964
8965         /* Make sure no transcoder isn't still depending on us. */
8966         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8967                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8968                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8969         }
8970
8971         I915_WRITE(PCH_DPLL(pll->id), 0);
8972         POSTING_READ(PCH_DPLL(pll->id));
8973         udelay(200);
8974 }
8975
8976 static char *ibx_pch_dpll_names[] = {
8977         "PCH DPLL A",
8978         "PCH DPLL B",
8979 };
8980
8981 static void ibx_pch_dpll_init(struct drm_device *dev)
8982 {
8983         struct drm_i915_private *dev_priv = dev->dev_private;
8984         int i;
8985
8986         dev_priv->num_shared_dpll = 2;
8987
8988         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8989                 dev_priv->shared_dplls[i].id = i;
8990                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8991                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8992                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8993                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8994                 dev_priv->shared_dplls[i].get_hw_state =
8995                         ibx_pch_dpll_get_hw_state;
8996         }
8997 }
8998
8999 static void intel_shared_dpll_init(struct drm_device *dev)
9000 {
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002
9003         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9004                 ibx_pch_dpll_init(dev);
9005         else
9006                 dev_priv->num_shared_dpll = 0;
9007
9008         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9009         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9010                       dev_priv->num_shared_dpll);
9011 }
9012
9013 static void intel_crtc_init(struct drm_device *dev, int pipe)
9014 {
9015         drm_i915_private_t *dev_priv = dev->dev_private;
9016         struct intel_crtc *intel_crtc;
9017         int i;
9018
9019         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9020         if (intel_crtc == NULL)
9021                 return;
9022
9023         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9024
9025         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9026         for (i = 0; i < 256; i++) {
9027                 intel_crtc->lut_r[i] = i;
9028                 intel_crtc->lut_g[i] = i;
9029                 intel_crtc->lut_b[i] = i;
9030         }
9031
9032         /* Swap pipes & planes for FBC on pre-965 */
9033         intel_crtc->pipe = pipe;
9034         intel_crtc->plane = pipe;
9035         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9036                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9037                 intel_crtc->plane = !pipe;
9038         }
9039
9040         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9041                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9042         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9043         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9044
9045         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9046 }
9047
9048 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9049                                 struct drm_file *file)
9050 {
9051         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9052         struct drm_mode_object *drmmode_obj;
9053         struct intel_crtc *crtc;
9054
9055         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9056                 return -ENODEV;
9057
9058         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9059                         DRM_MODE_OBJECT_CRTC);
9060
9061         if (!drmmode_obj) {
9062                 DRM_ERROR("no such CRTC id\n");
9063                 return -EINVAL;
9064         }
9065
9066         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9067         pipe_from_crtc_id->pipe = crtc->pipe;
9068
9069         return 0;
9070 }
9071
9072 static int intel_encoder_clones(struct intel_encoder *encoder)
9073 {
9074         struct drm_device *dev = encoder->base.dev;
9075         struct intel_encoder *source_encoder;
9076         int index_mask = 0;
9077         int entry = 0;
9078
9079         list_for_each_entry(source_encoder,
9080                             &dev->mode_config.encoder_list, base.head) {
9081
9082                 if (encoder == source_encoder)
9083                         index_mask |= (1 << entry);
9084
9085                 /* Intel hw has only one MUX where enocoders could be cloned. */
9086                 if (encoder->cloneable && source_encoder->cloneable)
9087                         index_mask |= (1 << entry);
9088
9089                 entry++;
9090         }
9091
9092         return index_mask;
9093 }
9094
9095 static bool has_edp_a(struct drm_device *dev)
9096 {
9097         struct drm_i915_private *dev_priv = dev->dev_private;
9098
9099         if (!IS_MOBILE(dev))
9100                 return false;
9101
9102         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9103                 return false;
9104
9105         if (IS_GEN5(dev) &&
9106             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9107                 return false;
9108
9109         return true;
9110 }
9111
9112 static void intel_setup_outputs(struct drm_device *dev)
9113 {
9114         struct drm_i915_private *dev_priv = dev->dev_private;
9115         struct intel_encoder *encoder;
9116         bool dpd_is_edp = false;
9117
9118         intel_lvds_init(dev);
9119
9120         if (!IS_ULT(dev))
9121                 intel_crt_init(dev);
9122
9123         if (HAS_DDI(dev)) {
9124                 int found;
9125
9126                 /* Haswell uses DDI functions to detect digital outputs */
9127                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9128                 /* DDI A only supports eDP */
9129                 if (found)
9130                         intel_ddi_init(dev, PORT_A);
9131
9132                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9133                  * register */
9134                 found = I915_READ(SFUSE_STRAP);
9135
9136                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9137                         intel_ddi_init(dev, PORT_B);
9138                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9139                         intel_ddi_init(dev, PORT_C);
9140                 if (found & SFUSE_STRAP_DDID_DETECTED)
9141                         intel_ddi_init(dev, PORT_D);
9142         } else if (HAS_PCH_SPLIT(dev)) {
9143                 int found;
9144                 dpd_is_edp = intel_dpd_is_edp(dev);
9145
9146                 if (has_edp_a(dev))
9147                         intel_dp_init(dev, DP_A, PORT_A);
9148
9149                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9150                         /* PCH SDVOB multiplex with HDMIB */
9151                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9152                         if (!found)
9153                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9154                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9155                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9156                 }
9157
9158                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9159                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9160
9161                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9162                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9163
9164                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9165                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9166
9167                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9168                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9169         } else if (IS_VALLEYVIEW(dev)) {
9170                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9171                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9172                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9173
9174                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9175                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9176                                         PORT_B);
9177                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9178                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9179                 }
9180         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9181                 bool found = false;
9182
9183                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9184                         DRM_DEBUG_KMS("probing SDVOB\n");
9185                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9186                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9187                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9188                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9189                         }
9190
9191                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9192                                 intel_dp_init(dev, DP_B, PORT_B);
9193                 }
9194
9195                 /* Before G4X SDVOC doesn't have its own detect register */
9196
9197                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9198                         DRM_DEBUG_KMS("probing SDVOC\n");
9199                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9200                 }
9201
9202                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9203
9204                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9205                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9206                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9207                         }
9208                         if (SUPPORTS_INTEGRATED_DP(dev))
9209                                 intel_dp_init(dev, DP_C, PORT_C);
9210                 }
9211
9212                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9213                     (I915_READ(DP_D) & DP_DETECTED))
9214                         intel_dp_init(dev, DP_D, PORT_D);
9215         } else if (IS_GEN2(dev))
9216                 intel_dvo_init(dev);
9217
9218         if (SUPPORTS_TV(dev))
9219                 intel_tv_init(dev);
9220
9221         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9222                 encoder->base.possible_crtcs = encoder->crtc_mask;
9223                 encoder->base.possible_clones =
9224                         intel_encoder_clones(encoder);
9225         }
9226
9227         intel_init_pch_refclk(dev);
9228
9229         drm_helper_move_panel_connectors_to_head(dev);
9230 }
9231
9232 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9233 {
9234         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9235
9236         drm_framebuffer_cleanup(fb);
9237         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9238
9239         kfree(intel_fb);
9240 }
9241
9242 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9243                                                 struct drm_file *file,
9244                                                 unsigned int *handle)
9245 {
9246         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9247         struct drm_i915_gem_object *obj = intel_fb->obj;
9248
9249         return drm_gem_handle_create(file, &obj->base, handle);
9250 }
9251
9252 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9253         .destroy = intel_user_framebuffer_destroy,
9254         .create_handle = intel_user_framebuffer_create_handle,
9255 };
9256
9257 int intel_framebuffer_init(struct drm_device *dev,
9258                            struct intel_framebuffer *intel_fb,
9259                            struct drm_mode_fb_cmd2 *mode_cmd,
9260                            struct drm_i915_gem_object *obj)
9261 {
9262         int pitch_limit;
9263         int ret;
9264
9265         if (obj->tiling_mode == I915_TILING_Y) {
9266                 DRM_DEBUG("hardware does not support tiling Y\n");
9267                 return -EINVAL;
9268         }
9269
9270         if (mode_cmd->pitches[0] & 63) {
9271                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9272                           mode_cmd->pitches[0]);
9273                 return -EINVAL;
9274         }
9275
9276         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9277                 pitch_limit = 32*1024;
9278         } else if (INTEL_INFO(dev)->gen >= 4) {
9279                 if (obj->tiling_mode)
9280                         pitch_limit = 16*1024;
9281                 else
9282                         pitch_limit = 32*1024;
9283         } else if (INTEL_INFO(dev)->gen >= 3) {
9284                 if (obj->tiling_mode)
9285                         pitch_limit = 8*1024;
9286                 else
9287                         pitch_limit = 16*1024;
9288         } else
9289                 /* XXX DSPC is limited to 4k tiled */
9290                 pitch_limit = 8*1024;
9291
9292         if (mode_cmd->pitches[0] > pitch_limit) {
9293                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9294                           obj->tiling_mode ? "tiled" : "linear",
9295                           mode_cmd->pitches[0], pitch_limit);
9296                 return -EINVAL;
9297         }
9298
9299         if (obj->tiling_mode != I915_TILING_NONE &&
9300             mode_cmd->pitches[0] != obj->stride) {
9301                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9302                           mode_cmd->pitches[0], obj->stride);
9303                 return -EINVAL;
9304         }
9305
9306         /* Reject formats not supported by any plane early. */
9307         switch (mode_cmd->pixel_format) {
9308         case DRM_FORMAT_C8:
9309         case DRM_FORMAT_RGB565:
9310         case DRM_FORMAT_XRGB8888:
9311         case DRM_FORMAT_ARGB8888:
9312                 break;
9313         case DRM_FORMAT_XRGB1555:
9314         case DRM_FORMAT_ARGB1555:
9315                 if (INTEL_INFO(dev)->gen > 3) {
9316                         DRM_DEBUG("unsupported pixel format: %s\n",
9317                                   drm_get_format_name(mode_cmd->pixel_format));
9318                         return -EINVAL;
9319                 }
9320                 break;
9321         case DRM_FORMAT_XBGR8888:
9322         case DRM_FORMAT_ABGR8888:
9323         case DRM_FORMAT_XRGB2101010:
9324         case DRM_FORMAT_ARGB2101010:
9325         case DRM_FORMAT_XBGR2101010:
9326         case DRM_FORMAT_ABGR2101010:
9327                 if (INTEL_INFO(dev)->gen < 4) {
9328                         DRM_DEBUG("unsupported pixel format: %s\n",
9329                                   drm_get_format_name(mode_cmd->pixel_format));
9330                         return -EINVAL;
9331                 }
9332                 break;
9333         case DRM_FORMAT_YUYV:
9334         case DRM_FORMAT_UYVY:
9335         case DRM_FORMAT_YVYU:
9336         case DRM_FORMAT_VYUY:
9337                 if (INTEL_INFO(dev)->gen < 5) {
9338                         DRM_DEBUG("unsupported pixel format: %s\n",
9339                                   drm_get_format_name(mode_cmd->pixel_format));
9340                         return -EINVAL;
9341                 }
9342                 break;
9343         default:
9344                 DRM_DEBUG("unsupported pixel format: %s\n",
9345                           drm_get_format_name(mode_cmd->pixel_format));
9346                 return -EINVAL;
9347         }
9348
9349         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9350         if (mode_cmd->offsets[0] != 0)
9351                 return -EINVAL;
9352
9353         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9354         intel_fb->obj = obj;
9355
9356         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9357         if (ret) {
9358                 DRM_ERROR("framebuffer init failed %d\n", ret);
9359                 return ret;
9360         }
9361
9362         return 0;
9363 }
9364
9365 static struct drm_framebuffer *
9366 intel_user_framebuffer_create(struct drm_device *dev,
9367                               struct drm_file *filp,
9368                               struct drm_mode_fb_cmd2 *mode_cmd)
9369 {
9370         struct drm_i915_gem_object *obj;
9371
9372         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9373                                                 mode_cmd->handles[0]));
9374         if (&obj->base == NULL)
9375                 return ERR_PTR(-ENOENT);
9376
9377         return intel_framebuffer_create(dev, mode_cmd, obj);
9378 }
9379
9380 static const struct drm_mode_config_funcs intel_mode_funcs = {
9381         .fb_create = intel_user_framebuffer_create,
9382         .output_poll_changed = intel_fb_output_poll_changed,
9383 };
9384
9385 /* Set up chip specific display functions */
9386 static void intel_init_display(struct drm_device *dev)
9387 {
9388         struct drm_i915_private *dev_priv = dev->dev_private;
9389
9390         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9391                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9392         else if (IS_VALLEYVIEW(dev))
9393                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9394         else if (IS_PINEVIEW(dev))
9395                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9396         else
9397                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9398
9399         if (HAS_DDI(dev)) {
9400                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9401                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9402                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9403                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9404                 dev_priv->display.off = haswell_crtc_off;
9405                 dev_priv->display.update_plane = ironlake_update_plane;
9406         } else if (HAS_PCH_SPLIT(dev)) {
9407                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9408                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9409                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9410                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9411                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9412                 dev_priv->display.off = ironlake_crtc_off;
9413                 dev_priv->display.update_plane = ironlake_update_plane;
9414         } else if (IS_VALLEYVIEW(dev)) {
9415                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9416                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9417                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9418                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9419                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9420                 dev_priv->display.off = i9xx_crtc_off;
9421                 dev_priv->display.update_plane = i9xx_update_plane;
9422         } else {
9423                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9424                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9425                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9426                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9427                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9428                 dev_priv->display.off = i9xx_crtc_off;
9429                 dev_priv->display.update_plane = i9xx_update_plane;
9430         }
9431
9432         /* Returns the core display clock speed */
9433         if (IS_VALLEYVIEW(dev))
9434                 dev_priv->display.get_display_clock_speed =
9435                         valleyview_get_display_clock_speed;
9436         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9437                 dev_priv->display.get_display_clock_speed =
9438                         i945_get_display_clock_speed;
9439         else if (IS_I915G(dev))
9440                 dev_priv->display.get_display_clock_speed =
9441                         i915_get_display_clock_speed;
9442         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9443                 dev_priv->display.get_display_clock_speed =
9444                         i9xx_misc_get_display_clock_speed;
9445         else if (IS_I915GM(dev))
9446                 dev_priv->display.get_display_clock_speed =
9447                         i915gm_get_display_clock_speed;
9448         else if (IS_I865G(dev))
9449                 dev_priv->display.get_display_clock_speed =
9450                         i865_get_display_clock_speed;
9451         else if (IS_I85X(dev))
9452                 dev_priv->display.get_display_clock_speed =
9453                         i855_get_display_clock_speed;
9454         else /* 852, 830 */
9455                 dev_priv->display.get_display_clock_speed =
9456                         i830_get_display_clock_speed;
9457
9458         if (HAS_PCH_SPLIT(dev)) {
9459                 if (IS_GEN5(dev)) {
9460                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9461                         dev_priv->display.write_eld = ironlake_write_eld;
9462                 } else if (IS_GEN6(dev)) {
9463                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9464                         dev_priv->display.write_eld = ironlake_write_eld;
9465                 } else if (IS_IVYBRIDGE(dev)) {
9466                         /* FIXME: detect B0+ stepping and use auto training */
9467                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9468                         dev_priv->display.write_eld = ironlake_write_eld;
9469                         dev_priv->display.modeset_global_resources =
9470                                 ivb_modeset_global_resources;
9471                 } else if (IS_HASWELL(dev)) {
9472                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9473                         dev_priv->display.write_eld = haswell_write_eld;
9474                         dev_priv->display.modeset_global_resources =
9475                                 haswell_modeset_global_resources;
9476                 }
9477         } else if (IS_G4X(dev)) {
9478                 dev_priv->display.write_eld = g4x_write_eld;
9479         }
9480
9481         /* Default just returns -ENODEV to indicate unsupported */
9482         dev_priv->display.queue_flip = intel_default_queue_flip;
9483
9484         switch (INTEL_INFO(dev)->gen) {
9485         case 2:
9486                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9487                 break;
9488
9489         case 3:
9490                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9491                 break;
9492
9493         case 4:
9494         case 5:
9495                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9496                 break;
9497
9498         case 6:
9499                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9500                 break;
9501         case 7:
9502                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9503                 break;
9504         }
9505 }
9506
9507 /*
9508  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9509  * resume, or other times.  This quirk makes sure that's the case for
9510  * affected systems.
9511  */
9512 static void quirk_pipea_force(struct drm_device *dev)
9513 {
9514         struct drm_i915_private *dev_priv = dev->dev_private;
9515
9516         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9517         DRM_INFO("applying pipe a force quirk\n");
9518 }
9519
9520 /*
9521  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9522  */
9523 static void quirk_ssc_force_disable(struct drm_device *dev)
9524 {
9525         struct drm_i915_private *dev_priv = dev->dev_private;
9526         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9527         DRM_INFO("applying lvds SSC disable quirk\n");
9528 }
9529
9530 /*
9531  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9532  * brightness value
9533  */
9534 static void quirk_invert_brightness(struct drm_device *dev)
9535 {
9536         struct drm_i915_private *dev_priv = dev->dev_private;
9537         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9538         DRM_INFO("applying inverted panel brightness quirk\n");
9539 }
9540
9541 struct intel_quirk {
9542         int device;
9543         int subsystem_vendor;
9544         int subsystem_device;
9545         void (*hook)(struct drm_device *dev);
9546 };
9547
9548 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9549 struct intel_dmi_quirk {
9550         void (*hook)(struct drm_device *dev);
9551         const struct dmi_system_id (*dmi_id_list)[];
9552 };
9553
9554 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9555 {
9556         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9557         return 1;
9558 }
9559
9560 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9561         {
9562                 .dmi_id_list = &(const struct dmi_system_id[]) {
9563                         {
9564                                 .callback = intel_dmi_reverse_brightness,
9565                                 .ident = "NCR Corporation",
9566                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9567                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9568                                 },
9569                         },
9570                         { }  /* terminating entry */
9571                 },
9572                 .hook = quirk_invert_brightness,
9573         },
9574 };
9575
9576 static struct intel_quirk intel_quirks[] = {
9577         /* HP Mini needs pipe A force quirk (LP: #322104) */
9578         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9579
9580         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9581         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9582
9583         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9584         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9585
9586         /* 830/845 need to leave pipe A & dpll A up */
9587         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9588         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9589
9590         /* Lenovo U160 cannot use SSC on LVDS */
9591         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9592
9593         /* Sony Vaio Y cannot use SSC on LVDS */
9594         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9595
9596         /* Acer Aspire 5734Z must invert backlight brightness */
9597         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9598
9599         /* Acer/eMachines G725 */
9600         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9601
9602         /* Acer/eMachines e725 */
9603         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9604
9605         /* Acer/Packard Bell NCL20 */
9606         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9607
9608         /* Acer Aspire 4736Z */
9609         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9610 };
9611
9612 static void intel_init_quirks(struct drm_device *dev)
9613 {
9614         struct pci_dev *d = dev->pdev;
9615         int i;
9616
9617         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9618                 struct intel_quirk *q = &intel_quirks[i];
9619
9620                 if (d->device == q->device &&
9621                     (d->subsystem_vendor == q->subsystem_vendor ||
9622                      q->subsystem_vendor == PCI_ANY_ID) &&
9623                     (d->subsystem_device == q->subsystem_device ||
9624                      q->subsystem_device == PCI_ANY_ID))
9625                         q->hook(dev);
9626         }
9627         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9628                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9629                         intel_dmi_quirks[i].hook(dev);
9630         }
9631 }
9632
9633 /* Disable the VGA plane that we never use */
9634 static void i915_disable_vga(struct drm_device *dev)
9635 {
9636         struct drm_i915_private *dev_priv = dev->dev_private;
9637         u8 sr1;
9638         u32 vga_reg = i915_vgacntrl_reg(dev);
9639
9640         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9641         outb(SR01, VGA_SR_INDEX);
9642         sr1 = inb(VGA_SR_DATA);
9643         outb(sr1 | 1<<5, VGA_SR_DATA);
9644         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9645         udelay(300);
9646
9647         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9648         POSTING_READ(vga_reg);
9649 }
9650
9651 void intel_modeset_init_hw(struct drm_device *dev)
9652 {
9653         intel_init_power_well(dev);
9654
9655         intel_prepare_ddi(dev);
9656
9657         intel_init_clock_gating(dev);
9658
9659         mutex_lock(&dev->struct_mutex);
9660         intel_enable_gt_powersave(dev);
9661         mutex_unlock(&dev->struct_mutex);
9662 }
9663
9664 void intel_modeset_suspend_hw(struct drm_device *dev)
9665 {
9666         intel_suspend_hw(dev);
9667 }
9668
9669 void intel_modeset_init(struct drm_device *dev)
9670 {
9671         struct drm_i915_private *dev_priv = dev->dev_private;
9672         int i, j, ret;
9673
9674         drm_mode_config_init(dev);
9675
9676         dev->mode_config.min_width = 0;
9677         dev->mode_config.min_height = 0;
9678
9679         dev->mode_config.preferred_depth = 24;
9680         dev->mode_config.prefer_shadow = 1;
9681
9682         dev->mode_config.funcs = &intel_mode_funcs;
9683
9684         intel_init_quirks(dev);
9685
9686         intel_init_pm(dev);
9687
9688         if (INTEL_INFO(dev)->num_pipes == 0)
9689                 return;
9690
9691         intel_init_display(dev);
9692
9693         if (IS_GEN2(dev)) {
9694                 dev->mode_config.max_width = 2048;
9695                 dev->mode_config.max_height = 2048;
9696         } else if (IS_GEN3(dev)) {
9697                 dev->mode_config.max_width = 4096;
9698                 dev->mode_config.max_height = 4096;
9699         } else {
9700                 dev->mode_config.max_width = 8192;
9701                 dev->mode_config.max_height = 8192;
9702         }
9703         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9704
9705         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9706                       INTEL_INFO(dev)->num_pipes,
9707                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9708
9709         for_each_pipe(i) {
9710                 intel_crtc_init(dev, i);
9711                 for (j = 0; j < dev_priv->num_plane; j++) {
9712                         ret = intel_plane_init(dev, i, j);
9713                         if (ret)
9714                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9715                                               pipe_name(i), sprite_name(i, j), ret);
9716                 }
9717         }
9718
9719         intel_cpu_pll_init(dev);
9720         intel_shared_dpll_init(dev);
9721
9722         /* Just disable it once at startup */
9723         i915_disable_vga(dev);
9724         intel_setup_outputs(dev);
9725
9726         /* Just in case the BIOS is doing something questionable. */
9727         intel_disable_fbc(dev);
9728 }
9729
9730 static void
9731 intel_connector_break_all_links(struct intel_connector *connector)
9732 {
9733         connector->base.dpms = DRM_MODE_DPMS_OFF;
9734         connector->base.encoder = NULL;
9735         connector->encoder->connectors_active = false;
9736         connector->encoder->base.crtc = NULL;
9737 }
9738
9739 static void intel_enable_pipe_a(struct drm_device *dev)
9740 {
9741         struct intel_connector *connector;
9742         struct drm_connector *crt = NULL;
9743         struct intel_load_detect_pipe load_detect_temp;
9744
9745         /* We can't just switch on the pipe A, we need to set things up with a
9746          * proper mode and output configuration. As a gross hack, enable pipe A
9747          * by enabling the load detect pipe once. */
9748         list_for_each_entry(connector,
9749                             &dev->mode_config.connector_list,
9750                             base.head) {
9751                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9752                         crt = &connector->base;
9753                         break;
9754                 }
9755         }
9756
9757         if (!crt)
9758                 return;
9759
9760         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9761                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9762
9763
9764 }
9765
9766 static bool
9767 intel_check_plane_mapping(struct intel_crtc *crtc)
9768 {
9769         struct drm_device *dev = crtc->base.dev;
9770         struct drm_i915_private *dev_priv = dev->dev_private;
9771         u32 reg, val;
9772
9773         if (INTEL_INFO(dev)->num_pipes == 1)
9774                 return true;
9775
9776         reg = DSPCNTR(!crtc->plane);
9777         val = I915_READ(reg);
9778
9779         if ((val & DISPLAY_PLANE_ENABLE) &&
9780             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9781                 return false;
9782
9783         return true;
9784 }
9785
9786 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9787 {
9788         struct drm_device *dev = crtc->base.dev;
9789         struct drm_i915_private *dev_priv = dev->dev_private;
9790         u32 reg;
9791
9792         /* Clear any frame start delays used for debugging left by the BIOS */
9793         reg = PIPECONF(crtc->config.cpu_transcoder);
9794         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9795
9796         /* We need to sanitize the plane -> pipe mapping first because this will
9797          * disable the crtc (and hence change the state) if it is wrong. Note
9798          * that gen4+ has a fixed plane -> pipe mapping.  */
9799         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9800                 struct intel_connector *connector;
9801                 bool plane;
9802
9803                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9804                               crtc->base.base.id);
9805
9806                 /* Pipe has the wrong plane attached and the plane is active.
9807                  * Temporarily change the plane mapping and disable everything
9808                  * ...  */
9809                 plane = crtc->plane;
9810                 crtc->plane = !plane;
9811                 dev_priv->display.crtc_disable(&crtc->base);
9812                 crtc->plane = plane;
9813
9814                 /* ... and break all links. */
9815                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9816                                     base.head) {
9817                         if (connector->encoder->base.crtc != &crtc->base)
9818                                 continue;
9819
9820                         intel_connector_break_all_links(connector);
9821                 }
9822
9823                 WARN_ON(crtc->active);
9824                 crtc->base.enabled = false;
9825         }
9826
9827         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9828             crtc->pipe == PIPE_A && !crtc->active) {
9829                 /* BIOS forgot to enable pipe A, this mostly happens after
9830                  * resume. Force-enable the pipe to fix this, the update_dpms
9831                  * call below we restore the pipe to the right state, but leave
9832                  * the required bits on. */
9833                 intel_enable_pipe_a(dev);
9834         }
9835
9836         /* Adjust the state of the output pipe according to whether we
9837          * have active connectors/encoders. */
9838         intel_crtc_update_dpms(&crtc->base);
9839
9840         if (crtc->active != crtc->base.enabled) {
9841                 struct intel_encoder *encoder;
9842
9843                 /* This can happen either due to bugs in the get_hw_state
9844                  * functions or because the pipe is force-enabled due to the
9845                  * pipe A quirk. */
9846                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9847                               crtc->base.base.id,
9848                               crtc->base.enabled ? "enabled" : "disabled",
9849                               crtc->active ? "enabled" : "disabled");
9850
9851                 crtc->base.enabled = crtc->active;
9852
9853                 /* Because we only establish the connector -> encoder ->
9854                  * crtc links if something is active, this means the
9855                  * crtc is now deactivated. Break the links. connector
9856                  * -> encoder links are only establish when things are
9857                  *  actually up, hence no need to break them. */
9858                 WARN_ON(crtc->active);
9859
9860                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9861                         WARN_ON(encoder->connectors_active);
9862                         encoder->base.crtc = NULL;
9863                 }
9864         }
9865 }
9866
9867 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9868 {
9869         struct intel_connector *connector;
9870         struct drm_device *dev = encoder->base.dev;
9871
9872         /* We need to check both for a crtc link (meaning that the
9873          * encoder is active and trying to read from a pipe) and the
9874          * pipe itself being active. */
9875         bool has_active_crtc = encoder->base.crtc &&
9876                 to_intel_crtc(encoder->base.crtc)->active;
9877
9878         if (encoder->connectors_active && !has_active_crtc) {
9879                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9880                               encoder->base.base.id,
9881                               drm_get_encoder_name(&encoder->base));
9882
9883                 /* Connector is active, but has no active pipe. This is
9884                  * fallout from our resume register restoring. Disable
9885                  * the encoder manually again. */
9886                 if (encoder->base.crtc) {
9887                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9888                                       encoder->base.base.id,
9889                                       drm_get_encoder_name(&encoder->base));
9890                         encoder->disable(encoder);
9891                 }
9892
9893                 /* Inconsistent output/port/pipe state happens presumably due to
9894                  * a bug in one of the get_hw_state functions. Or someplace else
9895                  * in our code, like the register restore mess on resume. Clamp
9896                  * things to off as a safer default. */
9897                 list_for_each_entry(connector,
9898                                     &dev->mode_config.connector_list,
9899                                     base.head) {
9900                         if (connector->encoder != encoder)
9901                                 continue;
9902
9903                         intel_connector_break_all_links(connector);
9904                 }
9905         }
9906         /* Enabled encoders without active connectors will be fixed in
9907          * the crtc fixup. */
9908 }
9909
9910 void i915_redisable_vga(struct drm_device *dev)
9911 {
9912         struct drm_i915_private *dev_priv = dev->dev_private;
9913         u32 vga_reg = i915_vgacntrl_reg(dev);
9914
9915         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9916                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9917                 i915_disable_vga(dev);
9918         }
9919 }
9920
9921 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9922 {
9923         struct drm_i915_private *dev_priv = dev->dev_private;
9924         enum pipe pipe;
9925         struct intel_crtc *crtc;
9926         struct intel_encoder *encoder;
9927         struct intel_connector *connector;
9928         int i;
9929
9930         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9931                             base.head) {
9932                 memset(&crtc->config, 0, sizeof(crtc->config));
9933
9934                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9935                                                                  &crtc->config);
9936
9937                 crtc->base.enabled = crtc->active;
9938
9939                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9940                               crtc->base.base.id,
9941                               crtc->active ? "enabled" : "disabled");
9942         }
9943
9944         /* FIXME: Smash this into the new shared dpll infrastructure. */
9945         if (HAS_DDI(dev))
9946                 intel_ddi_setup_hw_pll_state(dev);
9947
9948         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9949                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9950
9951                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9952                 pll->active = 0;
9953                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9954                                     base.head) {
9955                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9956                                 pll->active++;
9957                 }
9958                 pll->refcount = pll->active;
9959
9960                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9961                               pll->name, pll->refcount);
9962         }
9963
9964         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9965                             base.head) {
9966                 pipe = 0;
9967
9968                 if (encoder->get_hw_state(encoder, &pipe)) {
9969                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9970                         encoder->base.crtc = &crtc->base;
9971                         if (encoder->get_config)
9972                                 encoder->get_config(encoder, &crtc->config);
9973                 } else {
9974                         encoder->base.crtc = NULL;
9975                 }
9976
9977                 encoder->connectors_active = false;
9978                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9979                               encoder->base.base.id,
9980                               drm_get_encoder_name(&encoder->base),
9981                               encoder->base.crtc ? "enabled" : "disabled",
9982                               pipe);
9983         }
9984
9985         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9986                             base.head) {
9987                 if (!crtc->active)
9988                         continue;
9989                 if (dev_priv->display.get_clock)
9990                         dev_priv->display.get_clock(crtc,
9991                                                     &crtc->config);
9992         }
9993
9994         list_for_each_entry(connector, &dev->mode_config.connector_list,
9995                             base.head) {
9996                 if (connector->get_hw_state(connector)) {
9997                         connector->base.dpms = DRM_MODE_DPMS_ON;
9998                         connector->encoder->connectors_active = true;
9999                         connector->base.encoder = &connector->encoder->base;
10000                 } else {
10001                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10002                         connector->base.encoder = NULL;
10003                 }
10004                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10005                               connector->base.base.id,
10006                               drm_get_connector_name(&connector->base),
10007                               connector->base.encoder ? "enabled" : "disabled");
10008         }
10009 }
10010
10011 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10012  * and i915 state tracking structures. */
10013 void intel_modeset_setup_hw_state(struct drm_device *dev,
10014                                   bool force_restore)
10015 {
10016         struct drm_i915_private *dev_priv = dev->dev_private;
10017         enum pipe pipe;
10018         struct drm_plane *plane;
10019         struct intel_crtc *crtc;
10020         struct intel_encoder *encoder;
10021
10022         intel_modeset_readout_hw_state(dev);
10023
10024         /*
10025          * Now that we have the config, copy it to each CRTC struct
10026          * Note that this could go away if we move to using crtc_config
10027          * checking everywhere.
10028          */
10029         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10030                             base.head) {
10031                 if (crtc->active && i915_fastboot) {
10032                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10033
10034                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10035                                       crtc->base.base.id);
10036                         drm_mode_debug_printmodeline(&crtc->base.mode);
10037                 }
10038         }
10039
10040         /* HW state is read out, now we need to sanitize this mess. */
10041         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10042                             base.head) {
10043                 intel_sanitize_encoder(encoder);
10044         }
10045
10046         for_each_pipe(pipe) {
10047                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10048                 intel_sanitize_crtc(crtc);
10049                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10050         }
10051
10052         if (force_restore) {
10053                 /*
10054                  * We need to use raw interfaces for restoring state to avoid
10055                  * checking (bogus) intermediate states.
10056                  */
10057                 for_each_pipe(pipe) {
10058                         struct drm_crtc *crtc =
10059                                 dev_priv->pipe_to_crtc_mapping[pipe];
10060
10061                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10062                                          crtc->fb);
10063                 }
10064                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10065                         intel_plane_restore(plane);
10066
10067                 i915_redisable_vga(dev);
10068         } else {
10069                 intel_modeset_update_staged_output_state(dev);
10070         }
10071
10072         intel_modeset_check_state(dev);
10073
10074         drm_mode_config_reset(dev);
10075 }
10076
10077 void intel_modeset_gem_init(struct drm_device *dev)
10078 {
10079         intel_modeset_init_hw(dev);
10080
10081         intel_setup_overlay(dev);
10082
10083         intel_modeset_setup_hw_state(dev, false);
10084 }
10085
10086 void intel_modeset_cleanup(struct drm_device *dev)
10087 {
10088         struct drm_i915_private *dev_priv = dev->dev_private;
10089         struct drm_crtc *crtc;
10090         struct intel_crtc *intel_crtc;
10091
10092         /*
10093          * Interrupts and polling as the first thing to avoid creating havoc.
10094          * Too much stuff here (turning of rps, connectors, ...) would
10095          * experience fancy races otherwise.
10096          */
10097         drm_irq_uninstall(dev);
10098         cancel_work_sync(&dev_priv->hotplug_work);
10099         /*
10100          * Due to the hpd irq storm handling the hotplug work can re-arm the
10101          * poll handlers. Hence disable polling after hpd handling is shut down.
10102          */
10103         drm_kms_helper_poll_fini(dev);
10104
10105         mutex_lock(&dev->struct_mutex);
10106
10107         intel_unregister_dsm_handler();
10108
10109         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10110                 /* Skip inactive CRTCs */
10111                 if (!crtc->fb)
10112                         continue;
10113
10114                 intel_crtc = to_intel_crtc(crtc);
10115                 intel_increase_pllclock(crtc);
10116         }
10117
10118         intel_disable_fbc(dev);
10119
10120         intel_disable_gt_powersave(dev);
10121
10122         ironlake_teardown_rc6(dev);
10123
10124         mutex_unlock(&dev->struct_mutex);
10125
10126         /* flush any delayed tasks or pending work */
10127         flush_scheduled_work();
10128
10129         /* destroy backlight, if any, before the connectors */
10130         intel_panel_destroy_backlight(dev);
10131
10132         drm_mode_config_cleanup(dev);
10133
10134         intel_cleanup_overlay(dev);
10135 }
10136
10137 /*
10138  * Return which encoder is currently attached for connector.
10139  */
10140 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10141 {
10142         return &intel_attached_encoder(connector)->base;
10143 }
10144
10145 void intel_connector_attach_encoder(struct intel_connector *connector,
10146                                     struct intel_encoder *encoder)
10147 {
10148         connector->encoder = encoder;
10149         drm_mode_connector_attach_encoder(&connector->base,
10150                                           &encoder->base);
10151 }
10152
10153 /*
10154  * set vga decode state - true == enable VGA decode
10155  */
10156 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10157 {
10158         struct drm_i915_private *dev_priv = dev->dev_private;
10159         u16 gmch_ctrl;
10160
10161         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10162         if (state)
10163                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10164         else
10165                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10166         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10167         return 0;
10168 }
10169
10170 struct intel_display_error_state {
10171
10172         u32 power_well_driver;
10173
10174         struct intel_cursor_error_state {
10175                 u32 control;
10176                 u32 position;
10177                 u32 base;
10178                 u32 size;
10179         } cursor[I915_MAX_PIPES];
10180
10181         struct intel_pipe_error_state {
10182                 enum transcoder cpu_transcoder;
10183                 u32 conf;
10184                 u32 source;
10185
10186                 u32 htotal;
10187                 u32 hblank;
10188                 u32 hsync;
10189                 u32 vtotal;
10190                 u32 vblank;
10191                 u32 vsync;
10192         } pipe[I915_MAX_PIPES];
10193
10194         struct intel_plane_error_state {
10195                 u32 control;
10196                 u32 stride;
10197                 u32 size;
10198                 u32 pos;
10199                 u32 addr;
10200                 u32 surface;
10201                 u32 tile_offset;
10202         } plane[I915_MAX_PIPES];
10203 };
10204
10205 struct intel_display_error_state *
10206 intel_display_capture_error_state(struct drm_device *dev)
10207 {
10208         drm_i915_private_t *dev_priv = dev->dev_private;
10209         struct intel_display_error_state *error;
10210         enum transcoder cpu_transcoder;
10211         int i;
10212
10213         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10214         if (error == NULL)
10215                 return NULL;
10216
10217         if (HAS_POWER_WELL(dev))
10218                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10219
10220         for_each_pipe(i) {
10221                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10222                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10223
10224                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10225                         error->cursor[i].control = I915_READ(CURCNTR(i));
10226                         error->cursor[i].position = I915_READ(CURPOS(i));
10227                         error->cursor[i].base = I915_READ(CURBASE(i));
10228                 } else {
10229                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10230                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10231                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10232                 }
10233
10234                 error->plane[i].control = I915_READ(DSPCNTR(i));
10235                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10236                 if (INTEL_INFO(dev)->gen <= 3) {
10237                         error->plane[i].size = I915_READ(DSPSIZE(i));
10238                         error->plane[i].pos = I915_READ(DSPPOS(i));
10239                 }
10240                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10241                         error->plane[i].addr = I915_READ(DSPADDR(i));
10242                 if (INTEL_INFO(dev)->gen >= 4) {
10243                         error->plane[i].surface = I915_READ(DSPSURF(i));
10244                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10245                 }
10246
10247                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10248                 error->pipe[i].source = I915_READ(PIPESRC(i));
10249                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10250                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10251                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10252                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10253                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10254                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10255         }
10256
10257         /* In the code above we read the registers without checking if the power
10258          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10259          * prevent the next I915_WRITE from detecting it and printing an error
10260          * message. */
10261         if (HAS_POWER_WELL(dev))
10262                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10263
10264         return error;
10265 }
10266
10267 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10268
10269 void
10270 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10271                                 struct drm_device *dev,
10272                                 struct intel_display_error_state *error)
10273 {
10274         int i;
10275
10276         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10277         if (HAS_POWER_WELL(dev))
10278                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10279                            error->power_well_driver);
10280         for_each_pipe(i) {
10281                 err_printf(m, "Pipe [%d]:\n", i);
10282                 err_printf(m, "  CPU transcoder: %c\n",
10283                            transcoder_name(error->pipe[i].cpu_transcoder));
10284                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10285                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10286                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10287                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10288                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10289                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10290                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10291                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10292
10293                 err_printf(m, "Plane [%d]:\n", i);
10294                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10295                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10296                 if (INTEL_INFO(dev)->gen <= 3) {
10297                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10298                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10299                 }
10300                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10301                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10302                 if (INTEL_INFO(dev)->gen >= 4) {
10303                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10304                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10305                 }
10306
10307                 err_printf(m, "Cursor [%d]:\n", i);
10308                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10309                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10310                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10311         }
10312 }