2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state,
92 static int intel_framebuffer_init(struct drm_device *dev,
93 struct intel_framebuffer *ifb,
94 struct drm_mode_fb_cmd2 *mode_cmd,
95 struct drm_i915_gem_object *obj);
96 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
97 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
98 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
99 struct intel_link_m_n *m_n,
100 struct intel_link_m_n *m2_n2);
101 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
102 static void haswell_set_pipeconf(struct drm_crtc *crtc);
103 static void intel_set_pipe_csc(struct drm_crtc *crtc);
104 static void vlv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void chv_prepare_pll(struct intel_crtc *crtc,
107 const struct intel_crtc_state *pipe_config);
108 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
109 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
110 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
111 struct intel_crtc_state *crtc_state);
112 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
115 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
117 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
119 if (!connector->mst_port)
120 return connector->encoder;
122 return &connector->mst_port->mst_encoders[pipe]->base;
131 int p2_slow, p2_fast;
134 typedef struct intel_limit intel_limit_t;
136 intel_range_t dot, vco, n, m, m1, m2, p, p1;
141 intel_pch_rawclk(struct drm_device *dev)
143 struct drm_i915_private *dev_priv = dev->dev_private;
145 WARN_ON(!HAS_PCH_SPLIT(dev));
147 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
150 static inline u32 /* units of 100MHz */
151 intel_fdi_link_freq(struct drm_device *dev)
154 struct drm_i915_private *dev_priv = dev->dev_private;
155 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
160 static const intel_limit_t intel_limits_i8xx_dac = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 2 },
173 static const intel_limit_t intel_limits_i8xx_dvo = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 2, .max = 33 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 4, .p2_fast = 4 },
186 static const intel_limit_t intel_limits_i8xx_lvds = {
187 .dot = { .min = 25000, .max = 350000 },
188 .vco = { .min = 908000, .max = 1512000 },
189 .n = { .min = 2, .max = 16 },
190 .m = { .min = 96, .max = 140 },
191 .m1 = { .min = 18, .max = 26 },
192 .m2 = { .min = 6, .max = 16 },
193 .p = { .min = 4, .max = 128 },
194 .p1 = { .min = 1, .max = 6 },
195 .p2 = { .dot_limit = 165000,
196 .p2_slow = 14, .p2_fast = 7 },
199 static const intel_limit_t intel_limits_i9xx_sdvo = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 200000,
209 .p2_slow = 10, .p2_fast = 5 },
212 static const intel_limit_t intel_limits_i9xx_lvds = {
213 .dot = { .min = 20000, .max = 400000 },
214 .vco = { .min = 1400000, .max = 2800000 },
215 .n = { .min = 1, .max = 6 },
216 .m = { .min = 70, .max = 120 },
217 .m1 = { .min = 8, .max = 18 },
218 .m2 = { .min = 3, .max = 7 },
219 .p = { .min = 7, .max = 98 },
220 .p1 = { .min = 1, .max = 8 },
221 .p2 = { .dot_limit = 112000,
222 .p2_slow = 14, .p2_fast = 7 },
226 static const intel_limit_t intel_limits_g4x_sdvo = {
227 .dot = { .min = 25000, .max = 270000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 10, .max = 30 },
234 .p1 = { .min = 1, .max = 3},
235 .p2 = { .dot_limit = 270000,
241 static const intel_limit_t intel_limits_g4x_hdmi = {
242 .dot = { .min = 22000, .max = 400000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 4 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 16, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8},
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 10, .p2_fast = 5 },
254 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
255 .dot = { .min = 20000, .max = 115000 },
256 .vco = { .min = 1750000, .max = 3500000 },
257 .n = { .min = 1, .max = 3 },
258 .m = { .min = 104, .max = 138 },
259 .m1 = { .min = 17, .max = 23 },
260 .m2 = { .min = 5, .max = 11 },
261 .p = { .min = 28, .max = 112 },
262 .p1 = { .min = 2, .max = 8 },
263 .p2 = { .dot_limit = 0,
264 .p2_slow = 14, .p2_fast = 14
268 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
269 .dot = { .min = 80000, .max = 224000 },
270 .vco = { .min = 1750000, .max = 3500000 },
271 .n = { .min = 1, .max = 3 },
272 .m = { .min = 104, .max = 138 },
273 .m1 = { .min = 17, .max = 23 },
274 .m2 = { .min = 5, .max = 11 },
275 .p = { .min = 14, .max = 42 },
276 .p1 = { .min = 2, .max = 6 },
277 .p2 = { .dot_limit = 0,
278 .p2_slow = 7, .p2_fast = 7
282 static const intel_limit_t intel_limits_pineview_sdvo = {
283 .dot = { .min = 20000, .max = 400000},
284 .vco = { .min = 1700000, .max = 3500000 },
285 /* Pineview's Ncounter is a ring counter */
286 .n = { .min = 3, .max = 6 },
287 .m = { .min = 2, .max = 256 },
288 /* Pineview only has one combined m divider, which we treat as m2. */
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 200000,
294 .p2_slow = 10, .p2_fast = 5 },
297 static const intel_limit_t intel_limits_pineview_lvds = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1700000, .max = 3500000 },
300 .n = { .min = 3, .max = 6 },
301 .m = { .min = 2, .max = 256 },
302 .m1 = { .min = 0, .max = 0 },
303 .m2 = { .min = 0, .max = 254 },
304 .p = { .min = 7, .max = 112 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 112000,
307 .p2_slow = 14, .p2_fast = 14 },
310 /* Ironlake / Sandybridge
312 * We calculate clock using (register_value + 2) for N/M1/M2, so here
313 * the range value for them is (actual_value - 2).
315 static const intel_limit_t intel_limits_ironlake_dac = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 5 },
319 .m = { .min = 79, .max = 127 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 5, .max = 80 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 10, .p2_fast = 5 },
328 static const intel_limit_t intel_limits_ironlake_single_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 118 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 28, .max = 112 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 14, .p2_fast = 14 },
341 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
342 .dot = { .min = 25000, .max = 350000 },
343 .vco = { .min = 1760000, .max = 3510000 },
344 .n = { .min = 1, .max = 3 },
345 .m = { .min = 79, .max = 127 },
346 .m1 = { .min = 12, .max = 22 },
347 .m2 = { .min = 5, .max = 9 },
348 .p = { .min = 14, .max = 56 },
349 .p1 = { .min = 2, .max = 8 },
350 .p2 = { .dot_limit = 225000,
351 .p2_slow = 7, .p2_fast = 7 },
354 /* LVDS 100mhz refclk limits. */
355 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 2 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 28, .max = 112 },
363 .p1 = { .min = 2, .max = 8 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 14, .p2_fast = 14 },
368 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
369 .dot = { .min = 25000, .max = 350000 },
370 .vco = { .min = 1760000, .max = 3510000 },
371 .n = { .min = 1, .max = 3 },
372 .m = { .min = 79, .max = 126 },
373 .m1 = { .min = 12, .max = 22 },
374 .m2 = { .min = 5, .max = 9 },
375 .p = { .min = 14, .max = 42 },
376 .p1 = { .min = 2, .max = 6 },
377 .p2 = { .dot_limit = 225000,
378 .p2_slow = 7, .p2_fast = 7 },
381 static const intel_limit_t intel_limits_vlv = {
383 * These are the data rate limits (measured in fast clocks)
384 * since those are the strictest limits we have. The fast
385 * clock and actual rate limits are more relaxed, so checking
386 * them would make no difference.
388 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
389 .vco = { .min = 4000000, .max = 6000000 },
390 .n = { .min = 1, .max = 7 },
391 .m1 = { .min = 2, .max = 3 },
392 .m2 = { .min = 11, .max = 156 },
393 .p1 = { .min = 2, .max = 3 },
394 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
397 static const intel_limit_t intel_limits_chv = {
399 * These are the data rate limits (measured in fast clocks)
400 * since those are the strictest limits we have. The fast
401 * clock and actual rate limits are more relaxed, so checking
402 * them would make no difference.
404 .dot = { .min = 25000 * 5, .max = 540000 * 5},
405 .vco = { .min = 4800000, .max = 6480000 },
406 .n = { .min = 1, .max = 1 },
407 .m1 = { .min = 2, .max = 2 },
408 .m2 = { .min = 24 << 22, .max = 175 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 14 },
413 static const intel_limit_t intel_limits_bxt = {
414 /* FIXME: find real dot limits */
415 .dot = { .min = 0, .max = INT_MAX },
416 .vco = { .min = 4800000, .max = 6480000 },
417 .n = { .min = 1, .max = 1 },
418 .m1 = { .min = 2, .max = 2 },
419 /* FIXME: find real m2 limits */
420 .m2 = { .min = 2 << 22, .max = 255 << 22 },
421 .p1 = { .min = 2, .max = 4 },
422 .p2 = { .p2_slow = 1, .p2_fast = 20 },
425 static void vlv_clock(int refclk, intel_clock_t *clock)
427 clock->m = clock->m1 * clock->m2;
428 clock->p = clock->p1 * clock->p2;
429 if (WARN_ON(clock->n == 0 || clock->p == 0))
431 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
432 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
436 * Returns whether any output on the specified pipe is of the specified type
438 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
440 struct drm_device *dev = crtc->base.dev;
441 struct intel_encoder *encoder;
443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
444 if (encoder->type == type)
451 * Returns whether any output on the specified pipe will have the specified
452 * type after a staged modeset is complete, i.e., the same as
453 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 struct drm_atomic_state *state = crtc_state->base.state;
460 struct drm_connector *connector;
461 struct drm_connector_state *connector_state;
462 struct intel_encoder *encoder;
463 int i, num_connectors = 0;
465 for_each_connector_in_state(state, connector, connector_state, i) {
466 if (connector_state->crtc != crtc_state->base.crtc)
471 encoder = to_intel_encoder(connector_state->best_encoder);
472 if (encoder->type == type)
476 WARN_ON(num_connectors == 0);
481 static const intel_limit_t *
482 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
484 struct drm_device *dev = crtc_state->base.crtc->dev;
485 const intel_limit_t *limit;
487 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
488 if (intel_is_dual_link_lvds(dev)) {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_dual_lvds_100m;
492 limit = &intel_limits_ironlake_dual_lvds;
494 if (refclk == 100000)
495 limit = &intel_limits_ironlake_single_lvds_100m;
497 limit = &intel_limits_ironlake_single_lvds;
500 limit = &intel_limits_ironlake_dac;
505 static const intel_limit_t *
506 intel_g4x_limit(struct intel_crtc_state *crtc_state)
508 struct drm_device *dev = crtc_state->base.crtc->dev;
509 const intel_limit_t *limit;
511 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
512 if (intel_is_dual_link_lvds(dev))
513 limit = &intel_limits_g4x_dual_channel_lvds;
515 limit = &intel_limits_g4x_single_channel_lvds;
516 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
517 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
518 limit = &intel_limits_g4x_hdmi;
519 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
520 limit = &intel_limits_g4x_sdvo;
521 } else /* The option is for other outputs */
522 limit = &intel_limits_i9xx_sdvo;
527 static const intel_limit_t *
528 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
530 struct drm_device *dev = crtc_state->base.crtc->dev;
531 const intel_limit_t *limit;
534 limit = &intel_limits_bxt;
535 else if (HAS_PCH_SPLIT(dev))
536 limit = intel_ironlake_limit(crtc_state, refclk);
537 else if (IS_G4X(dev)) {
538 limit = intel_g4x_limit(crtc_state);
539 } else if (IS_PINEVIEW(dev)) {
540 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
541 limit = &intel_limits_pineview_lvds;
543 limit = &intel_limits_pineview_sdvo;
544 } else if (IS_CHERRYVIEW(dev)) {
545 limit = &intel_limits_chv;
546 } else if (IS_VALLEYVIEW(dev)) {
547 limit = &intel_limits_vlv;
548 } else if (!IS_GEN2(dev)) {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i9xx_lvds;
552 limit = &intel_limits_i9xx_sdvo;
554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i8xx_lvds;
556 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
557 limit = &intel_limits_i8xx_dvo;
559 limit = &intel_limits_i8xx_dac;
564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
565 static void pineview_clock(int refclk, intel_clock_t *clock)
567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
569 if (WARN_ON(clock->n == 0 || clock->p == 0))
571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
577 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580 static void i9xx_clock(int refclk, intel_clock_t *clock)
582 clock->m = i9xx_dpll_compute_m(clock);
583 clock->p = clock->p1 * clock->p2;
584 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
586 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
587 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static void chv_clock(int refclk, intel_clock_t *clock)
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
603 * Returns whether the given set of divisors are valid for a given refclk with
604 * the given connectors.
607 static bool intel_PLL_is_valid(struct drm_device *dev,
608 const intel_limit_t *limit,
609 const intel_clock_t *clock)
611 if (clock->n < limit->n.min || limit->n.max < clock->n)
612 INTELPllInvalid("n out of range\n");
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
616 INTELPllInvalid("m2 out of range\n");
617 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
618 INTELPllInvalid("m1 out of range\n");
620 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
621 if (clock->m1 <= clock->m2)
622 INTELPllInvalid("m1 <= m2\n");
624 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
625 if (clock->p < limit->p.min || limit->p.max < clock->p)
626 INTELPllInvalid("p out of range\n");
627 if (clock->m < limit->m.min || limit->m.max < clock->m)
628 INTELPllInvalid("m out of range\n");
631 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
632 INTELPllInvalid("vco out of range\n");
633 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
634 * connector, etc., rather than just a single range.
636 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
637 INTELPllInvalid("dot out of range\n");
643 i9xx_find_best_dpll(const intel_limit_t *limit,
644 struct intel_crtc_state *crtc_state,
645 int target, int refclk, intel_clock_t *match_clock,
646 intel_clock_t *best_clock)
648 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
649 struct drm_device *dev = crtc->base.dev;
653 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
662 clock.p2 = limit->p2.p2_slow;
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
667 clock.p2 = limit->p2.p2_fast;
670 memset(best_clock, 0, sizeof(*best_clock));
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 if (clock.m2 >= clock.m1)
678 for (clock.n = limit->n.min;
679 clock.n <= limit->n.max; clock.n++) {
680 for (clock.p1 = limit->p1.min;
681 clock.p1 <= limit->p1.max; clock.p1++) {
684 i9xx_clock(refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
689 clock.p != match_clock->p)
692 this_err = abs(clock.dot - target);
693 if (this_err < err) {
702 return (err != target);
706 pnv_find_best_dpll(const intel_limit_t *limit,
707 struct intel_crtc_state *crtc_state,
708 int target, int refclk, intel_clock_t *match_clock,
709 intel_clock_t *best_clock)
711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
712 struct drm_device *dev = crtc->base.dev;
716 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
718 * For LVDS just rely on its current settings for dual-channel.
719 * We haven't figured out how to reliably set up different
720 * single/dual channel state, if we even can.
722 if (intel_is_dual_link_lvds(dev))
723 clock.p2 = limit->p2.p2_fast;
725 clock.p2 = limit->p2.p2_slow;
727 if (target < limit->p2.dot_limit)
728 clock.p2 = limit->p2.p2_slow;
730 clock.p2 = limit->p2.p2_fast;
733 memset(best_clock, 0, sizeof(*best_clock));
735 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
737 for (clock.m2 = limit->m2.min;
738 clock.m2 <= limit->m2.max; clock.m2++) {
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
745 pineview_clock(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
750 clock.p != match_clock->p)
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
763 return (err != target);
767 g4x_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
772 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
773 struct drm_device *dev = crtc->base.dev;
777 /* approximately equals target * 0.00585 */
778 int err_most = (target >> 8) + (target >> 9);
781 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
782 if (intel_is_dual_link_lvds(dev))
783 clock.p2 = limit->p2.p2_fast;
785 clock.p2 = limit->p2.p2_slow;
787 if (target < limit->p2.dot_limit)
788 clock.p2 = limit->p2.p2_slow;
790 clock.p2 = limit->p2.p2_fast;
793 memset(best_clock, 0, sizeof(*best_clock));
794 max_n = limit->n.max;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
806 i9xx_clock(refclk, &clock);
807 if (!intel_PLL_is_valid(dev, limit,
811 this_err = abs(clock.dot - target);
812 if (this_err < err_most) {
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
839 if (IS_CHERRYVIEW(dev)) {
842 return calculated_clock->p > best_clock->p;
845 if (WARN_ON_ONCE(!target_freq))
848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
862 return *error_ppm + 10 < best_error_ppm;
866 vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
872 struct drm_device *dev = crtc->base.dev;
874 unsigned int bestppm = 1000000;
875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
879 target *= 5; /* fast clock */
881 memset(best_clock, 0, sizeof(*best_clock));
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
888 clock.p = clock.p1 * clock.p2;
889 /* based on hardware requirement, prefer bigger m1,m2 values */
890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
896 vlv_clock(refclk, &clock);
898 if (!intel_PLL_is_valid(dev, limit,
902 if (!vlv_PLL_is_optimal(dev, target,
920 chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 unsigned int best_error_ppm;
932 memset(best_clock, 0, sizeof(*best_clock));
933 best_error_ppm = 1000000;
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 unsigned int error_ppm;
949 clock.p = clock.p1 * clock.p2;
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
954 if (m2 > INT_MAX/clock.m1)
959 chv_clock(refclk, &clock);
961 if (!intel_PLL_is_valid(dev, limit, &clock))
964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
969 best_error_ppm = error_ppm;
977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
980 int refclk = i9xx_get_refclk(crtc_state, 0);
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
986 bool intel_crtc_active(struct drm_crtc *crtc)
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
993 * We can ditch the adjusted_mode.crtc_clock check as soon
994 * as Haswell has gained clock readout/fastboot support.
996 * We can ditch the crtc->primary->fb check as soon as we can
997 * properly reconstruct framebuffers.
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1003 return intel_crtc->active && crtc->primary->state->fb &&
1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1013 return intel_crtc->config->cpu_transcoder;
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1024 line_mask = DSL_LINEMASK_GEN2;
1026 line_mask = DSL_LINEMASK_GEN3;
1028 line1 = I915_READ(reg) & line_mask;
1030 line2 = I915_READ(reg) & line_mask;
1032 return line1 == line2;
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
1037 * @crtc: crtc whose pipe to wait for
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1053 struct drm_device *dev = crtc->base.dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056 enum pipe pipe = crtc->pipe;
1058 if (INTEL_INFO(dev)->gen >= 4) {
1059 int reg = PIPECONF(cpu_transcoder);
1061 /* Wait for the Pipe State to go off */
1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1064 WARN(1, "pipe_off wait timed out\n");
1066 /* Wait for the display line to settle */
1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068 WARN(1, "pipe_off wait timed out\n");
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1077 * Returns true if @port is connected, false otherwise.
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1084 if (HAS_PCH_IBX(dev_priv->dev)) {
1085 switch (port->port) {
1087 bit = SDE_PORTB_HOTPLUG;
1090 bit = SDE_PORTC_HOTPLUG;
1093 bit = SDE_PORTD_HOTPLUG;
1099 switch (port->port) {
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1114 return I915_READ(SDEISR) & bit;
1117 static const char *state_string(bool enabled)
1119 return enabled ? "on" : "off";
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
1133 I915_STATE_WARN(cur_state != state,
1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 mutex_lock(&dev_priv->sb_lock);
1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146 mutex_unlock(&dev_priv->sb_lock);
1148 cur_state = val & DSI_PLL_VCO_EN;
1149 I915_STATE_WARN(cur_state != state,
1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1161 if (crtc->config->shared_dpll < 0)
1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1173 struct intel_dpll_hw_state hw_state;
1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180 I915_STATE_WARN(cur_state != state,
1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1204 I915_STATE_WARN(cur_state != state,
1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
1221 I915_STATE_WARN(cur_state != state,
1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1234 /* ILK FDI PLL is always enabled */
1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239 if (HAS_DDI(dev_priv->dev))
1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1265 struct drm_device *dev = dev_priv->dev;
1268 enum pipe panel_pipe = PIPE_A;
1271 if (WARN_ON(HAS_DDI(dev)))
1274 if (HAS_PCH_SPLIT(dev)) {
1277 pp_reg = PCH_PP_CONTROL;
1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1289 pp_reg = PP_CONTROL;
1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1299 I915_STATE_WARN(panel_pipe == pipe && locked,
1300 "panel assertion failure, pipe %c regs locked\n",
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1307 struct drm_device *dev = dev_priv->dev;
1310 if (IS_845G(dev) || IS_I865G(dev))
1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1315 I915_STATE_WARN(cur_state != state,
1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1336 if (!intel_display_power_is_enabled(dev_priv,
1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1345 I915_STATE_WARN(cur_state != state,
1346 "pipe %c assertion failure (expected %s, current %s)\n",
1347 pipe_name(pipe), state_string(state), state_string(cur_state));
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360 I915_STATE_WARN(cur_state != state,
1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1371 struct drm_device *dev = dev_priv->dev;
1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381 "plane %c assertion failure, should be disabled but not\n",
1386 /* Need to check both planes against the pipe */
1387 for_each_pipe(dev_priv, i) {
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1401 struct drm_device *dev = dev_priv->dev;
1405 if (INTEL_INFO(dev)->gen >= 9) {
1406 for_each_sprite(dev_priv, pipe, sprite) {
1407 val = I915_READ(PLANE_CTL(pipe, sprite));
1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1412 } else if (IS_VALLEYVIEW(dev)) {
1413 for_each_sprite(dev_priv, pipe, sprite) {
1414 reg = SPCNTR(pipe, sprite);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & SP_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 sprite_name(pipe, sprite), pipe_name(pipe));
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1422 val = I915_READ(reg);
1423 I915_STATE_WARN(val & SPRITE_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
1428 val = I915_READ(reg);
1429 I915_STATE_WARN(val & DVS_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438 drm_crtc_vblank_put(crtc);
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1461 reg = PCH_TRANSCONF(pipe);
1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
1464 I915_STATE_WARN(enabled,
1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
1472 if ((val & DP_PORT_EN) == 0)
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1493 if ((val & SDVO_ENABLE) == 0)
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1512 if ((val & LVDS_PORT_EN) == 0)
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg, u32 port_sel)
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549 && (val & DP_PIPEB_SELECT),
1550 "IBX PCH dp port still using transcoder B\n");
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1556 u32 val = I915_READ(reg);
1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559 reg, pipe_name(pipe));
1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562 && (val & SDVO_PIPE_B_SELECT),
1563 "IBX PCH hdmi port still using transcoder B\n");
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577 val = I915_READ(reg);
1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
1583 val = I915_READ(reg);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1593 static void intel_init_dpio(struct drm_device *dev)
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1597 if (!IS_VALLEYVIEW(dev))
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614 const struct intel_crtc_state *pipe_config)
1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1626 /* PLL is protected by panel, make sure we can write it */
1627 if (IS_MOBILE(dev_priv->dev))
1628 assert_panel_unlocked(dev_priv, crtc->pipe);
1630 I915_WRITE(reg, dpll);
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638 POSTING_READ(DPLL_MD(crtc->pipe));
1640 /* We do this three times for luck */
1641 I915_WRITE(reg, dpll);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg, dpll);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1649 udelay(150); /* wait for warmup */
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653 const struct intel_crtc_state *pipe_config)
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1665 mutex_lock(&dev_priv->sb_lock);
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1672 mutex_unlock(&dev_priv->sb_lock);
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1682 /* Check PLL is locked */
1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1686 /* not sure when this should be written */
1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688 POSTING_READ(DPLL_MD(pipe));
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1693 struct intel_crtc *crtc;
1696 for_each_intel_crtc(dev, crtc)
1697 count += crtc->active &&
1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
1710 assert_pipe_disabled(dev_priv, crtc->pipe);
1712 /* No really, not for ILK+ */
1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1715 /* PLL is protected by panel, make sure we can write it */
1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1732 /* Wait for the clocks to stabilize. */
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
1738 crtc->config->dpll_hw_state.dpll_md);
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1743 * So write it again.
1745 I915_WRITE(reg, dpll);
1748 /* We do this three times for luck */
1749 I915_WRITE(reg, dpll);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg, dpll);
1754 udelay(150); /* wait for warmup */
1755 I915_WRITE(reg, dpll);
1757 udelay(150); /* wait for warmup */
1761 * i9xx_disable_pll - disable a PLL
1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1767 * Note! This is for pre-ILK only.
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778 intel_num_dvo_pipes(dev) == 1) {
1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1793 I915_WRITE(DPLL(pipe), 0);
1794 POSTING_READ(DPLL(pipe));
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1809 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1810 I915_WRITE(DPLL(pipe), val);
1811 POSTING_READ(DPLL(pipe));
1815 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1820 /* Make sure the pipe isn't still relying on us */
1821 assert_pipe_disabled(dev_priv, pipe);
1823 /* Set PLL en = 0 */
1824 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827 I915_WRITE(DPLL(pipe), val);
1828 POSTING_READ(DPLL(pipe));
1830 mutex_lock(&dev_priv->sb_lock);
1832 /* Disable 10bit clock to display controller */
1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834 val &= ~DPIO_DCLKP_EN;
1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1837 /* disable left/right clock distribution */
1838 if (pipe != PIPE_B) {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 mutex_unlock(&dev_priv->sb_lock);
1851 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1852 struct intel_digital_port *dport,
1853 unsigned int expected_mask)
1858 switch (dport->port) {
1860 port_mask = DPLL_PORTB_READY_MASK;
1864 port_mask = DPLL_PORTC_READY_MASK;
1866 expected_mask <<= 4;
1869 port_mask = DPLL_PORTD_READY_MASK;
1870 dpll_reg = DPIO_PHY_STATUS;
1876 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1881 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1883 struct drm_device *dev = crtc->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1887 if (WARN_ON(pll == NULL))
1890 WARN_ON(!pll->config.crtc_mask);
1891 if (pll->active == 0) {
1892 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1894 assert_shared_dpll_disabled(dev_priv, pll);
1896 pll->mode_set(dev_priv, pll);
1901 * intel_enable_shared_dpll - enable PCH PLL
1902 * @dev_priv: i915 private structure
1903 * @pipe: pipe PLL to enable
1905 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906 * drives the transcoder clock.
1908 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1914 if (WARN_ON(pll == NULL))
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1920 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1924 if (pll->active++) {
1926 assert_shared_dpll_enabled(dev_priv, pll);
1931 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1933 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1934 pll->enable(dev_priv, pll);
1938 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1940 struct drm_device *dev = crtc->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1944 /* PCH only available on ILK+ */
1945 BUG_ON(INTEL_INFO(dev)->gen < 5);
1946 if (WARN_ON(pll == NULL))
1949 if (WARN_ON(pll->config.crtc_mask == 0))
1952 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953 pll->name, pll->active, pll->on,
1954 crtc->base.base.id);
1956 if (WARN_ON(pll->active == 0)) {
1957 assert_shared_dpll_disabled(dev_priv, pll);
1961 assert_shared_dpll_enabled(dev_priv, pll);
1966 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1967 pll->disable(dev_priv, pll);
1970 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1973 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 struct drm_device *dev = dev_priv->dev;
1977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979 uint32_t reg, val, pipeconf_val;
1981 /* PCH only available on ILK+ */
1982 BUG_ON(!HAS_PCH_SPLIT(dev));
1984 /* Make sure PCH DPLL is enabled */
1985 assert_shared_dpll_enabled(dev_priv,
1986 intel_crtc_to_shared_dpll(intel_crtc));
1988 /* FDI must be feeding us bits for PCH ports */
1989 assert_fdi_tx_enabled(dev_priv, pipe);
1990 assert_fdi_rx_enabled(dev_priv, pipe);
1992 if (HAS_PCH_CPT(dev)) {
1993 /* Workaround: Set the timing override bit before enabling the
1994 * pch transcoder. */
1995 reg = TRANS_CHICKEN2(pipe);
1996 val = I915_READ(reg);
1997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(reg, val);
2001 reg = PCH_TRANSCONF(pipe);
2002 val = I915_READ(reg);
2003 pipeconf_val = I915_READ(PIPECONF(pipe));
2005 if (HAS_PCH_IBX(dev_priv->dev)) {
2007 * make the BPC in transcoder be consistent with
2008 * that in pipeconf reg.
2010 val &= ~PIPECONF_BPC_MASK;
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016 if (HAS_PCH_IBX(dev_priv->dev) &&
2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2020 val |= TRANS_INTERLACED;
2022 val |= TRANS_PROGRESSIVE;
2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030 enum transcoder cpu_transcoder)
2032 u32 val, pipeconf_val;
2034 /* PCH only available on ILK+ */
2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2037 /* FDI must be feeding us bits for PCH ports */
2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
2051 val |= TRANS_INTERLACED;
2053 val |= TRANS_PROGRESSIVE;
2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057 DRM_ERROR("Failed to enable PCH transcoder\n");
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2063 struct drm_device *dev = dev_priv->dev;
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2073 reg = PCH_TRANSCONF(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2094 val = I915_READ(LPT_TRANSCONF);
2095 val &= ~TRANS_ENABLE;
2096 I915_WRITE(LPT_TRANSCONF, val);
2097 /* wait for PCH transcoder off, transcoder state */
2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099 DRM_ERROR("Failed to disable PCH transcoder\n");
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104 I915_WRITE(_TRANSA_CHICKEN2, val);
2108 * intel_enable_pipe - enable a pipe, asserting requirements
2109 * @crtc: crtc responsible for the pipe
2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2121 enum pipe pch_transcoder;
2125 assert_planes_disabled(dev_priv, pipe);
2126 assert_cursor_disabled(dev_priv, pipe);
2127 assert_sprites_disabled(dev_priv, pipe);
2129 if (HAS_PCH_LPT(dev_priv->dev))
2130 pch_transcoder = TRANSCODER_A;
2132 pch_transcoder = pipe;
2135 * A pipe without a PLL won't actually be able to drive bits from
2136 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141 assert_dsi_pll_enabled(dev_priv);
2143 assert_pll_enabled(dev_priv, pipe);
2145 if (crtc->config->has_pch_encoder) {
2146 /* if driving the PCH, we need FDI enabled */
2147 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148 assert_fdi_tx_pll_enabled(dev_priv,
2149 (enum pipe) cpu_transcoder);
2151 /* FIXME: assert CPU port conditions for SNB+ */
2154 reg = PIPECONF(cpu_transcoder);
2155 val = I915_READ(reg);
2156 if (val & PIPECONF_ENABLE) {
2157 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2162 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 * intel_disable_pipe - disable a pipe, asserting requirements
2168 * @crtc: crtc whose pipes is to be disabled
2170 * Disable the pipe of @crtc, making sure that various hardware
2171 * specific requirements are met, if applicable, e.g. plane
2172 * disabled, panel fitter off, etc.
2174 * Will wait until the pipe has shut down before returning.
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2178 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180 enum pipe pipe = crtc->pipe;
2185 * Make sure planes won't keep trying to pump pixels to us,
2186 * or we might hang the display.
2188 assert_planes_disabled(dev_priv, pipe);
2189 assert_cursor_disabled(dev_priv, pipe);
2190 assert_sprites_disabled(dev_priv, pipe);
2192 reg = PIPECONF(cpu_transcoder);
2193 val = I915_READ(reg);
2194 if ((val & PIPECONF_ENABLE) == 0)
2198 * Double wide has implications for planes
2199 * so best keep it disabled when not needed.
2201 if (crtc->config->double_wide)
2202 val &= ~PIPECONF_DOUBLE_WIDE;
2204 /* Don't disable pipe or pipe PLLs if needed */
2205 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2206 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2207 val &= ~PIPECONF_ENABLE;
2209 I915_WRITE(reg, val);
2210 if ((val & PIPECONF_ENABLE) == 0)
2211 intel_wait_for_pipe_off(crtc);
2215 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2216 * @plane: plane to be enabled
2217 * @crtc: crtc for the plane
2219 * Enable @plane on @crtc, making sure that the pipe is running first.
2221 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2222 struct drm_crtc *crtc)
2224 struct drm_device *dev = plane->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2229 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2230 to_intel_plane_state(plane->state)->visible = true;
2232 dev_priv->display.update_primary_plane(crtc, plane->fb,
2236 static bool need_vtd_wa(struct drm_device *dev)
2238 #ifdef CONFIG_INTEL_IOMMU
2239 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2246 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2247 uint64_t fb_format_modifier)
2249 unsigned int tile_height;
2250 uint32_t pixel_bytes;
2252 switch (fb_format_modifier) {
2253 case DRM_FORMAT_MOD_NONE:
2256 case I915_FORMAT_MOD_X_TILED:
2257 tile_height = IS_GEN2(dev) ? 16 : 8;
2259 case I915_FORMAT_MOD_Y_TILED:
2262 case I915_FORMAT_MOD_Yf_TILED:
2263 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2264 switch (pixel_bytes) {
2278 "128-bit pixels are not supported for display!");
2284 MISSING_CASE(fb_format_modifier);
2293 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2294 uint32_t pixel_format, uint64_t fb_format_modifier)
2296 return ALIGN(height, intel_tile_height(dev, pixel_format,
2297 fb_format_modifier));
2301 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2302 const struct drm_plane_state *plane_state)
2304 struct intel_rotation_info *info = &view->rotation_info;
2306 *view = i915_ggtt_view_normal;
2311 if (!intel_rotation_90_or_270(plane_state->rotation))
2314 *view = i915_ggtt_view_rotated;
2316 info->height = fb->height;
2317 info->pixel_format = fb->pixel_format;
2318 info->pitch = fb->pitches[0];
2319 info->fb_modifier = fb->modifier[0];
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326 struct drm_framebuffer *fb,
2327 const struct drm_plane_state *plane_state,
2328 struct intel_engine_cs *pipelined)
2330 struct drm_device *dev = fb->dev;
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333 struct i915_ggtt_view view;
2337 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2339 switch (fb->modifier[0]) {
2340 case DRM_FORMAT_MOD_NONE:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344 alignment = 128 * 1024;
2345 else if (INTEL_INFO(dev)->gen >= 4)
2346 alignment = 4 * 1024;
2348 alignment = 64 * 1024;
2350 case I915_FORMAT_MOD_X_TILED:
2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2354 /* pin() will align the object as required by fence */
2358 case I915_FORMAT_MOD_Y_TILED:
2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2363 alignment = 1 * 1024 * 1024;
2366 MISSING_CASE(fb->modifier[0]);
2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2389 intel_runtime_pm_get(dev_priv);
2391 dev_priv->mm.interruptible = false;
2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2395 goto err_interruptible;
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2402 ret = i915_gem_object_get_fence(obj);
2406 i915_gem_object_pin_fence(obj);
2408 dev_priv->mm.interruptible = true;
2409 intel_runtime_pm_put(dev_priv);
2413 i915_gem_object_unpin_from_display_plane(obj, &view);
2415 dev_priv->mm.interruptible = true;
2416 intel_runtime_pm_put(dev_priv);
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421 const struct drm_plane_state *plane_state)
2423 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424 struct i915_ggtt_view view;
2427 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432 i915_gem_object_unpin_fence(obj);
2433 i915_gem_object_unpin_from_display_plane(obj, &view);
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437 * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439 unsigned int tiling_mode,
2443 if (tiling_mode != I915_TILING_NONE) {
2444 unsigned int tile_rows, tiles;
2449 tiles = *x / (512/cpp);
2452 return tile_rows * pitch * 8 + tiles * 4096;
2454 unsigned int offset;
2456 offset = *y * pitch + *x * cpp;
2458 *x = (offset & 4095) / cpp;
2459 return offset & -4096;
2463 static int i9xx_format_to_fourcc(int format)
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2493 return DRM_FORMAT_ABGR8888;
2495 return DRM_FORMAT_XBGR8888;
2498 return DRM_FORMAT_ARGB8888;
2500 return DRM_FORMAT_XRGB8888;
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2504 return DRM_FORMAT_XBGR2101010;
2506 return DRM_FORMAT_XRGB2101010;
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_gem_object *obj = NULL;
2516 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517 struct drm_framebuffer *fb = &plane_config->fb->base;
2518 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2522 size_aligned -= base_aligned;
2524 if (plane_config->size == 0)
2527 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2534 obj->tiling_mode = plane_config->tiling;
2535 if (obj->tiling_mode == I915_TILING_X)
2536 obj->stride = fb->pitches[0];
2538 mode_cmd.pixel_format = fb->pixel_format;
2539 mode_cmd.width = fb->width;
2540 mode_cmd.height = fb->height;
2541 mode_cmd.pitches[0] = fb->pitches[0];
2542 mode_cmd.modifier[0] = fb->modifier[0];
2543 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2545 mutex_lock(&dev->struct_mutex);
2546 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2548 DRM_DEBUG_KMS("intel fb init failed\n");
2551 mutex_unlock(&dev->struct_mutex);
2553 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2557 drm_gem_object_unreference(&obj->base);
2558 mutex_unlock(&dev->struct_mutex);
2562 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2564 update_state_fb(struct drm_plane *plane)
2566 if (plane->fb == plane->state->fb)
2569 if (plane->state->fb)
2570 drm_framebuffer_unreference(plane->state->fb);
2571 plane->state->fb = plane->fb;
2572 if (plane->state->fb)
2573 drm_framebuffer_reference(plane->state->fb);
2577 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2578 struct intel_initial_plane_config *plane_config)
2580 struct drm_device *dev = intel_crtc->base.dev;
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct intel_crtc *i;
2584 struct drm_i915_gem_object *obj;
2585 struct drm_plane *primary = intel_crtc->base.primary;
2586 struct drm_framebuffer *fb;
2588 if (!plane_config->fb)
2591 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2592 fb = &plane_config->fb->base;
2596 kfree(plane_config->fb);
2599 * Failed to alloc the obj, check to see if we should share
2600 * an fb with another CRTC instead
2602 for_each_crtc(dev, c) {
2603 i = to_intel_crtc(c);
2605 if (c == &intel_crtc->base)
2611 fb = c->primary->fb;
2615 obj = intel_fb_obj(fb);
2616 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2617 drm_framebuffer_reference(fb);
2625 obj = intel_fb_obj(fb);
2626 if (obj->tiling_mode != I915_TILING_NONE)
2627 dev_priv->preserve_bios_swizzle = true;
2630 primary->state->crtc = &intel_crtc->base;
2631 primary->crtc = &intel_crtc->base;
2632 update_state_fb(primary);
2633 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2636 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2637 struct drm_framebuffer *fb,
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 struct drm_plane *primary = crtc->primary;
2644 bool visible = to_intel_plane_state(primary->state)->visible;
2645 struct drm_i915_gem_object *obj;
2646 int plane = intel_crtc->plane;
2647 unsigned long linear_offset;
2649 u32 reg = DSPCNTR(plane);
2652 if (!visible || !fb) {
2654 if (INTEL_INFO(dev)->gen >= 4)
2655 I915_WRITE(DSPSURF(plane), 0);
2657 I915_WRITE(DSPADDR(plane), 0);
2662 obj = intel_fb_obj(fb);
2663 if (WARN_ON(obj == NULL))
2666 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2668 dspcntr = DISPPLANE_GAMMA_ENABLE;
2670 dspcntr |= DISPLAY_PLANE_ENABLE;
2672 if (INTEL_INFO(dev)->gen < 4) {
2673 if (intel_crtc->pipe == PIPE_B)
2674 dspcntr |= DISPPLANE_SEL_PIPE_B;
2676 /* pipesrc and dspsize control the size that is scaled from,
2677 * which should always be the user's requested size.
2679 I915_WRITE(DSPSIZE(plane),
2680 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681 (intel_crtc->config->pipe_src_w - 1));
2682 I915_WRITE(DSPPOS(plane), 0);
2683 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2684 I915_WRITE(PRIMSIZE(plane),
2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
2687 I915_WRITE(PRIMPOS(plane), 0);
2688 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2691 switch (fb->pixel_format) {
2693 dspcntr |= DISPPLANE_8BPP;
2695 case DRM_FORMAT_XRGB1555:
2696 dspcntr |= DISPPLANE_BGRX555;
2698 case DRM_FORMAT_RGB565:
2699 dspcntr |= DISPPLANE_BGRX565;
2701 case DRM_FORMAT_XRGB8888:
2702 dspcntr |= DISPPLANE_BGRX888;
2704 case DRM_FORMAT_XBGR8888:
2705 dspcntr |= DISPPLANE_RGBX888;
2707 case DRM_FORMAT_XRGB2101010:
2708 dspcntr |= DISPPLANE_BGRX101010;
2710 case DRM_FORMAT_XBGR2101010:
2711 dspcntr |= DISPPLANE_RGBX101010;
2717 if (INTEL_INFO(dev)->gen >= 4 &&
2718 obj->tiling_mode != I915_TILING_NONE)
2719 dspcntr |= DISPPLANE_TILED;
2722 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2724 linear_offset = y * fb->pitches[0] + x * pixel_size;
2726 if (INTEL_INFO(dev)->gen >= 4) {
2727 intel_crtc->dspaddr_offset =
2728 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2731 linear_offset -= intel_crtc->dspaddr_offset;
2733 intel_crtc->dspaddr_offset = linear_offset;
2736 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2737 dspcntr |= DISPPLANE_ROTATE_180;
2739 x += (intel_crtc->config->pipe_src_w - 1);
2740 y += (intel_crtc->config->pipe_src_h - 1);
2742 /* Finding the last pixel of the last line of the display
2743 data and adding to linear_offset*/
2745 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2746 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2749 I915_WRITE(reg, dspcntr);
2751 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2752 if (INTEL_INFO(dev)->gen >= 4) {
2753 I915_WRITE(DSPSURF(plane),
2754 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2755 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2756 I915_WRITE(DSPLINOFF(plane), linear_offset);
2758 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2762 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2763 struct drm_framebuffer *fb,
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 struct drm_plane *primary = crtc->primary;
2770 bool visible = to_intel_plane_state(primary->state)->visible;
2771 struct drm_i915_gem_object *obj;
2772 int plane = intel_crtc->plane;
2773 unsigned long linear_offset;
2775 u32 reg = DSPCNTR(plane);
2778 if (!visible || !fb) {
2780 I915_WRITE(DSPSURF(plane), 0);
2785 obj = intel_fb_obj(fb);
2786 if (WARN_ON(obj == NULL))
2789 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2791 dspcntr = DISPPLANE_GAMMA_ENABLE;
2793 dspcntr |= DISPLAY_PLANE_ENABLE;
2795 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2796 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2798 switch (fb->pixel_format) {
2800 dspcntr |= DISPPLANE_8BPP;
2802 case DRM_FORMAT_RGB565:
2803 dspcntr |= DISPPLANE_BGRX565;
2805 case DRM_FORMAT_XRGB8888:
2806 dspcntr |= DISPPLANE_BGRX888;
2808 case DRM_FORMAT_XBGR8888:
2809 dspcntr |= DISPPLANE_RGBX888;
2811 case DRM_FORMAT_XRGB2101010:
2812 dspcntr |= DISPPLANE_BGRX101010;
2814 case DRM_FORMAT_XBGR2101010:
2815 dspcntr |= DISPPLANE_RGBX101010;
2821 if (obj->tiling_mode != I915_TILING_NONE)
2822 dspcntr |= DISPPLANE_TILED;
2824 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2825 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2827 linear_offset = y * fb->pitches[0] + x * pixel_size;
2828 intel_crtc->dspaddr_offset =
2829 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2832 linear_offset -= intel_crtc->dspaddr_offset;
2833 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834 dspcntr |= DISPPLANE_ROTATE_180;
2836 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837 x += (intel_crtc->config->pipe_src_w - 1);
2838 y += (intel_crtc->config->pipe_src_h - 1);
2840 /* Finding the last pixel of the last line of the display
2841 data and adding to linear_offset*/
2843 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2848 I915_WRITE(reg, dspcntr);
2850 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2851 I915_WRITE(DSPSURF(plane),
2852 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2853 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2854 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2856 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2857 I915_WRITE(DSPLINOFF(plane), linear_offset);
2862 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2863 uint32_t pixel_format)
2865 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2868 * The stride is either expressed as a multiple of 64 bytes
2869 * chunks for linear buffers or in number of tiles for tiled
2872 switch (fb_modifier) {
2873 case DRM_FORMAT_MOD_NONE:
2875 case I915_FORMAT_MOD_X_TILED:
2876 if (INTEL_INFO(dev)->gen == 2)
2879 case I915_FORMAT_MOD_Y_TILED:
2880 /* No need to check for old gens and Y tiling since this is
2881 * about the display engine and those will be blocked before
2885 case I915_FORMAT_MOD_Yf_TILED:
2886 if (bits_per_pixel == 8)
2891 MISSING_CASE(fb_modifier);
2896 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2897 struct drm_i915_gem_object *obj)
2899 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2901 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2902 view = &i915_ggtt_view_rotated;
2904 return i915_gem_obj_ggtt_offset_view(obj, view);
2908 * This function detaches (aka. unbinds) unused scalers in hardware
2910 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2912 struct drm_device *dev;
2913 struct drm_i915_private *dev_priv;
2914 struct intel_crtc_scaler_state *scaler_state;
2917 if (!intel_crtc || !intel_crtc->config)
2920 dev = intel_crtc->base.dev;
2921 dev_priv = dev->dev_private;
2922 scaler_state = &intel_crtc->config->scaler_state;
2924 /* loop through and disable scalers that aren't in use */
2925 for (i = 0; i < intel_crtc->num_scalers; i++) {
2926 if (!scaler_state->scalers[i].in_use) {
2927 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2929 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2930 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2931 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936 u32 skl_plane_ctl_format(uint32_t pixel_format)
2938 switch (pixel_format) {
2940 return PLANE_CTL_FORMAT_INDEXED;
2941 case DRM_FORMAT_RGB565:
2942 return PLANE_CTL_FORMAT_RGB_565;
2943 case DRM_FORMAT_XBGR8888:
2944 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2945 case DRM_FORMAT_XRGB8888:
2946 return PLANE_CTL_FORMAT_XRGB_8888;
2948 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2949 * to be already pre-multiplied. We need to add a knob (or a different
2950 * DRM_FORMAT) for user-space to configure that.
2952 case DRM_FORMAT_ABGR8888:
2953 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2954 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955 case DRM_FORMAT_ARGB8888:
2956 return PLANE_CTL_FORMAT_XRGB_8888 |
2957 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2958 case DRM_FORMAT_XRGB2101010:
2959 return PLANE_CTL_FORMAT_XRGB_2101010;
2960 case DRM_FORMAT_XBGR2101010:
2961 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2962 case DRM_FORMAT_YUYV:
2963 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2964 case DRM_FORMAT_YVYU:
2965 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2966 case DRM_FORMAT_UYVY:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2968 case DRM_FORMAT_VYUY:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2971 MISSING_CASE(pixel_format);
2977 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2979 switch (fb_modifier) {
2980 case DRM_FORMAT_MOD_NONE:
2982 case I915_FORMAT_MOD_X_TILED:
2983 return PLANE_CTL_TILED_X;
2984 case I915_FORMAT_MOD_Y_TILED:
2985 return PLANE_CTL_TILED_Y;
2986 case I915_FORMAT_MOD_Yf_TILED:
2987 return PLANE_CTL_TILED_YF;
2989 MISSING_CASE(fb_modifier);
2995 u32 skl_plane_ctl_rotation(unsigned int rotation)
2998 case BIT(DRM_ROTATE_0):
3001 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3002 * while i915 HW rotation is clockwise, thats why this swapping.
3004 case BIT(DRM_ROTATE_90):
3005 return PLANE_CTL_ROTATE_270;
3006 case BIT(DRM_ROTATE_180):
3007 return PLANE_CTL_ROTATE_180;
3008 case BIT(DRM_ROTATE_270):
3009 return PLANE_CTL_ROTATE_90;
3011 MISSING_CASE(rotation);
3017 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3018 struct drm_framebuffer *fb,
3021 struct drm_device *dev = crtc->dev;
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3024 struct drm_plane *plane = crtc->primary;
3025 bool visible = to_intel_plane_state(plane->state)->visible;
3026 struct drm_i915_gem_object *obj;
3027 int pipe = intel_crtc->pipe;
3028 u32 plane_ctl, stride_div, stride;
3029 u32 tile_height, plane_offset, plane_size;
3030 unsigned int rotation;
3031 int x_offset, y_offset;
3032 unsigned long surf_addr;
3033 struct intel_crtc_state *crtc_state = intel_crtc->config;
3034 struct intel_plane_state *plane_state;
3035 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3036 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3039 plane_state = to_intel_plane_state(plane->state);
3041 if (!visible || !fb) {
3042 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3043 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3044 POSTING_READ(PLANE_CTL(pipe, 0));
3048 plane_ctl = PLANE_CTL_ENABLE |
3049 PLANE_CTL_PIPE_GAMMA_ENABLE |
3050 PLANE_CTL_PIPE_CSC_ENABLE;
3052 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3053 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3054 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3056 rotation = plane->state->rotation;
3057 plane_ctl |= skl_plane_ctl_rotation(rotation);
3059 obj = intel_fb_obj(fb);
3060 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3062 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3065 * FIXME: intel_plane_state->src, dst aren't set when transitional
3066 * update_plane helpers are called from legacy paths.
3067 * Once full atomic crtc is available, below check can be avoided.
3069 if (drm_rect_width(&plane_state->src)) {
3070 scaler_id = plane_state->scaler_id;
3071 src_x = plane_state->src.x1 >> 16;
3072 src_y = plane_state->src.y1 >> 16;
3073 src_w = drm_rect_width(&plane_state->src) >> 16;
3074 src_h = drm_rect_height(&plane_state->src) >> 16;
3075 dst_x = plane_state->dst.x1;
3076 dst_y = plane_state->dst.y1;
3077 dst_w = drm_rect_width(&plane_state->dst);
3078 dst_h = drm_rect_height(&plane_state->dst);
3080 WARN_ON(x != src_x || y != src_y);
3082 src_w = intel_crtc->config->pipe_src_w;
3083 src_h = intel_crtc->config->pipe_src_h;
3086 if (intel_rotation_90_or_270(rotation)) {
3087 /* stride = Surface height in tiles */
3088 tile_height = intel_tile_height(dev, fb->pixel_format,
3090 stride = DIV_ROUND_UP(fb->height, tile_height);
3091 x_offset = stride * tile_height - y - src_h;
3093 plane_size = (src_w - 1) << 16 | (src_h - 1);
3095 stride = fb->pitches[0] / stride_div;
3098 plane_size = (src_h - 1) << 16 | (src_w - 1);
3100 plane_offset = y_offset << 16 | x_offset;
3102 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3103 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3104 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3105 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3107 if (scaler_id >= 0) {
3108 uint32_t ps_ctrl = 0;
3110 WARN_ON(!dst_w || !dst_h);
3111 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3112 crtc_state->scaler_state.scalers[scaler_id].mode;
3113 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3114 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3115 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3116 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3117 I915_WRITE(PLANE_POS(pipe, 0), 0);
3119 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3122 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3124 POSTING_READ(PLANE_SURF(pipe, 0));
3127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3129 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3130 int x, int y, enum mode_set_atomic state)
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3135 if (dev_priv->display.disable_fbc)
3136 dev_priv->display.disable_fbc(dev);
3138 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143 static void intel_complete_page_flips(struct drm_device *dev)
3145 struct drm_crtc *crtc;
3147 for_each_crtc(dev, crtc) {
3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149 enum plane plane = intel_crtc->plane;
3151 intel_prepare_page_flip(dev, plane);
3152 intel_finish_page_flip_plane(dev, plane);
3156 static void intel_update_primary_planes(struct drm_device *dev)
3158 struct drm_i915_private *dev_priv = dev->dev_private;
3159 struct drm_crtc *crtc;
3161 for_each_crtc(dev, crtc) {
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164 drm_modeset_lock(&crtc->mutex, NULL);
3166 * FIXME: Once we have proper support for primary planes (and
3167 * disabling them without disabling the entire crtc) allow again
3168 * a NULL crtc->primary->fb.
3170 if (intel_crtc->active && crtc->primary->fb)
3171 dev_priv->display.update_primary_plane(crtc,
3175 drm_modeset_unlock(&crtc->mutex);
3179 void intel_crtc_reset(struct intel_crtc *crtc)
3181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3186 intel_crtc_disable_planes(&crtc->base);
3187 dev_priv->display.crtc_disable(&crtc->base);
3188 dev_priv->display.crtc_enable(&crtc->base);
3189 intel_crtc_enable_planes(&crtc->base);
3192 void intel_prepare_reset(struct drm_device *dev)
3194 struct drm_i915_private *dev_priv = to_i915(dev);
3195 struct intel_crtc *crtc;
3197 /* no reset support for gen2 */
3201 /* reset doesn't touch the display */
3202 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3205 drm_modeset_lock_all(dev);
3208 * Disabling the crtcs gracefully seems nicer. Also the
3209 * g33 docs say we should at least disable all the planes.
3211 for_each_intel_crtc(dev, crtc) {
3215 intel_crtc_disable_planes(&crtc->base);
3216 dev_priv->display.crtc_disable(&crtc->base);
3220 void intel_finish_reset(struct drm_device *dev)
3222 struct drm_i915_private *dev_priv = to_i915(dev);
3225 * Flips in the rings will be nuked by the reset,
3226 * so complete all pending flips so that user space
3227 * will get its events and not get stuck.
3229 intel_complete_page_flips(dev);
3231 /* no reset support for gen2 */
3235 /* reset doesn't touch the display */
3236 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3238 * Flips in the rings have been nuked by the reset,
3239 * so update the base address of all primary
3240 * planes to the the last fb to make sure we're
3241 * showing the correct fb after a reset.
3243 intel_update_primary_planes(dev);
3248 * The display has been reset as well,
3249 * so need a full re-initialization.
3251 intel_runtime_pm_disable_interrupts(dev_priv);
3252 intel_runtime_pm_enable_interrupts(dev_priv);
3254 intel_modeset_init_hw(dev);
3256 spin_lock_irq(&dev_priv->irq_lock);
3257 if (dev_priv->display.hpd_irq_setup)
3258 dev_priv->display.hpd_irq_setup(dev);
3259 spin_unlock_irq(&dev_priv->irq_lock);
3261 intel_modeset_setup_hw_state(dev, true);
3263 intel_hpd_init(dev_priv);
3265 drm_modeset_unlock_all(dev);
3269 intel_finish_fb(struct drm_framebuffer *old_fb)
3271 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3272 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3273 bool was_interruptible = dev_priv->mm.interruptible;
3276 /* Big Hammer, we also need to ensure that any pending
3277 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3278 * current scanout is retired before unpinning the old
3279 * framebuffer. Note that we rely on userspace rendering
3280 * into the buffer attached to the pipe they are waiting
3281 * on. If not, userspace generates a GPU hang with IPEHR
3282 * point to the MI_WAIT_FOR_EVENT.
3284 * This should only fail upon a hung GPU, in which case we
3285 * can safely continue.
3287 dev_priv->mm.interruptible = false;
3288 ret = i915_gem_object_wait_rendering(obj, true);
3289 dev_priv->mm.interruptible = was_interruptible;
3294 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3296 struct drm_device *dev = crtc->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3301 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3302 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3305 spin_lock_irq(&dev->event_lock);
3306 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3307 spin_unlock_irq(&dev->event_lock);
3312 static void intel_update_pipe_size(struct intel_crtc *crtc)
3314 struct drm_device *dev = crtc->base.dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 const struct drm_display_mode *adjusted_mode;
3322 * Update pipe size and adjust fitter if needed: the reason for this is
3323 * that in compute_mode_changes we check the native mode (not the pfit
3324 * mode) to see if we can flip rather than do a full mode set. In the
3325 * fastboot case, we'll flip, but if we don't update the pipesrc and
3326 * pfit state, we'll end up with a big fb scanned out into the wrong
3329 * To fix this properly, we need to hoist the checks up into
3330 * compute_mode_changes (or above), check the actual pfit state and
3331 * whether the platform allows pfit disable with pipe active, and only
3332 * then update the pipesrc and pfit state, even on the flip path.
3335 adjusted_mode = &crtc->config->base.adjusted_mode;
3337 I915_WRITE(PIPESRC(crtc->pipe),
3338 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3339 (adjusted_mode->crtc_vdisplay - 1));
3340 if (!crtc->config->pch_pfit.enabled &&
3341 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3342 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3343 I915_WRITE(PF_CTL(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3345 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3347 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3348 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int pipe = intel_crtc->pipe;
3359 /* enable normal train */
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 if (IS_IVYBRIDGE(dev)) {
3363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366 temp &= ~FDI_LINK_TRAIN_NONE;
3367 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369 I915_WRITE(reg, temp);
3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_NONE;
3380 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382 /* wait one idle pattern time */
3386 /* IVB wants error correction enabled */
3387 if (IS_IVYBRIDGE(dev))
3388 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389 FDI_FE_ERRC_ENABLE);
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 struct drm_device *dev = crtc->dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 int pipe = intel_crtc->pipe;
3399 u32 reg, temp, tries;
3401 /* FDI needs bits from pipe first */
3402 assert_pipe_enabled(dev_priv, pipe);
3404 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406 reg = FDI_RX_IMR(pipe);
3407 temp = I915_READ(reg);
3408 temp &= ~FDI_RX_SYMBOL_LOCK;
3409 temp &= ~FDI_RX_BIT_LOCK;
3410 I915_WRITE(reg, temp);
3414 /* enable CPU FDI TX and PCH FDI RX */
3415 reg = FDI_TX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3418 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
3421 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423 reg = FDI_RX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_PATTERN_1;
3427 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3432 /* Ironlake workaround, enable clock pointer after FDI enable*/
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3435 FDI_RX_PHASE_SYNC_POINTER_EN);
3437 reg = FDI_RX_IIR(pipe);
3438 for (tries = 0; tries < 5; tries++) {
3439 temp = I915_READ(reg);
3440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442 if ((temp & FDI_RX_BIT_LOCK)) {
3443 DRM_DEBUG_KMS("FDI train 1 done.\n");
3444 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3449 DRM_ERROR("FDI train 1 fail!\n");
3452 reg = FDI_TX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_NONE;
3455 temp |= FDI_LINK_TRAIN_PATTERN_2;
3456 I915_WRITE(reg, temp);
3458 reg = FDI_RX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~FDI_LINK_TRAIN_NONE;
3461 temp |= FDI_LINK_TRAIN_PATTERN_2;
3462 I915_WRITE(reg, temp);
3467 reg = FDI_RX_IIR(pipe);
3468 for (tries = 0; tries < 5; tries++) {
3469 temp = I915_READ(reg);
3470 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472 if (temp & FDI_RX_SYMBOL_LOCK) {
3473 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3474 DRM_DEBUG_KMS("FDI train 2 done.\n");
3479 DRM_ERROR("FDI train 2 fail!\n");
3481 DRM_DEBUG_KMS("FDI train done\n");
3485 static const int snb_b_fdi_train_param[] = {
3486 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3487 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3488 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3489 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3492 /* The FDI link training functions for SNB/Cougarpoint. */
3493 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
3499 u32 reg, temp, i, retry;
3501 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503 reg = FDI_RX_IMR(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_RX_SYMBOL_LOCK;
3506 temp &= ~FDI_RX_BIT_LOCK;
3507 I915_WRITE(reg, temp);
3512 /* enable CPU FDI TX and PCH FDI RX */
3513 reg = FDI_TX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1;
3519 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3524 I915_WRITE(FDI_RX_MISC(pipe),
3525 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527 reg = FDI_RX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 if (HAS_PCH_CPT(dev)) {
3530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533 temp &= ~FDI_LINK_TRAIN_NONE;
3534 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3541 for (i = 0; i < 4; i++) {
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 temp |= snb_b_fdi_train_param[i];
3546 I915_WRITE(reg, temp);
3551 for (retry = 0; retry < 5; retry++) {
3552 reg = FDI_RX_IIR(pipe);
3553 temp = I915_READ(reg);
3554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555 if (temp & FDI_RX_BIT_LOCK) {
3556 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557 DRM_DEBUG_KMS("FDI train 1 done.\n");
3566 DRM_ERROR("FDI train 1 fail!\n");
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578 I915_WRITE(reg, temp);
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 if (HAS_PCH_CPT(dev)) {
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586 temp &= ~FDI_LINK_TRAIN_NONE;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589 I915_WRITE(reg, temp);
3594 for (i = 0; i < 4; i++) {
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598 temp |= snb_b_fdi_train_param[i];
3599 I915_WRITE(reg, temp);
3604 for (retry = 0; retry < 5; retry++) {
3605 reg = FDI_RX_IIR(pipe);
3606 temp = I915_READ(reg);
3607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608 if (temp & FDI_RX_SYMBOL_LOCK) {
3609 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610 DRM_DEBUG_KMS("FDI train 2 done.\n");
3619 DRM_ERROR("FDI train 2 fail!\n");
3621 DRM_DEBUG_KMS("FDI train done.\n");
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627 struct drm_device *dev = crtc->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 int pipe = intel_crtc->pipe;
3631 u32 reg, temp, i, j;
3633 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635 reg = FDI_RX_IMR(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_RX_SYMBOL_LOCK;
3638 temp &= ~FDI_RX_BIT_LOCK;
3639 I915_WRITE(reg, temp);
3644 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645 I915_READ(FDI_RX_IIR(pipe)));
3647 /* Try each vswing and preemphasis setting twice before moving on */
3648 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649 /* disable first in case we need to retry */
3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653 temp &= ~FDI_TX_ENABLE;
3654 I915_WRITE(reg, temp);
3656 reg = FDI_RX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp &= ~FDI_LINK_TRAIN_AUTO;
3659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660 temp &= ~FDI_RX_ENABLE;
3661 I915_WRITE(reg, temp);
3663 /* enable CPU FDI TX and PCH FDI RX */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670 temp |= snb_b_fdi_train_param[j/2];
3671 temp |= FDI_COMPOSITE_SYNC;
3672 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674 I915_WRITE(FDI_RX_MISC(pipe),
3675 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680 temp |= FDI_COMPOSITE_SYNC;
3681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3684 udelay(1); /* should be 0.5us */
3686 for (i = 0; i < 4; i++) {
3687 reg = FDI_RX_IIR(pipe);
3688 temp = I915_READ(reg);
3689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691 if (temp & FDI_RX_BIT_LOCK ||
3692 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3698 udelay(1); /* should be 0.5us */
3701 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3706 reg = FDI_TX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710 I915_WRITE(reg, temp);
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716 I915_WRITE(reg, temp);
3719 udelay(2); /* should be 1.5us */
3721 for (i = 0; i < 4; i++) {
3722 reg = FDI_RX_IIR(pipe);
3723 temp = I915_READ(reg);
3724 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726 if (temp & FDI_RX_SYMBOL_LOCK ||
3727 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3733 udelay(2); /* should be 1.5us */
3736 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3740 DRM_DEBUG_KMS("FDI train done.\n");
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 struct drm_device *dev = intel_crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 int pipe = intel_crtc->pipe;
3751 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752 reg = FDI_RX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3762 /* Switch from Rawclk to PCDclk */
3763 temp = I915_READ(reg);
3764 I915_WRITE(reg, temp | FDI_PCDCLK);
3769 /* Enable CPU FDI TX PLL, always on for Ironlake */
3770 reg = FDI_TX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 struct drm_device *dev = intel_crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 int pipe = intel_crtc->pipe;
3787 /* Switch from PCDclk to Rawclk */
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792 /* Disable CPU FDI TX PLL */
3793 reg = FDI_TX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804 /* Wait for the clocks to turn off. */
3809 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814 int pipe = intel_crtc->pipe;
3817 /* disable CPU FDI tx and PCH FDI rx */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3823 reg = FDI_RX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 temp &= ~(0x7 << 16);
3826 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3827 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3832 /* Ironlake workaround, disable clock pointer after downing FDI */
3833 if (HAS_PCH_IBX(dev))
3834 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836 /* still set train pattern 1 */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 temp &= ~FDI_LINK_TRAIN_NONE;
3840 temp |= FDI_LINK_TRAIN_PATTERN_1;
3841 I915_WRITE(reg, temp);
3843 reg = FDI_RX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 if (HAS_PCH_CPT(dev)) {
3846 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3847 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849 temp &= ~FDI_LINK_TRAIN_NONE;
3850 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852 /* BPC in FDI rx is consistent with that in PIPECONF */
3853 temp &= ~(0x07 << 16);
3854 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3855 I915_WRITE(reg, temp);
3861 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 struct intel_crtc *crtc;
3865 /* Note that we don't need to be called with mode_config.lock here
3866 * as our list of CRTC objects is static for the lifetime of the
3867 * device and so cannot disappear as we iterate. Similarly, we can
3868 * happily treat the predicates as racy, atomic checks as userspace
3869 * cannot claim and pin a new fb without at least acquring the
3870 * struct_mutex and so serialising with us.
3872 for_each_intel_crtc(dev, crtc) {
3873 if (atomic_read(&crtc->unpin_work_count) == 0)
3876 if (crtc->unpin_work)
3877 intel_wait_for_vblank(dev, crtc->pipe);
3885 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3888 struct intel_unpin_work *work = intel_crtc->unpin_work;
3890 /* ensure that the unpin work is consistent wrt ->pending. */
3892 intel_crtc->unpin_work = NULL;
3895 drm_send_vblank_event(intel_crtc->base.dev,
3899 drm_crtc_vblank_put(&intel_crtc->base);
3901 wake_up_all(&dev_priv->pending_flip_queue);
3902 queue_work(dev_priv->wq, &work->work);
3904 trace_i915_flip_complete(intel_crtc->plane,
3905 work->pending_flip_obj);
3908 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 struct drm_device *dev = crtc->dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3913 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3914 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3915 !intel_crtc_has_pending_flip(crtc),
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919 spin_lock_irq(&dev->event_lock);
3920 if (intel_crtc->unpin_work) {
3921 WARN_ONCE(1, "Removing stuck page flip\n");
3922 page_flip_completed(intel_crtc);
3924 spin_unlock_irq(&dev->event_lock);
3927 if (crtc->primary->fb) {
3928 mutex_lock(&dev->struct_mutex);
3929 intel_finish_fb(crtc->primary->fb);
3930 mutex_unlock(&dev->struct_mutex);
3934 /* Program iCLKIP clock to the desired frequency */
3935 static void lpt_program_iclkip(struct drm_crtc *crtc)
3937 struct drm_device *dev = crtc->dev;
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3940 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3943 mutex_lock(&dev_priv->sb_lock);
3945 /* It is necessary to ungate the pixclk gate prior to programming
3946 * the divisors, and gate it back when it is done.
3948 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950 /* Disable SSCCTL */
3951 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3952 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3956 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3957 if (clock == 20000) {
3962 /* The iCLK virtual clock root frequency is in MHz,
3963 * but the adjusted_mode->crtc_clock in in KHz. To get the
3964 * divisors, it is necessary to divide one by another, so we
3965 * convert the virtual clock precision to KHz here for higher
3968 u32 iclk_virtual_root_freq = 172800 * 1000;
3969 u32 iclk_pi_range = 64;
3970 u32 desired_divisor, msb_divisor_value, pi_value;
3972 desired_divisor = (iclk_virtual_root_freq / clock);
3973 msb_divisor_value = desired_divisor / iclk_pi_range;
3974 pi_value = desired_divisor % iclk_pi_range;
3977 divsel = msb_divisor_value - 2;
3978 phaseinc = pi_value;
3981 /* This should not happen with any sane values */
3982 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3983 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3984 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3985 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3994 /* Program SSCDIVINTPHASE6 */
3995 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3996 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3997 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3998 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3999 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4000 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4001 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4002 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4004 /* Program SSCAUXDIV */
4005 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4006 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4007 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4008 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4010 /* Enable modulator and associated divider */
4011 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4012 temp &= ~SBI_SSCCTL_DISABLE;
4013 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4015 /* Wait for initialization time */
4018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4020 mutex_unlock(&dev_priv->sb_lock);
4023 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4024 enum pipe pch_transcoder)
4026 struct drm_device *dev = crtc->base.dev;
4027 struct drm_i915_private *dev_priv = dev->dev_private;
4028 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4030 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4031 I915_READ(HTOTAL(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4033 I915_READ(HBLANK(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4035 I915_READ(HSYNC(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4038 I915_READ(VTOTAL(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4040 I915_READ(VBLANK(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4042 I915_READ(VSYNC(cpu_transcoder)));
4043 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4044 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4047 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4052 temp = I915_READ(SOUTH_CHICKEN1);
4053 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059 temp &= ~FDI_BC_BIFURCATION_SELECT;
4061 temp |= FDI_BC_BIFURCATION_SELECT;
4063 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4064 I915_WRITE(SOUTH_CHICKEN1, temp);
4065 POSTING_READ(SOUTH_CHICKEN1);
4068 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070 struct drm_device *dev = intel_crtc->base.dev;
4072 switch (intel_crtc->pipe) {
4076 if (intel_crtc->config->fdi_lanes > 2)
4077 cpt_set_fdi_bc_bifurcation(dev, false);
4079 cpt_set_fdi_bc_bifurcation(dev, true);
4083 cpt_set_fdi_bc_bifurcation(dev, true);
4092 * Enable PCH resources required for PCH ports:
4094 * - FDI training & RX/TX
4095 * - update transcoder timings
4096 * - DP transcoding bits
4099 static void ironlake_pch_enable(struct drm_crtc *crtc)
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 int pipe = intel_crtc->pipe;
4107 assert_pch_transcoder_disabled(dev_priv, pipe);
4109 if (IS_IVYBRIDGE(dev))
4110 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112 /* Write the TU size bits before fdi link training, so that error
4113 * detection works. */
4114 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4115 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117 /* For PCH output, training FDI link */
4118 dev_priv->display.fdi_link_train(crtc);
4120 /* We need to program the right clock selection before writing the pixel
4121 * mutliplier into the DPLL. */
4122 if (HAS_PCH_CPT(dev)) {
4125 temp = I915_READ(PCH_DPLL_SEL);
4126 temp |= TRANS_DPLL_ENABLE(pipe);
4127 sel = TRANS_DPLLB_SEL(pipe);
4128 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4132 I915_WRITE(PCH_DPLL_SEL, temp);
4135 /* XXX: pch pll's can be enabled any time before we enable the PCH
4136 * transcoder, and we actually should do this to not upset any PCH
4137 * transcoder that already use the clock when we share it.
4139 * Note that enable_shared_dpll tries to do the right thing, but
4140 * get_shared_dpll unconditionally resets the pll - we need that to have
4141 * the right LVDS enable sequence. */
4142 intel_enable_shared_dpll(intel_crtc);
4144 /* set transcoder timing, panel must allow it */
4145 assert_panel_unlocked(dev_priv, pipe);
4146 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4148 intel_fdi_normal_train(crtc);
4150 /* For PCH DP, enable TRANS_DP_CTL */
4151 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4152 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4153 reg = TRANS_DP_CTL(pipe);
4154 temp = I915_READ(reg);
4155 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4156 TRANS_DP_SYNC_MASK |
4158 temp |= TRANS_DP_OUTPUT_ENABLE;
4159 temp |= bpc << 9; /* same format but at 11:9 */
4161 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4162 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4163 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4164 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4166 switch (intel_trans_dp_port_sel(crtc)) {
4168 temp |= TRANS_DP_PORT_SEL_B;
4171 temp |= TRANS_DP_PORT_SEL_C;
4174 temp |= TRANS_DP_PORT_SEL_D;
4180 I915_WRITE(reg, temp);
4183 ironlake_enable_pch_transcoder(dev_priv, pipe);
4186 static void lpt_pch_enable(struct drm_crtc *crtc)
4188 struct drm_device *dev = crtc->dev;
4189 struct drm_i915_private *dev_priv = dev->dev_private;
4190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4193 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4195 lpt_program_iclkip(crtc);
4197 /* Set transcoder timing. */
4198 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4200 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4203 void intel_put_shared_dpll(struct intel_crtc *crtc)
4205 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4210 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4211 WARN(1, "bad %s crtc mask\n", pll->name);
4215 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4216 if (pll->config.crtc_mask == 0) {
4218 WARN_ON(pll->active);
4221 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4224 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4225 struct intel_crtc_state *crtc_state)
4227 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4228 struct intel_shared_dpll *pll;
4229 enum intel_dpll_id i;
4231 if (HAS_PCH_IBX(dev_priv->dev)) {
4232 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4233 i = (enum intel_dpll_id) crtc->pipe;
4234 pll = &dev_priv->shared_dplls[i];
4236 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4237 crtc->base.base.id, pll->name);
4239 WARN_ON(pll->new_config->crtc_mask);
4244 if (IS_BROXTON(dev_priv->dev)) {
4245 /* PLL is attached to port in bxt */
4246 struct intel_encoder *encoder;
4247 struct intel_digital_port *intel_dig_port;
4249 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4250 if (WARN_ON(!encoder))
4253 intel_dig_port = enc_to_dig_port(&encoder->base);
4254 /* 1:1 mapping between ports and PLLs */
4255 i = (enum intel_dpll_id)intel_dig_port->port;
4256 pll = &dev_priv->shared_dplls[i];
4257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258 crtc->base.base.id, pll->name);
4259 WARN_ON(pll->new_config->crtc_mask);
4264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4265 pll = &dev_priv->shared_dplls[i];
4267 /* Only want to check enabled timings first */
4268 if (pll->new_config->crtc_mask == 0)
4271 if (memcmp(&crtc_state->dpll_hw_state,
4272 &pll->new_config->hw_state,
4273 sizeof(pll->new_config->hw_state)) == 0) {
4274 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4275 crtc->base.base.id, pll->name,
4276 pll->new_config->crtc_mask,
4282 /* Ok no matching timings, maybe there's a free one? */
4283 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4284 pll = &dev_priv->shared_dplls[i];
4285 if (pll->new_config->crtc_mask == 0) {
4286 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4287 crtc->base.base.id, pll->name);
4295 if (pll->new_config->crtc_mask == 0)
4296 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4298 crtc_state->shared_dpll = i;
4299 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4300 pipe_name(crtc->pipe));
4302 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4308 * intel_shared_dpll_start_config - start a new PLL staged config
4309 * @dev_priv: DRM device
4310 * @clear_pipes: mask of pipes that will have their PLLs freed
4312 * Starts a new PLL staged config, copying the current config but
4313 * releasing the references of pipes specified in clear_pipes.
4315 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4316 unsigned clear_pipes)
4318 struct intel_shared_dpll *pll;
4319 enum intel_dpll_id i;
4321 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4322 pll = &dev_priv->shared_dplls[i];
4324 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4326 if (!pll->new_config)
4329 pll->new_config->crtc_mask &= ~clear_pipes;
4336 pll = &dev_priv->shared_dplls[i];
4337 kfree(pll->new_config);
4338 pll->new_config = NULL;
4344 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4346 struct intel_shared_dpll *pll;
4347 enum intel_dpll_id i;
4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
4352 WARN_ON(pll->new_config == &pll->config);
4354 pll->config = *pll->new_config;
4355 kfree(pll->new_config);
4356 pll->new_config = NULL;
4360 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4362 struct intel_shared_dpll *pll;
4363 enum intel_dpll_id i;
4365 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4366 pll = &dev_priv->shared_dplls[i];
4368 WARN_ON(pll->new_config == &pll->config);
4370 kfree(pll->new_config);
4371 pll->new_config = NULL;
4375 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4377 struct drm_i915_private *dev_priv = dev->dev_private;
4378 int dslreg = PIPEDSL(pipe);
4381 temp = I915_READ(dslreg);
4383 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4384 if (wait_for(I915_READ(dslreg) != temp, 5))
4385 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4390 * skl_update_scaler_users - Stages update to crtc's scaler state
4392 * @crtc_state: crtc_state
4393 * @plane: plane (NULL indicates crtc is requesting update)
4394 * @plane_state: plane's state
4395 * @force_detach: request unconditional detachment of scaler
4397 * This function updates scaler state for requested plane or crtc.
4398 * To request scaler usage update for a plane, caller shall pass plane pointer.
4399 * To request scaler usage update for crtc, caller shall pass plane pointer
4403 * 0 - scaler_usage updated successfully
4404 * error - requested scaling cannot be supported or other error condition
4407 skl_update_scaler_users(
4408 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4409 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4414 int src_w, src_h, dst_w, dst_h;
4416 struct drm_framebuffer *fb;
4417 struct intel_crtc_scaler_state *scaler_state;
4418 unsigned int rotation;
4420 if (!intel_crtc || !crtc_state)
4423 scaler_state = &crtc_state->scaler_state;
4425 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4426 fb = intel_plane ? plane_state->base.fb : NULL;
4429 src_w = drm_rect_width(&plane_state->src) >> 16;
4430 src_h = drm_rect_height(&plane_state->src) >> 16;
4431 dst_w = drm_rect_width(&plane_state->dst);
4432 dst_h = drm_rect_height(&plane_state->dst);
4433 scaler_id = &plane_state->scaler_id;
4434 rotation = plane_state->base.rotation;
4436 struct drm_display_mode *adjusted_mode =
4437 &crtc_state->base.adjusted_mode;
4438 src_w = crtc_state->pipe_src_w;
4439 src_h = crtc_state->pipe_src_h;
4440 dst_w = adjusted_mode->hdisplay;
4441 dst_h = adjusted_mode->vdisplay;
4442 scaler_id = &scaler_state->scaler_id;
4443 rotation = DRM_ROTATE_0;
4446 need_scaling = intel_rotation_90_or_270(rotation) ?
4447 (src_h != dst_w || src_w != dst_h):
4448 (src_w != dst_w || src_h != dst_h);
4451 * if plane is being disabled or scaler is no more required or force detach
4452 * - free scaler binded to this plane/crtc
4453 * - in order to do this, update crtc->scaler_usage
4455 * Here scaler state in crtc_state is set free so that
4456 * scaler can be assigned to other user. Actual register
4457 * update to free the scaler is done in plane/panel-fit programming.
4458 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4460 if (force_detach || !need_scaling || (intel_plane &&
4461 (!fb || !plane_state->visible))) {
4462 if (*scaler_id >= 0) {
4463 scaler_state->scaler_users &= ~(1 << idx);
4464 scaler_state->scalers[*scaler_id].in_use = 0;
4466 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4467 "crtc_state = %p scaler_users = 0x%x\n",
4468 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4469 intel_plane ? intel_plane->base.base.id :
4470 intel_crtc->base.base.id, crtc_state,
4471 scaler_state->scaler_users);
4478 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4479 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4481 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4482 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4483 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4484 "size is out of scaler range\n",
4485 intel_plane ? "PLANE" : "CRTC",
4486 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4487 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4491 /* check colorkey */
4492 if (WARN_ON(intel_plane &&
4493 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4494 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4495 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4499 /* Check src format */
4501 switch (fb->pixel_format) {
4502 case DRM_FORMAT_RGB565:
4503 case DRM_FORMAT_XBGR8888:
4504 case DRM_FORMAT_XRGB8888:
4505 case DRM_FORMAT_ABGR8888:
4506 case DRM_FORMAT_ARGB8888:
4507 case DRM_FORMAT_XRGB2101010:
4508 case DRM_FORMAT_XBGR2101010:
4509 case DRM_FORMAT_YUYV:
4510 case DRM_FORMAT_YVYU:
4511 case DRM_FORMAT_UYVY:
4512 case DRM_FORMAT_VYUY:
4515 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4516 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4521 /* mark this plane as a scaler user in crtc_state */
4522 scaler_state->scaler_users |= (1 << idx);
4523 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4524 "crtc_state = %p scaler_users = 0x%x\n",
4525 intel_plane ? "PLANE" : "CRTC",
4526 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4527 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4531 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4533 struct drm_device *dev = crtc->base.dev;
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 int pipe = crtc->pipe;
4536 struct intel_crtc_scaler_state *scaler_state =
4537 &crtc->config->scaler_state;
4539 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4541 /* To update pfit, first update scaler state */
4542 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4543 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4544 skl_detach_scalers(crtc);
4548 if (crtc->config->pch_pfit.enabled) {
4551 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4552 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4556 id = scaler_state->scaler_id;
4557 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4558 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4559 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4560 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4562 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4566 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4568 struct drm_device *dev = crtc->base.dev;
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 int pipe = crtc->pipe;
4572 if (crtc->config->pch_pfit.enabled) {
4573 /* Force use of hard-coded filter coefficients
4574 * as some pre-programmed values are broken,
4577 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4578 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4579 PF_PIPE_SEL_IVB(pipe));
4581 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4582 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4583 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4587 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4589 struct drm_device *dev = crtc->dev;
4590 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4591 struct drm_plane *plane;
4592 struct intel_plane *intel_plane;
4594 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4595 intel_plane = to_intel_plane(plane);
4596 if (intel_plane->pipe == pipe)
4597 intel_plane_restore(&intel_plane->base);
4601 void hsw_enable_ips(struct intel_crtc *crtc)
4603 struct drm_device *dev = crtc->base.dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4606 if (!crtc->config->ips_enabled)
4609 /* We can only enable IPS after we enable a plane and wait for a vblank */
4610 intel_wait_for_vblank(dev, crtc->pipe);
4612 assert_plane_enabled(dev_priv, crtc->plane);
4613 if (IS_BROADWELL(dev)) {
4614 mutex_lock(&dev_priv->rps.hw_lock);
4615 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4616 mutex_unlock(&dev_priv->rps.hw_lock);
4617 /* Quoting Art Runyan: "its not safe to expect any particular
4618 * value in IPS_CTL bit 31 after enabling IPS through the
4619 * mailbox." Moreover, the mailbox may return a bogus state,
4620 * so we need to just enable it and continue on.
4623 I915_WRITE(IPS_CTL, IPS_ENABLE);
4624 /* The bit only becomes 1 in the next vblank, so this wait here
4625 * is essentially intel_wait_for_vblank. If we don't have this
4626 * and don't wait for vblanks until the end of crtc_enable, then
4627 * the HW state readout code will complain that the expected
4628 * IPS_CTL value is not the one we read. */
4629 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4630 DRM_ERROR("Timed out waiting for IPS enable\n");
4634 void hsw_disable_ips(struct intel_crtc *crtc)
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4639 if (!crtc->config->ips_enabled)
4642 assert_plane_enabled(dev_priv, crtc->plane);
4643 if (IS_BROADWELL(dev)) {
4644 mutex_lock(&dev_priv->rps.hw_lock);
4645 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4646 mutex_unlock(&dev_priv->rps.hw_lock);
4647 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4648 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4649 DRM_ERROR("Timed out waiting for IPS disable\n");
4651 I915_WRITE(IPS_CTL, 0);
4652 POSTING_READ(IPS_CTL);
4655 /* We need to wait for a vblank before we can disable the plane. */
4656 intel_wait_for_vblank(dev, crtc->pipe);
4659 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4660 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4662 struct drm_device *dev = crtc->dev;
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4665 enum pipe pipe = intel_crtc->pipe;
4666 int palreg = PALETTE(pipe);
4668 bool reenable_ips = false;
4670 /* The clocks have to be on to load the palette. */
4671 if (!crtc->state->enable || !intel_crtc->active)
4674 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4675 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4676 assert_dsi_pll_enabled(dev_priv);
4678 assert_pll_enabled(dev_priv, pipe);
4681 /* use legacy palette for Ironlake */
4682 if (!HAS_GMCH_DISPLAY(dev))
4683 palreg = LGC_PALETTE(pipe);
4685 /* Workaround : Do not read or write the pipe palette/gamma data while
4686 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4688 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4689 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4690 GAMMA_MODE_MODE_SPLIT)) {
4691 hsw_disable_ips(intel_crtc);
4692 reenable_ips = true;
4695 for (i = 0; i < 256; i++) {
4696 I915_WRITE(palreg + 4 * i,
4697 (intel_crtc->lut_r[i] << 16) |
4698 (intel_crtc->lut_g[i] << 8) |
4699 intel_crtc->lut_b[i]);
4703 hsw_enable_ips(intel_crtc);
4706 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4708 if (intel_crtc->overlay) {
4709 struct drm_device *dev = intel_crtc->base.dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4712 mutex_lock(&dev->struct_mutex);
4713 dev_priv->mm.interruptible = false;
4714 (void) intel_overlay_switch_off(intel_crtc->overlay);
4715 dev_priv->mm.interruptible = true;
4716 mutex_unlock(&dev->struct_mutex);
4719 /* Let userspace switch the overlay on again. In most cases userspace
4720 * has to recompute where to put it anyway.
4725 * intel_post_enable_primary - Perform operations after enabling primary plane
4726 * @crtc: the CRTC whose primary plane was just enabled
4728 * Performs potentially sleeping operations that must be done after the primary
4729 * plane is enabled, such as updating FBC and IPS. Note that this may be
4730 * called due to an explicit primary plane update, or due to an implicit
4731 * re-enable that is caused when a sprite plane is updated to no longer
4732 * completely hide the primary plane.
4735 intel_post_enable_primary(struct drm_crtc *crtc)
4737 struct drm_device *dev = crtc->dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 int pipe = intel_crtc->pipe;
4743 * BDW signals flip done immediately if the plane
4744 * is disabled, even if the plane enable is already
4745 * armed to occur at the next vblank :(
4747 if (IS_BROADWELL(dev))
4748 intel_wait_for_vblank(dev, pipe);
4751 * FIXME IPS should be fine as long as one plane is
4752 * enabled, but in practice it seems to have problems
4753 * when going from primary only to sprite only and vice
4756 hsw_enable_ips(intel_crtc);
4758 mutex_lock(&dev->struct_mutex);
4759 intel_fbc_update(dev);
4760 mutex_unlock(&dev->struct_mutex);
4763 * Gen2 reports pipe underruns whenever all planes are disabled.
4764 * So don't enable underrun reporting before at least some planes
4766 * FIXME: Need to fix the logic to work when we turn off all planes
4767 * but leave the pipe running.
4770 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4772 /* Underruns don't raise interrupts, so check manually. */
4773 if (HAS_GMCH_DISPLAY(dev))
4774 i9xx_check_fifo_underruns(dev_priv);
4778 * intel_pre_disable_primary - Perform operations before disabling primary plane
4779 * @crtc: the CRTC whose primary plane is to be disabled
4781 * Performs potentially sleeping operations that must be done before the
4782 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4783 * be called due to an explicit primary plane update, or due to an implicit
4784 * disable that is caused when a sprite plane completely hides the primary
4788 intel_pre_disable_primary(struct drm_crtc *crtc)
4790 struct drm_device *dev = crtc->dev;
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793 int pipe = intel_crtc->pipe;
4796 * Gen2 reports pipe underruns whenever all planes are disabled.
4797 * So diasble underrun reporting before all the planes get disabled.
4798 * FIXME: Need to fix the logic to work when we turn off all planes
4799 * but leave the pipe running.
4802 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4805 * Vblank time updates from the shadow to live plane control register
4806 * are blocked if the memory self-refresh mode is active at that
4807 * moment. So to make sure the plane gets truly disabled, disable
4808 * first the self-refresh mode. The self-refresh enable bit in turn
4809 * will be checked/applied by the HW only at the next frame start
4810 * event which is after the vblank start event, so we need to have a
4811 * wait-for-vblank between disabling the plane and the pipe.
4813 if (HAS_GMCH_DISPLAY(dev))
4814 intel_set_memory_cxsr(dev_priv, false);
4816 mutex_lock(&dev->struct_mutex);
4817 if (dev_priv->fbc.crtc == intel_crtc)
4818 intel_fbc_disable(dev);
4819 mutex_unlock(&dev->struct_mutex);
4822 * FIXME IPS should be fine as long as one plane is
4823 * enabled, but in practice it seems to have problems
4824 * when going from primary only to sprite only and vice
4827 hsw_disable_ips(intel_crtc);
4830 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4832 struct drm_device *dev = crtc->dev;
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 int pipe = intel_crtc->pipe;
4836 intel_enable_primary_hw_plane(crtc->primary, crtc);
4837 intel_enable_sprite_planes(crtc);
4838 intel_crtc_update_cursor(crtc, true);
4840 intel_post_enable_primary(crtc);
4843 * FIXME: Once we grow proper nuclear flip support out of this we need
4844 * to compute the mask of flip planes precisely. For the time being
4845 * consider this a flip to a NULL plane.
4847 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4850 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4852 struct drm_device *dev = crtc->dev;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct intel_plane *intel_plane;
4855 int pipe = intel_crtc->pipe;
4857 intel_crtc_wait_for_pending_flips(crtc);
4859 intel_pre_disable_primary(crtc);
4861 intel_crtc_dpms_overlay_disable(intel_crtc);
4862 for_each_intel_plane(dev, intel_plane) {
4863 if (intel_plane->pipe == pipe) {
4864 struct drm_crtc *from = intel_plane->base.crtc;
4866 intel_plane->disable_plane(&intel_plane->base,
4867 from ?: crtc, true);
4872 * FIXME: Once we grow proper nuclear flip support out of this we need
4873 * to compute the mask of flip planes precisely. For the time being
4874 * consider this a flip to a NULL plane.
4876 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4879 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4881 struct drm_device *dev = crtc->dev;
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4884 struct intel_encoder *encoder;
4885 int pipe = intel_crtc->pipe;
4887 WARN_ON(!crtc->state->enable);
4889 if (intel_crtc->active)
4892 if (intel_crtc->config->has_pch_encoder)
4893 intel_prepare_shared_dpll(intel_crtc);
4895 if (intel_crtc->config->has_dp_encoder)
4896 intel_dp_set_m_n(intel_crtc, M1_N1);
4898 intel_set_pipe_timings(intel_crtc);
4900 if (intel_crtc->config->has_pch_encoder) {
4901 intel_cpu_transcoder_set_m_n(intel_crtc,
4902 &intel_crtc->config->fdi_m_n, NULL);
4905 ironlake_set_pipeconf(crtc);
4907 intel_crtc->active = true;
4909 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4910 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4912 for_each_encoder_on_crtc(dev, crtc, encoder)
4913 if (encoder->pre_enable)
4914 encoder->pre_enable(encoder);
4916 if (intel_crtc->config->has_pch_encoder) {
4917 /* Note: FDI PLL enabling _must_ be done before we enable the
4918 * cpu pipes, hence this is separate from all the other fdi/pch
4920 ironlake_fdi_pll_enable(intel_crtc);
4922 assert_fdi_tx_disabled(dev_priv, pipe);
4923 assert_fdi_rx_disabled(dev_priv, pipe);
4926 ironlake_pfit_enable(intel_crtc);
4929 * On ILK+ LUT must be loaded before the pipe is running but with
4932 intel_crtc_load_lut(crtc);
4934 intel_update_watermarks(crtc);
4935 intel_enable_pipe(intel_crtc);
4937 if (intel_crtc->config->has_pch_encoder)
4938 ironlake_pch_enable(crtc);
4940 assert_vblank_disabled(crtc);
4941 drm_crtc_vblank_on(crtc);
4943 for_each_encoder_on_crtc(dev, crtc, encoder)
4944 encoder->enable(encoder);
4946 if (HAS_PCH_CPT(dev))
4947 cpt_verify_modeset(dev, intel_crtc->pipe);
4950 /* IPS only exists on ULT machines and is tied to pipe A. */
4951 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4953 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4957 * This implements the workaround described in the "notes" section of the mode
4958 * set sequence documentation. When going from no pipes or single pipe to
4959 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4960 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4962 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4964 struct drm_device *dev = crtc->base.dev;
4965 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4967 /* We want to get the other_active_crtc only if there's only 1 other
4969 for_each_intel_crtc(dev, crtc_it) {
4970 if (!crtc_it->active || crtc_it == crtc)
4973 if (other_active_crtc)
4976 other_active_crtc = crtc_it;
4978 if (!other_active_crtc)
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985 static void haswell_crtc_enable(struct drm_crtc *crtc)
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990 struct intel_encoder *encoder;
4991 int pipe = intel_crtc->pipe;
4993 WARN_ON(!crtc->state->enable);
4995 if (intel_crtc->active)
4998 if (intel_crtc_to_shared_dpll(intel_crtc))
4999 intel_enable_shared_dpll(intel_crtc);
5001 if (intel_crtc->config->has_dp_encoder)
5002 intel_dp_set_m_n(intel_crtc, M1_N1);
5004 intel_set_pipe_timings(intel_crtc);
5006 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5007 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5008 intel_crtc->config->pixel_multiplier - 1);
5011 if (intel_crtc->config->has_pch_encoder) {
5012 intel_cpu_transcoder_set_m_n(intel_crtc,
5013 &intel_crtc->config->fdi_m_n, NULL);
5016 haswell_set_pipeconf(crtc);
5018 intel_set_pipe_csc(crtc);
5020 intel_crtc->active = true;
5022 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5023 for_each_encoder_on_crtc(dev, crtc, encoder)
5024 if (encoder->pre_enable)
5025 encoder->pre_enable(encoder);
5027 if (intel_crtc->config->has_pch_encoder) {
5028 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030 dev_priv->display.fdi_link_train(crtc);
5033 intel_ddi_enable_pipe_clock(intel_crtc);
5035 if (INTEL_INFO(dev)->gen == 9)
5036 skylake_pfit_update(intel_crtc, 1);
5037 else if (INTEL_INFO(dev)->gen < 9)
5038 ironlake_pfit_enable(intel_crtc);
5040 MISSING_CASE(INTEL_INFO(dev)->gen);
5043 * On ILK+ LUT must be loaded before the pipe is running but with
5046 intel_crtc_load_lut(crtc);
5048 intel_ddi_set_pipe_settings(crtc);
5049 intel_ddi_enable_transcoder_func(crtc);
5051 intel_update_watermarks(crtc);
5052 intel_enable_pipe(intel_crtc);
5054 if (intel_crtc->config->has_pch_encoder)
5055 lpt_pch_enable(crtc);
5057 if (intel_crtc->config->dp_encoder_is_mst)
5058 intel_ddi_set_vc_payload_alloc(crtc, true);
5060 assert_vblank_disabled(crtc);
5061 drm_crtc_vblank_on(crtc);
5063 for_each_encoder_on_crtc(dev, crtc, encoder) {
5064 encoder->enable(encoder);
5065 intel_opregion_notify_encoder(encoder, true);
5068 /* If we change the relative order between pipe/planes enabling, we need
5069 * to change the workaround. */
5070 haswell_mode_set_planes_workaround(intel_crtc);
5073 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 int pipe = crtc->pipe;
5079 /* To avoid upsetting the power well on haswell only disable the pfit if
5080 * it's in use. The hw state code will make sure we get this right. */
5081 if (crtc->config->pch_pfit.enabled) {
5082 I915_WRITE(PF_CTL(pipe), 0);
5083 I915_WRITE(PF_WIN_POS(pipe), 0);
5084 I915_WRITE(PF_WIN_SZ(pipe), 0);
5088 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5093 struct intel_encoder *encoder;
5094 int pipe = intel_crtc->pipe;
5097 if (!intel_crtc->active)
5100 for_each_encoder_on_crtc(dev, crtc, encoder)
5101 encoder->disable(encoder);
5103 drm_crtc_vblank_off(crtc);
5104 assert_vblank_disabled(crtc);
5106 if (intel_crtc->config->has_pch_encoder)
5107 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5109 intel_disable_pipe(intel_crtc);
5111 ironlake_pfit_disable(intel_crtc);
5113 if (intel_crtc->config->has_pch_encoder)
5114 ironlake_fdi_disable(crtc);
5116 for_each_encoder_on_crtc(dev, crtc, encoder)
5117 if (encoder->post_disable)
5118 encoder->post_disable(encoder);
5120 if (intel_crtc->config->has_pch_encoder) {
5121 ironlake_disable_pch_transcoder(dev_priv, pipe);
5123 if (HAS_PCH_CPT(dev)) {
5124 /* disable TRANS_DP_CTL */
5125 reg = TRANS_DP_CTL(pipe);
5126 temp = I915_READ(reg);
5127 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5128 TRANS_DP_PORT_SEL_MASK);
5129 temp |= TRANS_DP_PORT_SEL_NONE;
5130 I915_WRITE(reg, temp);
5132 /* disable DPLL_SEL */
5133 temp = I915_READ(PCH_DPLL_SEL);
5134 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5135 I915_WRITE(PCH_DPLL_SEL, temp);
5138 /* disable PCH DPLL */
5139 intel_disable_shared_dpll(intel_crtc);
5141 ironlake_fdi_pll_disable(intel_crtc);
5144 intel_crtc->active = false;
5145 intel_update_watermarks(crtc);
5147 mutex_lock(&dev->struct_mutex);
5148 intel_fbc_update(dev);
5149 mutex_unlock(&dev->struct_mutex);
5152 static void haswell_crtc_disable(struct drm_crtc *crtc)
5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 struct intel_encoder *encoder;
5158 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5160 if (!intel_crtc->active)
5163 for_each_encoder_on_crtc(dev, crtc, encoder) {
5164 intel_opregion_notify_encoder(encoder, false);
5165 encoder->disable(encoder);
5168 drm_crtc_vblank_off(crtc);
5169 assert_vblank_disabled(crtc);
5171 if (intel_crtc->config->has_pch_encoder)
5172 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5174 intel_disable_pipe(intel_crtc);
5176 if (intel_crtc->config->dp_encoder_is_mst)
5177 intel_ddi_set_vc_payload_alloc(crtc, false);
5179 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5181 if (INTEL_INFO(dev)->gen == 9)
5182 skylake_pfit_update(intel_crtc, 0);
5183 else if (INTEL_INFO(dev)->gen < 9)
5184 ironlake_pfit_disable(intel_crtc);
5186 MISSING_CASE(INTEL_INFO(dev)->gen);
5188 intel_ddi_disable_pipe_clock(intel_crtc);
5190 if (intel_crtc->config->has_pch_encoder) {
5191 lpt_disable_pch_transcoder(dev_priv);
5192 intel_ddi_fdi_disable(crtc);
5195 for_each_encoder_on_crtc(dev, crtc, encoder)
5196 if (encoder->post_disable)
5197 encoder->post_disable(encoder);
5199 intel_crtc->active = false;
5200 intel_update_watermarks(crtc);
5202 mutex_lock(&dev->struct_mutex);
5203 intel_fbc_update(dev);
5204 mutex_unlock(&dev->struct_mutex);
5206 if (intel_crtc_to_shared_dpll(intel_crtc))
5207 intel_disable_shared_dpll(intel_crtc);
5210 static void ironlake_crtc_off(struct drm_crtc *crtc)
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213 intel_put_shared_dpll(intel_crtc);
5217 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5219 struct drm_device *dev = crtc->base.dev;
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221 struct intel_crtc_state *pipe_config = crtc->config;
5223 if (!pipe_config->gmch_pfit.control)
5227 * The panel fitter should only be adjusted whilst the pipe is disabled,
5228 * according to register description and PRM.
5230 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5231 assert_pipe_disabled(dev_priv, crtc->pipe);
5233 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5234 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5236 /* Border color in case we don't scale up to the full screen. Black by
5237 * default, change to something else for debugging. */
5238 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5241 static enum intel_display_power_domain port_to_power_domain(enum port port)
5245 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5247 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5249 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5251 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5254 return POWER_DOMAIN_PORT_OTHER;
5258 #define for_each_power_domain(domain, mask) \
5259 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5260 if ((1 << (domain)) & (mask))
5262 enum intel_display_power_domain
5263 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5265 struct drm_device *dev = intel_encoder->base.dev;
5266 struct intel_digital_port *intel_dig_port;
5268 switch (intel_encoder->type) {
5269 case INTEL_OUTPUT_UNKNOWN:
5270 /* Only DDI platforms should ever use this output type */
5271 WARN_ON_ONCE(!HAS_DDI(dev));
5272 case INTEL_OUTPUT_DISPLAYPORT:
5273 case INTEL_OUTPUT_HDMI:
5274 case INTEL_OUTPUT_EDP:
5275 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5276 return port_to_power_domain(intel_dig_port->port);
5277 case INTEL_OUTPUT_DP_MST:
5278 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5279 return port_to_power_domain(intel_dig_port->port);
5280 case INTEL_OUTPUT_ANALOG:
5281 return POWER_DOMAIN_PORT_CRT;
5282 case INTEL_OUTPUT_DSI:
5283 return POWER_DOMAIN_PORT_DSI;
5285 return POWER_DOMAIN_PORT_OTHER;
5289 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5291 struct drm_device *dev = crtc->dev;
5292 struct intel_encoder *intel_encoder;
5293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294 enum pipe pipe = intel_crtc->pipe;
5296 enum transcoder transcoder;
5298 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5300 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5301 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5302 if (intel_crtc->config->pch_pfit.enabled ||
5303 intel_crtc->config->pch_pfit.force_thru)
5304 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5306 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5307 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5312 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5314 struct drm_device *dev = state->dev;
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5317 struct intel_crtc *crtc;
5320 * First get all needed power domains, then put all unneeded, to avoid
5321 * any unnecessary toggling of the power wells.
5323 for_each_intel_crtc(dev, crtc) {
5324 enum intel_display_power_domain domain;
5326 if (!crtc->base.state->enable)
5329 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5331 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5332 intel_display_power_get(dev_priv, domain);
5335 if (dev_priv->display.modeset_global_resources)
5336 dev_priv->display.modeset_global_resources(state);
5338 for_each_intel_crtc(dev, crtc) {
5339 enum intel_display_power_domain domain;
5341 for_each_power_domain(domain, crtc->enabled_power_domains)
5342 intel_display_power_put(dev_priv, domain);
5344 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5347 intel_display_set_init_power(dev_priv, false);
5350 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5355 uint32_t current_freq;
5358 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5359 switch (frequency) {
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5362 ratio = BXT_DE_PLL_RATIO(60);
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5366 ratio = BXT_DE_PLL_RATIO(60);
5369 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5370 ratio = BXT_DE_PLL_RATIO(60);
5373 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5374 ratio = BXT_DE_PLL_RATIO(60);
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5378 ratio = BXT_DE_PLL_RATIO(65);
5382 * Bypass frequency with DE PLL disabled. Init ratio, divider
5383 * to suppress GCC warning.
5389 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5394 mutex_lock(&dev_priv->rps.hw_lock);
5395 /* Inform power controller of upcoming frequency change */
5396 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 mutex_unlock(&dev_priv->rps.hw_lock);
5401 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5406 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5407 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5408 current_freq = current_freq * 500 + 1000;
5411 * DE PLL has to be disabled when
5412 * - setting to 19.2MHz (bypass, PLL isn't used)
5413 * - before setting to 624MHz (PLL needs toggling)
5414 * - before setting to any frequency from 624MHz (PLL needs toggling)
5416 if (frequency == 19200 || frequency == 624000 ||
5417 current_freq == 624000) {
5418 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5420 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5422 DRM_ERROR("timout waiting for DE PLL unlock\n");
5425 if (frequency != 19200) {
5428 val = I915_READ(BXT_DE_PLL_CTL);
5429 val &= ~BXT_DE_PLL_RATIO_MASK;
5431 I915_WRITE(BXT_DE_PLL_CTL, val);
5433 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5435 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5436 DRM_ERROR("timeout waiting for DE PLL lock\n");
5438 val = I915_READ(CDCLK_CTL);
5439 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5442 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5445 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5446 if (frequency >= 500000)
5447 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5450 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5451 val |= (frequency - 1000) / 500;
5452 I915_WRITE(CDCLK_CTL, val);
5455 mutex_lock(&dev_priv->rps.hw_lock);
5456 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5457 DIV_ROUND_UP(frequency, 25000));
5458 mutex_unlock(&dev_priv->rps.hw_lock);
5461 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5466 dev_priv->cdclk_freq = frequency;
5469 void broxton_init_cdclk(struct drm_device *dev)
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5475 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5476 * or else the reset will hang because there is no PCH to respond.
5477 * Move the handshake programming to initialization sequence.
5478 * Previously was left up to BIOS.
5480 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5481 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5482 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5484 /* Enable PG1 for cdclk */
5485 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5487 /* check if cd clock is enabled */
5488 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5489 DRM_DEBUG_KMS("Display already initialized\n");
5495 * - The initial CDCLK needs to be read from VBT.
5496 * Need to make this change after VBT has changes for BXT.
5497 * - check if setting the max (or any) cdclk freq is really necessary
5498 * here, it belongs to modeset time
5500 broxton_set_cdclk(dev, 624000);
5502 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5503 POSTING_READ(DBUF_CTL);
5507 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5508 DRM_ERROR("DBuf power enable timeout!\n");
5511 void broxton_uninit_cdclk(struct drm_device *dev)
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5515 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5516 POSTING_READ(DBUF_CTL);
5520 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5521 DRM_ERROR("DBuf power disable timeout!\n");
5523 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5524 broxton_set_cdclk(dev, 19200);
5526 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5529 static const struct skl_cdclk_entry {
5532 } skl_cdclk_frequencies[] = {
5533 { .freq = 308570, .vco = 8640 },
5534 { .freq = 337500, .vco = 8100 },
5535 { .freq = 432000, .vco = 8640 },
5536 { .freq = 450000, .vco = 8100 },
5537 { .freq = 540000, .vco = 8100 },
5538 { .freq = 617140, .vco = 8640 },
5539 { .freq = 675000, .vco = 8100 },
5542 static unsigned int skl_cdclk_decimal(unsigned int freq)
5544 return (freq - 1000) / 500;
5547 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5551 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5552 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5554 if (e->freq == freq)
5562 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5564 unsigned int min_freq;
5567 /* select the minimum CDCLK before enabling DPLL 0 */
5568 val = I915_READ(CDCLK_CTL);
5569 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5570 val |= CDCLK_FREQ_337_308;
5572 if (required_vco == 8640)
5577 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5579 I915_WRITE(CDCLK_CTL, val);
5580 POSTING_READ(CDCLK_CTL);
5583 * We always enable DPLL0 with the lowest link rate possible, but still
5584 * taking into account the VCO required to operate the eDP panel at the
5585 * desired frequency. The usual DP link rates operate with a VCO of
5586 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5587 * The modeset code is responsible for the selection of the exact link
5588 * rate later on, with the constraint of choosing a frequency that
5589 * works with required_vco.
5591 val = I915_READ(DPLL_CTRL1);
5593 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5594 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5595 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5596 if (required_vco == 8640)
5597 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5600 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5603 I915_WRITE(DPLL_CTRL1, val);
5604 POSTING_READ(DPLL_CTRL1);
5606 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5608 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5609 DRM_ERROR("DPLL0 not locked\n");
5612 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5617 /* inform PCU we want to change CDCLK */
5618 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5619 mutex_lock(&dev_priv->rps.hw_lock);
5620 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5621 mutex_unlock(&dev_priv->rps.hw_lock);
5623 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5626 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5630 for (i = 0; i < 15; i++) {
5631 if (skl_cdclk_pcu_ready(dev_priv))
5639 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5641 u32 freq_select, pcu_ack;
5643 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5645 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646 DRM_ERROR("failed to inform PCU about cdclk change\n");
5654 freq_select = CDCLK_FREQ_450_432;
5658 freq_select = CDCLK_FREQ_540;
5664 freq_select = CDCLK_FREQ_337_308;
5669 freq_select = CDCLK_FREQ_675_617;
5674 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5675 POSTING_READ(CDCLK_CTL);
5677 /* inform PCU of the change */
5678 mutex_lock(&dev_priv->rps.hw_lock);
5679 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680 mutex_unlock(&dev_priv->rps.hw_lock);
5683 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5685 /* disable DBUF power */
5686 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5687 POSTING_READ(DBUF_CTL);
5691 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5692 DRM_ERROR("DBuf power disable timeout\n");
5695 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5696 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5697 DRM_ERROR("Couldn't disable DPLL0\n");
5699 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5702 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5705 unsigned int required_vco;
5707 /* enable PCH reset handshake */
5708 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5709 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5711 /* enable PG1 and Misc I/O */
5712 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5714 /* DPLL0 already enabed !? */
5715 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5716 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5721 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5722 skl_dpll0_enable(dev_priv, required_vco);
5724 /* set CDCLK to the frequency the BIOS chose */
5725 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5727 /* enable DBUF power */
5728 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5729 POSTING_READ(DBUF_CTL);
5733 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5734 DRM_ERROR("DBuf power enable timeout\n");
5737 /* returns HPLL frequency in kHz */
5738 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5740 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5742 /* Obtain SKU information */
5743 mutex_lock(&dev_priv->sb_lock);
5744 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5745 CCK_FUSE_HPLL_FREQ_MASK;
5746 mutex_unlock(&dev_priv->sb_lock);
5748 return vco_freq[hpll_freq] * 1000;
5751 static void vlv_update_cdclk(struct drm_device *dev)
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5755 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5756 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5757 dev_priv->cdclk_freq);
5760 * Program the gmbus_freq based on the cdclk frequency.
5761 * BSpec erroneously claims we should aim for 4MHz, but
5762 * in fact 1MHz is the correct frequency.
5764 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5767 /* Adjust CDclk dividers to allow high res or save power if possible */
5768 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5770 struct drm_i915_private *dev_priv = dev->dev_private;
5773 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5774 != dev_priv->cdclk_freq);
5776 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5778 else if (cdclk == 266667)
5783 mutex_lock(&dev_priv->rps.hw_lock);
5784 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5785 val &= ~DSPFREQGUAR_MASK;
5786 val |= (cmd << DSPFREQGUAR_SHIFT);
5787 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5788 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5789 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5791 DRM_ERROR("timed out waiting for CDclk change\n");
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5795 mutex_lock(&dev_priv->sb_lock);
5797 if (cdclk == 400000) {
5800 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5802 /* adjust cdclk divider */
5803 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5804 val &= ~DISPLAY_FREQUENCY_VALUES;
5806 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5808 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5809 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5811 DRM_ERROR("timed out waiting for CDclk change\n");
5814 /* adjust self-refresh exit latency value */
5815 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819 * For high bandwidth configs, we set a higher latency in the bunit
5820 * so that the core display fetch happens in time to avoid underruns.
5822 if (cdclk == 400000)
5823 val |= 4500 / 250; /* 4.5 usec */
5825 val |= 3000 / 250; /* 3.0 usec */
5826 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5828 mutex_unlock(&dev_priv->sb_lock);
5830 vlv_update_cdclk(dev);
5833 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5838 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5839 != dev_priv->cdclk_freq);
5848 MISSING_CASE(cdclk);
5853 * Specs are full of misinformation, but testing on actual
5854 * hardware has shown that we just need to write the desired
5855 * CCK divider into the Punit register.
5857 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5859 mutex_lock(&dev_priv->rps.hw_lock);
5860 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5861 val &= ~DSPFREQGUAR_MASK_CHV;
5862 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5863 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5864 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5865 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5867 DRM_ERROR("timed out waiting for CDclk change\n");
5869 mutex_unlock(&dev_priv->rps.hw_lock);
5871 vlv_update_cdclk(dev);
5874 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5877 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5878 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5881 * Really only a few cases to deal with, as only 4 CDclks are supported:
5884 * 320/333MHz (depends on HPLL freq)
5886 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5887 * of the lower bin and adjust if needed.
5889 * We seem to get an unstable or solid color picture at 200MHz.
5890 * Not sure what's wrong. For now use 200MHz only when all pipes
5893 if (!IS_CHERRYVIEW(dev_priv) &&
5894 max_pixclk > freq_320*limit/100)
5896 else if (max_pixclk > 266667*limit/100)
5898 else if (max_pixclk > 0)
5904 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5909 * - remove the guardband, it's not needed on BXT
5910 * - set 19.2MHz bypass frequency if there are no active pipes
5912 if (max_pixclk > 576000*9/10)
5914 else if (max_pixclk > 384000*9/10)
5916 else if (max_pixclk > 288000*9/10)
5918 else if (max_pixclk > 144000*9/10)
5924 /* Compute the max pixel clock for new configuration. Uses atomic state if
5925 * that's non-NULL, look at current state otherwise. */
5926 static int intel_mode_max_pixclk(struct drm_device *dev,
5927 struct drm_atomic_state *state)
5929 struct intel_crtc *intel_crtc;
5930 struct intel_crtc_state *crtc_state;
5933 for_each_intel_crtc(dev, intel_crtc) {
5936 intel_atomic_get_crtc_state(state, intel_crtc);
5938 crtc_state = intel_crtc->config;
5939 if (IS_ERR(crtc_state))
5940 return PTR_ERR(crtc_state);
5942 if (!crtc_state->base.enable)
5945 max_pixclk = max(max_pixclk,
5946 crtc_state->base.adjusted_mode.crtc_clock);
5952 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5954 struct drm_i915_private *dev_priv = to_i915(state->dev);
5955 struct drm_crtc *crtc;
5956 struct drm_crtc_state *crtc_state;
5957 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5963 if (IS_VALLEYVIEW(dev_priv))
5964 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5966 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5968 if (cdclk == dev_priv->cdclk_freq)
5971 /* add all active pipes to the state */
5972 for_each_crtc(state->dev, crtc) {
5973 if (!crtc->state->enable)
5976 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5977 if (IS_ERR(crtc_state))
5978 return PTR_ERR(crtc_state);
5981 /* disable/enable all currently active pipes while we change cdclk */
5982 for_each_crtc_in_state(state, crtc, crtc_state, i)
5983 if (crtc_state->enable)
5984 crtc_state->mode_changed = true;
5989 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5991 unsigned int credits, default_credits;
5993 if (IS_CHERRYVIEW(dev_priv))
5994 default_credits = PFI_CREDIT(12);
5996 default_credits = PFI_CREDIT(8);
5998 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5999 /* CHV suggested value is 31 or 63 */
6000 if (IS_CHERRYVIEW(dev_priv))
6001 credits = PFI_CREDIT_31;
6003 credits = PFI_CREDIT(15);
6005 credits = default_credits;
6009 * WA - write default credits before re-programming
6010 * FIXME: should we also set the resend bit here?
6012 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6015 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016 credits | PFI_CREDIT_RESEND);
6019 * FIXME is this guaranteed to clear
6020 * immediately or should we poll for it?
6022 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6025 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6027 struct drm_device *dev = old_state->dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6032 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6034 if (WARN_ON(max_pixclk < 0))
6037 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6039 if (req_cdclk != dev_priv->cdclk_freq) {
6041 * FIXME: We can end up here with all power domains off, yet
6042 * with a CDCLK frequency other than the minimum. To account
6043 * for this take the PIPE-A power domain, which covers the HW
6044 * blocks needed for the following programming. This can be
6045 * removed once it's guaranteed that we get here either with
6046 * the minimum CDCLK set, or the required power domains
6049 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6051 if (IS_CHERRYVIEW(dev))
6052 cherryview_set_cdclk(dev, req_cdclk);
6054 valleyview_set_cdclk(dev, req_cdclk);
6056 vlv_program_pfi_credits(dev_priv);
6058 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6062 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = to_i915(dev);
6066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6067 struct intel_encoder *encoder;
6068 int pipe = intel_crtc->pipe;
6071 WARN_ON(!crtc->state->enable);
6073 if (intel_crtc->active)
6076 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6079 if (IS_CHERRYVIEW(dev))
6080 chv_prepare_pll(intel_crtc, intel_crtc->config);
6082 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6085 if (intel_crtc->config->has_dp_encoder)
6086 intel_dp_set_m_n(intel_crtc, M1_N1);
6088 intel_set_pipe_timings(intel_crtc);
6090 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6093 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6094 I915_WRITE(CHV_CANVAS(pipe), 0);
6097 i9xx_set_pipeconf(intel_crtc);
6099 intel_crtc->active = true;
6101 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 if (encoder->pre_pll_enable)
6105 encoder->pre_pll_enable(encoder);
6108 if (IS_CHERRYVIEW(dev))
6109 chv_enable_pll(intel_crtc, intel_crtc->config);
6111 vlv_enable_pll(intel_crtc, intel_crtc->config);
6114 for_each_encoder_on_crtc(dev, crtc, encoder)
6115 if (encoder->pre_enable)
6116 encoder->pre_enable(encoder);
6118 i9xx_pfit_enable(intel_crtc);
6120 intel_crtc_load_lut(crtc);
6122 intel_update_watermarks(crtc);
6123 intel_enable_pipe(intel_crtc);
6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 encoder->enable(encoder);
6132 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6137 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6138 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6141 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6143 struct drm_device *dev = crtc->dev;
6144 struct drm_i915_private *dev_priv = to_i915(dev);
6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146 struct intel_encoder *encoder;
6147 int pipe = intel_crtc->pipe;
6149 WARN_ON(!crtc->state->enable);
6151 if (intel_crtc->active)
6154 i9xx_set_pll_dividers(intel_crtc);
6156 if (intel_crtc->config->has_dp_encoder)
6157 intel_dp_set_m_n(intel_crtc, M1_N1);
6159 intel_set_pipe_timings(intel_crtc);
6161 i9xx_set_pipeconf(intel_crtc);
6163 intel_crtc->active = true;
6166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6168 for_each_encoder_on_crtc(dev, crtc, encoder)
6169 if (encoder->pre_enable)
6170 encoder->pre_enable(encoder);
6172 i9xx_enable_pll(intel_crtc);
6174 i9xx_pfit_enable(intel_crtc);
6176 intel_crtc_load_lut(crtc);
6178 intel_update_watermarks(crtc);
6179 intel_enable_pipe(intel_crtc);
6181 assert_vblank_disabled(crtc);
6182 drm_crtc_vblank_on(crtc);
6184 for_each_encoder_on_crtc(dev, crtc, encoder)
6185 encoder->enable(encoder);
6188 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6190 struct drm_device *dev = crtc->base.dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6193 if (!crtc->config->gmch_pfit.control)
6196 assert_pipe_disabled(dev_priv, crtc->pipe);
6198 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6199 I915_READ(PFIT_CONTROL));
6200 I915_WRITE(PFIT_CONTROL, 0);
6203 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6205 struct drm_device *dev = crtc->dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 struct intel_encoder *encoder;
6209 int pipe = intel_crtc->pipe;
6211 if (!intel_crtc->active)
6215 * On gen2 planes are double buffered but the pipe isn't, so we must
6216 * wait for planes to fully turn off before disabling the pipe.
6217 * We also need to wait on all gmch platforms because of the
6218 * self-refresh mode constraint explained above.
6220 intel_wait_for_vblank(dev, pipe);
6222 for_each_encoder_on_crtc(dev, crtc, encoder)
6223 encoder->disable(encoder);
6225 drm_crtc_vblank_off(crtc);
6226 assert_vblank_disabled(crtc);
6228 intel_disable_pipe(intel_crtc);
6230 i9xx_pfit_disable(intel_crtc);
6232 for_each_encoder_on_crtc(dev, crtc, encoder)
6233 if (encoder->post_disable)
6234 encoder->post_disable(encoder);
6236 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6237 if (IS_CHERRYVIEW(dev))
6238 chv_disable_pll(dev_priv, pipe);
6239 else if (IS_VALLEYVIEW(dev))
6240 vlv_disable_pll(dev_priv, pipe);
6242 i9xx_disable_pll(intel_crtc);
6246 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6248 intel_crtc->active = false;
6249 intel_update_watermarks(crtc);
6251 mutex_lock(&dev->struct_mutex);
6252 intel_fbc_update(dev);
6253 mutex_unlock(&dev->struct_mutex);
6256 static void i9xx_crtc_off(struct drm_crtc *crtc)
6260 /* Master function to enable/disable CRTC and corresponding power wells */
6261 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266 enum intel_display_power_domain domain;
6267 unsigned long domains;
6270 if (!intel_crtc->active) {
6271 domains = get_crtc_power_domains(crtc);
6272 for_each_power_domain(domain, domains)
6273 intel_display_power_get(dev_priv, domain);
6274 intel_crtc->enabled_power_domains = domains;
6276 dev_priv->display.crtc_enable(crtc);
6277 intel_crtc_enable_planes(crtc);
6280 if (intel_crtc->active) {
6281 intel_crtc_disable_planes(crtc);
6282 dev_priv->display.crtc_disable(crtc);
6284 domains = intel_crtc->enabled_power_domains;
6285 for_each_power_domain(domain, domains)
6286 intel_display_power_put(dev_priv, domain);
6287 intel_crtc->enabled_power_domains = 0;
6293 * Sets the power management mode of the pipe and plane.
6295 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6297 struct drm_device *dev = crtc->dev;
6298 struct intel_encoder *intel_encoder;
6299 bool enable = false;
6301 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6302 enable |= intel_encoder->connectors_active;
6304 intel_crtc_control(crtc, enable);
6306 crtc->state->active = enable;
6309 static void intel_crtc_disable(struct drm_crtc *crtc)
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_connector *connector;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6315 /* crtc should still be enabled when we disable it. */
6316 WARN_ON(!crtc->state->enable);
6318 intel_crtc_disable_planes(crtc);
6319 dev_priv->display.crtc_disable(crtc);
6320 dev_priv->display.off(crtc);
6322 drm_plane_helper_disable(crtc->primary);
6324 /* Update computed state. */
6325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6326 if (!connector->encoder || !connector->encoder->crtc)
6329 if (connector->encoder->crtc != crtc)
6332 connector->dpms = DRM_MODE_DPMS_OFF;
6333 to_intel_encoder(connector->encoder)->connectors_active = false;
6337 void intel_encoder_destroy(struct drm_encoder *encoder)
6339 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6341 drm_encoder_cleanup(encoder);
6342 kfree(intel_encoder);
6345 /* Simple dpms helper for encoders with just one connector, no cloning and only
6346 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347 * state of the entire output pipe. */
6348 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6350 if (mode == DRM_MODE_DPMS_ON) {
6351 encoder->connectors_active = true;
6353 intel_crtc_update_dpms(encoder->base.crtc);
6355 encoder->connectors_active = false;
6357 intel_crtc_update_dpms(encoder->base.crtc);
6361 /* Cross check the actual hw state with our own modeset state tracking (and it's
6362 * internal consistency). */
6363 static void intel_connector_check_state(struct intel_connector *connector)
6365 if (connector->get_hw_state(connector)) {
6366 struct intel_encoder *encoder = connector->encoder;
6367 struct drm_crtc *crtc;
6368 bool encoder_enabled;
6371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372 connector->base.base.id,
6373 connector->base.name);
6375 /* there is no real hw state for MST connectors */
6376 if (connector->mst_port)
6379 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6380 "wrong connector dpms state\n");
6381 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6382 "active connector not linked to encoder\n");
6385 I915_STATE_WARN(!encoder->connectors_active,
6386 "encoder->connectors_active not set\n");
6388 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6389 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6390 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6393 crtc = encoder->base.crtc;
6395 I915_STATE_WARN(!crtc->state->enable,
6396 "crtc not enabled\n");
6397 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6398 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6399 "encoder active on the wrong pipe\n");
6404 int intel_connector_init(struct intel_connector *connector)
6406 struct drm_connector_state *connector_state;
6408 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6409 if (!connector_state)
6412 connector->base.state = connector_state;
6416 struct intel_connector *intel_connector_alloc(void)
6418 struct intel_connector *connector;
6420 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6424 if (intel_connector_init(connector) < 0) {
6432 /* Even simpler default implementation, if there's really no special case to
6434 void intel_connector_dpms(struct drm_connector *connector, int mode)
6436 /* All the simple cases only support two dpms states. */
6437 if (mode != DRM_MODE_DPMS_ON)
6438 mode = DRM_MODE_DPMS_OFF;
6440 if (mode == connector->dpms)
6443 connector->dpms = mode;
6445 /* Only need to change hw state when actually enabled */
6446 if (connector->encoder)
6447 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6449 intel_modeset_check_state(connector->dev);
6452 /* Simple connector->get_hw_state implementation for encoders that support only
6453 * one connector and no cloning and hence the encoder state determines the state
6454 * of the connector. */
6455 bool intel_connector_get_hw_state(struct intel_connector *connector)
6458 struct intel_encoder *encoder = connector->encoder;
6460 return encoder->get_hw_state(encoder, &pipe);
6463 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6465 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6466 return crtc_state->fdi_lanes;
6471 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6472 struct intel_crtc_state *pipe_config)
6474 struct drm_atomic_state *state = pipe_config->base.state;
6475 struct intel_crtc *other_crtc;
6476 struct intel_crtc_state *other_crtc_state;
6478 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479 pipe_name(pipe), pipe_config->fdi_lanes);
6480 if (pipe_config->fdi_lanes > 4) {
6481 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6487 if (pipe_config->fdi_lanes > 2) {
6488 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489 pipe_config->fdi_lanes);
6496 if (INTEL_INFO(dev)->num_pipes == 2)
6499 /* Ivybridge 3 pipe is really complicated */
6504 if (pipe_config->fdi_lanes <= 2)
6507 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6509 intel_atomic_get_crtc_state(state, other_crtc);
6510 if (IS_ERR(other_crtc_state))
6511 return PTR_ERR(other_crtc_state);
6513 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6514 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6520 if (pipe_config->fdi_lanes > 2) {
6521 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6526 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6528 intel_atomic_get_crtc_state(state, other_crtc);
6529 if (IS_ERR(other_crtc_state))
6530 return PTR_ERR(other_crtc_state);
6532 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6533 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6543 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6544 struct intel_crtc_state *pipe_config)
6546 struct drm_device *dev = intel_crtc->base.dev;
6547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548 int lane, link_bw, fdi_dotclock, ret;
6549 bool needs_recompute = false;
6552 /* FDI is a binary signal running at ~2.7GHz, encoding
6553 * each output octet as 10 bits. The actual frequency
6554 * is stored as a divider into a 100MHz clock, and the
6555 * mode pixel clock is stored in units of 1KHz.
6556 * Hence the bw of each lane in terms of the mode signal
6559 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6561 fdi_dotclock = adjusted_mode->crtc_clock;
6563 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6564 pipe_config->pipe_bpp);
6566 pipe_config->fdi_lanes = lane;
6568 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6569 link_bw, &pipe_config->fdi_m_n);
6571 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572 intel_crtc->pipe, pipe_config);
6573 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6574 pipe_config->pipe_bpp -= 2*3;
6575 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576 pipe_config->pipe_bpp);
6577 needs_recompute = true;
6578 pipe_config->bw_constrained = true;
6583 if (needs_recompute)
6589 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6590 struct intel_crtc_state *pipe_config)
6592 pipe_config->ips_enabled = i915.enable_ips &&
6593 hsw_crtc_supports_ips(crtc) &&
6594 pipe_config->pipe_bpp <= 24;
6597 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6598 struct intel_crtc_state *pipe_config)
6600 struct drm_device *dev = crtc->base.dev;
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6605 /* FIXME should check pixel clock limits on all platforms */
6606 if (INTEL_INFO(dev)->gen < 4) {
6608 dev_priv->display.get_display_clock_speed(dev);
6611 * Enable pixel doubling when the dot clock
6612 * is > 90% of the (display) core speed.
6614 * GDG double wide on either pipe,
6615 * otherwise pipe A only.
6617 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6618 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6620 pipe_config->double_wide = true;
6623 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6628 * Pipe horizontal size must be even in:
6630 * - LVDS dual channel mode
6631 * - Double wide pipe
6633 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6634 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6635 pipe_config->pipe_src_w &= ~1;
6637 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6638 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6640 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6641 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6645 hsw_compute_ips_config(crtc, pipe_config);
6647 if (pipe_config->has_pch_encoder)
6648 return ironlake_fdi_compute_config(crtc, pipe_config);
6650 /* FIXME: remove below call once atomic mode set is place and all crtc
6651 * related checks called from atomic_crtc_check function */
6653 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6654 crtc, pipe_config->base.state);
6655 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6660 static int skylake_get_display_clock_speed(struct drm_device *dev)
6662 struct drm_i915_private *dev_priv = to_i915(dev);
6663 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6664 uint32_t cdctl = I915_READ(CDCLK_CTL);
6667 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6668 WARN(1, "LCPLL1 not enabled\n");
6669 return 24000; /* 24MHz is the cd freq with NSSC ref */
6672 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6675 linkrate = (I915_READ(DPLL_CTRL1) &
6676 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6678 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6679 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6684 case CDCLK_FREQ_337_308:
6686 case CDCLK_FREQ_675_617:
6689 WARN(1, "Unknown cd freq selection\n");
6693 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6694 case CDCLK_FREQ_450_432:
6696 case CDCLK_FREQ_337_308:
6698 case CDCLK_FREQ_675_617:
6701 WARN(1, "Unknown cd freq selection\n");
6705 /* error case, do as if DPLL0 isn't enabled */
6709 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 uint32_t lcpll = I915_READ(LCPLL_CTL);
6713 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6715 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6717 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6719 else if (freq == LCPLL_CLK_FREQ_450)
6721 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6723 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6729 static int haswell_get_display_clock_speed(struct drm_device *dev)
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 uint32_t lcpll = I915_READ(LCPLL_CTL);
6733 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6735 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6737 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6739 else if (freq == LCPLL_CLK_FREQ_450)
6741 else if (IS_HSW_ULT(dev))
6747 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6749 struct drm_i915_private *dev_priv = dev->dev_private;
6753 if (dev_priv->hpll_freq == 0)
6754 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6756 mutex_lock(&dev_priv->sb_lock);
6757 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6758 mutex_unlock(&dev_priv->sb_lock);
6760 divider = val & DISPLAY_FREQUENCY_VALUES;
6762 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6763 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6764 "cdclk change in progress\n");
6766 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6769 static int ilk_get_display_clock_speed(struct drm_device *dev)
6774 static int i945_get_display_clock_speed(struct drm_device *dev)
6779 static int i915_get_display_clock_speed(struct drm_device *dev)
6784 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6789 static int pnv_get_display_clock_speed(struct drm_device *dev)
6793 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6795 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6798 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6800 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6802 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6805 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6806 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6808 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6813 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6817 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6819 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6822 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6823 case GC_DISPLAY_CLOCK_333_MHZ:
6826 case GC_DISPLAY_CLOCK_190_200_MHZ:
6832 static int i865_get_display_clock_speed(struct drm_device *dev)
6837 static int i855_get_display_clock_speed(struct drm_device *dev)
6840 /* Assume that the hardware is in the high speed state. This
6841 * should be the default.
6843 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6844 case GC_CLOCK_133_200:
6845 case GC_CLOCK_100_200:
6847 case GC_CLOCK_166_250:
6849 case GC_CLOCK_100_133:
6853 /* Shouldn't happen */
6857 static int i830_get_display_clock_speed(struct drm_device *dev)
6863 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6865 while (*num > DATA_LINK_M_N_MASK ||
6866 *den > DATA_LINK_M_N_MASK) {
6872 static void compute_m_n(unsigned int m, unsigned int n,
6873 uint32_t *ret_m, uint32_t *ret_n)
6875 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6876 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6877 intel_reduce_m_n_ratio(ret_m, ret_n);
6881 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6882 int pixel_clock, int link_clock,
6883 struct intel_link_m_n *m_n)
6887 compute_m_n(bits_per_pixel * pixel_clock,
6888 link_clock * nlanes * 8,
6889 &m_n->gmch_m, &m_n->gmch_n);
6891 compute_m_n(pixel_clock, link_clock,
6892 &m_n->link_m, &m_n->link_n);
6895 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6897 if (i915.panel_use_ssc >= 0)
6898 return i915.panel_use_ssc != 0;
6899 return dev_priv->vbt.lvds_use_ssc
6900 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6903 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6906 struct drm_device *dev = crtc_state->base.crtc->dev;
6907 struct drm_i915_private *dev_priv = dev->dev_private;
6910 WARN_ON(!crtc_state->base.state);
6912 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6914 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6915 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6916 refclk = dev_priv->vbt.lvds_ssc_freq;
6917 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6918 } else if (!IS_GEN2(dev)) {
6927 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6929 return (1 << dpll->n) << 16 | dpll->m2;
6932 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6934 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6937 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6938 struct intel_crtc_state *crtc_state,
6939 intel_clock_t *reduced_clock)
6941 struct drm_device *dev = crtc->base.dev;
6944 if (IS_PINEVIEW(dev)) {
6945 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6947 fp2 = pnv_dpll_compute_fp(reduced_clock);
6949 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6951 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6954 crtc_state->dpll_hw_state.fp0 = fp;
6956 crtc->lowfreq_avail = false;
6957 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6959 crtc_state->dpll_hw_state.fp1 = fp2;
6960 crtc->lowfreq_avail = true;
6962 crtc_state->dpll_hw_state.fp1 = fp;
6966 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6972 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6973 * and set it to a reasonable value instead.
6975 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6976 reg_val &= 0xffffff00;
6977 reg_val |= 0x00000030;
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6980 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6981 reg_val &= 0x8cffffff;
6982 reg_val = 0x8c000000;
6983 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6985 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6986 reg_val &= 0xffffff00;
6987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6989 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6990 reg_val &= 0x00ffffff;
6991 reg_val |= 0xb0000000;
6992 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6995 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6996 struct intel_link_m_n *m_n)
6998 struct drm_device *dev = crtc->base.dev;
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 int pipe = crtc->pipe;
7002 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7003 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7004 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7005 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7008 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7009 struct intel_link_m_n *m_n,
7010 struct intel_link_m_n *m2_n2)
7012 struct drm_device *dev = crtc->base.dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 int pipe = crtc->pipe;
7015 enum transcoder transcoder = crtc->config->cpu_transcoder;
7017 if (INTEL_INFO(dev)->gen >= 5) {
7018 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7019 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7020 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7021 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7022 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7023 * for gen < 8) and if DRRS is supported (to make sure the
7024 * registers are not unnecessarily accessed).
7026 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7027 crtc->config->has_drrs) {
7028 I915_WRITE(PIPE_DATA_M2(transcoder),
7029 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7030 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7031 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7032 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7035 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7036 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7037 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7038 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7042 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7044 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7047 dp_m_n = &crtc->config->dp_m_n;
7048 dp_m2_n2 = &crtc->config->dp_m2_n2;
7049 } else if (m_n == M2_N2) {
7052 * M2_N2 registers are not supported. Hence m2_n2 divider value
7053 * needs to be programmed into M1_N1.
7055 dp_m_n = &crtc->config->dp_m2_n2;
7057 DRM_ERROR("Unsupported divider value\n");
7061 if (crtc->config->has_pch_encoder)
7062 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7064 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7067 static void vlv_update_pll(struct intel_crtc *crtc,
7068 struct intel_crtc_state *pipe_config)
7073 * Enable DPIO clock input. We should never disable the reference
7074 * clock for pipe B, since VGA hotplug / manual detection depends
7077 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7078 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7079 /* We should never disable this, set it here for state tracking */
7080 if (crtc->pipe == PIPE_B)
7081 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7082 dpll |= DPLL_VCO_ENABLE;
7083 pipe_config->dpll_hw_state.dpll = dpll;
7085 dpll_md = (pipe_config->pixel_multiplier - 1)
7086 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7087 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7090 static void vlv_prepare_pll(struct intel_crtc *crtc,
7091 const struct intel_crtc_state *pipe_config)
7093 struct drm_device *dev = crtc->base.dev;
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 int pipe = crtc->pipe;
7097 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7098 u32 coreclk, reg_val;
7100 mutex_lock(&dev_priv->sb_lock);
7102 bestn = pipe_config->dpll.n;
7103 bestm1 = pipe_config->dpll.m1;
7104 bestm2 = pipe_config->dpll.m2;
7105 bestp1 = pipe_config->dpll.p1;
7106 bestp2 = pipe_config->dpll.p2;
7108 /* See eDP HDMI DPIO driver vbios notes doc */
7110 /* PLL B needs special handling */
7112 vlv_pllb_recal_opamp(dev_priv, pipe);
7114 /* Set up Tx target for periodic Rcomp update */
7115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7117 /* Disable target IRef on PLL */
7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7119 reg_val &= 0x00ffffff;
7120 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7122 /* Disable fast lock */
7123 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7125 /* Set idtafcrecal before PLL is enabled */
7126 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7127 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7128 mdiv |= ((bestn << DPIO_N_SHIFT));
7129 mdiv |= (1 << DPIO_K_SHIFT);
7132 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7133 * but we don't support that).
7134 * Note: don't use the DAC post divider as it seems unstable.
7136 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7139 mdiv |= DPIO_ENABLE_CALIBRATION;
7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7142 /* Set HBR and RBR LPF coefficients */
7143 if (pipe_config->port_clock == 162000 ||
7144 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7145 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7152 if (pipe_config->has_dp_encoder) {
7153 /* Use SSC source */
7155 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7158 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7160 } else { /* HDMI or VGA */
7161 /* Use bend source */
7163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7170 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7171 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7172 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7173 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7174 coreclk |= 0x01000000;
7175 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7178 mutex_unlock(&dev_priv->sb_lock);
7181 static void chv_update_pll(struct intel_crtc *crtc,
7182 struct intel_crtc_state *pipe_config)
7184 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7185 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7187 if (crtc->pipe != PIPE_A)
7188 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7190 pipe_config->dpll_hw_state.dpll_md =
7191 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7194 static void chv_prepare_pll(struct intel_crtc *crtc,
7195 const struct intel_crtc_state *pipe_config)
7197 struct drm_device *dev = crtc->base.dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 int pipe = crtc->pipe;
7200 int dpll_reg = DPLL(crtc->pipe);
7201 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7202 u32 loopfilter, tribuf_calcntr;
7203 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7207 bestn = pipe_config->dpll.n;
7208 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7209 bestm1 = pipe_config->dpll.m1;
7210 bestm2 = pipe_config->dpll.m2 >> 22;
7211 bestp1 = pipe_config->dpll.p1;
7212 bestp2 = pipe_config->dpll.p2;
7213 vco = pipe_config->dpll.vco;
7218 * Enable Refclk and SSC
7220 I915_WRITE(dpll_reg,
7221 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7223 mutex_lock(&dev_priv->sb_lock);
7225 /* p1 and p2 divider */
7226 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7227 5 << DPIO_CHV_S1_DIV_SHIFT |
7228 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7229 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7230 1 << DPIO_CHV_K_DIV_SHIFT);
7232 /* Feedback post-divider - m2 */
7233 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7235 /* Feedback refclk divider - n and m1 */
7236 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7237 DPIO_CHV_M1_DIV_BY_2 |
7238 1 << DPIO_CHV_N_DIV_SHIFT);
7240 /* M2 fraction division */
7242 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7244 /* M2 fraction division enable */
7245 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7246 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7247 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7249 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7250 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7252 /* Program digital lock detect threshold */
7253 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7254 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7255 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7256 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7258 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7259 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7262 if (vco == 5400000) {
7263 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7264 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7265 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7266 tribuf_calcntr = 0x9;
7267 } else if (vco <= 6200000) {
7268 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7269 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7270 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7271 tribuf_calcntr = 0x9;
7272 } else if (vco <= 6480000) {
7273 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7274 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7275 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7276 tribuf_calcntr = 0x8;
7278 /* Not supported. Apply the same limits as in the max case */
7279 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7280 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7281 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7284 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7286 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7287 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7288 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7289 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7292 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7293 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7296 mutex_unlock(&dev_priv->sb_lock);
7300 * vlv_force_pll_on - forcibly enable just the PLL
7301 * @dev_priv: i915 private structure
7302 * @pipe: pipe PLL to enable
7303 * @dpll: PLL configuration
7305 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7306 * in cases where we need the PLL enabled even when @pipe is not going to
7309 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7310 const struct dpll *dpll)
7312 struct intel_crtc *crtc =
7313 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7314 struct intel_crtc_state pipe_config = {
7315 .base.crtc = &crtc->base,
7316 .pixel_multiplier = 1,
7320 if (IS_CHERRYVIEW(dev)) {
7321 chv_update_pll(crtc, &pipe_config);
7322 chv_prepare_pll(crtc, &pipe_config);
7323 chv_enable_pll(crtc, &pipe_config);
7325 vlv_update_pll(crtc, &pipe_config);
7326 vlv_prepare_pll(crtc, &pipe_config);
7327 vlv_enable_pll(crtc, &pipe_config);
7332 * vlv_force_pll_off - forcibly disable just the PLL
7333 * @dev_priv: i915 private structure
7334 * @pipe: pipe PLL to disable
7336 * Disable the PLL for @pipe. To be used in cases where we need
7337 * the PLL enabled even when @pipe is not going to be enabled.
7339 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7341 if (IS_CHERRYVIEW(dev))
7342 chv_disable_pll(to_i915(dev), pipe);
7344 vlv_disable_pll(to_i915(dev), pipe);
7347 static void i9xx_update_pll(struct intel_crtc *crtc,
7348 struct intel_crtc_state *crtc_state,
7349 intel_clock_t *reduced_clock,
7352 struct drm_device *dev = crtc->base.dev;
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct dpll *clock = &crtc_state->dpll;
7358 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7360 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7361 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7363 dpll = DPLL_VGA_MODE_DIS;
7365 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7366 dpll |= DPLLB_MODE_LVDS;
7368 dpll |= DPLLB_MODE_DAC_SERIAL;
7370 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7371 dpll |= (crtc_state->pixel_multiplier - 1)
7372 << SDVO_MULTIPLIER_SHIFT_HIRES;
7376 dpll |= DPLL_SDVO_HIGH_SPEED;
7378 if (crtc_state->has_dp_encoder)
7379 dpll |= DPLL_SDVO_HIGH_SPEED;
7381 /* compute bitmask from p1 value */
7382 if (IS_PINEVIEW(dev))
7383 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7385 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7386 if (IS_G4X(dev) && reduced_clock)
7387 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7389 switch (clock->p2) {
7391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7403 if (INTEL_INFO(dev)->gen >= 4)
7404 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7406 if (crtc_state->sdvo_tv_clock)
7407 dpll |= PLL_REF_INPUT_TVCLKINBC;
7408 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7409 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7410 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7412 dpll |= PLL_REF_INPUT_DREFCLK;
7414 dpll |= DPLL_VCO_ENABLE;
7415 crtc_state->dpll_hw_state.dpll = dpll;
7417 if (INTEL_INFO(dev)->gen >= 4) {
7418 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7419 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7420 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7424 static void i8xx_update_pll(struct intel_crtc *crtc,
7425 struct intel_crtc_state *crtc_state,
7426 intel_clock_t *reduced_clock,
7429 struct drm_device *dev = crtc->base.dev;
7430 struct drm_i915_private *dev_priv = dev->dev_private;
7432 struct dpll *clock = &crtc_state->dpll;
7434 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7436 dpll = DPLL_VGA_MODE_DIS;
7438 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7439 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7442 dpll |= PLL_P1_DIVIDE_BY_TWO;
7444 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7446 dpll |= PLL_P2_DIVIDE_BY_4;
7449 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7450 dpll |= DPLL_DVO_2X_MODE;
7452 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7456 dpll |= PLL_REF_INPUT_DREFCLK;
7458 dpll |= DPLL_VCO_ENABLE;
7459 crtc_state->dpll_hw_state.dpll = dpll;
7462 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7464 struct drm_device *dev = intel_crtc->base.dev;
7465 struct drm_i915_private *dev_priv = dev->dev_private;
7466 enum pipe pipe = intel_crtc->pipe;
7467 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7468 struct drm_display_mode *adjusted_mode =
7469 &intel_crtc->config->base.adjusted_mode;
7470 uint32_t crtc_vtotal, crtc_vblank_end;
7473 /* We need to be careful not to changed the adjusted mode, for otherwise
7474 * the hw state checker will get angry at the mismatch. */
7475 crtc_vtotal = adjusted_mode->crtc_vtotal;
7476 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7478 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7479 /* the chip adds 2 halflines automatically */
7481 crtc_vblank_end -= 1;
7483 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7484 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7486 vsyncshift = adjusted_mode->crtc_hsync_start -
7487 adjusted_mode->crtc_htotal / 2;
7489 vsyncshift += adjusted_mode->crtc_htotal;
7492 if (INTEL_INFO(dev)->gen > 3)
7493 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7495 I915_WRITE(HTOTAL(cpu_transcoder),
7496 (adjusted_mode->crtc_hdisplay - 1) |
7497 ((adjusted_mode->crtc_htotal - 1) << 16));
7498 I915_WRITE(HBLANK(cpu_transcoder),
7499 (adjusted_mode->crtc_hblank_start - 1) |
7500 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7501 I915_WRITE(HSYNC(cpu_transcoder),
7502 (adjusted_mode->crtc_hsync_start - 1) |
7503 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7505 I915_WRITE(VTOTAL(cpu_transcoder),
7506 (adjusted_mode->crtc_vdisplay - 1) |
7507 ((crtc_vtotal - 1) << 16));
7508 I915_WRITE(VBLANK(cpu_transcoder),
7509 (adjusted_mode->crtc_vblank_start - 1) |
7510 ((crtc_vblank_end - 1) << 16));
7511 I915_WRITE(VSYNC(cpu_transcoder),
7512 (adjusted_mode->crtc_vsync_start - 1) |
7513 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7515 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7516 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7517 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7519 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7520 (pipe == PIPE_B || pipe == PIPE_C))
7521 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7523 /* pipesrc controls the size that is scaled from, which should
7524 * always be the user's requested size.
7526 I915_WRITE(PIPESRC(pipe),
7527 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7528 (intel_crtc->config->pipe_src_h - 1));
7531 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7532 struct intel_crtc_state *pipe_config)
7534 struct drm_device *dev = crtc->base.dev;
7535 struct drm_i915_private *dev_priv = dev->dev_private;
7536 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7539 tmp = I915_READ(HTOTAL(cpu_transcoder));
7540 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7541 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7542 tmp = I915_READ(HBLANK(cpu_transcoder));
7543 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7544 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7545 tmp = I915_READ(HSYNC(cpu_transcoder));
7546 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7547 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7549 tmp = I915_READ(VTOTAL(cpu_transcoder));
7550 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7551 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7552 tmp = I915_READ(VBLANK(cpu_transcoder));
7553 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7554 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7555 tmp = I915_READ(VSYNC(cpu_transcoder));
7556 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7557 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7559 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7560 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7561 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7562 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7565 tmp = I915_READ(PIPESRC(crtc->pipe));
7566 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7567 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7569 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7570 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7573 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7574 struct intel_crtc_state *pipe_config)
7576 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7577 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7578 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7579 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7581 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7582 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7583 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7584 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7586 mode->flags = pipe_config->base.adjusted_mode.flags;
7588 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7589 mode->flags |= pipe_config->base.adjusted_mode.flags;
7592 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7594 struct drm_device *dev = intel_crtc->base.dev;
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7600 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7601 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7602 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7604 if (intel_crtc->config->double_wide)
7605 pipeconf |= PIPECONF_DOUBLE_WIDE;
7607 /* only g4x and later have fancy bpc/dither controls */
7608 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7609 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7610 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7611 pipeconf |= PIPECONF_DITHER_EN |
7612 PIPECONF_DITHER_TYPE_SP;
7614 switch (intel_crtc->config->pipe_bpp) {
7616 pipeconf |= PIPECONF_6BPC;
7619 pipeconf |= PIPECONF_8BPC;
7622 pipeconf |= PIPECONF_10BPC;
7625 /* Case prevented by intel_choose_pipe_bpp_dither. */
7630 if (HAS_PIPE_CXSR(dev)) {
7631 if (intel_crtc->lowfreq_avail) {
7632 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7633 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7635 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7639 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7640 if (INTEL_INFO(dev)->gen < 4 ||
7641 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7642 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7644 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7646 pipeconf |= PIPECONF_PROGRESSIVE;
7648 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7649 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7651 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7652 POSTING_READ(PIPECONF(intel_crtc->pipe));
7655 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7656 struct intel_crtc_state *crtc_state)
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 int refclk, num_connectors = 0;
7661 intel_clock_t clock, reduced_clock;
7662 bool ok, has_reduced_clock = false;
7663 bool is_lvds = false, is_dsi = false;
7664 struct intel_encoder *encoder;
7665 const intel_limit_t *limit;
7666 struct drm_atomic_state *state = crtc_state->base.state;
7667 struct drm_connector *connector;
7668 struct drm_connector_state *connector_state;
7671 memset(&crtc_state->dpll_hw_state, 0,
7672 sizeof(crtc_state->dpll_hw_state));
7674 for_each_connector_in_state(state, connector, connector_state, i) {
7675 if (connector_state->crtc != &crtc->base)
7678 encoder = to_intel_encoder(connector_state->best_encoder);
7680 switch (encoder->type) {
7681 case INTEL_OUTPUT_LVDS:
7684 case INTEL_OUTPUT_DSI:
7697 if (!crtc_state->clock_set) {
7698 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7701 * Returns a set of divisors for the desired target clock with
7702 * the given refclk, or FALSE. The returned values represent
7703 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7706 limit = intel_limit(crtc_state, refclk);
7707 ok = dev_priv->display.find_dpll(limit, crtc_state,
7708 crtc_state->port_clock,
7709 refclk, NULL, &clock);
7711 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7715 if (is_lvds && dev_priv->lvds_downclock_avail) {
7717 * Ensure we match the reduced clock's P to the target
7718 * clock. If the clocks don't match, we can't switch
7719 * the display clock by using the FP0/FP1. In such case
7720 * we will disable the LVDS downclock feature.
7723 dev_priv->display.find_dpll(limit, crtc_state,
7724 dev_priv->lvds_downclock,
7728 /* Compat-code for transition, will disappear. */
7729 crtc_state->dpll.n = clock.n;
7730 crtc_state->dpll.m1 = clock.m1;
7731 crtc_state->dpll.m2 = clock.m2;
7732 crtc_state->dpll.p1 = clock.p1;
7733 crtc_state->dpll.p2 = clock.p2;
7737 i8xx_update_pll(crtc, crtc_state,
7738 has_reduced_clock ? &reduced_clock : NULL,
7740 } else if (IS_CHERRYVIEW(dev)) {
7741 chv_update_pll(crtc, crtc_state);
7742 } else if (IS_VALLEYVIEW(dev)) {
7743 vlv_update_pll(crtc, crtc_state);
7745 i9xx_update_pll(crtc, crtc_state,
7746 has_reduced_clock ? &reduced_clock : NULL,
7753 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7754 struct intel_crtc_state *pipe_config)
7756 struct drm_device *dev = crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7760 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7763 tmp = I915_READ(PFIT_CONTROL);
7764 if (!(tmp & PFIT_ENABLE))
7767 /* Check whether the pfit is attached to our pipe. */
7768 if (INTEL_INFO(dev)->gen < 4) {
7769 if (crtc->pipe != PIPE_B)
7772 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7776 pipe_config->gmch_pfit.control = tmp;
7777 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7778 if (INTEL_INFO(dev)->gen < 5)
7779 pipe_config->gmch_pfit.lvds_border_bits =
7780 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7783 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7784 struct intel_crtc_state *pipe_config)
7786 struct drm_device *dev = crtc->base.dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7788 int pipe = pipe_config->cpu_transcoder;
7789 intel_clock_t clock;
7791 int refclk = 100000;
7793 /* In case of MIPI DPLL will not even be used */
7794 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7797 mutex_lock(&dev_priv->sb_lock);
7798 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7799 mutex_unlock(&dev_priv->sb_lock);
7801 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7802 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7803 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7804 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7805 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7807 vlv_clock(refclk, &clock);
7809 /* clock.dot is the fast clock */
7810 pipe_config->port_clock = clock.dot / 5;
7814 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7815 struct intel_initial_plane_config *plane_config)
7817 struct drm_device *dev = crtc->base.dev;
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819 u32 val, base, offset;
7820 int pipe = crtc->pipe, plane = crtc->plane;
7821 int fourcc, pixel_format;
7822 unsigned int aligned_height;
7823 struct drm_framebuffer *fb;
7824 struct intel_framebuffer *intel_fb;
7826 val = I915_READ(DSPCNTR(plane));
7827 if (!(val & DISPLAY_PLANE_ENABLE))
7830 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7832 DRM_DEBUG_KMS("failed to alloc fb\n");
7836 fb = &intel_fb->base;
7838 if (INTEL_INFO(dev)->gen >= 4) {
7839 if (val & DISPPLANE_TILED) {
7840 plane_config->tiling = I915_TILING_X;
7841 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7845 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7846 fourcc = i9xx_format_to_fourcc(pixel_format);
7847 fb->pixel_format = fourcc;
7848 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7850 if (INTEL_INFO(dev)->gen >= 4) {
7851 if (plane_config->tiling)
7852 offset = I915_READ(DSPTILEOFF(plane));
7854 offset = I915_READ(DSPLINOFF(plane));
7855 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7857 base = I915_READ(DSPADDR(plane));
7859 plane_config->base = base;
7861 val = I915_READ(PIPESRC(pipe));
7862 fb->width = ((val >> 16) & 0xfff) + 1;
7863 fb->height = ((val >> 0) & 0xfff) + 1;
7865 val = I915_READ(DSPSTRIDE(pipe));
7866 fb->pitches[0] = val & 0xffffffc0;
7868 aligned_height = intel_fb_align_height(dev, fb->height,
7872 plane_config->size = fb->pitches[0] * aligned_height;
7874 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7875 pipe_name(pipe), plane, fb->width, fb->height,
7876 fb->bits_per_pixel, base, fb->pitches[0],
7877 plane_config->size);
7879 plane_config->fb = intel_fb;
7882 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7883 struct intel_crtc_state *pipe_config)
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 int pipe = pipe_config->cpu_transcoder;
7888 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7889 intel_clock_t clock;
7890 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7891 int refclk = 100000;
7893 mutex_lock(&dev_priv->sb_lock);
7894 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7895 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7896 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7897 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7898 mutex_unlock(&dev_priv->sb_lock);
7900 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7901 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7902 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7903 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7904 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7906 chv_clock(refclk, &clock);
7908 /* clock.dot is the fast clock */
7909 pipe_config->port_clock = clock.dot / 5;
7912 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7913 struct intel_crtc_state *pipe_config)
7915 struct drm_device *dev = crtc->base.dev;
7916 struct drm_i915_private *dev_priv = dev->dev_private;
7919 if (!intel_display_power_is_enabled(dev_priv,
7920 POWER_DOMAIN_PIPE(crtc->pipe)))
7923 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7924 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7926 tmp = I915_READ(PIPECONF(crtc->pipe));
7927 if (!(tmp & PIPECONF_ENABLE))
7930 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7931 switch (tmp & PIPECONF_BPC_MASK) {
7933 pipe_config->pipe_bpp = 18;
7936 pipe_config->pipe_bpp = 24;
7938 case PIPECONF_10BPC:
7939 pipe_config->pipe_bpp = 30;
7946 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7947 pipe_config->limited_color_range = true;
7949 if (INTEL_INFO(dev)->gen < 4)
7950 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7952 intel_get_pipe_timings(crtc, pipe_config);
7954 i9xx_get_pfit_config(crtc, pipe_config);
7956 if (INTEL_INFO(dev)->gen >= 4) {
7957 tmp = I915_READ(DPLL_MD(crtc->pipe));
7958 pipe_config->pixel_multiplier =
7959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7961 pipe_config->dpll_hw_state.dpll_md = tmp;
7962 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7963 tmp = I915_READ(DPLL(crtc->pipe));
7964 pipe_config->pixel_multiplier =
7965 ((tmp & SDVO_MULTIPLIER_MASK)
7966 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7968 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7969 * port and will be fixed up in the encoder->get_config
7971 pipe_config->pixel_multiplier = 1;
7973 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7974 if (!IS_VALLEYVIEW(dev)) {
7976 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7977 * on 830. Filter it out here so that we don't
7978 * report errors due to that.
7981 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7983 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7984 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7986 /* Mask out read-only status bits. */
7987 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7988 DPLL_PORTC_READY_MASK |
7989 DPLL_PORTB_READY_MASK);
7992 if (IS_CHERRYVIEW(dev))
7993 chv_crtc_clock_get(crtc, pipe_config);
7994 else if (IS_VALLEYVIEW(dev))
7995 vlv_crtc_clock_get(crtc, pipe_config);
7997 i9xx_crtc_clock_get(crtc, pipe_config);
8002 static void ironlake_init_pch_refclk(struct drm_device *dev)
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005 struct intel_encoder *encoder;
8007 bool has_lvds = false;
8008 bool has_cpu_edp = false;
8009 bool has_panel = false;
8010 bool has_ck505 = false;
8011 bool can_ssc = false;
8013 /* We need to take the global config into account */
8014 for_each_intel_encoder(dev, encoder) {
8015 switch (encoder->type) {
8016 case INTEL_OUTPUT_LVDS:
8020 case INTEL_OUTPUT_EDP:
8022 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8030 if (HAS_PCH_IBX(dev)) {
8031 has_ck505 = dev_priv->vbt.display_clock_mode;
8032 can_ssc = has_ck505;
8038 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8039 has_panel, has_lvds, has_ck505);
8041 /* Ironlake: try to setup display ref clock before DPLL
8042 * enabling. This is only under driver's control after
8043 * PCH B stepping, previous chipset stepping should be
8044 * ignoring this setting.
8046 val = I915_READ(PCH_DREF_CONTROL);
8048 /* As we must carefully and slowly disable/enable each source in turn,
8049 * compute the final state we want first and check if we need to
8050 * make any changes at all.
8053 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8055 final |= DREF_NONSPREAD_CK505_ENABLE;
8057 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8059 final &= ~DREF_SSC_SOURCE_MASK;
8060 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8061 final &= ~DREF_SSC1_ENABLE;
8064 final |= DREF_SSC_SOURCE_ENABLE;
8066 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8067 final |= DREF_SSC1_ENABLE;
8070 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8071 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8073 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8075 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8077 final |= DREF_SSC_SOURCE_DISABLE;
8078 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8084 /* Always enable nonspread source */
8085 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8088 val |= DREF_NONSPREAD_CK505_ENABLE;
8090 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8093 val &= ~DREF_SSC_SOURCE_MASK;
8094 val |= DREF_SSC_SOURCE_ENABLE;
8096 /* SSC must be turned on before enabling the CPU output */
8097 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8098 DRM_DEBUG_KMS("Using SSC on panel\n");
8099 val |= DREF_SSC1_ENABLE;
8101 val &= ~DREF_SSC1_ENABLE;
8103 /* Get SSC going before enabling the outputs */
8104 I915_WRITE(PCH_DREF_CONTROL, val);
8105 POSTING_READ(PCH_DREF_CONTROL);
8108 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8110 /* Enable CPU source on CPU attached eDP */
8112 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8113 DRM_DEBUG_KMS("Using SSC on eDP\n");
8114 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8116 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8118 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8120 I915_WRITE(PCH_DREF_CONTROL, val);
8121 POSTING_READ(PCH_DREF_CONTROL);
8124 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8126 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8128 /* Turn off CPU output */
8129 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8131 I915_WRITE(PCH_DREF_CONTROL, val);
8132 POSTING_READ(PCH_DREF_CONTROL);
8135 /* Turn off the SSC source */
8136 val &= ~DREF_SSC_SOURCE_MASK;
8137 val |= DREF_SSC_SOURCE_DISABLE;
8140 val &= ~DREF_SSC1_ENABLE;
8142 I915_WRITE(PCH_DREF_CONTROL, val);
8143 POSTING_READ(PCH_DREF_CONTROL);
8147 BUG_ON(val != final);
8150 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8154 tmp = I915_READ(SOUTH_CHICKEN2);
8155 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8156 I915_WRITE(SOUTH_CHICKEN2, tmp);
8158 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8159 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8160 DRM_ERROR("FDI mPHY reset assert timeout\n");
8162 tmp = I915_READ(SOUTH_CHICKEN2);
8163 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8164 I915_WRITE(SOUTH_CHICKEN2, tmp);
8166 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8167 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8168 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8171 /* WaMPhyProgramming:hsw */
8172 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8176 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8177 tmp &= ~(0xFF << 24);
8178 tmp |= (0x12 << 24);
8179 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8181 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8183 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8185 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8187 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8189 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8190 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8191 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8193 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8194 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8195 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8197 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8200 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8202 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8205 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8207 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8210 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8212 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8215 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8217 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8218 tmp &= ~(0xFF << 16);
8219 tmp |= (0x1C << 16);
8220 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8222 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8223 tmp &= ~(0xFF << 16);
8224 tmp |= (0x1C << 16);
8225 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8227 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8229 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8231 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8233 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8235 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8236 tmp &= ~(0xF << 28);
8238 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8240 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8241 tmp &= ~(0xF << 28);
8243 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8246 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8247 * Programming" based on the parameters passed:
8248 * - Sequence to enable CLKOUT_DP
8249 * - Sequence to enable CLKOUT_DP without spread
8250 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8252 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8255 struct drm_i915_private *dev_priv = dev->dev_private;
8258 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8260 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8261 with_fdi, "LP PCH doesn't have FDI\n"))
8264 mutex_lock(&dev_priv->sb_lock);
8266 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8267 tmp &= ~SBI_SSCCTL_DISABLE;
8268 tmp |= SBI_SSCCTL_PATHALT;
8269 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8274 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8275 tmp &= ~SBI_SSCCTL_PATHALT;
8276 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8279 lpt_reset_fdi_mphy(dev_priv);
8280 lpt_program_fdi_mphy(dev_priv);
8284 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8285 SBI_GEN0 : SBI_DBUFF0;
8286 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8287 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8288 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8290 mutex_unlock(&dev_priv->sb_lock);
8293 /* Sequence to disable CLKOUT_DP */
8294 static void lpt_disable_clkout_dp(struct drm_device *dev)
8296 struct drm_i915_private *dev_priv = dev->dev_private;
8299 mutex_lock(&dev_priv->sb_lock);
8301 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8302 SBI_GEN0 : SBI_DBUFF0;
8303 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8304 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8305 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8307 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8308 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8309 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8310 tmp |= SBI_SSCCTL_PATHALT;
8311 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8314 tmp |= SBI_SSCCTL_DISABLE;
8315 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8318 mutex_unlock(&dev_priv->sb_lock);
8321 static void lpt_init_pch_refclk(struct drm_device *dev)
8323 struct intel_encoder *encoder;
8324 bool has_vga = false;
8326 for_each_intel_encoder(dev, encoder) {
8327 switch (encoder->type) {
8328 case INTEL_OUTPUT_ANALOG:
8337 lpt_enable_clkout_dp(dev, true, true);
8339 lpt_disable_clkout_dp(dev);
8343 * Initialize reference clocks when the driver loads
8345 void intel_init_pch_refclk(struct drm_device *dev)
8347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8348 ironlake_init_pch_refclk(dev);
8349 else if (HAS_PCH_LPT(dev))
8350 lpt_init_pch_refclk(dev);
8353 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8355 struct drm_device *dev = crtc_state->base.crtc->dev;
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8357 struct drm_atomic_state *state = crtc_state->base.state;
8358 struct drm_connector *connector;
8359 struct drm_connector_state *connector_state;
8360 struct intel_encoder *encoder;
8361 int num_connectors = 0, i;
8362 bool is_lvds = false;
8364 for_each_connector_in_state(state, connector, connector_state, i) {
8365 if (connector_state->crtc != crtc_state->base.crtc)
8368 encoder = to_intel_encoder(connector_state->best_encoder);
8370 switch (encoder->type) {
8371 case INTEL_OUTPUT_LVDS:
8380 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8381 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8382 dev_priv->vbt.lvds_ssc_freq);
8383 return dev_priv->vbt.lvds_ssc_freq;
8389 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8391 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8393 int pipe = intel_crtc->pipe;
8398 switch (intel_crtc->config->pipe_bpp) {
8400 val |= PIPECONF_6BPC;
8403 val |= PIPECONF_8BPC;
8406 val |= PIPECONF_10BPC;
8409 val |= PIPECONF_12BPC;
8412 /* Case prevented by intel_choose_pipe_bpp_dither. */
8416 if (intel_crtc->config->dither)
8417 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8419 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8420 val |= PIPECONF_INTERLACED_ILK;
8422 val |= PIPECONF_PROGRESSIVE;
8424 if (intel_crtc->config->limited_color_range)
8425 val |= PIPECONF_COLOR_RANGE_SELECT;
8427 I915_WRITE(PIPECONF(pipe), val);
8428 POSTING_READ(PIPECONF(pipe));
8432 * Set up the pipe CSC unit.
8434 * Currently only full range RGB to limited range RGB conversion
8435 * is supported, but eventually this should handle various
8436 * RGB<->YCbCr scenarios as well.
8438 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8440 struct drm_device *dev = crtc->dev;
8441 struct drm_i915_private *dev_priv = dev->dev_private;
8442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8443 int pipe = intel_crtc->pipe;
8444 uint16_t coeff = 0x7800; /* 1.0 */
8447 * TODO: Check what kind of values actually come out of the pipe
8448 * with these coeff/postoff values and adjust to get the best
8449 * accuracy. Perhaps we even need to take the bpc value into
8453 if (intel_crtc->config->limited_color_range)
8454 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8457 * GY/GU and RY/RU should be the other way around according
8458 * to BSpec, but reality doesn't agree. Just set them up in
8459 * a way that results in the correct picture.
8461 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8462 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8464 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8465 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8467 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8468 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8470 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8471 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8472 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8474 if (INTEL_INFO(dev)->gen > 6) {
8475 uint16_t postoff = 0;
8477 if (intel_crtc->config->limited_color_range)
8478 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8480 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8481 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8482 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8484 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8486 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8488 if (intel_crtc->config->limited_color_range)
8489 mode |= CSC_BLACK_SCREEN_OFFSET;
8491 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8495 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8497 struct drm_device *dev = crtc->dev;
8498 struct drm_i915_private *dev_priv = dev->dev_private;
8499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8500 enum pipe pipe = intel_crtc->pipe;
8501 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8506 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8507 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8509 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8510 val |= PIPECONF_INTERLACED_ILK;
8512 val |= PIPECONF_PROGRESSIVE;
8514 I915_WRITE(PIPECONF(cpu_transcoder), val);
8515 POSTING_READ(PIPECONF(cpu_transcoder));
8517 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8518 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8520 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8523 switch (intel_crtc->config->pipe_bpp) {
8525 val |= PIPEMISC_DITHER_6_BPC;
8528 val |= PIPEMISC_DITHER_8_BPC;
8531 val |= PIPEMISC_DITHER_10_BPC;
8534 val |= PIPEMISC_DITHER_12_BPC;
8537 /* Case prevented by pipe_config_set_bpp. */
8541 if (intel_crtc->config->dither)
8542 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8544 I915_WRITE(PIPEMISC(pipe), val);
8548 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8549 struct intel_crtc_state *crtc_state,
8550 intel_clock_t *clock,
8551 bool *has_reduced_clock,
8552 intel_clock_t *reduced_clock)
8554 struct drm_device *dev = crtc->dev;
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8557 const intel_limit_t *limit;
8558 bool ret, is_lvds = false;
8560 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8562 refclk = ironlake_get_refclk(crtc_state);
8565 * Returns a set of divisors for the desired target clock with the given
8566 * refclk, or FALSE. The returned values represent the clock equation:
8567 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8569 limit = intel_limit(crtc_state, refclk);
8570 ret = dev_priv->display.find_dpll(limit, crtc_state,
8571 crtc_state->port_clock,
8572 refclk, NULL, clock);
8576 if (is_lvds && dev_priv->lvds_downclock_avail) {
8578 * Ensure we match the reduced clock's P to the target clock.
8579 * If the clocks don't match, we can't switch the display clock
8580 * by using the FP0/FP1. In such case we will disable the LVDS
8581 * downclock feature.
8583 *has_reduced_clock =
8584 dev_priv->display.find_dpll(limit, crtc_state,
8585 dev_priv->lvds_downclock,
8593 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8596 * Account for spread spectrum to avoid
8597 * oversubscribing the link. Max center spread
8598 * is 2.5%; use 5% for safety's sake.
8600 u32 bps = target_clock * bpp * 21 / 20;
8601 return DIV_ROUND_UP(bps, link_bw * 8);
8604 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8606 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8609 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8610 struct intel_crtc_state *crtc_state,
8612 intel_clock_t *reduced_clock, u32 *fp2)
8614 struct drm_crtc *crtc = &intel_crtc->base;
8615 struct drm_device *dev = crtc->dev;
8616 struct drm_i915_private *dev_priv = dev->dev_private;
8617 struct drm_atomic_state *state = crtc_state->base.state;
8618 struct drm_connector *connector;
8619 struct drm_connector_state *connector_state;
8620 struct intel_encoder *encoder;
8622 int factor, num_connectors = 0, i;
8623 bool is_lvds = false, is_sdvo = false;
8625 for_each_connector_in_state(state, connector, connector_state, i) {
8626 if (connector_state->crtc != crtc_state->base.crtc)
8629 encoder = to_intel_encoder(connector_state->best_encoder);
8631 switch (encoder->type) {
8632 case INTEL_OUTPUT_LVDS:
8635 case INTEL_OUTPUT_SDVO:
8636 case INTEL_OUTPUT_HDMI:
8646 /* Enable autotuning of the PLL clock (if permissible) */
8649 if ((intel_panel_use_ssc(dev_priv) &&
8650 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8651 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8653 } else if (crtc_state->sdvo_tv_clock)
8656 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8659 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8665 dpll |= DPLLB_MODE_LVDS;
8667 dpll |= DPLLB_MODE_DAC_SERIAL;
8669 dpll |= (crtc_state->pixel_multiplier - 1)
8670 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8673 dpll |= DPLL_SDVO_HIGH_SPEED;
8674 if (crtc_state->has_dp_encoder)
8675 dpll |= DPLL_SDVO_HIGH_SPEED;
8677 /* compute bitmask from p1 value */
8678 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8680 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8682 switch (crtc_state->dpll.p2) {
8684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8690 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8693 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8697 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8700 dpll |= PLL_REF_INPUT_DREFCLK;
8702 return dpll | DPLL_VCO_ENABLE;
8705 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8706 struct intel_crtc_state *crtc_state)
8708 struct drm_device *dev = crtc->base.dev;
8709 intel_clock_t clock, reduced_clock;
8710 u32 dpll = 0, fp = 0, fp2 = 0;
8711 bool ok, has_reduced_clock = false;
8712 bool is_lvds = false;
8713 struct intel_shared_dpll *pll;
8715 memset(&crtc_state->dpll_hw_state, 0,
8716 sizeof(crtc_state->dpll_hw_state));
8718 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8720 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8721 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8723 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8724 &has_reduced_clock, &reduced_clock);
8725 if (!ok && !crtc_state->clock_set) {
8726 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8729 /* Compat-code for transition, will disappear. */
8730 if (!crtc_state->clock_set) {
8731 crtc_state->dpll.n = clock.n;
8732 crtc_state->dpll.m1 = clock.m1;
8733 crtc_state->dpll.m2 = clock.m2;
8734 crtc_state->dpll.p1 = clock.p1;
8735 crtc_state->dpll.p2 = clock.p2;
8738 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8739 if (crtc_state->has_pch_encoder) {
8740 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8741 if (has_reduced_clock)
8742 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8744 dpll = ironlake_compute_dpll(crtc, crtc_state,
8745 &fp, &reduced_clock,
8746 has_reduced_clock ? &fp2 : NULL);
8748 crtc_state->dpll_hw_state.dpll = dpll;
8749 crtc_state->dpll_hw_state.fp0 = fp;
8750 if (has_reduced_clock)
8751 crtc_state->dpll_hw_state.fp1 = fp2;
8753 crtc_state->dpll_hw_state.fp1 = fp;
8755 pll = intel_get_shared_dpll(crtc, crtc_state);
8757 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8758 pipe_name(crtc->pipe));
8763 if (is_lvds && has_reduced_clock)
8764 crtc->lowfreq_avail = true;
8766 crtc->lowfreq_avail = false;
8771 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8772 struct intel_link_m_n *m_n)
8774 struct drm_device *dev = crtc->base.dev;
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 enum pipe pipe = crtc->pipe;
8778 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8779 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8780 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8782 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8783 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8784 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8787 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8788 enum transcoder transcoder,
8789 struct intel_link_m_n *m_n,
8790 struct intel_link_m_n *m2_n2)
8792 struct drm_device *dev = crtc->base.dev;
8793 struct drm_i915_private *dev_priv = dev->dev_private;
8794 enum pipe pipe = crtc->pipe;
8796 if (INTEL_INFO(dev)->gen >= 5) {
8797 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8798 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8799 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8801 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8802 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8803 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8804 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8805 * gen < 8) and if DRRS is supported (to make sure the
8806 * registers are not unnecessarily read).
8808 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8809 crtc->config->has_drrs) {
8810 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8811 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8812 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8814 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8815 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8816 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8819 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8820 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8821 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8823 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8824 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8825 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8829 void intel_dp_get_m_n(struct intel_crtc *crtc,
8830 struct intel_crtc_state *pipe_config)
8832 if (pipe_config->has_pch_encoder)
8833 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8835 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8836 &pipe_config->dp_m_n,
8837 &pipe_config->dp_m2_n2);
8840 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8841 struct intel_crtc_state *pipe_config)
8843 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8844 &pipe_config->fdi_m_n, NULL);
8847 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8848 struct intel_crtc_state *pipe_config)
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8852 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8853 uint32_t ps_ctrl = 0;
8857 /* find scaler attached to this pipe */
8858 for (i = 0; i < crtc->num_scalers; i++) {
8859 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8860 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8862 pipe_config->pch_pfit.enabled = true;
8863 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8864 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8869 scaler_state->scaler_id = id;
8871 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8873 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8878 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8879 struct intel_initial_plane_config *plane_config)
8881 struct drm_device *dev = crtc->base.dev;
8882 struct drm_i915_private *dev_priv = dev->dev_private;
8883 u32 val, base, offset, stride_mult, tiling;
8884 int pipe = crtc->pipe;
8885 int fourcc, pixel_format;
8886 unsigned int aligned_height;
8887 struct drm_framebuffer *fb;
8888 struct intel_framebuffer *intel_fb;
8890 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8892 DRM_DEBUG_KMS("failed to alloc fb\n");
8896 fb = &intel_fb->base;
8898 val = I915_READ(PLANE_CTL(pipe, 0));
8899 if (!(val & PLANE_CTL_ENABLE))
8902 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8903 fourcc = skl_format_to_fourcc(pixel_format,
8904 val & PLANE_CTL_ORDER_RGBX,
8905 val & PLANE_CTL_ALPHA_MASK);
8906 fb->pixel_format = fourcc;
8907 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8909 tiling = val & PLANE_CTL_TILED_MASK;
8911 case PLANE_CTL_TILED_LINEAR:
8912 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8914 case PLANE_CTL_TILED_X:
8915 plane_config->tiling = I915_TILING_X;
8916 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8918 case PLANE_CTL_TILED_Y:
8919 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8921 case PLANE_CTL_TILED_YF:
8922 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8925 MISSING_CASE(tiling);
8929 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8930 plane_config->base = base;
8932 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8934 val = I915_READ(PLANE_SIZE(pipe, 0));
8935 fb->height = ((val >> 16) & 0xfff) + 1;
8936 fb->width = ((val >> 0) & 0x1fff) + 1;
8938 val = I915_READ(PLANE_STRIDE(pipe, 0));
8939 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8941 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8943 aligned_height = intel_fb_align_height(dev, fb->height,
8947 plane_config->size = fb->pitches[0] * aligned_height;
8949 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8950 pipe_name(pipe), fb->width, fb->height,
8951 fb->bits_per_pixel, base, fb->pitches[0],
8952 plane_config->size);
8954 plane_config->fb = intel_fb;
8961 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8962 struct intel_crtc_state *pipe_config)
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
8968 tmp = I915_READ(PF_CTL(crtc->pipe));
8970 if (tmp & PF_ENABLE) {
8971 pipe_config->pch_pfit.enabled = true;
8972 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8973 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8975 /* We currently do not free assignements of panel fitters on
8976 * ivb/hsw (since we don't use the higher upscaling modes which
8977 * differentiates them) so just WARN about this case for now. */
8979 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8980 PF_PIPE_SEL_IVB(crtc->pipe));
8986 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8987 struct intel_initial_plane_config *plane_config)
8989 struct drm_device *dev = crtc->base.dev;
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991 u32 val, base, offset;
8992 int pipe = crtc->pipe;
8993 int fourcc, pixel_format;
8994 unsigned int aligned_height;
8995 struct drm_framebuffer *fb;
8996 struct intel_framebuffer *intel_fb;
8998 val = I915_READ(DSPCNTR(pipe));
8999 if (!(val & DISPLAY_PLANE_ENABLE))
9002 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9004 DRM_DEBUG_KMS("failed to alloc fb\n");
9008 fb = &intel_fb->base;
9010 if (INTEL_INFO(dev)->gen >= 4) {
9011 if (val & DISPPLANE_TILED) {
9012 plane_config->tiling = I915_TILING_X;
9013 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9017 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9018 fourcc = i9xx_format_to_fourcc(pixel_format);
9019 fb->pixel_format = fourcc;
9020 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9022 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9023 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9024 offset = I915_READ(DSPOFFSET(pipe));
9026 if (plane_config->tiling)
9027 offset = I915_READ(DSPTILEOFF(pipe));
9029 offset = I915_READ(DSPLINOFF(pipe));
9031 plane_config->base = base;
9033 val = I915_READ(PIPESRC(pipe));
9034 fb->width = ((val >> 16) & 0xfff) + 1;
9035 fb->height = ((val >> 0) & 0xfff) + 1;
9037 val = I915_READ(DSPSTRIDE(pipe));
9038 fb->pitches[0] = val & 0xffffffc0;
9040 aligned_height = intel_fb_align_height(dev, fb->height,
9044 plane_config->size = fb->pitches[0] * aligned_height;
9046 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9047 pipe_name(pipe), fb->width, fb->height,
9048 fb->bits_per_pixel, base, fb->pitches[0],
9049 plane_config->size);
9051 plane_config->fb = intel_fb;
9054 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9055 struct intel_crtc_state *pipe_config)
9057 struct drm_device *dev = crtc->base.dev;
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9061 if (!intel_display_power_is_enabled(dev_priv,
9062 POWER_DOMAIN_PIPE(crtc->pipe)))
9065 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9066 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9068 tmp = I915_READ(PIPECONF(crtc->pipe));
9069 if (!(tmp & PIPECONF_ENABLE))
9072 switch (tmp & PIPECONF_BPC_MASK) {
9074 pipe_config->pipe_bpp = 18;
9077 pipe_config->pipe_bpp = 24;
9079 case PIPECONF_10BPC:
9080 pipe_config->pipe_bpp = 30;
9082 case PIPECONF_12BPC:
9083 pipe_config->pipe_bpp = 36;
9089 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9090 pipe_config->limited_color_range = true;
9092 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9093 struct intel_shared_dpll *pll;
9095 pipe_config->has_pch_encoder = true;
9097 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9098 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9099 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9101 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9103 if (HAS_PCH_IBX(dev_priv->dev)) {
9104 pipe_config->shared_dpll =
9105 (enum intel_dpll_id) crtc->pipe;
9107 tmp = I915_READ(PCH_DPLL_SEL);
9108 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9109 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9111 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9114 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9116 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9117 &pipe_config->dpll_hw_state));
9119 tmp = pipe_config->dpll_hw_state.dpll;
9120 pipe_config->pixel_multiplier =
9121 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9122 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9124 ironlake_pch_clock_get(crtc, pipe_config);
9126 pipe_config->pixel_multiplier = 1;
9129 intel_get_pipe_timings(crtc, pipe_config);
9131 ironlake_get_pfit_config(crtc, pipe_config);
9136 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9138 struct drm_device *dev = dev_priv->dev;
9139 struct intel_crtc *crtc;
9141 for_each_intel_crtc(dev, crtc)
9142 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9143 pipe_name(crtc->pipe));
9145 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9146 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9147 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9148 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9149 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9150 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9151 "CPU PWM1 enabled\n");
9152 if (IS_HASWELL(dev))
9153 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9154 "CPU PWM2 enabled\n");
9155 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9156 "PCH PWM1 enabled\n");
9157 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9158 "Utility pin enabled\n");
9159 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9162 * In theory we can still leave IRQs enabled, as long as only the HPD
9163 * interrupts remain enabled. We used to check for that, but since it's
9164 * gen-specific and since we only disable LCPLL after we fully disable
9165 * the interrupts, the check below should be enough.
9167 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9170 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9172 struct drm_device *dev = dev_priv->dev;
9174 if (IS_HASWELL(dev))
9175 return I915_READ(D_COMP_HSW);
9177 return I915_READ(D_COMP_BDW);
9180 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9182 struct drm_device *dev = dev_priv->dev;
9184 if (IS_HASWELL(dev)) {
9185 mutex_lock(&dev_priv->rps.hw_lock);
9186 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9188 DRM_ERROR("Failed to write to D_COMP\n");
9189 mutex_unlock(&dev_priv->rps.hw_lock);
9191 I915_WRITE(D_COMP_BDW, val);
9192 POSTING_READ(D_COMP_BDW);
9197 * This function implements pieces of two sequences from BSpec:
9198 * - Sequence for display software to disable LCPLL
9199 * - Sequence for display software to allow package C8+
9200 * The steps implemented here are just the steps that actually touch the LCPLL
9201 * register. Callers should take care of disabling all the display engine
9202 * functions, doing the mode unset, fixing interrupts, etc.
9204 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9205 bool switch_to_fclk, bool allow_power_down)
9209 assert_can_disable_lcpll(dev_priv);
9211 val = I915_READ(LCPLL_CTL);
9213 if (switch_to_fclk) {
9214 val |= LCPLL_CD_SOURCE_FCLK;
9215 I915_WRITE(LCPLL_CTL, val);
9217 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9218 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9219 DRM_ERROR("Switching to FCLK failed\n");
9221 val = I915_READ(LCPLL_CTL);
9224 val |= LCPLL_PLL_DISABLE;
9225 I915_WRITE(LCPLL_CTL, val);
9226 POSTING_READ(LCPLL_CTL);
9228 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9229 DRM_ERROR("LCPLL still locked\n");
9231 val = hsw_read_dcomp(dev_priv);
9232 val |= D_COMP_COMP_DISABLE;
9233 hsw_write_dcomp(dev_priv, val);
9236 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9238 DRM_ERROR("D_COMP RCOMP still in progress\n");
9240 if (allow_power_down) {
9241 val = I915_READ(LCPLL_CTL);
9242 val |= LCPLL_POWER_DOWN_ALLOW;
9243 I915_WRITE(LCPLL_CTL, val);
9244 POSTING_READ(LCPLL_CTL);
9249 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9252 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9256 val = I915_READ(LCPLL_CTL);
9258 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9259 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9263 * Make sure we're not on PC8 state before disabling PC8, otherwise
9264 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9266 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9268 if (val & LCPLL_POWER_DOWN_ALLOW) {
9269 val &= ~LCPLL_POWER_DOWN_ALLOW;
9270 I915_WRITE(LCPLL_CTL, val);
9271 POSTING_READ(LCPLL_CTL);
9274 val = hsw_read_dcomp(dev_priv);
9275 val |= D_COMP_COMP_FORCE;
9276 val &= ~D_COMP_COMP_DISABLE;
9277 hsw_write_dcomp(dev_priv, val);
9279 val = I915_READ(LCPLL_CTL);
9280 val &= ~LCPLL_PLL_DISABLE;
9281 I915_WRITE(LCPLL_CTL, val);
9283 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9284 DRM_ERROR("LCPLL not locked yet\n");
9286 if (val & LCPLL_CD_SOURCE_FCLK) {
9287 val = I915_READ(LCPLL_CTL);
9288 val &= ~LCPLL_CD_SOURCE_FCLK;
9289 I915_WRITE(LCPLL_CTL, val);
9291 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9292 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9293 DRM_ERROR("Switching back to LCPLL failed\n");
9296 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9300 * Package states C8 and deeper are really deep PC states that can only be
9301 * reached when all the devices on the system allow it, so even if the graphics
9302 * device allows PC8+, it doesn't mean the system will actually get to these
9303 * states. Our driver only allows PC8+ when going into runtime PM.
9305 * The requirements for PC8+ are that all the outputs are disabled, the power
9306 * well is disabled and most interrupts are disabled, and these are also
9307 * requirements for runtime PM. When these conditions are met, we manually do
9308 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9309 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9312 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9313 * the state of some registers, so when we come back from PC8+ we need to
9314 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9315 * need to take care of the registers kept by RC6. Notice that this happens even
9316 * if we don't put the device in PCI D3 state (which is what currently happens
9317 * because of the runtime PM support).
9319 * For more, read "Display Sequences for Package C8" on the hardware
9322 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9324 struct drm_device *dev = dev_priv->dev;
9327 DRM_DEBUG_KMS("Enabling package C8+\n");
9329 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9330 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9331 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9332 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9335 lpt_disable_clkout_dp(dev);
9336 hsw_disable_lcpll(dev_priv, true, true);
9339 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9341 struct drm_device *dev = dev_priv->dev;
9344 DRM_DEBUG_KMS("Disabling package C8+\n");
9346 hsw_restore_lcpll(dev_priv);
9347 lpt_init_pch_refclk(dev);
9349 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9350 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9351 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9352 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9355 intel_prepare_ddi(dev);
9358 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9360 struct drm_device *dev = old_state->dev;
9361 struct drm_i915_private *dev_priv = dev->dev_private;
9362 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9365 /* see the comment in valleyview_modeset_global_resources */
9366 if (WARN_ON(max_pixclk < 0))
9369 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9371 if (req_cdclk != dev_priv->cdclk_freq)
9372 broxton_set_cdclk(dev, req_cdclk);
9375 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9376 struct intel_crtc_state *crtc_state)
9378 if (!intel_ddi_pll_select(crtc, crtc_state))
9381 crtc->lowfreq_avail = false;
9386 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9388 struct intel_crtc_state *pipe_config)
9392 pipe_config->ddi_pll_sel = SKL_DPLL0;
9393 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9396 pipe_config->ddi_pll_sel = SKL_DPLL1;
9397 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9400 pipe_config->ddi_pll_sel = SKL_DPLL2;
9401 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9404 DRM_ERROR("Incorrect port type\n");
9408 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9410 struct intel_crtc_state *pipe_config)
9412 u32 temp, dpll_ctl1;
9414 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9415 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9417 switch (pipe_config->ddi_pll_sel) {
9420 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9421 * of the shared DPLL framework and thus needs to be read out
9424 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9425 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9428 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9431 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9434 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9439 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9441 struct intel_crtc_state *pipe_config)
9443 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9445 switch (pipe_config->ddi_pll_sel) {
9446 case PORT_CLK_SEL_WRPLL1:
9447 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9449 case PORT_CLK_SEL_WRPLL2:
9450 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9455 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9456 struct intel_crtc_state *pipe_config)
9458 struct drm_device *dev = crtc->base.dev;
9459 struct drm_i915_private *dev_priv = dev->dev_private;
9460 struct intel_shared_dpll *pll;
9464 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9466 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9468 if (IS_SKYLAKE(dev))
9469 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9470 else if (IS_BROXTON(dev))
9471 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9473 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9475 if (pipe_config->shared_dpll >= 0) {
9476 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9478 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9479 &pipe_config->dpll_hw_state));
9483 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9484 * DDI E. So just check whether this pipe is wired to DDI E and whether
9485 * the PCH transcoder is on.
9487 if (INTEL_INFO(dev)->gen < 9 &&
9488 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9489 pipe_config->has_pch_encoder = true;
9491 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9492 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9493 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9495 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9499 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9500 struct intel_crtc_state *pipe_config)
9502 struct drm_device *dev = crtc->base.dev;
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504 enum intel_display_power_domain pfit_domain;
9507 if (!intel_display_power_is_enabled(dev_priv,
9508 POWER_DOMAIN_PIPE(crtc->pipe)))
9511 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9512 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9514 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9515 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9516 enum pipe trans_edp_pipe;
9517 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9519 WARN(1, "unknown pipe linked to edp transcoder\n");
9520 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9521 case TRANS_DDI_EDP_INPUT_A_ON:
9522 trans_edp_pipe = PIPE_A;
9524 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9525 trans_edp_pipe = PIPE_B;
9527 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9528 trans_edp_pipe = PIPE_C;
9532 if (trans_edp_pipe == crtc->pipe)
9533 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9536 if (!intel_display_power_is_enabled(dev_priv,
9537 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9540 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9541 if (!(tmp & PIPECONF_ENABLE))
9544 haswell_get_ddi_port_state(crtc, pipe_config);
9546 intel_get_pipe_timings(crtc, pipe_config);
9548 if (INTEL_INFO(dev)->gen >= 9) {
9549 skl_init_scalers(dev, crtc, pipe_config);
9552 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9554 if (INTEL_INFO(dev)->gen >= 9) {
9555 pipe_config->scaler_state.scaler_id = -1;
9556 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9559 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9560 if (INTEL_INFO(dev)->gen == 9)
9561 skylake_get_pfit_config(crtc, pipe_config);
9562 else if (INTEL_INFO(dev)->gen < 9)
9563 ironlake_get_pfit_config(crtc, pipe_config);
9565 MISSING_CASE(INTEL_INFO(dev)->gen);
9568 if (IS_HASWELL(dev))
9569 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9570 (I915_READ(IPS_CTL) & IPS_ENABLE);
9572 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9573 pipe_config->pixel_multiplier =
9574 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9576 pipe_config->pixel_multiplier = 1;
9582 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9584 struct drm_device *dev = crtc->dev;
9585 struct drm_i915_private *dev_priv = dev->dev_private;
9586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9587 uint32_t cntl = 0, size = 0;
9590 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9591 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9592 unsigned int stride = roundup_pow_of_two(width) * 4;
9596 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9607 cntl |= CURSOR_ENABLE |
9608 CURSOR_GAMMA_ENABLE |
9609 CURSOR_FORMAT_ARGB |
9610 CURSOR_STRIDE(stride);
9612 size = (height << 12) | width;
9615 if (intel_crtc->cursor_cntl != 0 &&
9616 (intel_crtc->cursor_base != base ||
9617 intel_crtc->cursor_size != size ||
9618 intel_crtc->cursor_cntl != cntl)) {
9619 /* On these chipsets we can only modify the base/size/stride
9620 * whilst the cursor is disabled.
9622 I915_WRITE(_CURACNTR, 0);
9623 POSTING_READ(_CURACNTR);
9624 intel_crtc->cursor_cntl = 0;
9627 if (intel_crtc->cursor_base != base) {
9628 I915_WRITE(_CURABASE, base);
9629 intel_crtc->cursor_base = base;
9632 if (intel_crtc->cursor_size != size) {
9633 I915_WRITE(CURSIZE, size);
9634 intel_crtc->cursor_size = size;
9637 if (intel_crtc->cursor_cntl != cntl) {
9638 I915_WRITE(_CURACNTR, cntl);
9639 POSTING_READ(_CURACNTR);
9640 intel_crtc->cursor_cntl = cntl;
9644 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9646 struct drm_device *dev = crtc->dev;
9647 struct drm_i915_private *dev_priv = dev->dev_private;
9648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9649 int pipe = intel_crtc->pipe;
9654 cntl = MCURSOR_GAMMA_ENABLE;
9655 switch (intel_crtc->base.cursor->state->crtc_w) {
9657 cntl |= CURSOR_MODE_64_ARGB_AX;
9660 cntl |= CURSOR_MODE_128_ARGB_AX;
9663 cntl |= CURSOR_MODE_256_ARGB_AX;
9666 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9669 cntl |= pipe << 28; /* Connect to correct pipe */
9671 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9672 cntl |= CURSOR_PIPE_CSC_ENABLE;
9675 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9676 cntl |= CURSOR_ROTATE_180;
9678 if (intel_crtc->cursor_cntl != cntl) {
9679 I915_WRITE(CURCNTR(pipe), cntl);
9680 POSTING_READ(CURCNTR(pipe));
9681 intel_crtc->cursor_cntl = cntl;
9684 /* and commit changes on next vblank */
9685 I915_WRITE(CURBASE(pipe), base);
9686 POSTING_READ(CURBASE(pipe));
9688 intel_crtc->cursor_base = base;
9691 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9692 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9695 struct drm_device *dev = crtc->dev;
9696 struct drm_i915_private *dev_priv = dev->dev_private;
9697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9698 int pipe = intel_crtc->pipe;
9699 int x = crtc->cursor_x;
9700 int y = crtc->cursor_y;
9701 u32 base = 0, pos = 0;
9704 base = intel_crtc->cursor_addr;
9706 if (x >= intel_crtc->config->pipe_src_w)
9709 if (y >= intel_crtc->config->pipe_src_h)
9713 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9716 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9719 pos |= x << CURSOR_X_SHIFT;
9722 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9725 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9728 pos |= y << CURSOR_Y_SHIFT;
9730 if (base == 0 && intel_crtc->cursor_base == 0)
9733 I915_WRITE(CURPOS(pipe), pos);
9735 /* ILK+ do this automagically */
9736 if (HAS_GMCH_DISPLAY(dev) &&
9737 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9738 base += (intel_crtc->base.cursor->state->crtc_h *
9739 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9742 if (IS_845G(dev) || IS_I865G(dev))
9743 i845_update_cursor(crtc, base);
9745 i9xx_update_cursor(crtc, base);
9748 static bool cursor_size_ok(struct drm_device *dev,
9749 uint32_t width, uint32_t height)
9751 if (width == 0 || height == 0)
9755 * 845g/865g are special in that they are only limited by
9756 * the width of their cursors, the height is arbitrary up to
9757 * the precision of the register. Everything else requires
9758 * square cursors, limited to a few power-of-two sizes.
9760 if (IS_845G(dev) || IS_I865G(dev)) {
9761 if ((width & 63) != 0)
9764 if (width > (IS_845G(dev) ? 64 : 512))
9770 switch (width | height) {
9785 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9786 u16 *blue, uint32_t start, uint32_t size)
9788 int end = (start + size > 256) ? 256 : start + size, i;
9789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9791 for (i = start; i < end; i++) {
9792 intel_crtc->lut_r[i] = red[i] >> 8;
9793 intel_crtc->lut_g[i] = green[i] >> 8;
9794 intel_crtc->lut_b[i] = blue[i] >> 8;
9797 intel_crtc_load_lut(crtc);
9800 /* VESA 640x480x72Hz mode to set on the pipe */
9801 static struct drm_display_mode load_detect_mode = {
9802 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9803 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9806 struct drm_framebuffer *
9807 __intel_framebuffer_create(struct drm_device *dev,
9808 struct drm_mode_fb_cmd2 *mode_cmd,
9809 struct drm_i915_gem_object *obj)
9811 struct intel_framebuffer *intel_fb;
9814 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9816 drm_gem_object_unreference(&obj->base);
9817 return ERR_PTR(-ENOMEM);
9820 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9824 return &intel_fb->base;
9826 drm_gem_object_unreference(&obj->base);
9829 return ERR_PTR(ret);
9832 static struct drm_framebuffer *
9833 intel_framebuffer_create(struct drm_device *dev,
9834 struct drm_mode_fb_cmd2 *mode_cmd,
9835 struct drm_i915_gem_object *obj)
9837 struct drm_framebuffer *fb;
9840 ret = i915_mutex_lock_interruptible(dev);
9842 return ERR_PTR(ret);
9843 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9844 mutex_unlock(&dev->struct_mutex);
9850 intel_framebuffer_pitch_for_width(int width, int bpp)
9852 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9853 return ALIGN(pitch, 64);
9857 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9859 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9860 return PAGE_ALIGN(pitch * mode->vdisplay);
9863 static struct drm_framebuffer *
9864 intel_framebuffer_create_for_mode(struct drm_device *dev,
9865 struct drm_display_mode *mode,
9868 struct drm_i915_gem_object *obj;
9869 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9871 obj = i915_gem_alloc_object(dev,
9872 intel_framebuffer_size_for_mode(mode, bpp));
9874 return ERR_PTR(-ENOMEM);
9876 mode_cmd.width = mode->hdisplay;
9877 mode_cmd.height = mode->vdisplay;
9878 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9880 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9882 return intel_framebuffer_create(dev, &mode_cmd, obj);
9885 static struct drm_framebuffer *
9886 mode_fits_in_fbdev(struct drm_device *dev,
9887 struct drm_display_mode *mode)
9889 #ifdef CONFIG_DRM_I915_FBDEV
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 struct drm_i915_gem_object *obj;
9892 struct drm_framebuffer *fb;
9894 if (!dev_priv->fbdev)
9897 if (!dev_priv->fbdev->fb)
9900 obj = dev_priv->fbdev->fb->obj;
9903 fb = &dev_priv->fbdev->fb->base;
9904 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9905 fb->bits_per_pixel))
9908 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9917 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9918 struct drm_crtc *crtc,
9919 struct drm_display_mode *mode,
9920 struct drm_framebuffer *fb,
9923 struct drm_plane_state *plane_state;
9924 int hdisplay, vdisplay;
9927 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9928 if (IS_ERR(plane_state))
9929 return PTR_ERR(plane_state);
9932 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9934 hdisplay = vdisplay = 0;
9936 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9939 drm_atomic_set_fb_for_plane(plane_state, fb);
9940 plane_state->crtc_x = 0;
9941 plane_state->crtc_y = 0;
9942 plane_state->crtc_w = hdisplay;
9943 plane_state->crtc_h = vdisplay;
9944 plane_state->src_x = x << 16;
9945 plane_state->src_y = y << 16;
9946 plane_state->src_w = hdisplay << 16;
9947 plane_state->src_h = vdisplay << 16;
9952 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9953 struct drm_display_mode *mode,
9954 struct intel_load_detect_pipe *old,
9955 struct drm_modeset_acquire_ctx *ctx)
9957 struct intel_crtc *intel_crtc;
9958 struct intel_encoder *intel_encoder =
9959 intel_attached_encoder(connector);
9960 struct drm_crtc *possible_crtc;
9961 struct drm_encoder *encoder = &intel_encoder->base;
9962 struct drm_crtc *crtc = NULL;
9963 struct drm_device *dev = encoder->dev;
9964 struct drm_framebuffer *fb;
9965 struct drm_mode_config *config = &dev->mode_config;
9966 struct drm_atomic_state *state = NULL;
9967 struct drm_connector_state *connector_state;
9968 struct intel_crtc_state *crtc_state;
9971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9972 connector->base.id, connector->name,
9973 encoder->base.id, encoder->name);
9976 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9981 * Algorithm gets a little messy:
9983 * - if the connector already has an assigned crtc, use it (but make
9984 * sure it's on first)
9986 * - try to find the first unused crtc that can drive this connector,
9987 * and use that if we find one
9990 /* See if we already have a CRTC for this connector */
9991 if (encoder->crtc) {
9992 crtc = encoder->crtc;
9994 ret = drm_modeset_lock(&crtc->mutex, ctx);
9997 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10001 old->dpms_mode = connector->dpms;
10002 old->load_detect_temp = false;
10004 /* Make sure the crtc and connector are running */
10005 if (connector->dpms != DRM_MODE_DPMS_ON)
10006 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10011 /* Find an unused one (if possible) */
10012 for_each_crtc(dev, possible_crtc) {
10014 if (!(encoder->possible_crtcs & (1 << i)))
10016 if (possible_crtc->state->enable)
10018 /* This can occur when applying the pipe A quirk on resume. */
10019 if (to_intel_crtc(possible_crtc)->new_enabled)
10022 crtc = possible_crtc;
10027 * If we didn't find an unused CRTC, don't use any.
10030 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10034 ret = drm_modeset_lock(&crtc->mutex, ctx);
10037 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10040 intel_encoder->new_crtc = to_intel_crtc(crtc);
10041 to_intel_connector(connector)->new_encoder = intel_encoder;
10043 intel_crtc = to_intel_crtc(crtc);
10044 intel_crtc->new_enabled = true;
10045 old->dpms_mode = connector->dpms;
10046 old->load_detect_temp = true;
10047 old->release_fb = NULL;
10049 state = drm_atomic_state_alloc(dev);
10053 state->acquire_ctx = ctx;
10055 connector_state = drm_atomic_get_connector_state(state, connector);
10056 if (IS_ERR(connector_state)) {
10057 ret = PTR_ERR(connector_state);
10061 connector_state->crtc = crtc;
10062 connector_state->best_encoder = &intel_encoder->base;
10064 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10065 if (IS_ERR(crtc_state)) {
10066 ret = PTR_ERR(crtc_state);
10070 crtc_state->base.active = crtc_state->base.enable = true;
10073 mode = &load_detect_mode;
10075 /* We need a framebuffer large enough to accommodate all accesses
10076 * that the plane may generate whilst we perform load detection.
10077 * We can not rely on the fbcon either being present (we get called
10078 * during its initialisation to detect all boot displays, or it may
10079 * not even exist) or that it is large enough to satisfy the
10082 fb = mode_fits_in_fbdev(dev, mode);
10084 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10085 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10086 old->release_fb = fb;
10088 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10090 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10094 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10098 drm_mode_copy(&crtc_state->base.mode, mode);
10100 if (intel_set_mode(crtc, state, true)) {
10101 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10102 if (old->release_fb)
10103 old->release_fb->funcs->destroy(old->release_fb);
10106 crtc->primary->crtc = crtc;
10108 /* let the connector get through one full cycle before testing */
10109 intel_wait_for_vblank(dev, intel_crtc->pipe);
10113 intel_crtc->new_enabled = crtc->state->enable;
10115 drm_atomic_state_free(state);
10118 if (ret == -EDEADLK) {
10119 drm_modeset_backoff(ctx);
10126 void intel_release_load_detect_pipe(struct drm_connector *connector,
10127 struct intel_load_detect_pipe *old,
10128 struct drm_modeset_acquire_ctx *ctx)
10130 struct drm_device *dev = connector->dev;
10131 struct intel_encoder *intel_encoder =
10132 intel_attached_encoder(connector);
10133 struct drm_encoder *encoder = &intel_encoder->base;
10134 struct drm_crtc *crtc = encoder->crtc;
10135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10136 struct drm_atomic_state *state;
10137 struct drm_connector_state *connector_state;
10138 struct intel_crtc_state *crtc_state;
10141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10142 connector->base.id, connector->name,
10143 encoder->base.id, encoder->name);
10145 if (old->load_detect_temp) {
10146 state = drm_atomic_state_alloc(dev);
10150 state->acquire_ctx = ctx;
10152 connector_state = drm_atomic_get_connector_state(state, connector);
10153 if (IS_ERR(connector_state))
10156 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10157 if (IS_ERR(crtc_state))
10160 to_intel_connector(connector)->new_encoder = NULL;
10161 intel_encoder->new_crtc = NULL;
10162 intel_crtc->new_enabled = false;
10164 connector_state->best_encoder = NULL;
10165 connector_state->crtc = NULL;
10167 crtc_state->base.enable = crtc_state->base.active = false;
10169 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10174 ret = intel_set_mode(crtc, state, true);
10178 if (old->release_fb) {
10179 drm_framebuffer_unregister_private(old->release_fb);
10180 drm_framebuffer_unreference(old->release_fb);
10186 /* Switch crtc and encoder back off if necessary */
10187 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10188 connector->funcs->dpms(connector, old->dpms_mode);
10192 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10193 drm_atomic_state_free(state);
10196 static int i9xx_pll_refclk(struct drm_device *dev,
10197 const struct intel_crtc_state *pipe_config)
10199 struct drm_i915_private *dev_priv = dev->dev_private;
10200 u32 dpll = pipe_config->dpll_hw_state.dpll;
10202 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10203 return dev_priv->vbt.lvds_ssc_freq;
10204 else if (HAS_PCH_SPLIT(dev))
10206 else if (!IS_GEN2(dev))
10212 /* Returns the clock of the currently programmed mode of the given pipe. */
10213 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10214 struct intel_crtc_state *pipe_config)
10216 struct drm_device *dev = crtc->base.dev;
10217 struct drm_i915_private *dev_priv = dev->dev_private;
10218 int pipe = pipe_config->cpu_transcoder;
10219 u32 dpll = pipe_config->dpll_hw_state.dpll;
10221 intel_clock_t clock;
10222 int refclk = i9xx_pll_refclk(dev, pipe_config);
10224 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10225 fp = pipe_config->dpll_hw_state.fp0;
10227 fp = pipe_config->dpll_hw_state.fp1;
10229 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10230 if (IS_PINEVIEW(dev)) {
10231 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10232 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10234 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10235 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10238 if (!IS_GEN2(dev)) {
10239 if (IS_PINEVIEW(dev))
10240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10241 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10244 DPLL_FPA01_P1_POST_DIV_SHIFT);
10246 switch (dpll & DPLL_MODE_MASK) {
10247 case DPLLB_MODE_DAC_SERIAL:
10248 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10251 case DPLLB_MODE_LVDS:
10252 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10256 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10257 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10261 if (IS_PINEVIEW(dev))
10262 pineview_clock(refclk, &clock);
10264 i9xx_clock(refclk, &clock);
10266 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10267 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10270 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10271 DPLL_FPA01_P1_POST_DIV_SHIFT);
10273 if (lvds & LVDS_CLKB_POWER_UP)
10278 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10281 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10282 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10284 if (dpll & PLL_P2_DIVIDE_BY_4)
10290 i9xx_clock(refclk, &clock);
10294 * This value includes pixel_multiplier. We will use
10295 * port_clock to compute adjusted_mode.crtc_clock in the
10296 * encoder's get_config() function.
10298 pipe_config->port_clock = clock.dot;
10301 int intel_dotclock_calculate(int link_freq,
10302 const struct intel_link_m_n *m_n)
10305 * The calculation for the data clock is:
10306 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10307 * But we want to avoid losing precison if possible, so:
10308 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10310 * and the link clock is simpler:
10311 * link_clock = (m * link_clock) / n
10317 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10320 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10321 struct intel_crtc_state *pipe_config)
10323 struct drm_device *dev = crtc->base.dev;
10325 /* read out port_clock from the DPLL */
10326 i9xx_crtc_clock_get(crtc, pipe_config);
10329 * This value does not include pixel_multiplier.
10330 * We will check that port_clock and adjusted_mode.crtc_clock
10331 * agree once we know their relationship in the encoder's
10332 * get_config() function.
10334 pipe_config->base.adjusted_mode.crtc_clock =
10335 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10336 &pipe_config->fdi_m_n);
10339 /** Returns the currently programmed mode of the given pipe. */
10340 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10341 struct drm_crtc *crtc)
10343 struct drm_i915_private *dev_priv = dev->dev_private;
10344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10345 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10346 struct drm_display_mode *mode;
10347 struct intel_crtc_state pipe_config;
10348 int htot = I915_READ(HTOTAL(cpu_transcoder));
10349 int hsync = I915_READ(HSYNC(cpu_transcoder));
10350 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10351 int vsync = I915_READ(VSYNC(cpu_transcoder));
10352 enum pipe pipe = intel_crtc->pipe;
10354 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10359 * Construct a pipe_config sufficient for getting the clock info
10360 * back out of crtc_clock_get.
10362 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10363 * to use a real value here instead.
10365 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10366 pipe_config.pixel_multiplier = 1;
10367 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10368 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10369 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10370 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10372 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10373 mode->hdisplay = (htot & 0xffff) + 1;
10374 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10375 mode->hsync_start = (hsync & 0xffff) + 1;
10376 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10377 mode->vdisplay = (vtot & 0xffff) + 1;
10378 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10379 mode->vsync_start = (vsync & 0xffff) + 1;
10380 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10382 drm_mode_set_name(mode);
10387 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10389 struct drm_device *dev = crtc->dev;
10390 struct drm_i915_private *dev_priv = dev->dev_private;
10391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10393 if (!HAS_GMCH_DISPLAY(dev))
10396 if (!dev_priv->lvds_downclock_avail)
10400 * Since this is called by a timer, we should never get here in
10403 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10404 int pipe = intel_crtc->pipe;
10405 int dpll_reg = DPLL(pipe);
10408 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10410 assert_panel_unlocked(dev_priv, pipe);
10412 dpll = I915_READ(dpll_reg);
10413 dpll |= DISPLAY_RATE_SELECT_FPA1;
10414 I915_WRITE(dpll_reg, dpll);
10415 intel_wait_for_vblank(dev, pipe);
10416 dpll = I915_READ(dpll_reg);
10417 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10418 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10423 void intel_mark_busy(struct drm_device *dev)
10425 struct drm_i915_private *dev_priv = dev->dev_private;
10427 if (dev_priv->mm.busy)
10430 intel_runtime_pm_get(dev_priv);
10431 i915_update_gfx_val(dev_priv);
10432 if (INTEL_INFO(dev)->gen >= 6)
10433 gen6_rps_busy(dev_priv);
10434 dev_priv->mm.busy = true;
10437 void intel_mark_idle(struct drm_device *dev)
10439 struct drm_i915_private *dev_priv = dev->dev_private;
10440 struct drm_crtc *crtc;
10442 if (!dev_priv->mm.busy)
10445 dev_priv->mm.busy = false;
10447 for_each_crtc(dev, crtc) {
10448 if (!crtc->primary->fb)
10451 intel_decrease_pllclock(crtc);
10454 if (INTEL_INFO(dev)->gen >= 6)
10455 gen6_rps_idle(dev->dev_private);
10457 intel_runtime_pm_put(dev_priv);
10460 static void intel_crtc_destroy(struct drm_crtc *crtc)
10462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10463 struct drm_device *dev = crtc->dev;
10464 struct intel_unpin_work *work;
10466 spin_lock_irq(&dev->event_lock);
10467 work = intel_crtc->unpin_work;
10468 intel_crtc->unpin_work = NULL;
10469 spin_unlock_irq(&dev->event_lock);
10472 cancel_work_sync(&work->work);
10476 drm_crtc_cleanup(crtc);
10481 static void intel_unpin_work_fn(struct work_struct *__work)
10483 struct intel_unpin_work *work =
10484 container_of(__work, struct intel_unpin_work, work);
10485 struct drm_device *dev = work->crtc->dev;
10486 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10488 mutex_lock(&dev->struct_mutex);
10489 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10490 drm_gem_object_unreference(&work->pending_flip_obj->base);
10492 intel_fbc_update(dev);
10494 if (work->flip_queued_req)
10495 i915_gem_request_assign(&work->flip_queued_req, NULL);
10496 mutex_unlock(&dev->struct_mutex);
10498 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10499 drm_framebuffer_unreference(work->old_fb);
10501 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10502 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10507 static void do_intel_finish_page_flip(struct drm_device *dev,
10508 struct drm_crtc *crtc)
10510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10511 struct intel_unpin_work *work;
10512 unsigned long flags;
10514 /* Ignore early vblank irqs */
10515 if (intel_crtc == NULL)
10519 * This is called both by irq handlers and the reset code (to complete
10520 * lost pageflips) so needs the full irqsave spinlocks.
10522 spin_lock_irqsave(&dev->event_lock, flags);
10523 work = intel_crtc->unpin_work;
10525 /* Ensure we don't miss a work->pending update ... */
10528 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10529 spin_unlock_irqrestore(&dev->event_lock, flags);
10533 page_flip_completed(intel_crtc);
10535 spin_unlock_irqrestore(&dev->event_lock, flags);
10538 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10540 struct drm_i915_private *dev_priv = dev->dev_private;
10541 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10543 do_intel_finish_page_flip(dev, crtc);
10546 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10548 struct drm_i915_private *dev_priv = dev->dev_private;
10549 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10551 do_intel_finish_page_flip(dev, crtc);
10554 /* Is 'a' after or equal to 'b'? */
10555 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10557 return !((a - b) & 0x80000000);
10560 static bool page_flip_finished(struct intel_crtc *crtc)
10562 struct drm_device *dev = crtc->base.dev;
10563 struct drm_i915_private *dev_priv = dev->dev_private;
10565 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10566 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10570 * The relevant registers doen't exist on pre-ctg.
10571 * As the flip done interrupt doesn't trigger for mmio
10572 * flips on gmch platforms, a flip count check isn't
10573 * really needed there. But since ctg has the registers,
10574 * include it in the check anyway.
10576 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10580 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10581 * used the same base address. In that case the mmio flip might
10582 * have completed, but the CS hasn't even executed the flip yet.
10584 * A flip count check isn't enough as the CS might have updated
10585 * the base address just after start of vblank, but before we
10586 * managed to process the interrupt. This means we'd complete the
10587 * CS flip too soon.
10589 * Combining both checks should get us a good enough result. It may
10590 * still happen that the CS flip has been executed, but has not
10591 * yet actually completed. But in case the base address is the same
10592 * anyway, we don't really care.
10594 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10595 crtc->unpin_work->gtt_offset &&
10596 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10597 crtc->unpin_work->flip_count);
10600 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10602 struct drm_i915_private *dev_priv = dev->dev_private;
10603 struct intel_crtc *intel_crtc =
10604 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10605 unsigned long flags;
10609 * This is called both by irq handlers and the reset code (to complete
10610 * lost pageflips) so needs the full irqsave spinlocks.
10612 * NB: An MMIO update of the plane base pointer will also
10613 * generate a page-flip completion irq, i.e. every modeset
10614 * is also accompanied by a spurious intel_prepare_page_flip().
10616 spin_lock_irqsave(&dev->event_lock, flags);
10617 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10618 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10619 spin_unlock_irqrestore(&dev->event_lock, flags);
10622 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10624 /* Ensure that the work item is consistent when activating it ... */
10626 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10627 /* and that it is marked active as soon as the irq could fire. */
10631 static int intel_gen2_queue_flip(struct drm_device *dev,
10632 struct drm_crtc *crtc,
10633 struct drm_framebuffer *fb,
10634 struct drm_i915_gem_object *obj,
10635 struct intel_engine_cs *ring,
10638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10642 ret = intel_ring_begin(ring, 6);
10646 /* Can't queue multiple flips, so wait for the previous
10647 * one to finish before executing the next.
10649 if (intel_crtc->plane)
10650 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10652 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10653 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10654 intel_ring_emit(ring, MI_NOOP);
10655 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10656 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10657 intel_ring_emit(ring, fb->pitches[0]);
10658 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10659 intel_ring_emit(ring, 0); /* aux display base address, unused */
10661 intel_mark_page_flip_active(intel_crtc);
10662 __intel_ring_advance(ring);
10666 static int intel_gen3_queue_flip(struct drm_device *dev,
10667 struct drm_crtc *crtc,
10668 struct drm_framebuffer *fb,
10669 struct drm_i915_gem_object *obj,
10670 struct intel_engine_cs *ring,
10673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10677 ret = intel_ring_begin(ring, 6);
10681 if (intel_crtc->plane)
10682 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10684 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10685 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10686 intel_ring_emit(ring, MI_NOOP);
10687 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10688 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10689 intel_ring_emit(ring, fb->pitches[0]);
10690 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10691 intel_ring_emit(ring, MI_NOOP);
10693 intel_mark_page_flip_active(intel_crtc);
10694 __intel_ring_advance(ring);
10698 static int intel_gen4_queue_flip(struct drm_device *dev,
10699 struct drm_crtc *crtc,
10700 struct drm_framebuffer *fb,
10701 struct drm_i915_gem_object *obj,
10702 struct intel_engine_cs *ring,
10705 struct drm_i915_private *dev_priv = dev->dev_private;
10706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10707 uint32_t pf, pipesrc;
10710 ret = intel_ring_begin(ring, 4);
10714 /* i965+ uses the linear or tiled offsets from the
10715 * Display Registers (which do not change across a page-flip)
10716 * so we need only reprogram the base address.
10718 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10719 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10720 intel_ring_emit(ring, fb->pitches[0]);
10721 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10724 /* XXX Enabling the panel-fitter across page-flip is so far
10725 * untested on non-native modes, so ignore it for now.
10726 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10729 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10730 intel_ring_emit(ring, pf | pipesrc);
10732 intel_mark_page_flip_active(intel_crtc);
10733 __intel_ring_advance(ring);
10737 static int intel_gen6_queue_flip(struct drm_device *dev,
10738 struct drm_crtc *crtc,
10739 struct drm_framebuffer *fb,
10740 struct drm_i915_gem_object *obj,
10741 struct intel_engine_cs *ring,
10744 struct drm_i915_private *dev_priv = dev->dev_private;
10745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10746 uint32_t pf, pipesrc;
10749 ret = intel_ring_begin(ring, 4);
10753 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10754 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10755 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10756 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10758 /* Contrary to the suggestions in the documentation,
10759 * "Enable Panel Fitter" does not seem to be required when page
10760 * flipping with a non-native mode, and worse causes a normal
10762 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10765 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10766 intel_ring_emit(ring, pf | pipesrc);
10768 intel_mark_page_flip_active(intel_crtc);
10769 __intel_ring_advance(ring);
10773 static int intel_gen7_queue_flip(struct drm_device *dev,
10774 struct drm_crtc *crtc,
10775 struct drm_framebuffer *fb,
10776 struct drm_i915_gem_object *obj,
10777 struct intel_engine_cs *ring,
10780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10781 uint32_t plane_bit = 0;
10784 switch (intel_crtc->plane) {
10786 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10789 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10792 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10795 WARN_ONCE(1, "unknown plane in flip command\n");
10800 if (ring->id == RCS) {
10803 * On Gen 8, SRM is now taking an extra dword to accommodate
10804 * 48bits addresses, and we need a NOOP for the batch size to
10812 * BSpec MI_DISPLAY_FLIP for IVB:
10813 * "The full packet must be contained within the same cache line."
10815 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10816 * cacheline, if we ever start emitting more commands before
10817 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10818 * then do the cacheline alignment, and finally emit the
10821 ret = intel_ring_cacheline_align(ring);
10825 ret = intel_ring_begin(ring, len);
10829 /* Unmask the flip-done completion message. Note that the bspec says that
10830 * we should do this for both the BCS and RCS, and that we must not unmask
10831 * more than one flip event at any time (or ensure that one flip message
10832 * can be sent by waiting for flip-done prior to queueing new flips).
10833 * Experimentation says that BCS works despite DERRMR masking all
10834 * flip-done completion events and that unmasking all planes at once
10835 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10836 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10838 if (ring->id == RCS) {
10839 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10840 intel_ring_emit(ring, DERRMR);
10841 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10842 DERRMR_PIPEB_PRI_FLIP_DONE |
10843 DERRMR_PIPEC_PRI_FLIP_DONE));
10845 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10846 MI_SRM_LRM_GLOBAL_GTT);
10848 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10849 MI_SRM_LRM_GLOBAL_GTT);
10850 intel_ring_emit(ring, DERRMR);
10851 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10852 if (IS_GEN8(dev)) {
10853 intel_ring_emit(ring, 0);
10854 intel_ring_emit(ring, MI_NOOP);
10858 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10859 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10860 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10861 intel_ring_emit(ring, (MI_NOOP));
10863 intel_mark_page_flip_active(intel_crtc);
10864 __intel_ring_advance(ring);
10868 static bool use_mmio_flip(struct intel_engine_cs *ring,
10869 struct drm_i915_gem_object *obj)
10872 * This is not being used for older platforms, because
10873 * non-availability of flip done interrupt forces us to use
10874 * CS flips. Older platforms derive flip done using some clever
10875 * tricks involving the flip_pending status bits and vblank irqs.
10876 * So using MMIO flips there would disrupt this mechanism.
10882 if (INTEL_INFO(ring->dev)->gen < 5)
10885 if (i915.use_mmio_flip < 0)
10887 else if (i915.use_mmio_flip > 0)
10889 else if (i915.enable_execlists)
10892 return ring != i915_gem_request_get_ring(obj->last_write_req);
10895 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10897 struct drm_device *dev = intel_crtc->base.dev;
10898 struct drm_i915_private *dev_priv = dev->dev_private;
10899 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10900 const enum pipe pipe = intel_crtc->pipe;
10903 ctl = I915_READ(PLANE_CTL(pipe, 0));
10904 ctl &= ~PLANE_CTL_TILED_MASK;
10905 switch (fb->modifier[0]) {
10906 case DRM_FORMAT_MOD_NONE:
10908 case I915_FORMAT_MOD_X_TILED:
10909 ctl |= PLANE_CTL_TILED_X;
10911 case I915_FORMAT_MOD_Y_TILED:
10912 ctl |= PLANE_CTL_TILED_Y;
10914 case I915_FORMAT_MOD_Yf_TILED:
10915 ctl |= PLANE_CTL_TILED_YF;
10918 MISSING_CASE(fb->modifier[0]);
10922 * The stride is either expressed as a multiple of 64 bytes chunks for
10923 * linear buffers or in number of tiles for tiled buffers.
10925 stride = fb->pitches[0] /
10926 intel_fb_stride_alignment(dev, fb->modifier[0],
10930 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10931 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10933 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10934 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10936 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10937 POSTING_READ(PLANE_SURF(pipe, 0));
10940 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10942 struct drm_device *dev = intel_crtc->base.dev;
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944 struct intel_framebuffer *intel_fb =
10945 to_intel_framebuffer(intel_crtc->base.primary->fb);
10946 struct drm_i915_gem_object *obj = intel_fb->obj;
10950 reg = DSPCNTR(intel_crtc->plane);
10951 dspcntr = I915_READ(reg);
10953 if (obj->tiling_mode != I915_TILING_NONE)
10954 dspcntr |= DISPPLANE_TILED;
10956 dspcntr &= ~DISPPLANE_TILED;
10958 I915_WRITE(reg, dspcntr);
10960 I915_WRITE(DSPSURF(intel_crtc->plane),
10961 intel_crtc->unpin_work->gtt_offset);
10962 POSTING_READ(DSPSURF(intel_crtc->plane));
10967 * XXX: This is the temporary way to update the plane registers until we get
10968 * around to using the usual plane update functions for MMIO flips
10970 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10972 struct drm_device *dev = intel_crtc->base.dev;
10973 bool atomic_update;
10974 u32 start_vbl_count;
10976 intel_mark_page_flip_active(intel_crtc);
10978 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10980 if (INTEL_INFO(dev)->gen >= 9)
10981 skl_do_mmio_flip(intel_crtc);
10983 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10984 ilk_do_mmio_flip(intel_crtc);
10987 intel_pipe_update_end(intel_crtc, start_vbl_count);
10990 static void intel_mmio_flip_work_func(struct work_struct *work)
10992 struct intel_mmio_flip *mmio_flip =
10993 container_of(work, struct intel_mmio_flip, work);
10995 if (mmio_flip->req)
10996 WARN_ON(__i915_wait_request(mmio_flip->req,
10997 mmio_flip->crtc->reset_counter,
10999 &mmio_flip->i915->rps.mmioflips));
11001 intel_do_mmio_flip(mmio_flip->crtc);
11003 i915_gem_request_unreference__unlocked(mmio_flip->req);
11007 static int intel_queue_mmio_flip(struct drm_device *dev,
11008 struct drm_crtc *crtc,
11009 struct drm_framebuffer *fb,
11010 struct drm_i915_gem_object *obj,
11011 struct intel_engine_cs *ring,
11014 struct intel_mmio_flip *mmio_flip;
11016 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11017 if (mmio_flip == NULL)
11020 mmio_flip->i915 = to_i915(dev);
11021 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11022 mmio_flip->crtc = to_intel_crtc(crtc);
11024 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11025 schedule_work(&mmio_flip->work);
11030 static int intel_default_queue_flip(struct drm_device *dev,
11031 struct drm_crtc *crtc,
11032 struct drm_framebuffer *fb,
11033 struct drm_i915_gem_object *obj,
11034 struct intel_engine_cs *ring,
11040 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11041 struct drm_crtc *crtc)
11043 struct drm_i915_private *dev_priv = dev->dev_private;
11044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11045 struct intel_unpin_work *work = intel_crtc->unpin_work;
11048 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11051 if (!work->enable_stall_check)
11054 if (work->flip_ready_vblank == 0) {
11055 if (work->flip_queued_req &&
11056 !i915_gem_request_completed(work->flip_queued_req, true))
11059 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11062 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11065 /* Potential stall - if we see that the flip has happened,
11066 * assume a missed interrupt. */
11067 if (INTEL_INFO(dev)->gen >= 4)
11068 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11070 addr = I915_READ(DSPADDR(intel_crtc->plane));
11072 /* There is a potential issue here with a false positive after a flip
11073 * to the same address. We could address this by checking for a
11074 * non-incrementing frame counter.
11076 return addr == work->gtt_offset;
11079 void intel_check_page_flip(struct drm_device *dev, int pipe)
11081 struct drm_i915_private *dev_priv = dev->dev_private;
11082 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11084 struct intel_unpin_work *work;
11086 WARN_ON(!in_interrupt());
11091 spin_lock(&dev->event_lock);
11092 work = intel_crtc->unpin_work;
11093 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11094 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11095 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11096 page_flip_completed(intel_crtc);
11099 if (work != NULL &&
11100 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11101 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11102 spin_unlock(&dev->event_lock);
11105 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11106 struct drm_framebuffer *fb,
11107 struct drm_pending_vblank_event *event,
11108 uint32_t page_flip_flags)
11110 struct drm_device *dev = crtc->dev;
11111 struct drm_i915_private *dev_priv = dev->dev_private;
11112 struct drm_framebuffer *old_fb = crtc->primary->fb;
11113 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11115 struct drm_plane *primary = crtc->primary;
11116 enum pipe pipe = intel_crtc->pipe;
11117 struct intel_unpin_work *work;
11118 struct intel_engine_cs *ring;
11123 * drm_mode_page_flip_ioctl() should already catch this, but double
11124 * check to be safe. In the future we may enable pageflipping from
11125 * a disabled primary plane.
11127 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11130 /* Can't change pixel format via MI display flips. */
11131 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11135 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11136 * Note that pitch changes could also affect these register.
11138 if (INTEL_INFO(dev)->gen > 3 &&
11139 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11140 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11143 if (i915_terminally_wedged(&dev_priv->gpu_error))
11146 work = kzalloc(sizeof(*work), GFP_KERNEL);
11150 work->event = event;
11152 work->old_fb = old_fb;
11153 INIT_WORK(&work->work, intel_unpin_work_fn);
11155 ret = drm_crtc_vblank_get(crtc);
11159 /* We borrow the event spin lock for protecting unpin_work */
11160 spin_lock_irq(&dev->event_lock);
11161 if (intel_crtc->unpin_work) {
11162 /* Before declaring the flip queue wedged, check if
11163 * the hardware completed the operation behind our backs.
11165 if (__intel_pageflip_stall_check(dev, crtc)) {
11166 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11167 page_flip_completed(intel_crtc);
11169 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11170 spin_unlock_irq(&dev->event_lock);
11172 drm_crtc_vblank_put(crtc);
11177 intel_crtc->unpin_work = work;
11178 spin_unlock_irq(&dev->event_lock);
11180 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11181 flush_workqueue(dev_priv->wq);
11183 /* Reference the objects for the scheduled work. */
11184 drm_framebuffer_reference(work->old_fb);
11185 drm_gem_object_reference(&obj->base);
11187 crtc->primary->fb = fb;
11188 update_state_fb(crtc->primary);
11190 work->pending_flip_obj = obj;
11192 ret = i915_mutex_lock_interruptible(dev);
11196 atomic_inc(&intel_crtc->unpin_work_count);
11197 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11199 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11200 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11202 if (IS_VALLEYVIEW(dev)) {
11203 ring = &dev_priv->ring[BCS];
11204 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11205 /* vlv: DISPLAY_FLIP fails to change tiling */
11207 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11208 ring = &dev_priv->ring[BCS];
11209 } else if (INTEL_INFO(dev)->gen >= 7) {
11210 ring = i915_gem_request_get_ring(obj->last_write_req);
11211 if (ring == NULL || ring->id != RCS)
11212 ring = &dev_priv->ring[BCS];
11214 ring = &dev_priv->ring[RCS];
11217 mmio_flip = use_mmio_flip(ring, obj);
11219 /* When using CS flips, we want to emit semaphores between rings.
11220 * However, when using mmio flips we will create a task to do the
11221 * synchronisation, so all we want here is to pin the framebuffer
11222 * into the display plane and skip any waits.
11224 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11225 crtc->primary->state,
11226 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11228 goto cleanup_pending;
11230 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11231 + intel_crtc->dspaddr_offset;
11234 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11237 goto cleanup_unpin;
11239 i915_gem_request_assign(&work->flip_queued_req,
11240 obj->last_write_req);
11242 if (obj->last_write_req) {
11243 ret = i915_gem_check_olr(obj->last_write_req);
11245 goto cleanup_unpin;
11248 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11251 goto cleanup_unpin;
11253 i915_gem_request_assign(&work->flip_queued_req,
11254 intel_ring_get_request(ring));
11257 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11258 work->enable_stall_check = true;
11260 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11261 INTEL_FRONTBUFFER_PRIMARY(pipe));
11263 intel_fbc_disable(dev);
11264 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11265 mutex_unlock(&dev->struct_mutex);
11267 trace_i915_flip_request(intel_crtc->plane, obj);
11272 intel_unpin_fb_obj(fb, crtc->primary->state);
11274 atomic_dec(&intel_crtc->unpin_work_count);
11275 mutex_unlock(&dev->struct_mutex);
11277 crtc->primary->fb = old_fb;
11278 update_state_fb(crtc->primary);
11280 drm_gem_object_unreference_unlocked(&obj->base);
11281 drm_framebuffer_unreference(work->old_fb);
11283 spin_lock_irq(&dev->event_lock);
11284 intel_crtc->unpin_work = NULL;
11285 spin_unlock_irq(&dev->event_lock);
11287 drm_crtc_vblank_put(crtc);
11293 ret = intel_plane_restore(primary);
11294 if (ret == 0 && event) {
11295 spin_lock_irq(&dev->event_lock);
11296 drm_send_vblank_event(dev, pipe, event);
11297 spin_unlock_irq(&dev->event_lock);
11303 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11304 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11305 .load_lut = intel_crtc_load_lut,
11306 .atomic_begin = intel_begin_crtc_commit,
11307 .atomic_flush = intel_finish_crtc_commit,
11311 * intel_modeset_update_staged_output_state
11313 * Updates the staged output configuration state, e.g. after we've read out the
11314 * current hw state.
11316 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11318 struct intel_crtc *crtc;
11319 struct intel_encoder *encoder;
11320 struct intel_connector *connector;
11322 for_each_intel_connector(dev, connector) {
11323 connector->new_encoder =
11324 to_intel_encoder(connector->base.encoder);
11327 for_each_intel_encoder(dev, encoder) {
11328 encoder->new_crtc =
11329 to_intel_crtc(encoder->base.crtc);
11332 for_each_intel_crtc(dev, crtc) {
11333 crtc->new_enabled = crtc->base.state->enable;
11337 /* Transitional helper to copy current connector/encoder state to
11338 * connector->state. This is needed so that code that is partially
11339 * converted to atomic does the right thing.
11341 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11343 struct intel_connector *connector;
11345 for_each_intel_connector(dev, connector) {
11346 if (connector->base.encoder) {
11347 connector->base.state->best_encoder =
11348 connector->base.encoder;
11349 connector->base.state->crtc =
11350 connector->base.encoder->crtc;
11352 connector->base.state->best_encoder = NULL;
11353 connector->base.state->crtc = NULL;
11358 /* Fixup legacy state after an atomic state swap.
11360 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11362 struct intel_crtc *crtc;
11363 struct intel_encoder *encoder;
11364 struct intel_connector *connector;
11366 for_each_intel_connector(state->dev, connector) {
11367 connector->base.encoder = connector->base.state->best_encoder;
11368 if (connector->base.encoder)
11369 connector->base.encoder->crtc =
11370 connector->base.state->crtc;
11373 /* Update crtc of disabled encoders */
11374 for_each_intel_encoder(state->dev, encoder) {
11375 int num_connectors = 0;
11377 for_each_intel_connector(state->dev, connector)
11378 if (connector->base.encoder == &encoder->base)
11381 if (num_connectors == 0)
11382 encoder->base.crtc = NULL;
11385 for_each_intel_crtc(state->dev, crtc) {
11386 crtc->base.enabled = crtc->base.state->enable;
11387 crtc->config = to_intel_crtc_state(crtc->base.state);
11392 connected_sink_compute_bpp(struct intel_connector *connector,
11393 struct intel_crtc_state *pipe_config)
11395 int bpp = pipe_config->pipe_bpp;
11397 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11398 connector->base.base.id,
11399 connector->base.name);
11401 /* Don't use an invalid EDID bpc value */
11402 if (connector->base.display_info.bpc &&
11403 connector->base.display_info.bpc * 3 < bpp) {
11404 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11405 bpp, connector->base.display_info.bpc*3);
11406 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11409 /* Clamp bpp to 8 on screens without EDID 1.4 */
11410 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11411 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11413 pipe_config->pipe_bpp = 24;
11418 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11419 struct intel_crtc_state *pipe_config)
11421 struct drm_device *dev = crtc->base.dev;
11422 struct drm_atomic_state *state;
11423 struct drm_connector *connector;
11424 struct drm_connector_state *connector_state;
11427 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11429 else if (INTEL_INFO(dev)->gen >= 5)
11435 pipe_config->pipe_bpp = bpp;
11437 state = pipe_config->base.state;
11439 /* Clamp display bpp to EDID value */
11440 for_each_connector_in_state(state, connector, connector_state, i) {
11441 if (connector_state->crtc != &crtc->base)
11444 connected_sink_compute_bpp(to_intel_connector(connector),
11451 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11453 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11454 "type: 0x%x flags: 0x%x\n",
11456 mode->crtc_hdisplay, mode->crtc_hsync_start,
11457 mode->crtc_hsync_end, mode->crtc_htotal,
11458 mode->crtc_vdisplay, mode->crtc_vsync_start,
11459 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11462 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11463 struct intel_crtc_state *pipe_config,
11464 const char *context)
11466 struct drm_device *dev = crtc->base.dev;
11467 struct drm_plane *plane;
11468 struct intel_plane *intel_plane;
11469 struct intel_plane_state *state;
11470 struct drm_framebuffer *fb;
11472 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11473 context, pipe_config, pipe_name(crtc->pipe));
11475 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11476 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11477 pipe_config->pipe_bpp, pipe_config->dither);
11478 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11479 pipe_config->has_pch_encoder,
11480 pipe_config->fdi_lanes,
11481 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11482 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11483 pipe_config->fdi_m_n.tu);
11484 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11485 pipe_config->has_dp_encoder,
11486 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11487 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11488 pipe_config->dp_m_n.tu);
11490 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11491 pipe_config->has_dp_encoder,
11492 pipe_config->dp_m2_n2.gmch_m,
11493 pipe_config->dp_m2_n2.gmch_n,
11494 pipe_config->dp_m2_n2.link_m,
11495 pipe_config->dp_m2_n2.link_n,
11496 pipe_config->dp_m2_n2.tu);
11498 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11499 pipe_config->has_audio,
11500 pipe_config->has_infoframe);
11502 DRM_DEBUG_KMS("requested mode:\n");
11503 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11504 DRM_DEBUG_KMS("adjusted mode:\n");
11505 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11506 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11507 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11508 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11509 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11510 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11512 pipe_config->scaler_state.scaler_users,
11513 pipe_config->scaler_state.scaler_id);
11514 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11515 pipe_config->gmch_pfit.control,
11516 pipe_config->gmch_pfit.pgm_ratios,
11517 pipe_config->gmch_pfit.lvds_border_bits);
11518 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11519 pipe_config->pch_pfit.pos,
11520 pipe_config->pch_pfit.size,
11521 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11522 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11523 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11525 if (IS_BROXTON(dev)) {
11526 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11527 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11528 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11529 pipe_config->ddi_pll_sel,
11530 pipe_config->dpll_hw_state.ebb0,
11531 pipe_config->dpll_hw_state.pll0,
11532 pipe_config->dpll_hw_state.pll1,
11533 pipe_config->dpll_hw_state.pll2,
11534 pipe_config->dpll_hw_state.pll3,
11535 pipe_config->dpll_hw_state.pll6,
11536 pipe_config->dpll_hw_state.pll8,
11537 pipe_config->dpll_hw_state.pcsdw12);
11538 } else if (IS_SKYLAKE(dev)) {
11539 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11540 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11541 pipe_config->ddi_pll_sel,
11542 pipe_config->dpll_hw_state.ctrl1,
11543 pipe_config->dpll_hw_state.cfgcr1,
11544 pipe_config->dpll_hw_state.cfgcr2);
11545 } else if (HAS_DDI(dev)) {
11546 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11547 pipe_config->ddi_pll_sel,
11548 pipe_config->dpll_hw_state.wrpll);
11550 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11551 "fp0: 0x%x, fp1: 0x%x\n",
11552 pipe_config->dpll_hw_state.dpll,
11553 pipe_config->dpll_hw_state.dpll_md,
11554 pipe_config->dpll_hw_state.fp0,
11555 pipe_config->dpll_hw_state.fp1);
11558 DRM_DEBUG_KMS("planes on this crtc\n");
11559 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11560 intel_plane = to_intel_plane(plane);
11561 if (intel_plane->pipe != crtc->pipe)
11564 state = to_intel_plane_state(plane->state);
11565 fb = state->base.fb;
11567 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11568 "disabled, scaler_id = %d\n",
11569 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11570 plane->base.id, intel_plane->pipe,
11571 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11572 drm_plane_index(plane), state->scaler_id);
11576 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11577 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11578 plane->base.id, intel_plane->pipe,
11579 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11580 drm_plane_index(plane));
11581 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11582 fb->base.id, fb->width, fb->height, fb->pixel_format);
11583 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11585 state->src.x1 >> 16, state->src.y1 >> 16,
11586 drm_rect_width(&state->src) >> 16,
11587 drm_rect_height(&state->src) >> 16,
11588 state->dst.x1, state->dst.y1,
11589 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11593 static bool encoders_cloneable(const struct intel_encoder *a,
11594 const struct intel_encoder *b)
11596 /* masks could be asymmetric, so check both ways */
11597 return a == b || (a->cloneable & (1 << b->type) &&
11598 b->cloneable & (1 << a->type));
11601 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11602 struct intel_crtc *crtc,
11603 struct intel_encoder *encoder)
11605 struct intel_encoder *source_encoder;
11606 struct drm_connector *connector;
11607 struct drm_connector_state *connector_state;
11610 for_each_connector_in_state(state, connector, connector_state, i) {
11611 if (connector_state->crtc != &crtc->base)
11615 to_intel_encoder(connector_state->best_encoder);
11616 if (!encoders_cloneable(encoder, source_encoder))
11623 static bool check_encoder_cloning(struct drm_atomic_state *state,
11624 struct intel_crtc *crtc)
11626 struct intel_encoder *encoder;
11627 struct drm_connector *connector;
11628 struct drm_connector_state *connector_state;
11631 for_each_connector_in_state(state, connector, connector_state, i) {
11632 if (connector_state->crtc != &crtc->base)
11635 encoder = to_intel_encoder(connector_state->best_encoder);
11636 if (!check_single_encoder_cloning(state, crtc, encoder))
11643 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11645 struct drm_device *dev = state->dev;
11646 struct intel_encoder *encoder;
11647 struct drm_connector *connector;
11648 struct drm_connector_state *connector_state;
11649 unsigned int used_ports = 0;
11653 * Walk the connector list instead of the encoder
11654 * list to detect the problem on ddi platforms
11655 * where there's just one encoder per digital port.
11657 for_each_connector_in_state(state, connector, connector_state, i) {
11658 if (!connector_state->best_encoder)
11661 encoder = to_intel_encoder(connector_state->best_encoder);
11663 WARN_ON(!connector_state->crtc);
11665 switch (encoder->type) {
11666 unsigned int port_mask;
11667 case INTEL_OUTPUT_UNKNOWN:
11668 if (WARN_ON(!HAS_DDI(dev)))
11670 case INTEL_OUTPUT_DISPLAYPORT:
11671 case INTEL_OUTPUT_HDMI:
11672 case INTEL_OUTPUT_EDP:
11673 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11675 /* the same port mustn't appear more than once */
11676 if (used_ports & port_mask)
11679 used_ports |= port_mask;
11689 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11691 struct drm_crtc_state tmp_state;
11692 struct intel_crtc_scaler_state scaler_state;
11693 struct intel_dpll_hw_state dpll_hw_state;
11694 enum intel_dpll_id shared_dpll;
11695 uint32_t ddi_pll_sel;
11697 /* FIXME: before the switch to atomic started, a new pipe_config was
11698 * kzalloc'd. Code that depends on any field being zero should be
11699 * fixed, so that the crtc_state can be safely duplicated. For now,
11700 * only fields that are know to not cause problems are preserved. */
11702 tmp_state = crtc_state->base;
11703 scaler_state = crtc_state->scaler_state;
11704 shared_dpll = crtc_state->shared_dpll;
11705 dpll_hw_state = crtc_state->dpll_hw_state;
11706 ddi_pll_sel = crtc_state->ddi_pll_sel;
11708 memset(crtc_state, 0, sizeof *crtc_state);
11710 crtc_state->base = tmp_state;
11711 crtc_state->scaler_state = scaler_state;
11712 crtc_state->shared_dpll = shared_dpll;
11713 crtc_state->dpll_hw_state = dpll_hw_state;
11714 crtc_state->ddi_pll_sel = ddi_pll_sel;
11718 intel_modeset_pipe_config(struct drm_crtc *crtc,
11719 struct drm_atomic_state *state,
11720 struct intel_crtc_state *pipe_config)
11722 struct intel_encoder *encoder;
11723 struct drm_connector *connector;
11724 struct drm_connector_state *connector_state;
11725 int base_bpp, ret = -EINVAL;
11729 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11730 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11734 if (!check_digital_port_conflicts(state)) {
11735 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11739 clear_intel_crtc_state(pipe_config);
11741 pipe_config->cpu_transcoder =
11742 (enum transcoder) to_intel_crtc(crtc)->pipe;
11745 * Sanitize sync polarity flags based on requested ones. If neither
11746 * positive or negative polarity is requested, treat this as meaning
11747 * negative polarity.
11749 if (!(pipe_config->base.adjusted_mode.flags &
11750 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11751 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11753 if (!(pipe_config->base.adjusted_mode.flags &
11754 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11755 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11757 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11758 * plane pixel format and any sink constraints into account. Returns the
11759 * source plane bpp so that dithering can be selected on mismatches
11760 * after encoders and crtc also have had their say. */
11761 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11767 * Determine the real pipe dimensions. Note that stereo modes can
11768 * increase the actual pipe size due to the frame doubling and
11769 * insertion of additional space for blanks between the frame. This
11770 * is stored in the crtc timings. We use the requested mode to do this
11771 * computation to clearly distinguish it from the adjusted mode, which
11772 * can be changed by the connectors in the below retry loop.
11774 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11775 &pipe_config->pipe_src_w,
11776 &pipe_config->pipe_src_h);
11779 /* Ensure the port clock defaults are reset when retrying. */
11780 pipe_config->port_clock = 0;
11781 pipe_config->pixel_multiplier = 1;
11783 /* Fill in default crtc timings, allow encoders to overwrite them. */
11784 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11785 CRTC_STEREO_DOUBLE);
11787 /* Pass our mode to the connectors and the CRTC to give them a chance to
11788 * adjust it according to limitations or connector properties, and also
11789 * a chance to reject the mode entirely.
11791 for_each_connector_in_state(state, connector, connector_state, i) {
11792 if (connector_state->crtc != crtc)
11795 encoder = to_intel_encoder(connector_state->best_encoder);
11797 if (!(encoder->compute_config(encoder, pipe_config))) {
11798 DRM_DEBUG_KMS("Encoder config failure\n");
11803 /* Set default port clock if not overwritten by the encoder. Needs to be
11804 * done afterwards in case the encoder adjusts the mode. */
11805 if (!pipe_config->port_clock)
11806 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11807 * pipe_config->pixel_multiplier;
11809 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11811 DRM_DEBUG_KMS("CRTC fixup failed\n");
11815 if (ret == RETRY) {
11816 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11821 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11823 goto encoder_retry;
11826 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11827 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11828 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11835 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11837 struct drm_encoder *encoder;
11838 struct drm_device *dev = crtc->dev;
11840 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11841 if (encoder->crtc == crtc)
11848 needs_modeset(struct drm_crtc_state *state)
11850 return state->mode_changed || state->active_changed;
11854 intel_modeset_update_state(struct drm_atomic_state *state)
11856 struct drm_device *dev = state->dev;
11857 struct drm_i915_private *dev_priv = dev->dev_private;
11858 struct intel_encoder *intel_encoder;
11859 struct drm_crtc *crtc;
11860 struct drm_crtc_state *crtc_state;
11861 struct drm_connector *connector;
11864 intel_shared_dpll_commit(dev_priv);
11866 for_each_intel_encoder(dev, intel_encoder) {
11867 if (!intel_encoder->base.crtc)
11870 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11871 if (crtc != intel_encoder->base.crtc)
11874 if (crtc_state->enable && needs_modeset(crtc_state))
11875 intel_encoder->connectors_active = false;
11881 drm_atomic_helper_swap_state(state->dev, state);
11882 intel_modeset_fixup_state(state);
11884 /* Double check state. */
11885 for_each_crtc(dev, crtc) {
11886 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11889 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11890 if (!connector->encoder || !connector->encoder->crtc)
11893 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11894 if (crtc != connector->encoder->crtc)
11897 if (crtc->state->enable && needs_modeset(crtc->state)) {
11898 struct drm_property *dpms_property =
11899 dev->mode_config.dpms_property;
11901 connector->dpms = DRM_MODE_DPMS_ON;
11902 drm_object_property_set_value(&connector->base,
11906 intel_encoder = to_intel_encoder(connector->encoder);
11907 intel_encoder->connectors_active = true;
11916 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11920 if (clock1 == clock2)
11923 if (!clock1 || !clock2)
11926 diff = abs(clock1 - clock2);
11928 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11934 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11935 list_for_each_entry((intel_crtc), \
11936 &(dev)->mode_config.crtc_list, \
11938 if (mask & (1 <<(intel_crtc)->pipe))
11941 intel_pipe_config_compare(struct drm_device *dev,
11942 struct intel_crtc_state *current_config,
11943 struct intel_crtc_state *pipe_config)
11945 #define PIPE_CONF_CHECK_X(name) \
11946 if (current_config->name != pipe_config->name) { \
11947 DRM_ERROR("mismatch in " #name " " \
11948 "(expected 0x%08x, found 0x%08x)\n", \
11949 current_config->name, \
11950 pipe_config->name); \
11954 #define PIPE_CONF_CHECK_I(name) \
11955 if (current_config->name != pipe_config->name) { \
11956 DRM_ERROR("mismatch in " #name " " \
11957 "(expected %i, found %i)\n", \
11958 current_config->name, \
11959 pipe_config->name); \
11963 /* This is required for BDW+ where there is only one set of registers for
11964 * switching between high and low RR.
11965 * This macro can be used whenever a comparison has to be made between one
11966 * hw state and multiple sw state variables.
11968 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11969 if ((current_config->name != pipe_config->name) && \
11970 (current_config->alt_name != pipe_config->name)) { \
11971 DRM_ERROR("mismatch in " #name " " \
11972 "(expected %i or %i, found %i)\n", \
11973 current_config->name, \
11974 current_config->alt_name, \
11975 pipe_config->name); \
11979 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11980 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11981 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11982 "(expected %i, found %i)\n", \
11983 current_config->name & (mask), \
11984 pipe_config->name & (mask)); \
11988 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11989 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11990 DRM_ERROR("mismatch in " #name " " \
11991 "(expected %i, found %i)\n", \
11992 current_config->name, \
11993 pipe_config->name); \
11997 #define PIPE_CONF_QUIRK(quirk) \
11998 ((current_config->quirks | pipe_config->quirks) & (quirk))
12000 PIPE_CONF_CHECK_I(cpu_transcoder);
12002 PIPE_CONF_CHECK_I(has_pch_encoder);
12003 PIPE_CONF_CHECK_I(fdi_lanes);
12004 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12005 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12006 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12007 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12008 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12010 PIPE_CONF_CHECK_I(has_dp_encoder);
12012 if (INTEL_INFO(dev)->gen < 8) {
12013 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12014 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12015 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12016 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12017 PIPE_CONF_CHECK_I(dp_m_n.tu);
12019 if (current_config->has_drrs) {
12020 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12021 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12022 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12023 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12024 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12027 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12028 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12029 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12030 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12031 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12034 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12035 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12036 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12037 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12038 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12045 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12048 PIPE_CONF_CHECK_I(pixel_multiplier);
12049 PIPE_CONF_CHECK_I(has_hdmi_sink);
12050 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12051 IS_VALLEYVIEW(dev))
12052 PIPE_CONF_CHECK_I(limited_color_range);
12053 PIPE_CONF_CHECK_I(has_infoframe);
12055 PIPE_CONF_CHECK_I(has_audio);
12057 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12058 DRM_MODE_FLAG_INTERLACE);
12060 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12061 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12062 DRM_MODE_FLAG_PHSYNC);
12063 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12064 DRM_MODE_FLAG_NHSYNC);
12065 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12066 DRM_MODE_FLAG_PVSYNC);
12067 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12068 DRM_MODE_FLAG_NVSYNC);
12071 PIPE_CONF_CHECK_I(pipe_src_w);
12072 PIPE_CONF_CHECK_I(pipe_src_h);
12075 * FIXME: BIOS likes to set up a cloned config with lvds+external
12076 * screen. Since we don't yet re-compute the pipe config when moving
12077 * just the lvds port away to another pipe the sw tracking won't match.
12079 * Proper atomic modesets with recomputed global state will fix this.
12080 * Until then just don't check gmch state for inherited modes.
12082 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12083 PIPE_CONF_CHECK_I(gmch_pfit.control);
12084 /* pfit ratios are autocomputed by the hw on gen4+ */
12085 if (INTEL_INFO(dev)->gen < 4)
12086 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12087 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12090 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12091 if (current_config->pch_pfit.enabled) {
12092 PIPE_CONF_CHECK_I(pch_pfit.pos);
12093 PIPE_CONF_CHECK_I(pch_pfit.size);
12096 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12098 /* BDW+ don't expose a synchronous way to read the state */
12099 if (IS_HASWELL(dev))
12100 PIPE_CONF_CHECK_I(ips_enabled);
12102 PIPE_CONF_CHECK_I(double_wide);
12104 PIPE_CONF_CHECK_X(ddi_pll_sel);
12106 PIPE_CONF_CHECK_I(shared_dpll);
12107 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12108 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12109 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12110 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12111 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12112 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12113 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12114 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12116 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12117 PIPE_CONF_CHECK_I(pipe_bpp);
12119 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12120 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12122 #undef PIPE_CONF_CHECK_X
12123 #undef PIPE_CONF_CHECK_I
12124 #undef PIPE_CONF_CHECK_I_ALT
12125 #undef PIPE_CONF_CHECK_FLAGS
12126 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12127 #undef PIPE_CONF_QUIRK
12132 static void check_wm_state(struct drm_device *dev)
12134 struct drm_i915_private *dev_priv = dev->dev_private;
12135 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12136 struct intel_crtc *intel_crtc;
12139 if (INTEL_INFO(dev)->gen < 9)
12142 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12143 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12145 for_each_intel_crtc(dev, intel_crtc) {
12146 struct skl_ddb_entry *hw_entry, *sw_entry;
12147 const enum pipe pipe = intel_crtc->pipe;
12149 if (!intel_crtc->active)
12153 for_each_plane(dev_priv, pipe, plane) {
12154 hw_entry = &hw_ddb.plane[pipe][plane];
12155 sw_entry = &sw_ddb->plane[pipe][plane];
12157 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12160 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12161 "(expected (%u,%u), found (%u,%u))\n",
12162 pipe_name(pipe), plane + 1,
12163 sw_entry->start, sw_entry->end,
12164 hw_entry->start, hw_entry->end);
12168 hw_entry = &hw_ddb.cursor[pipe];
12169 sw_entry = &sw_ddb->cursor[pipe];
12171 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12174 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12175 "(expected (%u,%u), found (%u,%u))\n",
12177 sw_entry->start, sw_entry->end,
12178 hw_entry->start, hw_entry->end);
12183 check_connector_state(struct drm_device *dev)
12185 struct intel_connector *connector;
12187 for_each_intel_connector(dev, connector) {
12188 /* This also checks the encoder/connector hw state with the
12189 * ->get_hw_state callbacks. */
12190 intel_connector_check_state(connector);
12192 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12193 "connector's staged encoder doesn't match current encoder\n");
12198 check_encoder_state(struct drm_device *dev)
12200 struct intel_encoder *encoder;
12201 struct intel_connector *connector;
12203 for_each_intel_encoder(dev, encoder) {
12204 bool enabled = false;
12205 bool active = false;
12206 enum pipe pipe, tracked_pipe;
12208 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12209 encoder->base.base.id,
12210 encoder->base.name);
12212 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12213 "encoder's stage crtc doesn't match current crtc\n");
12214 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12215 "encoder's active_connectors set, but no crtc\n");
12217 for_each_intel_connector(dev, connector) {
12218 if (connector->base.encoder != &encoder->base)
12221 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12225 * for MST connectors if we unplug the connector is gone
12226 * away but the encoder is still connected to a crtc
12227 * until a modeset happens in response to the hotplug.
12229 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12232 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12233 "encoder's enabled state mismatch "
12234 "(expected %i, found %i)\n",
12235 !!encoder->base.crtc, enabled);
12236 I915_STATE_WARN(active && !encoder->base.crtc,
12237 "active encoder with no crtc\n");
12239 I915_STATE_WARN(encoder->connectors_active != active,
12240 "encoder's computed active state doesn't match tracked active state "
12241 "(expected %i, found %i)\n", active, encoder->connectors_active);
12243 active = encoder->get_hw_state(encoder, &pipe);
12244 I915_STATE_WARN(active != encoder->connectors_active,
12245 "encoder's hw state doesn't match sw tracking "
12246 "(expected %i, found %i)\n",
12247 encoder->connectors_active, active);
12249 if (!encoder->base.crtc)
12252 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12253 I915_STATE_WARN(active && pipe != tracked_pipe,
12254 "active encoder's pipe doesn't match"
12255 "(expected %i, found %i)\n",
12256 tracked_pipe, pipe);
12262 check_crtc_state(struct drm_device *dev)
12264 struct drm_i915_private *dev_priv = dev->dev_private;
12265 struct intel_crtc *crtc;
12266 struct intel_encoder *encoder;
12267 struct intel_crtc_state pipe_config;
12269 for_each_intel_crtc(dev, crtc) {
12270 bool enabled = false;
12271 bool active = false;
12273 memset(&pipe_config, 0, sizeof(pipe_config));
12275 DRM_DEBUG_KMS("[CRTC:%d]\n",
12276 crtc->base.base.id);
12278 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12279 "active crtc, but not enabled in sw tracking\n");
12281 for_each_intel_encoder(dev, encoder) {
12282 if (encoder->base.crtc != &crtc->base)
12285 if (encoder->connectors_active)
12289 I915_STATE_WARN(active != crtc->active,
12290 "crtc's computed active state doesn't match tracked active state "
12291 "(expected %i, found %i)\n", active, crtc->active);
12292 I915_STATE_WARN(enabled != crtc->base.state->enable,
12293 "crtc's computed enabled state doesn't match tracked enabled state "
12294 "(expected %i, found %i)\n", enabled,
12295 crtc->base.state->enable);
12297 active = dev_priv->display.get_pipe_config(crtc,
12300 /* hw state is inconsistent with the pipe quirk */
12301 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12302 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12303 active = crtc->active;
12305 for_each_intel_encoder(dev, encoder) {
12307 if (encoder->base.crtc != &crtc->base)
12309 if (encoder->get_hw_state(encoder, &pipe))
12310 encoder->get_config(encoder, &pipe_config);
12313 I915_STATE_WARN(crtc->active != active,
12314 "crtc active state doesn't match with hw state "
12315 "(expected %i, found %i)\n", crtc->active, active);
12318 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12319 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12320 intel_dump_pipe_config(crtc, &pipe_config,
12322 intel_dump_pipe_config(crtc, crtc->config,
12329 check_shared_dpll_state(struct drm_device *dev)
12331 struct drm_i915_private *dev_priv = dev->dev_private;
12332 struct intel_crtc *crtc;
12333 struct intel_dpll_hw_state dpll_hw_state;
12336 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12337 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12338 int enabled_crtcs = 0, active_crtcs = 0;
12341 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12343 DRM_DEBUG_KMS("%s\n", pll->name);
12345 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12347 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12348 "more active pll users than references: %i vs %i\n",
12349 pll->active, hweight32(pll->config.crtc_mask));
12350 I915_STATE_WARN(pll->active && !pll->on,
12351 "pll in active use but not on in sw tracking\n");
12352 I915_STATE_WARN(pll->on && !pll->active,
12353 "pll in on but not on in use in sw tracking\n");
12354 I915_STATE_WARN(pll->on != active,
12355 "pll on state mismatch (expected %i, found %i)\n",
12358 for_each_intel_crtc(dev, crtc) {
12359 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12361 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12364 I915_STATE_WARN(pll->active != active_crtcs,
12365 "pll active crtcs mismatch (expected %i, found %i)\n",
12366 pll->active, active_crtcs);
12367 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12368 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12369 hweight32(pll->config.crtc_mask), enabled_crtcs);
12371 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12372 sizeof(dpll_hw_state)),
12373 "pll hw state mismatch\n");
12378 intel_modeset_check_state(struct drm_device *dev)
12380 check_wm_state(dev);
12381 check_connector_state(dev);
12382 check_encoder_state(dev);
12383 check_crtc_state(dev);
12384 check_shared_dpll_state(dev);
12387 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12391 * FDI already provided one idea for the dotclock.
12392 * Yell if the encoder disagrees.
12394 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12395 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12396 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12399 static void update_scanline_offset(struct intel_crtc *crtc)
12401 struct drm_device *dev = crtc->base.dev;
12404 * The scanline counter increments at the leading edge of hsync.
12406 * On most platforms it starts counting from vtotal-1 on the
12407 * first active line. That means the scanline counter value is
12408 * always one less than what we would expect. Ie. just after
12409 * start of vblank, which also occurs at start of hsync (on the
12410 * last active line), the scanline counter will read vblank_start-1.
12412 * On gen2 the scanline counter starts counting from 1 instead
12413 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12414 * to keep the value positive), instead of adding one.
12416 * On HSW+ the behaviour of the scanline counter depends on the output
12417 * type. For DP ports it behaves like most other platforms, but on HDMI
12418 * there's an extra 1 line difference. So we need to add two instead of
12419 * one to the value.
12421 if (IS_GEN2(dev)) {
12422 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12425 vtotal = mode->crtc_vtotal;
12426 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12429 crtc->scanline_offset = vtotal - 1;
12430 } else if (HAS_DDI(dev) &&
12431 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12432 crtc->scanline_offset = 2;
12434 crtc->scanline_offset = 1;
12437 static struct intel_crtc_state *
12438 intel_modeset_compute_config(struct drm_crtc *crtc,
12439 struct drm_atomic_state *state)
12441 struct intel_crtc_state *pipe_config;
12444 ret = drm_atomic_add_affected_connectors(state, crtc);
12446 return ERR_PTR(ret);
12448 ret = drm_atomic_helper_check_modeset(state->dev, state);
12450 return ERR_PTR(ret);
12453 * Note this needs changes when we start tracking multiple modes
12454 * and crtcs. At that point we'll need to compute the whole config
12455 * (i.e. one pipe_config for each crtc) rather than just the one
12458 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12459 if (IS_ERR(pipe_config))
12460 return pipe_config;
12462 if (!pipe_config->base.enable)
12463 return pipe_config;
12465 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12467 return ERR_PTR(ret);
12469 /* Check things that can only be changed through modeset */
12470 if (pipe_config->has_audio !=
12471 to_intel_crtc(crtc)->config->has_audio)
12472 pipe_config->base.mode_changed = true;
12475 * Note we have an issue here with infoframes: current code
12476 * only updates them on the full mode set path per hw
12477 * requirements. So here we should be checking for any
12478 * required changes and forcing a mode set.
12481 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12483 ret = drm_atomic_helper_check_planes(state->dev, state);
12485 return ERR_PTR(ret);
12487 return pipe_config;
12490 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12492 struct drm_device *dev = state->dev;
12493 struct drm_i915_private *dev_priv = to_i915(dev);
12494 unsigned clear_pipes = 0;
12495 struct intel_crtc *intel_crtc;
12496 struct intel_crtc_state *intel_crtc_state;
12497 struct drm_crtc *crtc;
12498 struct drm_crtc_state *crtc_state;
12502 if (!dev_priv->display.crtc_compute_clock)
12505 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12506 intel_crtc = to_intel_crtc(crtc);
12507 intel_crtc_state = to_intel_crtc_state(crtc_state);
12509 if (needs_modeset(crtc_state)) {
12510 clear_pipes |= 1 << intel_crtc->pipe;
12511 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12515 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12519 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12520 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12523 intel_crtc = to_intel_crtc(crtc);
12524 intel_crtc_state = to_intel_crtc_state(crtc_state);
12526 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12529 intel_shared_dpll_abort_config(dev_priv);
12538 /* Code that should eventually be part of atomic_check() */
12539 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12541 struct drm_device *dev = state->dev;
12545 * See if the config requires any additional preparation, e.g.
12546 * to adjust global state with pipes off. We need to do this
12547 * here so we can get the modeset_pipe updated config for the new
12548 * mode set on this crtc. For other crtcs we need to use the
12549 * adjusted_mode bits in the crtc directly.
12551 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12552 ret = valleyview_modeset_global_pipes(state);
12557 ret = __intel_set_mode_setup_plls(state);
12564 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12565 struct intel_crtc_state *pipe_config)
12567 struct drm_device *dev = modeset_crtc->dev;
12568 struct drm_i915_private *dev_priv = dev->dev_private;
12569 struct drm_atomic_state *state = pipe_config->base.state;
12570 struct drm_crtc *crtc;
12571 struct drm_crtc_state *crtc_state;
12575 ret = __intel_set_mode_checks(state);
12579 ret = drm_atomic_helper_prepare_planes(dev, state);
12583 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12584 if (!needs_modeset(crtc_state))
12587 if (!crtc_state->enable) {
12588 intel_crtc_disable(crtc);
12589 } else if (crtc->state->enable) {
12590 intel_crtc_disable_planes(crtc);
12591 dev_priv->display.crtc_disable(crtc);
12595 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12596 * to set it here already despite that we pass it down the callchain.
12598 * Note we'll need to fix this up when we start tracking multiple
12599 * pipes; here we assume a single modeset_pipe and only track the
12600 * single crtc and mode.
12602 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12603 modeset_crtc->mode = pipe_config->base.mode;
12606 * Calculate and store various constants which
12607 * are later needed by vblank and swap-completion
12608 * timestamping. They are derived from true hwmode.
12610 drm_calc_timestamping_constants(modeset_crtc,
12611 &pipe_config->base.adjusted_mode);
12614 /* Only after disabling all output pipelines that will be changed can we
12615 * update the the output configuration. */
12616 intel_modeset_update_state(state);
12618 /* The state has been swaped above, so state actually contains the
12619 * old state now. */
12621 modeset_update_crtc_power_domains(state);
12623 drm_atomic_helper_commit_planes(dev, state);
12625 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12626 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12627 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12630 update_scanline_offset(to_intel_crtc(crtc));
12632 dev_priv->display.crtc_enable(crtc);
12633 intel_crtc_enable_planes(crtc);
12636 /* FIXME: add subpixel order */
12638 drm_atomic_helper_cleanup_planes(dev, state);
12640 drm_atomic_state_free(state);
12645 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12646 struct intel_crtc_state *pipe_config,
12647 bool force_restore)
12651 ret = __intel_set_mode(crtc, pipe_config);
12653 if (ret == 0 && force_restore) {
12654 intel_modeset_update_staged_output_state(crtc->dev);
12655 intel_modeset_check_state(crtc->dev);
12661 static int intel_set_mode(struct drm_crtc *crtc,
12662 struct drm_atomic_state *state,
12663 bool force_restore)
12665 struct intel_crtc_state *pipe_config;
12668 pipe_config = intel_modeset_compute_config(crtc, state);
12669 if (IS_ERR(pipe_config)) {
12670 ret = PTR_ERR(pipe_config);
12674 ret = intel_set_mode_with_config(crtc, pipe_config, force_restore);
12682 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12684 struct drm_device *dev = crtc->dev;
12685 struct drm_atomic_state *state;
12686 struct intel_encoder *encoder;
12687 struct intel_connector *connector;
12688 struct drm_connector_state *connector_state;
12689 struct intel_crtc_state *crtc_state;
12692 state = drm_atomic_state_alloc(dev);
12694 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12699 state->acquire_ctx = dev->mode_config.acquire_ctx;
12701 /* The force restore path in the HW readout code relies on the staged
12702 * config still keeping the user requested config while the actual
12703 * state has been overwritten by the configuration read from HW. We
12704 * need to copy the staged config to the atomic state, otherwise the
12705 * mode set will just reapply the state the HW is already in. */
12706 for_each_intel_encoder(dev, encoder) {
12707 if (&encoder->new_crtc->base != crtc)
12710 for_each_intel_connector(dev, connector) {
12711 if (connector->new_encoder != encoder)
12714 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12715 if (IS_ERR(connector_state)) {
12716 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12717 connector->base.base.id,
12718 connector->base.name,
12719 PTR_ERR(connector_state));
12723 connector_state->crtc = crtc;
12724 connector_state->best_encoder = &encoder->base;
12728 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12729 if (IS_ERR(crtc_state)) {
12730 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12731 crtc->base.id, PTR_ERR(crtc_state));
12732 drm_atomic_state_free(state);
12736 crtc_state->base.active = crtc_state->base.enable =
12737 to_intel_crtc(crtc)->new_enabled;
12739 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12741 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12742 crtc->primary->fb, crtc->x, crtc->y);
12744 ret = intel_set_mode(crtc, state, false);
12746 drm_atomic_state_free(state);
12749 #undef for_each_intel_crtc_masked
12751 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12752 struct drm_mode_set *set)
12756 for (ro = 0; ro < set->num_connectors; ro++)
12757 if (set->connectors[ro] == &connector->base)
12764 intel_modeset_stage_output_state(struct drm_device *dev,
12765 struct drm_mode_set *set,
12766 struct drm_atomic_state *state)
12768 struct intel_connector *connector;
12769 struct drm_connector *drm_connector;
12770 struct drm_connector_state *connector_state;
12771 struct drm_crtc *crtc;
12772 struct drm_crtc_state *crtc_state;
12775 /* The upper layers ensure that we either disable a crtc or have a list
12776 * of connectors. For paranoia, double-check this. */
12777 WARN_ON(!set->fb && (set->num_connectors != 0));
12778 WARN_ON(set->fb && (set->num_connectors == 0));
12780 for_each_intel_connector(dev, connector) {
12781 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12783 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12787 drm_atomic_get_connector_state(state, &connector->base);
12788 if (IS_ERR(connector_state))
12789 return PTR_ERR(connector_state);
12792 int pipe = to_intel_crtc(set->crtc)->pipe;
12793 connector_state->best_encoder =
12794 &intel_find_encoder(connector, pipe)->base;
12797 if (connector->base.state->crtc != set->crtc)
12800 /* If we disable the crtc, disable all its connectors. Also, if
12801 * the connector is on the changing crtc but not on the new
12802 * connector list, disable it. */
12803 if (!set->fb || !in_mode_set) {
12804 connector_state->best_encoder = NULL;
12806 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12807 connector->base.base.id,
12808 connector->base.name);
12811 /* connector->new_encoder is now updated for all connectors. */
12813 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12814 connector = to_intel_connector(drm_connector);
12816 if (!connector_state->best_encoder) {
12817 ret = drm_atomic_set_crtc_for_connector(connector_state,
12825 if (intel_connector_in_mode_set(connector, set)) {
12826 struct drm_crtc *crtc = connector->base.state->crtc;
12828 /* If this connector was in a previous crtc, add it
12829 * to the state. We might need to disable it. */
12832 drm_atomic_get_crtc_state(state, crtc);
12833 if (IS_ERR(crtc_state))
12834 return PTR_ERR(crtc_state);
12837 ret = drm_atomic_set_crtc_for_connector(connector_state,
12843 /* Make sure the new CRTC will work with the encoder */
12844 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12845 connector_state->crtc)) {
12849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12850 connector->base.base.id,
12851 connector->base.name,
12852 connector_state->crtc->base.id);
12854 if (connector_state->best_encoder != &connector->encoder->base)
12855 connector->encoder =
12856 to_intel_encoder(connector_state->best_encoder);
12859 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12860 bool has_connectors;
12862 ret = drm_atomic_add_affected_connectors(state, crtc);
12866 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12867 if (has_connectors != crtc_state->enable)
12868 crtc_state->enable =
12869 crtc_state->active = has_connectors;
12872 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12873 set->fb, set->x, set->y);
12877 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12878 if (IS_ERR(crtc_state))
12879 return PTR_ERR(crtc_state);
12882 drm_mode_copy(&crtc_state->mode, set->mode);
12884 if (set->num_connectors)
12885 crtc_state->active = true;
12890 static bool primary_plane_visible(struct drm_crtc *crtc)
12892 struct intel_plane_state *plane_state =
12893 to_intel_plane_state(crtc->primary->state);
12895 return plane_state->visible;
12898 static int intel_crtc_set_config(struct drm_mode_set *set)
12900 struct drm_device *dev;
12901 struct drm_atomic_state *state = NULL;
12902 struct intel_crtc_state *pipe_config;
12903 bool primary_plane_was_visible;
12907 BUG_ON(!set->crtc);
12908 BUG_ON(!set->crtc->helper_private);
12910 /* Enforce sane interface api - has been abused by the fb helper. */
12911 BUG_ON(!set->mode && set->fb);
12912 BUG_ON(set->fb && set->num_connectors == 0);
12915 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12916 set->crtc->base.id, set->fb->base.id,
12917 (int)set->num_connectors, set->x, set->y);
12919 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12922 dev = set->crtc->dev;
12924 state = drm_atomic_state_alloc(dev);
12928 state->acquire_ctx = dev->mode_config.acquire_ctx;
12930 ret = intel_modeset_stage_output_state(dev, set, state);
12934 pipe_config = intel_modeset_compute_config(set->crtc, state);
12935 if (IS_ERR(pipe_config)) {
12936 ret = PTR_ERR(pipe_config);
12940 intel_update_pipe_size(to_intel_crtc(set->crtc));
12942 primary_plane_was_visible = primary_plane_visible(set->crtc);
12944 ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
12947 pipe_config->base.enable &&
12948 pipe_config->base.planes_changed &&
12949 !needs_modeset(&pipe_config->base)) {
12950 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12953 * We need to make sure the primary plane is re-enabled if it
12954 * has previously been turned off.
12956 if (ret == 0 && !primary_plane_was_visible &&
12957 primary_plane_visible(set->crtc)) {
12958 WARN_ON(!intel_crtc->active);
12959 intel_post_enable_primary(set->crtc);
12963 * In the fastboot case this may be our only check of the
12964 * state after boot. It would be better to only do it on
12965 * the first update, but we don't have a nice way of doing that
12966 * (and really, set_config isn't used much for high freq page
12967 * flipping, so increasing its cost here shouldn't be a big
12970 if (i915.fastboot && ret == 0)
12971 intel_modeset_check_state(set->crtc->dev);
12975 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12976 set->crtc->base.id, ret);
12981 drm_atomic_state_free(state);
12985 static const struct drm_crtc_funcs intel_crtc_funcs = {
12986 .gamma_set = intel_crtc_gamma_set,
12987 .set_config = intel_crtc_set_config,
12988 .destroy = intel_crtc_destroy,
12989 .page_flip = intel_crtc_page_flip,
12990 .atomic_duplicate_state = intel_crtc_duplicate_state,
12991 .atomic_destroy_state = intel_crtc_destroy_state,
12994 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12995 struct intel_shared_dpll *pll,
12996 struct intel_dpll_hw_state *hw_state)
13000 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13003 val = I915_READ(PCH_DPLL(pll->id));
13004 hw_state->dpll = val;
13005 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13006 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13008 return val & DPLL_VCO_ENABLE;
13011 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13012 struct intel_shared_dpll *pll)
13014 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13015 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13018 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13019 struct intel_shared_dpll *pll)
13021 /* PCH refclock must be enabled first */
13022 ibx_assert_pch_refclk_enabled(dev_priv);
13024 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13026 /* Wait for the clocks to stabilize. */
13027 POSTING_READ(PCH_DPLL(pll->id));
13030 /* The pixel multiplier can only be updated once the
13031 * DPLL is enabled and the clocks are stable.
13033 * So write it again.
13035 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13036 POSTING_READ(PCH_DPLL(pll->id));
13040 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13041 struct intel_shared_dpll *pll)
13043 struct drm_device *dev = dev_priv->dev;
13044 struct intel_crtc *crtc;
13046 /* Make sure no transcoder isn't still depending on us. */
13047 for_each_intel_crtc(dev, crtc) {
13048 if (intel_crtc_to_shared_dpll(crtc) == pll)
13049 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13052 I915_WRITE(PCH_DPLL(pll->id), 0);
13053 POSTING_READ(PCH_DPLL(pll->id));
13057 static char *ibx_pch_dpll_names[] = {
13062 static void ibx_pch_dpll_init(struct drm_device *dev)
13064 struct drm_i915_private *dev_priv = dev->dev_private;
13067 dev_priv->num_shared_dpll = 2;
13069 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13070 dev_priv->shared_dplls[i].id = i;
13071 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13072 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13073 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13074 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13075 dev_priv->shared_dplls[i].get_hw_state =
13076 ibx_pch_dpll_get_hw_state;
13080 static void intel_shared_dpll_init(struct drm_device *dev)
13082 struct drm_i915_private *dev_priv = dev->dev_private;
13085 intel_ddi_pll_init(dev);
13086 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13087 ibx_pch_dpll_init(dev);
13089 dev_priv->num_shared_dpll = 0;
13091 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13095 * intel_wm_need_update - Check whether watermarks need updating
13096 * @plane: drm plane
13097 * @state: new plane state
13099 * Check current plane state versus the new one to determine whether
13100 * watermarks need to be recalculated.
13102 * Returns true or false.
13104 bool intel_wm_need_update(struct drm_plane *plane,
13105 struct drm_plane_state *state)
13107 /* Update watermarks on tiling changes. */
13108 if (!plane->state->fb || !state->fb ||
13109 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13110 plane->state->rotation != state->rotation)
13117 * intel_prepare_plane_fb - Prepare fb for usage on plane
13118 * @plane: drm plane to prepare for
13119 * @fb: framebuffer to prepare for presentation
13121 * Prepares a framebuffer for usage on a display plane. Generally this
13122 * involves pinning the underlying object and updating the frontbuffer tracking
13123 * bits. Some older platforms need special physical address handling for
13126 * Returns 0 on success, negative error code on failure.
13129 intel_prepare_plane_fb(struct drm_plane *plane,
13130 struct drm_framebuffer *fb,
13131 const struct drm_plane_state *new_state)
13133 struct drm_device *dev = plane->dev;
13134 struct intel_plane *intel_plane = to_intel_plane(plane);
13135 enum pipe pipe = intel_plane->pipe;
13136 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13137 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13138 unsigned frontbuffer_bits = 0;
13144 switch (plane->type) {
13145 case DRM_PLANE_TYPE_PRIMARY:
13146 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13148 case DRM_PLANE_TYPE_CURSOR:
13149 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13151 case DRM_PLANE_TYPE_OVERLAY:
13152 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13156 mutex_lock(&dev->struct_mutex);
13158 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13159 INTEL_INFO(dev)->cursor_needs_physical) {
13160 int align = IS_I830(dev) ? 16 * 1024 : 256;
13161 ret = i915_gem_object_attach_phys(obj, align);
13163 DRM_DEBUG_KMS("failed to attach phys object\n");
13165 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13169 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13171 mutex_unlock(&dev->struct_mutex);
13177 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13178 * @plane: drm plane to clean up for
13179 * @fb: old framebuffer that was on plane
13181 * Cleans up a framebuffer that has just been removed from a plane.
13184 intel_cleanup_plane_fb(struct drm_plane *plane,
13185 struct drm_framebuffer *fb,
13186 const struct drm_plane_state *old_state)
13188 struct drm_device *dev = plane->dev;
13189 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13194 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13195 !INTEL_INFO(dev)->cursor_needs_physical) {
13196 mutex_lock(&dev->struct_mutex);
13197 intel_unpin_fb_obj(fb, old_state);
13198 mutex_unlock(&dev->struct_mutex);
13203 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13206 struct drm_device *dev;
13207 struct drm_i915_private *dev_priv;
13208 int crtc_clock, cdclk;
13210 if (!intel_crtc || !crtc_state)
13211 return DRM_PLANE_HELPER_NO_SCALING;
13213 dev = intel_crtc->base.dev;
13214 dev_priv = dev->dev_private;
13215 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13216 cdclk = dev_priv->display.get_display_clock_speed(dev);
13218 if (!crtc_clock || !cdclk)
13219 return DRM_PLANE_HELPER_NO_SCALING;
13222 * skl max scale is lower of:
13223 * close to 3 but not 3, -1 is for that purpose
13227 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13233 intel_check_primary_plane(struct drm_plane *plane,
13234 struct intel_plane_state *state)
13236 struct drm_device *dev = plane->dev;
13237 struct drm_i915_private *dev_priv = dev->dev_private;
13238 struct drm_crtc *crtc = state->base.crtc;
13239 struct intel_crtc *intel_crtc;
13240 struct intel_crtc_state *crtc_state;
13241 struct drm_framebuffer *fb = state->base.fb;
13242 struct drm_rect *dest = &state->dst;
13243 struct drm_rect *src = &state->src;
13244 const struct drm_rect *clip = &state->clip;
13245 bool can_position = false;
13246 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13247 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13250 crtc = crtc ? crtc : plane->crtc;
13251 intel_crtc = to_intel_crtc(crtc);
13252 crtc_state = state->base.state ?
13253 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13255 if (INTEL_INFO(dev)->gen >= 9) {
13256 /* use scaler when colorkey is not required */
13257 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13259 max_scale = skl_max_scale(intel_crtc, crtc_state);
13261 can_position = true;
13264 ret = drm_plane_helper_check_update(plane, crtc, fb,
13268 can_position, true,
13273 if (intel_crtc->active) {
13274 struct intel_plane_state *old_state =
13275 to_intel_plane_state(plane->state);
13277 intel_crtc->atomic.wait_for_flips = true;
13280 * FBC does not work on some platforms for rotated
13281 * planes, so disable it when rotation is not 0 and
13282 * update it when rotation is set back to 0.
13284 * FIXME: This is redundant with the fbc update done in
13285 * the primary plane enable function except that that
13286 * one is done too late. We eventually need to unify
13289 if (state->visible &&
13290 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13291 dev_priv->fbc.crtc == intel_crtc &&
13292 state->base.rotation != BIT(DRM_ROTATE_0)) {
13293 intel_crtc->atomic.disable_fbc = true;
13296 if (state->visible && !old_state->visible) {
13298 * BDW signals flip done immediately if the plane
13299 * is disabled, even if the plane enable is already
13300 * armed to occur at the next vblank :(
13302 if (IS_BROADWELL(dev))
13303 intel_crtc->atomic.wait_vblank = true;
13307 * FIXME: Actually if we will still have any other plane enabled
13308 * on the pipe we could let IPS enabled still, but for
13309 * now lets consider that when we make primary invisible
13310 * by setting DSPCNTR to 0 on update_primary_plane function
13311 * IPS needs to be disable.
13313 if (!state->visible || !fb)
13314 intel_crtc->atomic.disable_ips = true;
13316 intel_crtc->atomic.fb_bits |=
13317 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13319 intel_crtc->atomic.update_fbc = true;
13321 if (intel_wm_need_update(plane, &state->base))
13322 intel_crtc->atomic.update_wm = true;
13325 if (INTEL_INFO(dev)->gen >= 9) {
13326 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13327 to_intel_plane(plane), state, 0);
13336 intel_commit_primary_plane(struct drm_plane *plane,
13337 struct intel_plane_state *state)
13339 struct drm_crtc *crtc = state->base.crtc;
13340 struct drm_framebuffer *fb = state->base.fb;
13341 struct drm_device *dev = plane->dev;
13342 struct drm_i915_private *dev_priv = dev->dev_private;
13343 struct intel_crtc *intel_crtc;
13344 struct drm_rect *src = &state->src;
13346 crtc = crtc ? crtc : plane->crtc;
13347 intel_crtc = to_intel_crtc(crtc);
13350 crtc->x = src->x1 >> 16;
13351 crtc->y = src->y1 >> 16;
13353 if (intel_crtc->active) {
13354 if (state->visible)
13355 /* FIXME: kill this fastboot hack */
13356 intel_update_pipe_size(intel_crtc);
13358 dev_priv->display.update_primary_plane(crtc, plane->fb,
13364 intel_disable_primary_plane(struct drm_plane *plane,
13365 struct drm_crtc *crtc,
13368 struct drm_device *dev = plane->dev;
13369 struct drm_i915_private *dev_priv = dev->dev_private;
13371 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13374 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13376 struct drm_device *dev = crtc->dev;
13377 struct drm_i915_private *dev_priv = dev->dev_private;
13378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13379 struct intel_plane *intel_plane;
13380 struct drm_plane *p;
13381 unsigned fb_bits = 0;
13383 /* Track fb's for any planes being disabled */
13384 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13385 intel_plane = to_intel_plane(p);
13387 if (intel_crtc->atomic.disabled_planes &
13388 (1 << drm_plane_index(p))) {
13390 case DRM_PLANE_TYPE_PRIMARY:
13391 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13393 case DRM_PLANE_TYPE_CURSOR:
13394 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13396 case DRM_PLANE_TYPE_OVERLAY:
13397 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13401 mutex_lock(&dev->struct_mutex);
13402 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13403 mutex_unlock(&dev->struct_mutex);
13407 if (intel_crtc->atomic.wait_for_flips)
13408 intel_crtc_wait_for_pending_flips(crtc);
13410 if (intel_crtc->atomic.disable_fbc)
13411 intel_fbc_disable(dev);
13413 if (intel_crtc->atomic.disable_ips)
13414 hsw_disable_ips(intel_crtc);
13416 if (intel_crtc->atomic.pre_disable_primary)
13417 intel_pre_disable_primary(crtc);
13419 if (intel_crtc->atomic.update_wm)
13420 intel_update_watermarks(crtc);
13422 intel_runtime_pm_get(dev_priv);
13424 /* Perform vblank evasion around commit operation */
13425 if (intel_crtc->active)
13426 intel_crtc->atomic.evade =
13427 intel_pipe_update_start(intel_crtc,
13428 &intel_crtc->atomic.start_vbl_count);
13431 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13433 struct drm_device *dev = crtc->dev;
13434 struct drm_i915_private *dev_priv = dev->dev_private;
13435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13436 struct drm_plane *p;
13438 if (intel_crtc->atomic.evade)
13439 intel_pipe_update_end(intel_crtc,
13440 intel_crtc->atomic.start_vbl_count);
13442 intel_runtime_pm_put(dev_priv);
13444 if (intel_crtc->atomic.wait_vblank)
13445 intel_wait_for_vblank(dev, intel_crtc->pipe);
13447 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13449 if (intel_crtc->atomic.update_fbc) {
13450 mutex_lock(&dev->struct_mutex);
13451 intel_fbc_update(dev);
13452 mutex_unlock(&dev->struct_mutex);
13455 if (intel_crtc->atomic.post_enable_primary)
13456 intel_post_enable_primary(crtc);
13458 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13459 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13460 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13463 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13467 * intel_plane_destroy - destroy a plane
13468 * @plane: plane to destroy
13470 * Common destruction function for all types of planes (primary, cursor,
13473 void intel_plane_destroy(struct drm_plane *plane)
13475 struct intel_plane *intel_plane = to_intel_plane(plane);
13476 drm_plane_cleanup(plane);
13477 kfree(intel_plane);
13480 const struct drm_plane_funcs intel_plane_funcs = {
13481 .update_plane = drm_atomic_helper_update_plane,
13482 .disable_plane = drm_atomic_helper_disable_plane,
13483 .destroy = intel_plane_destroy,
13484 .set_property = drm_atomic_helper_plane_set_property,
13485 .atomic_get_property = intel_plane_atomic_get_property,
13486 .atomic_set_property = intel_plane_atomic_set_property,
13487 .atomic_duplicate_state = intel_plane_duplicate_state,
13488 .atomic_destroy_state = intel_plane_destroy_state,
13492 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13495 struct intel_plane *primary;
13496 struct intel_plane_state *state;
13497 const uint32_t *intel_primary_formats;
13500 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13501 if (primary == NULL)
13504 state = intel_create_plane_state(&primary->base);
13509 primary->base.state = &state->base;
13511 primary->can_scale = false;
13512 primary->max_downscale = 1;
13513 if (INTEL_INFO(dev)->gen >= 9) {
13514 primary->can_scale = true;
13515 state->scaler_id = -1;
13517 primary->pipe = pipe;
13518 primary->plane = pipe;
13519 primary->check_plane = intel_check_primary_plane;
13520 primary->commit_plane = intel_commit_primary_plane;
13521 primary->disable_plane = intel_disable_primary_plane;
13522 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13523 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13524 primary->plane = !pipe;
13526 if (INTEL_INFO(dev)->gen >= 9) {
13527 intel_primary_formats = skl_primary_formats;
13528 num_formats = ARRAY_SIZE(skl_primary_formats);
13529 } else if (INTEL_INFO(dev)->gen >= 4) {
13530 intel_primary_formats = i965_primary_formats;
13531 num_formats = ARRAY_SIZE(i965_primary_formats);
13533 intel_primary_formats = i8xx_primary_formats;
13534 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13537 drm_universal_plane_init(dev, &primary->base, 0,
13538 &intel_plane_funcs,
13539 intel_primary_formats, num_formats,
13540 DRM_PLANE_TYPE_PRIMARY);
13542 if (INTEL_INFO(dev)->gen >= 4)
13543 intel_create_rotation_property(dev, primary);
13545 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13547 return &primary->base;
13550 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13552 if (!dev->mode_config.rotation_property) {
13553 unsigned long flags = BIT(DRM_ROTATE_0) |
13554 BIT(DRM_ROTATE_180);
13556 if (INTEL_INFO(dev)->gen >= 9)
13557 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13559 dev->mode_config.rotation_property =
13560 drm_mode_create_rotation_property(dev, flags);
13562 if (dev->mode_config.rotation_property)
13563 drm_object_attach_property(&plane->base.base,
13564 dev->mode_config.rotation_property,
13565 plane->base.state->rotation);
13569 intel_check_cursor_plane(struct drm_plane *plane,
13570 struct intel_plane_state *state)
13572 struct drm_crtc *crtc = state->base.crtc;
13573 struct drm_device *dev = plane->dev;
13574 struct drm_framebuffer *fb = state->base.fb;
13575 struct drm_rect *dest = &state->dst;
13576 struct drm_rect *src = &state->src;
13577 const struct drm_rect *clip = &state->clip;
13578 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13579 struct intel_crtc *intel_crtc;
13583 crtc = crtc ? crtc : plane->crtc;
13584 intel_crtc = to_intel_crtc(crtc);
13586 ret = drm_plane_helper_check_update(plane, crtc, fb,
13588 DRM_PLANE_HELPER_NO_SCALING,
13589 DRM_PLANE_HELPER_NO_SCALING,
13590 true, true, &state->visible);
13595 /* if we want to turn off the cursor ignore width and height */
13599 /* Check for which cursor types we support */
13600 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13601 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13602 state->base.crtc_w, state->base.crtc_h);
13606 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13607 if (obj->base.size < stride * state->base.crtc_h) {
13608 DRM_DEBUG_KMS("buffer is too small\n");
13612 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13613 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13618 if (intel_crtc->active) {
13619 if (plane->state->crtc_w != state->base.crtc_w)
13620 intel_crtc->atomic.update_wm = true;
13622 intel_crtc->atomic.fb_bits |=
13623 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13630 intel_disable_cursor_plane(struct drm_plane *plane,
13631 struct drm_crtc *crtc,
13634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13638 intel_crtc->cursor_bo = NULL;
13639 intel_crtc->cursor_addr = 0;
13642 intel_crtc_update_cursor(crtc, false);
13646 intel_commit_cursor_plane(struct drm_plane *plane,
13647 struct intel_plane_state *state)
13649 struct drm_crtc *crtc = state->base.crtc;
13650 struct drm_device *dev = plane->dev;
13651 struct intel_crtc *intel_crtc;
13652 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13655 crtc = crtc ? crtc : plane->crtc;
13656 intel_crtc = to_intel_crtc(crtc);
13658 plane->fb = state->base.fb;
13659 crtc->cursor_x = state->base.crtc_x;
13660 crtc->cursor_y = state->base.crtc_y;
13662 if (intel_crtc->cursor_bo == obj)
13667 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13668 addr = i915_gem_obj_ggtt_offset(obj);
13670 addr = obj->phys_handle->busaddr;
13672 intel_crtc->cursor_addr = addr;
13673 intel_crtc->cursor_bo = obj;
13676 if (intel_crtc->active)
13677 intel_crtc_update_cursor(crtc, state->visible);
13680 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13683 struct intel_plane *cursor;
13684 struct intel_plane_state *state;
13686 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13687 if (cursor == NULL)
13690 state = intel_create_plane_state(&cursor->base);
13695 cursor->base.state = &state->base;
13697 cursor->can_scale = false;
13698 cursor->max_downscale = 1;
13699 cursor->pipe = pipe;
13700 cursor->plane = pipe;
13701 cursor->check_plane = intel_check_cursor_plane;
13702 cursor->commit_plane = intel_commit_cursor_plane;
13703 cursor->disable_plane = intel_disable_cursor_plane;
13705 drm_universal_plane_init(dev, &cursor->base, 0,
13706 &intel_plane_funcs,
13707 intel_cursor_formats,
13708 ARRAY_SIZE(intel_cursor_formats),
13709 DRM_PLANE_TYPE_CURSOR);
13711 if (INTEL_INFO(dev)->gen >= 4) {
13712 if (!dev->mode_config.rotation_property)
13713 dev->mode_config.rotation_property =
13714 drm_mode_create_rotation_property(dev,
13715 BIT(DRM_ROTATE_0) |
13716 BIT(DRM_ROTATE_180));
13717 if (dev->mode_config.rotation_property)
13718 drm_object_attach_property(&cursor->base.base,
13719 dev->mode_config.rotation_property,
13720 state->base.rotation);
13723 if (INTEL_INFO(dev)->gen >=9)
13724 state->scaler_id = -1;
13726 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13728 return &cursor->base;
13731 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13732 struct intel_crtc_state *crtc_state)
13735 struct intel_scaler *intel_scaler;
13736 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13738 for (i = 0; i < intel_crtc->num_scalers; i++) {
13739 intel_scaler = &scaler_state->scalers[i];
13740 intel_scaler->in_use = 0;
13741 intel_scaler->id = i;
13743 intel_scaler->mode = PS_SCALER_MODE_DYN;
13746 scaler_state->scaler_id = -1;
13749 static void intel_crtc_init(struct drm_device *dev, int pipe)
13751 struct drm_i915_private *dev_priv = dev->dev_private;
13752 struct intel_crtc *intel_crtc;
13753 struct intel_crtc_state *crtc_state = NULL;
13754 struct drm_plane *primary = NULL;
13755 struct drm_plane *cursor = NULL;
13758 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13759 if (intel_crtc == NULL)
13762 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13765 intel_crtc->config = crtc_state;
13766 intel_crtc->base.state = &crtc_state->base;
13767 crtc_state->base.crtc = &intel_crtc->base;
13769 /* initialize shared scalers */
13770 if (INTEL_INFO(dev)->gen >= 9) {
13771 if (pipe == PIPE_C)
13772 intel_crtc->num_scalers = 1;
13774 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13776 skl_init_scalers(dev, intel_crtc, crtc_state);
13779 primary = intel_primary_plane_create(dev, pipe);
13783 cursor = intel_cursor_plane_create(dev, pipe);
13787 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13788 cursor, &intel_crtc_funcs);
13792 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13793 for (i = 0; i < 256; i++) {
13794 intel_crtc->lut_r[i] = i;
13795 intel_crtc->lut_g[i] = i;
13796 intel_crtc->lut_b[i] = i;
13800 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13801 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13803 intel_crtc->pipe = pipe;
13804 intel_crtc->plane = pipe;
13805 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13806 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13807 intel_crtc->plane = !pipe;
13810 intel_crtc->cursor_base = ~0;
13811 intel_crtc->cursor_cntl = ~0;
13812 intel_crtc->cursor_size = ~0;
13814 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13815 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13816 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13817 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13819 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13821 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13826 drm_plane_cleanup(primary);
13828 drm_plane_cleanup(cursor);
13833 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13835 struct drm_encoder *encoder = connector->base.encoder;
13836 struct drm_device *dev = connector->base.dev;
13838 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13840 if (!encoder || WARN_ON(!encoder->crtc))
13841 return INVALID_PIPE;
13843 return to_intel_crtc(encoder->crtc)->pipe;
13846 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13847 struct drm_file *file)
13849 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13850 struct drm_crtc *drmmode_crtc;
13851 struct intel_crtc *crtc;
13853 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13855 if (!drmmode_crtc) {
13856 DRM_ERROR("no such CRTC id\n");
13860 crtc = to_intel_crtc(drmmode_crtc);
13861 pipe_from_crtc_id->pipe = crtc->pipe;
13866 static int intel_encoder_clones(struct intel_encoder *encoder)
13868 struct drm_device *dev = encoder->base.dev;
13869 struct intel_encoder *source_encoder;
13870 int index_mask = 0;
13873 for_each_intel_encoder(dev, source_encoder) {
13874 if (encoders_cloneable(encoder, source_encoder))
13875 index_mask |= (1 << entry);
13883 static bool has_edp_a(struct drm_device *dev)
13885 struct drm_i915_private *dev_priv = dev->dev_private;
13887 if (!IS_MOBILE(dev))
13890 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13893 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13899 static bool intel_crt_present(struct drm_device *dev)
13901 struct drm_i915_private *dev_priv = dev->dev_private;
13903 if (INTEL_INFO(dev)->gen >= 9)
13906 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13909 if (IS_CHERRYVIEW(dev))
13912 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13918 static void intel_setup_outputs(struct drm_device *dev)
13920 struct drm_i915_private *dev_priv = dev->dev_private;
13921 struct intel_encoder *encoder;
13922 bool dpd_is_edp = false;
13924 intel_lvds_init(dev);
13926 if (intel_crt_present(dev))
13927 intel_crt_init(dev);
13929 if (IS_BROXTON(dev)) {
13931 * FIXME: Broxton doesn't support port detection via the
13932 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13933 * detect the ports.
13935 intel_ddi_init(dev, PORT_A);
13936 intel_ddi_init(dev, PORT_B);
13937 intel_ddi_init(dev, PORT_C);
13938 } else if (HAS_DDI(dev)) {
13942 * Haswell uses DDI functions to detect digital outputs.
13943 * On SKL pre-D0 the strap isn't connected, so we assume
13946 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13947 /* WaIgnoreDDIAStrap: skl */
13949 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13950 intel_ddi_init(dev, PORT_A);
13952 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13954 found = I915_READ(SFUSE_STRAP);
13956 if (found & SFUSE_STRAP_DDIB_DETECTED)
13957 intel_ddi_init(dev, PORT_B);
13958 if (found & SFUSE_STRAP_DDIC_DETECTED)
13959 intel_ddi_init(dev, PORT_C);
13960 if (found & SFUSE_STRAP_DDID_DETECTED)
13961 intel_ddi_init(dev, PORT_D);
13962 } else if (HAS_PCH_SPLIT(dev)) {
13964 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13966 if (has_edp_a(dev))
13967 intel_dp_init(dev, DP_A, PORT_A);
13969 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13970 /* PCH SDVOB multiplex with HDMIB */
13971 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13973 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13974 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13975 intel_dp_init(dev, PCH_DP_B, PORT_B);
13978 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13979 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13981 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13982 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13984 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13985 intel_dp_init(dev, PCH_DP_C, PORT_C);
13987 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13988 intel_dp_init(dev, PCH_DP_D, PORT_D);
13989 } else if (IS_VALLEYVIEW(dev)) {
13991 * The DP_DETECTED bit is the latched state of the DDC
13992 * SDA pin at boot. However since eDP doesn't require DDC
13993 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13994 * eDP ports may have been muxed to an alternate function.
13995 * Thus we can't rely on the DP_DETECTED bit alone to detect
13996 * eDP ports. Consult the VBT as well as DP_DETECTED to
13997 * detect eDP ports.
13999 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14000 !intel_dp_is_edp(dev, PORT_B))
14001 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14003 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14004 intel_dp_is_edp(dev, PORT_B))
14005 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14007 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14008 !intel_dp_is_edp(dev, PORT_C))
14009 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14011 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14012 intel_dp_is_edp(dev, PORT_C))
14013 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14015 if (IS_CHERRYVIEW(dev)) {
14016 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14017 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14019 /* eDP not supported on port D, so don't check VBT */
14020 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14021 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14024 intel_dsi_init(dev);
14025 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14026 bool found = false;
14028 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14029 DRM_DEBUG_KMS("probing SDVOB\n");
14030 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14031 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14032 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14033 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14036 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14037 intel_dp_init(dev, DP_B, PORT_B);
14040 /* Before G4X SDVOC doesn't have its own detect register */
14042 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14043 DRM_DEBUG_KMS("probing SDVOC\n");
14044 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14047 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14049 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14050 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14051 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14053 if (SUPPORTS_INTEGRATED_DP(dev))
14054 intel_dp_init(dev, DP_C, PORT_C);
14057 if (SUPPORTS_INTEGRATED_DP(dev) &&
14058 (I915_READ(DP_D) & DP_DETECTED))
14059 intel_dp_init(dev, DP_D, PORT_D);
14060 } else if (IS_GEN2(dev))
14061 intel_dvo_init(dev);
14063 if (SUPPORTS_TV(dev))
14064 intel_tv_init(dev);
14066 intel_psr_init(dev);
14068 for_each_intel_encoder(dev, encoder) {
14069 encoder->base.possible_crtcs = encoder->crtc_mask;
14070 encoder->base.possible_clones =
14071 intel_encoder_clones(encoder);
14074 intel_init_pch_refclk(dev);
14076 drm_helper_move_panel_connectors_to_head(dev);
14079 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14081 struct drm_device *dev = fb->dev;
14082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14084 drm_framebuffer_cleanup(fb);
14085 mutex_lock(&dev->struct_mutex);
14086 WARN_ON(!intel_fb->obj->framebuffer_references--);
14087 drm_gem_object_unreference(&intel_fb->obj->base);
14088 mutex_unlock(&dev->struct_mutex);
14092 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14093 struct drm_file *file,
14094 unsigned int *handle)
14096 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14097 struct drm_i915_gem_object *obj = intel_fb->obj;
14099 return drm_gem_handle_create(file, &obj->base, handle);
14102 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14103 .destroy = intel_user_framebuffer_destroy,
14104 .create_handle = intel_user_framebuffer_create_handle,
14108 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14109 uint32_t pixel_format)
14111 u32 gen = INTEL_INFO(dev)->gen;
14114 /* "The stride in bytes must not exceed the of the size of 8K
14115 * pixels and 32K bytes."
14117 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14118 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14120 } else if (gen >= 4) {
14121 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14125 } else if (gen >= 3) {
14126 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14131 /* XXX DSPC is limited to 4k tiled */
14136 static int intel_framebuffer_init(struct drm_device *dev,
14137 struct intel_framebuffer *intel_fb,
14138 struct drm_mode_fb_cmd2 *mode_cmd,
14139 struct drm_i915_gem_object *obj)
14141 unsigned int aligned_height;
14143 u32 pitch_limit, stride_alignment;
14145 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14147 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14148 /* Enforce that fb modifier and tiling mode match, but only for
14149 * X-tiled. This is needed for FBC. */
14150 if (!!(obj->tiling_mode == I915_TILING_X) !=
14151 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14152 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14156 if (obj->tiling_mode == I915_TILING_X)
14157 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14158 else if (obj->tiling_mode == I915_TILING_Y) {
14159 DRM_DEBUG("No Y tiling for legacy addfb\n");
14164 /* Passed in modifier sanity checking. */
14165 switch (mode_cmd->modifier[0]) {
14166 case I915_FORMAT_MOD_Y_TILED:
14167 case I915_FORMAT_MOD_Yf_TILED:
14168 if (INTEL_INFO(dev)->gen < 9) {
14169 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14170 mode_cmd->modifier[0]);
14173 case DRM_FORMAT_MOD_NONE:
14174 case I915_FORMAT_MOD_X_TILED:
14177 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14178 mode_cmd->modifier[0]);
14182 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14183 mode_cmd->pixel_format);
14184 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14185 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14186 mode_cmd->pitches[0], stride_alignment);
14190 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14191 mode_cmd->pixel_format);
14192 if (mode_cmd->pitches[0] > pitch_limit) {
14193 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14194 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14195 "tiled" : "linear",
14196 mode_cmd->pitches[0], pitch_limit);
14200 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14201 mode_cmd->pitches[0] != obj->stride) {
14202 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14203 mode_cmd->pitches[0], obj->stride);
14207 /* Reject formats not supported by any plane early. */
14208 switch (mode_cmd->pixel_format) {
14209 case DRM_FORMAT_C8:
14210 case DRM_FORMAT_RGB565:
14211 case DRM_FORMAT_XRGB8888:
14212 case DRM_FORMAT_ARGB8888:
14214 case DRM_FORMAT_XRGB1555:
14215 if (INTEL_INFO(dev)->gen > 3) {
14216 DRM_DEBUG("unsupported pixel format: %s\n",
14217 drm_get_format_name(mode_cmd->pixel_format));
14221 case DRM_FORMAT_ABGR8888:
14222 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14223 DRM_DEBUG("unsupported pixel format: %s\n",
14224 drm_get_format_name(mode_cmd->pixel_format));
14228 case DRM_FORMAT_XBGR8888:
14229 case DRM_FORMAT_XRGB2101010:
14230 case DRM_FORMAT_XBGR2101010:
14231 if (INTEL_INFO(dev)->gen < 4) {
14232 DRM_DEBUG("unsupported pixel format: %s\n",
14233 drm_get_format_name(mode_cmd->pixel_format));
14237 case DRM_FORMAT_ABGR2101010:
14238 if (!IS_VALLEYVIEW(dev)) {
14239 DRM_DEBUG("unsupported pixel format: %s\n",
14240 drm_get_format_name(mode_cmd->pixel_format));
14244 case DRM_FORMAT_YUYV:
14245 case DRM_FORMAT_UYVY:
14246 case DRM_FORMAT_YVYU:
14247 case DRM_FORMAT_VYUY:
14248 if (INTEL_INFO(dev)->gen < 5) {
14249 DRM_DEBUG("unsupported pixel format: %s\n",
14250 drm_get_format_name(mode_cmd->pixel_format));
14255 DRM_DEBUG("unsupported pixel format: %s\n",
14256 drm_get_format_name(mode_cmd->pixel_format));
14260 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14261 if (mode_cmd->offsets[0] != 0)
14264 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14265 mode_cmd->pixel_format,
14266 mode_cmd->modifier[0]);
14267 /* FIXME drm helper for size checks (especially planar formats)? */
14268 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14271 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14272 intel_fb->obj = obj;
14273 intel_fb->obj->framebuffer_references++;
14275 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14277 DRM_ERROR("framebuffer init failed %d\n", ret);
14284 static struct drm_framebuffer *
14285 intel_user_framebuffer_create(struct drm_device *dev,
14286 struct drm_file *filp,
14287 struct drm_mode_fb_cmd2 *mode_cmd)
14289 struct drm_i915_gem_object *obj;
14291 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14292 mode_cmd->handles[0]));
14293 if (&obj->base == NULL)
14294 return ERR_PTR(-ENOENT);
14296 return intel_framebuffer_create(dev, mode_cmd, obj);
14299 #ifndef CONFIG_DRM_I915_FBDEV
14300 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14305 static const struct drm_mode_config_funcs intel_mode_funcs = {
14306 .fb_create = intel_user_framebuffer_create,
14307 .output_poll_changed = intel_fbdev_output_poll_changed,
14308 .atomic_check = intel_atomic_check,
14309 .atomic_commit = intel_atomic_commit,
14312 /* Set up chip specific display functions */
14313 static void intel_init_display(struct drm_device *dev)
14315 struct drm_i915_private *dev_priv = dev->dev_private;
14317 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14318 dev_priv->display.find_dpll = g4x_find_best_dpll;
14319 else if (IS_CHERRYVIEW(dev))
14320 dev_priv->display.find_dpll = chv_find_best_dpll;
14321 else if (IS_VALLEYVIEW(dev))
14322 dev_priv->display.find_dpll = vlv_find_best_dpll;
14323 else if (IS_PINEVIEW(dev))
14324 dev_priv->display.find_dpll = pnv_find_best_dpll;
14326 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14328 if (INTEL_INFO(dev)->gen >= 9) {
14329 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14330 dev_priv->display.get_initial_plane_config =
14331 skylake_get_initial_plane_config;
14332 dev_priv->display.crtc_compute_clock =
14333 haswell_crtc_compute_clock;
14334 dev_priv->display.crtc_enable = haswell_crtc_enable;
14335 dev_priv->display.crtc_disable = haswell_crtc_disable;
14336 dev_priv->display.off = ironlake_crtc_off;
14337 dev_priv->display.update_primary_plane =
14338 skylake_update_primary_plane;
14339 } else if (HAS_DDI(dev)) {
14340 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14341 dev_priv->display.get_initial_plane_config =
14342 ironlake_get_initial_plane_config;
14343 dev_priv->display.crtc_compute_clock =
14344 haswell_crtc_compute_clock;
14345 dev_priv->display.crtc_enable = haswell_crtc_enable;
14346 dev_priv->display.crtc_disable = haswell_crtc_disable;
14347 dev_priv->display.off = ironlake_crtc_off;
14348 dev_priv->display.update_primary_plane =
14349 ironlake_update_primary_plane;
14350 } else if (HAS_PCH_SPLIT(dev)) {
14351 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14352 dev_priv->display.get_initial_plane_config =
14353 ironlake_get_initial_plane_config;
14354 dev_priv->display.crtc_compute_clock =
14355 ironlake_crtc_compute_clock;
14356 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14357 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14358 dev_priv->display.off = ironlake_crtc_off;
14359 dev_priv->display.update_primary_plane =
14360 ironlake_update_primary_plane;
14361 } else if (IS_VALLEYVIEW(dev)) {
14362 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14363 dev_priv->display.get_initial_plane_config =
14364 i9xx_get_initial_plane_config;
14365 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14366 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14367 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14368 dev_priv->display.off = i9xx_crtc_off;
14369 dev_priv->display.update_primary_plane =
14370 i9xx_update_primary_plane;
14372 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14373 dev_priv->display.get_initial_plane_config =
14374 i9xx_get_initial_plane_config;
14375 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14376 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14377 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14378 dev_priv->display.off = i9xx_crtc_off;
14379 dev_priv->display.update_primary_plane =
14380 i9xx_update_primary_plane;
14383 /* Returns the core display clock speed */
14384 if (IS_SKYLAKE(dev))
14385 dev_priv->display.get_display_clock_speed =
14386 skylake_get_display_clock_speed;
14387 else if (IS_BROADWELL(dev))
14388 dev_priv->display.get_display_clock_speed =
14389 broadwell_get_display_clock_speed;
14390 else if (IS_HASWELL(dev))
14391 dev_priv->display.get_display_clock_speed =
14392 haswell_get_display_clock_speed;
14393 else if (IS_VALLEYVIEW(dev))
14394 dev_priv->display.get_display_clock_speed =
14395 valleyview_get_display_clock_speed;
14396 else if (IS_GEN5(dev))
14397 dev_priv->display.get_display_clock_speed =
14398 ilk_get_display_clock_speed;
14399 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14400 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14401 dev_priv->display.get_display_clock_speed =
14402 i945_get_display_clock_speed;
14403 else if (IS_I915G(dev))
14404 dev_priv->display.get_display_clock_speed =
14405 i915_get_display_clock_speed;
14406 else if (IS_I945GM(dev) || IS_845G(dev))
14407 dev_priv->display.get_display_clock_speed =
14408 i9xx_misc_get_display_clock_speed;
14409 else if (IS_PINEVIEW(dev))
14410 dev_priv->display.get_display_clock_speed =
14411 pnv_get_display_clock_speed;
14412 else if (IS_I915GM(dev))
14413 dev_priv->display.get_display_clock_speed =
14414 i915gm_get_display_clock_speed;
14415 else if (IS_I865G(dev))
14416 dev_priv->display.get_display_clock_speed =
14417 i865_get_display_clock_speed;
14418 else if (IS_I85X(dev))
14419 dev_priv->display.get_display_clock_speed =
14420 i855_get_display_clock_speed;
14421 else /* 852, 830 */
14422 dev_priv->display.get_display_clock_speed =
14423 i830_get_display_clock_speed;
14425 if (IS_GEN5(dev)) {
14426 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14427 } else if (IS_GEN6(dev)) {
14428 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14429 } else if (IS_IVYBRIDGE(dev)) {
14430 /* FIXME: detect B0+ stepping and use auto training */
14431 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14432 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14433 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14434 } else if (IS_VALLEYVIEW(dev)) {
14435 dev_priv->display.modeset_global_resources =
14436 valleyview_modeset_global_resources;
14437 } else if (IS_BROXTON(dev)) {
14438 dev_priv->display.modeset_global_resources =
14439 broxton_modeset_global_resources;
14442 switch (INTEL_INFO(dev)->gen) {
14444 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14448 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14453 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14457 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14460 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14461 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14464 /* Drop through - unsupported since execlist only. */
14466 /* Default just returns -ENODEV to indicate unsupported */
14467 dev_priv->display.queue_flip = intel_default_queue_flip;
14470 intel_panel_init_backlight_funcs(dev);
14472 mutex_init(&dev_priv->pps_mutex);
14476 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14477 * resume, or other times. This quirk makes sure that's the case for
14478 * affected systems.
14480 static void quirk_pipea_force(struct drm_device *dev)
14482 struct drm_i915_private *dev_priv = dev->dev_private;
14484 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14485 DRM_INFO("applying pipe a force quirk\n");
14488 static void quirk_pipeb_force(struct drm_device *dev)
14490 struct drm_i915_private *dev_priv = dev->dev_private;
14492 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14493 DRM_INFO("applying pipe b force quirk\n");
14497 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14499 static void quirk_ssc_force_disable(struct drm_device *dev)
14501 struct drm_i915_private *dev_priv = dev->dev_private;
14502 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14503 DRM_INFO("applying lvds SSC disable quirk\n");
14507 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14510 static void quirk_invert_brightness(struct drm_device *dev)
14512 struct drm_i915_private *dev_priv = dev->dev_private;
14513 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14514 DRM_INFO("applying inverted panel brightness quirk\n");
14517 /* Some VBT's incorrectly indicate no backlight is present */
14518 static void quirk_backlight_present(struct drm_device *dev)
14520 struct drm_i915_private *dev_priv = dev->dev_private;
14521 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14522 DRM_INFO("applying backlight present quirk\n");
14525 struct intel_quirk {
14527 int subsystem_vendor;
14528 int subsystem_device;
14529 void (*hook)(struct drm_device *dev);
14532 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14533 struct intel_dmi_quirk {
14534 void (*hook)(struct drm_device *dev);
14535 const struct dmi_system_id (*dmi_id_list)[];
14538 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14540 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14544 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14546 .dmi_id_list = &(const struct dmi_system_id[]) {
14548 .callback = intel_dmi_reverse_brightness,
14549 .ident = "NCR Corporation",
14550 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14551 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14554 { } /* terminating entry */
14556 .hook = quirk_invert_brightness,
14560 static struct intel_quirk intel_quirks[] = {
14561 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14562 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14564 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14565 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14567 /* 830 needs to leave pipe A & dpll A up */
14568 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14570 /* 830 needs to leave pipe B & dpll B up */
14571 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14573 /* Lenovo U160 cannot use SSC on LVDS */
14574 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14576 /* Sony Vaio Y cannot use SSC on LVDS */
14577 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14579 /* Acer Aspire 5734Z must invert backlight brightness */
14580 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14582 /* Acer/eMachines G725 */
14583 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14585 /* Acer/eMachines e725 */
14586 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14588 /* Acer/Packard Bell NCL20 */
14589 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14591 /* Acer Aspire 4736Z */
14592 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14594 /* Acer Aspire 5336 */
14595 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14597 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14598 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14600 /* Acer C720 Chromebook (Core i3 4005U) */
14601 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14603 /* Apple Macbook 2,1 (Core 2 T7400) */
14604 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14606 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14607 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14609 /* HP Chromebook 14 (Celeron 2955U) */
14610 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14612 /* Dell Chromebook 11 */
14613 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14616 static void intel_init_quirks(struct drm_device *dev)
14618 struct pci_dev *d = dev->pdev;
14621 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14622 struct intel_quirk *q = &intel_quirks[i];
14624 if (d->device == q->device &&
14625 (d->subsystem_vendor == q->subsystem_vendor ||
14626 q->subsystem_vendor == PCI_ANY_ID) &&
14627 (d->subsystem_device == q->subsystem_device ||
14628 q->subsystem_device == PCI_ANY_ID))
14631 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14632 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14633 intel_dmi_quirks[i].hook(dev);
14637 /* Disable the VGA plane that we never use */
14638 static void i915_disable_vga(struct drm_device *dev)
14640 struct drm_i915_private *dev_priv = dev->dev_private;
14642 u32 vga_reg = i915_vgacntrl_reg(dev);
14644 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14645 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14646 outb(SR01, VGA_SR_INDEX);
14647 sr1 = inb(VGA_SR_DATA);
14648 outb(sr1 | 1<<5, VGA_SR_DATA);
14649 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14652 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14653 POSTING_READ(vga_reg);
14656 void intel_modeset_init_hw(struct drm_device *dev)
14658 intel_prepare_ddi(dev);
14660 if (IS_VALLEYVIEW(dev))
14661 vlv_update_cdclk(dev);
14663 intel_init_clock_gating(dev);
14665 intel_enable_gt_powersave(dev);
14668 void intel_modeset_init(struct drm_device *dev)
14670 struct drm_i915_private *dev_priv = dev->dev_private;
14673 struct intel_crtc *crtc;
14675 drm_mode_config_init(dev);
14677 dev->mode_config.min_width = 0;
14678 dev->mode_config.min_height = 0;
14680 dev->mode_config.preferred_depth = 24;
14681 dev->mode_config.prefer_shadow = 1;
14683 dev->mode_config.allow_fb_modifiers = true;
14685 dev->mode_config.funcs = &intel_mode_funcs;
14687 intel_init_quirks(dev);
14689 intel_init_pm(dev);
14691 if (INTEL_INFO(dev)->num_pipes == 0)
14694 intel_init_display(dev);
14695 intel_init_audio(dev);
14697 if (IS_GEN2(dev)) {
14698 dev->mode_config.max_width = 2048;
14699 dev->mode_config.max_height = 2048;
14700 } else if (IS_GEN3(dev)) {
14701 dev->mode_config.max_width = 4096;
14702 dev->mode_config.max_height = 4096;
14704 dev->mode_config.max_width = 8192;
14705 dev->mode_config.max_height = 8192;
14708 if (IS_845G(dev) || IS_I865G(dev)) {
14709 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14710 dev->mode_config.cursor_height = 1023;
14711 } else if (IS_GEN2(dev)) {
14712 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14713 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14715 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14716 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14719 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14721 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14722 INTEL_INFO(dev)->num_pipes,
14723 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14725 for_each_pipe(dev_priv, pipe) {
14726 intel_crtc_init(dev, pipe);
14727 for_each_sprite(dev_priv, pipe, sprite) {
14728 ret = intel_plane_init(dev, pipe, sprite);
14730 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14731 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14735 intel_init_dpio(dev);
14737 intel_shared_dpll_init(dev);
14739 /* Just disable it once at startup */
14740 i915_disable_vga(dev);
14741 intel_setup_outputs(dev);
14743 /* Just in case the BIOS is doing something questionable. */
14744 intel_fbc_disable(dev);
14746 drm_modeset_lock_all(dev);
14747 intel_modeset_setup_hw_state(dev, false);
14748 drm_modeset_unlock_all(dev);
14750 for_each_intel_crtc(dev, crtc) {
14755 * Note that reserving the BIOS fb up front prevents us
14756 * from stuffing other stolen allocations like the ring
14757 * on top. This prevents some ugliness at boot time, and
14758 * can even allow for smooth boot transitions if the BIOS
14759 * fb is large enough for the active pipe configuration.
14761 if (dev_priv->display.get_initial_plane_config) {
14762 dev_priv->display.get_initial_plane_config(crtc,
14763 &crtc->plane_config);
14765 * If the fb is shared between multiple heads, we'll
14766 * just get the first one.
14768 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14773 static void intel_enable_pipe_a(struct drm_device *dev)
14775 struct intel_connector *connector;
14776 struct drm_connector *crt = NULL;
14777 struct intel_load_detect_pipe load_detect_temp;
14778 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14780 /* We can't just switch on the pipe A, we need to set things up with a
14781 * proper mode and output configuration. As a gross hack, enable pipe A
14782 * by enabling the load detect pipe once. */
14783 for_each_intel_connector(dev, connector) {
14784 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14785 crt = &connector->base;
14793 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14794 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14798 intel_check_plane_mapping(struct intel_crtc *crtc)
14800 struct drm_device *dev = crtc->base.dev;
14801 struct drm_i915_private *dev_priv = dev->dev_private;
14804 if (INTEL_INFO(dev)->num_pipes == 1)
14807 reg = DSPCNTR(!crtc->plane);
14808 val = I915_READ(reg);
14810 if ((val & DISPLAY_PLANE_ENABLE) &&
14811 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14817 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14819 struct drm_device *dev = crtc->base.dev;
14820 struct drm_i915_private *dev_priv = dev->dev_private;
14823 /* Clear any frame start delays used for debugging left by the BIOS */
14824 reg = PIPECONF(crtc->config->cpu_transcoder);
14825 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14827 /* restore vblank interrupts to correct state */
14828 drm_crtc_vblank_reset(&crtc->base);
14829 if (crtc->active) {
14830 update_scanline_offset(crtc);
14831 drm_crtc_vblank_on(&crtc->base);
14834 /* We need to sanitize the plane -> pipe mapping first because this will
14835 * disable the crtc (and hence change the state) if it is wrong. Note
14836 * that gen4+ has a fixed plane -> pipe mapping. */
14837 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14838 struct intel_connector *connector;
14841 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14842 crtc->base.base.id);
14844 /* Pipe has the wrong plane attached and the plane is active.
14845 * Temporarily change the plane mapping and disable everything
14847 plane = crtc->plane;
14848 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14849 crtc->plane = !plane;
14850 intel_crtc_disable_planes(&crtc->base);
14851 dev_priv->display.crtc_disable(&crtc->base);
14852 crtc->plane = plane;
14854 /* ... and break all links. */
14855 for_each_intel_connector(dev, connector) {
14856 if (connector->encoder->base.crtc != &crtc->base)
14859 connector->base.dpms = DRM_MODE_DPMS_OFF;
14860 connector->base.encoder = NULL;
14862 /* multiple connectors may have the same encoder:
14863 * handle them and break crtc link separately */
14864 for_each_intel_connector(dev, connector)
14865 if (connector->encoder->base.crtc == &crtc->base) {
14866 connector->encoder->base.crtc = NULL;
14867 connector->encoder->connectors_active = false;
14870 WARN_ON(crtc->active);
14871 crtc->base.state->enable = false;
14872 crtc->base.state->active = false;
14873 crtc->base.enabled = false;
14876 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14877 crtc->pipe == PIPE_A && !crtc->active) {
14878 /* BIOS forgot to enable pipe A, this mostly happens after
14879 * resume. Force-enable the pipe to fix this, the update_dpms
14880 * call below we restore the pipe to the right state, but leave
14881 * the required bits on. */
14882 intel_enable_pipe_a(dev);
14885 /* Adjust the state of the output pipe according to whether we
14886 * have active connectors/encoders. */
14887 intel_crtc_update_dpms(&crtc->base);
14889 if (crtc->active != crtc->base.state->enable) {
14890 struct intel_encoder *encoder;
14892 /* This can happen either due to bugs in the get_hw_state
14893 * functions or because the pipe is force-enabled due to the
14895 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14896 crtc->base.base.id,
14897 crtc->base.state->enable ? "enabled" : "disabled",
14898 crtc->active ? "enabled" : "disabled");
14900 crtc->base.state->enable = crtc->active;
14901 crtc->base.state->active = crtc->active;
14902 crtc->base.enabled = crtc->active;
14904 /* Because we only establish the connector -> encoder ->
14905 * crtc links if something is active, this means the
14906 * crtc is now deactivated. Break the links. connector
14907 * -> encoder links are only establish when things are
14908 * actually up, hence no need to break them. */
14909 WARN_ON(crtc->active);
14911 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14912 WARN_ON(encoder->connectors_active);
14913 encoder->base.crtc = NULL;
14917 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14919 * We start out with underrun reporting disabled to avoid races.
14920 * For correct bookkeeping mark this on active crtcs.
14922 * Also on gmch platforms we dont have any hardware bits to
14923 * disable the underrun reporting. Which means we need to start
14924 * out with underrun reporting disabled also on inactive pipes,
14925 * since otherwise we'll complain about the garbage we read when
14926 * e.g. coming up after runtime pm.
14928 * No protection against concurrent access is required - at
14929 * worst a fifo underrun happens which also sets this to false.
14931 crtc->cpu_fifo_underrun_disabled = true;
14932 crtc->pch_fifo_underrun_disabled = true;
14936 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14938 struct intel_connector *connector;
14939 struct drm_device *dev = encoder->base.dev;
14941 /* We need to check both for a crtc link (meaning that the
14942 * encoder is active and trying to read from a pipe) and the
14943 * pipe itself being active. */
14944 bool has_active_crtc = encoder->base.crtc &&
14945 to_intel_crtc(encoder->base.crtc)->active;
14947 if (encoder->connectors_active && !has_active_crtc) {
14948 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14949 encoder->base.base.id,
14950 encoder->base.name);
14952 /* Connector is active, but has no active pipe. This is
14953 * fallout from our resume register restoring. Disable
14954 * the encoder manually again. */
14955 if (encoder->base.crtc) {
14956 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14957 encoder->base.base.id,
14958 encoder->base.name);
14959 encoder->disable(encoder);
14960 if (encoder->post_disable)
14961 encoder->post_disable(encoder);
14963 encoder->base.crtc = NULL;
14964 encoder->connectors_active = false;
14966 /* Inconsistent output/port/pipe state happens presumably due to
14967 * a bug in one of the get_hw_state functions. Or someplace else
14968 * in our code, like the register restore mess on resume. Clamp
14969 * things to off as a safer default. */
14970 for_each_intel_connector(dev, connector) {
14971 if (connector->encoder != encoder)
14973 connector->base.dpms = DRM_MODE_DPMS_OFF;
14974 connector->base.encoder = NULL;
14977 /* Enabled encoders without active connectors will be fixed in
14978 * the crtc fixup. */
14981 void i915_redisable_vga_power_on(struct drm_device *dev)
14983 struct drm_i915_private *dev_priv = dev->dev_private;
14984 u32 vga_reg = i915_vgacntrl_reg(dev);
14986 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14987 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14988 i915_disable_vga(dev);
14992 void i915_redisable_vga(struct drm_device *dev)
14994 struct drm_i915_private *dev_priv = dev->dev_private;
14996 /* This function can be called both from intel_modeset_setup_hw_state or
14997 * at a very early point in our resume sequence, where the power well
14998 * structures are not yet restored. Since this function is at a very
14999 * paranoid "someone might have enabled VGA while we were not looking"
15000 * level, just check if the power well is enabled instead of trying to
15001 * follow the "don't touch the power well if we don't need it" policy
15002 * the rest of the driver uses. */
15003 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15006 i915_redisable_vga_power_on(dev);
15009 static bool primary_get_hw_state(struct intel_crtc *crtc)
15011 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15016 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15019 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15021 struct drm_i915_private *dev_priv = dev->dev_private;
15023 struct intel_crtc *crtc;
15024 struct intel_encoder *encoder;
15025 struct intel_connector *connector;
15028 for_each_intel_crtc(dev, crtc) {
15029 struct drm_plane *primary = crtc->base.primary;
15030 struct intel_plane_state *plane_state;
15032 memset(crtc->config, 0, sizeof(*crtc->config));
15034 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15036 crtc->active = dev_priv->display.get_pipe_config(crtc,
15039 crtc->base.state->enable = crtc->active;
15040 crtc->base.state->active = crtc->active;
15041 crtc->base.enabled = crtc->active;
15043 plane_state = to_intel_plane_state(primary->state);
15044 plane_state->visible = primary_get_hw_state(crtc);
15046 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15047 crtc->base.base.id,
15048 crtc->active ? "enabled" : "disabled");
15051 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15052 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15054 pll->on = pll->get_hw_state(dev_priv, pll,
15055 &pll->config.hw_state);
15057 pll->config.crtc_mask = 0;
15058 for_each_intel_crtc(dev, crtc) {
15059 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15061 pll->config.crtc_mask |= 1 << crtc->pipe;
15065 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15066 pll->name, pll->config.crtc_mask, pll->on);
15068 if (pll->config.crtc_mask)
15069 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15072 for_each_intel_encoder(dev, encoder) {
15075 if (encoder->get_hw_state(encoder, &pipe)) {
15076 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15077 encoder->base.crtc = &crtc->base;
15078 encoder->get_config(encoder, crtc->config);
15080 encoder->base.crtc = NULL;
15083 encoder->connectors_active = false;
15084 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15085 encoder->base.base.id,
15086 encoder->base.name,
15087 encoder->base.crtc ? "enabled" : "disabled",
15091 for_each_intel_connector(dev, connector) {
15092 if (connector->get_hw_state(connector)) {
15093 connector->base.dpms = DRM_MODE_DPMS_ON;
15094 connector->encoder->connectors_active = true;
15095 connector->base.encoder = &connector->encoder->base;
15097 connector->base.dpms = DRM_MODE_DPMS_OFF;
15098 connector->base.encoder = NULL;
15100 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15101 connector->base.base.id,
15102 connector->base.name,
15103 connector->base.encoder ? "enabled" : "disabled");
15107 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15108 * and i915 state tracking structures. */
15109 void intel_modeset_setup_hw_state(struct drm_device *dev,
15110 bool force_restore)
15112 struct drm_i915_private *dev_priv = dev->dev_private;
15114 struct intel_crtc *crtc;
15115 struct intel_encoder *encoder;
15118 intel_modeset_readout_hw_state(dev);
15121 * Now that we have the config, copy it to each CRTC struct
15122 * Note that this could go away if we move to using crtc_config
15123 * checking everywhere.
15125 for_each_intel_crtc(dev, crtc) {
15126 if (crtc->active && i915.fastboot) {
15127 intel_mode_from_pipe_config(&crtc->base.mode,
15129 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15130 crtc->base.base.id);
15131 drm_mode_debug_printmodeline(&crtc->base.mode);
15135 /* HW state is read out, now we need to sanitize this mess. */
15136 for_each_intel_encoder(dev, encoder) {
15137 intel_sanitize_encoder(encoder);
15140 for_each_pipe(dev_priv, pipe) {
15141 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15142 intel_sanitize_crtc(crtc);
15143 intel_dump_pipe_config(crtc, crtc->config,
15144 "[setup_hw_state]");
15147 intel_modeset_update_connector_atomic_state(dev);
15149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15150 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15152 if (!pll->on || pll->active)
15155 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15157 pll->disable(dev_priv, pll);
15162 skl_wm_get_hw_state(dev);
15163 else if (HAS_PCH_SPLIT(dev))
15164 ilk_wm_get_hw_state(dev);
15166 if (force_restore) {
15167 i915_redisable_vga(dev);
15170 * We need to use raw interfaces for restoring state to avoid
15171 * checking (bogus) intermediate states.
15173 for_each_pipe(dev_priv, pipe) {
15174 struct drm_crtc *crtc =
15175 dev_priv->pipe_to_crtc_mapping[pipe];
15177 intel_crtc_restore_mode(crtc);
15180 intel_modeset_update_staged_output_state(dev);
15183 intel_modeset_check_state(dev);
15186 void intel_modeset_gem_init(struct drm_device *dev)
15188 struct drm_i915_private *dev_priv = dev->dev_private;
15189 struct drm_crtc *c;
15190 struct drm_i915_gem_object *obj;
15193 mutex_lock(&dev->struct_mutex);
15194 intel_init_gt_powersave(dev);
15195 mutex_unlock(&dev->struct_mutex);
15198 * There may be no VBT; and if the BIOS enabled SSC we can
15199 * just keep using it to avoid unnecessary flicker. Whereas if the
15200 * BIOS isn't using it, don't assume it will work even if the VBT
15201 * indicates as much.
15203 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15204 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15207 intel_modeset_init_hw(dev);
15209 intel_setup_overlay(dev);
15212 * Make sure any fbs we allocated at startup are properly
15213 * pinned & fenced. When we do the allocation it's too early
15216 for_each_crtc(dev, c) {
15217 obj = intel_fb_obj(c->primary->fb);
15221 mutex_lock(&dev->struct_mutex);
15222 ret = intel_pin_and_fence_fb_obj(c->primary,
15226 mutex_unlock(&dev->struct_mutex);
15228 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15229 to_intel_crtc(c)->pipe);
15230 drm_framebuffer_unreference(c->primary->fb);
15231 c->primary->fb = NULL;
15232 update_state_fb(c->primary);
15236 intel_backlight_register(dev);
15239 void intel_connector_unregister(struct intel_connector *intel_connector)
15241 struct drm_connector *connector = &intel_connector->base;
15243 intel_panel_destroy_backlight(connector);
15244 drm_connector_unregister(connector);
15247 void intel_modeset_cleanup(struct drm_device *dev)
15249 struct drm_i915_private *dev_priv = dev->dev_private;
15250 struct drm_connector *connector;
15252 intel_disable_gt_powersave(dev);
15254 intel_backlight_unregister(dev);
15257 * Interrupts and polling as the first thing to avoid creating havoc.
15258 * Too much stuff here (turning of connectors, ...) would
15259 * experience fancy races otherwise.
15261 intel_irq_uninstall(dev_priv);
15264 * Due to the hpd irq storm handling the hotplug work can re-arm the
15265 * poll handlers. Hence disable polling after hpd handling is shut down.
15267 drm_kms_helper_poll_fini(dev);
15269 mutex_lock(&dev->struct_mutex);
15271 intel_unregister_dsm_handler();
15273 intel_fbc_disable(dev);
15275 mutex_unlock(&dev->struct_mutex);
15277 /* flush any delayed tasks or pending work */
15278 flush_scheduled_work();
15280 /* destroy the backlight and sysfs files before encoders/connectors */
15281 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15282 struct intel_connector *intel_connector;
15284 intel_connector = to_intel_connector(connector);
15285 intel_connector->unregister(intel_connector);
15288 drm_mode_config_cleanup(dev);
15290 intel_cleanup_overlay(dev);
15292 mutex_lock(&dev->struct_mutex);
15293 intel_cleanup_gt_powersave(dev);
15294 mutex_unlock(&dev->struct_mutex);
15298 * Return which encoder is currently attached for connector.
15300 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15302 return &intel_attached_encoder(connector)->base;
15305 void intel_connector_attach_encoder(struct intel_connector *connector,
15306 struct intel_encoder *encoder)
15308 connector->encoder = encoder;
15309 drm_mode_connector_attach_encoder(&connector->base,
15314 * set vga decode state - true == enable VGA decode
15316 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15318 struct drm_i915_private *dev_priv = dev->dev_private;
15319 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15322 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15323 DRM_ERROR("failed to read control word\n");
15327 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15331 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15333 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15335 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15336 DRM_ERROR("failed to write control word\n");
15343 struct intel_display_error_state {
15345 u32 power_well_driver;
15347 int num_transcoders;
15349 struct intel_cursor_error_state {
15354 } cursor[I915_MAX_PIPES];
15356 struct intel_pipe_error_state {
15357 bool power_domain_on;
15360 } pipe[I915_MAX_PIPES];
15362 struct intel_plane_error_state {
15370 } plane[I915_MAX_PIPES];
15372 struct intel_transcoder_error_state {
15373 bool power_domain_on;
15374 enum transcoder cpu_transcoder;
15387 struct intel_display_error_state *
15388 intel_display_capture_error_state(struct drm_device *dev)
15390 struct drm_i915_private *dev_priv = dev->dev_private;
15391 struct intel_display_error_state *error;
15392 int transcoders[] = {
15400 if (INTEL_INFO(dev)->num_pipes == 0)
15403 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15407 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15408 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15410 for_each_pipe(dev_priv, i) {
15411 error->pipe[i].power_domain_on =
15412 __intel_display_power_is_enabled(dev_priv,
15413 POWER_DOMAIN_PIPE(i));
15414 if (!error->pipe[i].power_domain_on)
15417 error->cursor[i].control = I915_READ(CURCNTR(i));
15418 error->cursor[i].position = I915_READ(CURPOS(i));
15419 error->cursor[i].base = I915_READ(CURBASE(i));
15421 error->plane[i].control = I915_READ(DSPCNTR(i));
15422 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15423 if (INTEL_INFO(dev)->gen <= 3) {
15424 error->plane[i].size = I915_READ(DSPSIZE(i));
15425 error->plane[i].pos = I915_READ(DSPPOS(i));
15427 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15428 error->plane[i].addr = I915_READ(DSPADDR(i));
15429 if (INTEL_INFO(dev)->gen >= 4) {
15430 error->plane[i].surface = I915_READ(DSPSURF(i));
15431 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15434 error->pipe[i].source = I915_READ(PIPESRC(i));
15436 if (HAS_GMCH_DISPLAY(dev))
15437 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15440 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15441 if (HAS_DDI(dev_priv->dev))
15442 error->num_transcoders++; /* Account for eDP. */
15444 for (i = 0; i < error->num_transcoders; i++) {
15445 enum transcoder cpu_transcoder = transcoders[i];
15447 error->transcoder[i].power_domain_on =
15448 __intel_display_power_is_enabled(dev_priv,
15449 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15450 if (!error->transcoder[i].power_domain_on)
15453 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15455 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15456 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15457 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15458 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15459 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15460 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15461 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15467 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15470 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15471 struct drm_device *dev,
15472 struct intel_display_error_state *error)
15474 struct drm_i915_private *dev_priv = dev->dev_private;
15480 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15481 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15482 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15483 error->power_well_driver);
15484 for_each_pipe(dev_priv, i) {
15485 err_printf(m, "Pipe [%d]:\n", i);
15486 err_printf(m, " Power: %s\n",
15487 error->pipe[i].power_domain_on ? "on" : "off");
15488 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15489 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15491 err_printf(m, "Plane [%d]:\n", i);
15492 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15493 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15494 if (INTEL_INFO(dev)->gen <= 3) {
15495 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15496 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15498 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15499 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15500 if (INTEL_INFO(dev)->gen >= 4) {
15501 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15502 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15505 err_printf(m, "Cursor [%d]:\n", i);
15506 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15507 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15508 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15511 for (i = 0; i < error->num_transcoders; i++) {
15512 err_printf(m, "CPU transcoder: %c\n",
15513 transcoder_name(error->transcoder[i].cpu_transcoder));
15514 err_printf(m, " Power: %s\n",
15515 error->transcoder[i].power_domain_on ? "on" : "off");
15516 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15517 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15518 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15519 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15520 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15521 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15522 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15526 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15528 struct intel_crtc *crtc;
15530 for_each_intel_crtc(dev, crtc) {
15531 struct intel_unpin_work *work;
15533 spin_lock_irq(&dev->event_lock);
15535 work = crtc->unpin_work;
15537 if (work && work->event &&
15538 work->event->base.file_priv == file) {
15539 kfree(work->event);
15540 work->event = NULL;
15543 spin_unlock_irq(&dev->event_lock);