drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 333         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 434         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 447         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 reg = PIPEDSL(pipe);
 807         u32 line1, line2;
 808         u32 line_mask;
 809
 810         if (IS_GEN2(dev))
 811                 line_mask = DSL_LINEMASK_GEN2;
 812         else
 813                 line_mask = DSL_LINEMASK_GEN3;
 814
 815         line1 = I915_READ(reg) & line_mask;
 816         mdelay(5);
 817         line2 = I915_READ(reg) & line_mask;
 818
 819         return line1 == line2;
 820 }
 821
 822 /*
 823  * intel_wait_for_pipe_off - wait for pipe to turn off
 824  * @dev: drm device
 825  * @pipe: pipe to wait for
 826  *
 827  * After disabling a pipe, we can't wait for vblank in the usual way,
 828  * spinning on the vblank interrupt status bit, since we won't actually
 829  * see an interrupt when the pipe is disabled.
 830  *
 831  * On Gen4 and above:
 832  *   wait for the pipe register state bit to turn off
 833  *
 834  * Otherwise:
 835  *   wait for the display line value to settle (it usually
 836  *   ends up stopping at the start of the next frame).
 837  *
 838  */
 839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 840 {
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 843                                                                       pipe);
 844
 845         if (INTEL_INFO(dev)->gen >= 4) {
 846                 int reg = PIPECONF(cpu_transcoder);
 847
 848                 /* Wait for the Pipe State to go off */
 849                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 850                              100))
 851                         WARN(1, "pipe_off wait timed out\n");
 852         } else {
 853                 /* Wait for the display line to settle */
 854                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 855                         WARN(1, "pipe_off wait timed out\n");
 856         }
 857 }
 858
 859 /*
 860  * ibx_digital_port_connected - is the specified port connected?
 861  * @dev_priv: i915 private structure
 862  * @port: the port to test
 863  *
 864  * Returns true if @port is connected, false otherwise.
 865  */
 866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 867                                 struct intel_digital_port *port)
 868 {
 869         u32 bit;
 870
 871         if (HAS_PCH_IBX(dev_priv->dev)) {
 872                 switch(port->port) {
 873                 case PORT_B:
 874                         bit = SDE_PORTB_HOTPLUG;
 875                         break;
 876                 case PORT_C:
 877                         bit = SDE_PORTC_HOTPLUG;
 878                         break;
 879                 case PORT_D:
 880                         bit = SDE_PORTD_HOTPLUG;
 881                         break;
 882                 default:
 883                         return true;
 884                 }
 885         } else {
 886                 switch(port->port) {
 887                 case PORT_B:
 888                         bit = SDE_PORTB_HOTPLUG_CPT;
 889                         break;
 890                 case PORT_C:
 891                         bit = SDE_PORTC_HOTPLUG_CPT;
 892                         break;
 893                 case PORT_D:
 894                         bit = SDE_PORTD_HOTPLUG_CPT;
 895                         break;
 896                 default:
 897                         return true;
 898                 }
 899         }
 900
 901         return I915_READ(SDEISR) & bit;
 902 }
 903
 904 static const char *state_string(bool enabled)
 905 {
 906         return enabled ? "on" : "off";
 907 }
 908
 909 /* Only for pre-ILK configs */
 910 void assert_pll(struct drm_i915_private *dev_priv,
 911                 enum pipe pipe, bool state)
 912 {
 913         int reg;
 914         u32 val;
 915         bool cur_state;
 916
 917         reg = DPLL(pipe);
 918         val = I915_READ(reg);
 919         cur_state = !!(val & DPLL_VCO_ENABLE);
 920         WARN(cur_state != state,
 921              "PLL state assertion failure (expected %s, current %s)\n",
 922              state_string(state), state_string(cur_state));
 923 }
 924
 925 /* XXX: the dsi pll is shared between MIPI DSI ports */
 926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 927 {
 928         u32 val;
 929         bool cur_state;
 930
 931         mutex_lock(&dev_priv->dpio_lock);
 932         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 933         mutex_unlock(&dev_priv->dpio_lock);
 934
 935         cur_state = val & DSI_PLL_VCO_EN;
 936         WARN(cur_state != state,
 937              "DSI PLL state assertion failure (expected %s, current %s)\n",
 938              state_string(state), state_string(cur_state));
 939 }
 940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 942
 943 struct intel_shared_dpll *
 944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 945 {
 946         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 947
 948         if (crtc->config.shared_dpll < 0)
 949                 return NULL;
 950
 951         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 952 }
 953
 954 /* For ILK+ */
 955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 956                         struct intel_shared_dpll *pll,
 957                         bool state)
 958 {
 959         bool cur_state;
 960         struct intel_dpll_hw_state hw_state;
 961
 962         if (HAS_PCH_LPT(dev_priv->dev)) {
 963                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 964                 return;
 965         }
 966
 967         if (WARN (!pll,
 968                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 969                 return;
 970
 971         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 972         WARN(cur_state != state,
 973              "%s assertion failure (expected %s, current %s)\n",
 974              pll->name, state_string(state), state_string(cur_state));
 975 }
 976
 977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 978                           enum pipe pipe, bool state)
 979 {
 980         int reg;
 981         u32 val;
 982         bool cur_state;
 983         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 984                                                                       pipe);
 985
 986         if (HAS_DDI(dev_priv->dev)) {
 987                 /* DDI does not have a specific FDI_TX register */
 988                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 989                 val = I915_READ(reg);
 990                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 991         } else {
 992                 reg = FDI_TX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_TX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI TX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004                           enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = FDI_RX_CTL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & FDI_RX_ENABLE);
1013         WARN(cur_state != state,
1014              "FDI RX state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         /* ILK FDI PLL is always enabled */
1027         if (dev_priv->info->gen == 5)
1028                 return;
1029
1030         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031         if (HAS_DDI(dev_priv->dev))
1032                 return;
1033
1034         reg = FDI_TX_CTL(pipe);
1035         val = I915_READ(reg);
1036         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = FDI_RX_CTL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049         WARN(cur_state != state,
1050              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055                                   enum pipe pipe)
1056 {
1057         int pp_reg, lvds_reg;
1058         u32 val;
1059         enum pipe panel_pipe = PIPE_A;
1060         bool locked = true;
1061
1062         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063                 pp_reg = PCH_PP_CONTROL;
1064                 lvds_reg = PCH_LVDS;
1065         } else {
1066                 pp_reg = PP_CONTROL;
1067                 lvds_reg = LVDS;
1068         }
1069
1070         val = I915_READ(pp_reg);
1071         if (!(val & PANEL_POWER_ON) ||
1072             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073                 locked = false;
1074
1075         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076                 panel_pipe = PIPE_B;
1077
1078         WARN(panel_pipe == pipe && locked,
1079              "panel assertion failure, pipe %c regs locked\n",
1080              pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         struct drm_device *dev = dev_priv->dev;
1087         bool cur_state;
1088
1089         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091         else if (IS_845G(dev) || IS_I865G(dev))
1092                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093         else
1094                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096         WARN(cur_state != state,
1097              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098              pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104                  enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         /* if we need the pipe A quirk it must be always on */
1113         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114                 state = true;
1115
1116         if (!intel_display_power_enabled(dev_priv->dev,
1117                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118                 cur_state = false;
1119         } else {
1120                 reg = PIPECONF(cpu_transcoder);
1121                 val = I915_READ(reg);
1122                 cur_state = !!(val & PIPECONF_ENABLE);
1123         }
1124
1125         WARN(cur_state != state,
1126              "pipe %c assertion failure (expected %s, current %s)\n",
1127              pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131                          enum plane plane, bool state)
1132 {
1133         int reg;
1134         u32 val;
1135         bool cur_state;
1136
1137         reg = DSPCNTR(plane);
1138         val = I915_READ(reg);
1139         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140         WARN(cur_state != state,
1141              "plane %c assertion failure (expected %s, current %s)\n",
1142              plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149                                    enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154         int cur_pipe;
1155
1156         /* Primary planes are fixed to pipes on gen4+ */
1157         if (INTEL_INFO(dev)->gen >= 4) {
1158                 reg = DSPCNTR(pipe);
1159                 val = I915_READ(reg);
1160                 WARN((val & DISPLAY_PLANE_ENABLE),
1161                      "plane %c assertion failure, should be disabled but not\n",
1162                      plane_name(pipe));
1163                 return;
1164         }
1165
1166         /* Need to check both planes against the pipe */
1167         for_each_pipe(i) {
1168                 reg = DSPCNTR(i);
1169                 val = I915_READ(reg);
1170                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171                         DISPPLANE_SEL_PIPE_SHIFT;
1172                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(i), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179                                     enum pipe pipe)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         int reg, i;
1183         u32 val;
1184
1185         if (IS_VALLEYVIEW(dev)) {
1186                 for (i = 0; i < dev_priv->num_plane; i++) {
1187                         reg = SPCNTR(pipe, i);
1188                         val = I915_READ(reg);
1189                         WARN((val & SP_ENABLE),
1190                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                              sprite_name(pipe, i), pipe_name(pipe));
1192                 }
1193         } else if (INTEL_INFO(dev)->gen >= 7) {
1194                 reg = SPRCTL(pipe);
1195                 val = I915_READ(reg);
1196                 WARN((val & SPRITE_ENABLE),
1197                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198                      plane_name(pipe), pipe_name(pipe));
1199         } else if (INTEL_INFO(dev)->gen >= 5) {
1200                 reg = DVSCNTR(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & DVS_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210         u32 val;
1211         bool enabled;
1212
1213         if (HAS_PCH_LPT(dev_priv->dev)) {
1214                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215                 return;
1216         }
1217
1218         val = I915_READ(PCH_DREF_CONTROL);
1219         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220                             DREF_SUPERSPREAD_SOURCE_MASK));
1221         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229         bool enabled;
1230
1231         reg = PCH_TRANSCONF(pipe);
1232         val = I915_READ(reg);
1233         enabled = !!(val & TRANS_ENABLE);
1234         WARN(enabled,
1235              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236              pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240                             enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242         if ((val & DP_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249                         return false;
1250         } else {
1251                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252                         return false;
1253         }
1254         return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258                               enum pipe pipe, u32 val)
1259 {
1260         if ((val & SDVO_ENABLE) == 0)
1261                 return false;
1262
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274                               enum pipe pipe, u32 val)
1275 {
1276         if ((val & LVDS_PORT_EN) == 0)
1277                 return false;
1278
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290                               enum pipe pipe, u32 val)
1291 {
1292         if ((val & ADPA_DAC_ENABLE) == 0)
1293                 return false;
1294         if (HAS_PCH_CPT(dev_priv->dev)) {
1295                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296                         return false;
1297         } else {
1298                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299                         return false;
1300         }
1301         return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305                                    enum pipe pipe, int reg, u32 port_sel)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313              && (val & DP_PIPEB_SELECT),
1314              "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318                                      enum pipe pipe, int reg)
1319 {
1320         u32 val = I915_READ(reg);
1321         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323              reg, pipe_name(pipe));
1324
1325         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326              && (val & SDVO_PIPE_B_SELECT),
1327              "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331                                       enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335
1336         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340         reg = PCH_ADPA;
1341         val = I915_READ(reg);
1342         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343              "PCH VGA enabled on transcoder %c, should be disabled\n",
1344              pipe_name(pipe));
1345
1346         reg = PCH_LVDS;
1347         val = I915_READ(reg);
1348         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         if (!IS_VALLEYVIEW(dev))
1362                 return;
1363
1364         /*
1365          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1367          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368          *   b. The other bits such as sfr settings / modesel may all be set
1369          *      to 0.
1370          *
1371          * This should only be done on init and resume from S3 with both
1372          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373          */
1374         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379         struct drm_device *dev = crtc->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int reg = DPLL(crtc->pipe);
1382         u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384         assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386         /* No really, not for ILK+ */
1387         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389         /* PLL is protected by panel, make sure we can write it */
1390         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391                 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150);
1396
1397         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401         POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403         /* We do this three times for luck */
1404         I915_WRITE(reg, dpll);
1405         POSTING_READ(reg);
1406         udelay(150); /* wait for warmup */
1407         I915_WRITE(reg, dpll);
1408         POSTING_READ(reg);
1409         udelay(150); /* wait for warmup */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int reg = DPLL(crtc->pipe);
1420         u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422         assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424         /* No really, not for ILK+ */
1425         BUG_ON(dev_priv->info->gen >= 5);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         if (IS_MOBILE(dev) && !IS_I830(dev))
1429                 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431         I915_WRITE(reg, dpll);
1432
1433         /* Wait for the clocks to stabilize. */
1434         POSTING_READ(reg);
1435         udelay(150);
1436
1437         if (INTEL_INFO(dev)->gen >= 4) {
1438                 I915_WRITE(DPLL_MD(crtc->pipe),
1439                            crtc->config.dpll_hw_state.dpll_md);
1440         } else {
1441                 /* The pixel multiplier can only be updated once the
1442                  * DPLL is enabled and the clocks are stable.
1443                  *
1444                  * So write it again.
1445                  */
1446                 I915_WRITE(reg, dpll);
1447         }
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, dpll);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, dpll);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * i9xx_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         /* Don't disable pipe A or pipe A PLLs if needed */
1473         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474                 return;
1475
1476         /* Make sure the pipe isn't still relying on us */
1477         assert_pipe_disabled(dev_priv, pipe);
1478
1479         I915_WRITE(DPLL(pipe), 0);
1480         POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485         u32 val = 0;
1486
1487         /* Make sure the pipe isn't still relying on us */
1488         assert_pipe_disabled(dev_priv, pipe);
1489
1490         /* Leave integrated clock source enabled */
1491         if (pipe == PIPE_B)
1492                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493         I915_WRITE(DPLL(pipe), val);
1494         POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499         u32 port_mask;
1500
1501         if (!port)
1502                 port_mask = DPLL_PORTB_READY_MASK;
1503         else
1504                 port_mask = DPLL_PORTC_READY_MASK;
1505
1506         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508                      'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512  * ironlake_enable_shared_dpll - enable PCH PLL
1513  * @dev_priv: i915 private structure
1514  * @pipe: pipe PLL to enable
1515  *
1516  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517  * drives the transcoder clock.
1518  */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524         /* PCH PLLs only available on ILK, SNB and IVB */
1525         BUG_ON(dev_priv->info->gen < 5);
1526         if (WARN_ON(pll == NULL))
1527                 return;
1528
1529         if (WARN_ON(pll->refcount == 0))
1530                 return;
1531
1532         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533                       pll->name, pll->active, pll->on,
1534                       crtc->base.base.id);
1535
1536         if (pll->active++) {
1537                 WARN_ON(!pll->on);
1538                 assert_shared_dpll_enabled(dev_priv, pll);
1539                 return;
1540         }
1541         WARN_ON(pll->on);
1542
1543         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544         pll->enable(dev_priv, pll);
1545         pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553         /* PCH only available on ILK+ */
1554         BUG_ON(dev_priv->info->gen < 5);
1555         if (WARN_ON(pll == NULL))
1556                return;
1557
1558         if (WARN_ON(pll->refcount == 0))
1559                 return;
1560
1561         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562                       pll->name, pll->active, pll->on,
1563                       crtc->base.base.id);
1564
1565         if (WARN_ON(pll->active == 0)) {
1566                 assert_shared_dpll_disabled(dev_priv, pll);
1567                 return;
1568         }
1569
1570         assert_shared_dpll_enabled(dev_priv, pll);
1571         WARN_ON(!pll->on);
1572         if (--pll->active)
1573                 return;
1574
1575         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576         pll->disable(dev_priv, pll);
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586         uint32_t reg, val, pipeconf_val;
1587
1588         /* PCH only available on ILK+ */
1589         BUG_ON(dev_priv->info->gen < 5);
1590
1591         /* Make sure PCH DPLL is enabled */
1592         assert_shared_dpll_enabled(dev_priv,
1593                                    intel_crtc_to_shared_dpll(intel_crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port, bool dsi)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_cursor_disabled(dev_priv, pipe);
1739         assert_sprites_disabled(dev_priv, pipe);
1740
1741         if (HAS_PCH_LPT(dev_priv->dev))
1742                 pch_transcoder = TRANSCODER_A;
1743         else
1744                 pch_transcoder = pipe;
1745
1746         /*
1747          * A pipe without a PLL won't actually be able to drive bits from
1748          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1749          * need the check.
1750          */
1751         if (!HAS_PCH_SPLIT(dev_priv->dev))
1752                 if (dsi)
1753                         assert_dsi_pll_enabled(dev_priv);
1754                 else
1755                         assert_pll_enabled(dev_priv, pipe);
1756         else {
1757                 if (pch_port) {
1758                         /* if driving the PCH, we need FDI enabled */
1759                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760                         assert_fdi_tx_pll_enabled(dev_priv,
1761                                                   (enum pipe) cpu_transcoder);
1762                 }
1763                 /* FIXME: assert CPU port conditions for SNB+ */
1764         }
1765
1766         reg = PIPECONF(cpu_transcoder);
1767         val = I915_READ(reg);
1768         if (val & PIPECONF_ENABLE)
1769                 return;
1770
1771         I915_WRITE(reg, val | PIPECONF_ENABLE);
1772         intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776  * intel_disable_pipe - disable a pipe, asserting requirements
1777  * @dev_priv: i915 private structure
1778  * @pipe: pipe to disable
1779  *
1780  * Disable @pipe, making sure that various hardware specific requirements
1781  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782  *
1783  * @pipe should be %PIPE_A or %PIPE_B.
1784  *
1785  * Will wait until the pipe has shut down before returning.
1786  */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788                                enum pipe pipe)
1789 {
1790         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791                                                                       pipe);
1792         int reg;
1793         u32 val;
1794
1795         /*
1796          * Make sure planes won't keep trying to pump pixels to us,
1797          * or we might hang the display.
1798          */
1799         assert_planes_disabled(dev_priv, pipe);
1800         assert_cursor_disabled(dev_priv, pipe);
1801         assert_sprites_disabled(dev_priv, pipe);
1802
1803         /* Don't disable pipe A or pipe A PLLs if needed */
1804         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805                 return;
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if ((val & PIPECONF_ENABLE) == 0)
1810                 return;
1811
1812         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817  * Plane regs are double buffered, going from enabled->disabled needs a
1818  * trigger in order to latch.  The display address reg provides this.
1819  */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane)
1822 {
1823         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825         I915_WRITE(reg, I915_READ(reg));
1826         POSTING_READ(reg);
1827 }
1828
1829 /**
1830  * intel_enable_primary_plane - enable the primary plane on a given pipe
1831  * @dev_priv: i915 private structure
1832  * @plane: plane to enable
1833  * @pipe: pipe being fed
1834  *
1835  * Enable @plane on @pipe, making sure that @pipe is running first.
1836  */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838                                        enum plane plane, enum pipe pipe)
1839 {
1840         struct intel_crtc *intel_crtc =
1841                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842         int reg;
1843         u32 val;
1844
1845         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846         assert_pipe_enabled(dev_priv, pipe);
1847
1848         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850         intel_crtc->primary_enabled = true;
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_primary_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_primary_plane - disable the primary plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871                                         enum plane plane, enum pipe pipe)
1872 {
1873         struct intel_crtc *intel_crtc =
1874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875         int reg;
1876         u32 val;
1877
1878         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880         intel_crtc->primary_enabled = false;
1881
1882         reg = DSPCNTR(plane);
1883         val = I915_READ(reg);
1884         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885                 return;
1886
1887         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888         intel_flush_primary_plane(dev_priv, plane);
1889         intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896                 return true;
1897 #endif
1898         return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903                            struct drm_i915_gem_object *obj,
1904                            struct intel_ring_buffer *pipelined)
1905 {
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 alignment;
1908         int ret;
1909
1910         switch (obj->tiling_mode) {
1911         case I915_TILING_NONE:
1912                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913                         alignment = 128 * 1024;
1914                 else if (INTEL_INFO(dev)->gen >= 4)
1915                         alignment = 4 * 1024;
1916                 else
1917                         alignment = 64 * 1024;
1918                 break;
1919         case I915_TILING_X:
1920                 /* pin() will align the object as required by fence */
1921                 alignment = 0;
1922                 break;
1923         case I915_TILING_Y:
1924                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1925                 return -EINVAL;
1926         default:
1927                 BUG();
1928         }
1929
1930         /* Note that the w/a also requires 64 PTE of padding following the
1931          * bo. We currently fill all unused PTE with the shadow page and so
1932          * we should always have valid PTE following the scanout preventing
1933          * the VT-d warning.
1934          */
1935         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936                 alignment = 256 * 1024;
1937
1938         dev_priv->mm.interruptible = false;
1939         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1940         if (ret)
1941                 goto err_interruptible;
1942
1943         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944          * fence, whereas 965+ only requires a fence if using
1945          * framebuffer compression.  For simplicity, we always install
1946          * a fence as the cost is not that onerous.
1947          */
1948         ret = i915_gem_object_get_fence(obj);
1949         if (ret)
1950                 goto err_unpin;
1951
1952         i915_gem_object_pin_fence(obj);
1953
1954         dev_priv->mm.interruptible = true;
1955         return 0;
1956
1957 err_unpin:
1958         i915_gem_object_unpin_from_display_plane(obj);
1959 err_interruptible:
1960         dev_priv->mm.interruptible = true;
1961         return ret;
1962 }
1963
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965 {
1966         i915_gem_object_unpin_fence(obj);
1967         i915_gem_object_unpin_from_display_plane(obj);
1968 }
1969
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971  * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973                                              unsigned int tiling_mode,
1974                                              unsigned int cpp,
1975                                              unsigned int pitch)
1976 {
1977         if (tiling_mode != I915_TILING_NONE) {
1978                 unsigned int tile_rows, tiles;
1979
1980                 tile_rows = *y / 8;
1981                 *y %= 8;
1982
1983                 tiles = *x / (512/cpp);
1984                 *x %= 512/cpp;
1985
1986                 return tile_rows * pitch * 8 + tiles * 4096;
1987         } else {
1988                 unsigned int offset;
1989
1990                 offset = *y * pitch + *x * cpp;
1991                 *y = 0;
1992                 *x = (offset & 4095) / cpp;
1993                 return offset & -4096;
1994         }
1995 }
1996
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998                              int x, int y)
1999 {
2000         struct drm_device *dev = crtc->dev;
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003         struct intel_framebuffer *intel_fb;
2004         struct drm_i915_gem_object *obj;
2005         int plane = intel_crtc->plane;
2006         unsigned long linear_offset;
2007         u32 dspcntr;
2008         u32 reg;
2009
2010         switch (plane) {
2011         case 0:
2012         case 1:
2013                 break;
2014         default:
2015                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2016                 return -EINVAL;
2017         }
2018
2019         intel_fb = to_intel_framebuffer(fb);
2020         obj = intel_fb->obj;
2021
2022         reg = DSPCNTR(plane);
2023         dspcntr = I915_READ(reg);
2024         /* Mask out pixel format bits in case we change it */
2025         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026         switch (fb->pixel_format) {
2027         case DRM_FORMAT_C8:
2028                 dspcntr |= DISPPLANE_8BPP;
2029                 break;
2030         case DRM_FORMAT_XRGB1555:
2031         case DRM_FORMAT_ARGB1555:
2032                 dspcntr |= DISPPLANE_BGRX555;
2033                 break;
2034         case DRM_FORMAT_RGB565:
2035                 dspcntr |= DISPPLANE_BGRX565;
2036                 break;
2037         case DRM_FORMAT_XRGB8888:
2038         case DRM_FORMAT_ARGB8888:
2039                 dspcntr |= DISPPLANE_BGRX888;
2040                 break;
2041         case DRM_FORMAT_XBGR8888:
2042         case DRM_FORMAT_ABGR8888:
2043                 dspcntr |= DISPPLANE_RGBX888;
2044                 break;
2045         case DRM_FORMAT_XRGB2101010:
2046         case DRM_FORMAT_ARGB2101010:
2047                 dspcntr |= DISPPLANE_BGRX101010;
2048                 break;
2049         case DRM_FORMAT_XBGR2101010:
2050         case DRM_FORMAT_ABGR2101010:
2051                 dspcntr |= DISPPLANE_RGBX101010;
2052                 break;
2053         default:
2054                 BUG();
2055         }
2056
2057         if (INTEL_INFO(dev)->gen >= 4) {
2058                 if (obj->tiling_mode != I915_TILING_NONE)
2059                         dspcntr |= DISPPLANE_TILED;
2060                 else
2061                         dspcntr &= ~DISPPLANE_TILED;
2062         }
2063
2064         if (IS_G4X(dev))
2065                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
2067         I915_WRITE(reg, dspcntr);
2068
2069         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2070
2071         if (INTEL_INFO(dev)->gen >= 4) {
2072                 intel_crtc->dspaddr_offset =
2073                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074                                                        fb->bits_per_pixel / 8,
2075                                                        fb->pitches[0]);
2076                 linear_offset -= intel_crtc->dspaddr_offset;
2077         } else {
2078                 intel_crtc->dspaddr_offset = linear_offset;
2079         }
2080
2081         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083                       fb->pitches[0]);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090         } else
2091                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2092         POSTING_READ(reg);
2093
2094         return 0;
2095 }
2096
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098                                  struct drm_framebuffer *fb, int x, int y)
2099 {
2100         struct drm_device *dev = crtc->dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103         struct intel_framebuffer *intel_fb;
2104         struct drm_i915_gem_object *obj;
2105         int plane = intel_crtc->plane;
2106         unsigned long linear_offset;
2107         u32 dspcntr;
2108         u32 reg;
2109
2110         switch (plane) {
2111         case 0:
2112         case 1:
2113         case 2:
2114                 break;
2115         default:
2116                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2117                 return -EINVAL;
2118         }
2119
2120         intel_fb = to_intel_framebuffer(fb);
2121         obj = intel_fb->obj;
2122
2123         reg = DSPCNTR(plane);
2124         dspcntr = I915_READ(reg);
2125         /* Mask out pixel format bits in case we change it */
2126         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127         switch (fb->pixel_format) {
2128         case DRM_FORMAT_C8:
2129                 dspcntr |= DISPPLANE_8BPP;
2130                 break;
2131         case DRM_FORMAT_RGB565:
2132                 dspcntr |= DISPPLANE_BGRX565;
2133                 break;
2134         case DRM_FORMAT_XRGB8888:
2135         case DRM_FORMAT_ARGB8888:
2136                 dspcntr |= DISPPLANE_BGRX888;
2137                 break;
2138         case DRM_FORMAT_XBGR8888:
2139         case DRM_FORMAT_ABGR8888:
2140                 dspcntr |= DISPPLANE_RGBX888;
2141                 break;
2142         case DRM_FORMAT_XRGB2101010:
2143         case DRM_FORMAT_ARGB2101010:
2144                 dspcntr |= DISPPLANE_BGRX101010;
2145                 break;
2146         case DRM_FORMAT_XBGR2101010:
2147         case DRM_FORMAT_ABGR2101010:
2148                 dspcntr |= DISPPLANE_RGBX101010;
2149                 break;
2150         default:
2151                 BUG();
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         if (IS_HASWELL(dev))
2160                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161         else
2162                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2163
2164         I915_WRITE(reg, dspcntr);
2165
2166         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167         intel_crtc->dspaddr_offset =
2168                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169                                                fb->bits_per_pixel / 8,
2170                                                fb->pitches[0]);
2171         linear_offset -= intel_crtc->dspaddr_offset;
2172
2173         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175                       fb->pitches[0]);
2176         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177         I915_MODIFY_DISPBASE(DSPSURF(plane),
2178                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179         if (IS_HASWELL(dev)) {
2180                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181         } else {
2182                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184         }
2185         POSTING_READ(reg);
2186
2187         return 0;
2188 }
2189
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2191 static int
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193                            int x, int y, enum mode_set_atomic state)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198         if (dev_priv->display.disable_fbc)
2199                 dev_priv->display.disable_fbc(dev);
2200         intel_increase_pllclock(crtc);
2201
2202         return dev_priv->display.update_plane(crtc, fb, x, y);
2203 }
2204
2205 void intel_display_handle_reset(struct drm_device *dev)
2206 {
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_crtc *crtc;
2209
2210         /*
2211          * Flips in the rings have been nuked by the reset,
2212          * so complete all pending flips so that user space
2213          * will get its events and not get stuck.
2214          *
2215          * Also update the base address of all primary
2216          * planes to the the last fb to make sure we're
2217          * showing the correct fb after a reset.
2218          *
2219          * Need to make two loops over the crtcs so that we
2220          * don't try to grab a crtc mutex before the
2221          * pending_flip_queue really got woken up.
2222          */
2223
2224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226                 enum plane plane = intel_crtc->plane;
2227
2228                 intel_prepare_page_flip(dev, plane);
2229                 intel_finish_page_flip_plane(dev, plane);
2230         }
2231
2232         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235                 mutex_lock(&crtc->mutex);
2236                 if (intel_crtc->active)
2237                         dev_priv->display.update_plane(crtc, crtc->fb,
2238                                                        crtc->x, crtc->y);
2239                 mutex_unlock(&crtc->mutex);
2240         }
2241 }
2242
2243 static int
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2245 {
2246         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248         bool was_interruptible = dev_priv->mm.interruptible;
2249         int ret;
2250
2251         /* Big Hammer, we also need to ensure that any pending
2252          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253          * current scanout is retired before unpinning the old
2254          * framebuffer.
2255          *
2256          * This should only fail upon a hung GPU, in which case we
2257          * can safely continue.
2258          */
2259         dev_priv->mm.interruptible = false;
2260         ret = i915_gem_object_finish_gpu(obj);
2261         dev_priv->mm.interruptible = was_interruptible;
2262
2263         return ret;
2264 }
2265
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_master_private *master_priv;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272         if (!dev->primary->master)
2273                 return;
2274
2275         master_priv = dev->primary->master->driver_priv;
2276         if (!master_priv->sarea_priv)
2277                 return;
2278
2279         switch (intel_crtc->pipe) {
2280         case 0:
2281                 master_priv->sarea_priv->pipeA_x = x;
2282                 master_priv->sarea_priv->pipeA_y = y;
2283                 break;
2284         case 1:
2285                 master_priv->sarea_priv->pipeB_x = x;
2286                 master_priv->sarea_priv->pipeB_y = y;
2287                 break;
2288         default:
2289                 break;
2290         }
2291 }
2292
2293 static int
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295                     struct drm_framebuffer *fb)
2296 {
2297         struct drm_device *dev = crtc->dev;
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300         struct drm_framebuffer *old_fb;
2301         int ret;
2302
2303         /* no fb bound */
2304         if (!fb) {
2305                 DRM_ERROR("No FB bound\n");
2306                 return 0;
2307         }
2308
2309         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311                           plane_name(intel_crtc->plane),
2312                           INTEL_INFO(dev)->num_pipes);
2313                 return -EINVAL;
2314         }
2315
2316         mutex_lock(&dev->struct_mutex);
2317         ret = intel_pin_and_fence_fb_obj(dev,
2318                                          to_intel_framebuffer(fb)->obj,
2319                                          NULL);
2320         if (ret != 0) {
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("pin & fence failed\n");
2323                 return ret;
2324         }
2325
2326         /*
2327          * Update pipe size and adjust fitter if needed: the reason for this is
2328          * that in compute_mode_changes we check the native mode (not the pfit
2329          * mode) to see if we can flip rather than do a full mode set. In the
2330          * fastboot case, we'll flip, but if we don't update the pipesrc and
2331          * pfit state, we'll end up with a big fb scanned out into the wrong
2332          * sized surface.
2333          *
2334          * To fix this properly, we need to hoist the checks up into
2335          * compute_mode_changes (or above), check the actual pfit state and
2336          * whether the platform allows pfit disable with pipe active, and only
2337          * then update the pipesrc and pfit state, even on the flip path.
2338          */
2339         if (i915_fastboot) {
2340                 const struct drm_display_mode *adjusted_mode =
2341                         &intel_crtc->config.adjusted_mode;
2342
2343                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345                            (adjusted_mode->crtc_vdisplay - 1));
2346                 if (!intel_crtc->config.pch_pfit.enabled &&
2347                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352                 }
2353         }
2354
2355         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2356         if (ret) {
2357                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358                 mutex_unlock(&dev->struct_mutex);
2359                 DRM_ERROR("failed to update base address\n");
2360                 return ret;
2361         }
2362
2363         old_fb = crtc->fb;
2364         crtc->fb = fb;
2365         crtc->x = x;
2366         crtc->y = y;
2367
2368         if (old_fb) {
2369                 if (intel_crtc->active && old_fb != fb)
2370                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2371                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372         }
2373
2374         intel_update_fbc(dev);
2375         intel_edp_psr_update(dev);
2376         mutex_unlock(&dev->struct_mutex);
2377
2378         intel_crtc_update_sarea_pos(crtc, x, y);
2379
2380         return 0;
2381 }
2382
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384 {
2385         struct drm_device *dev = crtc->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388         int pipe = intel_crtc->pipe;
2389         u32 reg, temp;
2390
2391         /* enable normal train */
2392         reg = FDI_TX_CTL(pipe);
2393         temp = I915_READ(reg);
2394         if (IS_IVYBRIDGE(dev)) {
2395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         } else {
2398                 temp &= ~FDI_LINK_TRAIN_NONE;
2399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         }
2401         I915_WRITE(reg, temp);
2402
2403         reg = FDI_RX_CTL(pipe);
2404         temp = I915_READ(reg);
2405         if (HAS_PCH_CPT(dev)) {
2406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408         } else {
2409                 temp &= ~FDI_LINK_TRAIN_NONE;
2410                 temp |= FDI_LINK_TRAIN_NONE;
2411         }
2412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414         /* wait one idle pattern time */
2415         POSTING_READ(reg);
2416         udelay(1000);
2417
2418         /* IVB wants error correction enabled */
2419         if (IS_IVYBRIDGE(dev))
2420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421                            FDI_FE_ERRC_ENABLE);
2422 }
2423
2424 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2425 {
2426         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2427 }
2428
2429 static void ivb_modeset_global_resources(struct drm_device *dev)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_crtc *pipe_B_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2434         struct intel_crtc *pipe_C_crtc =
2435                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2436         uint32_t temp;
2437
2438         /*
2439          * When everything is off disable fdi C so that we could enable fdi B
2440          * with all lanes. Note that we don't care about enabled pipes without
2441          * an enabled pch encoder.
2442          */
2443         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2444             !pipe_has_enabled_pch(pipe_C_crtc)) {
2445                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447
2448                 temp = I915_READ(SOUTH_CHICKEN1);
2449                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451                 I915_WRITE(SOUTH_CHICKEN1, temp);
2452         }
2453 }
2454
2455 /* The FDI link training functions for ILK/Ibexpeak. */
2456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457 {
2458         struct drm_device *dev = crtc->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461         int pipe = intel_crtc->pipe;
2462         int plane = intel_crtc->plane;
2463         u32 reg, temp, tries;
2464
2465         /* FDI needs bits from pipe & plane first */
2466         assert_pipe_enabled(dev_priv, pipe);
2467         assert_plane_enabled(dev_priv, plane);
2468
2469         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470            for train result */
2471         reg = FDI_RX_IMR(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_RX_SYMBOL_LOCK;
2474         temp &= ~FDI_RX_BIT_LOCK;
2475         I915_WRITE(reg, temp);
2476         I915_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2487
2488         reg = FDI_RX_CTL(pipe);
2489         temp = I915_READ(reg);
2490         temp &= ~FDI_LINK_TRAIN_NONE;
2491         temp |= FDI_LINK_TRAIN_PATTERN_1;
2492         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494         POSTING_READ(reg);
2495         udelay(150);
2496
2497         /* Ironlake workaround, enable clock pointer after FDI enable*/
2498         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2500                    FDI_RX_PHASE_SYNC_POINTER_EN);
2501
2502         reg = FDI_RX_IIR(pipe);
2503         for (tries = 0; tries < 5; tries++) {
2504                 temp = I915_READ(reg);
2505                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506
2507                 if ((temp & FDI_RX_BIT_LOCK)) {
2508                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2509                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2510                         break;
2511                 }
2512         }
2513         if (tries == 5)
2514                 DRM_ERROR("FDI train 1 fail!\n");
2515
2516         /* Train 2 */
2517         reg = FDI_TX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_2;
2521         I915_WRITE(reg, temp);
2522
2523         reg = FDI_RX_CTL(pipe);
2524         temp = I915_READ(reg);
2525         temp &= ~FDI_LINK_TRAIN_NONE;
2526         temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         I915_WRITE(reg, temp);
2528
2529         POSTING_READ(reg);
2530         udelay(150);
2531
2532         reg = FDI_RX_IIR(pipe);
2533         for (tries = 0; tries < 5; tries++) {
2534                 temp = I915_READ(reg);
2535                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536
2537                 if (temp & FDI_RX_SYMBOL_LOCK) {
2538                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                         break;
2541                 }
2542         }
2543         if (tries == 5)
2544                 DRM_ERROR("FDI train 2 fail!\n");
2545
2546         DRM_DEBUG_KMS("FDI train done\n");
2547
2548 }
2549
2550 static const int snb_b_fdi_train_param[] = {
2551         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2552         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2553         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2554         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555 };
2556
2557 /* The FDI link training functions for SNB/Cougarpoint. */
2558 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2559 {
2560         struct drm_device *dev = crtc->dev;
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563         int pipe = intel_crtc->pipe;
2564         u32 reg, temp, i, retry;
2565
2566         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567            for train result */
2568         reg = FDI_RX_IMR(pipe);
2569         temp = I915_READ(reg);
2570         temp &= ~FDI_RX_SYMBOL_LOCK;
2571         temp &= ~FDI_RX_BIT_LOCK;
2572         I915_WRITE(reg, temp);
2573
2574         POSTING_READ(reg);
2575         udelay(150);
2576
2577         /* enable CPU FDI TX and PCH FDI RX */
2578         reg = FDI_TX_CTL(pipe);
2579         temp = I915_READ(reg);
2580         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2581         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2582         temp &= ~FDI_LINK_TRAIN_NONE;
2583         temp |= FDI_LINK_TRAIN_PATTERN_1;
2584         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585         /* SNB-B */
2586         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2587         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2588
2589         I915_WRITE(FDI_RX_MISC(pipe),
2590                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591
2592         reg = FDI_RX_CTL(pipe);
2593         temp = I915_READ(reg);
2594         if (HAS_PCH_CPT(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597         } else {
2598                 temp &= ~FDI_LINK_TRAIN_NONE;
2599                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600         }
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         for (i = 0; i < 4; i++) {
2607                 reg = FDI_TX_CTL(pipe);
2608                 temp = I915_READ(reg);
2609                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610                 temp |= snb_b_fdi_train_param[i];
2611                 I915_WRITE(reg, temp);
2612
2613                 POSTING_READ(reg);
2614                 udelay(500);
2615
2616                 for (retry = 0; retry < 5; retry++) {
2617                         reg = FDI_RX_IIR(pipe);
2618                         temp = I915_READ(reg);
2619                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620                         if (temp & FDI_RX_BIT_LOCK) {
2621                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623                                 break;
2624                         }
2625                         udelay(50);
2626                 }
2627                 if (retry < 5)
2628                         break;
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2;
2638         if (IS_GEN6(dev)) {
2639                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640                 /* SNB-B */
2641                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642         }
2643         I915_WRITE(reg, temp);
2644
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         if (HAS_PCH_CPT(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650         } else {
2651                 temp &= ~FDI_LINK_TRAIN_NONE;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653         }
2654         I915_WRITE(reg, temp);
2655
2656         POSTING_READ(reg);
2657         udelay(150);
2658
2659         for (i = 0; i < 4; i++) {
2660                 reg = FDI_TX_CTL(pipe);
2661                 temp = I915_READ(reg);
2662                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663                 temp |= snb_b_fdi_train_param[i];
2664                 I915_WRITE(reg, temp);
2665
2666                 POSTING_READ(reg);
2667                 udelay(500);
2668
2669                 for (retry = 0; retry < 5; retry++) {
2670                         reg = FDI_RX_IIR(pipe);
2671                         temp = I915_READ(reg);
2672                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673                         if (temp & FDI_RX_SYMBOL_LOCK) {
2674                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676                                 break;
2677                         }
2678                         udelay(50);
2679                 }
2680                 if (retry < 5)
2681                         break;
2682         }
2683         if (i == 4)
2684                 DRM_ERROR("FDI train 2 fail!\n");
2685
2686         DRM_DEBUG_KMS("FDI train done.\n");
2687 }
2688
2689 /* Manual link training for Ivy Bridge A0 parts */
2690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691 {
2692         struct drm_device *dev = crtc->dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp, i, j;
2697
2698         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699            for train result */
2700         reg = FDI_RX_IMR(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~FDI_RX_SYMBOL_LOCK;
2703         temp &= ~FDI_RX_BIT_LOCK;
2704         I915_WRITE(reg, temp);
2705
2706         POSTING_READ(reg);
2707         udelay(150);
2708
2709         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710                       I915_READ(FDI_RX_IIR(pipe)));
2711
2712         /* Try each vswing and preemphasis setting twice before moving on */
2713         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2714                 /* disable first in case we need to retry */
2715                 reg = FDI_TX_CTL(pipe);
2716                 temp = I915_READ(reg);
2717                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718                 temp &= ~FDI_TX_ENABLE;
2719                 I915_WRITE(reg, temp);
2720
2721                 reg = FDI_RX_CTL(pipe);
2722                 temp = I915_READ(reg);
2723                 temp &= ~FDI_LINK_TRAIN_AUTO;
2724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725                 temp &= ~FDI_RX_ENABLE;
2726                 I915_WRITE(reg, temp);
2727
2728                 /* enable CPU FDI TX and PCH FDI RX */
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2732                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2733                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2734                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735                 temp |= snb_b_fdi_train_param[j/2];
2736                 temp |= FDI_COMPOSITE_SYNC;
2737                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2738
2739                 I915_WRITE(FDI_RX_MISC(pipe),
2740                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2741
2742                 reg = FDI_RX_CTL(pipe);
2743                 temp = I915_READ(reg);
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745                 temp |= FDI_COMPOSITE_SYNC;
2746                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2747
2748                 POSTING_READ(reg);
2749                 udelay(1); /* should be 0.5us */
2750
2751                 for (i = 0; i < 4; i++) {
2752                         reg = FDI_RX_IIR(pipe);
2753                         temp = I915_READ(reg);
2754                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2755
2756                         if (temp & FDI_RX_BIT_LOCK ||
2757                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2758                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2759                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2760                                               i);
2761                                 break;
2762                         }
2763                         udelay(1); /* should be 0.5us */
2764                 }
2765                 if (i == 4) {
2766                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2767                         continue;
2768                 }
2769
2770                 /* Train 2 */
2771                 reg = FDI_TX_CTL(pipe);
2772                 temp = I915_READ(reg);
2773                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775                 I915_WRITE(reg, temp);
2776
2777                 reg = FDI_RX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2780                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2781                 I915_WRITE(reg, temp);
2782
2783                 POSTING_READ(reg);
2784                 udelay(2); /* should be 1.5us */
2785
2786                 for (i = 0; i < 4; i++) {
2787                         reg = FDI_RX_IIR(pipe);
2788                         temp = I915_READ(reg);
2789                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2790
2791                         if (temp & FDI_RX_SYMBOL_LOCK ||
2792                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2793                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2794                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2795                                               i);
2796                                 goto train_done;
2797                         }
2798                         udelay(2); /* should be 1.5us */
2799                 }
2800                 if (i == 4)
2801                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2802         }
2803
2804 train_done:
2805         DRM_DEBUG_KMS("FDI train done.\n");
2806 }
2807
2808 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2809 {
2810         struct drm_device *dev = intel_crtc->base.dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         int pipe = intel_crtc->pipe;
2813         u32 reg, temp;
2814
2815
2816         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2817         reg = FDI_RX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2820         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2821         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2822         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2823
2824         POSTING_READ(reg);
2825         udelay(200);
2826
2827         /* Switch from Rawclk to PCDclk */
2828         temp = I915_READ(reg);
2829         I915_WRITE(reg, temp | FDI_PCDCLK);
2830
2831         POSTING_READ(reg);
2832         udelay(200);
2833
2834         /* Enable CPU FDI TX PLL, always on for Ironlake */
2835         reg = FDI_TX_CTL(pipe);
2836         temp = I915_READ(reg);
2837         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                 POSTING_READ(reg);
2841                 udelay(100);
2842         }
2843 }
2844
2845 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2846 {
2847         struct drm_device *dev = intel_crtc->base.dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         int pipe = intel_crtc->pipe;
2850         u32 reg, temp;
2851
2852         /* Switch from PCDclk to Rawclk */
2853         reg = FDI_RX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2856
2857         /* Disable CPU FDI TX PLL */
2858         reg = FDI_TX_CTL(pipe);
2859         temp = I915_READ(reg);
2860         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2861
2862         POSTING_READ(reg);
2863         udelay(100);
2864
2865         reg = FDI_RX_CTL(pipe);
2866         temp = I915_READ(reg);
2867         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2868
2869         /* Wait for the clocks to turn off. */
2870         POSTING_READ(reg);
2871         udelay(100);
2872 }
2873
2874 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879         int pipe = intel_crtc->pipe;
2880         u32 reg, temp;
2881
2882         /* disable CPU FDI tx and PCH FDI rx */
2883         reg = FDI_TX_CTL(pipe);
2884         temp = I915_READ(reg);
2885         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2886         POSTING_READ(reg);
2887
2888         reg = FDI_RX_CTL(pipe);
2889         temp = I915_READ(reg);
2890         temp &= ~(0x7 << 16);
2891         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2892         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2893
2894         POSTING_READ(reg);
2895         udelay(100);
2896
2897         /* Ironlake workaround, disable clock pointer after downing FDI */
2898         if (HAS_PCH_IBX(dev)) {
2899                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2900         }
2901
2902         /* still set train pattern 1 */
2903         reg = FDI_TX_CTL(pipe);
2904         temp = I915_READ(reg);
2905         temp &= ~FDI_LINK_TRAIN_NONE;
2906         temp |= FDI_LINK_TRAIN_PATTERN_1;
2907         I915_WRITE(reg, temp);
2908
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         if (HAS_PCH_CPT(dev)) {
2912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914         } else {
2915                 temp &= ~FDI_LINK_TRAIN_NONE;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2917         }
2918         /* BPC in FDI rx is consistent with that in PIPECONF */
2919         temp &= ~(0x07 << 16);
2920         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2921         I915_WRITE(reg, temp);
2922
2923         POSTING_READ(reg);
2924         udelay(100);
2925 }
2926
2927 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2928 {
2929         struct drm_device *dev = crtc->dev;
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932         unsigned long flags;
2933         bool pending;
2934
2935         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2936             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2937                 return false;
2938
2939         spin_lock_irqsave(&dev->event_lock, flags);
2940         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2941         spin_unlock_irqrestore(&dev->event_lock, flags);
2942
2943         return pending;
2944 }
2945
2946 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2947 {
2948         struct drm_device *dev = crtc->dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951         if (crtc->fb == NULL)
2952                 return;
2953
2954         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2955
2956         wait_event(dev_priv->pending_flip_queue,
2957                    !intel_crtc_has_pending_flip(crtc));
2958
2959         mutex_lock(&dev->struct_mutex);
2960         intel_finish_fb(crtc->fb);
2961         mutex_unlock(&dev->struct_mutex);
2962 }
2963
2964 /* Program iCLKIP clock to the desired frequency */
2965 static void lpt_program_iclkip(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2970         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971         u32 temp;
2972
2973         mutex_lock(&dev_priv->dpio_lock);
2974
2975         /* It is necessary to ungate the pixclk gate prior to programming
2976          * the divisors, and gate it back when it is done.
2977          */
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980         /* Disable SSCCTL */
2981         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2982                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983                                 SBI_SSCCTL_DISABLE,
2984                         SBI_ICLK);
2985
2986         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2987         if (clock == 20000) {
2988                 auxdiv = 1;
2989                 divsel = 0x41;
2990                 phaseinc = 0x20;
2991         } else {
2992                 /* The iCLK virtual clock root frequency is in MHz,
2993                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2994                  * divisors, it is necessary to divide one by another, so we
2995                  * convert the virtual clock precision to KHz here for higher
2996                  * precision.
2997                  */
2998                 u32 iclk_virtual_root_freq = 172800 * 1000;
2999                 u32 iclk_pi_range = 64;
3000                 u32 desired_divisor, msb_divisor_value, pi_value;
3001
3002                 desired_divisor = (iclk_virtual_root_freq / clock);
3003                 msb_divisor_value = desired_divisor / iclk_pi_range;
3004                 pi_value = desired_divisor % iclk_pi_range;
3005
3006                 auxdiv = 0;
3007                 divsel = msb_divisor_value - 2;
3008                 phaseinc = pi_value;
3009         }
3010
3011         /* This should not happen with any sane values */
3012         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3018                         clock,
3019                         auxdiv,
3020                         divsel,
3021                         phasedir,
3022                         phaseinc);
3023
3024         /* Program SSCDIVINTPHASE6 */
3025         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3026         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3032         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3033
3034         /* Program SSCAUXDIV */
3035         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3036         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3038         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3039
3040         /* Enable modulator and associated divider */
3041         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3042         temp &= ~SBI_SSCCTL_DISABLE;
3043         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3044
3045         /* Wait for initialization time */
3046         udelay(24);
3047
3048         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3049
3050         mutex_unlock(&dev_priv->dpio_lock);
3051 }
3052
3053 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3054                                                 enum pipe pch_transcoder)
3055 {
3056         struct drm_device *dev = crtc->base.dev;
3057         struct drm_i915_private *dev_priv = dev->dev_private;
3058         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3059
3060         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3061                    I915_READ(HTOTAL(cpu_transcoder)));
3062         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3063                    I915_READ(HBLANK(cpu_transcoder)));
3064         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3065                    I915_READ(HSYNC(cpu_transcoder)));
3066
3067         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3068                    I915_READ(VTOTAL(cpu_transcoder)));
3069         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3070                    I915_READ(VBLANK(cpu_transcoder)));
3071         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3072                    I915_READ(VSYNC(cpu_transcoder)));
3073         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3074                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3075 }
3076
3077 /*
3078  * Enable PCH resources required for PCH ports:
3079  *   - PCH PLLs
3080  *   - FDI training & RX/TX
3081  *   - update transcoder timings
3082  *   - DP transcoding bits
3083  *   - transcoder
3084  */
3085 static void ironlake_pch_enable(struct drm_crtc *crtc)
3086 {
3087         struct drm_device *dev = crtc->dev;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3090         int pipe = intel_crtc->pipe;
3091         u32 reg, temp;
3092
3093         assert_pch_transcoder_disabled(dev_priv, pipe);
3094
3095         /* Write the TU size bits before fdi link training, so that error
3096          * detection works. */
3097         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3098                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3099
3100         /* For PCH output, training FDI link */
3101         dev_priv->display.fdi_link_train(crtc);
3102
3103         /* We need to program the right clock selection before writing the pixel
3104          * mutliplier into the DPLL. */
3105         if (HAS_PCH_CPT(dev)) {
3106                 u32 sel;
3107
3108                 temp = I915_READ(PCH_DPLL_SEL);
3109                 temp |= TRANS_DPLL_ENABLE(pipe);
3110                 sel = TRANS_DPLLB_SEL(pipe);
3111                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3112                         temp |= sel;
3113                 else
3114                         temp &= ~sel;
3115                 I915_WRITE(PCH_DPLL_SEL, temp);
3116         }
3117
3118         /* XXX: pch pll's can be enabled any time before we enable the PCH
3119          * transcoder, and we actually should do this to not upset any PCH
3120          * transcoder that already use the clock when we share it.
3121          *
3122          * Note that enable_shared_dpll tries to do the right thing, but
3123          * get_shared_dpll unconditionally resets the pll - we need that to have
3124          * the right LVDS enable sequence. */
3125         ironlake_enable_shared_dpll(intel_crtc);
3126
3127         /* set transcoder timing, panel must allow it */
3128         assert_panel_unlocked(dev_priv, pipe);
3129         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3130
3131         intel_fdi_normal_train(crtc);
3132
3133         /* For PCH DP, enable TRANS_DP_CTL */
3134         if (HAS_PCH_CPT(dev) &&
3135             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3136              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3137                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3138                 reg = TRANS_DP_CTL(pipe);
3139                 temp = I915_READ(reg);
3140                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3141                           TRANS_DP_SYNC_MASK |
3142                           TRANS_DP_BPC_MASK);
3143                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3144                          TRANS_DP_ENH_FRAMING);
3145                 temp |= bpc << 9; /* same format but at 11:9 */
3146
3147                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3148                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3149                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3150                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3151
3152                 switch (intel_trans_dp_port_sel(crtc)) {
3153                 case PCH_DP_B:
3154                         temp |= TRANS_DP_PORT_SEL_B;
3155                         break;
3156                 case PCH_DP_C:
3157                         temp |= TRANS_DP_PORT_SEL_C;
3158                         break;
3159                 case PCH_DP_D:
3160                         temp |= TRANS_DP_PORT_SEL_D;
3161                         break;
3162                 default:
3163                         BUG();
3164                 }
3165
3166                 I915_WRITE(reg, temp);
3167         }
3168
3169         ironlake_enable_pch_transcoder(dev_priv, pipe);
3170 }
3171
3172 static void lpt_pch_enable(struct drm_crtc *crtc)
3173 {
3174         struct drm_device *dev = crtc->dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3178
3179         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3180
3181         lpt_program_iclkip(crtc);
3182
3183         /* Set transcoder timing. */
3184         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3185
3186         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3187 }
3188
3189 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3190 {
3191         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3192
3193         if (pll == NULL)
3194                 return;
3195
3196         if (pll->refcount == 0) {
3197                 WARN(1, "bad %s refcount\n", pll->name);
3198                 return;
3199         }
3200
3201         if (--pll->refcount == 0) {
3202                 WARN_ON(pll->on);
3203                 WARN_ON(pll->active);
3204         }
3205
3206         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3207 }
3208
3209 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3210 {
3211         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3212         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3213         enum intel_dpll_id i;
3214
3215         if (pll) {
3216                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3217                               crtc->base.base.id, pll->name);
3218                 intel_put_shared_dpll(crtc);
3219         }
3220
3221         if (HAS_PCH_IBX(dev_priv->dev)) {
3222                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3223                 i = (enum intel_dpll_id) crtc->pipe;
3224                 pll = &dev_priv->shared_dplls[i];
3225
3226                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3227                               crtc->base.base.id, pll->name);
3228
3229                 goto found;
3230         }
3231
3232         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3233                 pll = &dev_priv->shared_dplls[i];
3234
3235                 /* Only want to check enabled timings first */
3236                 if (pll->refcount == 0)
3237                         continue;
3238
3239                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3240                            sizeof(pll->hw_state)) == 0) {
3241                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3242                                       crtc->base.base.id,
3243                                       pll->name, pll->refcount, pll->active);
3244
3245                         goto found;
3246                 }
3247         }
3248
3249         /* Ok no matching timings, maybe there's a free one? */
3250         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3251                 pll = &dev_priv->shared_dplls[i];
3252                 if (pll->refcount == 0) {
3253                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3254                                       crtc->base.base.id, pll->name);
3255                         goto found;
3256                 }
3257         }
3258
3259         return NULL;
3260
3261 found:
3262         crtc->config.shared_dpll = i;
3263         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3264                          pipe_name(crtc->pipe));
3265
3266         if (pll->active == 0) {
3267                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3268                        sizeof(pll->hw_state));
3269
3270                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3271                 WARN_ON(pll->on);
3272                 assert_shared_dpll_disabled(dev_priv, pll);
3273
3274                 pll->mode_set(dev_priv, pll);
3275         }
3276         pll->refcount++;
3277
3278         return pll;
3279 }
3280
3281 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3282 {
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         int dslreg = PIPEDSL(pipe);
3285         u32 temp;
3286
3287         temp = I915_READ(dslreg);
3288         udelay(500);
3289         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3290                 if (wait_for(I915_READ(dslreg) != temp, 5))
3291                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3292         }
3293 }
3294
3295 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3296 {
3297         struct drm_device *dev = crtc->base.dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         int pipe = crtc->pipe;
3300
3301         if (crtc->config.pch_pfit.enabled) {
3302                 /* Force use of hard-coded filter coefficients
3303                  * as some pre-programmed values are broken,
3304                  * e.g. x201.
3305                  */
3306                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3307                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3308                                                  PF_PIPE_SEL_IVB(pipe));
3309                 else
3310                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3311                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3312                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3313         }
3314 }
3315
3316 static void intel_enable_planes(struct drm_crtc *crtc)
3317 {
3318         struct drm_device *dev = crtc->dev;
3319         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3320         struct intel_plane *intel_plane;
3321
3322         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3323                 if (intel_plane->pipe == pipe)
3324                         intel_plane_restore(&intel_plane->base);
3325 }
3326
3327 static void intel_disable_planes(struct drm_crtc *crtc)
3328 {
3329         struct drm_device *dev = crtc->dev;
3330         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3331         struct intel_plane *intel_plane;
3332
3333         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3334                 if (intel_plane->pipe == pipe)
3335                         intel_plane_disable(&intel_plane->base);
3336 }
3337
3338 void hsw_enable_ips(struct intel_crtc *crtc)
3339 {
3340         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3341
3342         if (!crtc->config.ips_enabled)
3343                 return;
3344
3345         /* We can only enable IPS after we enable a plane and wait for a vblank.
3346          * We guarantee that the plane is enabled by calling intel_enable_ips
3347          * only after intel_enable_plane. And intel_enable_plane already waits
3348          * for a vblank, so all we need to do here is to enable the IPS bit. */
3349         assert_plane_enabled(dev_priv, crtc->plane);
3350         I915_WRITE(IPS_CTL, IPS_ENABLE);
3351
3352         /* The bit only becomes 1 in the next vblank, so this wait here is
3353          * essentially intel_wait_for_vblank. If we don't have this and don't
3354          * wait for vblanks until the end of crtc_enable, then the HW state
3355          * readout code will complain that the expected IPS_CTL value is not the
3356          * one we read. */
3357         if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3358                 DRM_ERROR("Timed out waiting for IPS enable\n");
3359 }
3360
3361 void hsw_disable_ips(struct intel_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->base.dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366         if (!crtc->config.ips_enabled)
3367                 return;
3368
3369         assert_plane_enabled(dev_priv, crtc->plane);
3370         I915_WRITE(IPS_CTL, 0);
3371         POSTING_READ(IPS_CTL);
3372
3373         /* We need to wait for a vblank before we can disable the plane. */
3374         intel_wait_for_vblank(dev, crtc->pipe);
3375 }
3376
3377 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3378 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         enum pipe pipe = intel_crtc->pipe;
3384         int palreg = PALETTE(pipe);
3385         int i;
3386         bool reenable_ips = false;
3387
3388         /* The clocks have to be on to load the palette. */
3389         if (!crtc->enabled || !intel_crtc->active)
3390                 return;
3391
3392         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3393                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3394                         assert_dsi_pll_enabled(dev_priv);
3395                 else
3396                         assert_pll_enabled(dev_priv, pipe);
3397         }
3398
3399         /* use legacy palette for Ironlake */
3400         if (HAS_PCH_SPLIT(dev))
3401                 palreg = LGC_PALETTE(pipe);
3402
3403         /* Workaround : Do not read or write the pipe palette/gamma data while
3404          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3405          */
3406         if (intel_crtc->config.ips_enabled &&
3407             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3408              GAMMA_MODE_MODE_SPLIT)) {
3409                 hsw_disable_ips(intel_crtc);
3410                 reenable_ips = true;
3411         }
3412
3413         for (i = 0; i < 256; i++) {
3414                 I915_WRITE(palreg + 4 * i,
3415                            (intel_crtc->lut_r[i] << 16) |
3416                            (intel_crtc->lut_g[i] << 8) |
3417                            intel_crtc->lut_b[i]);
3418         }
3419
3420         if (reenable_ips)
3421                 hsw_enable_ips(intel_crtc);
3422 }
3423
3424 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         struct drm_i915_private *dev_priv = dev->dev_private;
3428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429         struct intel_encoder *encoder;
3430         int pipe = intel_crtc->pipe;
3431         int plane = intel_crtc->plane;
3432
3433         WARN_ON(!crtc->enabled);
3434
3435         if (intel_crtc->active)
3436                 return;
3437
3438         intel_crtc->active = true;
3439
3440         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3441         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3442
3443         for_each_encoder_on_crtc(dev, crtc, encoder)
3444                 if (encoder->pre_enable)
3445                         encoder->pre_enable(encoder);
3446
3447         if (intel_crtc->config.has_pch_encoder) {
3448                 /* Note: FDI PLL enabling _must_ be done before we enable the
3449                  * cpu pipes, hence this is separate from all the other fdi/pch
3450                  * enabling. */
3451                 ironlake_fdi_pll_enable(intel_crtc);
3452         } else {
3453                 assert_fdi_tx_disabled(dev_priv, pipe);
3454                 assert_fdi_rx_disabled(dev_priv, pipe);
3455         }
3456
3457         ironlake_pfit_enable(intel_crtc);
3458
3459         /*
3460          * On ILK+ LUT must be loaded before the pipe is running but with
3461          * clocks enabled
3462          */
3463         intel_crtc_load_lut(crtc);
3464
3465         intel_update_watermarks(crtc);
3466         intel_enable_pipe(dev_priv, pipe,
3467                           intel_crtc->config.has_pch_encoder, false);
3468         intel_enable_primary_plane(dev_priv, plane, pipe);
3469         intel_enable_planes(crtc);
3470         intel_crtc_update_cursor(crtc, true);
3471
3472         if (intel_crtc->config.has_pch_encoder)
3473                 ironlake_pch_enable(crtc);
3474
3475         mutex_lock(&dev->struct_mutex);
3476         intel_update_fbc(dev);
3477         mutex_unlock(&dev->struct_mutex);
3478
3479         for_each_encoder_on_crtc(dev, crtc, encoder)
3480                 encoder->enable(encoder);
3481
3482         if (HAS_PCH_CPT(dev))
3483                 cpt_verify_modeset(dev, intel_crtc->pipe);
3484
3485         /*
3486          * There seems to be a race in PCH platform hw (at least on some
3487          * outputs) where an enabled pipe still completes any pageflip right
3488          * away (as if the pipe is off) instead of waiting for vblank. As soon
3489          * as the first vblank happend, everything works as expected. Hence just
3490          * wait for one vblank before returning to avoid strange things
3491          * happening.
3492          */
3493         intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 /* IPS only exists on ULT machines and is tied to pipe A. */
3497 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3498 {
3499         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3500 }
3501
3502 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         int plane = intel_crtc->plane;
3509
3510         intel_enable_primary_plane(dev_priv, plane, pipe);
3511         intel_enable_planes(crtc);
3512         intel_crtc_update_cursor(crtc, true);
3513
3514         hsw_enable_ips(intel_crtc);
3515
3516         mutex_lock(&dev->struct_mutex);
3517         intel_update_fbc(dev);
3518         mutex_unlock(&dev->struct_mutex);
3519 }
3520
3521 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526         int pipe = intel_crtc->pipe;
3527         int plane = intel_crtc->plane;
3528
3529         intel_crtc_wait_for_pending_flips(crtc);
3530         drm_vblank_off(dev, pipe);
3531
3532         /* FBC must be disabled before disabling the plane on HSW. */
3533         if (dev_priv->fbc.plane == plane)
3534                 intel_disable_fbc(dev);
3535
3536         hsw_disable_ips(intel_crtc);
3537
3538         intel_crtc_update_cursor(crtc, false);
3539         intel_disable_planes(crtc);
3540         intel_disable_primary_plane(dev_priv, plane, pipe);
3541 }
3542
3543 /*
3544  * This implements the workaround described in the "notes" section of the mode
3545  * set sequence documentation. When going from no pipes or single pipe to
3546  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3547  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3548  */
3549 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->base.dev;
3552         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3553
3554         /* We want to get the other_active_crtc only if there's only 1 other
3555          * active crtc. */
3556         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3557                 if (!crtc_it->active || crtc_it == crtc)
3558                         continue;
3559
3560                 if (other_active_crtc)
3561                         return;
3562
3563                 other_active_crtc = crtc_it;
3564         }
3565         if (!other_active_crtc)
3566                 return;
3567
3568         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3569         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3570 }
3571
3572 static void haswell_crtc_enable(struct drm_crtc *crtc)
3573 {
3574         struct drm_device *dev = crtc->dev;
3575         struct drm_i915_private *dev_priv = dev->dev_private;
3576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3577         struct intel_encoder *encoder;
3578         int pipe = intel_crtc->pipe;
3579
3580         WARN_ON(!crtc->enabled);
3581
3582         if (intel_crtc->active)
3583                 return;
3584
3585         intel_crtc->active = true;
3586
3587         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3588         if (intel_crtc->config.has_pch_encoder)
3589                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3590
3591         if (intel_crtc->config.has_pch_encoder)
3592                 dev_priv->display.fdi_link_train(crtc);
3593
3594         for_each_encoder_on_crtc(dev, crtc, encoder)
3595                 if (encoder->pre_enable)
3596                         encoder->pre_enable(encoder);
3597
3598         intel_ddi_enable_pipe_clock(intel_crtc);
3599
3600         ironlake_pfit_enable(intel_crtc);
3601
3602         /*
3603          * On ILK+ LUT must be loaded before the pipe is running but with
3604          * clocks enabled
3605          */
3606         intel_crtc_load_lut(crtc);
3607
3608         intel_ddi_set_pipe_settings(crtc);
3609         intel_ddi_enable_transcoder_func(crtc);
3610
3611         intel_update_watermarks(crtc);
3612         intel_enable_pipe(dev_priv, pipe,
3613                           intel_crtc->config.has_pch_encoder, false);
3614
3615         if (intel_crtc->config.has_pch_encoder)
3616                 lpt_pch_enable(crtc);
3617
3618         for_each_encoder_on_crtc(dev, crtc, encoder) {
3619                 encoder->enable(encoder);
3620                 intel_opregion_notify_encoder(encoder, true);
3621         }
3622
3623         /* If we change the relative order between pipe/planes enabling, we need
3624          * to change the workaround. */
3625         haswell_mode_set_planes_workaround(intel_crtc);
3626         haswell_crtc_enable_planes(crtc);
3627
3628         /*
3629          * There seems to be a race in PCH platform hw (at least on some
3630          * outputs) where an enabled pipe still completes any pageflip right
3631          * away (as if the pipe is off) instead of waiting for vblank. As soon
3632          * as the first vblank happend, everything works as expected. Hence just
3633          * wait for one vblank before returning to avoid strange things
3634          * happening.
3635          */
3636         intel_wait_for_vblank(dev, intel_crtc->pipe);
3637 }
3638
3639 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->base.dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         int pipe = crtc->pipe;
3644
3645         /* To avoid upsetting the power well on haswell only disable the pfit if
3646          * it's in use. The hw state code will make sure we get this right. */
3647         if (crtc->config.pch_pfit.enabled) {
3648                 I915_WRITE(PF_CTL(pipe), 0);
3649                 I915_WRITE(PF_WIN_POS(pipe), 0);
3650                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3651         }
3652 }
3653
3654 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3655 {
3656         struct drm_device *dev = crtc->dev;
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659         struct intel_encoder *encoder;
3660         int pipe = intel_crtc->pipe;
3661         int plane = intel_crtc->plane;
3662         u32 reg, temp;
3663
3664
3665         if (!intel_crtc->active)
3666                 return;
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->disable(encoder);
3670
3671         intel_crtc_wait_for_pending_flips(crtc);
3672         drm_vblank_off(dev, pipe);
3673
3674         if (dev_priv->fbc.plane == plane)
3675                 intel_disable_fbc(dev);
3676
3677         intel_crtc_update_cursor(crtc, false);
3678         intel_disable_planes(crtc);
3679         intel_disable_primary_plane(dev_priv, plane, pipe);
3680
3681         if (intel_crtc->config.has_pch_encoder)
3682                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3683
3684         intel_disable_pipe(dev_priv, pipe);
3685
3686         ironlake_pfit_disable(intel_crtc);
3687
3688         for_each_encoder_on_crtc(dev, crtc, encoder)
3689                 if (encoder->post_disable)
3690                         encoder->post_disable(encoder);
3691
3692         if (intel_crtc->config.has_pch_encoder) {
3693                 ironlake_fdi_disable(crtc);
3694
3695                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3696                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3697
3698                 if (HAS_PCH_CPT(dev)) {
3699                         /* disable TRANS_DP_CTL */
3700                         reg = TRANS_DP_CTL(pipe);
3701                         temp = I915_READ(reg);
3702                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3703                                   TRANS_DP_PORT_SEL_MASK);
3704                         temp |= TRANS_DP_PORT_SEL_NONE;
3705                         I915_WRITE(reg, temp);
3706
3707                         /* disable DPLL_SEL */
3708                         temp = I915_READ(PCH_DPLL_SEL);
3709                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3710                         I915_WRITE(PCH_DPLL_SEL, temp);
3711                 }
3712
3713                 /* disable PCH DPLL */
3714                 intel_disable_shared_dpll(intel_crtc);
3715
3716                 ironlake_fdi_pll_disable(intel_crtc);
3717         }
3718
3719         intel_crtc->active = false;
3720         intel_update_watermarks(crtc);
3721
3722         mutex_lock(&dev->struct_mutex);
3723         intel_update_fbc(dev);
3724         mutex_unlock(&dev->struct_mutex);
3725 }
3726
3727 static void haswell_crtc_disable(struct drm_crtc *crtc)
3728 {
3729         struct drm_device *dev = crtc->dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732         struct intel_encoder *encoder;
3733         int pipe = intel_crtc->pipe;
3734         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3735
3736         if (!intel_crtc->active)
3737                 return;
3738
3739         haswell_crtc_disable_planes(crtc);
3740
3741         for_each_encoder_on_crtc(dev, crtc, encoder) {
3742                 intel_opregion_notify_encoder(encoder, false);
3743                 encoder->disable(encoder);
3744         }
3745
3746         if (intel_crtc->config.has_pch_encoder)
3747                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3748         intel_disable_pipe(dev_priv, pipe);
3749
3750         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3751
3752         ironlake_pfit_disable(intel_crtc);
3753
3754         intel_ddi_disable_pipe_clock(intel_crtc);
3755
3756         for_each_encoder_on_crtc(dev, crtc, encoder)
3757                 if (encoder->post_disable)
3758                         encoder->post_disable(encoder);
3759
3760         if (intel_crtc->config.has_pch_encoder) {
3761                 lpt_disable_pch_transcoder(dev_priv);
3762                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3763                 intel_ddi_fdi_disable(crtc);
3764         }
3765
3766         intel_crtc->active = false;
3767         intel_update_watermarks(crtc);
3768
3769         mutex_lock(&dev->struct_mutex);
3770         intel_update_fbc(dev);
3771         mutex_unlock(&dev->struct_mutex);
3772 }
3773
3774 static void ironlake_crtc_off(struct drm_crtc *crtc)
3775 {
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         intel_put_shared_dpll(intel_crtc);
3778 }
3779
3780 static void haswell_crtc_off(struct drm_crtc *crtc)
3781 {
3782         intel_ddi_put_crtc_pll(crtc);
3783 }
3784
3785 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3786 {
3787         if (!enable && intel_crtc->overlay) {
3788                 struct drm_device *dev = intel_crtc->base.dev;
3789                 struct drm_i915_private *dev_priv = dev->dev_private;
3790
3791                 mutex_lock(&dev->struct_mutex);
3792                 dev_priv->mm.interruptible = false;
3793                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3794                 dev_priv->mm.interruptible = true;
3795                 mutex_unlock(&dev->struct_mutex);
3796         }
3797
3798         /* Let userspace switch the overlay on again. In most cases userspace
3799          * has to recompute where to put it anyway.
3800          */
3801 }
3802
3803 /**
3804  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3805  * cursor plane briefly if not already running after enabling the display
3806  * plane.
3807  * This workaround avoids occasional blank screens when self refresh is
3808  * enabled.
3809  */
3810 static void
3811 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3812 {
3813         u32 cntl = I915_READ(CURCNTR(pipe));
3814
3815         if ((cntl & CURSOR_MODE) == 0) {
3816                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3817
3818                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3819                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3820                 intel_wait_for_vblank(dev_priv->dev, pipe);
3821                 I915_WRITE(CURCNTR(pipe), cntl);
3822                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3823                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3824         }
3825 }
3826
3827 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3828 {
3829         struct drm_device *dev = crtc->base.dev;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc_config *pipe_config = &crtc->config;
3832
3833         if (!crtc->config.gmch_pfit.control)
3834                 return;
3835
3836         /*
3837          * The panel fitter should only be adjusted whilst the pipe is disabled,
3838          * according to register description and PRM.
3839          */
3840         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3841         assert_pipe_disabled(dev_priv, crtc->pipe);
3842
3843         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3844         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3845
3846         /* Border color in case we don't scale up to the full screen. Black by
3847          * default, change to something else for debugging. */
3848         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3849 }
3850
3851 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3852 {
3853         struct drm_device *dev = crtc->dev;
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856         struct intel_encoder *encoder;
3857         int pipe = intel_crtc->pipe;
3858         int plane = intel_crtc->plane;
3859         bool is_dsi;
3860
3861         WARN_ON(!crtc->enabled);
3862
3863         if (intel_crtc->active)
3864                 return;
3865
3866         intel_crtc->active = true;
3867
3868         for_each_encoder_on_crtc(dev, crtc, encoder)
3869                 if (encoder->pre_pll_enable)
3870                         encoder->pre_pll_enable(encoder);
3871
3872         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3873
3874         if (!is_dsi)
3875                 vlv_enable_pll(intel_crtc);
3876
3877         for_each_encoder_on_crtc(dev, crtc, encoder)
3878                 if (encoder->pre_enable)
3879                         encoder->pre_enable(encoder);
3880
3881         i9xx_pfit_enable(intel_crtc);
3882
3883         intel_crtc_load_lut(crtc);
3884
3885         intel_update_watermarks(crtc);
3886         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3887         intel_enable_primary_plane(dev_priv, plane, pipe);
3888         intel_enable_planes(crtc);
3889         intel_crtc_update_cursor(crtc, true);
3890
3891         intel_update_fbc(dev);
3892
3893         for_each_encoder_on_crtc(dev, crtc, encoder)
3894                 encoder->enable(encoder);
3895 }
3896
3897 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3898 {
3899         struct drm_device *dev = crtc->dev;
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902         struct intel_encoder *encoder;
3903         int pipe = intel_crtc->pipe;
3904         int plane = intel_crtc->plane;
3905
3906         WARN_ON(!crtc->enabled);
3907
3908         if (intel_crtc->active)
3909                 return;
3910
3911         intel_crtc->active = true;
3912
3913         for_each_encoder_on_crtc(dev, crtc, encoder)
3914                 if (encoder->pre_enable)
3915                         encoder->pre_enable(encoder);
3916
3917         i9xx_enable_pll(intel_crtc);
3918
3919         i9xx_pfit_enable(intel_crtc);
3920
3921         intel_crtc_load_lut(crtc);
3922
3923         intel_update_watermarks(crtc);
3924         intel_enable_pipe(dev_priv, pipe, false, false);
3925         intel_enable_primary_plane(dev_priv, plane, pipe);
3926         intel_enable_planes(crtc);
3927         /* The fixup needs to happen before cursor is enabled */
3928         if (IS_G4X(dev))
3929                 g4x_fixup_plane(dev_priv, pipe);
3930         intel_crtc_update_cursor(crtc, true);
3931
3932         /* Give the overlay scaler a chance to enable if it's on this pipe */
3933         intel_crtc_dpms_overlay(intel_crtc, true);
3934
3935         intel_update_fbc(dev);
3936
3937         for_each_encoder_on_crtc(dev, crtc, encoder)
3938                 encoder->enable(encoder);
3939 }
3940
3941 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3942 {
3943         struct drm_device *dev = crtc->base.dev;
3944         struct drm_i915_private *dev_priv = dev->dev_private;
3945
3946         if (!crtc->config.gmch_pfit.control)
3947                 return;
3948
3949         assert_pipe_disabled(dev_priv, crtc->pipe);
3950
3951         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3952                          I915_READ(PFIT_CONTROL));
3953         I915_WRITE(PFIT_CONTROL, 0);
3954 }
3955
3956 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         struct intel_encoder *encoder;
3962         int pipe = intel_crtc->pipe;
3963         int plane = intel_crtc->plane;
3964
3965         if (!intel_crtc->active)
3966                 return;
3967
3968         for_each_encoder_on_crtc(dev, crtc, encoder)
3969                 encoder->disable(encoder);
3970
3971         /* Give the overlay scaler a chance to disable if it's on this pipe */
3972         intel_crtc_wait_for_pending_flips(crtc);
3973         drm_vblank_off(dev, pipe);
3974
3975         if (dev_priv->fbc.plane == plane)
3976                 intel_disable_fbc(dev);
3977
3978         intel_crtc_dpms_overlay(intel_crtc, false);
3979         intel_crtc_update_cursor(crtc, false);
3980         intel_disable_planes(crtc);
3981         intel_disable_primary_plane(dev_priv, plane, pipe);
3982
3983         intel_disable_pipe(dev_priv, pipe);
3984
3985         i9xx_pfit_disable(intel_crtc);
3986
3987         for_each_encoder_on_crtc(dev, crtc, encoder)
3988                 if (encoder->post_disable)
3989                         encoder->post_disable(encoder);
3990
3991         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3992                 vlv_disable_pll(dev_priv, pipe);
3993         else if (!IS_VALLEYVIEW(dev))
3994                 i9xx_disable_pll(dev_priv, pipe);
3995
3996         intel_crtc->active = false;
3997         intel_update_watermarks(crtc);
3998
3999         intel_update_fbc(dev);
4000 }
4001
4002 static void i9xx_crtc_off(struct drm_crtc *crtc)
4003 {
4004 }
4005
4006 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4007                                     bool enabled)
4008 {
4009         struct drm_device *dev = crtc->dev;
4010         struct drm_i915_master_private *master_priv;
4011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4012         int pipe = intel_crtc->pipe;
4013
4014         if (!dev->primary->master)
4015                 return;
4016
4017         master_priv = dev->primary->master->driver_priv;
4018         if (!master_priv->sarea_priv)
4019                 return;
4020
4021         switch (pipe) {
4022         case 0:
4023                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4024                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4025                 break;
4026         case 1:
4027                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4028                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4029                 break;
4030         default:
4031                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4032                 break;
4033         }
4034 }
4035
4036 /**
4037  * Sets the power management mode of the pipe and plane.
4038  */
4039 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4040 {
4041         struct drm_device *dev = crtc->dev;
4042         struct drm_i915_private *dev_priv = dev->dev_private;
4043         struct intel_encoder *intel_encoder;
4044         bool enable = false;
4045
4046         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4047                 enable |= intel_encoder->connectors_active;
4048
4049         if (enable)
4050                 dev_priv->display.crtc_enable(crtc);
4051         else
4052                 dev_priv->display.crtc_disable(crtc);
4053
4054         intel_crtc_update_sarea(crtc, enable);
4055 }
4056
4057 static void intel_crtc_disable(struct drm_crtc *crtc)
4058 {
4059         struct drm_device *dev = crtc->dev;
4060         struct drm_connector *connector;
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063
4064         /* crtc should still be enabled when we disable it. */
4065         WARN_ON(!crtc->enabled);
4066
4067         dev_priv->display.crtc_disable(crtc);
4068         intel_crtc->eld_vld = false;
4069         intel_crtc_update_sarea(crtc, false);
4070         dev_priv->display.off(crtc);
4071
4072         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4073         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4074         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4075
4076         if (crtc->fb) {
4077                 mutex_lock(&dev->struct_mutex);
4078                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4079                 mutex_unlock(&dev->struct_mutex);
4080                 crtc->fb = NULL;
4081         }
4082
4083         /* Update computed state. */
4084         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4085                 if (!connector->encoder || !connector->encoder->crtc)
4086                         continue;
4087
4088                 if (connector->encoder->crtc != crtc)
4089                         continue;
4090
4091                 connector->dpms = DRM_MODE_DPMS_OFF;
4092                 to_intel_encoder(connector->encoder)->connectors_active = false;
4093         }
4094 }
4095
4096 void intel_encoder_destroy(struct drm_encoder *encoder)
4097 {
4098         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4099
4100         drm_encoder_cleanup(encoder);
4101         kfree(intel_encoder);
4102 }
4103
4104 /* Simple dpms helper for encoders with just one connector, no cloning and only
4105  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4106  * state of the entire output pipe. */
4107 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4108 {
4109         if (mode == DRM_MODE_DPMS_ON) {
4110                 encoder->connectors_active = true;
4111
4112                 intel_crtc_update_dpms(encoder->base.crtc);
4113         } else {
4114                 encoder->connectors_active = false;
4115
4116                 intel_crtc_update_dpms(encoder->base.crtc);
4117         }
4118 }
4119
4120 /* Cross check the actual hw state with our own modeset state tracking (and it's
4121  * internal consistency). */
4122 static void intel_connector_check_state(struct intel_connector *connector)
4123 {
4124         if (connector->get_hw_state(connector)) {
4125                 struct intel_encoder *encoder = connector->encoder;
4126                 struct drm_crtc *crtc;
4127                 bool encoder_enabled;
4128                 enum pipe pipe;
4129
4130                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4131                               connector->base.base.id,
4132                               drm_get_connector_name(&connector->base));
4133
4134                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4135                      "wrong connector dpms state\n");
4136                 WARN(connector->base.encoder != &encoder->base,
4137                      "active connector not linked to encoder\n");
4138                 WARN(!encoder->connectors_active,
4139                      "encoder->connectors_active not set\n");
4140
4141                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4142                 WARN(!encoder_enabled, "encoder not enabled\n");
4143                 if (WARN_ON(!encoder->base.crtc))
4144                         return;
4145
4146                 crtc = encoder->base.crtc;
4147
4148                 WARN(!crtc->enabled, "crtc not enabled\n");
4149                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4150                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4151                      "encoder active on the wrong pipe\n");
4152         }
4153 }
4154
4155 /* Even simpler default implementation, if there's really no special case to
4156  * consider. */
4157 void intel_connector_dpms(struct drm_connector *connector, int mode)
4158 {
4159         struct intel_encoder *encoder = intel_attached_encoder(connector);
4160
4161         /* All the simple cases only support two dpms states. */
4162         if (mode != DRM_MODE_DPMS_ON)
4163                 mode = DRM_MODE_DPMS_OFF;
4164
4165         if (mode == connector->dpms)
4166                 return;
4167
4168         connector->dpms = mode;
4169
4170         /* Only need to change hw state when actually enabled */
4171         if (encoder->base.crtc)
4172                 intel_encoder_dpms(encoder, mode);
4173         else
4174                 WARN_ON(encoder->connectors_active != false);
4175
4176         intel_modeset_check_state(connector->dev);
4177 }
4178
4179 /* Simple connector->get_hw_state implementation for encoders that support only
4180  * one connector and no cloning and hence the encoder state determines the state
4181  * of the connector. */
4182 bool intel_connector_get_hw_state(struct intel_connector *connector)
4183 {
4184         enum pipe pipe = 0;
4185         struct intel_encoder *encoder = connector->encoder;
4186
4187         return encoder->get_hw_state(encoder, &pipe);
4188 }
4189
4190 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4191                                      struct intel_crtc_config *pipe_config)
4192 {
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         struct intel_crtc *pipe_B_crtc =
4195                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4196
4197         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4198                       pipe_name(pipe), pipe_config->fdi_lanes);
4199         if (pipe_config->fdi_lanes > 4) {
4200                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4201                               pipe_name(pipe), pipe_config->fdi_lanes);
4202                 return false;
4203         }
4204
4205         if (IS_HASWELL(dev)) {
4206                 if (pipe_config->fdi_lanes > 2) {
4207                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4208                                       pipe_config->fdi_lanes);
4209                         return false;
4210                 } else {
4211                         return true;
4212                 }
4213         }
4214
4215         if (INTEL_INFO(dev)->num_pipes == 2)
4216                 return true;
4217
4218         /* Ivybridge 3 pipe is really complicated */
4219         switch (pipe) {
4220         case PIPE_A:
4221                 return true;
4222         case PIPE_B:
4223                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4224                     pipe_config->fdi_lanes > 2) {
4225                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4226                                       pipe_name(pipe), pipe_config->fdi_lanes);
4227                         return false;
4228                 }
4229                 return true;
4230         case PIPE_C:
4231                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4232                     pipe_B_crtc->config.fdi_lanes <= 2) {
4233                         if (pipe_config->fdi_lanes > 2) {
4234                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4235                                               pipe_name(pipe), pipe_config->fdi_lanes);
4236                                 return false;
4237                         }
4238                 } else {
4239                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4240                         return false;
4241                 }
4242                 return true;
4243         default:
4244                 BUG();
4245         }
4246 }
4247
4248 #define RETRY 1
4249 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4250                                        struct intel_crtc_config *pipe_config)
4251 {
4252         struct drm_device *dev = intel_crtc->base.dev;
4253         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4254         int lane, link_bw, fdi_dotclock;
4255         bool setup_ok, needs_recompute = false;
4256
4257 retry:
4258         /* FDI is a binary signal running at ~2.7GHz, encoding
4259          * each output octet as 10 bits. The actual frequency
4260          * is stored as a divider into a 100MHz clock, and the
4261          * mode pixel clock is stored in units of 1KHz.
4262          * Hence the bw of each lane in terms of the mode signal
4263          * is:
4264          */
4265         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4266
4267         fdi_dotclock = adjusted_mode->crtc_clock;
4268
4269         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4270                                            pipe_config->pipe_bpp);
4271
4272         pipe_config->fdi_lanes = lane;
4273
4274         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4275                                link_bw, &pipe_config->fdi_m_n);
4276
4277         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4278                                             intel_crtc->pipe, pipe_config);
4279         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4280                 pipe_config->pipe_bpp -= 2*3;
4281                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4282                               pipe_config->pipe_bpp);
4283                 needs_recompute = true;
4284                 pipe_config->bw_constrained = true;
4285
4286                 goto retry;
4287         }
4288
4289         if (needs_recompute)
4290                 return RETRY;
4291
4292         return setup_ok ? 0 : -EINVAL;
4293 }
4294
4295 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4296                                    struct intel_crtc_config *pipe_config)
4297 {
4298         pipe_config->ips_enabled = i915_enable_ips &&
4299                                    hsw_crtc_supports_ips(crtc) &&
4300                                    pipe_config->pipe_bpp <= 24;
4301 }
4302
4303 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4304                                      struct intel_crtc_config *pipe_config)
4305 {
4306         struct drm_device *dev = crtc->base.dev;
4307         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4308
4309         /* FIXME should check pixel clock limits on all platforms */
4310         if (INTEL_INFO(dev)->gen < 4) {
4311                 struct drm_i915_private *dev_priv = dev->dev_private;
4312                 int clock_limit =
4313                         dev_priv->display.get_display_clock_speed(dev);
4314
4315                 /*
4316                  * Enable pixel doubling when the dot clock
4317                  * is > 90% of the (display) core speed.
4318                  *
4319                  * GDG double wide on either pipe,
4320                  * otherwise pipe A only.
4321                  */
4322                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4323                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4324                         clock_limit *= 2;
4325                         pipe_config->double_wide = true;
4326                 }
4327
4328                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4329                         return -EINVAL;
4330         }
4331
4332         /*
4333          * Pipe horizontal size must be even in:
4334          * - DVO ganged mode
4335          * - LVDS dual channel mode
4336          * - Double wide pipe
4337          */
4338         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4339              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4340                 pipe_config->pipe_src_w &= ~1;
4341
4342         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4343          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4344          */
4345         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4346                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4347                 return -EINVAL;
4348
4349         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4350                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4351         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4352                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4353                  * for lvds. */
4354                 pipe_config->pipe_bpp = 8*3;
4355         }
4356
4357         if (HAS_IPS(dev))
4358                 hsw_compute_ips_config(crtc, pipe_config);
4359
4360         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4361          * clock survives for now. */
4362         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4363                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4364
4365         if (pipe_config->has_pch_encoder)
4366                 return ironlake_fdi_compute_config(crtc, pipe_config);
4367
4368         return 0;
4369 }
4370
4371 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4372 {
4373         return 400000; /* FIXME */
4374 }
4375
4376 static int i945_get_display_clock_speed(struct drm_device *dev)
4377 {
4378         return 400000;
4379 }
4380
4381 static int i915_get_display_clock_speed(struct drm_device *dev)
4382 {
4383         return 333000;
4384 }
4385
4386 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4387 {
4388         return 200000;
4389 }
4390
4391 static int pnv_get_display_clock_speed(struct drm_device *dev)
4392 {
4393         u16 gcfgc = 0;
4394
4395         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4396
4397         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4398         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4399                 return 267000;
4400         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4401                 return 333000;
4402         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4403                 return 444000;
4404         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4405                 return 200000;
4406         default:
4407                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4408         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4409                 return 133000;
4410         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4411                 return 167000;
4412         }
4413 }
4414
4415 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4416 {
4417         u16 gcfgc = 0;
4418
4419         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4420
4421         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4422                 return 133000;
4423         else {
4424                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4425                 case GC_DISPLAY_CLOCK_333_MHZ:
4426                         return 333000;
4427                 default:
4428                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4429                         return 190000;
4430                 }
4431         }
4432 }
4433
4434 static int i865_get_display_clock_speed(struct drm_device *dev)
4435 {
4436         return 266000;
4437 }
4438
4439 static int i855_get_display_clock_speed(struct drm_device *dev)
4440 {
4441         u16 hpllcc = 0;
4442         /* Assume that the hardware is in the high speed state.  This
4443          * should be the default.
4444          */
4445         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4446         case GC_CLOCK_133_200:
4447         case GC_CLOCK_100_200:
4448                 return 200000;
4449         case GC_CLOCK_166_250:
4450                 return 250000;
4451         case GC_CLOCK_100_133:
4452                 return 133000;
4453         }
4454
4455         /* Shouldn't happen */
4456         return 0;
4457 }
4458
4459 static int i830_get_display_clock_speed(struct drm_device *dev)
4460 {
4461         return 133000;
4462 }
4463
4464 static void
4465 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4466 {
4467         while (*num > DATA_LINK_M_N_MASK ||
4468                *den > DATA_LINK_M_N_MASK) {
4469                 *num >>= 1;
4470                 *den >>= 1;
4471         }
4472 }
4473
4474 static void compute_m_n(unsigned int m, unsigned int n,
4475                         uint32_t *ret_m, uint32_t *ret_n)
4476 {
4477         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4478         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4479         intel_reduce_m_n_ratio(ret_m, ret_n);
4480 }
4481
4482 void
4483 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4484                        int pixel_clock, int link_clock,
4485                        struct intel_link_m_n *m_n)
4486 {
4487         m_n->tu = 64;
4488
4489         compute_m_n(bits_per_pixel * pixel_clock,
4490                     link_clock * nlanes * 8,
4491                     &m_n->gmch_m, &m_n->gmch_n);
4492
4493         compute_m_n(pixel_clock, link_clock,
4494                     &m_n->link_m, &m_n->link_n);
4495 }
4496
4497 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4498 {
4499         if (i915_panel_use_ssc >= 0)
4500                 return i915_panel_use_ssc != 0;
4501         return dev_priv->vbt.lvds_use_ssc
4502                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4503 }
4504
4505 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4506 {
4507         struct drm_device *dev = crtc->dev;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         int refclk;
4510
4511         if (IS_VALLEYVIEW(dev)) {
4512                 refclk = 100000;
4513         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4514             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4515                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4516                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4517                               refclk / 1000);
4518         } else if (!IS_GEN2(dev)) {
4519                 refclk = 96000;
4520         } else {
4521                 refclk = 48000;
4522         }
4523
4524         return refclk;
4525 }
4526
4527 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4528 {
4529         return (1 << dpll->n) << 16 | dpll->m2;
4530 }
4531
4532 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4533 {
4534         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4535 }
4536
4537 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4538                                      intel_clock_t *reduced_clock)
4539 {
4540         struct drm_device *dev = crtc->base.dev;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         int pipe = crtc->pipe;
4543         u32 fp, fp2 = 0;
4544
4545         if (IS_PINEVIEW(dev)) {
4546                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4547                 if (reduced_clock)
4548                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4549         } else {
4550                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4551                 if (reduced_clock)
4552                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4553         }
4554
4555         I915_WRITE(FP0(pipe), fp);
4556         crtc->config.dpll_hw_state.fp0 = fp;
4557
4558         crtc->lowfreq_avail = false;
4559         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4560             reduced_clock && i915_powersave) {
4561                 I915_WRITE(FP1(pipe), fp2);
4562                 crtc->config.dpll_hw_state.fp1 = fp2;
4563                 crtc->lowfreq_avail = true;
4564         } else {
4565                 I915_WRITE(FP1(pipe), fp);
4566                 crtc->config.dpll_hw_state.fp1 = fp;
4567         }
4568 }
4569
4570 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4571                 pipe)
4572 {
4573         u32 reg_val;
4574
4575         /*
4576          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4577          * and set it to a reasonable value instead.
4578          */
4579         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4580         reg_val &= 0xffffff00;
4581         reg_val |= 0x00000030;
4582         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4583
4584         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4585         reg_val &= 0x8cffffff;
4586         reg_val = 0x8c000000;
4587         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4588
4589         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4590         reg_val &= 0xffffff00;
4591         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4592
4593         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4594         reg_val &= 0x00ffffff;
4595         reg_val |= 0xb0000000;
4596         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4597 }
4598
4599 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4600                                          struct intel_link_m_n *m_n)
4601 {
4602         struct drm_device *dev = crtc->base.dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         int pipe = crtc->pipe;
4605
4606         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4607         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4608         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4609         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4610 }
4611
4612 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4613                                          struct intel_link_m_n *m_n)
4614 {
4615         struct drm_device *dev = crtc->base.dev;
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         int pipe = crtc->pipe;
4618         enum transcoder transcoder = crtc->config.cpu_transcoder;
4619
4620         if (INTEL_INFO(dev)->gen >= 5) {
4621                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4622                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4623                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4624                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4625         } else {
4626                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4627                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4628                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4629                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4630         }
4631 }
4632
4633 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4634 {
4635         if (crtc->config.has_pch_encoder)
4636                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4637         else
4638                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4639 }
4640
4641 static void vlv_update_pll(struct intel_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->base.dev;
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         int pipe = crtc->pipe;
4646         u32 dpll, mdiv;
4647         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4648         u32 coreclk, reg_val, dpll_md;
4649
4650         mutex_lock(&dev_priv->dpio_lock);
4651
4652         bestn = crtc->config.dpll.n;
4653         bestm1 = crtc->config.dpll.m1;
4654         bestm2 = crtc->config.dpll.m2;
4655         bestp1 = crtc->config.dpll.p1;
4656         bestp2 = crtc->config.dpll.p2;
4657
4658         /* See eDP HDMI DPIO driver vbios notes doc */
4659
4660         /* PLL B needs special handling */
4661         if (pipe)
4662                 vlv_pllb_recal_opamp(dev_priv, pipe);
4663
4664         /* Set up Tx target for periodic Rcomp update */
4665         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4666
4667         /* Disable target IRef on PLL */
4668         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4669         reg_val &= 0x00ffffff;
4670         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4671
4672         /* Disable fast lock */
4673         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4674
4675         /* Set idtafcrecal before PLL is enabled */
4676         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4677         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4678         mdiv |= ((bestn << DPIO_N_SHIFT));
4679         mdiv |= (1 << DPIO_K_SHIFT);
4680
4681         /*
4682          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4683          * but we don't support that).
4684          * Note: don't use the DAC post divider as it seems unstable.
4685          */
4686         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4687         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4688
4689         mdiv |= DPIO_ENABLE_CALIBRATION;
4690         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4691
4692         /* Set HBR and RBR LPF coefficients */
4693         if (crtc->config.port_clock == 162000 ||
4694             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4695             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4696                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4697                                  0x009f0003);
4698         else
4699                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4700                                  0x00d0000f);
4701
4702         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4703             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4704                 /* Use SSC source */
4705                 if (!pipe)
4706                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4707                                          0x0df40000);
4708                 else
4709                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4710                                          0x0df70000);
4711         } else { /* HDMI or VGA */
4712                 /* Use bend source */
4713                 if (!pipe)
4714                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4715                                          0x0df70000);
4716                 else
4717                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4718                                          0x0df40000);
4719         }
4720
4721         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4722         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4723         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4724             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4725                 coreclk |= 0x01000000;
4726         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4727
4728         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4729
4730         /* Enable DPIO clock input */
4731         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4732                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4733         /* We should never disable this, set it here for state tracking */
4734         if (pipe == PIPE_B)
4735                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4736         dpll |= DPLL_VCO_ENABLE;
4737         crtc->config.dpll_hw_state.dpll = dpll;
4738
4739         dpll_md = (crtc->config.pixel_multiplier - 1)
4740                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4741         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4742
4743         if (crtc->config.has_dp_encoder)
4744                 intel_dp_set_m_n(crtc);
4745
4746         mutex_unlock(&dev_priv->dpio_lock);
4747 }
4748
4749 static void i9xx_update_pll(struct intel_crtc *crtc,
4750                             intel_clock_t *reduced_clock,
4751                             int num_connectors)
4752 {
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         u32 dpll;
4756         bool is_sdvo;
4757         struct dpll *clock = &crtc->config.dpll;
4758
4759         i9xx_update_pll_dividers(crtc, reduced_clock);
4760
4761         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4762                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4763
4764         dpll = DPLL_VGA_MODE_DIS;
4765
4766         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4767                 dpll |= DPLLB_MODE_LVDS;
4768         else
4769                 dpll |= DPLLB_MODE_DAC_SERIAL;
4770
4771         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4772                 dpll |= (crtc->config.pixel_multiplier - 1)
4773                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4774         }
4775
4776         if (is_sdvo)
4777                 dpll |= DPLL_SDVO_HIGH_SPEED;
4778
4779         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4780                 dpll |= DPLL_SDVO_HIGH_SPEED;
4781
4782         /* compute bitmask from p1 value */
4783         if (IS_PINEVIEW(dev))
4784                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4785         else {
4786                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4787                 if (IS_G4X(dev) && reduced_clock)
4788                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4789         }
4790         switch (clock->p2) {
4791         case 5:
4792                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4793                 break;
4794         case 7:
4795                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4796                 break;
4797         case 10:
4798                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4799                 break;
4800         case 14:
4801                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4802                 break;
4803         }
4804         if (INTEL_INFO(dev)->gen >= 4)
4805                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4806
4807         if (crtc->config.sdvo_tv_clock)
4808                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4809         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4810                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4811                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4812         else
4813                 dpll |= PLL_REF_INPUT_DREFCLK;
4814
4815         dpll |= DPLL_VCO_ENABLE;
4816         crtc->config.dpll_hw_state.dpll = dpll;
4817
4818         if (INTEL_INFO(dev)->gen >= 4) {
4819                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4820                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4821                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4822         }
4823
4824         if (crtc->config.has_dp_encoder)
4825                 intel_dp_set_m_n(crtc);
4826 }
4827
4828 static void i8xx_update_pll(struct intel_crtc *crtc,
4829                             intel_clock_t *reduced_clock,
4830                             int num_connectors)
4831 {
4832         struct drm_device *dev = crtc->base.dev;
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834         u32 dpll;
4835         struct dpll *clock = &crtc->config.dpll;
4836
4837         i9xx_update_pll_dividers(crtc, reduced_clock);
4838
4839         dpll = DPLL_VGA_MODE_DIS;
4840
4841         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4842                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4843         } else {
4844                 if (clock->p1 == 2)
4845                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4846                 else
4847                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4848                 if (clock->p2 == 4)
4849                         dpll |= PLL_P2_DIVIDE_BY_4;
4850         }
4851
4852         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4853                 dpll |= DPLL_DVO_2X_MODE;
4854
4855         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4856                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4857                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4858         else
4859                 dpll |= PLL_REF_INPUT_DREFCLK;
4860
4861         dpll |= DPLL_VCO_ENABLE;
4862         crtc->config.dpll_hw_state.dpll = dpll;
4863 }
4864
4865 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4866 {
4867         struct drm_device *dev = intel_crtc->base.dev;
4868         struct drm_i915_private *dev_priv = dev->dev_private;
4869         enum pipe pipe = intel_crtc->pipe;
4870         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4871         struct drm_display_mode *adjusted_mode =
4872                 &intel_crtc->config.adjusted_mode;
4873         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4874
4875         /* We need to be careful not to changed the adjusted mode, for otherwise
4876          * the hw state checker will get angry at the mismatch. */
4877         crtc_vtotal = adjusted_mode->crtc_vtotal;
4878         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4879
4880         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4881                 /* the chip adds 2 halflines automatically */
4882                 crtc_vtotal -= 1;
4883                 crtc_vblank_end -= 1;
4884                 vsyncshift = adjusted_mode->crtc_hsync_start
4885                              - adjusted_mode->crtc_htotal / 2;
4886         } else {
4887                 vsyncshift = 0;
4888         }
4889
4890         if (INTEL_INFO(dev)->gen > 3)
4891                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4892
4893         I915_WRITE(HTOTAL(cpu_transcoder),
4894                    (adjusted_mode->crtc_hdisplay - 1) |
4895                    ((adjusted_mode->crtc_htotal - 1) << 16));
4896         I915_WRITE(HBLANK(cpu_transcoder),
4897                    (adjusted_mode->crtc_hblank_start - 1) |
4898                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4899         I915_WRITE(HSYNC(cpu_transcoder),
4900                    (adjusted_mode->crtc_hsync_start - 1) |
4901                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4902
4903         I915_WRITE(VTOTAL(cpu_transcoder),
4904                    (adjusted_mode->crtc_vdisplay - 1) |
4905                    ((crtc_vtotal - 1) << 16));
4906         I915_WRITE(VBLANK(cpu_transcoder),
4907                    (adjusted_mode->crtc_vblank_start - 1) |
4908                    ((crtc_vblank_end - 1) << 16));
4909         I915_WRITE(VSYNC(cpu_transcoder),
4910                    (adjusted_mode->crtc_vsync_start - 1) |
4911                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4912
4913         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4914          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4915          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4916          * bits. */
4917         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4918             (pipe == PIPE_B || pipe == PIPE_C))
4919                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4920
4921         /* pipesrc controls the size that is scaled from, which should
4922          * always be the user's requested size.
4923          */
4924         I915_WRITE(PIPESRC(pipe),
4925                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4926                    (intel_crtc->config.pipe_src_h - 1));
4927 }
4928
4929 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4930                                    struct intel_crtc_config *pipe_config)
4931 {
4932         struct drm_device *dev = crtc->base.dev;
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4935         uint32_t tmp;
4936
4937         tmp = I915_READ(HTOTAL(cpu_transcoder));
4938         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4939         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4940         tmp = I915_READ(HBLANK(cpu_transcoder));
4941         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4942         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4943         tmp = I915_READ(HSYNC(cpu_transcoder));
4944         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4945         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4946
4947         tmp = I915_READ(VTOTAL(cpu_transcoder));
4948         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4949         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4950         tmp = I915_READ(VBLANK(cpu_transcoder));
4951         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4952         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4953         tmp = I915_READ(VSYNC(cpu_transcoder));
4954         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4955         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4956
4957         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4958                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4959                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4960                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4961         }
4962
4963         tmp = I915_READ(PIPESRC(crtc->pipe));
4964         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4965         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4966
4967         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4968         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4969 }
4970
4971 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4972                                              struct intel_crtc_config *pipe_config)
4973 {
4974         struct drm_crtc *crtc = &intel_crtc->base;
4975
4976         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4977         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4978         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4979         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4980
4981         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4982         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4983         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4984         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4985
4986         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4987
4988         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4989         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4990 }
4991
4992 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4993 {
4994         struct drm_device *dev = intel_crtc->base.dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         uint32_t pipeconf;
4997
4998         pipeconf = 0;
4999
5000         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5001             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5002                 pipeconf |= PIPECONF_ENABLE;
5003
5004         if (intel_crtc->config.double_wide)
5005                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5006
5007         /* only g4x and later have fancy bpc/dither controls */
5008         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5009                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5010                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5011                         pipeconf |= PIPECONF_DITHER_EN |
5012                                     PIPECONF_DITHER_TYPE_SP;
5013
5014                 switch (intel_crtc->config.pipe_bpp) {
5015                 case 18:
5016                         pipeconf |= PIPECONF_6BPC;
5017                         break;
5018                 case 24:
5019                         pipeconf |= PIPECONF_8BPC;
5020                         break;
5021                 case 30:
5022                         pipeconf |= PIPECONF_10BPC;
5023                         break;
5024                 default:
5025                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5026                         BUG();
5027                 }
5028         }
5029
5030         if (HAS_PIPE_CXSR(dev)) {
5031                 if (intel_crtc->lowfreq_avail) {
5032                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5033                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5034                 } else {
5035                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5036                 }
5037         }
5038
5039         if (!IS_GEN2(dev) &&
5040             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5041                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5042         else
5043                 pipeconf |= PIPECONF_PROGRESSIVE;
5044
5045         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5046                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5047
5048         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5049         POSTING_READ(PIPECONF(intel_crtc->pipe));
5050 }
5051
5052 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5053                               int x, int y,
5054                               struct drm_framebuffer *fb)
5055 {
5056         struct drm_device *dev = crtc->dev;
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059         int pipe = intel_crtc->pipe;
5060         int plane = intel_crtc->plane;
5061         int refclk, num_connectors = 0;
5062         intel_clock_t clock, reduced_clock;
5063         u32 dspcntr;
5064         bool ok, has_reduced_clock = false;
5065         bool is_lvds = false, is_dsi = false;
5066         struct intel_encoder *encoder;
5067         const intel_limit_t *limit;
5068         int ret;
5069
5070         for_each_encoder_on_crtc(dev, crtc, encoder) {
5071                 switch (encoder->type) {
5072                 case INTEL_OUTPUT_LVDS:
5073                         is_lvds = true;
5074                         break;
5075                 case INTEL_OUTPUT_DSI:
5076                         is_dsi = true;
5077                         break;
5078                 }
5079
5080                 num_connectors++;
5081         }
5082
5083         if (is_dsi)
5084                 goto skip_dpll;
5085
5086         if (!intel_crtc->config.clock_set) {
5087                 refclk = i9xx_get_refclk(crtc, num_connectors);
5088
5089                 /*
5090                  * Returns a set of divisors for the desired target clock with
5091                  * the given refclk, or FALSE.  The returned values represent
5092                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5093                  * 2) / p1 / p2.
5094                  */
5095                 limit = intel_limit(crtc, refclk);
5096                 ok = dev_priv->display.find_dpll(limit, crtc,
5097                                                  intel_crtc->config.port_clock,
5098                                                  refclk, NULL, &clock);
5099                 if (!ok) {
5100                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5101                         return -EINVAL;
5102                 }
5103
5104                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5105                         /*
5106                          * Ensure we match the reduced clock's P to the target
5107                          * clock.  If the clocks don't match, we can't switch
5108                          * the display clock by using the FP0/FP1. In such case
5109                          * we will disable the LVDS downclock feature.
5110                          */
5111                         has_reduced_clock =
5112                                 dev_priv->display.find_dpll(limit, crtc,
5113                                                             dev_priv->lvds_downclock,
5114                                                             refclk, &clock,
5115                                                             &reduced_clock);
5116                 }
5117                 /* Compat-code for transition, will disappear. */
5118                 intel_crtc->config.dpll.n = clock.n;
5119                 intel_crtc->config.dpll.m1 = clock.m1;
5120                 intel_crtc->config.dpll.m2 = clock.m2;
5121                 intel_crtc->config.dpll.p1 = clock.p1;
5122                 intel_crtc->config.dpll.p2 = clock.p2;
5123         }
5124
5125         if (IS_GEN2(dev)) {
5126                 i8xx_update_pll(intel_crtc,
5127                                 has_reduced_clock ? &reduced_clock : NULL,
5128                                 num_connectors);
5129         } else if (IS_VALLEYVIEW(dev)) {
5130                 vlv_update_pll(intel_crtc);
5131         } else {
5132                 i9xx_update_pll(intel_crtc,
5133                                 has_reduced_clock ? &reduced_clock : NULL,
5134                                 num_connectors);
5135         }
5136
5137 skip_dpll:
5138         /* Set up the display plane register */
5139         dspcntr = DISPPLANE_GAMMA_ENABLE;
5140
5141         if (!IS_VALLEYVIEW(dev)) {
5142                 if (pipe == 0)
5143                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5144                 else
5145                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5146         }
5147
5148         intel_set_pipe_timings(intel_crtc);
5149
5150         /* pipesrc and dspsize control the size that is scaled from,
5151          * which should always be the user's requested size.
5152          */
5153         I915_WRITE(DSPSIZE(plane),
5154                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5155                    (intel_crtc->config.pipe_src_w - 1));
5156         I915_WRITE(DSPPOS(plane), 0);
5157
5158         i9xx_set_pipeconf(intel_crtc);
5159
5160         I915_WRITE(DSPCNTR(plane), dspcntr);
5161         POSTING_READ(DSPCNTR(plane));
5162
5163         ret = intel_pipe_set_base(crtc, x, y, fb);
5164
5165         return ret;
5166 }
5167
5168 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5169                                  struct intel_crtc_config *pipe_config)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         uint32_t tmp;
5174
5175         tmp = I915_READ(PFIT_CONTROL);
5176         if (!(tmp & PFIT_ENABLE))
5177                 return;
5178
5179         /* Check whether the pfit is attached to our pipe. */
5180         if (INTEL_INFO(dev)->gen < 4) {
5181                 if (crtc->pipe != PIPE_B)
5182                         return;
5183         } else {
5184                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5185                         return;
5186         }
5187
5188         pipe_config->gmch_pfit.control = tmp;
5189         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5190         if (INTEL_INFO(dev)->gen < 5)
5191                 pipe_config->gmch_pfit.lvds_border_bits =
5192                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5193 }
5194
5195 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5196                                struct intel_crtc_config *pipe_config)
5197 {
5198         struct drm_device *dev = crtc->base.dev;
5199         struct drm_i915_private *dev_priv = dev->dev_private;
5200         int pipe = pipe_config->cpu_transcoder;
5201         intel_clock_t clock;
5202         u32 mdiv;
5203         int refclk = 100000;
5204
5205         mutex_lock(&dev_priv->dpio_lock);
5206         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5207         mutex_unlock(&dev_priv->dpio_lock);
5208
5209         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5210         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5211         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5212         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5213         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5214
5215         vlv_clock(refclk, &clock);
5216
5217         /* clock.dot is the fast clock */
5218         pipe_config->port_clock = clock.dot / 5;
5219 }
5220
5221 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5222                                  struct intel_crtc_config *pipe_config)
5223 {
5224         struct drm_device *dev = crtc->base.dev;
5225         struct drm_i915_private *dev_priv = dev->dev_private;
5226         uint32_t tmp;
5227
5228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5229         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5230
5231         tmp = I915_READ(PIPECONF(crtc->pipe));
5232         if (!(tmp & PIPECONF_ENABLE))
5233                 return false;
5234
5235         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5236                 switch (tmp & PIPECONF_BPC_MASK) {
5237                 case PIPECONF_6BPC:
5238                         pipe_config->pipe_bpp = 18;
5239                         break;
5240                 case PIPECONF_8BPC:
5241                         pipe_config->pipe_bpp = 24;
5242                         break;
5243                 case PIPECONF_10BPC:
5244                         pipe_config->pipe_bpp = 30;
5245                         break;
5246                 default:
5247                         break;
5248                 }
5249         }
5250
5251         if (INTEL_INFO(dev)->gen < 4)
5252                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5253
5254         intel_get_pipe_timings(crtc, pipe_config);
5255
5256         i9xx_get_pfit_config(crtc, pipe_config);
5257
5258         if (INTEL_INFO(dev)->gen >= 4) {
5259                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5260                 pipe_config->pixel_multiplier =
5261                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5262                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5263                 pipe_config->dpll_hw_state.dpll_md = tmp;
5264         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5265                 tmp = I915_READ(DPLL(crtc->pipe));
5266                 pipe_config->pixel_multiplier =
5267                         ((tmp & SDVO_MULTIPLIER_MASK)
5268                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5269         } else {
5270                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5271                  * port and will be fixed up in the encoder->get_config
5272                  * function. */
5273                 pipe_config->pixel_multiplier = 1;
5274         }
5275         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5276         if (!IS_VALLEYVIEW(dev)) {
5277                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5278                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5279         } else {
5280                 /* Mask out read-only status bits. */
5281                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5282                                                      DPLL_PORTC_READY_MASK |
5283                                                      DPLL_PORTB_READY_MASK);
5284         }
5285
5286         if (IS_VALLEYVIEW(dev))
5287                 vlv_crtc_clock_get(crtc, pipe_config);
5288         else
5289                 i9xx_crtc_clock_get(crtc, pipe_config);
5290
5291         return true;
5292 }
5293
5294 static void ironlake_init_pch_refclk(struct drm_device *dev)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         struct drm_mode_config *mode_config = &dev->mode_config;
5298         struct intel_encoder *encoder;
5299         u32 val, final;
5300         bool has_lvds = false;
5301         bool has_cpu_edp = false;
5302         bool has_panel = false;
5303         bool has_ck505 = false;
5304         bool can_ssc = false;
5305
5306         /* We need to take the global config into account */
5307         list_for_each_entry(encoder, &mode_config->encoder_list,
5308                             base.head) {
5309                 switch (encoder->type) {
5310                 case INTEL_OUTPUT_LVDS:
5311                         has_panel = true;
5312                         has_lvds = true;
5313                         break;
5314                 case INTEL_OUTPUT_EDP:
5315                         has_panel = true;
5316                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5317                                 has_cpu_edp = true;
5318                         break;
5319                 }
5320         }
5321
5322         if (HAS_PCH_IBX(dev)) {
5323                 has_ck505 = dev_priv->vbt.display_clock_mode;
5324                 can_ssc = has_ck505;
5325         } else {
5326                 has_ck505 = false;
5327                 can_ssc = true;
5328         }
5329
5330         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5331                       has_panel, has_lvds, has_ck505);
5332
5333         /* Ironlake: try to setup display ref clock before DPLL
5334          * enabling. This is only under driver's control after
5335          * PCH B stepping, previous chipset stepping should be
5336          * ignoring this setting.
5337          */
5338         val = I915_READ(PCH_DREF_CONTROL);
5339
5340         /* As we must carefully and slowly disable/enable each source in turn,
5341          * compute the final state we want first and check if we need to
5342          * make any changes at all.
5343          */
5344         final = val;
5345         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5346         if (has_ck505)
5347                 final |= DREF_NONSPREAD_CK505_ENABLE;
5348         else
5349                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5350
5351         final &= ~DREF_SSC_SOURCE_MASK;
5352         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5353         final &= ~DREF_SSC1_ENABLE;
5354
5355         if (has_panel) {
5356                 final |= DREF_SSC_SOURCE_ENABLE;
5357
5358                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5359                         final |= DREF_SSC1_ENABLE;
5360
5361                 if (has_cpu_edp) {
5362                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5363                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5364                         else
5365                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5366                 } else
5367                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5368         } else {
5369                 final |= DREF_SSC_SOURCE_DISABLE;
5370                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5371         }
5372
5373         if (final == val)
5374                 return;
5375
5376         /* Always enable nonspread source */
5377         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5378
5379         if (has_ck505)
5380                 val |= DREF_NONSPREAD_CK505_ENABLE;
5381         else
5382                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5383
5384         if (has_panel) {
5385                 val &= ~DREF_SSC_SOURCE_MASK;
5386                 val |= DREF_SSC_SOURCE_ENABLE;
5387
5388                 /* SSC must be turned on before enabling the CPU output  */
5389                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5390                         DRM_DEBUG_KMS("Using SSC on panel\n");
5391                         val |= DREF_SSC1_ENABLE;
5392                 } else
5393                         val &= ~DREF_SSC1_ENABLE;
5394
5395                 /* Get SSC going before enabling the outputs */
5396                 I915_WRITE(PCH_DREF_CONTROL, val);
5397                 POSTING_READ(PCH_DREF_CONTROL);
5398                 udelay(200);
5399
5400                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5401
5402                 /* Enable CPU source on CPU attached eDP */
5403                 if (has_cpu_edp) {
5404                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5405                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5406                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5407                         }
5408                         else
5409                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5410                 } else
5411                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5412
5413                 I915_WRITE(PCH_DREF_CONTROL, val);
5414                 POSTING_READ(PCH_DREF_CONTROL);
5415                 udelay(200);
5416         } else {
5417                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5418
5419                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5420
5421                 /* Turn off CPU output */
5422                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5423
5424                 I915_WRITE(PCH_DREF_CONTROL, val);
5425                 POSTING_READ(PCH_DREF_CONTROL);
5426                 udelay(200);
5427
5428                 /* Turn off the SSC source */
5429                 val &= ~DREF_SSC_SOURCE_MASK;
5430                 val |= DREF_SSC_SOURCE_DISABLE;
5431
5432                 /* Turn off SSC1 */
5433                 val &= ~DREF_SSC1_ENABLE;
5434
5435                 I915_WRITE(PCH_DREF_CONTROL, val);
5436                 POSTING_READ(PCH_DREF_CONTROL);
5437                 udelay(200);
5438         }
5439
5440         BUG_ON(val != final);
5441 }
5442
5443 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5444 {
5445         uint32_t tmp;
5446
5447         tmp = I915_READ(SOUTH_CHICKEN2);
5448         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5449         I915_WRITE(SOUTH_CHICKEN2, tmp);
5450
5451         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5452                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5453                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5454
5455         tmp = I915_READ(SOUTH_CHICKEN2);
5456         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5457         I915_WRITE(SOUTH_CHICKEN2, tmp);
5458
5459         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5460                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5461                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5462 }
5463
5464 /* WaMPhyProgramming:hsw */
5465 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5466 {
5467         uint32_t tmp;
5468
5469         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5470         tmp &= ~(0xFF << 24);
5471         tmp |= (0x12 << 24);
5472         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5473
5474         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5475         tmp |= (1 << 11);
5476         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5477
5478         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5479         tmp |= (1 << 11);
5480         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5481
5482         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5483         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5484         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5485
5486         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5487         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5488         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5489
5490         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5491         tmp &= ~(7 << 13);
5492         tmp |= (5 << 13);
5493         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5494
5495         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5496         tmp &= ~(7 << 13);
5497         tmp |= (5 << 13);
5498         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5499
5500         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5501         tmp &= ~0xFF;
5502         tmp |= 0x1C;
5503         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5504
5505         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5506         tmp &= ~0xFF;
5507         tmp |= 0x1C;
5508         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5509
5510         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5511         tmp &= ~(0xFF << 16);
5512         tmp |= (0x1C << 16);
5513         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5514
5515         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5516         tmp &= ~(0xFF << 16);
5517         tmp |= (0x1C << 16);
5518         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5519
5520         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5521         tmp |= (1 << 27);
5522         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5523
5524         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5525         tmp |= (1 << 27);
5526         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5527
5528         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5529         tmp &= ~(0xF << 28);
5530         tmp |= (4 << 28);
5531         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5532
5533         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5534         tmp &= ~(0xF << 28);
5535         tmp |= (4 << 28);
5536         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5537 }
5538
5539 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5540  * Programming" based on the parameters passed:
5541  * - Sequence to enable CLKOUT_DP
5542  * - Sequence to enable CLKOUT_DP without spread
5543  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5544  */
5545 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5546                                  bool with_fdi)
5547 {
5548         struct drm_i915_private *dev_priv = dev->dev_private;
5549         uint32_t reg, tmp;
5550
5551         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5552                 with_spread = true;
5553         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5554                  with_fdi, "LP PCH doesn't have FDI\n"))
5555                 with_fdi = false;
5556
5557         mutex_lock(&dev_priv->dpio_lock);
5558
5559         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5560         tmp &= ~SBI_SSCCTL_DISABLE;
5561         tmp |= SBI_SSCCTL_PATHALT;
5562         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5563
5564         udelay(24);
5565
5566         if (with_spread) {
5567                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5568                 tmp &= ~SBI_SSCCTL_PATHALT;
5569                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5570
5571                 if (with_fdi) {
5572                         lpt_reset_fdi_mphy(dev_priv);
5573                         lpt_program_fdi_mphy(dev_priv);
5574                 }
5575         }
5576
5577         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5578                SBI_GEN0 : SBI_DBUFF0;
5579         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5580         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5581         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5582
5583         mutex_unlock(&dev_priv->dpio_lock);
5584 }
5585
5586 /* Sequence to disable CLKOUT_DP */
5587 static void lpt_disable_clkout_dp(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590         uint32_t reg, tmp;
5591
5592         mutex_lock(&dev_priv->dpio_lock);
5593
5594         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5595                SBI_GEN0 : SBI_DBUFF0;
5596         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5597         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5598         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5599
5600         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5601         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5602                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5603                         tmp |= SBI_SSCCTL_PATHALT;
5604                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605                         udelay(32);
5606                 }
5607                 tmp |= SBI_SSCCTL_DISABLE;
5608                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5609         }
5610
5611         mutex_unlock(&dev_priv->dpio_lock);
5612 }
5613
5614 static void lpt_init_pch_refclk(struct drm_device *dev)
5615 {
5616         struct drm_mode_config *mode_config = &dev->mode_config;
5617         struct intel_encoder *encoder;
5618         bool has_vga = false;
5619
5620         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5621                 switch (encoder->type) {
5622                 case INTEL_OUTPUT_ANALOG:
5623                         has_vga = true;
5624                         break;
5625                 }
5626         }
5627
5628         if (has_vga)
5629                 lpt_enable_clkout_dp(dev, true, true);
5630         else
5631                 lpt_disable_clkout_dp(dev);
5632 }
5633
5634 /*
5635  * Initialize reference clocks when the driver loads
5636  */
5637 void intel_init_pch_refclk(struct drm_device *dev)
5638 {
5639         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5640                 ironlake_init_pch_refclk(dev);
5641         else if (HAS_PCH_LPT(dev))
5642                 lpt_init_pch_refclk(dev);
5643 }
5644
5645 static int ironlake_get_refclk(struct drm_crtc *crtc)
5646 {
5647         struct drm_device *dev = crtc->dev;
5648         struct drm_i915_private *dev_priv = dev->dev_private;
5649         struct intel_encoder *encoder;
5650         int num_connectors = 0;
5651         bool is_lvds = false;
5652
5653         for_each_encoder_on_crtc(dev, crtc, encoder) {
5654                 switch (encoder->type) {
5655                 case INTEL_OUTPUT_LVDS:
5656                         is_lvds = true;
5657                         break;
5658                 }
5659                 num_connectors++;
5660         }
5661
5662         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5663                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5664                               dev_priv->vbt.lvds_ssc_freq);
5665                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5666         }
5667
5668         return 120000;
5669 }
5670
5671 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5672 {
5673         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5675         int pipe = intel_crtc->pipe;
5676         uint32_t val;
5677
5678         val = 0;
5679
5680         switch (intel_crtc->config.pipe_bpp) {
5681         case 18:
5682                 val |= PIPECONF_6BPC;
5683                 break;
5684         case 24:
5685                 val |= PIPECONF_8BPC;
5686                 break;
5687         case 30:
5688                 val |= PIPECONF_10BPC;
5689                 break;
5690         case 36:
5691                 val |= PIPECONF_12BPC;
5692                 break;
5693         default:
5694                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5695                 BUG();
5696         }
5697
5698         if (intel_crtc->config.dither)
5699                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5700
5701         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5702                 val |= PIPECONF_INTERLACED_ILK;
5703         else
5704                 val |= PIPECONF_PROGRESSIVE;
5705
5706         if (intel_crtc->config.limited_color_range)
5707                 val |= PIPECONF_COLOR_RANGE_SELECT;
5708
5709         I915_WRITE(PIPECONF(pipe), val);
5710         POSTING_READ(PIPECONF(pipe));
5711 }
5712
5713 /*
5714  * Set up the pipe CSC unit.
5715  *
5716  * Currently only full range RGB to limited range RGB conversion
5717  * is supported, but eventually this should handle various
5718  * RGB<->YCbCr scenarios as well.
5719  */
5720 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5721 {
5722         struct drm_device *dev = crtc->dev;
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725         int pipe = intel_crtc->pipe;
5726         uint16_t coeff = 0x7800; /* 1.0 */
5727
5728         /*
5729          * TODO: Check what kind of values actually come out of the pipe
5730          * with these coeff/postoff values and adjust to get the best
5731          * accuracy. Perhaps we even need to take the bpc value into
5732          * consideration.
5733          */
5734
5735         if (intel_crtc->config.limited_color_range)
5736                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5737
5738         /*
5739          * GY/GU and RY/RU should be the other way around according
5740          * to BSpec, but reality doesn't agree. Just set them up in
5741          * a way that results in the correct picture.
5742          */
5743         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5744         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5745
5746         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5747         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5748
5749         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5750         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5751
5752         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5753         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5754         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5755
5756         if (INTEL_INFO(dev)->gen > 6) {
5757                 uint16_t postoff = 0;
5758
5759                 if (intel_crtc->config.limited_color_range)
5760                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5761
5762                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5763                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5764                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5765
5766                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5767         } else {
5768                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5769
5770                 if (intel_crtc->config.limited_color_range)
5771                         mode |= CSC_BLACK_SCREEN_OFFSET;
5772
5773                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5774         }
5775 }
5776
5777 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5778 {
5779         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5781         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5782         uint32_t val;
5783
5784         val = 0;
5785
5786         if (intel_crtc->config.dither)
5787                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5788
5789         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5790                 val |= PIPECONF_INTERLACED_ILK;
5791         else
5792                 val |= PIPECONF_PROGRESSIVE;
5793
5794         I915_WRITE(PIPECONF(cpu_transcoder), val);
5795         POSTING_READ(PIPECONF(cpu_transcoder));
5796
5797         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5798         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5799 }
5800
5801 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5802                                     intel_clock_t *clock,
5803                                     bool *has_reduced_clock,
5804                                     intel_clock_t *reduced_clock)
5805 {
5806         struct drm_device *dev = crtc->dev;
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         struct intel_encoder *intel_encoder;
5809         int refclk;
5810         const intel_limit_t *limit;
5811         bool ret, is_lvds = false;
5812
5813         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5814                 switch (intel_encoder->type) {
5815                 case INTEL_OUTPUT_LVDS:
5816                         is_lvds = true;
5817                         break;
5818                 }
5819         }
5820
5821         refclk = ironlake_get_refclk(crtc);
5822
5823         /*
5824          * Returns a set of divisors for the desired target clock with the given
5825          * refclk, or FALSE.  The returned values represent the clock equation:
5826          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5827          */
5828         limit = intel_limit(crtc, refclk);
5829         ret = dev_priv->display.find_dpll(limit, crtc,
5830                                           to_intel_crtc(crtc)->config.port_clock,
5831                                           refclk, NULL, clock);
5832         if (!ret)
5833                 return false;
5834
5835         if (is_lvds && dev_priv->lvds_downclock_avail) {
5836                 /*
5837                  * Ensure we match the reduced clock's P to the target clock.
5838                  * If the clocks don't match, we can't switch the display clock
5839                  * by using the FP0/FP1. In such case we will disable the LVDS
5840                  * downclock feature.
5841                 */
5842                 *has_reduced_clock =
5843                         dev_priv->display.find_dpll(limit, crtc,
5844                                                     dev_priv->lvds_downclock,
5845                                                     refclk, clock,
5846                                                     reduced_clock);
5847         }
5848
5849         return true;
5850 }
5851
5852 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5853 {
5854         struct drm_i915_private *dev_priv = dev->dev_private;
5855         uint32_t temp;
5856
5857         temp = I915_READ(SOUTH_CHICKEN1);
5858         if (temp & FDI_BC_BIFURCATION_SELECT)
5859                 return;
5860
5861         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5862         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5863
5864         temp |= FDI_BC_BIFURCATION_SELECT;
5865         DRM_DEBUG_KMS("enabling fdi C rx\n");
5866         I915_WRITE(SOUTH_CHICKEN1, temp);
5867         POSTING_READ(SOUTH_CHICKEN1);
5868 }
5869
5870 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5871 {
5872         struct drm_device *dev = intel_crtc->base.dev;
5873         struct drm_i915_private *dev_priv = dev->dev_private;
5874
5875         switch (intel_crtc->pipe) {
5876         case PIPE_A:
5877                 break;
5878         case PIPE_B:
5879                 if (intel_crtc->config.fdi_lanes > 2)
5880                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5881                 else
5882                         cpt_enable_fdi_bc_bifurcation(dev);
5883
5884                 break;
5885         case PIPE_C:
5886                 cpt_enable_fdi_bc_bifurcation(dev);
5887
5888                 break;
5889         default:
5890                 BUG();
5891         }
5892 }
5893
5894 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5895 {
5896         /*
5897          * Account for spread spectrum to avoid
5898          * oversubscribing the link. Max center spread
5899          * is 2.5%; use 5% for safety's sake.
5900          */
5901         u32 bps = target_clock * bpp * 21 / 20;
5902         return bps / (link_bw * 8) + 1;
5903 }
5904
5905 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5906 {
5907         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5908 }
5909
5910 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5911                                       u32 *fp,
5912                                       intel_clock_t *reduced_clock, u32 *fp2)
5913 {
5914         struct drm_crtc *crtc = &intel_crtc->base;
5915         struct drm_device *dev = crtc->dev;
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917         struct intel_encoder *intel_encoder;
5918         uint32_t dpll;
5919         int factor, num_connectors = 0;
5920         bool is_lvds = false, is_sdvo = false;
5921
5922         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5923                 switch (intel_encoder->type) {
5924                 case INTEL_OUTPUT_LVDS:
5925                         is_lvds = true;
5926                         break;
5927                 case INTEL_OUTPUT_SDVO:
5928                 case INTEL_OUTPUT_HDMI:
5929                         is_sdvo = true;
5930                         break;
5931                 }
5932
5933                 num_connectors++;
5934         }
5935
5936         /* Enable autotuning of the PLL clock (if permissible) */
5937         factor = 21;
5938         if (is_lvds) {
5939                 if ((intel_panel_use_ssc(dev_priv) &&
5940                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5941                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5942                         factor = 25;
5943         } else if (intel_crtc->config.sdvo_tv_clock)
5944                 factor = 20;
5945
5946         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5947                 *fp |= FP_CB_TUNE;
5948
5949         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5950                 *fp2 |= FP_CB_TUNE;
5951
5952         dpll = 0;
5953
5954         if (is_lvds)
5955                 dpll |= DPLLB_MODE_LVDS;
5956         else
5957                 dpll |= DPLLB_MODE_DAC_SERIAL;
5958
5959         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5960                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5961
5962         if (is_sdvo)
5963                 dpll |= DPLL_SDVO_HIGH_SPEED;
5964         if (intel_crtc->config.has_dp_encoder)
5965                 dpll |= DPLL_SDVO_HIGH_SPEED;
5966
5967         /* compute bitmask from p1 value */
5968         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5969         /* also FPA1 */
5970         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5971
5972         switch (intel_crtc->config.dpll.p2) {
5973         case 5:
5974                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5975                 break;
5976         case 7:
5977                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5978                 break;
5979         case 10:
5980                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5981                 break;
5982         case 14:
5983                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5984                 break;
5985         }
5986
5987         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5988                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5989         else
5990                 dpll |= PLL_REF_INPUT_DREFCLK;
5991
5992         return dpll | DPLL_VCO_ENABLE;
5993 }
5994
5995 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5996                                   int x, int y,
5997                                   struct drm_framebuffer *fb)
5998 {
5999         struct drm_device *dev = crtc->dev;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002         int pipe = intel_crtc->pipe;
6003         int plane = intel_crtc->plane;
6004         int num_connectors = 0;
6005         intel_clock_t clock, reduced_clock;
6006         u32 dpll = 0, fp = 0, fp2 = 0;
6007         bool ok, has_reduced_clock = false;
6008         bool is_lvds = false;
6009         struct intel_encoder *encoder;
6010         struct intel_shared_dpll *pll;
6011         int ret;
6012
6013         for_each_encoder_on_crtc(dev, crtc, encoder) {
6014                 switch (encoder->type) {
6015                 case INTEL_OUTPUT_LVDS:
6016                         is_lvds = true;
6017                         break;
6018                 }
6019
6020                 num_connectors++;
6021         }
6022
6023         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6024              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6025
6026         ok = ironlake_compute_clocks(crtc, &clock,
6027                                      &has_reduced_clock, &reduced_clock);
6028         if (!ok && !intel_crtc->config.clock_set) {
6029                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6030                 return -EINVAL;
6031         }
6032         /* Compat-code for transition, will disappear. */
6033         if (!intel_crtc->config.clock_set) {
6034                 intel_crtc->config.dpll.n = clock.n;
6035                 intel_crtc->config.dpll.m1 = clock.m1;
6036                 intel_crtc->config.dpll.m2 = clock.m2;
6037                 intel_crtc->config.dpll.p1 = clock.p1;
6038                 intel_crtc->config.dpll.p2 = clock.p2;
6039         }
6040
6041         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6042         if (intel_crtc->config.has_pch_encoder) {
6043                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6044                 if (has_reduced_clock)
6045                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6046
6047                 dpll = ironlake_compute_dpll(intel_crtc,
6048                                              &fp, &reduced_clock,
6049                                              has_reduced_clock ? &fp2 : NULL);
6050
6051                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6052                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6053                 if (has_reduced_clock)
6054                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6055                 else
6056                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6057
6058                 pll = intel_get_shared_dpll(intel_crtc);
6059                 if (pll == NULL) {
6060                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6061                                          pipe_name(pipe));
6062                         return -EINVAL;
6063                 }
6064         } else
6065                 intel_put_shared_dpll(intel_crtc);
6066
6067         if (intel_crtc->config.has_dp_encoder)
6068                 intel_dp_set_m_n(intel_crtc);
6069
6070         if (is_lvds && has_reduced_clock && i915_powersave)
6071                 intel_crtc->lowfreq_avail = true;
6072         else
6073                 intel_crtc->lowfreq_avail = false;
6074
6075         if (intel_crtc->config.has_pch_encoder) {
6076                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6077
6078         }
6079
6080         intel_set_pipe_timings(intel_crtc);
6081
6082         if (intel_crtc->config.has_pch_encoder) {
6083                 intel_cpu_transcoder_set_m_n(intel_crtc,
6084                                              &intel_crtc->config.fdi_m_n);
6085         }
6086
6087         if (IS_IVYBRIDGE(dev))
6088                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6089
6090         ironlake_set_pipeconf(crtc);
6091
6092         /* Set up the display plane register */
6093         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6094         POSTING_READ(DSPCNTR(plane));
6095
6096         ret = intel_pipe_set_base(crtc, x, y, fb);
6097
6098         return ret;
6099 }
6100
6101 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6102                                          struct intel_link_m_n *m_n)
6103 {
6104         struct drm_device *dev = crtc->base.dev;
6105         struct drm_i915_private *dev_priv = dev->dev_private;
6106         enum pipe pipe = crtc->pipe;
6107
6108         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6109         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6110         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6111                 & ~TU_SIZE_MASK;
6112         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6113         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6114                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6115 }
6116
6117 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6118                                          enum transcoder transcoder,
6119                                          struct intel_link_m_n *m_n)
6120 {
6121         struct drm_device *dev = crtc->base.dev;
6122         struct drm_i915_private *dev_priv = dev->dev_private;
6123         enum pipe pipe = crtc->pipe;
6124
6125         if (INTEL_INFO(dev)->gen >= 5) {
6126                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6127                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6128                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6129                         & ~TU_SIZE_MASK;
6130                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6131                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6132                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6133         } else {
6134                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6135                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6136                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6137                         & ~TU_SIZE_MASK;
6138                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6139                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6140                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6141         }
6142 }
6143
6144 void intel_dp_get_m_n(struct intel_crtc *crtc,
6145                       struct intel_crtc_config *pipe_config)
6146 {
6147         if (crtc->config.has_pch_encoder)
6148                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6149         else
6150                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6151                                              &pipe_config->dp_m_n);
6152 }
6153
6154 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6155                                         struct intel_crtc_config *pipe_config)
6156 {
6157         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6158                                      &pipe_config->fdi_m_n);
6159 }
6160
6161 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6162                                      struct intel_crtc_config *pipe_config)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         uint32_t tmp;
6167
6168         tmp = I915_READ(PF_CTL(crtc->pipe));
6169
6170         if (tmp & PF_ENABLE) {
6171                 pipe_config->pch_pfit.enabled = true;
6172                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6173                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6174
6175                 /* We currently do not free assignements of panel fitters on
6176                  * ivb/hsw (since we don't use the higher upscaling modes which
6177                  * differentiates them) so just WARN about this case for now. */
6178                 if (IS_GEN7(dev)) {
6179                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6180                                 PF_PIPE_SEL_IVB(crtc->pipe));
6181                 }
6182         }
6183 }
6184
6185 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6186                                      struct intel_crtc_config *pipe_config)
6187 {
6188         struct drm_device *dev = crtc->base.dev;
6189         struct drm_i915_private *dev_priv = dev->dev_private;
6190         uint32_t tmp;
6191
6192         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6193         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6194
6195         tmp = I915_READ(PIPECONF(crtc->pipe));
6196         if (!(tmp & PIPECONF_ENABLE))
6197                 return false;
6198
6199         switch (tmp & PIPECONF_BPC_MASK) {
6200         case PIPECONF_6BPC:
6201                 pipe_config->pipe_bpp = 18;
6202                 break;
6203         case PIPECONF_8BPC:
6204                 pipe_config->pipe_bpp = 24;
6205                 break;
6206         case PIPECONF_10BPC:
6207                 pipe_config->pipe_bpp = 30;
6208                 break;
6209         case PIPECONF_12BPC:
6210                 pipe_config->pipe_bpp = 36;
6211                 break;
6212         default:
6213                 break;
6214         }
6215
6216         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6217                 struct intel_shared_dpll *pll;
6218
6219                 pipe_config->has_pch_encoder = true;
6220
6221                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6222                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6223                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6224
6225                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6226
6227                 if (HAS_PCH_IBX(dev_priv->dev)) {
6228                         pipe_config->shared_dpll =
6229                                 (enum intel_dpll_id) crtc->pipe;
6230                 } else {
6231                         tmp = I915_READ(PCH_DPLL_SEL);
6232                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6233                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6234                         else
6235                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6236                 }
6237
6238                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6239
6240                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6241                                            &pipe_config->dpll_hw_state));
6242
6243                 tmp = pipe_config->dpll_hw_state.dpll;
6244                 pipe_config->pixel_multiplier =
6245                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6246                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6247
6248                 ironlake_pch_clock_get(crtc, pipe_config);
6249         } else {
6250                 pipe_config->pixel_multiplier = 1;
6251         }
6252
6253         intel_get_pipe_timings(crtc, pipe_config);
6254
6255         ironlake_get_pfit_config(crtc, pipe_config);
6256
6257         return true;
6258 }
6259
6260 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6261 {
6262         struct drm_device *dev = dev_priv->dev;
6263         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6264         struct intel_crtc *crtc;
6265         unsigned long irqflags;
6266         uint32_t val;
6267
6268         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6269                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6270                      pipe_name(crtc->pipe));
6271
6272         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6273         WARN(plls->spll_refcount, "SPLL enabled\n");
6274         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6275         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6276         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6277         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6278              "CPU PWM1 enabled\n");
6279         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6280              "CPU PWM2 enabled\n");
6281         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6282              "PCH PWM1 enabled\n");
6283         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6284              "Utility pin enabled\n");
6285         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6286
6287         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6288         val = I915_READ(DEIMR);
6289         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6290              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6291         val = I915_READ(SDEIMR);
6292         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6293              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6294         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6295 }
6296
6297 /*
6298  * This function implements pieces of two sequences from BSpec:
6299  * - Sequence for display software to disable LCPLL
6300  * - Sequence for display software to allow package C8+
6301  * The steps implemented here are just the steps that actually touch the LCPLL
6302  * register. Callers should take care of disabling all the display engine
6303  * functions, doing the mode unset, fixing interrupts, etc.
6304  */
6305 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6306                               bool switch_to_fclk, bool allow_power_down)
6307 {
6308         uint32_t val;
6309
6310         assert_can_disable_lcpll(dev_priv);
6311
6312         val = I915_READ(LCPLL_CTL);
6313
6314         if (switch_to_fclk) {
6315                 val |= LCPLL_CD_SOURCE_FCLK;
6316                 I915_WRITE(LCPLL_CTL, val);
6317
6318                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6319                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6320                         DRM_ERROR("Switching to FCLK failed\n");
6321
6322                 val = I915_READ(LCPLL_CTL);
6323         }
6324
6325         val |= LCPLL_PLL_DISABLE;
6326         I915_WRITE(LCPLL_CTL, val);
6327         POSTING_READ(LCPLL_CTL);
6328
6329         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6330                 DRM_ERROR("LCPLL still locked\n");
6331
6332         val = I915_READ(D_COMP);
6333         val |= D_COMP_COMP_DISABLE;
6334         mutex_lock(&dev_priv->rps.hw_lock);
6335         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6336                 DRM_ERROR("Failed to disable D_COMP\n");
6337         mutex_unlock(&dev_priv->rps.hw_lock);
6338         POSTING_READ(D_COMP);
6339         ndelay(100);
6340
6341         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6342                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6343
6344         if (allow_power_down) {
6345                 val = I915_READ(LCPLL_CTL);
6346                 val |= LCPLL_POWER_DOWN_ALLOW;
6347                 I915_WRITE(LCPLL_CTL, val);
6348                 POSTING_READ(LCPLL_CTL);
6349         }
6350 }
6351
6352 /*
6353  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6354  * source.
6355  */
6356 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6357 {
6358         uint32_t val;
6359
6360         val = I915_READ(LCPLL_CTL);
6361
6362         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6363                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6364                 return;
6365
6366         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6367          * we'll hang the machine! */
6368         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6369
6370         if (val & LCPLL_POWER_DOWN_ALLOW) {
6371                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6372                 I915_WRITE(LCPLL_CTL, val);
6373                 POSTING_READ(LCPLL_CTL);
6374         }
6375
6376         val = I915_READ(D_COMP);
6377         val |= D_COMP_COMP_FORCE;
6378         val &= ~D_COMP_COMP_DISABLE;
6379         mutex_lock(&dev_priv->rps.hw_lock);
6380         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6381                 DRM_ERROR("Failed to enable D_COMP\n");
6382         mutex_unlock(&dev_priv->rps.hw_lock);
6383         POSTING_READ(D_COMP);
6384
6385         val = I915_READ(LCPLL_CTL);
6386         val &= ~LCPLL_PLL_DISABLE;
6387         I915_WRITE(LCPLL_CTL, val);
6388
6389         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6390                 DRM_ERROR("LCPLL not locked yet\n");
6391
6392         if (val & LCPLL_CD_SOURCE_FCLK) {
6393                 val = I915_READ(LCPLL_CTL);
6394                 val &= ~LCPLL_CD_SOURCE_FCLK;
6395                 I915_WRITE(LCPLL_CTL, val);
6396
6397                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6398                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6399                         DRM_ERROR("Switching back to LCPLL failed\n");
6400         }
6401
6402         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6403 }
6404
6405 void hsw_enable_pc8_work(struct work_struct *__work)
6406 {
6407         struct drm_i915_private *dev_priv =
6408                 container_of(to_delayed_work(__work), struct drm_i915_private,
6409                              pc8.enable_work);
6410         struct drm_device *dev = dev_priv->dev;
6411         uint32_t val;
6412
6413         if (dev_priv->pc8.enabled)
6414                 return;
6415
6416         DRM_DEBUG_KMS("Enabling package C8+\n");
6417
6418         dev_priv->pc8.enabled = true;
6419
6420         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6421                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6422                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6423                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6424         }
6425
6426         lpt_disable_clkout_dp(dev);
6427         hsw_pc8_disable_interrupts(dev);
6428         hsw_disable_lcpll(dev_priv, true, true);
6429 }
6430
6431 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6432 {
6433         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6434         WARN(dev_priv->pc8.disable_count < 1,
6435              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6436
6437         dev_priv->pc8.disable_count--;
6438         if (dev_priv->pc8.disable_count != 0)
6439                 return;
6440
6441         schedule_delayed_work(&dev_priv->pc8.enable_work,
6442                               msecs_to_jiffies(i915_pc8_timeout));
6443 }
6444
6445 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6446 {
6447         struct drm_device *dev = dev_priv->dev;
6448         uint32_t val;
6449
6450         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6451         WARN(dev_priv->pc8.disable_count < 0,
6452              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6453
6454         dev_priv->pc8.disable_count++;
6455         if (dev_priv->pc8.disable_count != 1)
6456                 return;
6457
6458         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6459         if (!dev_priv->pc8.enabled)
6460                 return;
6461
6462         DRM_DEBUG_KMS("Disabling package C8+\n");
6463
6464         hsw_restore_lcpll(dev_priv);
6465         hsw_pc8_restore_interrupts(dev);
6466         lpt_init_pch_refclk(dev);
6467
6468         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6469                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6470                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6471                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6472         }
6473
6474         intel_prepare_ddi(dev);
6475         i915_gem_init_swizzling(dev);
6476         mutex_lock(&dev_priv->rps.hw_lock);
6477         gen6_update_ring_freq(dev);
6478         mutex_unlock(&dev_priv->rps.hw_lock);
6479         dev_priv->pc8.enabled = false;
6480 }
6481
6482 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6483 {
6484         mutex_lock(&dev_priv->pc8.lock);
6485         __hsw_enable_package_c8(dev_priv);
6486         mutex_unlock(&dev_priv->pc8.lock);
6487 }
6488
6489 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6490 {
6491         mutex_lock(&dev_priv->pc8.lock);
6492         __hsw_disable_package_c8(dev_priv);
6493         mutex_unlock(&dev_priv->pc8.lock);
6494 }
6495
6496 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6497 {
6498         struct drm_device *dev = dev_priv->dev;
6499         struct intel_crtc *crtc;
6500         uint32_t val;
6501
6502         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6503                 if (crtc->base.enabled)
6504                         return false;
6505
6506         /* This case is still possible since we have the i915.disable_power_well
6507          * parameter and also the KVMr or something else might be requesting the
6508          * power well. */
6509         val = I915_READ(HSW_PWR_WELL_DRIVER);
6510         if (val != 0) {
6511                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6512                 return false;
6513         }
6514
6515         return true;
6516 }
6517
6518 /* Since we're called from modeset_global_resources there's no way to
6519  * symmetrically increase and decrease the refcount, so we use
6520  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6521  * or not.
6522  */
6523 static void hsw_update_package_c8(struct drm_device *dev)
6524 {
6525         struct drm_i915_private *dev_priv = dev->dev_private;
6526         bool allow;
6527
6528         if (!i915_enable_pc8)
6529                 return;
6530
6531         mutex_lock(&dev_priv->pc8.lock);
6532
6533         allow = hsw_can_enable_package_c8(dev_priv);
6534
6535         if (allow == dev_priv->pc8.requirements_met)
6536                 goto done;
6537
6538         dev_priv->pc8.requirements_met = allow;
6539
6540         if (allow)
6541                 __hsw_enable_package_c8(dev_priv);
6542         else
6543                 __hsw_disable_package_c8(dev_priv);
6544
6545 done:
6546         mutex_unlock(&dev_priv->pc8.lock);
6547 }
6548
6549 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6550 {
6551         if (!dev_priv->pc8.gpu_idle) {
6552                 dev_priv->pc8.gpu_idle = true;
6553                 hsw_enable_package_c8(dev_priv);
6554         }
6555 }
6556
6557 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6558 {
6559         if (dev_priv->pc8.gpu_idle) {
6560                 dev_priv->pc8.gpu_idle = false;
6561                 hsw_disable_package_c8(dev_priv);
6562         }
6563 }
6564
6565 static void haswell_modeset_global_resources(struct drm_device *dev)
6566 {
6567         bool enable = false;
6568         struct intel_crtc *crtc;
6569
6570         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6571                 if (!crtc->base.enabled)
6572                         continue;
6573
6574                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6575                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6576                         enable = true;
6577         }
6578
6579         intel_set_power_well(dev, enable);
6580
6581         hsw_update_package_c8(dev);
6582 }
6583
6584 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6585                                  int x, int y,
6586                                  struct drm_framebuffer *fb)
6587 {
6588         struct drm_device *dev = crtc->dev;
6589         struct drm_i915_private *dev_priv = dev->dev_private;
6590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591         int plane = intel_crtc->plane;
6592         int ret;
6593
6594         if (!intel_ddi_pll_mode_set(crtc))
6595                 return -EINVAL;
6596
6597         if (intel_crtc->config.has_dp_encoder)
6598                 intel_dp_set_m_n(intel_crtc);
6599
6600         intel_crtc->lowfreq_avail = false;
6601
6602         intel_set_pipe_timings(intel_crtc);
6603
6604         if (intel_crtc->config.has_pch_encoder) {
6605                 intel_cpu_transcoder_set_m_n(intel_crtc,
6606                                              &intel_crtc->config.fdi_m_n);
6607         }
6608
6609         haswell_set_pipeconf(crtc);
6610
6611         intel_set_pipe_csc(crtc);
6612
6613         /* Set up the display plane register */
6614         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6615         POSTING_READ(DSPCNTR(plane));
6616
6617         ret = intel_pipe_set_base(crtc, x, y, fb);
6618
6619         return ret;
6620 }
6621
6622 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6623                                     struct intel_crtc_config *pipe_config)
6624 {
6625         struct drm_device *dev = crtc->base.dev;
6626         struct drm_i915_private *dev_priv = dev->dev_private;
6627         enum intel_display_power_domain pfit_domain;
6628         uint32_t tmp;
6629
6630         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6631         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6632
6633         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6634         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6635                 enum pipe trans_edp_pipe;
6636                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6637                 default:
6638                         WARN(1, "unknown pipe linked to edp transcoder\n");
6639                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6640                 case TRANS_DDI_EDP_INPUT_A_ON:
6641                         trans_edp_pipe = PIPE_A;
6642                         break;
6643                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6644                         trans_edp_pipe = PIPE_B;
6645                         break;
6646                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6647                         trans_edp_pipe = PIPE_C;
6648                         break;
6649                 }
6650
6651                 if (trans_edp_pipe == crtc->pipe)
6652                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6653         }
6654
6655         if (!intel_display_power_enabled(dev,
6656                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6657                 return false;
6658
6659         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6660         if (!(tmp & PIPECONF_ENABLE))
6661                 return false;
6662
6663         /*
6664          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6665          * DDI E. So just check whether this pipe is wired to DDI E and whether
6666          * the PCH transcoder is on.
6667          */
6668         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6669         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6670             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6671                 pipe_config->has_pch_encoder = true;
6672
6673                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6674                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6675                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6676
6677                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6678         }
6679
6680         intel_get_pipe_timings(crtc, pipe_config);
6681
6682         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6683         if (intel_display_power_enabled(dev, pfit_domain))
6684                 ironlake_get_pfit_config(crtc, pipe_config);
6685
6686         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6687                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6688
6689         pipe_config->pixel_multiplier = 1;
6690
6691         return true;
6692 }
6693
6694 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6695                                int x, int y,
6696                                struct drm_framebuffer *fb)
6697 {
6698         struct drm_device *dev = crtc->dev;
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         struct intel_encoder *encoder;
6701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6702         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6703         int pipe = intel_crtc->pipe;
6704         int ret;
6705
6706         drm_vblank_pre_modeset(dev, pipe);
6707
6708         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6709
6710         drm_vblank_post_modeset(dev, pipe);
6711
6712         if (ret != 0)
6713                 return ret;
6714
6715         for_each_encoder_on_crtc(dev, crtc, encoder) {
6716                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6717                         encoder->base.base.id,
6718                         drm_get_encoder_name(&encoder->base),
6719                         mode->base.id, mode->name);
6720                 encoder->mode_set(encoder);
6721         }
6722
6723         return 0;
6724 }
6725
6726 static bool intel_eld_uptodate(struct drm_connector *connector,
6727                                int reg_eldv, uint32_t bits_eldv,
6728                                int reg_elda, uint32_t bits_elda,
6729                                int reg_edid)
6730 {
6731         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6732         uint8_t *eld = connector->eld;
6733         uint32_t i;
6734
6735         i = I915_READ(reg_eldv);
6736         i &= bits_eldv;
6737
6738         if (!eld[0])
6739                 return !i;
6740
6741         if (!i)
6742                 return false;
6743
6744         i = I915_READ(reg_elda);
6745         i &= ~bits_elda;
6746         I915_WRITE(reg_elda, i);
6747
6748         for (i = 0; i < eld[2]; i++)
6749                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6750                         return false;
6751
6752         return true;
6753 }
6754
6755 static void g4x_write_eld(struct drm_connector *connector,
6756                           struct drm_crtc *crtc,
6757                           struct drm_display_mode *mode)
6758 {
6759         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6760         uint8_t *eld = connector->eld;
6761         uint32_t eldv;
6762         uint32_t len;
6763         uint32_t i;
6764
6765         i = I915_READ(G4X_AUD_VID_DID);
6766
6767         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6768                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6769         else
6770                 eldv = G4X_ELDV_DEVCTG;
6771
6772         if (intel_eld_uptodate(connector,
6773                                G4X_AUD_CNTL_ST, eldv,
6774                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6775                                G4X_HDMIW_HDMIEDID))
6776                 return;
6777
6778         i = I915_READ(G4X_AUD_CNTL_ST);
6779         i &= ~(eldv | G4X_ELD_ADDR);
6780         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6781         I915_WRITE(G4X_AUD_CNTL_ST, i);
6782
6783         if (!eld[0])
6784                 return;
6785
6786         len = min_t(uint8_t, eld[2], len);
6787         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6788         for (i = 0; i < len; i++)
6789                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6790
6791         i = I915_READ(G4X_AUD_CNTL_ST);
6792         i |= eldv;
6793         I915_WRITE(G4X_AUD_CNTL_ST, i);
6794 }
6795
6796 static void haswell_write_eld(struct drm_connector *connector,
6797                               struct drm_crtc *crtc,
6798                               struct drm_display_mode *mode)
6799 {
6800         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6801         uint8_t *eld = connector->eld;
6802         struct drm_device *dev = crtc->dev;
6803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6804         uint32_t eldv;
6805         uint32_t i;
6806         int len;
6807         int pipe = to_intel_crtc(crtc)->pipe;
6808         int tmp;
6809
6810         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6811         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6812         int aud_config = HSW_AUD_CFG(pipe);
6813         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6814
6815
6816         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6817
6818         /* Audio output enable */
6819         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6820         tmp = I915_READ(aud_cntrl_st2);
6821         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6822         I915_WRITE(aud_cntrl_st2, tmp);
6823
6824         /* Wait for 1 vertical blank */
6825         intel_wait_for_vblank(dev, pipe);
6826
6827         /* Set ELD valid state */
6828         tmp = I915_READ(aud_cntrl_st2);
6829         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6830         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6831         I915_WRITE(aud_cntrl_st2, tmp);
6832         tmp = I915_READ(aud_cntrl_st2);
6833         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6834
6835         /* Enable HDMI mode */
6836         tmp = I915_READ(aud_config);
6837         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6838         /* clear N_programing_enable and N_value_index */
6839         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6840         I915_WRITE(aud_config, tmp);
6841
6842         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6843
6844         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6845         intel_crtc->eld_vld = true;
6846
6847         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6848                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6849                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6850                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6851         } else
6852                 I915_WRITE(aud_config, 0);
6853
6854         if (intel_eld_uptodate(connector,
6855                                aud_cntrl_st2, eldv,
6856                                aud_cntl_st, IBX_ELD_ADDRESS,
6857                                hdmiw_hdmiedid))
6858                 return;
6859
6860         i = I915_READ(aud_cntrl_st2);
6861         i &= ~eldv;
6862         I915_WRITE(aud_cntrl_st2, i);
6863
6864         if (!eld[0])
6865                 return;
6866
6867         i = I915_READ(aud_cntl_st);
6868         i &= ~IBX_ELD_ADDRESS;
6869         I915_WRITE(aud_cntl_st, i);
6870         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6871         DRM_DEBUG_DRIVER("port num:%d\n", i);
6872
6873         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6874         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6875         for (i = 0; i < len; i++)
6876                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6877
6878         i = I915_READ(aud_cntrl_st2);
6879         i |= eldv;
6880         I915_WRITE(aud_cntrl_st2, i);
6881
6882 }
6883
6884 static void ironlake_write_eld(struct drm_connector *connector,
6885                                struct drm_crtc *crtc,
6886                                struct drm_display_mode *mode)
6887 {
6888         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6889         uint8_t *eld = connector->eld;
6890         uint32_t eldv;
6891         uint32_t i;
6892         int len;
6893         int hdmiw_hdmiedid;
6894         int aud_config;
6895         int aud_cntl_st;
6896         int aud_cntrl_st2;
6897         int pipe = to_intel_crtc(crtc)->pipe;
6898
6899         if (HAS_PCH_IBX(connector->dev)) {
6900                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6901                 aud_config = IBX_AUD_CFG(pipe);
6902                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6903                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6904         } else {
6905                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6906                 aud_config = CPT_AUD_CFG(pipe);
6907                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6908                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6909         }
6910
6911         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6912
6913         i = I915_READ(aud_cntl_st);
6914         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6915         if (!i) {
6916                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6917                 /* operate blindly on all ports */
6918                 eldv = IBX_ELD_VALIDB;
6919                 eldv |= IBX_ELD_VALIDB << 4;
6920                 eldv |= IBX_ELD_VALIDB << 8;
6921         } else {
6922                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6923                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6924         }
6925
6926         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6927                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6928                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6929                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6930         } else
6931                 I915_WRITE(aud_config, 0);
6932
6933         if (intel_eld_uptodate(connector,
6934                                aud_cntrl_st2, eldv,
6935                                aud_cntl_st, IBX_ELD_ADDRESS,
6936                                hdmiw_hdmiedid))
6937                 return;
6938
6939         i = I915_READ(aud_cntrl_st2);
6940         i &= ~eldv;
6941         I915_WRITE(aud_cntrl_st2, i);
6942
6943         if (!eld[0])
6944                 return;
6945
6946         i = I915_READ(aud_cntl_st);
6947         i &= ~IBX_ELD_ADDRESS;
6948         I915_WRITE(aud_cntl_st, i);
6949
6950         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6951         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6952         for (i = 0; i < len; i++)
6953                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6954
6955         i = I915_READ(aud_cntrl_st2);
6956         i |= eldv;
6957         I915_WRITE(aud_cntrl_st2, i);
6958 }
6959
6960 void intel_write_eld(struct drm_encoder *encoder,
6961                      struct drm_display_mode *mode)
6962 {
6963         struct drm_crtc *crtc = encoder->crtc;
6964         struct drm_connector *connector;
6965         struct drm_device *dev = encoder->dev;
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967
6968         connector = drm_select_eld(encoder, mode);
6969         if (!connector)
6970                 return;
6971
6972         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6973                          connector->base.id,
6974                          drm_get_connector_name(connector),
6975                          connector->encoder->base.id,
6976                          drm_get_encoder_name(connector->encoder));
6977
6978         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6979
6980         if (dev_priv->display.write_eld)
6981                 dev_priv->display.write_eld(connector, crtc, mode);
6982 }
6983
6984 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6985 {
6986         struct drm_device *dev = crtc->dev;
6987         struct drm_i915_private *dev_priv = dev->dev_private;
6988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989         bool visible = base != 0;
6990         u32 cntl;
6991
6992         if (intel_crtc->cursor_visible == visible)
6993                 return;
6994
6995         cntl = I915_READ(_CURACNTR);
6996         if (visible) {
6997                 /* On these chipsets we can only modify the base whilst
6998                  * the cursor is disabled.
6999                  */
7000                 I915_WRITE(_CURABASE, base);
7001
7002                 cntl &= ~(CURSOR_FORMAT_MASK);
7003                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7004                 cntl |= CURSOR_ENABLE |
7005                         CURSOR_GAMMA_ENABLE |
7006                         CURSOR_FORMAT_ARGB;
7007         } else
7008                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7009         I915_WRITE(_CURACNTR, cntl);
7010
7011         intel_crtc->cursor_visible = visible;
7012 }
7013
7014 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7015 {
7016         struct drm_device *dev = crtc->dev;
7017         struct drm_i915_private *dev_priv = dev->dev_private;
7018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019         int pipe = intel_crtc->pipe;
7020         bool visible = base != 0;
7021
7022         if (intel_crtc->cursor_visible != visible) {
7023                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7024                 if (base) {
7025                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7026                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7027                         cntl |= pipe << 28; /* Connect to correct pipe */
7028                 } else {
7029                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7030                         cntl |= CURSOR_MODE_DISABLE;
7031                 }
7032                 I915_WRITE(CURCNTR(pipe), cntl);
7033
7034                 intel_crtc->cursor_visible = visible;
7035         }
7036         /* and commit changes on next vblank */
7037         I915_WRITE(CURBASE(pipe), base);
7038 }
7039
7040 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7041 {
7042         struct drm_device *dev = crtc->dev;
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7045         int pipe = intel_crtc->pipe;
7046         bool visible = base != 0;
7047
7048         if (intel_crtc->cursor_visible != visible) {
7049                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7050                 if (base) {
7051                         cntl &= ~CURSOR_MODE;
7052                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7053                 } else {
7054                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7055                         cntl |= CURSOR_MODE_DISABLE;
7056                 }
7057                 if (IS_HASWELL(dev)) {
7058                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7059                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7060                 }
7061                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7062
7063                 intel_crtc->cursor_visible = visible;
7064         }
7065         /* and commit changes on next vblank */
7066         I915_WRITE(CURBASE_IVB(pipe), base);
7067 }
7068
7069 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7070 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7071                                      bool on)
7072 {
7073         struct drm_device *dev = crtc->dev;
7074         struct drm_i915_private *dev_priv = dev->dev_private;
7075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076         int pipe = intel_crtc->pipe;
7077         int x = intel_crtc->cursor_x;
7078         int y = intel_crtc->cursor_y;
7079         u32 base = 0, pos = 0;
7080         bool visible;
7081
7082         if (on)
7083                 base = intel_crtc->cursor_addr;
7084
7085         if (x >= intel_crtc->config.pipe_src_w)
7086                 base = 0;
7087
7088         if (y >= intel_crtc->config.pipe_src_h)
7089                 base = 0;
7090
7091         if (x < 0) {
7092                 if (x + intel_crtc->cursor_width <= 0)
7093                         base = 0;
7094
7095                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7096                 x = -x;
7097         }
7098         pos |= x << CURSOR_X_SHIFT;
7099
7100         if (y < 0) {
7101                 if (y + intel_crtc->cursor_height <= 0)
7102                         base = 0;
7103
7104                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7105                 y = -y;
7106         }
7107         pos |= y << CURSOR_Y_SHIFT;
7108
7109         visible = base != 0;
7110         if (!visible && !intel_crtc->cursor_visible)
7111                 return;
7112
7113         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7114                 I915_WRITE(CURPOS_IVB(pipe), pos);
7115                 ivb_update_cursor(crtc, base);
7116         } else {
7117                 I915_WRITE(CURPOS(pipe), pos);
7118                 if (IS_845G(dev) || IS_I865G(dev))
7119                         i845_update_cursor(crtc, base);
7120                 else
7121                         i9xx_update_cursor(crtc, base);
7122         }
7123 }
7124
7125 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7126                                  struct drm_file *file,
7127                                  uint32_t handle,
7128                                  uint32_t width, uint32_t height)
7129 {
7130         struct drm_device *dev = crtc->dev;
7131         struct drm_i915_private *dev_priv = dev->dev_private;
7132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133         struct drm_i915_gem_object *obj;
7134         uint32_t addr;
7135         int ret;
7136
7137         /* if we want to turn off the cursor ignore width and height */
7138         if (!handle) {
7139                 DRM_DEBUG_KMS("cursor off\n");
7140                 addr = 0;
7141                 obj = NULL;
7142                 mutex_lock(&dev->struct_mutex);
7143                 goto finish;
7144         }
7145
7146         /* Currently we only support 64x64 cursors */
7147         if (width != 64 || height != 64) {
7148                 DRM_ERROR("we currently only support 64x64 cursors\n");
7149                 return -EINVAL;
7150         }
7151
7152         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7153         if (&obj->base == NULL)
7154                 return -ENOENT;
7155
7156         if (obj->base.size < width * height * 4) {
7157                 DRM_ERROR("buffer is to small\n");
7158                 ret = -ENOMEM;
7159                 goto fail;
7160         }
7161
7162         /* we only need to pin inside GTT if cursor is non-phy */
7163         mutex_lock(&dev->struct_mutex);
7164         if (!dev_priv->info->cursor_needs_physical) {
7165                 unsigned alignment;
7166
7167                 if (obj->tiling_mode) {
7168                         DRM_ERROR("cursor cannot be tiled\n");
7169                         ret = -EINVAL;
7170                         goto fail_locked;
7171                 }
7172
7173                 /* Note that the w/a also requires 2 PTE of padding following
7174                  * the bo. We currently fill all unused PTE with the shadow
7175                  * page and so we should always have valid PTE following the
7176                  * cursor preventing the VT-d warning.
7177                  */
7178                 alignment = 0;
7179                 if (need_vtd_wa(dev))
7180                         alignment = 64*1024;
7181
7182                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7183                 if (ret) {
7184                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7185                         goto fail_locked;
7186                 }
7187
7188                 ret = i915_gem_object_put_fence(obj);
7189                 if (ret) {
7190                         DRM_ERROR("failed to release fence for cursor");
7191                         goto fail_unpin;
7192                 }
7193
7194                 addr = i915_gem_obj_ggtt_offset(obj);
7195         } else {
7196                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7197                 ret = i915_gem_attach_phys_object(dev, obj,
7198                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7199                                                   align);
7200                 if (ret) {
7201                         DRM_ERROR("failed to attach phys object\n");
7202                         goto fail_locked;
7203                 }
7204                 addr = obj->phys_obj->handle->busaddr;
7205         }
7206
7207         if (IS_GEN2(dev))
7208                 I915_WRITE(CURSIZE, (height << 12) | width);
7209
7210  finish:
7211         if (intel_crtc->cursor_bo) {
7212                 if (dev_priv->info->cursor_needs_physical) {
7213                         if (intel_crtc->cursor_bo != obj)
7214                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7215                 } else
7216                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7217                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7218         }
7219
7220         mutex_unlock(&dev->struct_mutex);
7221
7222         intel_crtc->cursor_addr = addr;
7223         intel_crtc->cursor_bo = obj;
7224         intel_crtc->cursor_width = width;
7225         intel_crtc->cursor_height = height;
7226
7227         if (intel_crtc->active)
7228                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7229
7230         return 0;
7231 fail_unpin:
7232         i915_gem_object_unpin_from_display_plane(obj);
7233 fail_locked:
7234         mutex_unlock(&dev->struct_mutex);
7235 fail:
7236         drm_gem_object_unreference_unlocked(&obj->base);
7237         return ret;
7238 }
7239
7240 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7241 {
7242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243
7244         intel_crtc->cursor_x = x;
7245         intel_crtc->cursor_y = y;
7246
7247         if (intel_crtc->active)
7248                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7249
7250         return 0;
7251 }
7252
7253 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7254                                  u16 *blue, uint32_t start, uint32_t size)
7255 {
7256         int end = (start + size > 256) ? 256 : start + size, i;
7257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7258
7259         for (i = start; i < end; i++) {
7260                 intel_crtc->lut_r[i] = red[i] >> 8;
7261                 intel_crtc->lut_g[i] = green[i] >> 8;
7262                 intel_crtc->lut_b[i] = blue[i] >> 8;
7263         }
7264
7265         intel_crtc_load_lut(crtc);
7266 }
7267
7268 /* VESA 640x480x72Hz mode to set on the pipe */
7269 static struct drm_display_mode load_detect_mode = {
7270         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7271                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7272 };
7273
7274 static struct drm_framebuffer *
7275 intel_framebuffer_create(struct drm_device *dev,
7276                          struct drm_mode_fb_cmd2 *mode_cmd,
7277                          struct drm_i915_gem_object *obj)
7278 {
7279         struct intel_framebuffer *intel_fb;
7280         int ret;
7281
7282         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7283         if (!intel_fb) {
7284                 drm_gem_object_unreference_unlocked(&obj->base);
7285                 return ERR_PTR(-ENOMEM);
7286         }
7287
7288         ret = i915_mutex_lock_interruptible(dev);
7289         if (ret)
7290                 goto err;
7291
7292         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7293         mutex_unlock(&dev->struct_mutex);
7294         if (ret)
7295                 goto err;
7296
7297         return &intel_fb->base;
7298 err:
7299         drm_gem_object_unreference_unlocked(&obj->base);
7300         kfree(intel_fb);
7301
7302         return ERR_PTR(ret);
7303 }
7304
7305 static u32
7306 intel_framebuffer_pitch_for_width(int width, int bpp)
7307 {
7308         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7309         return ALIGN(pitch, 64);
7310 }
7311
7312 static u32
7313 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7314 {
7315         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7316         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7317 }
7318
7319 static struct drm_framebuffer *
7320 intel_framebuffer_create_for_mode(struct drm_device *dev,
7321                                   struct drm_display_mode *mode,
7322                                   int depth, int bpp)
7323 {
7324         struct drm_i915_gem_object *obj;
7325         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7326
7327         obj = i915_gem_alloc_object(dev,
7328                                     intel_framebuffer_size_for_mode(mode, bpp));
7329         if (obj == NULL)
7330                 return ERR_PTR(-ENOMEM);
7331
7332         mode_cmd.width = mode->hdisplay;
7333         mode_cmd.height = mode->vdisplay;
7334         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7335                                                                 bpp);
7336         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7337
7338         return intel_framebuffer_create(dev, &mode_cmd, obj);
7339 }
7340
7341 static struct drm_framebuffer *
7342 mode_fits_in_fbdev(struct drm_device *dev,
7343                    struct drm_display_mode *mode)
7344 {
7345 #ifdef CONFIG_DRM_I915_FBDEV
7346         struct drm_i915_private *dev_priv = dev->dev_private;
7347         struct drm_i915_gem_object *obj;
7348         struct drm_framebuffer *fb;
7349
7350         if (dev_priv->fbdev == NULL)
7351                 return NULL;
7352
7353         obj = dev_priv->fbdev->ifb.obj;
7354         if (obj == NULL)
7355                 return NULL;
7356
7357         fb = &dev_priv->fbdev->ifb.base;
7358         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7359                                                                fb->bits_per_pixel))
7360                 return NULL;
7361
7362         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7363                 return NULL;
7364
7365         return fb;
7366 #else
7367         return NULL;
7368 #endif
7369 }
7370
7371 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7372                                 struct drm_display_mode *mode,
7373                                 struct intel_load_detect_pipe *old)
7374 {
7375         struct intel_crtc *intel_crtc;
7376         struct intel_encoder *intel_encoder =
7377                 intel_attached_encoder(connector);
7378         struct drm_crtc *possible_crtc;
7379         struct drm_encoder *encoder = &intel_encoder->base;
7380         struct drm_crtc *crtc = NULL;
7381         struct drm_device *dev = encoder->dev;
7382         struct drm_framebuffer *fb;
7383         int i = -1;
7384
7385         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7386                       connector->base.id, drm_get_connector_name(connector),
7387                       encoder->base.id, drm_get_encoder_name(encoder));
7388
7389         /*
7390          * Algorithm gets a little messy:
7391          *
7392          *   - if the connector already has an assigned crtc, use it (but make
7393          *     sure it's on first)
7394          *
7395          *   - try to find the first unused crtc that can drive this connector,
7396          *     and use that if we find one
7397          */
7398
7399         /* See if we already have a CRTC for this connector */
7400         if (encoder->crtc) {
7401                 crtc = encoder->crtc;
7402
7403                 mutex_lock(&crtc->mutex);
7404
7405                 old->dpms_mode = connector->dpms;
7406                 old->load_detect_temp = false;
7407
7408                 /* Make sure the crtc and connector are running */
7409                 if (connector->dpms != DRM_MODE_DPMS_ON)
7410                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7411
7412                 return true;
7413         }
7414
7415         /* Find an unused one (if possible) */
7416         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7417                 i++;
7418                 if (!(encoder->possible_crtcs & (1 << i)))
7419                         continue;
7420                 if (!possible_crtc->enabled) {
7421                         crtc = possible_crtc;
7422                         break;
7423                 }
7424         }
7425
7426         /*
7427          * If we didn't find an unused CRTC, don't use any.
7428          */
7429         if (!crtc) {
7430                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7431                 return false;
7432         }
7433
7434         mutex_lock(&crtc->mutex);
7435         intel_encoder->new_crtc = to_intel_crtc(crtc);
7436         to_intel_connector(connector)->new_encoder = intel_encoder;
7437
7438         intel_crtc = to_intel_crtc(crtc);
7439         old->dpms_mode = connector->dpms;
7440         old->load_detect_temp = true;
7441         old->release_fb = NULL;
7442
7443         if (!mode)
7444                 mode = &load_detect_mode;
7445
7446         /* We need a framebuffer large enough to accommodate all accesses
7447          * that the plane may generate whilst we perform load detection.
7448          * We can not rely on the fbcon either being present (we get called
7449          * during its initialisation to detect all boot displays, or it may
7450          * not even exist) or that it is large enough to satisfy the
7451          * requested mode.
7452          */
7453         fb = mode_fits_in_fbdev(dev, mode);
7454         if (fb == NULL) {
7455                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7456                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7457                 old->release_fb = fb;
7458         } else
7459                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7460         if (IS_ERR(fb)) {
7461                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7462                 mutex_unlock(&crtc->mutex);
7463                 return false;
7464         }
7465
7466         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7467                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7468                 if (old->release_fb)
7469                         old->release_fb->funcs->destroy(old->release_fb);
7470                 mutex_unlock(&crtc->mutex);
7471                 return false;
7472         }
7473
7474         /* let the connector get through one full cycle before testing */
7475         intel_wait_for_vblank(dev, intel_crtc->pipe);
7476         return true;
7477 }
7478
7479 void intel_release_load_detect_pipe(struct drm_connector *connector,
7480                                     struct intel_load_detect_pipe *old)
7481 {
7482         struct intel_encoder *intel_encoder =
7483                 intel_attached_encoder(connector);
7484         struct drm_encoder *encoder = &intel_encoder->base;
7485         struct drm_crtc *crtc = encoder->crtc;
7486
7487         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7488                       connector->base.id, drm_get_connector_name(connector),
7489                       encoder->base.id, drm_get_encoder_name(encoder));
7490
7491         if (old->load_detect_temp) {
7492                 to_intel_connector(connector)->new_encoder = NULL;
7493                 intel_encoder->new_crtc = NULL;
7494                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7495
7496                 if (old->release_fb) {
7497                         drm_framebuffer_unregister_private(old->release_fb);
7498                         drm_framebuffer_unreference(old->release_fb);
7499                 }
7500
7501                 mutex_unlock(&crtc->mutex);
7502                 return;
7503         }
7504
7505         /* Switch crtc and encoder back off if necessary */
7506         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7507                 connector->funcs->dpms(connector, old->dpms_mode);
7508
7509         mutex_unlock(&crtc->mutex);
7510 }
7511
7512 static int i9xx_pll_refclk(struct drm_device *dev,
7513                            const struct intel_crtc_config *pipe_config)
7514 {
7515         struct drm_i915_private *dev_priv = dev->dev_private;
7516         u32 dpll = pipe_config->dpll_hw_state.dpll;
7517
7518         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7519                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7520         else if (HAS_PCH_SPLIT(dev))
7521                 return 120000;
7522         else if (!IS_GEN2(dev))
7523                 return 96000;
7524         else
7525                 return 48000;
7526 }
7527
7528 /* Returns the clock of the currently programmed mode of the given pipe. */
7529 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7530                                 struct intel_crtc_config *pipe_config)
7531 {
7532         struct drm_device *dev = crtc->base.dev;
7533         struct drm_i915_private *dev_priv = dev->dev_private;
7534         int pipe = pipe_config->cpu_transcoder;
7535         u32 dpll = pipe_config->dpll_hw_state.dpll;
7536         u32 fp;
7537         intel_clock_t clock;
7538         int refclk = i9xx_pll_refclk(dev, pipe_config);
7539
7540         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7541                 fp = pipe_config->dpll_hw_state.fp0;
7542         else
7543                 fp = pipe_config->dpll_hw_state.fp1;
7544
7545         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7546         if (IS_PINEVIEW(dev)) {
7547                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7548                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7549         } else {
7550                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7551                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7552         }
7553
7554         if (!IS_GEN2(dev)) {
7555                 if (IS_PINEVIEW(dev))
7556                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7557                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7558                 else
7559                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7560                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7561
7562                 switch (dpll & DPLL_MODE_MASK) {
7563                 case DPLLB_MODE_DAC_SERIAL:
7564                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7565                                 5 : 10;
7566                         break;
7567                 case DPLLB_MODE_LVDS:
7568                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7569                                 7 : 14;
7570                         break;
7571                 default:
7572                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7573                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7574                         return;
7575                 }
7576
7577                 if (IS_PINEVIEW(dev))
7578                         pineview_clock(refclk, &clock);
7579                 else
7580                         i9xx_clock(refclk, &clock);
7581         } else {
7582                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7583
7584                 if (is_lvds) {
7585                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7586                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7587                         clock.p2 = 14;
7588                 } else {
7589                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7590                                 clock.p1 = 2;
7591                         else {
7592                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7593                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7594                         }
7595                         if (dpll & PLL_P2_DIVIDE_BY_4)
7596                                 clock.p2 = 4;
7597                         else
7598                                 clock.p2 = 2;
7599                 }
7600
7601                 i9xx_clock(refclk, &clock);
7602         }
7603
7604         /*
7605          * This value includes pixel_multiplier. We will use
7606          * port_clock to compute adjusted_mode.crtc_clock in the
7607          * encoder's get_config() function.
7608          */
7609         pipe_config->port_clock = clock.dot;
7610 }
7611
7612 int intel_dotclock_calculate(int link_freq,
7613                              const struct intel_link_m_n *m_n)
7614 {
7615         /*
7616          * The calculation for the data clock is:
7617          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7618          * But we want to avoid losing precison if possible, so:
7619          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7620          *
7621          * and the link clock is simpler:
7622          * link_clock = (m * link_clock) / n
7623          */
7624
7625         if (!m_n->link_n)
7626                 return 0;
7627
7628         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7629 }
7630
7631 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7632                                    struct intel_crtc_config *pipe_config)
7633 {
7634         struct drm_device *dev = crtc->base.dev;
7635
7636         /* read out port_clock from the DPLL */
7637         i9xx_crtc_clock_get(crtc, pipe_config);
7638
7639         /*
7640          * This value does not include pixel_multiplier.
7641          * We will check that port_clock and adjusted_mode.crtc_clock
7642          * agree once we know their relationship in the encoder's
7643          * get_config() function.
7644          */
7645         pipe_config->adjusted_mode.crtc_clock =
7646                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7647                                          &pipe_config->fdi_m_n);
7648 }
7649
7650 /** Returns the currently programmed mode of the given pipe. */
7651 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7652                                              struct drm_crtc *crtc)
7653 {
7654         struct drm_i915_private *dev_priv = dev->dev_private;
7655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7656         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7657         struct drm_display_mode *mode;
7658         struct intel_crtc_config pipe_config;
7659         int htot = I915_READ(HTOTAL(cpu_transcoder));
7660         int hsync = I915_READ(HSYNC(cpu_transcoder));
7661         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7662         int vsync = I915_READ(VSYNC(cpu_transcoder));
7663         enum pipe pipe = intel_crtc->pipe;
7664
7665         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7666         if (!mode)
7667                 return NULL;
7668
7669         /*
7670          * Construct a pipe_config sufficient for getting the clock info
7671          * back out of crtc_clock_get.
7672          *
7673          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7674          * to use a real value here instead.
7675          */
7676         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7677         pipe_config.pixel_multiplier = 1;
7678         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7679         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7680         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7681         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7682
7683         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7684         mode->hdisplay = (htot & 0xffff) + 1;
7685         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7686         mode->hsync_start = (hsync & 0xffff) + 1;
7687         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7688         mode->vdisplay = (vtot & 0xffff) + 1;
7689         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7690         mode->vsync_start = (vsync & 0xffff) + 1;
7691         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7692
7693         drm_mode_set_name(mode);
7694
7695         return mode;
7696 }
7697
7698 static void intel_increase_pllclock(struct drm_crtc *crtc)
7699 {
7700         struct drm_device *dev = crtc->dev;
7701         drm_i915_private_t *dev_priv = dev->dev_private;
7702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7703         int pipe = intel_crtc->pipe;
7704         int dpll_reg = DPLL(pipe);
7705         int dpll;
7706
7707         if (HAS_PCH_SPLIT(dev))
7708                 return;
7709
7710         if (!dev_priv->lvds_downclock_avail)
7711                 return;
7712
7713         dpll = I915_READ(dpll_reg);
7714         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7715                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7716
7717                 assert_panel_unlocked(dev_priv, pipe);
7718
7719                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7720                 I915_WRITE(dpll_reg, dpll);
7721                 intel_wait_for_vblank(dev, pipe);
7722
7723                 dpll = I915_READ(dpll_reg);
7724                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7725                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7726         }
7727 }
7728
7729 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7730 {
7731         struct drm_device *dev = crtc->dev;
7732         drm_i915_private_t *dev_priv = dev->dev_private;
7733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7734
7735         if (HAS_PCH_SPLIT(dev))
7736                 return;
7737
7738         if (!dev_priv->lvds_downclock_avail)
7739                 return;
7740
7741         /*
7742          * Since this is called by a timer, we should never get here in
7743          * the manual case.
7744          */
7745         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7746                 int pipe = intel_crtc->pipe;
7747                 int dpll_reg = DPLL(pipe);
7748                 int dpll;
7749
7750                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7751
7752                 assert_panel_unlocked(dev_priv, pipe);
7753
7754                 dpll = I915_READ(dpll_reg);
7755                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7756                 I915_WRITE(dpll_reg, dpll);
7757                 intel_wait_for_vblank(dev, pipe);
7758                 dpll = I915_READ(dpll_reg);
7759                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7760                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7761         }
7762
7763 }
7764
7765 void intel_mark_busy(struct drm_device *dev)
7766 {
7767         struct drm_i915_private *dev_priv = dev->dev_private;
7768
7769         hsw_package_c8_gpu_busy(dev_priv);
7770         i915_update_gfx_val(dev_priv);
7771 }
7772
7773 void intel_mark_idle(struct drm_device *dev)
7774 {
7775         struct drm_i915_private *dev_priv = dev->dev_private;
7776         struct drm_crtc *crtc;
7777
7778         hsw_package_c8_gpu_idle(dev_priv);
7779
7780         if (!i915_powersave)
7781                 return;
7782
7783         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7784                 if (!crtc->fb)
7785                         continue;
7786
7787                 intel_decrease_pllclock(crtc);
7788         }
7789
7790         if (dev_priv->info->gen >= 6)
7791                 gen6_rps_idle(dev->dev_private);
7792 }
7793
7794 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7795                         struct intel_ring_buffer *ring)
7796 {
7797         struct drm_device *dev = obj->base.dev;
7798         struct drm_crtc *crtc;
7799
7800         if (!i915_powersave)
7801                 return;
7802
7803         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7804                 if (!crtc->fb)
7805                         continue;
7806
7807                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7808                         continue;
7809
7810                 intel_increase_pllclock(crtc);
7811                 if (ring && intel_fbc_enabled(dev))
7812                         ring->fbc_dirty = true;
7813         }
7814 }
7815
7816 static void intel_crtc_destroy(struct drm_crtc *crtc)
7817 {
7818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7819         struct drm_device *dev = crtc->dev;
7820         struct intel_unpin_work *work;
7821         unsigned long flags;
7822
7823         spin_lock_irqsave(&dev->event_lock, flags);
7824         work = intel_crtc->unpin_work;
7825         intel_crtc->unpin_work = NULL;
7826         spin_unlock_irqrestore(&dev->event_lock, flags);
7827
7828         if (work) {
7829                 cancel_work_sync(&work->work);
7830                 kfree(work);
7831         }
7832
7833         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7834
7835         drm_crtc_cleanup(crtc);
7836
7837         kfree(intel_crtc);
7838 }
7839
7840 static void intel_unpin_work_fn(struct work_struct *__work)
7841 {
7842         struct intel_unpin_work *work =
7843                 container_of(__work, struct intel_unpin_work, work);
7844         struct drm_device *dev = work->crtc->dev;
7845
7846         mutex_lock(&dev->struct_mutex);
7847         intel_unpin_fb_obj(work->old_fb_obj);
7848         drm_gem_object_unreference(&work->pending_flip_obj->base);
7849         drm_gem_object_unreference(&work->old_fb_obj->base);
7850
7851         intel_update_fbc(dev);
7852         mutex_unlock(&dev->struct_mutex);
7853
7854         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7855         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7856
7857         kfree(work);
7858 }
7859
7860 static void do_intel_finish_page_flip(struct drm_device *dev,
7861                                       struct drm_crtc *crtc)
7862 {
7863         drm_i915_private_t *dev_priv = dev->dev_private;
7864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7865         struct intel_unpin_work *work;
7866         unsigned long flags;
7867
7868         /* Ignore early vblank irqs */
7869         if (intel_crtc == NULL)
7870                 return;
7871
7872         spin_lock_irqsave(&dev->event_lock, flags);
7873         work = intel_crtc->unpin_work;
7874
7875         /* Ensure we don't miss a work->pending update ... */
7876         smp_rmb();
7877
7878         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7879                 spin_unlock_irqrestore(&dev->event_lock, flags);
7880                 return;
7881         }
7882
7883         /* and that the unpin work is consistent wrt ->pending. */
7884         smp_rmb();
7885
7886         intel_crtc->unpin_work = NULL;
7887
7888         if (work->event)
7889                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7890
7891         drm_vblank_put(dev, intel_crtc->pipe);
7892
7893         spin_unlock_irqrestore(&dev->event_lock, flags);
7894
7895         wake_up_all(&dev_priv->pending_flip_queue);
7896
7897         queue_work(dev_priv->wq, &work->work);
7898
7899         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7900 }
7901
7902 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7903 {
7904         drm_i915_private_t *dev_priv = dev->dev_private;
7905         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7906
7907         do_intel_finish_page_flip(dev, crtc);
7908 }
7909
7910 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7911 {
7912         drm_i915_private_t *dev_priv = dev->dev_private;
7913         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7914
7915         do_intel_finish_page_flip(dev, crtc);
7916 }
7917
7918 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7919 {
7920         drm_i915_private_t *dev_priv = dev->dev_private;
7921         struct intel_crtc *intel_crtc =
7922                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7923         unsigned long flags;
7924
7925         /* NB: An MMIO update of the plane base pointer will also
7926          * generate a page-flip completion irq, i.e. every modeset
7927          * is also accompanied by a spurious intel_prepare_page_flip().
7928          */
7929         spin_lock_irqsave(&dev->event_lock, flags);
7930         if (intel_crtc->unpin_work)
7931                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7932         spin_unlock_irqrestore(&dev->event_lock, flags);
7933 }
7934
7935 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7936 {
7937         /* Ensure that the work item is consistent when activating it ... */
7938         smp_wmb();
7939         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7940         /* and that it is marked active as soon as the irq could fire. */
7941         smp_wmb();
7942 }
7943
7944 static int intel_gen2_queue_flip(struct drm_device *dev,
7945                                  struct drm_crtc *crtc,
7946                                  struct drm_framebuffer *fb,
7947                                  struct drm_i915_gem_object *obj,
7948                                  uint32_t flags)
7949 {
7950         struct drm_i915_private *dev_priv = dev->dev_private;
7951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7952         u32 flip_mask;
7953         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7954         int ret;
7955
7956         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7957         if (ret)
7958                 goto err;
7959
7960         ret = intel_ring_begin(ring, 6);
7961         if (ret)
7962                 goto err_unpin;
7963
7964         /* Can't queue multiple flips, so wait for the previous
7965          * one to finish before executing the next.
7966          */
7967         if (intel_crtc->plane)
7968                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7969         else
7970                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7971         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7972         intel_ring_emit(ring, MI_NOOP);
7973         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7974                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7975         intel_ring_emit(ring, fb->pitches[0]);
7976         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7977         intel_ring_emit(ring, 0); /* aux display base address, unused */
7978
7979         intel_mark_page_flip_active(intel_crtc);
7980         __intel_ring_advance(ring);
7981         return 0;
7982
7983 err_unpin:
7984         intel_unpin_fb_obj(obj);
7985 err:
7986         return ret;
7987 }
7988
7989 static int intel_gen3_queue_flip(struct drm_device *dev,
7990                                  struct drm_crtc *crtc,
7991                                  struct drm_framebuffer *fb,
7992                                  struct drm_i915_gem_object *obj,
7993                                  uint32_t flags)
7994 {
7995         struct drm_i915_private *dev_priv = dev->dev_private;
7996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7997         u32 flip_mask;
7998         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7999         int ret;
8000
8001         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8002         if (ret)
8003                 goto err;
8004
8005         ret = intel_ring_begin(ring, 6);
8006         if (ret)
8007                 goto err_unpin;
8008
8009         if (intel_crtc->plane)
8010                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8011         else
8012                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8013         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8014         intel_ring_emit(ring, MI_NOOP);
8015         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8016                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8017         intel_ring_emit(ring, fb->pitches[0]);
8018         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8019         intel_ring_emit(ring, MI_NOOP);
8020
8021         intel_mark_page_flip_active(intel_crtc);
8022         __intel_ring_advance(ring);
8023         return 0;
8024
8025 err_unpin:
8026         intel_unpin_fb_obj(obj);
8027 err:
8028         return ret;
8029 }
8030
8031 static int intel_gen4_queue_flip(struct drm_device *dev,
8032                                  struct drm_crtc *crtc,
8033                                  struct drm_framebuffer *fb,
8034                                  struct drm_i915_gem_object *obj,
8035                                  uint32_t flags)
8036 {
8037         struct drm_i915_private *dev_priv = dev->dev_private;
8038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8039         uint32_t pf, pipesrc;
8040         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8041         int ret;
8042
8043         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8044         if (ret)
8045                 goto err;
8046
8047         ret = intel_ring_begin(ring, 4);
8048         if (ret)
8049                 goto err_unpin;
8050
8051         /* i965+ uses the linear or tiled offsets from the
8052          * Display Registers (which do not change across a page-flip)
8053          * so we need only reprogram the base address.
8054          */
8055         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8056                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8057         intel_ring_emit(ring, fb->pitches[0]);
8058         intel_ring_emit(ring,
8059                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8060                         obj->tiling_mode);
8061
8062         /* XXX Enabling the panel-fitter across page-flip is so far
8063          * untested on non-native modes, so ignore it for now.
8064          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8065          */
8066         pf = 0;
8067         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8068         intel_ring_emit(ring, pf | pipesrc);
8069
8070         intel_mark_page_flip_active(intel_crtc);
8071         __intel_ring_advance(ring);
8072         return 0;
8073
8074 err_unpin:
8075         intel_unpin_fb_obj(obj);
8076 err:
8077         return ret;
8078 }
8079
8080 static int intel_gen6_queue_flip(struct drm_device *dev,
8081                                  struct drm_crtc *crtc,
8082                                  struct drm_framebuffer *fb,
8083                                  struct drm_i915_gem_object *obj,
8084                                  uint32_t flags)
8085 {
8086         struct drm_i915_private *dev_priv = dev->dev_private;
8087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8088         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8089         uint32_t pf, pipesrc;
8090         int ret;
8091
8092         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8093         if (ret)
8094                 goto err;
8095
8096         ret = intel_ring_begin(ring, 4);
8097         if (ret)
8098                 goto err_unpin;
8099
8100         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8101                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8102         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8103         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8104
8105         /* Contrary to the suggestions in the documentation,
8106          * "Enable Panel Fitter" does not seem to be required when page
8107          * flipping with a non-native mode, and worse causes a normal
8108          * modeset to fail.
8109          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8110          */
8111         pf = 0;
8112         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8113         intel_ring_emit(ring, pf | pipesrc);
8114
8115         intel_mark_page_flip_active(intel_crtc);
8116         __intel_ring_advance(ring);
8117         return 0;
8118
8119 err_unpin:
8120         intel_unpin_fb_obj(obj);
8121 err:
8122         return ret;
8123 }
8124
8125 static int intel_gen7_queue_flip(struct drm_device *dev,
8126                                  struct drm_crtc *crtc,
8127                                  struct drm_framebuffer *fb,
8128                                  struct drm_i915_gem_object *obj,
8129                                  uint32_t flags)
8130 {
8131         struct drm_i915_private *dev_priv = dev->dev_private;
8132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8133         struct intel_ring_buffer *ring;
8134         uint32_t plane_bit = 0;
8135         int len, ret;
8136
8137         ring = obj->ring;
8138         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8139                 ring = &dev_priv->ring[BCS];
8140
8141         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8142         if (ret)
8143                 goto err;
8144
8145         switch(intel_crtc->plane) {
8146         case PLANE_A:
8147                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8148                 break;
8149         case PLANE_B:
8150                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8151                 break;
8152         case PLANE_C:
8153                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8154                 break;
8155         default:
8156                 WARN_ONCE(1, "unknown plane in flip command\n");
8157                 ret = -ENODEV;
8158                 goto err_unpin;
8159         }
8160
8161         len = 4;
8162         if (ring->id == RCS)
8163                 len += 6;
8164
8165         ret = intel_ring_begin(ring, len);
8166         if (ret)
8167                 goto err_unpin;
8168
8169         /* Unmask the flip-done completion message. Note that the bspec says that
8170          * we should do this for both the BCS and RCS, and that we must not unmask
8171          * more than one flip event at any time (or ensure that one flip message
8172          * can be sent by waiting for flip-done prior to queueing new flips).
8173          * Experimentation says that BCS works despite DERRMR masking all
8174          * flip-done completion events and that unmasking all planes at once
8175          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8176          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8177          */
8178         if (ring->id == RCS) {
8179                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8180                 intel_ring_emit(ring, DERRMR);
8181                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8182                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8183                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8184                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8185                 intel_ring_emit(ring, DERRMR);
8186                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8187         }
8188
8189         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8190         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8191         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8192         intel_ring_emit(ring, (MI_NOOP));
8193
8194         intel_mark_page_flip_active(intel_crtc);
8195         __intel_ring_advance(ring);
8196         return 0;
8197
8198 err_unpin:
8199         intel_unpin_fb_obj(obj);
8200 err:
8201         return ret;
8202 }
8203
8204 static int intel_default_queue_flip(struct drm_device *dev,
8205                                     struct drm_crtc *crtc,
8206                                     struct drm_framebuffer *fb,
8207                                     struct drm_i915_gem_object *obj,
8208                                     uint32_t flags)
8209 {
8210         return -ENODEV;
8211 }
8212
8213 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8214                                 struct drm_framebuffer *fb,
8215                                 struct drm_pending_vblank_event *event,
8216                                 uint32_t page_flip_flags)
8217 {
8218         struct drm_device *dev = crtc->dev;
8219         struct drm_i915_private *dev_priv = dev->dev_private;
8220         struct drm_framebuffer *old_fb = crtc->fb;
8221         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8223         struct intel_unpin_work *work;
8224         unsigned long flags;
8225         int ret;
8226
8227         /* Can't change pixel format via MI display flips. */
8228         if (fb->pixel_format != crtc->fb->pixel_format)
8229                 return -EINVAL;
8230
8231         /*
8232          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8233          * Note that pitch changes could also affect these register.
8234          */
8235         if (INTEL_INFO(dev)->gen > 3 &&
8236             (fb->offsets[0] != crtc->fb->offsets[0] ||
8237              fb->pitches[0] != crtc->fb->pitches[0]))
8238                 return -EINVAL;
8239
8240         work = kzalloc(sizeof(*work), GFP_KERNEL);
8241         if (work == NULL)
8242                 return -ENOMEM;
8243
8244         work->event = event;
8245         work->crtc = crtc;
8246         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8247         INIT_WORK(&work->work, intel_unpin_work_fn);
8248
8249         ret = drm_vblank_get(dev, intel_crtc->pipe);
8250         if (ret)
8251                 goto free_work;
8252
8253         /* We borrow the event spin lock for protecting unpin_work */
8254         spin_lock_irqsave(&dev->event_lock, flags);
8255         if (intel_crtc->unpin_work) {
8256                 spin_unlock_irqrestore(&dev->event_lock, flags);
8257                 kfree(work);
8258                 drm_vblank_put(dev, intel_crtc->pipe);
8259
8260                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8261                 return -EBUSY;
8262         }
8263         intel_crtc->unpin_work = work;
8264         spin_unlock_irqrestore(&dev->event_lock, flags);
8265
8266         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8267                 flush_workqueue(dev_priv->wq);
8268
8269         ret = i915_mutex_lock_interruptible(dev);
8270         if (ret)
8271                 goto cleanup;
8272
8273         /* Reference the objects for the scheduled work. */
8274         drm_gem_object_reference(&work->old_fb_obj->base);
8275         drm_gem_object_reference(&obj->base);
8276
8277         crtc->fb = fb;
8278
8279         work->pending_flip_obj = obj;
8280
8281         work->enable_stall_check = true;
8282
8283         atomic_inc(&intel_crtc->unpin_work_count);
8284         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8285
8286         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8287         if (ret)
8288                 goto cleanup_pending;
8289
8290         intel_disable_fbc(dev);
8291         intel_mark_fb_busy(obj, NULL);
8292         mutex_unlock(&dev->struct_mutex);
8293
8294         trace_i915_flip_request(intel_crtc->plane, obj);
8295
8296         return 0;
8297
8298 cleanup_pending:
8299         atomic_dec(&intel_crtc->unpin_work_count);
8300         crtc->fb = old_fb;
8301         drm_gem_object_unreference(&work->old_fb_obj->base);
8302         drm_gem_object_unreference(&obj->base);
8303         mutex_unlock(&dev->struct_mutex);
8304
8305 cleanup:
8306         spin_lock_irqsave(&dev->event_lock, flags);
8307         intel_crtc->unpin_work = NULL;
8308         spin_unlock_irqrestore(&dev->event_lock, flags);
8309
8310         drm_vblank_put(dev, intel_crtc->pipe);
8311 free_work:
8312         kfree(work);
8313
8314         return ret;
8315 }
8316
8317 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8318         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8319         .load_lut = intel_crtc_load_lut,
8320 };
8321
8322 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8323                                   struct drm_crtc *crtc)
8324 {
8325         struct drm_device *dev;
8326         struct drm_crtc *tmp;
8327         int crtc_mask = 1;
8328
8329         WARN(!crtc, "checking null crtc?\n");
8330
8331         dev = crtc->dev;
8332
8333         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8334                 if (tmp == crtc)
8335                         break;
8336                 crtc_mask <<= 1;
8337         }
8338
8339         if (encoder->possible_crtcs & crtc_mask)
8340                 return true;
8341         return false;
8342 }
8343
8344 /**
8345  * intel_modeset_update_staged_output_state
8346  *
8347  * Updates the staged output configuration state, e.g. after we've read out the
8348  * current hw state.
8349  */
8350 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8351 {
8352         struct intel_encoder *encoder;
8353         struct intel_connector *connector;
8354
8355         list_for_each_entry(connector, &dev->mode_config.connector_list,
8356                             base.head) {
8357                 connector->new_encoder =
8358                         to_intel_encoder(connector->base.encoder);
8359         }
8360
8361         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8362                             base.head) {
8363                 encoder->new_crtc =
8364                         to_intel_crtc(encoder->base.crtc);
8365         }
8366 }
8367
8368 /**
8369  * intel_modeset_commit_output_state
8370  *
8371  * This function copies the stage display pipe configuration to the real one.
8372  */
8373 static void intel_modeset_commit_output_state(struct drm_device *dev)
8374 {
8375         struct intel_encoder *encoder;
8376         struct intel_connector *connector;
8377
8378         list_for_each_entry(connector, &dev->mode_config.connector_list,
8379                             base.head) {
8380                 connector->base.encoder = &connector->new_encoder->base;
8381         }
8382
8383         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8384                             base.head) {
8385                 encoder->base.crtc = &encoder->new_crtc->base;
8386         }
8387 }
8388
8389 static void
8390 connected_sink_compute_bpp(struct intel_connector * connector,
8391                            struct intel_crtc_config *pipe_config)
8392 {
8393         int bpp = pipe_config->pipe_bpp;
8394
8395         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8396                 connector->base.base.id,
8397                 drm_get_connector_name(&connector->base));
8398
8399         /* Don't use an invalid EDID bpc value */
8400         if (connector->base.display_info.bpc &&
8401             connector->base.display_info.bpc * 3 < bpp) {
8402                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8403                               bpp, connector->base.display_info.bpc*3);
8404                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8405         }
8406
8407         /* Clamp bpp to 8 on screens without EDID 1.4 */
8408         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8409                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8410                               bpp);
8411                 pipe_config->pipe_bpp = 24;
8412         }
8413 }
8414
8415 static int
8416 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8417                           struct drm_framebuffer *fb,
8418                           struct intel_crtc_config *pipe_config)
8419 {
8420         struct drm_device *dev = crtc->base.dev;
8421         struct intel_connector *connector;
8422         int bpp;
8423
8424         switch (fb->pixel_format) {
8425         case DRM_FORMAT_C8:
8426                 bpp = 8*3; /* since we go through a colormap */
8427                 break;
8428         case DRM_FORMAT_XRGB1555:
8429         case DRM_FORMAT_ARGB1555:
8430                 /* checked in intel_framebuffer_init already */
8431                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8432                         return -EINVAL;
8433         case DRM_FORMAT_RGB565:
8434                 bpp = 6*3; /* min is 18bpp */
8435                 break;
8436         case DRM_FORMAT_XBGR8888:
8437         case DRM_FORMAT_ABGR8888:
8438                 /* checked in intel_framebuffer_init already */
8439                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8440                         return -EINVAL;
8441         case DRM_FORMAT_XRGB8888:
8442         case DRM_FORMAT_ARGB8888:
8443                 bpp = 8*3;
8444                 break;
8445         case DRM_FORMAT_XRGB2101010:
8446         case DRM_FORMAT_ARGB2101010:
8447         case DRM_FORMAT_XBGR2101010:
8448         case DRM_FORMAT_ABGR2101010:
8449                 /* checked in intel_framebuffer_init already */
8450                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8451                         return -EINVAL;
8452                 bpp = 10*3;
8453                 break;
8454         /* TODO: gen4+ supports 16 bpc floating point, too. */
8455         default:
8456                 DRM_DEBUG_KMS("unsupported depth\n");
8457                 return -EINVAL;
8458         }
8459
8460         pipe_config->pipe_bpp = bpp;
8461
8462         /* Clamp display bpp to EDID value */
8463         list_for_each_entry(connector, &dev->mode_config.connector_list,
8464                             base.head) {
8465                 if (!connector->new_encoder ||
8466                     connector->new_encoder->new_crtc != crtc)
8467                         continue;
8468
8469                 connected_sink_compute_bpp(connector, pipe_config);
8470         }
8471
8472         return bpp;
8473 }
8474
8475 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8476 {
8477         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8478                         "type: 0x%x flags: 0x%x\n",
8479                 mode->crtc_clock,
8480                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8481                 mode->crtc_hsync_end, mode->crtc_htotal,
8482                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8483                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8484 }
8485
8486 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8487                                    struct intel_crtc_config *pipe_config,
8488                                    const char *context)
8489 {
8490         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8491                       context, pipe_name(crtc->pipe));
8492
8493         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8494         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8495                       pipe_config->pipe_bpp, pipe_config->dither);
8496         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8497                       pipe_config->has_pch_encoder,
8498                       pipe_config->fdi_lanes,
8499                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8500                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8501                       pipe_config->fdi_m_n.tu);
8502         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8503                       pipe_config->has_dp_encoder,
8504                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8505                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8506                       pipe_config->dp_m_n.tu);
8507         DRM_DEBUG_KMS("requested mode:\n");
8508         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8509         DRM_DEBUG_KMS("adjusted mode:\n");
8510         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8511         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8512         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8513         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8514                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8515         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8516                       pipe_config->gmch_pfit.control,
8517                       pipe_config->gmch_pfit.pgm_ratios,
8518                       pipe_config->gmch_pfit.lvds_border_bits);
8519         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8520                       pipe_config->pch_pfit.pos,
8521                       pipe_config->pch_pfit.size,
8522                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8523         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8524         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8525 }
8526
8527 static bool check_encoder_cloning(struct drm_crtc *crtc)
8528 {
8529         int num_encoders = 0;
8530         bool uncloneable_encoders = false;
8531         struct intel_encoder *encoder;
8532
8533         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8534                             base.head) {
8535                 if (&encoder->new_crtc->base != crtc)
8536                         continue;
8537
8538                 num_encoders++;
8539                 if (!encoder->cloneable)
8540                         uncloneable_encoders = true;
8541         }
8542
8543         return !(num_encoders > 1 && uncloneable_encoders);
8544 }
8545
8546 static struct intel_crtc_config *
8547 intel_modeset_pipe_config(struct drm_crtc *crtc,
8548                           struct drm_framebuffer *fb,
8549                           struct drm_display_mode *mode)
8550 {
8551         struct drm_device *dev = crtc->dev;
8552         struct intel_encoder *encoder;
8553         struct intel_crtc_config *pipe_config;
8554         int plane_bpp, ret = -EINVAL;
8555         bool retry = true;
8556
8557         if (!check_encoder_cloning(crtc)) {
8558                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8559                 return ERR_PTR(-EINVAL);
8560         }
8561
8562         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8563         if (!pipe_config)
8564                 return ERR_PTR(-ENOMEM);
8565
8566         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8567         drm_mode_copy(&pipe_config->requested_mode, mode);
8568
8569         pipe_config->cpu_transcoder =
8570                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8571         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8572
8573         /*
8574          * Sanitize sync polarity flags based on requested ones. If neither
8575          * positive or negative polarity is requested, treat this as meaning
8576          * negative polarity.
8577          */
8578         if (!(pipe_config->adjusted_mode.flags &
8579               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8580                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8581
8582         if (!(pipe_config->adjusted_mode.flags &
8583               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8584                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8585
8586         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8587          * plane pixel format and any sink constraints into account. Returns the
8588          * source plane bpp so that dithering can be selected on mismatches
8589          * after encoders and crtc also have had their say. */
8590         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8591                                               fb, pipe_config);
8592         if (plane_bpp < 0)
8593                 goto fail;
8594
8595         /*
8596          * Determine the real pipe dimensions. Note that stereo modes can
8597          * increase the actual pipe size due to the frame doubling and
8598          * insertion of additional space for blanks between the frame. This
8599          * is stored in the crtc timings. We use the requested mode to do this
8600          * computation to clearly distinguish it from the adjusted mode, which
8601          * can be changed by the connectors in the below retry loop.
8602          */
8603         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8604         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8605         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8606
8607 encoder_retry:
8608         /* Ensure the port clock defaults are reset when retrying. */
8609         pipe_config->port_clock = 0;
8610         pipe_config->pixel_multiplier = 1;
8611
8612         /* Fill in default crtc timings, allow encoders to overwrite them. */
8613         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8614
8615         /* Pass our mode to the connectors and the CRTC to give them a chance to
8616          * adjust it according to limitations or connector properties, and also
8617          * a chance to reject the mode entirely.
8618          */
8619         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8620                             base.head) {
8621
8622                 if (&encoder->new_crtc->base != crtc)
8623                         continue;
8624
8625                 if (!(encoder->compute_config(encoder, pipe_config))) {
8626                         DRM_DEBUG_KMS("Encoder config failure\n");
8627                         goto fail;
8628                 }
8629         }
8630
8631         /* Set default port clock if not overwritten by the encoder. Needs to be
8632          * done afterwards in case the encoder adjusts the mode. */
8633         if (!pipe_config->port_clock)
8634                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8635                         * pipe_config->pixel_multiplier;
8636
8637         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8638         if (ret < 0) {
8639                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8640                 goto fail;
8641         }
8642
8643         if (ret == RETRY) {
8644                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8645                         ret = -EINVAL;
8646                         goto fail;
8647                 }
8648
8649                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8650                 retry = false;
8651                 goto encoder_retry;
8652         }
8653
8654         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8655         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8656                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8657
8658         return pipe_config;
8659 fail:
8660         kfree(pipe_config);
8661         return ERR_PTR(ret);
8662 }
8663
8664 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8665  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8666 static void
8667 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8668                              unsigned *prepare_pipes, unsigned *disable_pipes)
8669 {
8670         struct intel_crtc *intel_crtc;
8671         struct drm_device *dev = crtc->dev;
8672         struct intel_encoder *encoder;
8673         struct intel_connector *connector;
8674         struct drm_crtc *tmp_crtc;
8675
8676         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8677
8678         /* Check which crtcs have changed outputs connected to them, these need
8679          * to be part of the prepare_pipes mask. We don't (yet) support global
8680          * modeset across multiple crtcs, so modeset_pipes will only have one
8681          * bit set at most. */
8682         list_for_each_entry(connector, &dev->mode_config.connector_list,
8683                             base.head) {
8684                 if (connector->base.encoder == &connector->new_encoder->base)
8685                         continue;
8686
8687                 if (connector->base.encoder) {
8688                         tmp_crtc = connector->base.encoder->crtc;
8689
8690                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8691                 }
8692
8693                 if (connector->new_encoder)
8694                         *prepare_pipes |=
8695                                 1 << connector->new_encoder->new_crtc->pipe;
8696         }
8697
8698         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8699                             base.head) {
8700                 if (encoder->base.crtc == &encoder->new_crtc->base)
8701                         continue;
8702
8703                 if (encoder->base.crtc) {
8704                         tmp_crtc = encoder->base.crtc;
8705
8706                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8707                 }
8708
8709                 if (encoder->new_crtc)
8710                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8711         }
8712
8713         /* Check for any pipes that will be fully disabled ... */
8714         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8715                             base.head) {
8716                 bool used = false;
8717
8718                 /* Don't try to disable disabled crtcs. */
8719                 if (!intel_crtc->base.enabled)
8720                         continue;
8721
8722                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8723                                     base.head) {
8724                         if (encoder->new_crtc == intel_crtc)
8725                                 used = true;
8726                 }
8727
8728                 if (!used)
8729                         *disable_pipes |= 1 << intel_crtc->pipe;
8730         }
8731
8732
8733         /* set_mode is also used to update properties on life display pipes. */
8734         intel_crtc = to_intel_crtc(crtc);
8735         if (crtc->enabled)
8736                 *prepare_pipes |= 1 << intel_crtc->pipe;
8737
8738         /*
8739          * For simplicity do a full modeset on any pipe where the output routing
8740          * changed. We could be more clever, but that would require us to be
8741          * more careful with calling the relevant encoder->mode_set functions.
8742          */
8743         if (*prepare_pipes)
8744                 *modeset_pipes = *prepare_pipes;
8745
8746         /* ... and mask these out. */
8747         *modeset_pipes &= ~(*disable_pipes);
8748         *prepare_pipes &= ~(*disable_pipes);
8749
8750         /*
8751          * HACK: We don't (yet) fully support global modesets. intel_set_config
8752          * obies this rule, but the modeset restore mode of
8753          * intel_modeset_setup_hw_state does not.
8754          */
8755         *modeset_pipes &= 1 << intel_crtc->pipe;
8756         *prepare_pipes &= 1 << intel_crtc->pipe;
8757
8758         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8759                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8760 }
8761
8762 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8763 {
8764         struct drm_encoder *encoder;
8765         struct drm_device *dev = crtc->dev;
8766
8767         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8768                 if (encoder->crtc == crtc)
8769                         return true;
8770
8771         return false;
8772 }
8773
8774 static void
8775 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8776 {
8777         struct intel_encoder *intel_encoder;
8778         struct intel_crtc *intel_crtc;
8779         struct drm_connector *connector;
8780
8781         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8782                             base.head) {
8783                 if (!intel_encoder->base.crtc)
8784                         continue;
8785
8786                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8787
8788                 if (prepare_pipes & (1 << intel_crtc->pipe))
8789                         intel_encoder->connectors_active = false;
8790         }
8791
8792         intel_modeset_commit_output_state(dev);
8793
8794         /* Update computed state. */
8795         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8796                             base.head) {
8797                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8798         }
8799
8800         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8801                 if (!connector->encoder || !connector->encoder->crtc)
8802                         continue;
8803
8804                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8805
8806                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8807                         struct drm_property *dpms_property =
8808                                 dev->mode_config.dpms_property;
8809
8810                         connector->dpms = DRM_MODE_DPMS_ON;
8811                         drm_object_property_set_value(&connector->base,
8812                                                          dpms_property,
8813                                                          DRM_MODE_DPMS_ON);
8814
8815                         intel_encoder = to_intel_encoder(connector->encoder);
8816                         intel_encoder->connectors_active = true;
8817                 }
8818         }
8819
8820 }
8821
8822 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8823 {
8824         int diff;
8825
8826         if (clock1 == clock2)
8827                 return true;
8828
8829         if (!clock1 || !clock2)
8830                 return false;
8831
8832         diff = abs(clock1 - clock2);
8833
8834         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8835                 return true;
8836
8837         return false;
8838 }
8839
8840 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8841         list_for_each_entry((intel_crtc), \
8842                             &(dev)->mode_config.crtc_list, \
8843                             base.head) \
8844                 if (mask & (1 <<(intel_crtc)->pipe))
8845
8846 static bool
8847 intel_pipe_config_compare(struct drm_device *dev,
8848                           struct intel_crtc_config *current_config,
8849                           struct intel_crtc_config *pipe_config)
8850 {
8851 #define PIPE_CONF_CHECK_X(name) \
8852         if (current_config->name != pipe_config->name) { \
8853                 DRM_ERROR("mismatch in " #name " " \
8854                           "(expected 0x%08x, found 0x%08x)\n", \
8855                           current_config->name, \
8856                           pipe_config->name); \
8857                 return false; \
8858         }
8859
8860 #define PIPE_CONF_CHECK_I(name) \
8861         if (current_config->name != pipe_config->name) { \
8862                 DRM_ERROR("mismatch in " #name " " \
8863                           "(expected %i, found %i)\n", \
8864                           current_config->name, \
8865                           pipe_config->name); \
8866                 return false; \
8867         }
8868
8869 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8870         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8871                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8872                           "(expected %i, found %i)\n", \
8873                           current_config->name & (mask), \
8874                           pipe_config->name & (mask)); \
8875                 return false; \
8876         }
8877
8878 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8879         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8880                 DRM_ERROR("mismatch in " #name " " \
8881                           "(expected %i, found %i)\n", \
8882                           current_config->name, \
8883                           pipe_config->name); \
8884                 return false; \
8885         }
8886
8887 #define PIPE_CONF_QUIRK(quirk)  \
8888         ((current_config->quirks | pipe_config->quirks) & (quirk))
8889
8890         PIPE_CONF_CHECK_I(cpu_transcoder);
8891
8892         PIPE_CONF_CHECK_I(has_pch_encoder);
8893         PIPE_CONF_CHECK_I(fdi_lanes);
8894         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8895         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8896         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8897         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8898         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8899
8900         PIPE_CONF_CHECK_I(has_dp_encoder);
8901         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8902         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8903         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8904         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8905         PIPE_CONF_CHECK_I(dp_m_n.tu);
8906
8907         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8908         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8909         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8910         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8911         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8912         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8913
8914         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8915         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8916         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8917         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8918         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8919         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8920
8921         PIPE_CONF_CHECK_I(pixel_multiplier);
8922
8923         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8924                               DRM_MODE_FLAG_INTERLACE);
8925
8926         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8927                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8928                                       DRM_MODE_FLAG_PHSYNC);
8929                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8930                                       DRM_MODE_FLAG_NHSYNC);
8931                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8932                                       DRM_MODE_FLAG_PVSYNC);
8933                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8934                                       DRM_MODE_FLAG_NVSYNC);
8935         }
8936
8937         PIPE_CONF_CHECK_I(pipe_src_w);
8938         PIPE_CONF_CHECK_I(pipe_src_h);
8939
8940         PIPE_CONF_CHECK_I(gmch_pfit.control);
8941         /* pfit ratios are autocomputed by the hw on gen4+ */
8942         if (INTEL_INFO(dev)->gen < 4)
8943                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8944         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8945         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8946         if (current_config->pch_pfit.enabled) {
8947                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8948                 PIPE_CONF_CHECK_I(pch_pfit.size);
8949         }
8950
8951         PIPE_CONF_CHECK_I(ips_enabled);
8952
8953         PIPE_CONF_CHECK_I(double_wide);
8954
8955         PIPE_CONF_CHECK_I(shared_dpll);
8956         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8957         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8958         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8959         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8960
8961         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8962                 PIPE_CONF_CHECK_I(pipe_bpp);
8963
8964         if (!IS_HASWELL(dev)) {
8965                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8966                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8967         }
8968
8969 #undef PIPE_CONF_CHECK_X
8970 #undef PIPE_CONF_CHECK_I
8971 #undef PIPE_CONF_CHECK_FLAGS
8972 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8973 #undef PIPE_CONF_QUIRK
8974
8975         return true;
8976 }
8977
8978 static void
8979 check_connector_state(struct drm_device *dev)
8980 {
8981         struct intel_connector *connector;
8982
8983         list_for_each_entry(connector, &dev->mode_config.connector_list,
8984                             base.head) {
8985                 /* This also checks the encoder/connector hw state with the
8986                  * ->get_hw_state callbacks. */
8987                 intel_connector_check_state(connector);
8988
8989                 WARN(&connector->new_encoder->base != connector->base.encoder,
8990                      "connector's staged encoder doesn't match current encoder\n");
8991         }
8992 }
8993
8994 static void
8995 check_encoder_state(struct drm_device *dev)
8996 {
8997         struct intel_encoder *encoder;
8998         struct intel_connector *connector;
8999
9000         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9001                             base.head) {
9002                 bool enabled = false;
9003                 bool active = false;
9004                 enum pipe pipe, tracked_pipe;
9005
9006                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9007                               encoder->base.base.id,
9008                               drm_get_encoder_name(&encoder->base));
9009
9010                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9011                      "encoder's stage crtc doesn't match current crtc\n");
9012                 WARN(encoder->connectors_active && !encoder->base.crtc,
9013                      "encoder's active_connectors set, but no crtc\n");
9014
9015                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9016                                     base.head) {
9017                         if (connector->base.encoder != &encoder->base)
9018                                 continue;
9019                         enabled = true;
9020                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9021                                 active = true;
9022                 }
9023                 WARN(!!encoder->base.crtc != enabled,
9024                      "encoder's enabled state mismatch "
9025                      "(expected %i, found %i)\n",
9026                      !!encoder->base.crtc, enabled);
9027                 WARN(active && !encoder->base.crtc,
9028                      "active encoder with no crtc\n");
9029
9030                 WARN(encoder->connectors_active != active,
9031                      "encoder's computed active state doesn't match tracked active state "
9032                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9033
9034                 active = encoder->get_hw_state(encoder, &pipe);
9035                 WARN(active != encoder->connectors_active,
9036                      "encoder's hw state doesn't match sw tracking "
9037                      "(expected %i, found %i)\n",
9038                      encoder->connectors_active, active);
9039
9040                 if (!encoder->base.crtc)
9041                         continue;
9042
9043                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9044                 WARN(active && pipe != tracked_pipe,
9045                      "active encoder's pipe doesn't match"
9046                      "(expected %i, found %i)\n",
9047                      tracked_pipe, pipe);
9048
9049         }
9050 }
9051
9052 static void
9053 check_crtc_state(struct drm_device *dev)
9054 {
9055         drm_i915_private_t *dev_priv = dev->dev_private;
9056         struct intel_crtc *crtc;
9057         struct intel_encoder *encoder;
9058         struct intel_crtc_config pipe_config;
9059
9060         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9061                             base.head) {
9062                 bool enabled = false;
9063                 bool active = false;
9064
9065                 memset(&pipe_config, 0, sizeof(pipe_config));
9066
9067                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9068                               crtc->base.base.id);
9069
9070                 WARN(crtc->active && !crtc->base.enabled,
9071                      "active crtc, but not enabled in sw tracking\n");
9072
9073                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9074                                     base.head) {
9075                         if (encoder->base.crtc != &crtc->base)
9076                                 continue;
9077                         enabled = true;
9078                         if (encoder->connectors_active)
9079                                 active = true;
9080                 }
9081
9082                 WARN(active != crtc->active,
9083                      "crtc's computed active state doesn't match tracked active state "
9084                      "(expected %i, found %i)\n", active, crtc->active);
9085                 WARN(enabled != crtc->base.enabled,
9086                      "crtc's computed enabled state doesn't match tracked enabled state "
9087                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9088
9089                 active = dev_priv->display.get_pipe_config(crtc,
9090                                                            &pipe_config);
9091
9092                 /* hw state is inconsistent with the pipe A quirk */
9093                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9094                         active = crtc->active;
9095
9096                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9097                                     base.head) {
9098                         enum pipe pipe;
9099                         if (encoder->base.crtc != &crtc->base)
9100                                 continue;
9101                         if (encoder->get_config &&
9102                             encoder->get_hw_state(encoder, &pipe))
9103                                 encoder->get_config(encoder, &pipe_config);
9104                 }
9105
9106                 WARN(crtc->active != active,
9107                      "crtc active state doesn't match with hw state "
9108                      "(expected %i, found %i)\n", crtc->active, active);
9109
9110                 if (active &&
9111                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9112                         WARN(1, "pipe state doesn't match!\n");
9113                         intel_dump_pipe_config(crtc, &pipe_config,
9114                                                "[hw state]");
9115                         intel_dump_pipe_config(crtc, &crtc->config,
9116                                                "[sw state]");
9117                 }
9118         }
9119 }
9120
9121 static void
9122 check_shared_dpll_state(struct drm_device *dev)
9123 {
9124         drm_i915_private_t *dev_priv = dev->dev_private;
9125         struct intel_crtc *crtc;
9126         struct intel_dpll_hw_state dpll_hw_state;
9127         int i;
9128
9129         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9130                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9131                 int enabled_crtcs = 0, active_crtcs = 0;
9132                 bool active;
9133
9134                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9135
9136                 DRM_DEBUG_KMS("%s\n", pll->name);
9137
9138                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9139
9140                 WARN(pll->active > pll->refcount,
9141                      "more active pll users than references: %i vs %i\n",
9142                      pll->active, pll->refcount);
9143                 WARN(pll->active && !pll->on,
9144                      "pll in active use but not on in sw tracking\n");
9145                 WARN(pll->on && !pll->active,
9146                      "pll in on but not on in use in sw tracking\n");
9147                 WARN(pll->on != active,
9148                      "pll on state mismatch (expected %i, found %i)\n",
9149                      pll->on, active);
9150
9151                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9152                                     base.head) {
9153                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9154                                 enabled_crtcs++;
9155                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9156                                 active_crtcs++;
9157                 }
9158                 WARN(pll->active != active_crtcs,
9159                      "pll active crtcs mismatch (expected %i, found %i)\n",
9160                      pll->active, active_crtcs);
9161                 WARN(pll->refcount != enabled_crtcs,
9162                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9163                      pll->refcount, enabled_crtcs);
9164
9165                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9166                                        sizeof(dpll_hw_state)),
9167                      "pll hw state mismatch\n");
9168         }
9169 }
9170
9171 void
9172 intel_modeset_check_state(struct drm_device *dev)
9173 {
9174         check_connector_state(dev);
9175         check_encoder_state(dev);
9176         check_crtc_state(dev);
9177         check_shared_dpll_state(dev);
9178 }
9179
9180 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9181                                      int dotclock)
9182 {
9183         /*
9184          * FDI already provided one idea for the dotclock.
9185          * Yell if the encoder disagrees.
9186          */
9187         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9188              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9189              pipe_config->adjusted_mode.crtc_clock, dotclock);
9190 }
9191
9192 static int __intel_set_mode(struct drm_crtc *crtc,
9193                             struct drm_display_mode *mode,
9194                             int x, int y, struct drm_framebuffer *fb)
9195 {
9196         struct drm_device *dev = crtc->dev;
9197         drm_i915_private_t *dev_priv = dev->dev_private;
9198         struct drm_display_mode *saved_mode, *saved_hwmode;
9199         struct intel_crtc_config *pipe_config = NULL;
9200         struct intel_crtc *intel_crtc;
9201         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9202         int ret = 0;
9203
9204         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9205         if (!saved_mode)
9206                 return -ENOMEM;
9207         saved_hwmode = saved_mode + 1;
9208
9209         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9210                                      &prepare_pipes, &disable_pipes);
9211
9212         *saved_hwmode = crtc->hwmode;
9213         *saved_mode = crtc->mode;
9214
9215         /* Hack: Because we don't (yet) support global modeset on multiple
9216          * crtcs, we don't keep track of the new mode for more than one crtc.
9217          * Hence simply check whether any bit is set in modeset_pipes in all the
9218          * pieces of code that are not yet converted to deal with mutliple crtcs
9219          * changing their mode at the same time. */
9220         if (modeset_pipes) {
9221                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9222                 if (IS_ERR(pipe_config)) {
9223                         ret = PTR_ERR(pipe_config);
9224                         pipe_config = NULL;
9225
9226                         goto out;
9227                 }
9228                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9229                                        "[modeset]");
9230         }
9231
9232         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9233                 intel_crtc_disable(&intel_crtc->base);
9234
9235         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9236                 if (intel_crtc->base.enabled)
9237                         dev_priv->display.crtc_disable(&intel_crtc->base);
9238         }
9239
9240         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9241          * to set it here already despite that we pass it down the callchain.
9242          */
9243         if (modeset_pipes) {
9244                 crtc->mode = *mode;
9245                 /* mode_set/enable/disable functions rely on a correct pipe
9246                  * config. */
9247                 to_intel_crtc(crtc)->config = *pipe_config;
9248         }
9249
9250         /* Only after disabling all output pipelines that will be changed can we
9251          * update the the output configuration. */
9252         intel_modeset_update_state(dev, prepare_pipes);
9253
9254         if (dev_priv->display.modeset_global_resources)
9255                 dev_priv->display.modeset_global_resources(dev);
9256
9257         /* Set up the DPLL and any encoders state that needs to adjust or depend
9258          * on the DPLL.
9259          */
9260         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9261                 ret = intel_crtc_mode_set(&intel_crtc->base,
9262                                           x, y, fb);
9263                 if (ret)
9264                         goto done;
9265         }
9266
9267         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9268         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9269                 dev_priv->display.crtc_enable(&intel_crtc->base);
9270
9271         if (modeset_pipes) {
9272                 /* Store real post-adjustment hardware mode. */
9273                 crtc->hwmode = pipe_config->adjusted_mode;
9274
9275                 /* Calculate and store various constants which
9276                  * are later needed by vblank and swap-completion
9277                  * timestamping. They are derived from true hwmode.
9278                  */
9279                 drm_calc_timestamping_constants(crtc);
9280         }
9281
9282         /* FIXME: add subpixel order */
9283 done:
9284         if (ret && crtc->enabled) {
9285                 crtc->hwmode = *saved_hwmode;
9286                 crtc->mode = *saved_mode;
9287         }
9288
9289 out:
9290         kfree(pipe_config);
9291         kfree(saved_mode);
9292         return ret;
9293 }
9294
9295 static int intel_set_mode(struct drm_crtc *crtc,
9296                           struct drm_display_mode *mode,
9297                           int x, int y, struct drm_framebuffer *fb)
9298 {
9299         int ret;
9300
9301         ret = __intel_set_mode(crtc, mode, x, y, fb);
9302
9303         if (ret == 0)
9304                 intel_modeset_check_state(crtc->dev);
9305
9306         return ret;
9307 }
9308
9309 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9310 {
9311         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9312 }
9313
9314 #undef for_each_intel_crtc_masked
9315
9316 static void intel_set_config_free(struct intel_set_config *config)
9317 {
9318         if (!config)
9319                 return;
9320
9321         kfree(config->save_connector_encoders);
9322         kfree(config->save_encoder_crtcs);
9323         kfree(config);
9324 }
9325
9326 static int intel_set_config_save_state(struct drm_device *dev,
9327                                        struct intel_set_config *config)
9328 {
9329         struct drm_encoder *encoder;
9330         struct drm_connector *connector;
9331         int count;
9332
9333         config->save_encoder_crtcs =
9334                 kcalloc(dev->mode_config.num_encoder,
9335                         sizeof(struct drm_crtc *), GFP_KERNEL);
9336         if (!config->save_encoder_crtcs)
9337                 return -ENOMEM;
9338
9339         config->save_connector_encoders =
9340                 kcalloc(dev->mode_config.num_connector,
9341                         sizeof(struct drm_encoder *), GFP_KERNEL);
9342         if (!config->save_connector_encoders)
9343                 return -ENOMEM;
9344
9345         /* Copy data. Note that driver private data is not affected.
9346          * Should anything bad happen only the expected state is
9347          * restored, not the drivers personal bookkeeping.
9348          */
9349         count = 0;
9350         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9351                 config->save_encoder_crtcs[count++] = encoder->crtc;
9352         }
9353
9354         count = 0;
9355         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9356                 config->save_connector_encoders[count++] = connector->encoder;
9357         }
9358
9359         return 0;
9360 }
9361
9362 static void intel_set_config_restore_state(struct drm_device *dev,
9363                                            struct intel_set_config *config)
9364 {
9365         struct intel_encoder *encoder;
9366         struct intel_connector *connector;
9367         int count;
9368
9369         count = 0;
9370         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9371                 encoder->new_crtc =
9372                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9373         }
9374
9375         count = 0;
9376         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9377                 connector->new_encoder =
9378                         to_intel_encoder(config->save_connector_encoders[count++]);
9379         }
9380 }
9381
9382 static bool
9383 is_crtc_connector_off(struct drm_mode_set *set)
9384 {
9385         int i;
9386
9387         if (set->num_connectors == 0)
9388                 return false;
9389
9390         if (WARN_ON(set->connectors == NULL))
9391                 return false;
9392
9393         for (i = 0; i < set->num_connectors; i++)
9394                 if (set->connectors[i]->encoder &&
9395                     set->connectors[i]->encoder->crtc == set->crtc &&
9396                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9397                         return true;
9398
9399         return false;
9400 }
9401
9402 static void
9403 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9404                                       struct intel_set_config *config)
9405 {
9406
9407         /* We should be able to check here if the fb has the same properties
9408          * and then just flip_or_move it */
9409         if (is_crtc_connector_off(set)) {
9410                 config->mode_changed = true;
9411         } else if (set->crtc->fb != set->fb) {
9412                 /* If we have no fb then treat it as a full mode set */
9413                 if (set->crtc->fb == NULL) {
9414                         struct intel_crtc *intel_crtc =
9415                                 to_intel_crtc(set->crtc);
9416
9417                         if (intel_crtc->active && i915_fastboot) {
9418                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9419                                 config->fb_changed = true;
9420                         } else {
9421                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9422                                 config->mode_changed = true;
9423                         }
9424                 } else if (set->fb == NULL) {
9425                         config->mode_changed = true;
9426                 } else if (set->fb->pixel_format !=
9427                            set->crtc->fb->pixel_format) {
9428                         config->mode_changed = true;
9429                 } else {
9430                         config->fb_changed = true;
9431                 }
9432         }
9433
9434         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9435                 config->fb_changed = true;
9436
9437         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9438                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9439                 drm_mode_debug_printmodeline(&set->crtc->mode);
9440                 drm_mode_debug_printmodeline(set->mode);
9441                 config->mode_changed = true;
9442         }
9443
9444         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9445                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9446 }
9447
9448 static int
9449 intel_modeset_stage_output_state(struct drm_device *dev,
9450                                  struct drm_mode_set *set,
9451                                  struct intel_set_config *config)
9452 {
9453         struct drm_crtc *new_crtc;
9454         struct intel_connector *connector;
9455         struct intel_encoder *encoder;
9456         int ro;
9457
9458         /* The upper layers ensure that we either disable a crtc or have a list
9459          * of connectors. For paranoia, double-check this. */
9460         WARN_ON(!set->fb && (set->num_connectors != 0));
9461         WARN_ON(set->fb && (set->num_connectors == 0));
9462
9463         list_for_each_entry(connector, &dev->mode_config.connector_list,
9464                             base.head) {
9465                 /* Otherwise traverse passed in connector list and get encoders
9466                  * for them. */
9467                 for (ro = 0; ro < set->num_connectors; ro++) {
9468                         if (set->connectors[ro] == &connector->base) {
9469                                 connector->new_encoder = connector->encoder;
9470                                 break;
9471                         }
9472                 }
9473
9474                 /* If we disable the crtc, disable all its connectors. Also, if
9475                  * the connector is on the changing crtc but not on the new
9476                  * connector list, disable it. */
9477                 if ((!set->fb || ro == set->num_connectors) &&
9478                     connector->base.encoder &&
9479                     connector->base.encoder->crtc == set->crtc) {
9480                         connector->new_encoder = NULL;
9481
9482                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9483                                 connector->base.base.id,
9484                                 drm_get_connector_name(&connector->base));
9485                 }
9486
9487
9488                 if (&connector->new_encoder->base != connector->base.encoder) {
9489                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9490                         config->mode_changed = true;
9491                 }
9492         }
9493         /* connector->new_encoder is now updated for all connectors. */
9494
9495         /* Update crtc of enabled connectors. */
9496         list_for_each_entry(connector, &dev->mode_config.connector_list,
9497                             base.head) {
9498                 if (!connector->new_encoder)
9499                         continue;
9500
9501                 new_crtc = connector->new_encoder->base.crtc;
9502
9503                 for (ro = 0; ro < set->num_connectors; ro++) {
9504                         if (set->connectors[ro] == &connector->base)
9505                                 new_crtc = set->crtc;
9506                 }
9507
9508                 /* Make sure the new CRTC will work with the encoder */
9509                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9510                                            new_crtc)) {
9511                         return -EINVAL;
9512                 }
9513                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9514
9515                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9516                         connector->base.base.id,
9517                         drm_get_connector_name(&connector->base),
9518                         new_crtc->base.id);
9519         }
9520
9521         /* Check for any encoders that needs to be disabled. */
9522         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9523                             base.head) {
9524                 list_for_each_entry(connector,
9525                                     &dev->mode_config.connector_list,
9526                                     base.head) {
9527                         if (connector->new_encoder == encoder) {
9528                                 WARN_ON(!connector->new_encoder->new_crtc);
9529
9530                                 goto next_encoder;
9531                         }
9532                 }
9533                 encoder->new_crtc = NULL;
9534 next_encoder:
9535                 /* Only now check for crtc changes so we don't miss encoders
9536                  * that will be disabled. */
9537                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9538                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9539                         config->mode_changed = true;
9540                 }
9541         }
9542         /* Now we've also updated encoder->new_crtc for all encoders. */
9543
9544         return 0;
9545 }
9546
9547 static int intel_crtc_set_config(struct drm_mode_set *set)
9548 {
9549         struct drm_device *dev;
9550         struct drm_mode_set save_set;
9551         struct intel_set_config *config;
9552         int ret;
9553
9554         BUG_ON(!set);
9555         BUG_ON(!set->crtc);
9556         BUG_ON(!set->crtc->helper_private);
9557
9558         /* Enforce sane interface api - has been abused by the fb helper. */
9559         BUG_ON(!set->mode && set->fb);
9560         BUG_ON(set->fb && set->num_connectors == 0);
9561
9562         if (set->fb) {
9563                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9564                                 set->crtc->base.id, set->fb->base.id,
9565                                 (int)set->num_connectors, set->x, set->y);
9566         } else {
9567                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9568         }
9569
9570         dev = set->crtc->dev;
9571
9572         ret = -ENOMEM;
9573         config = kzalloc(sizeof(*config), GFP_KERNEL);
9574         if (!config)
9575                 goto out_config;
9576
9577         ret = intel_set_config_save_state(dev, config);
9578         if (ret)
9579                 goto out_config;
9580
9581         save_set.crtc = set->crtc;
9582         save_set.mode = &set->crtc->mode;
9583         save_set.x = set->crtc->x;
9584         save_set.y = set->crtc->y;
9585         save_set.fb = set->crtc->fb;
9586
9587         /* Compute whether we need a full modeset, only an fb base update or no
9588          * change at all. In the future we might also check whether only the
9589          * mode changed, e.g. for LVDS where we only change the panel fitter in
9590          * such cases. */
9591         intel_set_config_compute_mode_changes(set, config);
9592
9593         ret = intel_modeset_stage_output_state(dev, set, config);
9594         if (ret)
9595                 goto fail;
9596
9597         if (config->mode_changed) {
9598                 ret = intel_set_mode(set->crtc, set->mode,
9599                                      set->x, set->y, set->fb);
9600         } else if (config->fb_changed) {
9601                 intel_crtc_wait_for_pending_flips(set->crtc);
9602
9603                 ret = intel_pipe_set_base(set->crtc,
9604                                           set->x, set->y, set->fb);
9605         }
9606
9607         if (ret) {
9608                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9609                               set->crtc->base.id, ret);
9610 fail:
9611                 intel_set_config_restore_state(dev, config);
9612
9613                 /* Try to restore the config */
9614                 if (config->mode_changed &&
9615                     intel_set_mode(save_set.crtc, save_set.mode,
9616                                    save_set.x, save_set.y, save_set.fb))
9617                         DRM_ERROR("failed to restore config after modeset failure\n");
9618         }
9619
9620 out_config:
9621         intel_set_config_free(config);
9622         return ret;
9623 }
9624
9625 static const struct drm_crtc_funcs intel_crtc_funcs = {
9626         .cursor_set = intel_crtc_cursor_set,
9627         .cursor_move = intel_crtc_cursor_move,
9628         .gamma_set = intel_crtc_gamma_set,
9629         .set_config = intel_crtc_set_config,
9630         .destroy = intel_crtc_destroy,
9631         .page_flip = intel_crtc_page_flip,
9632 };
9633
9634 static void intel_cpu_pll_init(struct drm_device *dev)
9635 {
9636         if (HAS_DDI(dev))
9637                 intel_ddi_pll_init(dev);
9638 }
9639
9640 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9641                                       struct intel_shared_dpll *pll,
9642                                       struct intel_dpll_hw_state *hw_state)
9643 {
9644         uint32_t val;
9645
9646         val = I915_READ(PCH_DPLL(pll->id));
9647         hw_state->dpll = val;
9648         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9649         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9650
9651         return val & DPLL_VCO_ENABLE;
9652 }
9653
9654 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9655                                   struct intel_shared_dpll *pll)
9656 {
9657         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9658         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9659 }
9660
9661 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9662                                 struct intel_shared_dpll *pll)
9663 {
9664         /* PCH refclock must be enabled first */
9665         assert_pch_refclk_enabled(dev_priv);
9666
9667         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9668
9669         /* Wait for the clocks to stabilize. */
9670         POSTING_READ(PCH_DPLL(pll->id));
9671         udelay(150);
9672
9673         /* The pixel multiplier can only be updated once the
9674          * DPLL is enabled and the clocks are stable.
9675          *
9676          * So write it again.
9677          */
9678         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9679         POSTING_READ(PCH_DPLL(pll->id));
9680         udelay(200);
9681 }
9682
9683 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9684                                  struct intel_shared_dpll *pll)
9685 {
9686         struct drm_device *dev = dev_priv->dev;
9687         struct intel_crtc *crtc;
9688
9689         /* Make sure no transcoder isn't still depending on us. */
9690         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9691                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9692                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9693         }
9694
9695         I915_WRITE(PCH_DPLL(pll->id), 0);
9696         POSTING_READ(PCH_DPLL(pll->id));
9697         udelay(200);
9698 }
9699
9700 static char *ibx_pch_dpll_names[] = {
9701         "PCH DPLL A",
9702         "PCH DPLL B",
9703 };
9704
9705 static void ibx_pch_dpll_init(struct drm_device *dev)
9706 {
9707         struct drm_i915_private *dev_priv = dev->dev_private;
9708         int i;
9709
9710         dev_priv->num_shared_dpll = 2;
9711
9712         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9713                 dev_priv->shared_dplls[i].id = i;
9714                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9715                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9716                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9717                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9718                 dev_priv->shared_dplls[i].get_hw_state =
9719                         ibx_pch_dpll_get_hw_state;
9720         }
9721 }
9722
9723 static void intel_shared_dpll_init(struct drm_device *dev)
9724 {
9725         struct drm_i915_private *dev_priv = dev->dev_private;
9726
9727         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9728                 ibx_pch_dpll_init(dev);
9729         else
9730                 dev_priv->num_shared_dpll = 0;
9731
9732         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9733         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9734                       dev_priv->num_shared_dpll);
9735 }
9736
9737 static void intel_crtc_init(struct drm_device *dev, int pipe)
9738 {
9739         drm_i915_private_t *dev_priv = dev->dev_private;
9740         struct intel_crtc *intel_crtc;
9741         int i;
9742
9743         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9744         if (intel_crtc == NULL)
9745                 return;
9746
9747         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9748
9749         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9750         for (i = 0; i < 256; i++) {
9751                 intel_crtc->lut_r[i] = i;
9752                 intel_crtc->lut_g[i] = i;
9753                 intel_crtc->lut_b[i] = i;
9754         }
9755
9756         /* Swap pipes & planes for FBC on pre-965 */
9757         intel_crtc->pipe = pipe;
9758         intel_crtc->plane = pipe;
9759         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9760                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9761                 intel_crtc->plane = !pipe;
9762         }
9763
9764         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9765                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9766         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9767         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9768
9769         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9770 }
9771
9772 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9773                                 struct drm_file *file)
9774 {
9775         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9776         struct drm_mode_object *drmmode_obj;
9777         struct intel_crtc *crtc;
9778
9779         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9780                 return -ENODEV;
9781
9782         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9783                         DRM_MODE_OBJECT_CRTC);
9784
9785         if (!drmmode_obj) {
9786                 DRM_ERROR("no such CRTC id\n");
9787                 return -EINVAL;
9788         }
9789
9790         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9791         pipe_from_crtc_id->pipe = crtc->pipe;
9792
9793         return 0;
9794 }
9795
9796 static int intel_encoder_clones(struct intel_encoder *encoder)
9797 {
9798         struct drm_device *dev = encoder->base.dev;
9799         struct intel_encoder *source_encoder;
9800         int index_mask = 0;
9801         int entry = 0;
9802
9803         list_for_each_entry(source_encoder,
9804                             &dev->mode_config.encoder_list, base.head) {
9805
9806                 if (encoder == source_encoder)
9807                         index_mask |= (1 << entry);
9808
9809                 /* Intel hw has only one MUX where enocoders could be cloned. */
9810                 if (encoder->cloneable && source_encoder->cloneable)
9811                         index_mask |= (1 << entry);
9812
9813                 entry++;
9814         }
9815
9816         return index_mask;
9817 }
9818
9819 static bool has_edp_a(struct drm_device *dev)
9820 {
9821         struct drm_i915_private *dev_priv = dev->dev_private;
9822
9823         if (!IS_MOBILE(dev))
9824                 return false;
9825
9826         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9827                 return false;
9828
9829         if (IS_GEN5(dev) &&
9830             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9831                 return false;
9832
9833         return true;
9834 }
9835
9836 static void intel_setup_outputs(struct drm_device *dev)
9837 {
9838         struct drm_i915_private *dev_priv = dev->dev_private;
9839         struct intel_encoder *encoder;
9840         bool dpd_is_edp = false;
9841
9842         intel_lvds_init(dev);
9843
9844         if (!IS_ULT(dev))
9845                 intel_crt_init(dev);
9846
9847         if (HAS_DDI(dev)) {
9848                 int found;
9849
9850                 /* Haswell uses DDI functions to detect digital outputs */
9851                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9852                 /* DDI A only supports eDP */
9853                 if (found)
9854                         intel_ddi_init(dev, PORT_A);
9855
9856                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9857                  * register */
9858                 found = I915_READ(SFUSE_STRAP);
9859
9860                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9861                         intel_ddi_init(dev, PORT_B);
9862                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9863                         intel_ddi_init(dev, PORT_C);
9864                 if (found & SFUSE_STRAP_DDID_DETECTED)
9865                         intel_ddi_init(dev, PORT_D);
9866         } else if (HAS_PCH_SPLIT(dev)) {
9867                 int found;
9868                 dpd_is_edp = intel_dpd_is_edp(dev);
9869
9870                 if (has_edp_a(dev))
9871                         intel_dp_init(dev, DP_A, PORT_A);
9872
9873                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9874                         /* PCH SDVOB multiplex with HDMIB */
9875                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9876                         if (!found)
9877                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9878                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9879                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9880                 }
9881
9882                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9883                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9884
9885                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9886                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9887
9888                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9889                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9890
9891                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9892                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9893         } else if (IS_VALLEYVIEW(dev)) {
9894                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9895                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9896                                         PORT_B);
9897                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9898                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9899                 }
9900
9901                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9902                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9903                                         PORT_C);
9904                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9905                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9906                                               PORT_C);
9907                 }
9908
9909                 intel_dsi_init(dev);
9910         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9911                 bool found = false;
9912
9913                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9914                         DRM_DEBUG_KMS("probing SDVOB\n");
9915                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9916                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9917                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9918                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9919                         }
9920
9921                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9922                                 intel_dp_init(dev, DP_B, PORT_B);
9923                 }
9924
9925                 /* Before G4X SDVOC doesn't have its own detect register */
9926
9927                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9928                         DRM_DEBUG_KMS("probing SDVOC\n");
9929                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9930                 }
9931
9932                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9933
9934                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9935                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9936                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9937                         }
9938                         if (SUPPORTS_INTEGRATED_DP(dev))
9939                                 intel_dp_init(dev, DP_C, PORT_C);
9940                 }
9941
9942                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9943                     (I915_READ(DP_D) & DP_DETECTED))
9944                         intel_dp_init(dev, DP_D, PORT_D);
9945         } else if (IS_GEN2(dev))
9946                 intel_dvo_init(dev);
9947
9948         if (SUPPORTS_TV(dev))
9949                 intel_tv_init(dev);
9950
9951         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9952                 encoder->base.possible_crtcs = encoder->crtc_mask;
9953                 encoder->base.possible_clones =
9954                         intel_encoder_clones(encoder);
9955         }
9956
9957         intel_init_pch_refclk(dev);
9958
9959         drm_helper_move_panel_connectors_to_head(dev);
9960 }
9961
9962 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9963 {
9964         drm_framebuffer_cleanup(&fb->base);
9965         WARN_ON(!fb->obj->framebuffer_references--);
9966         drm_gem_object_unreference_unlocked(&fb->obj->base);
9967 }
9968
9969 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9970 {
9971         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9972
9973         intel_framebuffer_fini(intel_fb);
9974         kfree(intel_fb);
9975 }
9976
9977 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9978                                                 struct drm_file *file,
9979                                                 unsigned int *handle)
9980 {
9981         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9982         struct drm_i915_gem_object *obj = intel_fb->obj;
9983
9984         return drm_gem_handle_create(file, &obj->base, handle);
9985 }
9986
9987 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9988         .destroy = intel_user_framebuffer_destroy,
9989         .create_handle = intel_user_framebuffer_create_handle,
9990 };
9991
9992 int intel_framebuffer_init(struct drm_device *dev,
9993                            struct intel_framebuffer *intel_fb,
9994                            struct drm_mode_fb_cmd2 *mode_cmd,
9995                            struct drm_i915_gem_object *obj)
9996 {
9997         int aligned_height, tile_height;
9998         int pitch_limit;
9999         int ret;
10000
10001         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10002
10003         if (obj->tiling_mode == I915_TILING_Y) {
10004                 DRM_DEBUG("hardware does not support tiling Y\n");
10005                 return -EINVAL;
10006         }
10007
10008         if (mode_cmd->pitches[0] & 63) {
10009                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10010                           mode_cmd->pitches[0]);
10011                 return -EINVAL;
10012         }
10013
10014         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10015                 pitch_limit = 32*1024;
10016         } else if (INTEL_INFO(dev)->gen >= 4) {
10017                 if (obj->tiling_mode)
10018                         pitch_limit = 16*1024;
10019                 else
10020                         pitch_limit = 32*1024;
10021         } else if (INTEL_INFO(dev)->gen >= 3) {
10022                 if (obj->tiling_mode)
10023                         pitch_limit = 8*1024;
10024                 else
10025                         pitch_limit = 16*1024;
10026         } else
10027                 /* XXX DSPC is limited to 4k tiled */
10028                 pitch_limit = 8*1024;
10029
10030         if (mode_cmd->pitches[0] > pitch_limit) {
10031                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10032                           obj->tiling_mode ? "tiled" : "linear",
10033                           mode_cmd->pitches[0], pitch_limit);
10034                 return -EINVAL;
10035         }
10036
10037         if (obj->tiling_mode != I915_TILING_NONE &&
10038             mode_cmd->pitches[0] != obj->stride) {
10039                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10040                           mode_cmd->pitches[0], obj->stride);
10041                 return -EINVAL;
10042         }
10043
10044         /* Reject formats not supported by any plane early. */
10045         switch (mode_cmd->pixel_format) {
10046         case DRM_FORMAT_C8:
10047         case DRM_FORMAT_RGB565:
10048         case DRM_FORMAT_XRGB8888:
10049         case DRM_FORMAT_ARGB8888:
10050                 break;
10051         case DRM_FORMAT_XRGB1555:
10052         case DRM_FORMAT_ARGB1555:
10053                 if (INTEL_INFO(dev)->gen > 3) {
10054                         DRM_DEBUG("unsupported pixel format: %s\n",
10055                                   drm_get_format_name(mode_cmd->pixel_format));
10056                         return -EINVAL;
10057                 }
10058                 break;
10059         case DRM_FORMAT_XBGR8888:
10060         case DRM_FORMAT_ABGR8888:
10061         case DRM_FORMAT_XRGB2101010:
10062         case DRM_FORMAT_ARGB2101010:
10063         case DRM_FORMAT_XBGR2101010:
10064         case DRM_FORMAT_ABGR2101010:
10065                 if (INTEL_INFO(dev)->gen < 4) {
10066                         DRM_DEBUG("unsupported pixel format: %s\n",
10067                                   drm_get_format_name(mode_cmd->pixel_format));
10068                         return -EINVAL;
10069                 }
10070                 break;
10071         case DRM_FORMAT_YUYV:
10072         case DRM_FORMAT_UYVY:
10073         case DRM_FORMAT_YVYU:
10074         case DRM_FORMAT_VYUY:
10075                 if (INTEL_INFO(dev)->gen < 5) {
10076                         DRM_DEBUG("unsupported pixel format: %s\n",
10077                                   drm_get_format_name(mode_cmd->pixel_format));
10078                         return -EINVAL;
10079                 }
10080                 break;
10081         default:
10082                 DRM_DEBUG("unsupported pixel format: %s\n",
10083                           drm_get_format_name(mode_cmd->pixel_format));
10084                 return -EINVAL;
10085         }
10086
10087         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10088         if (mode_cmd->offsets[0] != 0)
10089                 return -EINVAL;
10090
10091         tile_height = IS_GEN2(dev) ? 16 : 8;
10092         aligned_height = ALIGN(mode_cmd->height,
10093                                obj->tiling_mode ? tile_height : 1);
10094         /* FIXME drm helper for size checks (especially planar formats)? */
10095         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10096                 return -EINVAL;
10097
10098         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10099         intel_fb->obj = obj;
10100         intel_fb->obj->framebuffer_references++;
10101
10102         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10103         if (ret) {
10104                 DRM_ERROR("framebuffer init failed %d\n", ret);
10105                 return ret;
10106         }
10107
10108         return 0;
10109 }
10110
10111 static struct drm_framebuffer *
10112 intel_user_framebuffer_create(struct drm_device *dev,
10113                               struct drm_file *filp,
10114                               struct drm_mode_fb_cmd2 *mode_cmd)
10115 {
10116         struct drm_i915_gem_object *obj;
10117
10118         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10119                                                 mode_cmd->handles[0]));
10120         if (&obj->base == NULL)
10121                 return ERR_PTR(-ENOENT);
10122
10123         return intel_framebuffer_create(dev, mode_cmd, obj);
10124 }
10125
10126 #ifndef CONFIG_DRM_I915_FBDEV
10127 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10128 {
10129 }
10130 #endif
10131
10132 static const struct drm_mode_config_funcs intel_mode_funcs = {
10133         .fb_create = intel_user_framebuffer_create,
10134         .output_poll_changed = intel_fbdev_output_poll_changed,
10135 };
10136
10137 /* Set up chip specific display functions */
10138 static void intel_init_display(struct drm_device *dev)
10139 {
10140         struct drm_i915_private *dev_priv = dev->dev_private;
10141
10142         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10143                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10144         else if (IS_VALLEYVIEW(dev))
10145                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10146         else if (IS_PINEVIEW(dev))
10147                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10148         else
10149                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10150
10151         if (HAS_DDI(dev)) {
10152                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10153                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10154                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10155                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10156                 dev_priv->display.off = haswell_crtc_off;
10157                 dev_priv->display.update_plane = ironlake_update_plane;
10158         } else if (HAS_PCH_SPLIT(dev)) {
10159                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10160                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10161                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10162                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10163                 dev_priv->display.off = ironlake_crtc_off;
10164                 dev_priv->display.update_plane = ironlake_update_plane;
10165         } else if (IS_VALLEYVIEW(dev)) {
10166                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10167                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10168                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10169                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10170                 dev_priv->display.off = i9xx_crtc_off;
10171                 dev_priv->display.update_plane = i9xx_update_plane;
10172         } else {
10173                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10174                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10175                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10176                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10177                 dev_priv->display.off = i9xx_crtc_off;
10178                 dev_priv->display.update_plane = i9xx_update_plane;
10179         }
10180
10181         /* Returns the core display clock speed */
10182         if (IS_VALLEYVIEW(dev))
10183                 dev_priv->display.get_display_clock_speed =
10184                         valleyview_get_display_clock_speed;
10185         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10186                 dev_priv->display.get_display_clock_speed =
10187                         i945_get_display_clock_speed;
10188         else if (IS_I915G(dev))
10189                 dev_priv->display.get_display_clock_speed =
10190                         i915_get_display_clock_speed;
10191         else if (IS_I945GM(dev) || IS_845G(dev))
10192                 dev_priv->display.get_display_clock_speed =
10193                         i9xx_misc_get_display_clock_speed;
10194         else if (IS_PINEVIEW(dev))
10195                 dev_priv->display.get_display_clock_speed =
10196                         pnv_get_display_clock_speed;
10197         else if (IS_I915GM(dev))
10198                 dev_priv->display.get_display_clock_speed =
10199                         i915gm_get_display_clock_speed;
10200         else if (IS_I865G(dev))
10201                 dev_priv->display.get_display_clock_speed =
10202                         i865_get_display_clock_speed;
10203         else if (IS_I85X(dev))
10204                 dev_priv->display.get_display_clock_speed =
10205                         i855_get_display_clock_speed;
10206         else /* 852, 830 */
10207                 dev_priv->display.get_display_clock_speed =
10208                         i830_get_display_clock_speed;
10209
10210         if (HAS_PCH_SPLIT(dev)) {
10211                 if (IS_GEN5(dev)) {
10212                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10213                         dev_priv->display.write_eld = ironlake_write_eld;
10214                 } else if (IS_GEN6(dev)) {
10215                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10216                         dev_priv->display.write_eld = ironlake_write_eld;
10217                 } else if (IS_IVYBRIDGE(dev)) {
10218                         /* FIXME: detect B0+ stepping and use auto training */
10219                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10220                         dev_priv->display.write_eld = ironlake_write_eld;
10221                         dev_priv->display.modeset_global_resources =
10222                                 ivb_modeset_global_resources;
10223                 } else if (IS_HASWELL(dev)) {
10224                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10225                         dev_priv->display.write_eld = haswell_write_eld;
10226                         dev_priv->display.modeset_global_resources =
10227                                 haswell_modeset_global_resources;
10228                 }
10229         } else if (IS_G4X(dev)) {
10230                 dev_priv->display.write_eld = g4x_write_eld;
10231         }
10232
10233         /* Default just returns -ENODEV to indicate unsupported */
10234         dev_priv->display.queue_flip = intel_default_queue_flip;
10235
10236         switch (INTEL_INFO(dev)->gen) {
10237         case 2:
10238                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10239                 break;
10240
10241         case 3:
10242                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10243                 break;
10244
10245         case 4:
10246         case 5:
10247                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10248                 break;
10249
10250         case 6:
10251                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10252                 break;
10253         case 7:
10254                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10255                 break;
10256         }
10257 }
10258
10259 /*
10260  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10261  * resume, or other times.  This quirk makes sure that's the case for
10262  * affected systems.
10263  */
10264 static void quirk_pipea_force(struct drm_device *dev)
10265 {
10266         struct drm_i915_private *dev_priv = dev->dev_private;
10267
10268         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10269         DRM_INFO("applying pipe a force quirk\n");
10270 }
10271
10272 /*
10273  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10274  */
10275 static void quirk_ssc_force_disable(struct drm_device *dev)
10276 {
10277         struct drm_i915_private *dev_priv = dev->dev_private;
10278         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10279         DRM_INFO("applying lvds SSC disable quirk\n");
10280 }
10281
10282 /*
10283  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10284  * brightness value
10285  */
10286 static void quirk_invert_brightness(struct drm_device *dev)
10287 {
10288         struct drm_i915_private *dev_priv = dev->dev_private;
10289         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10290         DRM_INFO("applying inverted panel brightness quirk\n");
10291 }
10292
10293 /*
10294  * Some machines (Dell XPS13) suffer broken backlight controls if
10295  * BLM_PCH_PWM_ENABLE is set.
10296  */
10297 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10298 {
10299         struct drm_i915_private *dev_priv = dev->dev_private;
10300         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10301         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10302 }
10303
10304 struct intel_quirk {
10305         int device;
10306         int subsystem_vendor;
10307         int subsystem_device;
10308         void (*hook)(struct drm_device *dev);
10309 };
10310
10311 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10312 struct intel_dmi_quirk {
10313         void (*hook)(struct drm_device *dev);
10314         const struct dmi_system_id (*dmi_id_list)[];
10315 };
10316
10317 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10318 {
10319         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10320         return 1;
10321 }
10322
10323 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10324         {
10325                 .dmi_id_list = &(const struct dmi_system_id[]) {
10326                         {
10327                                 .callback = intel_dmi_reverse_brightness,
10328                                 .ident = "NCR Corporation",
10329                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10330                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10331                                 },
10332                         },
10333                         { }  /* terminating entry */
10334                 },
10335                 .hook = quirk_invert_brightness,
10336         },
10337 };
10338
10339 static struct intel_quirk intel_quirks[] = {
10340         /* HP Mini needs pipe A force quirk (LP: #322104) */
10341         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10342
10343         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10344         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10345
10346         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10347         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10348
10349         /* 830 needs to leave pipe A & dpll A up */
10350         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10351
10352         /* Lenovo U160 cannot use SSC on LVDS */
10353         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10354
10355         /* Sony Vaio Y cannot use SSC on LVDS */
10356         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10357
10358         /*
10359          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10360          * seem to use inverted backlight PWM.
10361          */
10362         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10363
10364         /* Dell XPS13 HD Sandy Bridge */
10365         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10366         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10367         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10368 };
10369
10370 static void intel_init_quirks(struct drm_device *dev)
10371 {
10372         struct pci_dev *d = dev->pdev;
10373         int i;
10374
10375         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10376                 struct intel_quirk *q = &intel_quirks[i];
10377
10378                 if (d->device == q->device &&
10379                     (d->subsystem_vendor == q->subsystem_vendor ||
10380                      q->subsystem_vendor == PCI_ANY_ID) &&
10381                     (d->subsystem_device == q->subsystem_device ||
10382                      q->subsystem_device == PCI_ANY_ID))
10383                         q->hook(dev);
10384         }
10385         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10386                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10387                         intel_dmi_quirks[i].hook(dev);
10388         }
10389 }
10390
10391 /* Disable the VGA plane that we never use */
10392 static void i915_disable_vga(struct drm_device *dev)
10393 {
10394         struct drm_i915_private *dev_priv = dev->dev_private;
10395         u8 sr1;
10396         u32 vga_reg = i915_vgacntrl_reg(dev);
10397
10398         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10399         outb(SR01, VGA_SR_INDEX);
10400         sr1 = inb(VGA_SR_DATA);
10401         outb(sr1 | 1<<5, VGA_SR_DATA);
10402         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10403         udelay(300);
10404
10405         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10406         POSTING_READ(vga_reg);
10407 }
10408
10409 static void i915_enable_vga_mem(struct drm_device *dev)
10410 {
10411         /* Enable VGA memory on Intel HD */
10412         if (HAS_PCH_SPLIT(dev)) {
10413                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10414                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10415                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10416                                                    VGA_RSRC_LEGACY_MEM |
10417                                                    VGA_RSRC_NORMAL_IO |
10418                                                    VGA_RSRC_NORMAL_MEM);
10419                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10420         }
10421 }
10422
10423 void i915_disable_vga_mem(struct drm_device *dev)
10424 {
10425         /* Disable VGA memory on Intel HD */
10426         if (HAS_PCH_SPLIT(dev)) {
10427                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10428                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10429                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10430                                                    VGA_RSRC_NORMAL_IO |
10431                                                    VGA_RSRC_NORMAL_MEM);
10432                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10433         }
10434 }
10435
10436 void intel_modeset_init_hw(struct drm_device *dev)
10437 {
10438         struct drm_i915_private *dev_priv = dev->dev_private;
10439
10440         intel_prepare_ddi(dev);
10441
10442         intel_init_clock_gating(dev);
10443
10444         /* Enable the CRI clock source so we can get at the display */
10445         if (IS_VALLEYVIEW(dev))
10446                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10447                            DPLL_INTEGRATED_CRI_CLK_VLV);
10448
10449         intel_init_dpio(dev);
10450
10451         mutex_lock(&dev->struct_mutex);
10452         intel_enable_gt_powersave(dev);
10453         mutex_unlock(&dev->struct_mutex);
10454 }
10455
10456 void intel_modeset_suspend_hw(struct drm_device *dev)
10457 {
10458         intel_suspend_hw(dev);
10459 }
10460
10461 void intel_modeset_init(struct drm_device *dev)
10462 {
10463         struct drm_i915_private *dev_priv = dev->dev_private;
10464         int i, j, ret;
10465
10466         drm_mode_config_init(dev);
10467
10468         dev->mode_config.min_width = 0;
10469         dev->mode_config.min_height = 0;
10470
10471         dev->mode_config.preferred_depth = 24;
10472         dev->mode_config.prefer_shadow = 1;
10473
10474         dev->mode_config.funcs = &intel_mode_funcs;
10475
10476         intel_init_quirks(dev);
10477
10478         intel_init_pm(dev);
10479
10480         if (INTEL_INFO(dev)->num_pipes == 0)
10481                 return;
10482
10483         intel_init_display(dev);
10484
10485         if (IS_GEN2(dev)) {
10486                 dev->mode_config.max_width = 2048;
10487                 dev->mode_config.max_height = 2048;
10488         } else if (IS_GEN3(dev)) {
10489                 dev->mode_config.max_width = 4096;
10490                 dev->mode_config.max_height = 4096;
10491         } else {
10492                 dev->mode_config.max_width = 8192;
10493                 dev->mode_config.max_height = 8192;
10494         }
10495         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10496
10497         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10498                       INTEL_INFO(dev)->num_pipes,
10499                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10500
10501         for_each_pipe(i) {
10502                 intel_crtc_init(dev, i);
10503                 for (j = 0; j < dev_priv->num_plane; j++) {
10504                         ret = intel_plane_init(dev, i, j);
10505                         if (ret)
10506                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10507                                               pipe_name(i), sprite_name(i, j), ret);
10508                 }
10509         }
10510
10511         intel_cpu_pll_init(dev);
10512         intel_shared_dpll_init(dev);
10513
10514         /* Just disable it once at startup */
10515         i915_disable_vga(dev);
10516         intel_setup_outputs(dev);
10517
10518         /* Just in case the BIOS is doing something questionable. */
10519         intel_disable_fbc(dev);
10520 }
10521
10522 static void
10523 intel_connector_break_all_links(struct intel_connector *connector)
10524 {
10525         connector->base.dpms = DRM_MODE_DPMS_OFF;
10526         connector->base.encoder = NULL;
10527         connector->encoder->connectors_active = false;
10528         connector->encoder->base.crtc = NULL;
10529 }
10530
10531 static void intel_enable_pipe_a(struct drm_device *dev)
10532 {
10533         struct intel_connector *connector;
10534         struct drm_connector *crt = NULL;
10535         struct intel_load_detect_pipe load_detect_temp;
10536
10537         /* We can't just switch on the pipe A, we need to set things up with a
10538          * proper mode and output configuration. As a gross hack, enable pipe A
10539          * by enabling the load detect pipe once. */
10540         list_for_each_entry(connector,
10541                             &dev->mode_config.connector_list,
10542                             base.head) {
10543                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10544                         crt = &connector->base;
10545                         break;
10546                 }
10547         }
10548
10549         if (!crt)
10550                 return;
10551
10552         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10553                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10554
10555
10556 }
10557
10558 static bool
10559 intel_check_plane_mapping(struct intel_crtc *crtc)
10560 {
10561         struct drm_device *dev = crtc->base.dev;
10562         struct drm_i915_private *dev_priv = dev->dev_private;
10563         u32 reg, val;
10564
10565         if (INTEL_INFO(dev)->num_pipes == 1)
10566                 return true;
10567
10568         reg = DSPCNTR(!crtc->plane);
10569         val = I915_READ(reg);
10570
10571         if ((val & DISPLAY_PLANE_ENABLE) &&
10572             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10573                 return false;
10574
10575         return true;
10576 }
10577
10578 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10579 {
10580         struct drm_device *dev = crtc->base.dev;
10581         struct drm_i915_private *dev_priv = dev->dev_private;
10582         u32 reg;
10583
10584         /* Clear any frame start delays used for debugging left by the BIOS */
10585         reg = PIPECONF(crtc->config.cpu_transcoder);
10586         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10587
10588         /* We need to sanitize the plane -> pipe mapping first because this will
10589          * disable the crtc (and hence change the state) if it is wrong. Note
10590          * that gen4+ has a fixed plane -> pipe mapping.  */
10591         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10592                 struct intel_connector *connector;
10593                 bool plane;
10594
10595                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10596                               crtc->base.base.id);
10597
10598                 /* Pipe has the wrong plane attached and the plane is active.
10599                  * Temporarily change the plane mapping and disable everything
10600                  * ...  */
10601                 plane = crtc->plane;
10602                 crtc->plane = !plane;
10603                 dev_priv->display.crtc_disable(&crtc->base);
10604                 crtc->plane = plane;
10605
10606                 /* ... and break all links. */
10607                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10608                                     base.head) {
10609                         if (connector->encoder->base.crtc != &crtc->base)
10610                                 continue;
10611
10612                         intel_connector_break_all_links(connector);
10613                 }
10614
10615                 WARN_ON(crtc->active);
10616                 crtc->base.enabled = false;
10617         }
10618
10619         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10620             crtc->pipe == PIPE_A && !crtc->active) {
10621                 /* BIOS forgot to enable pipe A, this mostly happens after
10622                  * resume. Force-enable the pipe to fix this, the update_dpms
10623                  * call below we restore the pipe to the right state, but leave
10624                  * the required bits on. */
10625                 intel_enable_pipe_a(dev);
10626         }
10627
10628         /* Adjust the state of the output pipe according to whether we
10629          * have active connectors/encoders. */
10630         intel_crtc_update_dpms(&crtc->base);
10631
10632         if (crtc->active != crtc->base.enabled) {
10633                 struct intel_encoder *encoder;
10634
10635                 /* This can happen either due to bugs in the get_hw_state
10636                  * functions or because the pipe is force-enabled due to the
10637                  * pipe A quirk. */
10638                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10639                               crtc->base.base.id,
10640                               crtc->base.enabled ? "enabled" : "disabled",
10641                               crtc->active ? "enabled" : "disabled");
10642
10643                 crtc->base.enabled = crtc->active;
10644
10645                 /* Because we only establish the connector -> encoder ->
10646                  * crtc links if something is active, this means the
10647                  * crtc is now deactivated. Break the links. connector
10648                  * -> encoder links are only establish when things are
10649                  *  actually up, hence no need to break them. */
10650                 WARN_ON(crtc->active);
10651
10652                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10653                         WARN_ON(encoder->connectors_active);
10654                         encoder->base.crtc = NULL;
10655                 }
10656         }
10657 }
10658
10659 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10660 {
10661         struct intel_connector *connector;
10662         struct drm_device *dev = encoder->base.dev;
10663
10664         /* We need to check both for a crtc link (meaning that the
10665          * encoder is active and trying to read from a pipe) and the
10666          * pipe itself being active. */
10667         bool has_active_crtc = encoder->base.crtc &&
10668                 to_intel_crtc(encoder->base.crtc)->active;
10669
10670         if (encoder->connectors_active && !has_active_crtc) {
10671                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10672                               encoder->base.base.id,
10673                               drm_get_encoder_name(&encoder->base));
10674
10675                 /* Connector is active, but has no active pipe. This is
10676                  * fallout from our resume register restoring. Disable
10677                  * the encoder manually again. */
10678                 if (encoder->base.crtc) {
10679                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10680                                       encoder->base.base.id,
10681                                       drm_get_encoder_name(&encoder->base));
10682                         encoder->disable(encoder);
10683                 }
10684
10685                 /* Inconsistent output/port/pipe state happens presumably due to
10686                  * a bug in one of the get_hw_state functions. Or someplace else
10687                  * in our code, like the register restore mess on resume. Clamp
10688                  * things to off as a safer default. */
10689                 list_for_each_entry(connector,
10690                                     &dev->mode_config.connector_list,
10691                                     base.head) {
10692                         if (connector->encoder != encoder)
10693                                 continue;
10694
10695                         intel_connector_break_all_links(connector);
10696                 }
10697         }
10698         /* Enabled encoders without active connectors will be fixed in
10699          * the crtc fixup. */
10700 }
10701
10702 void i915_redisable_vga(struct drm_device *dev)
10703 {
10704         struct drm_i915_private *dev_priv = dev->dev_private;
10705         u32 vga_reg = i915_vgacntrl_reg(dev);
10706
10707         /* This function can be called both from intel_modeset_setup_hw_state or
10708          * at a very early point in our resume sequence, where the power well
10709          * structures are not yet restored. Since this function is at a very
10710          * paranoid "someone might have enabled VGA while we were not looking"
10711          * level, just check if the power well is enabled instead of trying to
10712          * follow the "don't touch the power well if we don't need it" policy
10713          * the rest of the driver uses. */
10714         if (HAS_POWER_WELL(dev) &&
10715             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10716                 return;
10717
10718         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10719                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10720                 i915_disable_vga(dev);
10721                 i915_disable_vga_mem(dev);
10722         }
10723 }
10724
10725 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10726 {
10727         struct drm_i915_private *dev_priv = dev->dev_private;
10728         enum pipe pipe;
10729         struct intel_crtc *crtc;
10730         struct intel_encoder *encoder;
10731         struct intel_connector *connector;
10732         int i;
10733
10734         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10735                             base.head) {
10736                 memset(&crtc->config, 0, sizeof(crtc->config));
10737
10738                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10739                                                                  &crtc->config);
10740
10741                 crtc->base.enabled = crtc->active;
10742                 crtc->primary_enabled = crtc->active;
10743
10744                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10745                               crtc->base.base.id,
10746                               crtc->active ? "enabled" : "disabled");
10747         }
10748
10749         /* FIXME: Smash this into the new shared dpll infrastructure. */
10750         if (HAS_DDI(dev))
10751                 intel_ddi_setup_hw_pll_state(dev);
10752
10753         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10754                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10755
10756                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10757                 pll->active = 0;
10758                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10759                                     base.head) {
10760                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10761                                 pll->active++;
10762                 }
10763                 pll->refcount = pll->active;
10764
10765                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10766                               pll->name, pll->refcount, pll->on);
10767         }
10768
10769         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10770                             base.head) {
10771                 pipe = 0;
10772
10773                 if (encoder->get_hw_state(encoder, &pipe)) {
10774                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10775                         encoder->base.crtc = &crtc->base;
10776                         if (encoder->get_config)
10777                                 encoder->get_config(encoder, &crtc->config);
10778                 } else {
10779                         encoder->base.crtc = NULL;
10780                 }
10781
10782                 encoder->connectors_active = false;
10783                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10784                               encoder->base.base.id,
10785                               drm_get_encoder_name(&encoder->base),
10786                               encoder->base.crtc ? "enabled" : "disabled",
10787                               pipe_name(pipe));
10788         }
10789
10790         list_for_each_entry(connector, &dev->mode_config.connector_list,
10791                             base.head) {
10792                 if (connector->get_hw_state(connector)) {
10793                         connector->base.dpms = DRM_MODE_DPMS_ON;
10794                         connector->encoder->connectors_active = true;
10795                         connector->base.encoder = &connector->encoder->base;
10796                 } else {
10797                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10798                         connector->base.encoder = NULL;
10799                 }
10800                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10801                               connector->base.base.id,
10802                               drm_get_connector_name(&connector->base),
10803                               connector->base.encoder ? "enabled" : "disabled");
10804         }
10805 }
10806
10807 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10808  * and i915 state tracking structures. */
10809 void intel_modeset_setup_hw_state(struct drm_device *dev,
10810                                   bool force_restore)
10811 {
10812         struct drm_i915_private *dev_priv = dev->dev_private;
10813         enum pipe pipe;
10814         struct intel_crtc *crtc;
10815         struct intel_encoder *encoder;
10816         int i;
10817
10818         intel_modeset_readout_hw_state(dev);
10819
10820         /*
10821          * Now that we have the config, copy it to each CRTC struct
10822          * Note that this could go away if we move to using crtc_config
10823          * checking everywhere.
10824          */
10825         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10826                             base.head) {
10827                 if (crtc->active && i915_fastboot) {
10828                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10829
10830                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10831                                       crtc->base.base.id);
10832                         drm_mode_debug_printmodeline(&crtc->base.mode);
10833                 }
10834         }
10835
10836         /* HW state is read out, now we need to sanitize this mess. */
10837         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10838                             base.head) {
10839                 intel_sanitize_encoder(encoder);
10840         }
10841
10842         for_each_pipe(pipe) {
10843                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10844                 intel_sanitize_crtc(crtc);
10845                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10846         }
10847
10848         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10849                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10850
10851                 if (!pll->on || pll->active)
10852                         continue;
10853
10854                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10855
10856                 pll->disable(dev_priv, pll);
10857                 pll->on = false;
10858         }
10859
10860         if (IS_HASWELL(dev))
10861                 ilk_wm_get_hw_state(dev);
10862
10863         if (force_restore) {
10864                 i915_redisable_vga(dev);
10865
10866                 /*
10867                  * We need to use raw interfaces for restoring state to avoid
10868                  * checking (bogus) intermediate states.
10869                  */
10870                 for_each_pipe(pipe) {
10871                         struct drm_crtc *crtc =
10872                                 dev_priv->pipe_to_crtc_mapping[pipe];
10873
10874                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10875                                          crtc->fb);
10876                 }
10877         } else {
10878                 intel_modeset_update_staged_output_state(dev);
10879         }
10880
10881         intel_modeset_check_state(dev);
10882
10883         drm_mode_config_reset(dev);
10884 }
10885
10886 void intel_modeset_gem_init(struct drm_device *dev)
10887 {
10888         intel_modeset_init_hw(dev);
10889
10890         intel_setup_overlay(dev);
10891
10892         intel_modeset_setup_hw_state(dev, false);
10893 }
10894
10895 void intel_modeset_cleanup(struct drm_device *dev)
10896 {
10897         struct drm_i915_private *dev_priv = dev->dev_private;
10898         struct drm_crtc *crtc;
10899         struct drm_connector *connector;
10900
10901         /*
10902          * Interrupts and polling as the first thing to avoid creating havoc.
10903          * Too much stuff here (turning of rps, connectors, ...) would
10904          * experience fancy races otherwise.
10905          */
10906         drm_irq_uninstall(dev);
10907         cancel_work_sync(&dev_priv->hotplug_work);
10908         /*
10909          * Due to the hpd irq storm handling the hotplug work can re-arm the
10910          * poll handlers. Hence disable polling after hpd handling is shut down.
10911          */
10912         drm_kms_helper_poll_fini(dev);
10913
10914         mutex_lock(&dev->struct_mutex);
10915
10916         intel_unregister_dsm_handler();
10917
10918         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10919                 /* Skip inactive CRTCs */
10920                 if (!crtc->fb)
10921                         continue;
10922
10923                 intel_increase_pllclock(crtc);
10924         }
10925
10926         intel_disable_fbc(dev);
10927
10928         i915_enable_vga_mem(dev);
10929
10930         intel_disable_gt_powersave(dev);
10931
10932         ironlake_teardown_rc6(dev);
10933
10934         mutex_unlock(&dev->struct_mutex);
10935
10936         /* flush any delayed tasks or pending work */
10937         flush_scheduled_work();
10938
10939         /* destroy backlight, if any, before the connectors */
10940         intel_panel_destroy_backlight(dev);
10941
10942         /* destroy the sysfs files before encoders/connectors */
10943         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10944                 drm_sysfs_connector_remove(connector);
10945
10946         drm_mode_config_cleanup(dev);
10947
10948         intel_cleanup_overlay(dev);
10949 }
10950
10951 /*
10952  * Return which encoder is currently attached for connector.
10953  */
10954 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10955 {
10956         return &intel_attached_encoder(connector)->base;
10957 }
10958
10959 void intel_connector_attach_encoder(struct intel_connector *connector,
10960                                     struct intel_encoder *encoder)
10961 {
10962         connector->encoder = encoder;
10963         drm_mode_connector_attach_encoder(&connector->base,
10964                                           &encoder->base);
10965 }
10966
10967 /*
10968  * set vga decode state - true == enable VGA decode
10969  */
10970 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10971 {
10972         struct drm_i915_private *dev_priv = dev->dev_private;
10973         u16 gmch_ctrl;
10974
10975         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10976         if (state)
10977                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10978         else
10979                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10980         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10981         return 0;
10982 }
10983
10984 struct intel_display_error_state {
10985
10986         u32 power_well_driver;
10987
10988         int num_transcoders;
10989
10990         struct intel_cursor_error_state {
10991                 u32 control;
10992                 u32 position;
10993                 u32 base;
10994                 u32 size;
10995         } cursor[I915_MAX_PIPES];
10996
10997         struct intel_pipe_error_state {
10998                 u32 source;
10999         } pipe[I915_MAX_PIPES];
11000
11001         struct intel_plane_error_state {
11002                 u32 control;
11003                 u32 stride;
11004                 u32 size;
11005                 u32 pos;
11006                 u32 addr;
11007                 u32 surface;
11008                 u32 tile_offset;
11009         } plane[I915_MAX_PIPES];
11010
11011         struct intel_transcoder_error_state {
11012                 enum transcoder cpu_transcoder;
11013
11014                 u32 conf;
11015
11016                 u32 htotal;
11017                 u32 hblank;
11018                 u32 hsync;
11019                 u32 vtotal;
11020                 u32 vblank;
11021                 u32 vsync;
11022         } transcoder[4];
11023 };
11024
11025 struct intel_display_error_state *
11026 intel_display_capture_error_state(struct drm_device *dev)
11027 {
11028         drm_i915_private_t *dev_priv = dev->dev_private;
11029         struct intel_display_error_state *error;
11030         int transcoders[] = {
11031                 TRANSCODER_A,
11032                 TRANSCODER_B,
11033                 TRANSCODER_C,
11034                 TRANSCODER_EDP,
11035         };
11036         int i;
11037
11038         if (INTEL_INFO(dev)->num_pipes == 0)
11039                 return NULL;
11040
11041         error = kmalloc(sizeof(*error), GFP_ATOMIC);
11042         if (error == NULL)
11043                 return NULL;
11044
11045         if (HAS_POWER_WELL(dev))
11046                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11047
11048         for_each_pipe(i) {
11049                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11050                         error->cursor[i].control = I915_READ(CURCNTR(i));
11051                         error->cursor[i].position = I915_READ(CURPOS(i));
11052                         error->cursor[i].base = I915_READ(CURBASE(i));
11053                 } else {
11054                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11055                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11056                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11057                 }
11058
11059                 error->plane[i].control = I915_READ(DSPCNTR(i));
11060                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11061                 if (INTEL_INFO(dev)->gen <= 3) {
11062                         error->plane[i].size = I915_READ(DSPSIZE(i));
11063                         error->plane[i].pos = I915_READ(DSPPOS(i));
11064                 }
11065                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11066                         error->plane[i].addr = I915_READ(DSPADDR(i));
11067                 if (INTEL_INFO(dev)->gen >= 4) {
11068                         error->plane[i].surface = I915_READ(DSPSURF(i));
11069                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11070                 }
11071
11072                 error->pipe[i].source = I915_READ(PIPESRC(i));
11073         }
11074
11075         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11076         if (HAS_DDI(dev_priv->dev))
11077                 error->num_transcoders++; /* Account for eDP. */
11078
11079         for (i = 0; i < error->num_transcoders; i++) {
11080                 enum transcoder cpu_transcoder = transcoders[i];
11081
11082                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11083
11084                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11085                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11086                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11087                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11088                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11089                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11090                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11091         }
11092
11093         /* In the code above we read the registers without checking if the power
11094          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11095          * prevent the next I915_WRITE from detecting it and printing an error
11096          * message. */
11097         intel_uncore_clear_errors(dev);
11098
11099         return error;
11100 }
11101
11102 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11103
11104 void
11105 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11106                                 struct drm_device *dev,
11107                                 struct intel_display_error_state *error)
11108 {
11109         int i;
11110
11111         if (!error)
11112                 return;
11113
11114         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11115         if (HAS_POWER_WELL(dev))
11116                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11117                            error->power_well_driver);
11118         for_each_pipe(i) {
11119                 err_printf(m, "Pipe [%d]:\n", i);
11120                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11121
11122                 err_printf(m, "Plane [%d]:\n", i);
11123                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11124                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11125                 if (INTEL_INFO(dev)->gen <= 3) {
11126                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11127                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11128                 }
11129                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11130                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11131                 if (INTEL_INFO(dev)->gen >= 4) {
11132                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11133                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11134                 }
11135
11136                 err_printf(m, "Cursor [%d]:\n", i);
11137                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11138                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11139                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11140         }
11141
11142         for (i = 0; i < error->num_transcoders; i++) {
11143                 err_printf(m, "  CPU transcoder: %c\n",
11144                            transcoder_name(error->transcoder[i].cpu_transcoder));
11145                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11146                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11147                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11148                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11149                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11150                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11151                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11152         }
11153 }