drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         int reg;
1161         u32 val;
1162         bool cur_state;
1163
1164         reg = DPLL(pipe);
1165         val = I915_READ(reg);
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         if (HAS_DDI(dev_priv->dev)) {
1229                 /* DDI does not have a specific FDI_TX register */
1230                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1231                 val = I915_READ(reg);
1232                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1233         } else {
1234                 reg = FDI_TX_CTL(pipe);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & FDI_TX_ENABLE);
1237         }
1238         I915_STATE_WARN(cur_state != state,
1239              "FDI TX state assertion failure (expected %s, current %s)\n",
1240              state_string(state), state_string(cur_state));
1241 }
1242 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1244
1245 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246                           enum pipe pipe, bool state)
1247 {
1248         int reg;
1249         u32 val;
1250         bool cur_state;
1251
1252         reg = FDI_RX_CTL(pipe);
1253         val = I915_READ(reg);
1254         cur_state = !!(val & FDI_RX_ENABLE);
1255         I915_STATE_WARN(cur_state != state,
1256              "FDI RX state assertion failure (expected %s, current %s)\n",
1257              state_string(state), state_string(cur_state));
1258 }
1259 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1261
1262 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263                                       enum pipe pipe)
1264 {
1265         int reg;
1266         u32 val;
1267
1268         /* ILK FDI PLL is always enabled */
1269         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1270                 return;
1271
1272         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1273         if (HAS_DDI(dev_priv->dev))
1274                 return;
1275
1276         reg = FDI_TX_CTL(pipe);
1277         val = I915_READ(reg);
1278         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1279 }
1280
1281 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282                        enum pipe pipe, bool state)
1283 {
1284         int reg;
1285         u32 val;
1286         bool cur_state;
1287
1288         reg = FDI_RX_CTL(pipe);
1289         val = I915_READ(reg);
1290         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1291         I915_STATE_WARN(cur_state != state,
1292              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293              state_string(state), state_string(cur_state));
1294 }
1295
1296 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1297                            enum pipe pipe)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         int pp_reg;
1301         u32 val;
1302         enum pipe panel_pipe = PIPE_A;
1303         bool locked = true;
1304
1305         if (WARN_ON(HAS_DDI(dev)))
1306                 return;
1307
1308         if (HAS_PCH_SPLIT(dev)) {
1309                 u32 port_sel;
1310
1311                 pp_reg = PCH_PP_CONTROL;
1312                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1313
1314                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316                         panel_pipe = PIPE_B;
1317                 /* XXX: else fix for eDP */
1318         } else if (IS_VALLEYVIEW(dev)) {
1319                 /* presumably write lock depends on pipe, not port select */
1320                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1321                 panel_pipe = pipe;
1322         } else {
1323                 pp_reg = PP_CONTROL;
1324                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325                         panel_pipe = PIPE_B;
1326         }
1327
1328         val = I915_READ(pp_reg);
1329         if (!(val & PANEL_POWER_ON) ||
1330             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1331                 locked = false;
1332
1333         I915_STATE_WARN(panel_pipe == pipe && locked,
1334              "panel assertion failure, pipe %c regs locked\n",
1335              pipe_name(pipe));
1336 }
1337
1338 static void assert_cursor(struct drm_i915_private *dev_priv,
1339                           enum pipe pipe, bool state)
1340 {
1341         struct drm_device *dev = dev_priv->dev;
1342         bool cur_state;
1343
1344         if (IS_845G(dev) || IS_I865G(dev))
1345                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1346         else
1347                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1348
1349         I915_STATE_WARN(cur_state != state,
1350              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351              pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1355
1356 void assert_pipe(struct drm_i915_private *dev_priv,
1357                  enum pipe pipe, bool state)
1358 {
1359         int reg;
1360         u32 val;
1361         bool cur_state;
1362         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1363                                                                       pipe);
1364
1365         /* if we need the pipe quirk it must be always on */
1366         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1368                 state = true;
1369
1370         if (!intel_display_power_is_enabled(dev_priv,
1371                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1372                 cur_state = false;
1373         } else {
1374                 reg = PIPECONF(cpu_transcoder);
1375                 val = I915_READ(reg);
1376                 cur_state = !!(val & PIPECONF_ENABLE);
1377         }
1378
1379         I915_STATE_WARN(cur_state != state,
1380              "pipe %c assertion failure (expected %s, current %s)\n",
1381              pipe_name(pipe), state_string(state), state_string(cur_state));
1382 }
1383
1384 static void assert_plane(struct drm_i915_private *dev_priv,
1385                          enum plane plane, bool state)
1386 {
1387         int reg;
1388         u32 val;
1389         bool cur_state;
1390
1391         reg = DSPCNTR(plane);
1392         val = I915_READ(reg);
1393         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1394         I915_STATE_WARN(cur_state != state,
1395              "plane %c assertion failure (expected %s, current %s)\n",
1396              plane_name(plane), state_string(state), state_string(cur_state));
1397 }
1398
1399 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1401
1402 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1403                                    enum pipe pipe)
1404 {
1405         struct drm_device *dev = dev_priv->dev;
1406         int reg, i;
1407         u32 val;
1408         int cur_pipe;
1409
1410         /* Primary planes are fixed to pipes on gen4+ */
1411         if (INTEL_INFO(dev)->gen >= 4) {
1412                 reg = DSPCNTR(pipe);
1413                 val = I915_READ(reg);
1414                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1415                      "plane %c assertion failure, should be disabled but not\n",
1416                      plane_name(pipe));
1417                 return;
1418         }
1419
1420         /* Need to check both planes against the pipe */
1421         for_each_pipe(dev_priv, i) {
1422                 reg = DSPCNTR(i);
1423                 val = I915_READ(reg);
1424                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425                         DISPPLANE_SEL_PIPE_SHIFT;
1426                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1427                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428                      plane_name(i), pipe_name(pipe));
1429         }
1430 }
1431
1432 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1433                                     enum pipe pipe)
1434 {
1435         struct drm_device *dev = dev_priv->dev;
1436         int reg, sprite;
1437         u32 val;
1438
1439         if (INTEL_INFO(dev)->gen >= 9) {
1440                 for_each_sprite(dev_priv, pipe, sprite) {
1441                         val = I915_READ(PLANE_CTL(pipe, sprite));
1442                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1443                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444                              sprite, pipe_name(pipe));
1445                 }
1446         } else if (IS_VALLEYVIEW(dev)) {
1447                 for_each_sprite(dev_priv, pipe, sprite) {
1448                         reg = SPCNTR(pipe, sprite);
1449                         val = I915_READ(reg);
1450                         I915_STATE_WARN(val & SP_ENABLE,
1451                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1452                              sprite_name(pipe, sprite), pipe_name(pipe));
1453                 }
1454         } else if (INTEL_INFO(dev)->gen >= 7) {
1455                 reg = SPRCTL(pipe);
1456                 val = I915_READ(reg);
1457                 I915_STATE_WARN(val & SPRITE_ENABLE,
1458                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1459                      plane_name(pipe), pipe_name(pipe));
1460         } else if (INTEL_INFO(dev)->gen >= 5) {
1461                 reg = DVSCNTR(pipe);
1462                 val = I915_READ(reg);
1463                 I915_STATE_WARN(val & DVS_ENABLE,
1464                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1465                      plane_name(pipe), pipe_name(pipe));
1466         }
1467 }
1468
1469 static void assert_vblank_disabled(struct drm_crtc *crtc)
1470 {
1471         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1472                 drm_crtc_vblank_put(crtc);
1473 }
1474
1475 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1476 {
1477         u32 val;
1478         bool enabled;
1479
1480         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1481
1482         val = I915_READ(PCH_DREF_CONTROL);
1483         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484                             DREF_SUPERSPREAD_SOURCE_MASK));
1485         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1486 }
1487
1488 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1489                                            enum pipe pipe)
1490 {
1491         int reg;
1492         u32 val;
1493         bool enabled;
1494
1495         reg = PCH_TRANSCONF(pipe);
1496         val = I915_READ(reg);
1497         enabled = !!(val & TRANS_ENABLE);
1498         I915_STATE_WARN(enabled,
1499              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1500              pipe_name(pipe));
1501 }
1502
1503 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504                             enum pipe pipe, u32 port_sel, u32 val)
1505 {
1506         if ((val & DP_PORT_EN) == 0)
1507                 return false;
1508
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1513                         return false;
1514         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1516                         return false;
1517         } else {
1518                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1519                         return false;
1520         }
1521         return true;
1522 }
1523
1524 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525                               enum pipe pipe, u32 val)
1526 {
1527         if ((val & SDVO_ENABLE) == 0)
1528                 return false;
1529
1530         if (HAS_PCH_CPT(dev_priv->dev)) {
1531                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1532                         return false;
1533         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1535                         return false;
1536         } else {
1537                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1538                         return false;
1539         }
1540         return true;
1541 }
1542
1543 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544                               enum pipe pipe, u32 val)
1545 {
1546         if ((val & LVDS_PORT_EN) == 0)
1547                 return false;
1548
1549         if (HAS_PCH_CPT(dev_priv->dev)) {
1550                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1551                         return false;
1552         } else {
1553                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1554                         return false;
1555         }
1556         return true;
1557 }
1558
1559 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560                               enum pipe pipe, u32 val)
1561 {
1562         if ((val & ADPA_DAC_ENABLE) == 0)
1563                 return false;
1564         if (HAS_PCH_CPT(dev_priv->dev)) {
1565                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1566                         return false;
1567         } else {
1568                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1569                         return false;
1570         }
1571         return true;
1572 }
1573
1574 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1575                                    enum pipe pipe, int reg, u32 port_sel)
1576 {
1577         u32 val = I915_READ(reg);
1578         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1579              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1580              reg, pipe_name(pipe));
1581
1582         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1583              && (val & DP_PIPEB_SELECT),
1584              "IBX PCH dp port still using transcoder B\n");
1585 }
1586
1587 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588                                      enum pipe pipe, int reg)
1589 {
1590         u32 val = I915_READ(reg);
1591         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1592              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1593              reg, pipe_name(pipe));
1594
1595         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1596              && (val & SDVO_PIPE_B_SELECT),
1597              "IBX PCH hdmi port still using transcoder B\n");
1598 }
1599
1600 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1601                                       enum pipe pipe)
1602 {
1603         int reg;
1604         u32 val;
1605
1606         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1609
1610         reg = PCH_ADPA;
1611         val = I915_READ(reg);
1612         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1613              "PCH VGA enabled on transcoder %c, should be disabled\n",
1614              pipe_name(pipe));
1615
1616         reg = PCH_LVDS;
1617         val = I915_READ(reg);
1618         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1619              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1620              pipe_name(pipe));
1621
1622         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1625 }
1626
1627 static void vlv_enable_pll(struct intel_crtc *crtc,
1628                            const struct intel_crtc_state *pipe_config)
1629 {
1630         struct drm_device *dev = crtc->base.dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         int reg = DPLL(crtc->pipe);
1633         u32 dpll = pipe_config->dpll_hw_state.dpll;
1634
1635         assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637         /* No really, not for ILK+ */
1638         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1639
1640         /* PLL is protected by panel, make sure we can write it */
1641         if (IS_MOBILE(dev_priv->dev))
1642                 assert_panel_unlocked(dev_priv, crtc->pipe);
1643
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150);
1647
1648         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1650
1651         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1652         POSTING_READ(DPLL_MD(crtc->pipe));
1653
1654         /* We do this three times for luck */
1655         I915_WRITE(reg, dpll);
1656         POSTING_READ(reg);
1657         udelay(150); /* wait for warmup */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664 }
1665
1666 static void chv_enable_pll(struct intel_crtc *crtc,
1667                            const struct intel_crtc_state *pipe_config)
1668 {
1669         struct drm_device *dev = crtc->base.dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         int pipe = crtc->pipe;
1672         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1673         u32 tmp;
1674
1675         assert_pipe_disabled(dev_priv, crtc->pipe);
1676
1677         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1678
1679         mutex_lock(&dev_priv->sb_lock);
1680
1681         /* Enable back the 10bit clock to display controller */
1682         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683         tmp |= DPIO_DCLKP_EN;
1684         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1685
1686         mutex_unlock(&dev_priv->sb_lock);
1687
1688         /*
1689          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1690          */
1691         udelay(1);
1692
1693         /* Enable PLL */
1694         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1695
1696         /* Check PLL is locked */
1697         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1698                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1699
1700         /* not sure when this should be written */
1701         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1702         POSTING_READ(DPLL_MD(pipe));
1703 }
1704
1705 static int intel_num_dvo_pipes(struct drm_device *dev)
1706 {
1707         struct intel_crtc *crtc;
1708         int count = 0;
1709
1710         for_each_intel_crtc(dev, crtc)
1711                 count += crtc->base.state->active &&
1712                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1713
1714         return count;
1715 }
1716
1717 static void i9xx_enable_pll(struct intel_crtc *crtc)
1718 {
1719         struct drm_device *dev = crtc->base.dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         int reg = DPLL(crtc->pipe);
1722         u32 dpll = crtc->config->dpll_hw_state.dpll;
1723
1724         assert_pipe_disabled(dev_priv, crtc->pipe);
1725
1726         /* No really, not for ILK+ */
1727         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1728
1729         /* PLL is protected by panel, make sure we can write it */
1730         if (IS_MOBILE(dev) && !IS_I830(dev))
1731                 assert_panel_unlocked(dev_priv, crtc->pipe);
1732
1733         /* Enable DVO 2x clock on both PLLs if necessary */
1734         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1735                 /*
1736                  * It appears to be important that we don't enable this
1737                  * for the current pipe before otherwise configuring the
1738                  * PLL. No idea how this should be handled if multiple
1739                  * DVO outputs are enabled simultaneosly.
1740                  */
1741                 dpll |= DPLL_DVO_2X_MODE;
1742                 I915_WRITE(DPLL(!crtc->pipe),
1743                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Wait for the clocks to stabilize. */
1747         POSTING_READ(reg);
1748         udelay(150);
1749
1750         if (INTEL_INFO(dev)->gen >= 4) {
1751                 I915_WRITE(DPLL_MD(crtc->pipe),
1752                            crtc->config->dpll_hw_state.dpll_md);
1753         } else {
1754                 /* The pixel multiplier can only be updated once the
1755                  * DPLL is enabled and the clocks are stable.
1756                  *
1757                  * So write it again.
1758                  */
1759                 I915_WRITE(reg, dpll);
1760         }
1761
1762         /* We do this three times for luck */
1763         I915_WRITE(reg, dpll);
1764         POSTING_READ(reg);
1765         udelay(150); /* wait for warmup */
1766         I915_WRITE(reg, dpll);
1767         POSTING_READ(reg);
1768         udelay(150); /* wait for warmup */
1769         I915_WRITE(reg, dpll);
1770         POSTING_READ(reg);
1771         udelay(150); /* wait for warmup */
1772 }
1773
1774 /**
1775  * i9xx_disable_pll - disable a PLL
1776  * @dev_priv: i915 private structure
1777  * @pipe: pipe PLL to disable
1778  *
1779  * Disable the PLL for @pipe, making sure the pipe is off first.
1780  *
1781  * Note!  This is for pre-ILK only.
1782  */
1783 static void i9xx_disable_pll(struct intel_crtc *crtc)
1784 {
1785         struct drm_device *dev = crtc->base.dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         enum pipe pipe = crtc->pipe;
1788
1789         /* Disable DVO 2x clock on both PLLs if necessary */
1790         if (IS_I830(dev) &&
1791             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1792             !intel_num_dvo_pipes(dev)) {
1793                 I915_WRITE(DPLL(PIPE_B),
1794                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795                 I915_WRITE(DPLL(PIPE_A),
1796                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1797         }
1798
1799         /* Don't disable pipe or pipe PLLs if needed */
1800         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1802                 return;
1803
1804         /* Make sure the pipe isn't still relying on us */
1805         assert_pipe_disabled(dev_priv, pipe);
1806
1807         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1808         POSTING_READ(DPLL(pipe));
1809 }
1810
1811 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         u32 val;
1814
1815         /* Make sure the pipe isn't still relying on us */
1816         assert_pipe_disabled(dev_priv, pipe);
1817
1818         /*
1819          * Leave integrated clock source and reference clock enabled for pipe B.
1820          * The latter is needed for VGA hotplug / manual detection.
1821          */
1822         val = DPLL_VGA_MODE_DIS;
1823         if (pipe == PIPE_B)
1824                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1825         I915_WRITE(DPLL(pipe), val);
1826         POSTING_READ(DPLL(pipe));
1827
1828 }
1829
1830 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1831 {
1832         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1833         u32 val;
1834
1835         /* Make sure the pipe isn't still relying on us */
1836         assert_pipe_disabled(dev_priv, pipe);
1837
1838         /* Set PLL en = 0 */
1839         val = DPLL_SSC_REF_CLK_CHV |
1840                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1841         if (pipe != PIPE_A)
1842                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843         I915_WRITE(DPLL(pipe), val);
1844         POSTING_READ(DPLL(pipe));
1845
1846         mutex_lock(&dev_priv->sb_lock);
1847
1848         /* Disable 10bit clock to display controller */
1849         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850         val &= ~DPIO_DCLKP_EN;
1851         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1852
1853         mutex_unlock(&dev_priv->sb_lock);
1854 }
1855
1856 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1857                          struct intel_digital_port *dport,
1858                          unsigned int expected_mask)
1859 {
1860         u32 port_mask;
1861         int dpll_reg;
1862
1863         switch (dport->port) {
1864         case PORT_B:
1865                 port_mask = DPLL_PORTB_READY_MASK;
1866                 dpll_reg = DPLL(0);
1867                 break;
1868         case PORT_C:
1869                 port_mask = DPLL_PORTC_READY_MASK;
1870                 dpll_reg = DPLL(0);
1871                 expected_mask <<= 4;
1872                 break;
1873         case PORT_D:
1874                 port_mask = DPLL_PORTD_READY_MASK;
1875                 dpll_reg = DPIO_PHY_STATUS;
1876                 break;
1877         default:
1878                 BUG();
1879         }
1880
1881         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1884 }
1885
1886 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887 {
1888         struct drm_device *dev = crtc->base.dev;
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
1892         if (WARN_ON(pll == NULL))
1893                 return;
1894
1895         WARN_ON(!pll->config.crtc_mask);
1896         if (pll->active == 0) {
1897                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898                 WARN_ON(pll->on);
1899                 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901                 pll->mode_set(dev_priv, pll);
1902         }
1903 }
1904
1905 /**
1906  * intel_enable_shared_dpll - enable PCH PLL
1907  * @dev_priv: i915 private structure
1908  * @pipe: pipe PLL to enable
1909  *
1910  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911  * drives the transcoder clock.
1912  */
1913 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915         struct drm_device *dev = crtc->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919         if (WARN_ON(pll == NULL))
1920                 return;
1921
1922         if (WARN_ON(pll->config.crtc_mask == 0))
1923                 return;
1924
1925         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1926                       pll->name, pll->active, pll->on,
1927                       crtc->base.base.id);
1928
1929         if (pll->active++) {
1930                 WARN_ON(!pll->on);
1931                 assert_shared_dpll_enabled(dev_priv, pll);
1932                 return;
1933         }
1934         WARN_ON(pll->on);
1935
1936         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
1938         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1939         pll->enable(dev_priv, pll);
1940         pll->on = true;
1941 }
1942
1943 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1944 {
1945         struct drm_device *dev = crtc->base.dev;
1946         struct drm_i915_private *dev_priv = dev->dev_private;
1947         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1948
1949         /* PCH only available on ILK+ */
1950         if (INTEL_INFO(dev)->gen < 5)
1951                 return;
1952
1953         if (pll == NULL)
1954                 return;
1955
1956         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1957                 return;
1958
1959         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960                       pll->name, pll->active, pll->on,
1961                       crtc->base.base.id);
1962
1963         if (WARN_ON(pll->active == 0)) {
1964                 assert_shared_dpll_disabled(dev_priv, pll);
1965                 return;
1966         }
1967
1968         assert_shared_dpll_enabled(dev_priv, pll);
1969         WARN_ON(!pll->on);
1970         if (--pll->active)
1971                 return;
1972
1973         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1974         pll->disable(dev_priv, pll);
1975         pll->on = false;
1976
1977         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1978 }
1979
1980 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1981                                            enum pipe pipe)
1982 {
1983         struct drm_device *dev = dev_priv->dev;
1984         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1986         uint32_t reg, val, pipeconf_val;
1987
1988         /* PCH only available on ILK+ */
1989         BUG_ON(!HAS_PCH_SPLIT(dev));
1990
1991         /* Make sure PCH DPLL is enabled */
1992         assert_shared_dpll_enabled(dev_priv,
1993                                    intel_crtc_to_shared_dpll(intel_crtc));
1994
1995         /* FDI must be feeding us bits for PCH ports */
1996         assert_fdi_tx_enabled(dev_priv, pipe);
1997         assert_fdi_rx_enabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_CPT(dev)) {
2000                 /* Workaround: Set the timing override bit before enabling the
2001                  * pch transcoder. */
2002                 reg = TRANS_CHICKEN2(pipe);
2003                 val = I915_READ(reg);
2004                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005                 I915_WRITE(reg, val);
2006         }
2007
2008         reg = PCH_TRANSCONF(pipe);
2009         val = I915_READ(reg);
2010         pipeconf_val = I915_READ(PIPECONF(pipe));
2011
2012         if (HAS_PCH_IBX(dev_priv->dev)) {
2013                 /*
2014                  * Make the BPC in transcoder be consistent with
2015                  * that in pipeconf reg. For HDMI we must use 8bpc
2016                  * here for both 8bpc and 12bpc.
2017                  */
2018                 val &= ~PIPECONF_BPC_MASK;
2019                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020                         val |= PIPECONF_8BPC;
2021                 else
2022                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2023         }
2024
2025         val &= ~TRANS_INTERLACE_MASK;
2026         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2027                 if (HAS_PCH_IBX(dev_priv->dev) &&
2028                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2029                         val |= TRANS_LEGACY_INTERLACED_ILK;
2030                 else
2031                         val |= TRANS_INTERLACED;
2032         else
2033                 val |= TRANS_PROGRESSIVE;
2034
2035         I915_WRITE(reg, val | TRANS_ENABLE);
2036         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2037                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2038 }
2039
2040 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2041                                       enum transcoder cpu_transcoder)
2042 {
2043         u32 val, pipeconf_val;
2044
2045         /* PCH only available on ILK+ */
2046         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2047
2048         /* FDI must be feeding us bits for PCH ports */
2049         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2050         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2051
2052         /* Workaround: set timing override bit. */
2053         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2054         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2055         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2056
2057         val = TRANS_ENABLE;
2058         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2059
2060         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061             PIPECONF_INTERLACED_ILK)
2062                 val |= TRANS_INTERLACED;
2063         else
2064                 val |= TRANS_PROGRESSIVE;
2065
2066         I915_WRITE(LPT_TRANSCONF, val);
2067         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2068                 DRM_ERROR("Failed to enable PCH transcoder\n");
2069 }
2070
2071 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2072                                             enum pipe pipe)
2073 {
2074         struct drm_device *dev = dev_priv->dev;
2075         uint32_t reg, val;
2076
2077         /* FDI relies on the transcoder */
2078         assert_fdi_tx_disabled(dev_priv, pipe);
2079         assert_fdi_rx_disabled(dev_priv, pipe);
2080
2081         /* Ports must be off as well */
2082         assert_pch_ports_disabled(dev_priv, pipe);
2083
2084         reg = PCH_TRANSCONF(pipe);
2085         val = I915_READ(reg);
2086         val &= ~TRANS_ENABLE;
2087         I915_WRITE(reg, val);
2088         /* wait for PCH transcoder off, transcoder state */
2089         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2090                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2091
2092         if (!HAS_PCH_IBX(dev)) {
2093                 /* Workaround: Clear the timing override chicken bit again. */
2094                 reg = TRANS_CHICKEN2(pipe);
2095                 val = I915_READ(reg);
2096                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097                 I915_WRITE(reg, val);
2098         }
2099 }
2100
2101 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2102 {
2103         u32 val;
2104
2105         val = I915_READ(LPT_TRANSCONF);
2106         val &= ~TRANS_ENABLE;
2107         I915_WRITE(LPT_TRANSCONF, val);
2108         /* wait for PCH transcoder off, transcoder state */
2109         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2110                 DRM_ERROR("Failed to disable PCH transcoder\n");
2111
2112         /* Workaround: clear timing override bit. */
2113         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2114         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2115         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2116 }
2117
2118 /**
2119  * intel_enable_pipe - enable a pipe, asserting requirements
2120  * @crtc: crtc responsible for the pipe
2121  *
2122  * Enable @crtc's pipe, making sure that various hardware specific requirements
2123  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2124  */
2125 static void intel_enable_pipe(struct intel_crtc *crtc)
2126 {
2127         struct drm_device *dev = crtc->base.dev;
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         enum pipe pipe = crtc->pipe;
2130         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2131                                                                       pipe);
2132         enum pipe pch_transcoder;
2133         int reg;
2134         u32 val;
2135
2136         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2137
2138         assert_planes_disabled(dev_priv, pipe);
2139         assert_cursor_disabled(dev_priv, pipe);
2140         assert_sprites_disabled(dev_priv, pipe);
2141
2142         if (HAS_PCH_LPT(dev_priv->dev))
2143                 pch_transcoder = TRANSCODER_A;
2144         else
2145                 pch_transcoder = pipe;
2146
2147         /*
2148          * A pipe without a PLL won't actually be able to drive bits from
2149          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2150          * need the check.
2151          */
2152         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2153                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2154                         assert_dsi_pll_enabled(dev_priv);
2155                 else
2156                         assert_pll_enabled(dev_priv, pipe);
2157         else {
2158                 if (crtc->config->has_pch_encoder) {
2159                         /* if driving the PCH, we need FDI enabled */
2160                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2161                         assert_fdi_tx_pll_enabled(dev_priv,
2162                                                   (enum pipe) cpu_transcoder);
2163                 }
2164                 /* FIXME: assert CPU port conditions for SNB+ */
2165         }
2166
2167         reg = PIPECONF(cpu_transcoder);
2168         val = I915_READ(reg);
2169         if (val & PIPECONF_ENABLE) {
2170                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2172                 return;
2173         }
2174
2175         I915_WRITE(reg, val | PIPECONF_ENABLE);
2176         POSTING_READ(reg);
2177 }
2178
2179 /**
2180  * intel_disable_pipe - disable a pipe, asserting requirements
2181  * @crtc: crtc whose pipes is to be disabled
2182  *
2183  * Disable the pipe of @crtc, making sure that various hardware
2184  * specific requirements are met, if applicable, e.g. plane
2185  * disabled, panel fitter off, etc.
2186  *
2187  * Will wait until the pipe has shut down before returning.
2188  */
2189 static void intel_disable_pipe(struct intel_crtc *crtc)
2190 {
2191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2192         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2193         enum pipe pipe = crtc->pipe;
2194         int reg;
2195         u32 val;
2196
2197         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2198
2199         /*
2200          * Make sure planes won't keep trying to pump pixels to us,
2201          * or we might hang the display.
2202          */
2203         assert_planes_disabled(dev_priv, pipe);
2204         assert_cursor_disabled(dev_priv, pipe);
2205         assert_sprites_disabled(dev_priv, pipe);
2206
2207         reg = PIPECONF(cpu_transcoder);
2208         val = I915_READ(reg);
2209         if ((val & PIPECONF_ENABLE) == 0)
2210                 return;
2211
2212         /*
2213          * Double wide has implications for planes
2214          * so best keep it disabled when not needed.
2215          */
2216         if (crtc->config->double_wide)
2217                 val &= ~PIPECONF_DOUBLE_WIDE;
2218
2219         /* Don't disable pipe or pipe PLLs if needed */
2220         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2222                 val &= ~PIPECONF_ENABLE;
2223
2224         I915_WRITE(reg, val);
2225         if ((val & PIPECONF_ENABLE) == 0)
2226                 intel_wait_for_pipe_off(crtc);
2227 }
2228
2229 static bool need_vtd_wa(struct drm_device *dev)
2230 {
2231 #ifdef CONFIG_INTEL_IOMMU
2232         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2233                 return true;
2234 #endif
2235         return false;
2236 }
2237
2238 unsigned int
2239 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2240                   uint64_t fb_format_modifier, unsigned int plane)
2241 {
2242         unsigned int tile_height;
2243         uint32_t pixel_bytes;
2244
2245         switch (fb_format_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 tile_height = 1;
2248                 break;
2249         case I915_FORMAT_MOD_X_TILED:
2250                 tile_height = IS_GEN2(dev) ? 16 : 8;
2251                 break;
2252         case I915_FORMAT_MOD_Y_TILED:
2253                 tile_height = 32;
2254                 break;
2255         case I915_FORMAT_MOD_Yf_TILED:
2256                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2257                 switch (pixel_bytes) {
2258                 default:
2259                 case 1:
2260                         tile_height = 64;
2261                         break;
2262                 case 2:
2263                 case 4:
2264                         tile_height = 32;
2265                         break;
2266                 case 8:
2267                         tile_height = 16;
2268                         break;
2269                 case 16:
2270                         WARN_ONCE(1,
2271                                   "128-bit pixels are not supported for display!");
2272                         tile_height = 16;
2273                         break;
2274                 }
2275                 break;
2276         default:
2277                 MISSING_CASE(fb_format_modifier);
2278                 tile_height = 1;
2279                 break;
2280         }
2281
2282         return tile_height;
2283 }
2284
2285 unsigned int
2286 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287                       uint32_t pixel_format, uint64_t fb_format_modifier)
2288 {
2289         return ALIGN(height, intel_tile_height(dev, pixel_format,
2290                                                fb_format_modifier, 0));
2291 }
2292
2293 static int
2294 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295                         const struct drm_plane_state *plane_state)
2296 {
2297         struct intel_rotation_info *info = &view->rotation_info;
2298         unsigned int tile_height, tile_pitch;
2299
2300         *view = i915_ggtt_view_normal;
2301
2302         if (!plane_state)
2303                 return 0;
2304
2305         if (!intel_rotation_90_or_270(plane_state->rotation))
2306                 return 0;
2307
2308         *view = i915_ggtt_view_rotated;
2309
2310         info->height = fb->height;
2311         info->pixel_format = fb->pixel_format;
2312         info->pitch = fb->pitches[0];
2313         info->uv_offset = fb->offsets[1];
2314         info->fb_modifier = fb->modifier[0];
2315
2316         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2317                                         fb->modifier[0], 0);
2318         tile_pitch = PAGE_SIZE / tile_height;
2319         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
2323         if (info->pixel_format == DRM_FORMAT_NV12) {
2324                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325                                                 fb->modifier[0], 1);
2326                 tile_pitch = PAGE_SIZE / tile_height;
2327                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2329                                                      tile_height);
2330                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2331                                 PAGE_SIZE;
2332         }
2333
2334         return 0;
2335 }
2336
2337 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2338 {
2339         if (INTEL_INFO(dev_priv)->gen >= 9)
2340                 return 256 * 1024;
2341         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342                  IS_VALLEYVIEW(dev_priv))
2343                 return 128 * 1024;
2344         else if (INTEL_INFO(dev_priv)->gen >= 4)
2345                 return 4 * 1024;
2346         else
2347                 return 0;
2348 }
2349
2350 int
2351 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352                            struct drm_framebuffer *fb,
2353                            const struct drm_plane_state *plane_state,
2354                            struct intel_engine_cs *pipelined,
2355                            struct drm_i915_gem_request **pipelined_request)
2356 {
2357         struct drm_device *dev = fb->dev;
2358         struct drm_i915_private *dev_priv = dev->dev_private;
2359         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360         struct i915_ggtt_view view;
2361         u32 alignment;
2362         int ret;
2363
2364         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
2366         switch (fb->modifier[0]) {
2367         case DRM_FORMAT_MOD_NONE:
2368                 alignment = intel_linear_alignment(dev_priv);
2369                 break;
2370         case I915_FORMAT_MOD_X_TILED:
2371                 if (INTEL_INFO(dev)->gen >= 9)
2372                         alignment = 256 * 1024;
2373                 else {
2374                         /* pin() will align the object as required by fence */
2375                         alignment = 0;
2376                 }
2377                 break;
2378         case I915_FORMAT_MOD_Y_TILED:
2379         case I915_FORMAT_MOD_Yf_TILED:
2380                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381                           "Y tiling bo slipped through, driver bug!\n"))
2382                         return -EINVAL;
2383                 alignment = 1 * 1024 * 1024;
2384                 break;
2385         default:
2386                 MISSING_CASE(fb->modifier[0]);
2387                 return -EINVAL;
2388         }
2389
2390         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2391         if (ret)
2392                 return ret;
2393
2394         /* Note that the w/a also requires 64 PTE of padding following the
2395          * bo. We currently fill all unused PTE with the shadow page and so
2396          * we should always have valid PTE following the scanout preventing
2397          * the VT-d warning.
2398          */
2399         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400                 alignment = 256 * 1024;
2401
2402         /*
2403          * Global gtt pte registers are special registers which actually forward
2404          * writes to a chunk of system memory. Which means that there is no risk
2405          * that the register values disappear as soon as we call
2406          * intel_runtime_pm_put(), so it is correct to wrap only the
2407          * pin/unpin/fence and not more.
2408          */
2409         intel_runtime_pm_get(dev_priv);
2410
2411         dev_priv->mm.interruptible = false;
2412         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2413                                                    pipelined_request, &view);
2414         if (ret)
2415                 goto err_interruptible;
2416
2417         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418          * fence, whereas 965+ only requires a fence if using
2419          * framebuffer compression.  For simplicity, we always install
2420          * a fence as the cost is not that onerous.
2421          */
2422         ret = i915_gem_object_get_fence(obj);
2423         if (ret == -EDEADLK) {
2424                 /*
2425                  * -EDEADLK means there are no free fences
2426                  * no pending flips.
2427                  *
2428                  * This is propagated to atomic, but it uses
2429                  * -EDEADLK to force a locking recovery, so
2430                  * change the returned error to -EBUSY.
2431                  */
2432                 ret = -EBUSY;
2433                 goto err_unpin;
2434         } else if (ret)
2435                 goto err_unpin;
2436
2437         i915_gem_object_pin_fence(obj);
2438
2439         dev_priv->mm.interruptible = true;
2440         intel_runtime_pm_put(dev_priv);
2441         return 0;
2442
2443 err_unpin:
2444         i915_gem_object_unpin_from_display_plane(obj, &view);
2445 err_interruptible:
2446         dev_priv->mm.interruptible = true;
2447         intel_runtime_pm_put(dev_priv);
2448         return ret;
2449 }
2450
2451 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452                                const struct drm_plane_state *plane_state)
2453 {
2454         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2455         struct i915_ggtt_view view;
2456         int ret;
2457
2458         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2459
2460         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461         WARN_ONCE(ret, "Couldn't get view from plane state!");
2462
2463         i915_gem_object_unpin_fence(obj);
2464         i915_gem_object_unpin_from_display_plane(obj, &view);
2465 }
2466
2467 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468  * is assumed to be a power-of-two. */
2469 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2470                                              int *x, int *y,
2471                                              unsigned int tiling_mode,
2472                                              unsigned int cpp,
2473                                              unsigned int pitch)
2474 {
2475         if (tiling_mode != I915_TILING_NONE) {
2476                 unsigned int tile_rows, tiles;
2477
2478                 tile_rows = *y / 8;
2479                 *y %= 8;
2480
2481                 tiles = *x / (512/cpp);
2482                 *x %= 512/cpp;
2483
2484                 return tile_rows * pitch * 8 + tiles * 4096;
2485         } else {
2486                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2487                 unsigned int offset;
2488
2489                 offset = *y * pitch + *x * cpp;
2490                 *y = (offset & alignment) / pitch;
2491                 *x = ((offset & alignment) - *y * pitch) / cpp;
2492                 return offset & ~alignment;
2493         }
2494 }
2495
2496 static int i9xx_format_to_fourcc(int format)
2497 {
2498         switch (format) {
2499         case DISPPLANE_8BPP:
2500                 return DRM_FORMAT_C8;
2501         case DISPPLANE_BGRX555:
2502                 return DRM_FORMAT_XRGB1555;
2503         case DISPPLANE_BGRX565:
2504                 return DRM_FORMAT_RGB565;
2505         default:
2506         case DISPPLANE_BGRX888:
2507                 return DRM_FORMAT_XRGB8888;
2508         case DISPPLANE_RGBX888:
2509                 return DRM_FORMAT_XBGR8888;
2510         case DISPPLANE_BGRX101010:
2511                 return DRM_FORMAT_XRGB2101010;
2512         case DISPPLANE_RGBX101010:
2513                 return DRM_FORMAT_XBGR2101010;
2514         }
2515 }
2516
2517 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2518 {
2519         switch (format) {
2520         case PLANE_CTL_FORMAT_RGB_565:
2521                 return DRM_FORMAT_RGB565;
2522         default:
2523         case PLANE_CTL_FORMAT_XRGB_8888:
2524                 if (rgb_order) {
2525                         if (alpha)
2526                                 return DRM_FORMAT_ABGR8888;
2527                         else
2528                                 return DRM_FORMAT_XBGR8888;
2529                 } else {
2530                         if (alpha)
2531                                 return DRM_FORMAT_ARGB8888;
2532                         else
2533                                 return DRM_FORMAT_XRGB8888;
2534                 }
2535         case PLANE_CTL_FORMAT_XRGB_2101010:
2536                 if (rgb_order)
2537                         return DRM_FORMAT_XBGR2101010;
2538                 else
2539                         return DRM_FORMAT_XRGB2101010;
2540         }
2541 }
2542
2543 static bool
2544 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545                               struct intel_initial_plane_config *plane_config)
2546 {
2547         struct drm_device *dev = crtc->base.dev;
2548         struct drm_i915_gem_object *obj = NULL;
2549         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2550         struct drm_framebuffer *fb = &plane_config->fb->base;
2551         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2552         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2553                                     PAGE_SIZE);
2554
2555         size_aligned -= base_aligned;
2556
2557         if (plane_config->size == 0)
2558                 return false;
2559
2560         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2561                                                              base_aligned,
2562                                                              base_aligned,
2563                                                              size_aligned);
2564         if (!obj)
2565                 return false;
2566
2567         obj->tiling_mode = plane_config->tiling;
2568         if (obj->tiling_mode == I915_TILING_X)
2569                 obj->stride = fb->pitches[0];
2570
2571         mode_cmd.pixel_format = fb->pixel_format;
2572         mode_cmd.width = fb->width;
2573         mode_cmd.height = fb->height;
2574         mode_cmd.pitches[0] = fb->pitches[0];
2575         mode_cmd.modifier[0] = fb->modifier[0];
2576         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2577
2578         mutex_lock(&dev->struct_mutex);
2579         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2580                                    &mode_cmd, obj)) {
2581                 DRM_DEBUG_KMS("intel fb init failed\n");
2582                 goto out_unref_obj;
2583         }
2584         mutex_unlock(&dev->struct_mutex);
2585
2586         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2587         return true;
2588
2589 out_unref_obj:
2590         drm_gem_object_unreference(&obj->base);
2591         mutex_unlock(&dev->struct_mutex);
2592         return false;
2593 }
2594
2595 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2596 static void
2597 update_state_fb(struct drm_plane *plane)
2598 {
2599         if (plane->fb == plane->state->fb)
2600                 return;
2601
2602         if (plane->state->fb)
2603                 drm_framebuffer_unreference(plane->state->fb);
2604         plane->state->fb = plane->fb;
2605         if (plane->state->fb)
2606                 drm_framebuffer_reference(plane->state->fb);
2607 }
2608
2609 static void
2610 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2611                              struct intel_initial_plane_config *plane_config)
2612 {
2613         struct drm_device *dev = intel_crtc->base.dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct drm_crtc *c;
2616         struct intel_crtc *i;
2617         struct drm_i915_gem_object *obj;
2618         struct drm_plane *primary = intel_crtc->base.primary;
2619         struct drm_plane_state *plane_state = primary->state;
2620         struct drm_framebuffer *fb;
2621
2622         if (!plane_config->fb)
2623                 return;
2624
2625         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2626                 fb = &plane_config->fb->base;
2627                 goto valid_fb;
2628         }
2629
2630         kfree(plane_config->fb);
2631
2632         /*
2633          * Failed to alloc the obj, check to see if we should share
2634          * an fb with another CRTC instead
2635          */
2636         for_each_crtc(dev, c) {
2637                 i = to_intel_crtc(c);
2638
2639                 if (c == &intel_crtc->base)
2640                         continue;
2641
2642                 if (!i->active)
2643                         continue;
2644
2645                 fb = c->primary->fb;
2646                 if (!fb)
2647                         continue;
2648
2649                 obj = intel_fb_obj(fb);
2650                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2651                         drm_framebuffer_reference(fb);
2652                         goto valid_fb;
2653                 }
2654         }
2655
2656         return;
2657
2658 valid_fb:
2659         plane_state->src_x = plane_state->src_y = 0;
2660         plane_state->src_w = fb->width << 16;
2661         plane_state->src_h = fb->height << 16;
2662
2663         plane_state->crtc_x = plane_state->src_y = 0;
2664         plane_state->crtc_w = fb->width;
2665         plane_state->crtc_h = fb->height;
2666
2667         obj = intel_fb_obj(fb);
2668         if (obj->tiling_mode != I915_TILING_NONE)
2669                 dev_priv->preserve_bios_swizzle = true;
2670
2671         drm_framebuffer_reference(fb);
2672         primary->fb = primary->state->fb = fb;
2673         primary->crtc = primary->state->crtc = &intel_crtc->base;
2674         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2675         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2676 }
2677
2678 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2679                                       struct drm_framebuffer *fb,
2680                                       int x, int y)
2681 {
2682         struct drm_device *dev = crtc->dev;
2683         struct drm_i915_private *dev_priv = dev->dev_private;
2684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2685         struct drm_plane *primary = crtc->primary;
2686         bool visible = to_intel_plane_state(primary->state)->visible;
2687         struct drm_i915_gem_object *obj;
2688         int plane = intel_crtc->plane;
2689         unsigned long linear_offset;
2690         u32 dspcntr;
2691         u32 reg = DSPCNTR(plane);
2692         int pixel_size;
2693
2694         if (!visible || !fb) {
2695                 I915_WRITE(reg, 0);
2696                 if (INTEL_INFO(dev)->gen >= 4)
2697                         I915_WRITE(DSPSURF(plane), 0);
2698                 else
2699                         I915_WRITE(DSPADDR(plane), 0);
2700                 POSTING_READ(reg);
2701                 return;
2702         }
2703
2704         obj = intel_fb_obj(fb);
2705         if (WARN_ON(obj == NULL))
2706                 return;
2707
2708         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2709
2710         dspcntr = DISPPLANE_GAMMA_ENABLE;
2711
2712         dspcntr |= DISPLAY_PLANE_ENABLE;
2713
2714         if (INTEL_INFO(dev)->gen < 4) {
2715                 if (intel_crtc->pipe == PIPE_B)
2716                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2717
2718                 /* pipesrc and dspsize control the size that is scaled from,
2719                  * which should always be the user's requested size.
2720                  */
2721                 I915_WRITE(DSPSIZE(plane),
2722                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723                            (intel_crtc->config->pipe_src_w - 1));
2724                 I915_WRITE(DSPPOS(plane), 0);
2725         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2726                 I915_WRITE(PRIMSIZE(plane),
2727                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2728                            (intel_crtc->config->pipe_src_w - 1));
2729                 I915_WRITE(PRIMPOS(plane), 0);
2730                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2731         }
2732
2733         switch (fb->pixel_format) {
2734         case DRM_FORMAT_C8:
2735                 dspcntr |= DISPPLANE_8BPP;
2736                 break;
2737         case DRM_FORMAT_XRGB1555:
2738                 dspcntr |= DISPPLANE_BGRX555;
2739                 break;
2740         case DRM_FORMAT_RGB565:
2741                 dspcntr |= DISPPLANE_BGRX565;
2742                 break;
2743         case DRM_FORMAT_XRGB8888:
2744                 dspcntr |= DISPPLANE_BGRX888;
2745                 break;
2746         case DRM_FORMAT_XBGR8888:
2747                 dspcntr |= DISPPLANE_RGBX888;
2748                 break;
2749         case DRM_FORMAT_XRGB2101010:
2750                 dspcntr |= DISPPLANE_BGRX101010;
2751                 break;
2752         case DRM_FORMAT_XBGR2101010:
2753                 dspcntr |= DISPPLANE_RGBX101010;
2754                 break;
2755         default:
2756                 BUG();
2757         }
2758
2759         if (INTEL_INFO(dev)->gen >= 4 &&
2760             obj->tiling_mode != I915_TILING_NONE)
2761                 dspcntr |= DISPPLANE_TILED;
2762
2763         if (IS_G4X(dev))
2764                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2765
2766         linear_offset = y * fb->pitches[0] + x * pixel_size;
2767
2768         if (INTEL_INFO(dev)->gen >= 4) {
2769                 intel_crtc->dspaddr_offset =
2770                         intel_gen4_compute_page_offset(dev_priv,
2771                                                        &x, &y, obj->tiling_mode,
2772                                                        pixel_size,
2773                                                        fb->pitches[0]);
2774                 linear_offset -= intel_crtc->dspaddr_offset;
2775         } else {
2776                 intel_crtc->dspaddr_offset = linear_offset;
2777         }
2778
2779         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2780                 dspcntr |= DISPPLANE_ROTATE_180;
2781
2782                 x += (intel_crtc->config->pipe_src_w - 1);
2783                 y += (intel_crtc->config->pipe_src_h - 1);
2784
2785                 /* Finding the last pixel of the last line of the display
2786                 data and adding to linear_offset*/
2787                 linear_offset +=
2788                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2790         }
2791
2792         intel_crtc->adjusted_x = x;
2793         intel_crtc->adjusted_y = y;
2794
2795         I915_WRITE(reg, dspcntr);
2796
2797         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2798         if (INTEL_INFO(dev)->gen >= 4) {
2799                 I915_WRITE(DSPSURF(plane),
2800                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2801                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2802                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2803         } else
2804                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2805         POSTING_READ(reg);
2806 }
2807
2808 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2809                                           struct drm_framebuffer *fb,
2810                                           int x, int y)
2811 {
2812         struct drm_device *dev = crtc->dev;
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815         struct drm_plane *primary = crtc->primary;
2816         bool visible = to_intel_plane_state(primary->state)->visible;
2817         struct drm_i915_gem_object *obj;
2818         int plane = intel_crtc->plane;
2819         unsigned long linear_offset;
2820         u32 dspcntr;
2821         u32 reg = DSPCNTR(plane);
2822         int pixel_size;
2823
2824         if (!visible || !fb) {
2825                 I915_WRITE(reg, 0);
2826                 I915_WRITE(DSPSURF(plane), 0);
2827                 POSTING_READ(reg);
2828                 return;
2829         }
2830
2831         obj = intel_fb_obj(fb);
2832         if (WARN_ON(obj == NULL))
2833                 return;
2834
2835         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2836
2837         dspcntr = DISPPLANE_GAMMA_ENABLE;
2838
2839         dspcntr |= DISPLAY_PLANE_ENABLE;
2840
2841         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2843
2844         switch (fb->pixel_format) {
2845         case DRM_FORMAT_C8:
2846                 dspcntr |= DISPPLANE_8BPP;
2847                 break;
2848         case DRM_FORMAT_RGB565:
2849                 dspcntr |= DISPPLANE_BGRX565;
2850                 break;
2851         case DRM_FORMAT_XRGB8888:
2852                 dspcntr |= DISPPLANE_BGRX888;
2853                 break;
2854         case DRM_FORMAT_XBGR8888:
2855                 dspcntr |= DISPPLANE_RGBX888;
2856                 break;
2857         case DRM_FORMAT_XRGB2101010:
2858                 dspcntr |= DISPPLANE_BGRX101010;
2859                 break;
2860         case DRM_FORMAT_XBGR2101010:
2861                 dspcntr |= DISPPLANE_RGBX101010;
2862                 break;
2863         default:
2864                 BUG();
2865         }
2866
2867         if (obj->tiling_mode != I915_TILING_NONE)
2868                 dspcntr |= DISPPLANE_TILED;
2869
2870         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2871                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2872
2873         linear_offset = y * fb->pitches[0] + x * pixel_size;
2874         intel_crtc->dspaddr_offset =
2875                 intel_gen4_compute_page_offset(dev_priv,
2876                                                &x, &y, obj->tiling_mode,
2877                                                pixel_size,
2878                                                fb->pitches[0]);
2879         linear_offset -= intel_crtc->dspaddr_offset;
2880         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2881                 dspcntr |= DISPPLANE_ROTATE_180;
2882
2883                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2884                         x += (intel_crtc->config->pipe_src_w - 1);
2885                         y += (intel_crtc->config->pipe_src_h - 1);
2886
2887                         /* Finding the last pixel of the last line of the display
2888                         data and adding to linear_offset*/
2889                         linear_offset +=
2890                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2891                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2892                 }
2893         }
2894
2895         intel_crtc->adjusted_x = x;
2896         intel_crtc->adjusted_y = y;
2897
2898         I915_WRITE(reg, dspcntr);
2899
2900         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2901         I915_WRITE(DSPSURF(plane),
2902                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2903         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2904                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2905         } else {
2906                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2907                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2908         }
2909         POSTING_READ(reg);
2910 }
2911
2912 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2913                               uint32_t pixel_format)
2914 {
2915         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2916
2917         /*
2918          * The stride is either expressed as a multiple of 64 bytes
2919          * chunks for linear buffers or in number of tiles for tiled
2920          * buffers.
2921          */
2922         switch (fb_modifier) {
2923         case DRM_FORMAT_MOD_NONE:
2924                 return 64;
2925         case I915_FORMAT_MOD_X_TILED:
2926                 if (INTEL_INFO(dev)->gen == 2)
2927                         return 128;
2928                 return 512;
2929         case I915_FORMAT_MOD_Y_TILED:
2930                 /* No need to check for old gens and Y tiling since this is
2931                  * about the display engine and those will be blocked before
2932                  * we get here.
2933                  */
2934                 return 128;
2935         case I915_FORMAT_MOD_Yf_TILED:
2936                 if (bits_per_pixel == 8)
2937                         return 64;
2938                 else
2939                         return 128;
2940         default:
2941                 MISSING_CASE(fb_modifier);
2942                 return 64;
2943         }
2944 }
2945
2946 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2947                                      struct drm_i915_gem_object *obj,
2948                                      unsigned int plane)
2949 {
2950         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2951         struct i915_vma *vma;
2952         unsigned char *offset;
2953
2954         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2955                 view = &i915_ggtt_view_rotated;
2956
2957         vma = i915_gem_obj_to_ggtt_view(obj, view);
2958         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2959                 view->type))
2960                 return -1;
2961
2962         offset = (unsigned char *)vma->node.start;
2963
2964         if (plane == 1) {
2965                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2966                           PAGE_SIZE;
2967         }
2968
2969         return (unsigned long)offset;
2970 }
2971
2972 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2973 {
2974         struct drm_device *dev = intel_crtc->base.dev;
2975         struct drm_i915_private *dev_priv = dev->dev_private;
2976
2977         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2980 }
2981
2982 /*
2983  * This function detaches (aka. unbinds) unused scalers in hardware
2984  */
2985 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2986 {
2987         struct intel_crtc_scaler_state *scaler_state;
2988         int i;
2989
2990         scaler_state = &intel_crtc->config->scaler_state;
2991
2992         /* loop through and disable scalers that aren't in use */
2993         for (i = 0; i < intel_crtc->num_scalers; i++) {
2994                 if (!scaler_state->scalers[i].in_use)
2995                         skl_detach_scaler(intel_crtc, i);
2996         }
2997 }
2998
2999 u32 skl_plane_ctl_format(uint32_t pixel_format)
3000 {
3001         switch (pixel_format) {
3002         case DRM_FORMAT_C8:
3003                 return PLANE_CTL_FORMAT_INDEXED;
3004         case DRM_FORMAT_RGB565:
3005                 return PLANE_CTL_FORMAT_RGB_565;
3006         case DRM_FORMAT_XBGR8888:
3007                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3008         case DRM_FORMAT_XRGB8888:
3009                 return PLANE_CTL_FORMAT_XRGB_8888;
3010         /*
3011          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012          * to be already pre-multiplied. We need to add a knob (or a different
3013          * DRM_FORMAT) for user-space to configure that.
3014          */
3015         case DRM_FORMAT_ABGR8888:
3016                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3017                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018         case DRM_FORMAT_ARGB8888:
3019                 return PLANE_CTL_FORMAT_XRGB_8888 |
3020                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3021         case DRM_FORMAT_XRGB2101010:
3022                 return PLANE_CTL_FORMAT_XRGB_2101010;
3023         case DRM_FORMAT_XBGR2101010:
3024                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3025         case DRM_FORMAT_YUYV:
3026                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3027         case DRM_FORMAT_YVYU:
3028                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3029         case DRM_FORMAT_UYVY:
3030                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3031         case DRM_FORMAT_VYUY:
3032                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3033         default:
3034                 MISSING_CASE(pixel_format);
3035         }
3036
3037         return 0;
3038 }
3039
3040 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3041 {
3042         switch (fb_modifier) {
3043         case DRM_FORMAT_MOD_NONE:
3044                 break;
3045         case I915_FORMAT_MOD_X_TILED:
3046                 return PLANE_CTL_TILED_X;
3047         case I915_FORMAT_MOD_Y_TILED:
3048                 return PLANE_CTL_TILED_Y;
3049         case I915_FORMAT_MOD_Yf_TILED:
3050                 return PLANE_CTL_TILED_YF;
3051         default:
3052                 MISSING_CASE(fb_modifier);
3053         }
3054
3055         return 0;
3056 }
3057
3058 u32 skl_plane_ctl_rotation(unsigned int rotation)
3059 {
3060         switch (rotation) {
3061         case BIT(DRM_ROTATE_0):
3062                 break;
3063         /*
3064          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065          * while i915 HW rotation is clockwise, thats why this swapping.
3066          */
3067         case BIT(DRM_ROTATE_90):
3068                 return PLANE_CTL_ROTATE_270;
3069         case BIT(DRM_ROTATE_180):
3070                 return PLANE_CTL_ROTATE_180;
3071         case BIT(DRM_ROTATE_270):
3072                 return PLANE_CTL_ROTATE_90;
3073         default:
3074                 MISSING_CASE(rotation);
3075         }
3076
3077         return 0;
3078 }
3079
3080 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081                                          struct drm_framebuffer *fb,
3082                                          int x, int y)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         struct drm_plane *plane = crtc->primary;
3088         bool visible = to_intel_plane_state(plane->state)->visible;
3089         struct drm_i915_gem_object *obj;
3090         int pipe = intel_crtc->pipe;
3091         u32 plane_ctl, stride_div, stride;
3092         u32 tile_height, plane_offset, plane_size;
3093         unsigned int rotation;
3094         int x_offset, y_offset;
3095         unsigned long surf_addr;
3096         struct intel_crtc_state *crtc_state = intel_crtc->config;
3097         struct intel_plane_state *plane_state;
3098         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3100         int scaler_id = -1;
3101
3102         plane_state = to_intel_plane_state(plane->state);
3103
3104         if (!visible || !fb) {
3105                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107                 POSTING_READ(PLANE_CTL(pipe, 0));
3108                 return;
3109         }
3110
3111         plane_ctl = PLANE_CTL_ENABLE |
3112                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3113                     PLANE_CTL_PIPE_CSC_ENABLE;
3114
3115         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3118
3119         rotation = plane->state->rotation;
3120         plane_ctl |= skl_plane_ctl_rotation(rotation);
3121
3122         obj = intel_fb_obj(fb);
3123         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3124                                                fb->pixel_format);
3125         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3126
3127         /*
3128          * FIXME: intel_plane_state->src, dst aren't set when transitional
3129          * update_plane helpers are called from legacy paths.
3130          * Once full atomic crtc is available, below check can be avoided.
3131          */
3132         if (drm_rect_width(&plane_state->src)) {
3133                 scaler_id = plane_state->scaler_id;
3134                 src_x = plane_state->src.x1 >> 16;
3135                 src_y = plane_state->src.y1 >> 16;
3136                 src_w = drm_rect_width(&plane_state->src) >> 16;
3137                 src_h = drm_rect_height(&plane_state->src) >> 16;
3138                 dst_x = plane_state->dst.x1;
3139                 dst_y = plane_state->dst.y1;
3140                 dst_w = drm_rect_width(&plane_state->dst);
3141                 dst_h = drm_rect_height(&plane_state->dst);
3142
3143                 WARN_ON(x != src_x || y != src_y);
3144         } else {
3145                 src_w = intel_crtc->config->pipe_src_w;
3146                 src_h = intel_crtc->config->pipe_src_h;
3147         }
3148
3149         if (intel_rotation_90_or_270(rotation)) {
3150                 /* stride = Surface height in tiles */
3151                 tile_height = intel_tile_height(dev, fb->pixel_format,
3152                                                 fb->modifier[0], 0);
3153                 stride = DIV_ROUND_UP(fb->height, tile_height);
3154                 x_offset = stride * tile_height - y - src_h;
3155                 y_offset = x;
3156                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3157         } else {
3158                 stride = fb->pitches[0] / stride_div;
3159                 x_offset = x;
3160                 y_offset = y;
3161                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3162         }
3163         plane_offset = y_offset << 16 | x_offset;
3164
3165         intel_crtc->adjusted_x = x_offset;
3166         intel_crtc->adjusted_y = y_offset;
3167
3168         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3169         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3170         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3171         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3172
3173         if (scaler_id >= 0) {
3174                 uint32_t ps_ctrl = 0;
3175
3176                 WARN_ON(!dst_w || !dst_h);
3177                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3178                         crtc_state->scaler_state.scalers[scaler_id].mode;
3179                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3180                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3181                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3182                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3183                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3184         } else {
3185                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3186         }
3187
3188         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3189
3190         POSTING_READ(PLANE_SURF(pipe, 0));
3191 }
3192
3193 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3194 static int
3195 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3196                            int x, int y, enum mode_set_atomic state)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200
3201         if (dev_priv->fbc.disable_fbc)
3202                 dev_priv->fbc.disable_fbc(dev_priv);
3203
3204         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3205
3206         return 0;
3207 }
3208
3209 static void intel_complete_page_flips(struct drm_device *dev)
3210 {
3211         struct drm_crtc *crtc;
3212
3213         for_each_crtc(dev, crtc) {
3214                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215                 enum plane plane = intel_crtc->plane;
3216
3217                 intel_prepare_page_flip(dev, plane);
3218                 intel_finish_page_flip_plane(dev, plane);
3219         }
3220 }
3221
3222 static void intel_update_primary_planes(struct drm_device *dev)
3223 {
3224         struct drm_crtc *crtc;
3225
3226         for_each_crtc(dev, crtc) {
3227                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3228                 struct intel_plane_state *plane_state;
3229
3230                 drm_modeset_lock_crtc(crtc, &plane->base);
3231
3232                 plane_state = to_intel_plane_state(plane->base.state);
3233
3234                 if (plane_state->base.fb)
3235                         plane->commit_plane(&plane->base, plane_state);
3236
3237                 drm_modeset_unlock_crtc(crtc);
3238         }
3239 }
3240
3241 void intel_prepare_reset(struct drm_device *dev)
3242 {
3243         /* no reset support for gen2 */
3244         if (IS_GEN2(dev))
3245                 return;
3246
3247         /* reset doesn't touch the display */
3248         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3249                 return;
3250
3251         drm_modeset_lock_all(dev);
3252         /*
3253          * Disabling the crtcs gracefully seems nicer. Also the
3254          * g33 docs say we should at least disable all the planes.
3255          */
3256         intel_display_suspend(dev);
3257 }
3258
3259 void intel_finish_reset(struct drm_device *dev)
3260 {
3261         struct drm_i915_private *dev_priv = to_i915(dev);
3262
3263         /*
3264          * Flips in the rings will be nuked by the reset,
3265          * so complete all pending flips so that user space
3266          * will get its events and not get stuck.
3267          */
3268         intel_complete_page_flips(dev);
3269
3270         /* no reset support for gen2 */
3271         if (IS_GEN2(dev))
3272                 return;
3273
3274         /* reset doesn't touch the display */
3275         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3276                 /*
3277                  * Flips in the rings have been nuked by the reset,
3278                  * so update the base address of all primary
3279                  * planes to the the last fb to make sure we're
3280                  * showing the correct fb after a reset.
3281                  *
3282                  * FIXME: Atomic will make this obsolete since we won't schedule
3283                  * CS-based flips (which might get lost in gpu resets) any more.
3284                  */
3285                 intel_update_primary_planes(dev);
3286                 return;
3287         }
3288
3289         /*
3290          * The display has been reset as well,
3291          * so need a full re-initialization.
3292          */
3293         intel_runtime_pm_disable_interrupts(dev_priv);
3294         intel_runtime_pm_enable_interrupts(dev_priv);
3295
3296         intel_modeset_init_hw(dev);
3297
3298         spin_lock_irq(&dev_priv->irq_lock);
3299         if (dev_priv->display.hpd_irq_setup)
3300                 dev_priv->display.hpd_irq_setup(dev);
3301         spin_unlock_irq(&dev_priv->irq_lock);
3302
3303         intel_display_resume(dev);
3304
3305         intel_hpd_init(dev_priv);
3306
3307         drm_modeset_unlock_all(dev);
3308 }
3309
3310 static void
3311 intel_finish_fb(struct drm_framebuffer *old_fb)
3312 {
3313         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3314         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3315         bool was_interruptible = dev_priv->mm.interruptible;
3316         int ret;
3317
3318         /* Big Hammer, we also need to ensure that any pending
3319          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3320          * current scanout is retired before unpinning the old
3321          * framebuffer. Note that we rely on userspace rendering
3322          * into the buffer attached to the pipe they are waiting
3323          * on. If not, userspace generates a GPU hang with IPEHR
3324          * point to the MI_WAIT_FOR_EVENT.
3325          *
3326          * This should only fail upon a hung GPU, in which case we
3327          * can safely continue.
3328          */
3329         dev_priv->mm.interruptible = false;
3330         ret = i915_gem_object_wait_rendering(obj, true);
3331         dev_priv->mm.interruptible = was_interruptible;
3332
3333         WARN_ON(ret);
3334 }
3335
3336 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3337 {
3338         struct drm_device *dev = crtc->dev;
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341         bool pending;
3342
3343         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3344             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3345                 return false;
3346
3347         spin_lock_irq(&dev->event_lock);
3348         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3349         spin_unlock_irq(&dev->event_lock);
3350
3351         return pending;
3352 }
3353
3354 static void intel_update_pipe_config(struct intel_crtc *crtc,
3355                                      struct intel_crtc_state *old_crtc_state)
3356 {
3357         struct drm_device *dev = crtc->base.dev;
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         struct intel_crtc_state *pipe_config =
3360                 to_intel_crtc_state(crtc->base.state);
3361
3362         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3363         crtc->base.mode = crtc->base.state->mode;
3364
3365         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3366                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3367                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3368
3369         if (HAS_DDI(dev))
3370                 intel_set_pipe_csc(&crtc->base);
3371
3372         /*
3373          * Update pipe size and adjust fitter if needed: the reason for this is
3374          * that in compute_mode_changes we check the native mode (not the pfit
3375          * mode) to see if we can flip rather than do a full mode set. In the
3376          * fastboot case, we'll flip, but if we don't update the pipesrc and
3377          * pfit state, we'll end up with a big fb scanned out into the wrong
3378          * sized surface.
3379          */
3380
3381         I915_WRITE(PIPESRC(crtc->pipe),
3382                    ((pipe_config->pipe_src_w - 1) << 16) |
3383                    (pipe_config->pipe_src_h - 1));
3384
3385         /* on skylake this is done by detaching scalers */
3386         if (INTEL_INFO(dev)->gen >= 9) {
3387                 skl_detach_scalers(crtc);
3388
3389                 if (pipe_config->pch_pfit.enabled)
3390                         skylake_pfit_enable(crtc);
3391         } else if (HAS_PCH_SPLIT(dev)) {
3392                 if (pipe_config->pch_pfit.enabled)
3393                         ironlake_pfit_enable(crtc);
3394                 else if (old_crtc_state->pch_pfit.enabled)
3395                         ironlake_pfit_disable(crtc, true);
3396         }
3397 }
3398
3399 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3400 {
3401         struct drm_device *dev = crtc->dev;
3402         struct drm_i915_private *dev_priv = dev->dev_private;
3403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404         int pipe = intel_crtc->pipe;
3405         u32 reg, temp;
3406
3407         /* enable normal train */
3408         reg = FDI_TX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         if (IS_IVYBRIDGE(dev)) {
3411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3413         } else {
3414                 temp &= ~FDI_LINK_TRAIN_NONE;
3415                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3416         }
3417         I915_WRITE(reg, temp);
3418
3419         reg = FDI_RX_CTL(pipe);
3420         temp = I915_READ(reg);
3421         if (HAS_PCH_CPT(dev)) {
3422                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3423                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3424         } else {
3425                 temp &= ~FDI_LINK_TRAIN_NONE;
3426                 temp |= FDI_LINK_TRAIN_NONE;
3427         }
3428         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3429
3430         /* wait one idle pattern time */
3431         POSTING_READ(reg);
3432         udelay(1000);
3433
3434         /* IVB wants error correction enabled */
3435         if (IS_IVYBRIDGE(dev))
3436                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437                            FDI_FE_ERRC_ENABLE);
3438 }
3439
3440 /* The FDI link training functions for ILK/Ibexpeak. */
3441 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3442 {
3443         struct drm_device *dev = crtc->dev;
3444         struct drm_i915_private *dev_priv = dev->dev_private;
3445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446         int pipe = intel_crtc->pipe;
3447         u32 reg, temp, tries;
3448
3449         /* FDI needs bits from pipe first */
3450         assert_pipe_enabled(dev_priv, pipe);
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459         I915_READ(reg);
3460         udelay(150);
3461
3462         /* enable CPU FDI TX and PCH FDI RX */
3463         reg = FDI_TX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467         temp &= ~FDI_LINK_TRAIN_NONE;
3468         temp |= FDI_LINK_TRAIN_PATTERN_1;
3469         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3470
3471         reg = FDI_RX_CTL(pipe);
3472         temp = I915_READ(reg);
3473         temp &= ~FDI_LINK_TRAIN_NONE;
3474         temp |= FDI_LINK_TRAIN_PATTERN_1;
3475         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3476
3477         POSTING_READ(reg);
3478         udelay(150);
3479
3480         /* Ironlake workaround, enable clock pointer after FDI enable*/
3481         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3482         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3483                    FDI_RX_PHASE_SYNC_POINTER_EN);
3484
3485         reg = FDI_RX_IIR(pipe);
3486         for (tries = 0; tries < 5; tries++) {
3487                 temp = I915_READ(reg);
3488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489
3490                 if ((temp & FDI_RX_BIT_LOCK)) {
3491                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3492                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3493                         break;
3494                 }
3495         }
3496         if (tries == 5)
3497                 DRM_ERROR("FDI train 1 fail!\n");
3498
3499         /* Train 2 */
3500         reg = FDI_TX_CTL(pipe);
3501         temp = I915_READ(reg);
3502         temp &= ~FDI_LINK_TRAIN_NONE;
3503         temp |= FDI_LINK_TRAIN_PATTERN_2;
3504         I915_WRITE(reg, temp);
3505
3506         reg = FDI_RX_CTL(pipe);
3507         temp = I915_READ(reg);
3508         temp &= ~FDI_LINK_TRAIN_NONE;
3509         temp |= FDI_LINK_TRAIN_PATTERN_2;
3510         I915_WRITE(reg, temp);
3511
3512         POSTING_READ(reg);
3513         udelay(150);
3514
3515         reg = FDI_RX_IIR(pipe);
3516         for (tries = 0; tries < 5; tries++) {
3517                 temp = I915_READ(reg);
3518                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519
3520                 if (temp & FDI_RX_SYMBOL_LOCK) {
3521                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3522                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3523                         break;
3524                 }
3525         }
3526         if (tries == 5)
3527                 DRM_ERROR("FDI train 2 fail!\n");
3528
3529         DRM_DEBUG_KMS("FDI train done\n");
3530
3531 }
3532
3533 static const int snb_b_fdi_train_param[] = {
3534         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3535         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3536         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3537         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3538 };
3539
3540 /* The FDI link training functions for SNB/Cougarpoint. */
3541 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3542 {
3543         struct drm_device *dev = crtc->dev;
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546         int pipe = intel_crtc->pipe;
3547         u32 reg, temp, i, retry;
3548
3549         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3550            for train result */
3551         reg = FDI_RX_IMR(pipe);
3552         temp = I915_READ(reg);
3553         temp &= ~FDI_RX_SYMBOL_LOCK;
3554         temp &= ~FDI_RX_BIT_LOCK;
3555         I915_WRITE(reg, temp);
3556
3557         POSTING_READ(reg);
3558         udelay(150);
3559
3560         /* enable CPU FDI TX and PCH FDI RX */
3561         reg = FDI_TX_CTL(pipe);
3562         temp = I915_READ(reg);
3563         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3564         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3565         temp &= ~FDI_LINK_TRAIN_NONE;
3566         temp |= FDI_LINK_TRAIN_PATTERN_1;
3567         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568         /* SNB-B */
3569         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3570         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3571
3572         I915_WRITE(FDI_RX_MISC(pipe),
3573                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3574
3575         reg = FDI_RX_CTL(pipe);
3576         temp = I915_READ(reg);
3577         if (HAS_PCH_CPT(dev)) {
3578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3580         } else {
3581                 temp &= ~FDI_LINK_TRAIN_NONE;
3582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3583         }
3584         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3585
3586         POSTING_READ(reg);
3587         udelay(150);
3588
3589         for (i = 0; i < 4; i++) {
3590                 reg = FDI_TX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593                 temp |= snb_b_fdi_train_param[i];
3594                 I915_WRITE(reg, temp);
3595
3596                 POSTING_READ(reg);
3597                 udelay(500);
3598
3599                 for (retry = 0; retry < 5; retry++) {
3600                         reg = FDI_RX_IIR(pipe);
3601                         temp = I915_READ(reg);
3602                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603                         if (temp & FDI_RX_BIT_LOCK) {
3604                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3606                                 break;
3607                         }
3608                         udelay(50);
3609                 }
3610                 if (retry < 5)
3611                         break;
3612         }
3613         if (i == 4)
3614                 DRM_ERROR("FDI train 1 fail!\n");
3615
3616         /* Train 2 */
3617         reg = FDI_TX_CTL(pipe);
3618         temp = I915_READ(reg);
3619         temp &= ~FDI_LINK_TRAIN_NONE;
3620         temp |= FDI_LINK_TRAIN_PATTERN_2;
3621         if (IS_GEN6(dev)) {
3622                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623                 /* SNB-B */
3624                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3625         }
3626         I915_WRITE(reg, temp);
3627
3628         reg = FDI_RX_CTL(pipe);
3629         temp = I915_READ(reg);
3630         if (HAS_PCH_CPT(dev)) {
3631                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3632                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3633         } else {
3634                 temp &= ~FDI_LINK_TRAIN_NONE;
3635                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3636         }
3637         I915_WRITE(reg, temp);
3638
3639         POSTING_READ(reg);
3640         udelay(150);
3641
3642         for (i = 0; i < 4; i++) {
3643                 reg = FDI_TX_CTL(pipe);
3644                 temp = I915_READ(reg);
3645                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3646                 temp |= snb_b_fdi_train_param[i];
3647                 I915_WRITE(reg, temp);
3648
3649                 POSTING_READ(reg);
3650                 udelay(500);
3651
3652                 for (retry = 0; retry < 5; retry++) {
3653                         reg = FDI_RX_IIR(pipe);
3654                         temp = I915_READ(reg);
3655                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3656                         if (temp & FDI_RX_SYMBOL_LOCK) {
3657                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3659                                 break;
3660                         }
3661                         udelay(50);
3662                 }
3663                 if (retry < 5)
3664                         break;
3665         }
3666         if (i == 4)
3667                 DRM_ERROR("FDI train 2 fail!\n");
3668
3669         DRM_DEBUG_KMS("FDI train done.\n");
3670 }
3671
3672 /* Manual link training for Ivy Bridge A0 parts */
3673 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->dev;
3676         struct drm_i915_private *dev_priv = dev->dev_private;
3677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678         int pipe = intel_crtc->pipe;
3679         u32 reg, temp, i, j;
3680
3681         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3682            for train result */
3683         reg = FDI_RX_IMR(pipe);
3684         temp = I915_READ(reg);
3685         temp &= ~FDI_RX_SYMBOL_LOCK;
3686         temp &= ~FDI_RX_BIT_LOCK;
3687         I915_WRITE(reg, temp);
3688
3689         POSTING_READ(reg);
3690         udelay(150);
3691
3692         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3693                       I915_READ(FDI_RX_IIR(pipe)));
3694
3695         /* Try each vswing and preemphasis setting twice before moving on */
3696         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3697                 /* disable first in case we need to retry */
3698                 reg = FDI_TX_CTL(pipe);
3699                 temp = I915_READ(reg);
3700                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3701                 temp &= ~FDI_TX_ENABLE;
3702                 I915_WRITE(reg, temp);
3703
3704                 reg = FDI_RX_CTL(pipe);
3705                 temp = I915_READ(reg);
3706                 temp &= ~FDI_LINK_TRAIN_AUTO;
3707                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708                 temp &= ~FDI_RX_ENABLE;
3709                 I915_WRITE(reg, temp);
3710
3711                 /* enable CPU FDI TX and PCH FDI RX */
3712                 reg = FDI_TX_CTL(pipe);
3713                 temp = I915_READ(reg);
3714                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3715                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3716                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3717                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3718                 temp |= snb_b_fdi_train_param[j/2];
3719                 temp |= FDI_COMPOSITE_SYNC;
3720                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3721
3722                 I915_WRITE(FDI_RX_MISC(pipe),
3723                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3724
3725                 reg = FDI_RX_CTL(pipe);
3726                 temp = I915_READ(reg);
3727                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728                 temp |= FDI_COMPOSITE_SYNC;
3729                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3730
3731                 POSTING_READ(reg);
3732                 udelay(1); /* should be 0.5us */
3733
3734                 for (i = 0; i < 4; i++) {
3735                         reg = FDI_RX_IIR(pipe);
3736                         temp = I915_READ(reg);
3737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739                         if (temp & FDI_RX_BIT_LOCK ||
3740                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3741                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3742                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3743                                               i);
3744                                 break;
3745                         }
3746                         udelay(1); /* should be 0.5us */
3747                 }
3748                 if (i == 4) {
3749                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3750                         continue;
3751                 }
3752
3753                 /* Train 2 */
3754                 reg = FDI_TX_CTL(pipe);
3755                 temp = I915_READ(reg);
3756                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3757                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3758                 I915_WRITE(reg, temp);
3759
3760                 reg = FDI_RX_CTL(pipe);
3761                 temp = I915_READ(reg);
3762                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3763                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3764                 I915_WRITE(reg, temp);
3765
3766                 POSTING_READ(reg);
3767                 udelay(2); /* should be 1.5us */
3768
3769                 for (i = 0; i < 4; i++) {
3770                         reg = FDI_RX_IIR(pipe);
3771                         temp = I915_READ(reg);
3772                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3773
3774                         if (temp & FDI_RX_SYMBOL_LOCK ||
3775                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3776                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3777                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3778                                               i);
3779                                 goto train_done;
3780                         }
3781                         udelay(2); /* should be 1.5us */
3782                 }
3783                 if (i == 4)
3784                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3785         }
3786
3787 train_done:
3788         DRM_DEBUG_KMS("FDI train done.\n");
3789 }
3790
3791 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3792 {
3793         struct drm_device *dev = intel_crtc->base.dev;
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         int pipe = intel_crtc->pipe;
3796         u32 reg, temp;
3797
3798
3799         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3800         reg = FDI_RX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3803         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3804         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3805         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3806
3807         POSTING_READ(reg);
3808         udelay(200);
3809
3810         /* Switch from Rawclk to PCDclk */
3811         temp = I915_READ(reg);
3812         I915_WRITE(reg, temp | FDI_PCDCLK);
3813
3814         POSTING_READ(reg);
3815         udelay(200);
3816
3817         /* Enable CPU FDI TX PLL, always on for Ironlake */
3818         reg = FDI_TX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3821                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3822
3823                 POSTING_READ(reg);
3824                 udelay(100);
3825         }
3826 }
3827
3828 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3829 {
3830         struct drm_device *dev = intel_crtc->base.dev;
3831         struct drm_i915_private *dev_priv = dev->dev_private;
3832         int pipe = intel_crtc->pipe;
3833         u32 reg, temp;
3834
3835         /* Switch from PCDclk to Rawclk */
3836         reg = FDI_RX_CTL(pipe);
3837         temp = I915_READ(reg);
3838         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3839
3840         /* Disable CPU FDI TX PLL */
3841         reg = FDI_TX_CTL(pipe);
3842         temp = I915_READ(reg);
3843         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3844
3845         POSTING_READ(reg);
3846         udelay(100);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3851
3852         /* Wait for the clocks to turn off. */
3853         POSTING_READ(reg);
3854         udelay(100);
3855 }
3856
3857 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3858 {
3859         struct drm_device *dev = crtc->dev;
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862         int pipe = intel_crtc->pipe;
3863         u32 reg, temp;
3864
3865         /* disable CPU FDI tx and PCH FDI rx */
3866         reg = FDI_TX_CTL(pipe);
3867         temp = I915_READ(reg);
3868         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3869         POSTING_READ(reg);
3870
3871         reg = FDI_RX_CTL(pipe);
3872         temp = I915_READ(reg);
3873         temp &= ~(0x7 << 16);
3874         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3875         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3876
3877         POSTING_READ(reg);
3878         udelay(100);
3879
3880         /* Ironlake workaround, disable clock pointer after downing FDI */
3881         if (HAS_PCH_IBX(dev))
3882                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3883
3884         /* still set train pattern 1 */
3885         reg = FDI_TX_CTL(pipe);
3886         temp = I915_READ(reg);
3887         temp &= ~FDI_LINK_TRAIN_NONE;
3888         temp |= FDI_LINK_TRAIN_PATTERN_1;
3889         I915_WRITE(reg, temp);
3890
3891         reg = FDI_RX_CTL(pipe);
3892         temp = I915_READ(reg);
3893         if (HAS_PCH_CPT(dev)) {
3894                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3895                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3896         } else {
3897                 temp &= ~FDI_LINK_TRAIN_NONE;
3898                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3899         }
3900         /* BPC in FDI rx is consistent with that in PIPECONF */
3901         temp &= ~(0x07 << 16);
3902         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3903         I915_WRITE(reg, temp);
3904
3905         POSTING_READ(reg);
3906         udelay(100);
3907 }
3908
3909 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3910 {
3911         struct intel_crtc *crtc;
3912
3913         /* Note that we don't need to be called with mode_config.lock here
3914          * as our list of CRTC objects is static for the lifetime of the
3915          * device and so cannot disappear as we iterate. Similarly, we can
3916          * happily treat the predicates as racy, atomic checks as userspace
3917          * cannot claim and pin a new fb without at least acquring the
3918          * struct_mutex and so serialising with us.
3919          */
3920         for_each_intel_crtc(dev, crtc) {
3921                 if (atomic_read(&crtc->unpin_work_count) == 0)
3922                         continue;
3923
3924                 if (crtc->unpin_work)
3925                         intel_wait_for_vblank(dev, crtc->pipe);
3926
3927                 return true;
3928         }
3929
3930         return false;
3931 }
3932
3933 static void page_flip_completed(struct intel_crtc *intel_crtc)
3934 {
3935         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3936         struct intel_unpin_work *work = intel_crtc->unpin_work;
3937
3938         /* ensure that the unpin work is consistent wrt ->pending. */
3939         smp_rmb();
3940         intel_crtc->unpin_work = NULL;
3941
3942         if (work->event)
3943                 drm_send_vblank_event(intel_crtc->base.dev,
3944                                       intel_crtc->pipe,
3945                                       work->event);
3946
3947         drm_crtc_vblank_put(&intel_crtc->base);
3948
3949         wake_up_all(&dev_priv->pending_flip_queue);
3950         queue_work(dev_priv->wq, &work->work);
3951
3952         trace_i915_flip_complete(intel_crtc->plane,
3953                                  work->pending_flip_obj);
3954 }
3955
3956 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960
3961         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3962         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3963                                        !intel_crtc_has_pending_flip(crtc),
3964                                        60*HZ) == 0)) {
3965                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966
3967                 spin_lock_irq(&dev->event_lock);
3968                 if (intel_crtc->unpin_work) {
3969                         WARN_ONCE(1, "Removing stuck page flip\n");
3970                         page_flip_completed(intel_crtc);
3971                 }
3972                 spin_unlock_irq(&dev->event_lock);
3973         }
3974
3975         if (crtc->primary->fb) {
3976                 mutex_lock(&dev->struct_mutex);
3977                 intel_finish_fb(crtc->primary->fb);
3978                 mutex_unlock(&dev->struct_mutex);
3979         }
3980 }
3981
3982 /* Program iCLKIP clock to the desired frequency */
3983 static void lpt_program_iclkip(struct drm_crtc *crtc)
3984 {
3985         struct drm_device *dev = crtc->dev;
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3988         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3989         u32 temp;
3990
3991         mutex_lock(&dev_priv->sb_lock);
3992
3993         /* It is necessary to ungate the pixclk gate prior to programming
3994          * the divisors, and gate it back when it is done.
3995          */
3996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3997
3998         /* Disable SSCCTL */
3999         intel_sbi_write(dev_priv, SBI_SSCCTL6,
4000                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4001                                 SBI_SSCCTL_DISABLE,
4002                         SBI_ICLK);
4003
4004         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4005         if (clock == 20000) {
4006                 auxdiv = 1;
4007                 divsel = 0x41;
4008                 phaseinc = 0x20;
4009         } else {
4010                 /* The iCLK virtual clock root frequency is in MHz,
4011                  * but the adjusted_mode->crtc_clock in in KHz. To get the
4012                  * divisors, it is necessary to divide one by another, so we
4013                  * convert the virtual clock precision to KHz here for higher
4014                  * precision.
4015                  */
4016                 u32 iclk_virtual_root_freq = 172800 * 1000;
4017                 u32 iclk_pi_range = 64;
4018                 u32 desired_divisor, msb_divisor_value, pi_value;
4019
4020                 desired_divisor = (iclk_virtual_root_freq / clock);
4021                 msb_divisor_value = desired_divisor / iclk_pi_range;
4022                 pi_value = desired_divisor % iclk_pi_range;
4023
4024                 auxdiv = 0;
4025                 divsel = msb_divisor_value - 2;
4026                 phaseinc = pi_value;
4027         }
4028
4029         /* This should not happen with any sane values */
4030         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4034
4035         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4036                         clock,
4037                         auxdiv,
4038                         divsel,
4039                         phasedir,
4040                         phaseinc);
4041
4042         /* Program SSCDIVINTPHASE6 */
4043         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4044         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4050         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4051
4052         /* Program SSCAUXDIV */
4053         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4054         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4056         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4057
4058         /* Enable modulator and associated divider */
4059         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4060         temp &= ~SBI_SSCCTL_DISABLE;
4061         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4062
4063         /* Wait for initialization time */
4064         udelay(24);
4065
4066         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4067
4068         mutex_unlock(&dev_priv->sb_lock);
4069 }
4070
4071 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072                                                 enum pipe pch_transcoder)
4073 {
4074         struct drm_device *dev = crtc->base.dev;
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4077
4078         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079                    I915_READ(HTOTAL(cpu_transcoder)));
4080         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081                    I915_READ(HBLANK(cpu_transcoder)));
4082         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083                    I915_READ(HSYNC(cpu_transcoder)));
4084
4085         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086                    I915_READ(VTOTAL(cpu_transcoder)));
4087         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088                    I915_READ(VBLANK(cpu_transcoder)));
4089         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090                    I915_READ(VSYNC(cpu_transcoder)));
4091         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4093 }
4094
4095 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4096 {
4097         struct drm_i915_private *dev_priv = dev->dev_private;
4098         uint32_t temp;
4099
4100         temp = I915_READ(SOUTH_CHICKEN1);
4101         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4102                 return;
4103
4104         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4106
4107         temp &= ~FDI_BC_BIFURCATION_SELECT;
4108         if (enable)
4109                 temp |= FDI_BC_BIFURCATION_SELECT;
4110
4111         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4112         I915_WRITE(SOUTH_CHICKEN1, temp);
4113         POSTING_READ(SOUTH_CHICKEN1);
4114 }
4115
4116 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4117 {
4118         struct drm_device *dev = intel_crtc->base.dev;
4119
4120         switch (intel_crtc->pipe) {
4121         case PIPE_A:
4122                 break;
4123         case PIPE_B:
4124                 if (intel_crtc->config->fdi_lanes > 2)
4125                         cpt_set_fdi_bc_bifurcation(dev, false);
4126                 else
4127                         cpt_set_fdi_bc_bifurcation(dev, true);
4128
4129                 break;
4130         case PIPE_C:
4131                 cpt_set_fdi_bc_bifurcation(dev, true);
4132
4133                 break;
4134         default:
4135                 BUG();
4136         }
4137 }
4138
4139 /*
4140  * Enable PCH resources required for PCH ports:
4141  *   - PCH PLLs
4142  *   - FDI training & RX/TX
4143  *   - update transcoder timings
4144  *   - DP transcoding bits
4145  *   - transcoder
4146  */
4147 static void ironlake_pch_enable(struct drm_crtc *crtc)
4148 {
4149         struct drm_device *dev = crtc->dev;
4150         struct drm_i915_private *dev_priv = dev->dev_private;
4151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152         int pipe = intel_crtc->pipe;
4153         u32 reg, temp;
4154
4155         assert_pch_transcoder_disabled(dev_priv, pipe);
4156
4157         if (IS_IVYBRIDGE(dev))
4158                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4159
4160         /* Write the TU size bits before fdi link training, so that error
4161          * detection works. */
4162         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4164
4165         /* For PCH output, training FDI link */
4166         dev_priv->display.fdi_link_train(crtc);
4167
4168         /* We need to program the right clock selection before writing the pixel
4169          * mutliplier into the DPLL. */
4170         if (HAS_PCH_CPT(dev)) {
4171                 u32 sel;
4172
4173                 temp = I915_READ(PCH_DPLL_SEL);
4174                 temp |= TRANS_DPLL_ENABLE(pipe);
4175                 sel = TRANS_DPLLB_SEL(pipe);
4176                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4177                         temp |= sel;
4178                 else
4179                         temp &= ~sel;
4180                 I915_WRITE(PCH_DPLL_SEL, temp);
4181         }
4182
4183         /* XXX: pch pll's can be enabled any time before we enable the PCH
4184          * transcoder, and we actually should do this to not upset any PCH
4185          * transcoder that already use the clock when we share it.
4186          *
4187          * Note that enable_shared_dpll tries to do the right thing, but
4188          * get_shared_dpll unconditionally resets the pll - we need that to have
4189          * the right LVDS enable sequence. */
4190         intel_enable_shared_dpll(intel_crtc);
4191
4192         /* set transcoder timing, panel must allow it */
4193         assert_panel_unlocked(dev_priv, pipe);
4194         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4195
4196         intel_fdi_normal_train(crtc);
4197
4198         /* For PCH DP, enable TRANS_DP_CTL */
4199         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4200                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4201                 reg = TRANS_DP_CTL(pipe);
4202                 temp = I915_READ(reg);
4203                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4204                           TRANS_DP_SYNC_MASK |
4205                           TRANS_DP_BPC_MASK);
4206                 temp |= TRANS_DP_OUTPUT_ENABLE;
4207                 temp |= bpc << 9; /* same format but at 11:9 */
4208
4209                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4210                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4211                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4212                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4213
4214                 switch (intel_trans_dp_port_sel(crtc)) {
4215                 case PCH_DP_B:
4216                         temp |= TRANS_DP_PORT_SEL_B;
4217                         break;
4218                 case PCH_DP_C:
4219                         temp |= TRANS_DP_PORT_SEL_C;
4220                         break;
4221                 case PCH_DP_D:
4222                         temp |= TRANS_DP_PORT_SEL_D;
4223                         break;
4224                 default:
4225                         BUG();
4226                 }
4227
4228                 I915_WRITE(reg, temp);
4229         }
4230
4231         ironlake_enable_pch_transcoder(dev_priv, pipe);
4232 }
4233
4234 static void lpt_pch_enable(struct drm_crtc *crtc)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4240
4241         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4242
4243         lpt_program_iclkip(crtc);
4244
4245         /* Set transcoder timing. */
4246         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4247
4248         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4249 }
4250
4251 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252                                                 struct intel_crtc_state *crtc_state)
4253 {
4254         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4255         struct intel_shared_dpll *pll;
4256         struct intel_shared_dpll_config *shared_dpll;
4257         enum intel_dpll_id i;
4258
4259         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4260
4261         if (HAS_PCH_IBX(dev_priv->dev)) {
4262                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4263                 i = (enum intel_dpll_id) crtc->pipe;
4264                 pll = &dev_priv->shared_dplls[i];
4265
4266                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267                               crtc->base.base.id, pll->name);
4268
4269                 WARN_ON(shared_dpll[i].crtc_mask);
4270
4271                 goto found;
4272         }
4273
4274         if (IS_BROXTON(dev_priv->dev)) {
4275                 /* PLL is attached to port in bxt */
4276                 struct intel_encoder *encoder;
4277                 struct intel_digital_port *intel_dig_port;
4278
4279                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280                 if (WARN_ON(!encoder))
4281                         return NULL;
4282
4283                 intel_dig_port = enc_to_dig_port(&encoder->base);
4284                 /* 1:1 mapping between ports and PLLs */
4285                 i = (enum intel_dpll_id)intel_dig_port->port;
4286                 pll = &dev_priv->shared_dplls[i];
4287                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288                         crtc->base.base.id, pll->name);
4289                 WARN_ON(shared_dpll[i].crtc_mask);
4290
4291                 goto found;
4292         }
4293
4294         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295                 pll = &dev_priv->shared_dplls[i];
4296
4297                 /* Only want to check enabled timings first */
4298                 if (shared_dpll[i].crtc_mask == 0)
4299                         continue;
4300
4301                 if (memcmp(&crtc_state->dpll_hw_state,
4302                            &shared_dpll[i].hw_state,
4303                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4304                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4305                                       crtc->base.base.id, pll->name,
4306                                       shared_dpll[i].crtc_mask,
4307                                       pll->active);
4308                         goto found;
4309                 }
4310         }
4311
4312         /* Ok no matching timings, maybe there's a free one? */
4313         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314                 pll = &dev_priv->shared_dplls[i];
4315                 if (shared_dpll[i].crtc_mask == 0) {
4316                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317                                       crtc->base.base.id, pll->name);
4318                         goto found;
4319                 }
4320         }
4321
4322         return NULL;
4323
4324 found:
4325         if (shared_dpll[i].crtc_mask == 0)
4326                 shared_dpll[i].hw_state =
4327                         crtc_state->dpll_hw_state;
4328
4329         crtc_state->shared_dpll = i;
4330         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331                          pipe_name(crtc->pipe));
4332
4333         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4334
4335         return pll;
4336 }
4337
4338 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4339 {
4340         struct drm_i915_private *dev_priv = to_i915(state->dev);
4341         struct intel_shared_dpll_config *shared_dpll;
4342         struct intel_shared_dpll *pll;
4343         enum intel_dpll_id i;
4344
4345         if (!to_intel_atomic_state(state)->dpll_set)
4346                 return;
4347
4348         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4349         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350                 pll = &dev_priv->shared_dplls[i];
4351                 pll->config = shared_dpll[i];
4352         }
4353 }
4354
4355 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4356 {
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         int dslreg = PIPEDSL(pipe);
4359         u32 temp;
4360
4361         temp = I915_READ(dslreg);
4362         udelay(500);
4363         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4364                 if (wait_for(I915_READ(dslreg) != temp, 5))
4365                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4366         }
4367 }
4368
4369 static int
4370 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4371                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4372                   int src_w, int src_h, int dst_w, int dst_h)
4373 {
4374         struct intel_crtc_scaler_state *scaler_state =
4375                 &crtc_state->scaler_state;
4376         struct intel_crtc *intel_crtc =
4377                 to_intel_crtc(crtc_state->base.crtc);
4378         int need_scaling;
4379
4380         need_scaling = intel_rotation_90_or_270(rotation) ?
4381                 (src_h != dst_w || src_w != dst_h):
4382                 (src_w != dst_w || src_h != dst_h);
4383
4384         /*
4385          * if plane is being disabled or scaler is no more required or force detach
4386          *  - free scaler binded to this plane/crtc
4387          *  - in order to do this, update crtc->scaler_usage
4388          *
4389          * Here scaler state in crtc_state is set free so that
4390          * scaler can be assigned to other user. Actual register
4391          * update to free the scaler is done in plane/panel-fit programming.
4392          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4393          */
4394         if (force_detach || !need_scaling) {
4395                 if (*scaler_id >= 0) {
4396                         scaler_state->scaler_users &= ~(1 << scaler_user);
4397                         scaler_state->scalers[*scaler_id].in_use = 0;
4398
4399                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4400                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4401                                 intel_crtc->pipe, scaler_user, *scaler_id,
4402                                 scaler_state->scaler_users);
4403                         *scaler_id = -1;
4404                 }
4405                 return 0;
4406         }
4407
4408         /* range checks */
4409         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4410                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4411
4412                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4413                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4414                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4415                         "size is out of scaler range\n",
4416                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4417                 return -EINVAL;
4418         }
4419
4420         /* mark this plane as a scaler user in crtc_state */
4421         scaler_state->scaler_users |= (1 << scaler_user);
4422         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4424                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4425                 scaler_state->scaler_users);
4426
4427         return 0;
4428 }
4429
4430 /**
4431  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4432  *
4433  * @state: crtc's scaler state
4434  *
4435  * Return
4436  *     0 - scaler_usage updated successfully
4437  *    error - requested scaling cannot be supported or other error condition
4438  */
4439 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4440 {
4441         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4442         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4443
4444         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4445                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4446
4447         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4448                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4449                 state->pipe_src_w, state->pipe_src_h,
4450                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4451 }
4452
4453 /**
4454  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4455  *
4456  * @state: crtc's scaler state
4457  * @plane_state: atomic plane state to update
4458  *
4459  * Return
4460  *     0 - scaler_usage updated successfully
4461  *    error - requested scaling cannot be supported or other error condition
4462  */
4463 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4464                                    struct intel_plane_state *plane_state)
4465 {
4466
4467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4468         struct intel_plane *intel_plane =
4469                 to_intel_plane(plane_state->base.plane);
4470         struct drm_framebuffer *fb = plane_state->base.fb;
4471         int ret;
4472
4473         bool force_detach = !fb || !plane_state->visible;
4474
4475         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4476                       intel_plane->base.base.id, intel_crtc->pipe,
4477                       drm_plane_index(&intel_plane->base));
4478
4479         ret = skl_update_scaler(crtc_state, force_detach,
4480                                 drm_plane_index(&intel_plane->base),
4481                                 &plane_state->scaler_id,
4482                                 plane_state->base.rotation,
4483                                 drm_rect_width(&plane_state->src) >> 16,
4484                                 drm_rect_height(&plane_state->src) >> 16,
4485                                 drm_rect_width(&plane_state->dst),
4486                                 drm_rect_height(&plane_state->dst));
4487
4488         if (ret || plane_state->scaler_id < 0)
4489                 return ret;
4490
4491         /* check colorkey */
4492         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4493                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4494                               intel_plane->base.base.id);
4495                 return -EINVAL;
4496         }
4497
4498         /* Check src format */
4499         switch (fb->pixel_format) {
4500         case DRM_FORMAT_RGB565:
4501         case DRM_FORMAT_XBGR8888:
4502         case DRM_FORMAT_XRGB8888:
4503         case DRM_FORMAT_ABGR8888:
4504         case DRM_FORMAT_ARGB8888:
4505         case DRM_FORMAT_XRGB2101010:
4506         case DRM_FORMAT_XBGR2101010:
4507         case DRM_FORMAT_YUYV:
4508         case DRM_FORMAT_YVYU:
4509         case DRM_FORMAT_UYVY:
4510         case DRM_FORMAT_VYUY:
4511                 break;
4512         default:
4513                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4514                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4515                 return -EINVAL;
4516         }
4517
4518         return 0;
4519 }
4520
4521 static void skylake_scaler_disable(struct intel_crtc *crtc)
4522 {
4523         int i;
4524
4525         for (i = 0; i < crtc->num_scalers; i++)
4526                 skl_detach_scaler(crtc, i);
4527 }
4528
4529 static void skylake_pfit_enable(struct intel_crtc *crtc)
4530 {
4531         struct drm_device *dev = crtc->base.dev;
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         int pipe = crtc->pipe;
4534         struct intel_crtc_scaler_state *scaler_state =
4535                 &crtc->config->scaler_state;
4536
4537         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4538
4539         if (crtc->config->pch_pfit.enabled) {
4540                 int id;
4541
4542                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4543                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4544                         return;
4545                 }
4546
4547                 id = scaler_state->scaler_id;
4548                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4549                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4550                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4551                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4552
4553                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4554         }
4555 }
4556
4557 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->base.dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         int pipe = crtc->pipe;
4562
4563         if (crtc->config->pch_pfit.enabled) {
4564                 /* Force use of hard-coded filter coefficients
4565                  * as some pre-programmed values are broken,
4566                  * e.g. x201.
4567                  */
4568                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4569                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4570                                                  PF_PIPE_SEL_IVB(pipe));
4571                 else
4572                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4573                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4574                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4575         }
4576 }
4577
4578 void hsw_enable_ips(struct intel_crtc *crtc)
4579 {
4580         struct drm_device *dev = crtc->base.dev;
4581         struct drm_i915_private *dev_priv = dev->dev_private;
4582
4583         if (!crtc->config->ips_enabled)
4584                 return;
4585
4586         /* We can only enable IPS after we enable a plane and wait for a vblank */
4587         intel_wait_for_vblank(dev, crtc->pipe);
4588
4589         assert_plane_enabled(dev_priv, crtc->plane);
4590         if (IS_BROADWELL(dev)) {
4591                 mutex_lock(&dev_priv->rps.hw_lock);
4592                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4593                 mutex_unlock(&dev_priv->rps.hw_lock);
4594                 /* Quoting Art Runyan: "its not safe to expect any particular
4595                  * value in IPS_CTL bit 31 after enabling IPS through the
4596                  * mailbox." Moreover, the mailbox may return a bogus state,
4597                  * so we need to just enable it and continue on.
4598                  */
4599         } else {
4600                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4601                 /* The bit only becomes 1 in the next vblank, so this wait here
4602                  * is essentially intel_wait_for_vblank. If we don't have this
4603                  * and don't wait for vblanks until the end of crtc_enable, then
4604                  * the HW state readout code will complain that the expected
4605                  * IPS_CTL value is not the one we read. */
4606                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4607                         DRM_ERROR("Timed out waiting for IPS enable\n");
4608         }
4609 }
4610
4611 void hsw_disable_ips(struct intel_crtc *crtc)
4612 {
4613         struct drm_device *dev = crtc->base.dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615
4616         if (!crtc->config->ips_enabled)
4617                 return;
4618
4619         assert_plane_enabled(dev_priv, crtc->plane);
4620         if (IS_BROADWELL(dev)) {
4621                 mutex_lock(&dev_priv->rps.hw_lock);
4622                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4623                 mutex_unlock(&dev_priv->rps.hw_lock);
4624                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4625                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4626                         DRM_ERROR("Timed out waiting for IPS disable\n");
4627         } else {
4628                 I915_WRITE(IPS_CTL, 0);
4629                 POSTING_READ(IPS_CTL);
4630         }
4631
4632         /* We need to wait for a vblank before we can disable the plane. */
4633         intel_wait_for_vblank(dev, crtc->pipe);
4634 }
4635
4636 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4637 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4638 {
4639         struct drm_device *dev = crtc->dev;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642         enum pipe pipe = intel_crtc->pipe;
4643         int i;
4644         bool reenable_ips = false;
4645
4646         /* The clocks have to be on to load the palette. */
4647         if (!crtc->state->active)
4648                 return;
4649
4650         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4651                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4652                         assert_dsi_pll_enabled(dev_priv);
4653                 else
4654                         assert_pll_enabled(dev_priv, pipe);
4655         }
4656
4657         /* Workaround : Do not read or write the pipe palette/gamma data while
4658          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4659          */
4660         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4661             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4662              GAMMA_MODE_MODE_SPLIT)) {
4663                 hsw_disable_ips(intel_crtc);
4664                 reenable_ips = true;
4665         }
4666
4667         for (i = 0; i < 256; i++) {
4668                 u32 palreg;
4669
4670                 if (HAS_GMCH_DISPLAY(dev))
4671                         palreg = PALETTE(pipe, i);
4672                 else
4673                         palreg = LGC_PALETTE(pipe, i);
4674
4675                 I915_WRITE(palreg,
4676                            (intel_crtc->lut_r[i] << 16) |
4677                            (intel_crtc->lut_g[i] << 8) |
4678                            intel_crtc->lut_b[i]);
4679         }
4680
4681         if (reenable_ips)
4682                 hsw_enable_ips(intel_crtc);
4683 }
4684
4685 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4686 {
4687         if (intel_crtc->overlay) {
4688                 struct drm_device *dev = intel_crtc->base.dev;
4689                 struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691                 mutex_lock(&dev->struct_mutex);
4692                 dev_priv->mm.interruptible = false;
4693                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4694                 dev_priv->mm.interruptible = true;
4695                 mutex_unlock(&dev->struct_mutex);
4696         }
4697
4698         /* Let userspace switch the overlay on again. In most cases userspace
4699          * has to recompute where to put it anyway.
4700          */
4701 }
4702
4703 /**
4704  * intel_post_enable_primary - Perform operations after enabling primary plane
4705  * @crtc: the CRTC whose primary plane was just enabled
4706  *
4707  * Performs potentially sleeping operations that must be done after the primary
4708  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4709  * called due to an explicit primary plane update, or due to an implicit
4710  * re-enable that is caused when a sprite plane is updated to no longer
4711  * completely hide the primary plane.
4712  */
4713 static void
4714 intel_post_enable_primary(struct drm_crtc *crtc)
4715 {
4716         struct drm_device *dev = crtc->dev;
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719         int pipe = intel_crtc->pipe;
4720
4721         /*
4722          * BDW signals flip done immediately if the plane
4723          * is disabled, even if the plane enable is already
4724          * armed to occur at the next vblank :(
4725          */
4726         if (IS_BROADWELL(dev))
4727                 intel_wait_for_vblank(dev, pipe);
4728
4729         /*
4730          * FIXME IPS should be fine as long as one plane is
4731          * enabled, but in practice it seems to have problems
4732          * when going from primary only to sprite only and vice
4733          * versa.
4734          */
4735         hsw_enable_ips(intel_crtc);
4736
4737         /*
4738          * Gen2 reports pipe underruns whenever all planes are disabled.
4739          * So don't enable underrun reporting before at least some planes
4740          * are enabled.
4741          * FIXME: Need to fix the logic to work when we turn off all planes
4742          * but leave the pipe running.
4743          */
4744         if (IS_GEN2(dev))
4745                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4746
4747         /* Underruns don't raise interrupts, so check manually. */
4748         if (HAS_GMCH_DISPLAY(dev))
4749                 i9xx_check_fifo_underruns(dev_priv);
4750 }
4751
4752 /**
4753  * intel_pre_disable_primary - Perform operations before disabling primary plane
4754  * @crtc: the CRTC whose primary plane is to be disabled
4755  *
4756  * Performs potentially sleeping operations that must be done before the
4757  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4758  * be called due to an explicit primary plane update, or due to an implicit
4759  * disable that is caused when a sprite plane completely hides the primary
4760  * plane.
4761  */
4762 static void
4763 intel_pre_disable_primary(struct drm_crtc *crtc)
4764 {
4765         struct drm_device *dev = crtc->dev;
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768         int pipe = intel_crtc->pipe;
4769
4770         /*
4771          * Gen2 reports pipe underruns whenever all planes are disabled.
4772          * So diasble underrun reporting before all the planes get disabled.
4773          * FIXME: Need to fix the logic to work when we turn off all planes
4774          * but leave the pipe running.
4775          */
4776         if (IS_GEN2(dev))
4777                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4778
4779         /*
4780          * Vblank time updates from the shadow to live plane control register
4781          * are blocked if the memory self-refresh mode is active at that
4782          * moment. So to make sure the plane gets truly disabled, disable
4783          * first the self-refresh mode. The self-refresh enable bit in turn
4784          * will be checked/applied by the HW only at the next frame start
4785          * event which is after the vblank start event, so we need to have a
4786          * wait-for-vblank between disabling the plane and the pipe.
4787          */
4788         if (HAS_GMCH_DISPLAY(dev)) {
4789                 intel_set_memory_cxsr(dev_priv, false);
4790                 dev_priv->wm.vlv.cxsr = false;
4791                 intel_wait_for_vblank(dev, pipe);
4792         }
4793
4794         /*
4795          * FIXME IPS should be fine as long as one plane is
4796          * enabled, but in practice it seems to have problems
4797          * when going from primary only to sprite only and vice
4798          * versa.
4799          */
4800         hsw_disable_ips(intel_crtc);
4801 }
4802
4803 static void intel_post_plane_update(struct intel_crtc *crtc)
4804 {
4805         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4806         struct drm_device *dev = crtc->base.dev;
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct drm_plane *plane;
4809
4810         if (atomic->wait_vblank)
4811                 intel_wait_for_vblank(dev, crtc->pipe);
4812
4813         intel_frontbuffer_flip(dev, atomic->fb_bits);
4814
4815         if (atomic->disable_cxsr)
4816                 crtc->wm.cxsr_allowed = true;
4817
4818         if (crtc->atomic.update_wm_post)
4819                 intel_update_watermarks(&crtc->base);
4820
4821         if (atomic->update_fbc)
4822                 intel_fbc_update(dev_priv);
4823
4824         if (atomic->post_enable_primary)
4825                 intel_post_enable_primary(&crtc->base);
4826
4827         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4828                 intel_update_sprite_watermarks(plane, &crtc->base,
4829                                                0, 0, 0, false, false);
4830
4831         memset(atomic, 0, sizeof(*atomic));
4832 }
4833
4834 static void intel_pre_plane_update(struct intel_crtc *crtc)
4835 {
4836         struct drm_device *dev = crtc->base.dev;
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4839         struct drm_plane *p;
4840
4841         /* Track fb's for any planes being disabled */
4842         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4843                 struct intel_plane *plane = to_intel_plane(p);
4844
4845                 mutex_lock(&dev->struct_mutex);
4846                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4847                                   plane->frontbuffer_bit);
4848                 mutex_unlock(&dev->struct_mutex);
4849         }
4850
4851         if (atomic->wait_for_flips)
4852                 intel_crtc_wait_for_pending_flips(&crtc->base);
4853
4854         if (atomic->disable_fbc)
4855                 intel_fbc_disable_crtc(crtc);
4856
4857         if (crtc->atomic.disable_ips)
4858                 hsw_disable_ips(crtc);
4859
4860         if (atomic->pre_disable_primary)
4861                 intel_pre_disable_primary(&crtc->base);
4862
4863         if (atomic->disable_cxsr) {
4864                 crtc->wm.cxsr_allowed = false;
4865                 intel_set_memory_cxsr(dev_priv, false);
4866         }
4867 }
4868
4869 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4870 {
4871         struct drm_device *dev = crtc->dev;
4872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873         struct drm_plane *p;
4874         int pipe = intel_crtc->pipe;
4875
4876         intel_crtc_dpms_overlay_disable(intel_crtc);
4877
4878         drm_for_each_plane_mask(p, dev, plane_mask)
4879                 to_intel_plane(p)->disable_plane(p, crtc);
4880
4881         /*
4882          * FIXME: Once we grow proper nuclear flip support out of this we need
4883          * to compute the mask of flip planes precisely. For the time being
4884          * consider this a flip to a NULL plane.
4885          */
4886         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4887 }
4888
4889 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4890 {
4891         struct drm_device *dev = crtc->dev;
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894         struct intel_encoder *encoder;
4895         int pipe = intel_crtc->pipe;
4896
4897         if (WARN_ON(intel_crtc->active))
4898                 return;
4899
4900         if (intel_crtc->config->has_pch_encoder)
4901                 intel_prepare_shared_dpll(intel_crtc);
4902
4903         if (intel_crtc->config->has_dp_encoder)
4904                 intel_dp_set_m_n(intel_crtc, M1_N1);
4905
4906         intel_set_pipe_timings(intel_crtc);
4907
4908         if (intel_crtc->config->has_pch_encoder) {
4909                 intel_cpu_transcoder_set_m_n(intel_crtc,
4910                                      &intel_crtc->config->fdi_m_n, NULL);
4911         }
4912
4913         ironlake_set_pipeconf(crtc);
4914
4915         intel_crtc->active = true;
4916
4917         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4919
4920         for_each_encoder_on_crtc(dev, crtc, encoder)
4921                 if (encoder->pre_enable)
4922                         encoder->pre_enable(encoder);
4923
4924         if (intel_crtc->config->has_pch_encoder) {
4925                 /* Note: FDI PLL enabling _must_ be done before we enable the
4926                  * cpu pipes, hence this is separate from all the other fdi/pch
4927                  * enabling. */
4928                 ironlake_fdi_pll_enable(intel_crtc);
4929         } else {
4930                 assert_fdi_tx_disabled(dev_priv, pipe);
4931                 assert_fdi_rx_disabled(dev_priv, pipe);
4932         }
4933
4934         ironlake_pfit_enable(intel_crtc);
4935
4936         /*
4937          * On ILK+ LUT must be loaded before the pipe is running but with
4938          * clocks enabled
4939          */
4940         intel_crtc_load_lut(crtc);
4941
4942         intel_update_watermarks(crtc);
4943         intel_enable_pipe(intel_crtc);
4944
4945         if (intel_crtc->config->has_pch_encoder)
4946                 ironlake_pch_enable(crtc);
4947
4948         assert_vblank_disabled(crtc);
4949         drm_crtc_vblank_on(crtc);
4950
4951         for_each_encoder_on_crtc(dev, crtc, encoder)
4952                 encoder->enable(encoder);
4953
4954         if (HAS_PCH_CPT(dev))
4955                 cpt_verify_modeset(dev, intel_crtc->pipe);
4956 }
4957
4958 /* IPS only exists on ULT machines and is tied to pipe A. */
4959 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4960 {
4961         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4962 }
4963
4964 static void haswell_crtc_enable(struct drm_crtc *crtc)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969         struct intel_encoder *encoder;
4970         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4971         struct intel_crtc_state *pipe_config =
4972                 to_intel_crtc_state(crtc->state);
4973
4974         if (WARN_ON(intel_crtc->active))
4975                 return;
4976
4977         if (intel_crtc_to_shared_dpll(intel_crtc))
4978                 intel_enable_shared_dpll(intel_crtc);
4979
4980         if (intel_crtc->config->has_dp_encoder)
4981                 intel_dp_set_m_n(intel_crtc, M1_N1);
4982
4983         intel_set_pipe_timings(intel_crtc);
4984
4985         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4986                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4987                            intel_crtc->config->pixel_multiplier - 1);
4988         }
4989
4990         if (intel_crtc->config->has_pch_encoder) {
4991                 intel_cpu_transcoder_set_m_n(intel_crtc,
4992                                      &intel_crtc->config->fdi_m_n, NULL);
4993         }
4994
4995         haswell_set_pipeconf(crtc);
4996
4997         intel_set_pipe_csc(crtc);
4998
4999         intel_crtc->active = true;
5000
5001         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5002         for_each_encoder_on_crtc(dev, crtc, encoder)
5003                 if (encoder->pre_enable)
5004                         encoder->pre_enable(encoder);
5005
5006         if (intel_crtc->config->has_pch_encoder) {
5007                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5008                                                       true);
5009                 dev_priv->display.fdi_link_train(crtc);
5010         }
5011
5012         intel_ddi_enable_pipe_clock(intel_crtc);
5013
5014         if (INTEL_INFO(dev)->gen >= 9)
5015                 skylake_pfit_enable(intel_crtc);
5016         else
5017                 ironlake_pfit_enable(intel_crtc);
5018
5019         /*
5020          * On ILK+ LUT must be loaded before the pipe is running but with
5021          * clocks enabled
5022          */
5023         intel_crtc_load_lut(crtc);
5024
5025         intel_ddi_set_pipe_settings(crtc);
5026         intel_ddi_enable_transcoder_func(crtc);
5027
5028         intel_update_watermarks(crtc);
5029         intel_enable_pipe(intel_crtc);
5030
5031         if (intel_crtc->config->has_pch_encoder)
5032                 lpt_pch_enable(crtc);
5033
5034         if (intel_crtc->config->dp_encoder_is_mst)
5035                 intel_ddi_set_vc_payload_alloc(crtc, true);
5036
5037         assert_vblank_disabled(crtc);
5038         drm_crtc_vblank_on(crtc);
5039
5040         for_each_encoder_on_crtc(dev, crtc, encoder) {
5041                 encoder->enable(encoder);
5042                 intel_opregion_notify_encoder(encoder, true);
5043         }
5044
5045         /* If we change the relative order between pipe/planes enabling, we need
5046          * to change the workaround. */
5047         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5048         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5049                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5050                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5051         }
5052 }
5053
5054 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5055 {
5056         struct drm_device *dev = crtc->base.dev;
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         int pipe = crtc->pipe;
5059
5060         /* To avoid upsetting the power well on haswell only disable the pfit if
5061          * it's in use. The hw state code will make sure we get this right. */
5062         if (force || crtc->config->pch_pfit.enabled) {
5063                 I915_WRITE(PF_CTL(pipe), 0);
5064                 I915_WRITE(PF_WIN_POS(pipe), 0);
5065                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5066         }
5067 }
5068
5069 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5070 {
5071         struct drm_device *dev = crtc->dev;
5072         struct drm_i915_private *dev_priv = dev->dev_private;
5073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074         struct intel_encoder *encoder;
5075         int pipe = intel_crtc->pipe;
5076         u32 reg, temp;
5077
5078         for_each_encoder_on_crtc(dev, crtc, encoder)
5079                 encoder->disable(encoder);
5080
5081         drm_crtc_vblank_off(crtc);
5082         assert_vblank_disabled(crtc);
5083
5084         if (intel_crtc->config->has_pch_encoder)
5085                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5086
5087         intel_disable_pipe(intel_crtc);
5088
5089         ironlake_pfit_disable(intel_crtc, false);
5090
5091         if (intel_crtc->config->has_pch_encoder)
5092                 ironlake_fdi_disable(crtc);
5093
5094         for_each_encoder_on_crtc(dev, crtc, encoder)
5095                 if (encoder->post_disable)
5096                         encoder->post_disable(encoder);
5097
5098         if (intel_crtc->config->has_pch_encoder) {
5099                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5100
5101                 if (HAS_PCH_CPT(dev)) {
5102                         /* disable TRANS_DP_CTL */
5103                         reg = TRANS_DP_CTL(pipe);
5104                         temp = I915_READ(reg);
5105                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5106                                   TRANS_DP_PORT_SEL_MASK);
5107                         temp |= TRANS_DP_PORT_SEL_NONE;
5108                         I915_WRITE(reg, temp);
5109
5110                         /* disable DPLL_SEL */
5111                         temp = I915_READ(PCH_DPLL_SEL);
5112                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5113                         I915_WRITE(PCH_DPLL_SEL, temp);
5114                 }
5115
5116                 ironlake_fdi_pll_disable(intel_crtc);
5117         }
5118
5119         intel_crtc->active = false;
5120         intel_update_watermarks(crtc);
5121 }
5122
5123 static void haswell_crtc_disable(struct drm_crtc *crtc)
5124 {
5125         struct drm_device *dev = crtc->dev;
5126         struct drm_i915_private *dev_priv = dev->dev_private;
5127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128         struct intel_encoder *encoder;
5129         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5130
5131         for_each_encoder_on_crtc(dev, crtc, encoder) {
5132                 intel_opregion_notify_encoder(encoder, false);
5133                 encoder->disable(encoder);
5134         }
5135
5136         drm_crtc_vblank_off(crtc);
5137         assert_vblank_disabled(crtc);
5138
5139         if (intel_crtc->config->has_pch_encoder)
5140                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5141                                                       false);
5142         intel_disable_pipe(intel_crtc);
5143
5144         if (intel_crtc->config->dp_encoder_is_mst)
5145                 intel_ddi_set_vc_payload_alloc(crtc, false);
5146
5147         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5148
5149         if (INTEL_INFO(dev)->gen >= 9)
5150                 skylake_scaler_disable(intel_crtc);
5151         else
5152                 ironlake_pfit_disable(intel_crtc, false);
5153
5154         intel_ddi_disable_pipe_clock(intel_crtc);
5155
5156         if (intel_crtc->config->has_pch_encoder) {
5157                 lpt_disable_pch_transcoder(dev_priv);
5158                 intel_ddi_fdi_disable(crtc);
5159         }
5160
5161         for_each_encoder_on_crtc(dev, crtc, encoder)
5162                 if (encoder->post_disable)
5163                         encoder->post_disable(encoder);
5164
5165         intel_crtc->active = false;
5166         intel_update_watermarks(crtc);
5167 }
5168
5169 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         struct intel_crtc_state *pipe_config = crtc->config;
5174
5175         if (!pipe_config->gmch_pfit.control)
5176                 return;
5177
5178         /*
5179          * The panel fitter should only be adjusted whilst the pipe is disabled,
5180          * according to register description and PRM.
5181          */
5182         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5183         assert_pipe_disabled(dev_priv, crtc->pipe);
5184
5185         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5186         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5187
5188         /* Border color in case we don't scale up to the full screen. Black by
5189          * default, change to something else for debugging. */
5190         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5191 }
5192
5193 static enum intel_display_power_domain port_to_power_domain(enum port port)
5194 {
5195         switch (port) {
5196         case PORT_A:
5197                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5198         case PORT_B:
5199                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5200         case PORT_C:
5201                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5202         case PORT_D:
5203                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5204         case PORT_E:
5205                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5206         default:
5207                 WARN_ON_ONCE(1);
5208                 return POWER_DOMAIN_PORT_OTHER;
5209         }
5210 }
5211
5212 #define for_each_power_domain(domain, mask)                             \
5213         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5214                 if ((1 << (domain)) & (mask))
5215
5216 enum intel_display_power_domain
5217 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5218 {
5219         struct drm_device *dev = intel_encoder->base.dev;
5220         struct intel_digital_port *intel_dig_port;
5221
5222         switch (intel_encoder->type) {
5223         case INTEL_OUTPUT_UNKNOWN:
5224                 /* Only DDI platforms should ever use this output type */
5225                 WARN_ON_ONCE(!HAS_DDI(dev));
5226         case INTEL_OUTPUT_DISPLAYPORT:
5227         case INTEL_OUTPUT_HDMI:
5228         case INTEL_OUTPUT_EDP:
5229                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5230                 return port_to_power_domain(intel_dig_port->port);
5231         case INTEL_OUTPUT_DP_MST:
5232                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5233                 return port_to_power_domain(intel_dig_port->port);
5234         case INTEL_OUTPUT_ANALOG:
5235                 return POWER_DOMAIN_PORT_CRT;
5236         case INTEL_OUTPUT_DSI:
5237                 return POWER_DOMAIN_PORT_DSI;
5238         default:
5239                 return POWER_DOMAIN_PORT_OTHER;
5240         }
5241 }
5242
5243 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5244 {
5245         struct drm_device *dev = crtc->dev;
5246         struct intel_encoder *intel_encoder;
5247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248         enum pipe pipe = intel_crtc->pipe;
5249         unsigned long mask;
5250         enum transcoder transcoder;
5251
5252         if (!crtc->state->active)
5253                 return 0;
5254
5255         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5256
5257         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5258         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5259         if (intel_crtc->config->pch_pfit.enabled ||
5260             intel_crtc->config->pch_pfit.force_thru)
5261                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5262
5263         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5264                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5265
5266         return mask;
5267 }
5268
5269 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5270 {
5271         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273         enum intel_display_power_domain domain;
5274         unsigned long domains, new_domains, old_domains;
5275
5276         old_domains = intel_crtc->enabled_power_domains;
5277         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5278
5279         domains = new_domains & ~old_domains;
5280
5281         for_each_power_domain(domain, domains)
5282                 intel_display_power_get(dev_priv, domain);
5283
5284         return old_domains & ~new_domains;
5285 }
5286
5287 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5288                                       unsigned long domains)
5289 {
5290         enum intel_display_power_domain domain;
5291
5292         for_each_power_domain(domain, domains)
5293                 intel_display_power_put(dev_priv, domain);
5294 }
5295
5296 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5297 {
5298         struct drm_device *dev = state->dev;
5299         struct drm_i915_private *dev_priv = dev->dev_private;
5300         unsigned long put_domains[I915_MAX_PIPES] = {};
5301         struct drm_crtc_state *crtc_state;
5302         struct drm_crtc *crtc;
5303         int i;
5304
5305         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5306                 if (needs_modeset(crtc->state))
5307                         put_domains[to_intel_crtc(crtc)->pipe] =
5308                                 modeset_get_crtc_power_domains(crtc);
5309         }
5310
5311         if (dev_priv->display.modeset_commit_cdclk) {
5312                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5313
5314                 if (cdclk != dev_priv->cdclk_freq &&
5315                     !WARN_ON(!state->allow_modeset))
5316                         dev_priv->display.modeset_commit_cdclk(state);
5317         }
5318
5319         for (i = 0; i < I915_MAX_PIPES; i++)
5320                 if (put_domains[i])
5321                         modeset_put_power_domains(dev_priv, put_domains[i]);
5322 }
5323
5324 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5325 {
5326         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5327
5328         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5329             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5330                 return max_cdclk_freq;
5331         else if (IS_CHERRYVIEW(dev_priv))
5332                 return max_cdclk_freq*95/100;
5333         else if (INTEL_INFO(dev_priv)->gen < 4)
5334                 return 2*max_cdclk_freq*90/100;
5335         else
5336                 return max_cdclk_freq*90/100;
5337 }
5338
5339 static void intel_update_max_cdclk(struct drm_device *dev)
5340 {
5341         struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343         if (IS_SKYLAKE(dev)) {
5344                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5345
5346                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5347                         dev_priv->max_cdclk_freq = 675000;
5348                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5349                         dev_priv->max_cdclk_freq = 540000;
5350                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5351                         dev_priv->max_cdclk_freq = 450000;
5352                 else
5353                         dev_priv->max_cdclk_freq = 337500;
5354         } else if (IS_BROADWELL(dev))  {
5355                 /*
5356                  * FIXME with extra cooling we can allow
5357                  * 540 MHz for ULX and 675 Mhz for ULT.
5358                  * How can we know if extra cooling is
5359                  * available? PCI ID, VTB, something else?
5360                  */
5361                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5362                         dev_priv->max_cdclk_freq = 450000;
5363                 else if (IS_BDW_ULX(dev))
5364                         dev_priv->max_cdclk_freq = 450000;
5365                 else if (IS_BDW_ULT(dev))
5366                         dev_priv->max_cdclk_freq = 540000;
5367                 else
5368                         dev_priv->max_cdclk_freq = 675000;
5369         } else if (IS_CHERRYVIEW(dev)) {
5370                 dev_priv->max_cdclk_freq = 320000;
5371         } else if (IS_VALLEYVIEW(dev)) {
5372                 dev_priv->max_cdclk_freq = 400000;
5373         } else {
5374                 /* otherwise assume cdclk is fixed */
5375                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5376         }
5377
5378         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5379
5380         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5381                          dev_priv->max_cdclk_freq);
5382
5383         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5384                          dev_priv->max_dotclk_freq);
5385 }
5386
5387 static void intel_update_cdclk(struct drm_device *dev)
5388 {
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390
5391         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5392         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5393                          dev_priv->cdclk_freq);
5394
5395         /*
5396          * Program the gmbus_freq based on the cdclk frequency.
5397          * BSpec erroneously claims we should aim for 4MHz, but
5398          * in fact 1MHz is the correct frequency.
5399          */
5400         if (IS_VALLEYVIEW(dev)) {
5401                 /*
5402                  * Program the gmbus_freq based on the cdclk frequency.
5403                  * BSpec erroneously claims we should aim for 4MHz, but
5404                  * in fact 1MHz is the correct frequency.
5405                  */
5406                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5407         }
5408
5409         if (dev_priv->max_cdclk_freq == 0)
5410                 intel_update_max_cdclk(dev);
5411 }
5412
5413 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5414 {
5415         struct drm_i915_private *dev_priv = dev->dev_private;
5416         uint32_t divider;
5417         uint32_t ratio;
5418         uint32_t current_freq;
5419         int ret;
5420
5421         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5422         switch (frequency) {
5423         case 144000:
5424                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5425                 ratio = BXT_DE_PLL_RATIO(60);
5426                 break;
5427         case 288000:
5428                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5429                 ratio = BXT_DE_PLL_RATIO(60);
5430                 break;
5431         case 384000:
5432                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5433                 ratio = BXT_DE_PLL_RATIO(60);
5434                 break;
5435         case 576000:
5436                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5437                 ratio = BXT_DE_PLL_RATIO(60);
5438                 break;
5439         case 624000:
5440                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5441                 ratio = BXT_DE_PLL_RATIO(65);
5442                 break;
5443         case 19200:
5444                 /*
5445                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5446                  * to suppress GCC warning.
5447                  */
5448                 ratio = 0;
5449                 divider = 0;
5450                 break;
5451         default:
5452                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5453
5454                 return;
5455         }
5456
5457         mutex_lock(&dev_priv->rps.hw_lock);
5458         /* Inform power controller of upcoming frequency change */
5459         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5460                                       0x80000000);
5461         mutex_unlock(&dev_priv->rps.hw_lock);
5462
5463         if (ret) {
5464                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5465                           ret, frequency);
5466                 return;
5467         }
5468
5469         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5470         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5471         current_freq = current_freq * 500 + 1000;
5472
5473         /*
5474          * DE PLL has to be disabled when
5475          * - setting to 19.2MHz (bypass, PLL isn't used)
5476          * - before setting to 624MHz (PLL needs toggling)
5477          * - before setting to any frequency from 624MHz (PLL needs toggling)
5478          */
5479         if (frequency == 19200 || frequency == 624000 ||
5480             current_freq == 624000) {
5481                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5482                 /* Timeout 200us */
5483                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5484                              1))
5485                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5486         }
5487
5488         if (frequency != 19200) {
5489                 uint32_t val;
5490
5491                 val = I915_READ(BXT_DE_PLL_CTL);
5492                 val &= ~BXT_DE_PLL_RATIO_MASK;
5493                 val |= ratio;
5494                 I915_WRITE(BXT_DE_PLL_CTL, val);
5495
5496                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5497                 /* Timeout 200us */
5498                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5499                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5500
5501                 val = I915_READ(CDCLK_CTL);
5502                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5503                 val |= divider;
5504                 /*
5505                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5506                  * enable otherwise.
5507                  */
5508                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5509                 if (frequency >= 500000)
5510                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5511
5512                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5513                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5514                 val |= (frequency - 1000) / 500;
5515                 I915_WRITE(CDCLK_CTL, val);
5516         }
5517
5518         mutex_lock(&dev_priv->rps.hw_lock);
5519         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520                                       DIV_ROUND_UP(frequency, 25000));
5521         mutex_unlock(&dev_priv->rps.hw_lock);
5522
5523         if (ret) {
5524                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5525                           ret, frequency);
5526                 return;
5527         }
5528
5529         intel_update_cdclk(dev);
5530 }
5531
5532 void broxton_init_cdclk(struct drm_device *dev)
5533 {
5534         struct drm_i915_private *dev_priv = dev->dev_private;
5535         uint32_t val;
5536
5537         /*
5538          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5539          * or else the reset will hang because there is no PCH to respond.
5540          * Move the handshake programming to initialization sequence.
5541          * Previously was left up to BIOS.
5542          */
5543         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5544         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5545         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5546
5547         /* Enable PG1 for cdclk */
5548         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5549
5550         /* check if cd clock is enabled */
5551         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5552                 DRM_DEBUG_KMS("Display already initialized\n");
5553                 return;
5554         }
5555
5556         /*
5557          * FIXME:
5558          * - The initial CDCLK needs to be read from VBT.
5559          *   Need to make this change after VBT has changes for BXT.
5560          * - check if setting the max (or any) cdclk freq is really necessary
5561          *   here, it belongs to modeset time
5562          */
5563         broxton_set_cdclk(dev, 624000);
5564
5565         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5566         POSTING_READ(DBUF_CTL);
5567
5568         udelay(10);
5569
5570         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5571                 DRM_ERROR("DBuf power enable timeout!\n");
5572 }
5573
5574 void broxton_uninit_cdclk(struct drm_device *dev)
5575 {
5576         struct drm_i915_private *dev_priv = dev->dev_private;
5577
5578         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5579         POSTING_READ(DBUF_CTL);
5580
5581         udelay(10);
5582
5583         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5584                 DRM_ERROR("DBuf power disable timeout!\n");
5585
5586         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5587         broxton_set_cdclk(dev, 19200);
5588
5589         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5590 }
5591
5592 static const struct skl_cdclk_entry {
5593         unsigned int freq;
5594         unsigned int vco;
5595 } skl_cdclk_frequencies[] = {
5596         { .freq = 308570, .vco = 8640 },
5597         { .freq = 337500, .vco = 8100 },
5598         { .freq = 432000, .vco = 8640 },
5599         { .freq = 450000, .vco = 8100 },
5600         { .freq = 540000, .vco = 8100 },
5601         { .freq = 617140, .vco = 8640 },
5602         { .freq = 675000, .vco = 8100 },
5603 };
5604
5605 static unsigned int skl_cdclk_decimal(unsigned int freq)
5606 {
5607         return (freq - 1000) / 500;
5608 }
5609
5610 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5611 {
5612         unsigned int i;
5613
5614         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5615                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5616
5617                 if (e->freq == freq)
5618                         return e->vco;
5619         }
5620
5621         return 8100;
5622 }
5623
5624 static void
5625 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5626 {
5627         unsigned int min_freq;
5628         u32 val;
5629
5630         /* select the minimum CDCLK before enabling DPLL 0 */
5631         val = I915_READ(CDCLK_CTL);
5632         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5633         val |= CDCLK_FREQ_337_308;
5634
5635         if (required_vco == 8640)
5636                 min_freq = 308570;
5637         else
5638                 min_freq = 337500;
5639
5640         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5641
5642         I915_WRITE(CDCLK_CTL, val);
5643         POSTING_READ(CDCLK_CTL);
5644
5645         /*
5646          * We always enable DPLL0 with the lowest link rate possible, but still
5647          * taking into account the VCO required to operate the eDP panel at the
5648          * desired frequency. The usual DP link rates operate with a VCO of
5649          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5650          * The modeset code is responsible for the selection of the exact link
5651          * rate later on, with the constraint of choosing a frequency that
5652          * works with required_vco.
5653          */
5654         val = I915_READ(DPLL_CTRL1);
5655
5656         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5657                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5658         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5659         if (required_vco == 8640)
5660                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5661                                             SKL_DPLL0);
5662         else
5663                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5664                                             SKL_DPLL0);
5665
5666         I915_WRITE(DPLL_CTRL1, val);
5667         POSTING_READ(DPLL_CTRL1);
5668
5669         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5670
5671         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5672                 DRM_ERROR("DPLL0 not locked\n");
5673 }
5674
5675 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5676 {
5677         int ret;
5678         u32 val;
5679
5680         /* inform PCU we want to change CDCLK */
5681         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5682         mutex_lock(&dev_priv->rps.hw_lock);
5683         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5684         mutex_unlock(&dev_priv->rps.hw_lock);
5685
5686         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5687 }
5688
5689 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5690 {
5691         unsigned int i;
5692
5693         for (i = 0; i < 15; i++) {
5694                 if (skl_cdclk_pcu_ready(dev_priv))
5695                         return true;
5696                 udelay(10);
5697         }
5698
5699         return false;
5700 }
5701
5702 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5703 {
5704         struct drm_device *dev = dev_priv->dev;
5705         u32 freq_select, pcu_ack;
5706
5707         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5708
5709         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5710                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5711                 return;
5712         }
5713
5714         /* set CDCLK_CTL */
5715         switch(freq) {
5716         case 450000:
5717         case 432000:
5718                 freq_select = CDCLK_FREQ_450_432;
5719                 pcu_ack = 1;
5720                 break;
5721         case 540000:
5722                 freq_select = CDCLK_FREQ_540;
5723                 pcu_ack = 2;
5724                 break;
5725         case 308570:
5726         case 337500:
5727         default:
5728                 freq_select = CDCLK_FREQ_337_308;
5729                 pcu_ack = 0;
5730                 break;
5731         case 617140:
5732         case 675000:
5733                 freq_select = CDCLK_FREQ_675_617;
5734                 pcu_ack = 3;
5735                 break;
5736         }
5737
5738         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5739         POSTING_READ(CDCLK_CTL);
5740
5741         /* inform PCU of the change */
5742         mutex_lock(&dev_priv->rps.hw_lock);
5743         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5744         mutex_unlock(&dev_priv->rps.hw_lock);
5745
5746         intel_update_cdclk(dev);
5747 }
5748
5749 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5750 {
5751         /* disable DBUF power */
5752         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5753         POSTING_READ(DBUF_CTL);
5754
5755         udelay(10);
5756
5757         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5758                 DRM_ERROR("DBuf power disable timeout\n");
5759
5760         /*
5761          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5762          */
5763         if (dev_priv->csr.dmc_payload) {
5764                 /* disable DPLL0 */
5765                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5766                                         ~LCPLL_PLL_ENABLE);
5767                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5768                         DRM_ERROR("Couldn't disable DPLL0\n");
5769         }
5770
5771         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5772 }
5773
5774 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5775 {
5776         u32 val;
5777         unsigned int required_vco;
5778
5779         /* enable PCH reset handshake */
5780         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5781         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5782
5783         /* enable PG1 and Misc I/O */
5784         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5785
5786         /* DPLL0 not enabled (happens on early BIOS versions) */
5787         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5788                 /* enable DPLL0 */
5789                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5790                 skl_dpll0_enable(dev_priv, required_vco);
5791         }
5792
5793         /* set CDCLK to the frequency the BIOS chose */
5794         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5795
5796         /* enable DBUF power */
5797         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5798         POSTING_READ(DBUF_CTL);
5799
5800         udelay(10);
5801
5802         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5803                 DRM_ERROR("DBuf power enable timeout\n");
5804 }
5805
5806 /* Adjust CDclk dividers to allow high res or save power if possible */
5807 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5808 {
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         u32 val, cmd;
5811
5812         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5813                                         != dev_priv->cdclk_freq);
5814
5815         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5816                 cmd = 2;
5817         else if (cdclk == 266667)
5818                 cmd = 1;
5819         else
5820                 cmd = 0;
5821
5822         mutex_lock(&dev_priv->rps.hw_lock);
5823         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824         val &= ~DSPFREQGUAR_MASK;
5825         val |= (cmd << DSPFREQGUAR_SHIFT);
5826         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5829                      50)) {
5830                 DRM_ERROR("timed out waiting for CDclk change\n");
5831         }
5832         mutex_unlock(&dev_priv->rps.hw_lock);
5833
5834         mutex_lock(&dev_priv->sb_lock);
5835
5836         if (cdclk == 400000) {
5837                 u32 divider;
5838
5839                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5840
5841                 /* adjust cdclk divider */
5842                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5843                 val &= ~CCK_FREQUENCY_VALUES;
5844                 val |= divider;
5845                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5846
5847                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5848                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5849                              50))
5850                         DRM_ERROR("timed out waiting for CDclk change\n");
5851         }
5852
5853         /* adjust self-refresh exit latency value */
5854         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5855         val &= ~0x7f;
5856
5857         /*
5858          * For high bandwidth configs, we set a higher latency in the bunit
5859          * so that the core display fetch happens in time to avoid underruns.
5860          */
5861         if (cdclk == 400000)
5862                 val |= 4500 / 250; /* 4.5 usec */
5863         else
5864                 val |= 3000 / 250; /* 3.0 usec */
5865         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5866
5867         mutex_unlock(&dev_priv->sb_lock);
5868
5869         intel_update_cdclk(dev);
5870 }
5871
5872 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5873 {
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         u32 val, cmd;
5876
5877         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878                                                 != dev_priv->cdclk_freq);
5879
5880         switch (cdclk) {
5881         case 333333:
5882         case 320000:
5883         case 266667:
5884         case 200000:
5885                 break;
5886         default:
5887                 MISSING_CASE(cdclk);
5888                 return;
5889         }
5890
5891         /*
5892          * Specs are full of misinformation, but testing on actual
5893          * hardware has shown that we just need to write the desired
5894          * CCK divider into the Punit register.
5895          */
5896         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5897
5898         mutex_lock(&dev_priv->rps.hw_lock);
5899         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5900         val &= ~DSPFREQGUAR_MASK_CHV;
5901         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5902         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5903         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5904                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5905                      50)) {
5906                 DRM_ERROR("timed out waiting for CDclk change\n");
5907         }
5908         mutex_unlock(&dev_priv->rps.hw_lock);
5909
5910         intel_update_cdclk(dev);
5911 }
5912
5913 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5914                                  int max_pixclk)
5915 {
5916         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5917         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5918
5919         /*
5920          * Really only a few cases to deal with, as only 4 CDclks are supported:
5921          *   200MHz
5922          *   267MHz
5923          *   320/333MHz (depends on HPLL freq)
5924          *   400MHz (VLV only)
5925          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5926          * of the lower bin and adjust if needed.
5927          *
5928          * We seem to get an unstable or solid color picture at 200MHz.
5929          * Not sure what's wrong. For now use 200MHz only when all pipes
5930          * are off.
5931          */
5932         if (!IS_CHERRYVIEW(dev_priv) &&
5933             max_pixclk > freq_320*limit/100)
5934                 return 400000;
5935         else if (max_pixclk > 266667*limit/100)
5936                 return freq_320;
5937         else if (max_pixclk > 0)
5938                 return 266667;
5939         else
5940                 return 200000;
5941 }
5942
5943 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5944                               int max_pixclk)
5945 {
5946         /*
5947          * FIXME:
5948          * - remove the guardband, it's not needed on BXT
5949          * - set 19.2MHz bypass frequency if there are no active pipes
5950          */
5951         if (max_pixclk > 576000*9/10)
5952                 return 624000;
5953         else if (max_pixclk > 384000*9/10)
5954                 return 576000;
5955         else if (max_pixclk > 288000*9/10)
5956                 return 384000;
5957         else if (max_pixclk > 144000*9/10)
5958                 return 288000;
5959         else
5960                 return 144000;
5961 }
5962
5963 /* Compute the max pixel clock for new configuration. Uses atomic state if
5964  * that's non-NULL, look at current state otherwise. */
5965 static int intel_mode_max_pixclk(struct drm_device *dev,
5966                                  struct drm_atomic_state *state)
5967 {
5968         struct intel_crtc *intel_crtc;
5969         struct intel_crtc_state *crtc_state;
5970         int max_pixclk = 0;
5971
5972         for_each_intel_crtc(dev, intel_crtc) {
5973                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5974                 if (IS_ERR(crtc_state))
5975                         return PTR_ERR(crtc_state);
5976
5977                 if (!crtc_state->base.enable)
5978                         continue;
5979
5980                 max_pixclk = max(max_pixclk,
5981                                  crtc_state->base.adjusted_mode.crtc_clock);
5982         }
5983
5984         return max_pixclk;
5985 }
5986
5987 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5988 {
5989         struct drm_device *dev = state->dev;
5990         struct drm_i915_private *dev_priv = dev->dev_private;
5991         int max_pixclk = intel_mode_max_pixclk(dev, state);
5992
5993         if (max_pixclk < 0)
5994                 return max_pixclk;
5995
5996         to_intel_atomic_state(state)->cdclk =
5997                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5998
5999         return 0;
6000 }
6001
6002 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6003 {
6004         struct drm_device *dev = state->dev;
6005         struct drm_i915_private *dev_priv = dev->dev_private;
6006         int max_pixclk = intel_mode_max_pixclk(dev, state);
6007
6008         if (max_pixclk < 0)
6009                 return max_pixclk;
6010
6011         to_intel_atomic_state(state)->cdclk =
6012                 broxton_calc_cdclk(dev_priv, max_pixclk);
6013
6014         return 0;
6015 }
6016
6017 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6018 {
6019         unsigned int credits, default_credits;
6020
6021         if (IS_CHERRYVIEW(dev_priv))
6022                 default_credits = PFI_CREDIT(12);
6023         else
6024                 default_credits = PFI_CREDIT(8);
6025
6026         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6027                 /* CHV suggested value is 31 or 63 */
6028                 if (IS_CHERRYVIEW(dev_priv))
6029                         credits = PFI_CREDIT_63;
6030                 else
6031                         credits = PFI_CREDIT(15);
6032         } else {
6033                 credits = default_credits;
6034         }
6035
6036         /*
6037          * WA - write default credits before re-programming
6038          * FIXME: should we also set the resend bit here?
6039          */
6040         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6041                    default_credits);
6042
6043         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6044                    credits | PFI_CREDIT_RESEND);
6045
6046         /*
6047          * FIXME is this guaranteed to clear
6048          * immediately or should we poll for it?
6049          */
6050         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6051 }
6052
6053 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6054 {
6055         struct drm_device *dev = old_state->dev;
6056         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058
6059         /*
6060          * FIXME: We can end up here with all power domains off, yet
6061          * with a CDCLK frequency other than the minimum. To account
6062          * for this take the PIPE-A power domain, which covers the HW
6063          * blocks needed for the following programming. This can be
6064          * removed once it's guaranteed that we get here either with
6065          * the minimum CDCLK set, or the required power domains
6066          * enabled.
6067          */
6068         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6069
6070         if (IS_CHERRYVIEW(dev))
6071                 cherryview_set_cdclk(dev, req_cdclk);
6072         else
6073                 valleyview_set_cdclk(dev, req_cdclk);
6074
6075         vlv_program_pfi_credits(dev_priv);
6076
6077         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6078 }
6079
6080 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6081 {
6082         struct drm_device *dev = crtc->dev;
6083         struct drm_i915_private *dev_priv = to_i915(dev);
6084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6085         struct intel_encoder *encoder;
6086         int pipe = intel_crtc->pipe;
6087         bool is_dsi;
6088
6089         if (WARN_ON(intel_crtc->active))
6090                 return;
6091
6092         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6093
6094         if (intel_crtc->config->has_dp_encoder)
6095                 intel_dp_set_m_n(intel_crtc, M1_N1);
6096
6097         intel_set_pipe_timings(intel_crtc);
6098
6099         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6100                 struct drm_i915_private *dev_priv = dev->dev_private;
6101
6102                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6103                 I915_WRITE(CHV_CANVAS(pipe), 0);
6104         }
6105
6106         i9xx_set_pipeconf(intel_crtc);
6107
6108         intel_crtc->active = true;
6109
6110         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6111
6112         for_each_encoder_on_crtc(dev, crtc, encoder)
6113                 if (encoder->pre_pll_enable)
6114                         encoder->pre_pll_enable(encoder);
6115
6116         if (!is_dsi) {
6117                 if (IS_CHERRYVIEW(dev)) {
6118                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6119                         chv_enable_pll(intel_crtc, intel_crtc->config);
6120                 } else {
6121                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6122                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6123                 }
6124         }
6125
6126         for_each_encoder_on_crtc(dev, crtc, encoder)
6127                 if (encoder->pre_enable)
6128                         encoder->pre_enable(encoder);
6129
6130         i9xx_pfit_enable(intel_crtc);
6131
6132         intel_crtc_load_lut(crtc);
6133
6134         intel_enable_pipe(intel_crtc);
6135
6136         assert_vblank_disabled(crtc);
6137         drm_crtc_vblank_on(crtc);
6138
6139         for_each_encoder_on_crtc(dev, crtc, encoder)
6140                 encoder->enable(encoder);
6141 }
6142
6143 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6144 {
6145         struct drm_device *dev = crtc->base.dev;
6146         struct drm_i915_private *dev_priv = dev->dev_private;
6147
6148         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6149         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6150 }
6151
6152 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6153 {
6154         struct drm_device *dev = crtc->dev;
6155         struct drm_i915_private *dev_priv = to_i915(dev);
6156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157         struct intel_encoder *encoder;
6158         int pipe = intel_crtc->pipe;
6159
6160         if (WARN_ON(intel_crtc->active))
6161                 return;
6162
6163         i9xx_set_pll_dividers(intel_crtc);
6164
6165         if (intel_crtc->config->has_dp_encoder)
6166                 intel_dp_set_m_n(intel_crtc, M1_N1);
6167
6168         intel_set_pipe_timings(intel_crtc);
6169
6170         i9xx_set_pipeconf(intel_crtc);
6171
6172         intel_crtc->active = true;
6173
6174         if (!IS_GEN2(dev))
6175                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6176
6177         for_each_encoder_on_crtc(dev, crtc, encoder)
6178                 if (encoder->pre_enable)
6179                         encoder->pre_enable(encoder);
6180
6181         i9xx_enable_pll(intel_crtc);
6182
6183         i9xx_pfit_enable(intel_crtc);
6184
6185         intel_crtc_load_lut(crtc);
6186
6187         intel_update_watermarks(crtc);
6188         intel_enable_pipe(intel_crtc);
6189
6190         assert_vblank_disabled(crtc);
6191         drm_crtc_vblank_on(crtc);
6192
6193         for_each_encoder_on_crtc(dev, crtc, encoder)
6194                 encoder->enable(encoder);
6195 }
6196
6197 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6198 {
6199         struct drm_device *dev = crtc->base.dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201
6202         if (!crtc->config->gmch_pfit.control)
6203                 return;
6204
6205         assert_pipe_disabled(dev_priv, crtc->pipe);
6206
6207         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6208                          I915_READ(PFIT_CONTROL));
6209         I915_WRITE(PFIT_CONTROL, 0);
6210 }
6211
6212 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6213 {
6214         struct drm_device *dev = crtc->dev;
6215         struct drm_i915_private *dev_priv = dev->dev_private;
6216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217         struct intel_encoder *encoder;
6218         int pipe = intel_crtc->pipe;
6219
6220         /*
6221          * On gen2 planes are double buffered but the pipe isn't, so we must
6222          * wait for planes to fully turn off before disabling the pipe.
6223          * We also need to wait on all gmch platforms because of the
6224          * self-refresh mode constraint explained above.
6225          */
6226         intel_wait_for_vblank(dev, pipe);
6227
6228         for_each_encoder_on_crtc(dev, crtc, encoder)
6229                 encoder->disable(encoder);
6230
6231         drm_crtc_vblank_off(crtc);
6232         assert_vblank_disabled(crtc);
6233
6234         intel_disable_pipe(intel_crtc);
6235
6236         i9xx_pfit_disable(intel_crtc);
6237
6238         for_each_encoder_on_crtc(dev, crtc, encoder)
6239                 if (encoder->post_disable)
6240                         encoder->post_disable(encoder);
6241
6242         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6243                 if (IS_CHERRYVIEW(dev))
6244                         chv_disable_pll(dev_priv, pipe);
6245                 else if (IS_VALLEYVIEW(dev))
6246                         vlv_disable_pll(dev_priv, pipe);
6247                 else
6248                         i9xx_disable_pll(intel_crtc);
6249         }
6250
6251         for_each_encoder_on_crtc(dev, crtc, encoder)
6252                 if (encoder->post_pll_disable)
6253                         encoder->post_pll_disable(encoder);
6254
6255         if (!IS_GEN2(dev))
6256                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6257
6258         intel_crtc->active = false;
6259         intel_update_watermarks(crtc);
6260 }
6261
6262 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6263 {
6264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6266         enum intel_display_power_domain domain;
6267         unsigned long domains;
6268
6269         if (!intel_crtc->active)
6270                 return;
6271
6272         if (to_intel_plane_state(crtc->primary->state)->visible) {
6273                 intel_crtc_wait_for_pending_flips(crtc);
6274                 intel_pre_disable_primary(crtc);
6275         }
6276
6277         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6278         dev_priv->display.crtc_disable(crtc);
6279         intel_disable_shared_dpll(intel_crtc);
6280
6281         domains = intel_crtc->enabled_power_domains;
6282         for_each_power_domain(domain, domains)
6283                 intel_display_power_put(dev_priv, domain);
6284         intel_crtc->enabled_power_domains = 0;
6285 }
6286
6287 /*
6288  * turn all crtc's off, but do not adjust state
6289  * This has to be paired with a call to intel_modeset_setup_hw_state.
6290  */
6291 int intel_display_suspend(struct drm_device *dev)
6292 {
6293         struct drm_mode_config *config = &dev->mode_config;
6294         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6295         struct drm_atomic_state *state;
6296         struct drm_crtc *crtc;
6297         unsigned crtc_mask = 0;
6298         int ret = 0;
6299
6300         if (WARN_ON(!ctx))
6301                 return 0;
6302
6303         lockdep_assert_held(&ctx->ww_ctx);
6304         state = drm_atomic_state_alloc(dev);
6305         if (WARN_ON(!state))
6306                 return -ENOMEM;
6307
6308         state->acquire_ctx = ctx;
6309         state->allow_modeset = true;
6310
6311         for_each_crtc(dev, crtc) {
6312                 struct drm_crtc_state *crtc_state =
6313                         drm_atomic_get_crtc_state(state, crtc);
6314
6315                 ret = PTR_ERR_OR_ZERO(crtc_state);
6316                 if (ret)
6317                         goto free;
6318
6319                 if (!crtc_state->active)
6320                         continue;
6321
6322                 crtc_state->active = false;
6323                 crtc_mask |= 1 << drm_crtc_index(crtc);
6324         }
6325
6326         if (crtc_mask) {
6327                 ret = drm_atomic_commit(state);
6328
6329                 if (!ret) {
6330                         for_each_crtc(dev, crtc)
6331                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6332                                         crtc->state->active = true;
6333
6334                         return ret;
6335                 }
6336         }
6337
6338 free:
6339         if (ret)
6340                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6341         drm_atomic_state_free(state);
6342         return ret;
6343 }
6344
6345 void intel_encoder_destroy(struct drm_encoder *encoder)
6346 {
6347         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6348
6349         drm_encoder_cleanup(encoder);
6350         kfree(intel_encoder);
6351 }
6352
6353 /* Cross check the actual hw state with our own modeset state tracking (and it's
6354  * internal consistency). */
6355 static void intel_connector_check_state(struct intel_connector *connector)
6356 {
6357         struct drm_crtc *crtc = connector->base.state->crtc;
6358
6359         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360                       connector->base.base.id,
6361                       connector->base.name);
6362
6363         if (connector->get_hw_state(connector)) {
6364                 struct intel_encoder *encoder = connector->encoder;
6365                 struct drm_connector_state *conn_state = connector->base.state;
6366
6367                 I915_STATE_WARN(!crtc,
6368                          "connector enabled without attached crtc\n");
6369
6370                 if (!crtc)
6371                         return;
6372
6373                 I915_STATE_WARN(!crtc->state->active,
6374                       "connector is active, but attached crtc isn't\n");
6375
6376                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6377                         return;
6378
6379                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6380                         "atomic encoder doesn't match attached encoder\n");
6381
6382                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6383                         "attached encoder crtc differs from connector crtc\n");
6384         } else {
6385                 I915_STATE_WARN(crtc && crtc->state->active,
6386                         "attached crtc is active, but connector isn't\n");
6387                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6388                         "best encoder set without crtc!\n");
6389         }
6390 }
6391
6392 int intel_connector_init(struct intel_connector *connector)
6393 {
6394         struct drm_connector_state *connector_state;
6395
6396         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6397         if (!connector_state)
6398                 return -ENOMEM;
6399
6400         connector->base.state = connector_state;
6401         return 0;
6402 }
6403
6404 struct intel_connector *intel_connector_alloc(void)
6405 {
6406         struct intel_connector *connector;
6407
6408         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6409         if (!connector)
6410                 return NULL;
6411
6412         if (intel_connector_init(connector) < 0) {
6413                 kfree(connector);
6414                 return NULL;
6415         }
6416
6417         return connector;
6418 }
6419
6420 /* Simple connector->get_hw_state implementation for encoders that support only
6421  * one connector and no cloning and hence the encoder state determines the state
6422  * of the connector. */
6423 bool intel_connector_get_hw_state(struct intel_connector *connector)
6424 {
6425         enum pipe pipe = 0;
6426         struct intel_encoder *encoder = connector->encoder;
6427
6428         return encoder->get_hw_state(encoder, &pipe);
6429 }
6430
6431 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6432 {
6433         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6434                 return crtc_state->fdi_lanes;
6435
6436         return 0;
6437 }
6438
6439 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6440                                      struct intel_crtc_state *pipe_config)
6441 {
6442         struct drm_atomic_state *state = pipe_config->base.state;
6443         struct intel_crtc *other_crtc;
6444         struct intel_crtc_state *other_crtc_state;
6445
6446         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6447                       pipe_name(pipe), pipe_config->fdi_lanes);
6448         if (pipe_config->fdi_lanes > 4) {
6449                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6450                               pipe_name(pipe), pipe_config->fdi_lanes);
6451                 return -EINVAL;
6452         }
6453
6454         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6455                 if (pipe_config->fdi_lanes > 2) {
6456                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6457                                       pipe_config->fdi_lanes);
6458                         return -EINVAL;
6459                 } else {
6460                         return 0;
6461                 }
6462         }
6463
6464         if (INTEL_INFO(dev)->num_pipes == 2)
6465                 return 0;
6466
6467         /* Ivybridge 3 pipe is really complicated */
6468         switch (pipe) {
6469         case PIPE_A:
6470                 return 0;
6471         case PIPE_B:
6472                 if (pipe_config->fdi_lanes <= 2)
6473                         return 0;
6474
6475                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6476                 other_crtc_state =
6477                         intel_atomic_get_crtc_state(state, other_crtc);
6478                 if (IS_ERR(other_crtc_state))
6479                         return PTR_ERR(other_crtc_state);
6480
6481                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6482                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6483                                       pipe_name(pipe), pipe_config->fdi_lanes);
6484                         return -EINVAL;
6485                 }
6486                 return 0;
6487         case PIPE_C:
6488                 if (pipe_config->fdi_lanes > 2) {
6489                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6490                                       pipe_name(pipe), pipe_config->fdi_lanes);
6491                         return -EINVAL;
6492                 }
6493
6494                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6495                 other_crtc_state =
6496                         intel_atomic_get_crtc_state(state, other_crtc);
6497                 if (IS_ERR(other_crtc_state))
6498                         return PTR_ERR(other_crtc_state);
6499
6500                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6501                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6502                         return -EINVAL;
6503                 }
6504                 return 0;
6505         default:
6506                 BUG();
6507         }
6508 }
6509
6510 #define RETRY 1
6511 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6512                                        struct intel_crtc_state *pipe_config)
6513 {
6514         struct drm_device *dev = intel_crtc->base.dev;
6515         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6516         int lane, link_bw, fdi_dotclock, ret;
6517         bool needs_recompute = false;
6518
6519 retry:
6520         /* FDI is a binary signal running at ~2.7GHz, encoding
6521          * each output octet as 10 bits. The actual frequency
6522          * is stored as a divider into a 100MHz clock, and the
6523          * mode pixel clock is stored in units of 1KHz.
6524          * Hence the bw of each lane in terms of the mode signal
6525          * is:
6526          */
6527         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6528
6529         fdi_dotclock = adjusted_mode->crtc_clock;
6530
6531         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6532                                            pipe_config->pipe_bpp);
6533
6534         pipe_config->fdi_lanes = lane;
6535
6536         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6537                                link_bw, &pipe_config->fdi_m_n);
6538
6539         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6540                                        intel_crtc->pipe, pipe_config);
6541         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6542                 pipe_config->pipe_bpp -= 2*3;
6543                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6544                               pipe_config->pipe_bpp);
6545                 needs_recompute = true;
6546                 pipe_config->bw_constrained = true;
6547
6548                 goto retry;
6549         }
6550
6551         if (needs_recompute)
6552                 return RETRY;
6553
6554         return ret;
6555 }
6556
6557 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6558                                      struct intel_crtc_state *pipe_config)
6559 {
6560         if (pipe_config->pipe_bpp > 24)
6561                 return false;
6562
6563         /* HSW can handle pixel rate up to cdclk? */
6564         if (IS_HASWELL(dev_priv->dev))
6565                 return true;
6566
6567         /*
6568          * We compare against max which means we must take
6569          * the increased cdclk requirement into account when
6570          * calculating the new cdclk.
6571          *
6572          * Should measure whether using a lower cdclk w/o IPS
6573          */
6574         return ilk_pipe_pixel_rate(pipe_config) <=
6575                 dev_priv->max_cdclk_freq * 95 / 100;
6576 }
6577
6578 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6579                                    struct intel_crtc_state *pipe_config)
6580 {
6581         struct drm_device *dev = crtc->base.dev;
6582         struct drm_i915_private *dev_priv = dev->dev_private;
6583
6584         pipe_config->ips_enabled = i915.enable_ips &&
6585                 hsw_crtc_supports_ips(crtc) &&
6586                 pipe_config_supports_ips(dev_priv, pipe_config);
6587 }
6588
6589 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6590                                      struct intel_crtc_state *pipe_config)
6591 {
6592         struct drm_device *dev = crtc->base.dev;
6593         struct drm_i915_private *dev_priv = dev->dev_private;
6594         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6595
6596         /* FIXME should check pixel clock limits on all platforms */
6597         if (INTEL_INFO(dev)->gen < 4) {
6598                 int clock_limit = dev_priv->max_cdclk_freq;
6599
6600                 /*
6601                  * Enable pixel doubling when the dot clock
6602                  * is > 90% of the (display) core speed.
6603                  *
6604                  * GDG double wide on either pipe,
6605                  * otherwise pipe A only.
6606                  */
6607                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6608                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6609                         clock_limit *= 2;
6610                         pipe_config->double_wide = true;
6611                 }
6612
6613                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6614                         return -EINVAL;
6615         }
6616
6617         /*
6618          * Pipe horizontal size must be even in:
6619          * - DVO ganged mode
6620          * - LVDS dual channel mode
6621          * - Double wide pipe
6622          */
6623         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6624              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6625                 pipe_config->pipe_src_w &= ~1;
6626
6627         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6628          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6629          */
6630         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6631                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6632                 return -EINVAL;
6633
6634         if (HAS_IPS(dev))
6635                 hsw_compute_ips_config(crtc, pipe_config);
6636
6637         if (pipe_config->has_pch_encoder)
6638                 return ironlake_fdi_compute_config(crtc, pipe_config);
6639
6640         return 0;
6641 }
6642
6643 static int skylake_get_display_clock_speed(struct drm_device *dev)
6644 {
6645         struct drm_i915_private *dev_priv = to_i915(dev);
6646         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6647         uint32_t cdctl = I915_READ(CDCLK_CTL);
6648         uint32_t linkrate;
6649
6650         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6651                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6652
6653         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6654                 return 540000;
6655
6656         linkrate = (I915_READ(DPLL_CTRL1) &
6657                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6658
6659         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6660             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6661                 /* vco 8640 */
6662                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6663                 case CDCLK_FREQ_450_432:
6664                         return 432000;
6665                 case CDCLK_FREQ_337_308:
6666                         return 308570;
6667                 case CDCLK_FREQ_675_617:
6668                         return 617140;
6669                 default:
6670                         WARN(1, "Unknown cd freq selection\n");
6671                 }
6672         } else {
6673                 /* vco 8100 */
6674                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6675                 case CDCLK_FREQ_450_432:
6676                         return 450000;
6677                 case CDCLK_FREQ_337_308:
6678                         return 337500;
6679                 case CDCLK_FREQ_675_617:
6680                         return 675000;
6681                 default:
6682                         WARN(1, "Unknown cd freq selection\n");
6683                 }
6684         }
6685
6686         /* error case, do as if DPLL0 isn't enabled */
6687         return 24000;
6688 }
6689
6690 static int broxton_get_display_clock_speed(struct drm_device *dev)
6691 {
6692         struct drm_i915_private *dev_priv = to_i915(dev);
6693         uint32_t cdctl = I915_READ(CDCLK_CTL);
6694         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6695         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6696         int cdclk;
6697
6698         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6699                 return 19200;
6700
6701         cdclk = 19200 * pll_ratio / 2;
6702
6703         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6704         case BXT_CDCLK_CD2X_DIV_SEL_1:
6705                 return cdclk;  /* 576MHz or 624MHz */
6706         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6707                 return cdclk * 2 / 3; /* 384MHz */
6708         case BXT_CDCLK_CD2X_DIV_SEL_2:
6709                 return cdclk / 2; /* 288MHz */
6710         case BXT_CDCLK_CD2X_DIV_SEL_4:
6711                 return cdclk / 4; /* 144MHz */
6712         }
6713
6714         /* error case, do as if DE PLL isn't enabled */
6715         return 19200;
6716 }
6717
6718 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6719 {
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         uint32_t lcpll = I915_READ(LCPLL_CTL);
6722         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6723
6724         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6725                 return 800000;
6726         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6727                 return 450000;
6728         else if (freq == LCPLL_CLK_FREQ_450)
6729                 return 450000;
6730         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6731                 return 540000;
6732         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6733                 return 337500;
6734         else
6735                 return 675000;
6736 }
6737
6738 static int haswell_get_display_clock_speed(struct drm_device *dev)
6739 {
6740         struct drm_i915_private *dev_priv = dev->dev_private;
6741         uint32_t lcpll = I915_READ(LCPLL_CTL);
6742         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6743
6744         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6745                 return 800000;
6746         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6747                 return 450000;
6748         else if (freq == LCPLL_CLK_FREQ_450)
6749                 return 450000;
6750         else if (IS_HSW_ULT(dev))
6751                 return 337500;
6752         else
6753                 return 540000;
6754 }
6755
6756 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6757 {
6758         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6759                                       CCK_DISPLAY_CLOCK_CONTROL);
6760 }
6761
6762 static int ilk_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         return 450000;
6765 }
6766
6767 static int i945_get_display_clock_speed(struct drm_device *dev)
6768 {
6769         return 400000;
6770 }
6771
6772 static int i915_get_display_clock_speed(struct drm_device *dev)
6773 {
6774         return 333333;
6775 }
6776
6777 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6778 {
6779         return 200000;
6780 }
6781
6782 static int pnv_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         u16 gcfgc = 0;
6785
6786         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6787
6788         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6789         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6790                 return 266667;
6791         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6792                 return 333333;
6793         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6794                 return 444444;
6795         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6796                 return 200000;
6797         default:
6798                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6799         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6800                 return 133333;
6801         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6802                 return 166667;
6803         }
6804 }
6805
6806 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6807 {
6808         u16 gcfgc = 0;
6809
6810         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6811
6812         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6813                 return 133333;
6814         else {
6815                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6816                 case GC_DISPLAY_CLOCK_333_MHZ:
6817                         return 333333;
6818                 default:
6819                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6820                         return 190000;
6821                 }
6822         }
6823 }
6824
6825 static int i865_get_display_clock_speed(struct drm_device *dev)
6826 {
6827         return 266667;
6828 }
6829
6830 static int i85x_get_display_clock_speed(struct drm_device *dev)
6831 {
6832         u16 hpllcc = 0;
6833
6834         /*
6835          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6836          * encoding is different :(
6837          * FIXME is this the right way to detect 852GM/852GMV?
6838          */
6839         if (dev->pdev->revision == 0x1)
6840                 return 133333;
6841
6842         pci_bus_read_config_word(dev->pdev->bus,
6843                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6844
6845         /* Assume that the hardware is in the high speed state.  This
6846          * should be the default.
6847          */
6848         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6849         case GC_CLOCK_133_200:
6850         case GC_CLOCK_133_200_2:
6851         case GC_CLOCK_100_200:
6852                 return 200000;
6853         case GC_CLOCK_166_250:
6854                 return 250000;
6855         case GC_CLOCK_100_133:
6856                 return 133333;
6857         case GC_CLOCK_133_266:
6858         case GC_CLOCK_133_266_2:
6859         case GC_CLOCK_166_266:
6860                 return 266667;
6861         }
6862
6863         /* Shouldn't happen */
6864         return 0;
6865 }
6866
6867 static int i830_get_display_clock_speed(struct drm_device *dev)
6868 {
6869         return 133333;
6870 }
6871
6872 static unsigned int intel_hpll_vco(struct drm_device *dev)
6873 {
6874         struct drm_i915_private *dev_priv = dev->dev_private;
6875         static const unsigned int blb_vco[8] = {
6876                 [0] = 3200000,
6877                 [1] = 4000000,
6878                 [2] = 5333333,
6879                 [3] = 4800000,
6880                 [4] = 6400000,
6881         };
6882         static const unsigned int pnv_vco[8] = {
6883                 [0] = 3200000,
6884                 [1] = 4000000,
6885                 [2] = 5333333,
6886                 [3] = 4800000,
6887                 [4] = 2666667,
6888         };
6889         static const unsigned int cl_vco[8] = {
6890                 [0] = 3200000,
6891                 [1] = 4000000,
6892                 [2] = 5333333,
6893                 [3] = 6400000,
6894                 [4] = 3333333,
6895                 [5] = 3566667,
6896                 [6] = 4266667,
6897         };
6898         static const unsigned int elk_vco[8] = {
6899                 [0] = 3200000,
6900                 [1] = 4000000,
6901                 [2] = 5333333,
6902                 [3] = 4800000,
6903         };
6904         static const unsigned int ctg_vco[8] = {
6905                 [0] = 3200000,
6906                 [1] = 4000000,
6907                 [2] = 5333333,
6908                 [3] = 6400000,
6909                 [4] = 2666667,
6910                 [5] = 4266667,
6911         };
6912         const unsigned int *vco_table;
6913         unsigned int vco;
6914         uint8_t tmp = 0;
6915
6916         /* FIXME other chipsets? */
6917         if (IS_GM45(dev))
6918                 vco_table = ctg_vco;
6919         else if (IS_G4X(dev))
6920                 vco_table = elk_vco;
6921         else if (IS_CRESTLINE(dev))
6922                 vco_table = cl_vco;
6923         else if (IS_PINEVIEW(dev))
6924                 vco_table = pnv_vco;
6925         else if (IS_G33(dev))
6926                 vco_table = blb_vco;
6927         else
6928                 return 0;
6929
6930         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6931
6932         vco = vco_table[tmp & 0x7];
6933         if (vco == 0)
6934                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6935         else
6936                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6937
6938         return vco;
6939 }
6940
6941 static int gm45_get_display_clock_speed(struct drm_device *dev)
6942 {
6943         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6944         uint16_t tmp = 0;
6945
6946         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6947
6948         cdclk_sel = (tmp >> 12) & 0x1;
6949
6950         switch (vco) {
6951         case 2666667:
6952         case 4000000:
6953         case 5333333:
6954                 return cdclk_sel ? 333333 : 222222;
6955         case 3200000:
6956                 return cdclk_sel ? 320000 : 228571;
6957         default:
6958                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6959                 return 222222;
6960         }
6961 }
6962
6963 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6964 {
6965         static const uint8_t div_3200[] = { 16, 10,  8 };
6966         static const uint8_t div_4000[] = { 20, 12, 10 };
6967         static const uint8_t div_5333[] = { 24, 16, 14 };
6968         const uint8_t *div_table;
6969         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6970         uint16_t tmp = 0;
6971
6972         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6973
6974         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6975
6976         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6977                 goto fail;
6978
6979         switch (vco) {
6980         case 3200000:
6981                 div_table = div_3200;
6982                 break;
6983         case 4000000:
6984                 div_table = div_4000;
6985                 break;
6986         case 5333333:
6987                 div_table = div_5333;
6988                 break;
6989         default:
6990                 goto fail;
6991         }
6992
6993         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6994
6995 fail:
6996         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6997         return 200000;
6998 }
6999
7000 static int g33_get_display_clock_speed(struct drm_device *dev)
7001 {
7002         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7003         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7004         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7005         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7006         const uint8_t *div_table;
7007         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7008         uint16_t tmp = 0;
7009
7010         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7011
7012         cdclk_sel = (tmp >> 4) & 0x7;
7013
7014         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7015                 goto fail;
7016
7017         switch (vco) {
7018         case 3200000:
7019                 div_table = div_3200;
7020                 break;
7021         case 4000000:
7022                 div_table = div_4000;
7023                 break;
7024         case 4800000:
7025                 div_table = div_4800;
7026                 break;
7027         case 5333333:
7028                 div_table = div_5333;
7029                 break;
7030         default:
7031                 goto fail;
7032         }
7033
7034         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7035
7036 fail:
7037         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7038         return 190476;
7039 }
7040
7041 static void
7042 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7043 {
7044         while (*num > DATA_LINK_M_N_MASK ||
7045                *den > DATA_LINK_M_N_MASK) {
7046                 *num >>= 1;
7047                 *den >>= 1;
7048         }
7049 }
7050
7051 static void compute_m_n(unsigned int m, unsigned int n,
7052                         uint32_t *ret_m, uint32_t *ret_n)
7053 {
7054         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7055         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7056         intel_reduce_m_n_ratio(ret_m, ret_n);
7057 }
7058
7059 void
7060 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7061                        int pixel_clock, int link_clock,
7062                        struct intel_link_m_n *m_n)
7063 {
7064         m_n->tu = 64;
7065
7066         compute_m_n(bits_per_pixel * pixel_clock,
7067                     link_clock * nlanes * 8,
7068                     &m_n->gmch_m, &m_n->gmch_n);
7069
7070         compute_m_n(pixel_clock, link_clock,
7071                     &m_n->link_m, &m_n->link_n);
7072 }
7073
7074 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7075 {
7076         if (i915.panel_use_ssc >= 0)
7077                 return i915.panel_use_ssc != 0;
7078         return dev_priv->vbt.lvds_use_ssc
7079                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7080 }
7081
7082 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7083                            int num_connectors)
7084 {
7085         struct drm_device *dev = crtc_state->base.crtc->dev;
7086         struct drm_i915_private *dev_priv = dev->dev_private;
7087         int refclk;
7088
7089         WARN_ON(!crtc_state->base.state);
7090
7091         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7092                 refclk = 100000;
7093         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7094             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7095                 refclk = dev_priv->vbt.lvds_ssc_freq;
7096                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7097         } else if (!IS_GEN2(dev)) {
7098                 refclk = 96000;
7099         } else {
7100                 refclk = 48000;
7101         }
7102
7103         return refclk;
7104 }
7105
7106 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7107 {
7108         return (1 << dpll->n) << 16 | dpll->m2;
7109 }
7110
7111 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7112 {
7113         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7114 }
7115
7116 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7117                                      struct intel_crtc_state *crtc_state,
7118                                      intel_clock_t *reduced_clock)
7119 {
7120         struct drm_device *dev = crtc->base.dev;
7121         u32 fp, fp2 = 0;
7122
7123         if (IS_PINEVIEW(dev)) {
7124                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7125                 if (reduced_clock)
7126                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7127         } else {
7128                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7129                 if (reduced_clock)
7130                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7131         }
7132
7133         crtc_state->dpll_hw_state.fp0 = fp;
7134
7135         crtc->lowfreq_avail = false;
7136         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7137             reduced_clock) {
7138                 crtc_state->dpll_hw_state.fp1 = fp2;
7139                 crtc->lowfreq_avail = true;
7140         } else {
7141                 crtc_state->dpll_hw_state.fp1 = fp;
7142         }
7143 }
7144
7145 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7146                 pipe)
7147 {
7148         u32 reg_val;
7149
7150         /*
7151          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7152          * and set it to a reasonable value instead.
7153          */
7154         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7155         reg_val &= 0xffffff00;
7156         reg_val |= 0x00000030;
7157         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7158
7159         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7160         reg_val &= 0x8cffffff;
7161         reg_val = 0x8c000000;
7162         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7163
7164         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7165         reg_val &= 0xffffff00;
7166         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7167
7168         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7169         reg_val &= 0x00ffffff;
7170         reg_val |= 0xb0000000;
7171         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7172 }
7173
7174 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7175                                          struct intel_link_m_n *m_n)
7176 {
7177         struct drm_device *dev = crtc->base.dev;
7178         struct drm_i915_private *dev_priv = dev->dev_private;
7179         int pipe = crtc->pipe;
7180
7181         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7182         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7183         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7184         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7185 }
7186
7187 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7188                                          struct intel_link_m_n *m_n,
7189                                          struct intel_link_m_n *m2_n2)
7190 {
7191         struct drm_device *dev = crtc->base.dev;
7192         struct drm_i915_private *dev_priv = dev->dev_private;
7193         int pipe = crtc->pipe;
7194         enum transcoder transcoder = crtc->config->cpu_transcoder;
7195
7196         if (INTEL_INFO(dev)->gen >= 5) {
7197                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7199                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7200                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7201                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7202                  * for gen < 8) and if DRRS is supported (to make sure the
7203                  * registers are not unnecessarily accessed).
7204                  */
7205                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7206                         crtc->config->has_drrs) {
7207                         I915_WRITE(PIPE_DATA_M2(transcoder),
7208                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7209                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7210                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7211                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7212                 }
7213         } else {
7214                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7215                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7216                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7217                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7218         }
7219 }
7220
7221 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7222 {
7223         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7224
7225         if (m_n == M1_N1) {
7226                 dp_m_n = &crtc->config->dp_m_n;
7227                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7228         } else if (m_n == M2_N2) {
7229
7230                 /*
7231                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7232                  * needs to be programmed into M1_N1.
7233                  */
7234                 dp_m_n = &crtc->config->dp_m2_n2;
7235         } else {
7236                 DRM_ERROR("Unsupported divider value\n");
7237                 return;
7238         }
7239
7240         if (crtc->config->has_pch_encoder)
7241                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7242         else
7243                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7244 }
7245
7246 static void vlv_compute_dpll(struct intel_crtc *crtc,
7247                              struct intel_crtc_state *pipe_config)
7248 {
7249         u32 dpll, dpll_md;
7250
7251         /*
7252          * Enable DPIO clock input. We should never disable the reference
7253          * clock for pipe B, since VGA hotplug / manual detection depends
7254          * on it.
7255          */
7256         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7257                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7258         /* We should never disable this, set it here for state tracking */
7259         if (crtc->pipe == PIPE_B)
7260                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7261         dpll |= DPLL_VCO_ENABLE;
7262         pipe_config->dpll_hw_state.dpll = dpll;
7263
7264         dpll_md = (pipe_config->pixel_multiplier - 1)
7265                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7266         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7267 }
7268
7269 static void vlv_prepare_pll(struct intel_crtc *crtc,
7270                             const struct intel_crtc_state *pipe_config)
7271 {
7272         struct drm_device *dev = crtc->base.dev;
7273         struct drm_i915_private *dev_priv = dev->dev_private;
7274         int pipe = crtc->pipe;
7275         u32 mdiv;
7276         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7277         u32 coreclk, reg_val;
7278
7279         mutex_lock(&dev_priv->sb_lock);
7280
7281         bestn = pipe_config->dpll.n;
7282         bestm1 = pipe_config->dpll.m1;
7283         bestm2 = pipe_config->dpll.m2;
7284         bestp1 = pipe_config->dpll.p1;
7285         bestp2 = pipe_config->dpll.p2;
7286
7287         /* See eDP HDMI DPIO driver vbios notes doc */
7288
7289         /* PLL B needs special handling */
7290         if (pipe == PIPE_B)
7291                 vlv_pllb_recal_opamp(dev_priv, pipe);
7292
7293         /* Set up Tx target for periodic Rcomp update */
7294         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7295
7296         /* Disable target IRef on PLL */
7297         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7298         reg_val &= 0x00ffffff;
7299         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7300
7301         /* Disable fast lock */
7302         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7303
7304         /* Set idtafcrecal before PLL is enabled */
7305         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7306         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7307         mdiv |= ((bestn << DPIO_N_SHIFT));
7308         mdiv |= (1 << DPIO_K_SHIFT);
7309
7310         /*
7311          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7312          * but we don't support that).
7313          * Note: don't use the DAC post divider as it seems unstable.
7314          */
7315         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7316         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7317
7318         mdiv |= DPIO_ENABLE_CALIBRATION;
7319         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7320
7321         /* Set HBR and RBR LPF coefficients */
7322         if (pipe_config->port_clock == 162000 ||
7323             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7324             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7325                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7326                                  0x009f0003);
7327         else
7328                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7329                                  0x00d0000f);
7330
7331         if (pipe_config->has_dp_encoder) {
7332                 /* Use SSC source */
7333                 if (pipe == PIPE_A)
7334                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7335                                          0x0df40000);
7336                 else
7337                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7338                                          0x0df70000);
7339         } else { /* HDMI or VGA */
7340                 /* Use bend source */
7341                 if (pipe == PIPE_A)
7342                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7343                                          0x0df70000);
7344                 else
7345                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7346                                          0x0df40000);
7347         }
7348
7349         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7350         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7351         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7352             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7353                 coreclk |= 0x01000000;
7354         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7355
7356         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7357         mutex_unlock(&dev_priv->sb_lock);
7358 }
7359
7360 static void chv_compute_dpll(struct intel_crtc *crtc,
7361                              struct intel_crtc_state *pipe_config)
7362 {
7363         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7364                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7365                 DPLL_VCO_ENABLE;
7366         if (crtc->pipe != PIPE_A)
7367                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7368
7369         pipe_config->dpll_hw_state.dpll_md =
7370                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7371 }
7372
7373 static void chv_prepare_pll(struct intel_crtc *crtc,
7374                             const struct intel_crtc_state *pipe_config)
7375 {
7376         struct drm_device *dev = crtc->base.dev;
7377         struct drm_i915_private *dev_priv = dev->dev_private;
7378         int pipe = crtc->pipe;
7379         int dpll_reg = DPLL(crtc->pipe);
7380         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7381         u32 loopfilter, tribuf_calcntr;
7382         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7383         u32 dpio_val;
7384         int vco;
7385
7386         bestn = pipe_config->dpll.n;
7387         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7388         bestm1 = pipe_config->dpll.m1;
7389         bestm2 = pipe_config->dpll.m2 >> 22;
7390         bestp1 = pipe_config->dpll.p1;
7391         bestp2 = pipe_config->dpll.p2;
7392         vco = pipe_config->dpll.vco;
7393         dpio_val = 0;
7394         loopfilter = 0;
7395
7396         /*
7397          * Enable Refclk and SSC
7398          */
7399         I915_WRITE(dpll_reg,
7400                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7401
7402         mutex_lock(&dev_priv->sb_lock);
7403
7404         /* p1 and p2 divider */
7405         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7406                         5 << DPIO_CHV_S1_DIV_SHIFT |
7407                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7408                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7409                         1 << DPIO_CHV_K_DIV_SHIFT);
7410
7411         /* Feedback post-divider - m2 */
7412         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7413
7414         /* Feedback refclk divider - n and m1 */
7415         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7416                         DPIO_CHV_M1_DIV_BY_2 |
7417                         1 << DPIO_CHV_N_DIV_SHIFT);
7418
7419         /* M2 fraction division */
7420         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7421
7422         /* M2 fraction division enable */
7423         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7424         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7425         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7426         if (bestm2_frac)
7427                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7428         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7429
7430         /* Program digital lock detect threshold */
7431         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7432         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7433                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7434         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7435         if (!bestm2_frac)
7436                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7437         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7438
7439         /* Loop filter */
7440         if (vco == 5400000) {
7441                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7442                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7443                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7444                 tribuf_calcntr = 0x9;
7445         } else if (vco <= 6200000) {
7446                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7447                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7448                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449                 tribuf_calcntr = 0x9;
7450         } else if (vco <= 6480000) {
7451                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7452                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7453                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7454                 tribuf_calcntr = 0x8;
7455         } else {
7456                 /* Not supported. Apply the same limits as in the max case */
7457                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7458                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7459                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7460                 tribuf_calcntr = 0;
7461         }
7462         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7463
7464         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7465         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7466         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7467         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7468
7469         /* AFC Recal */
7470         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7471                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7472                         DPIO_AFC_RECAL);
7473
7474         mutex_unlock(&dev_priv->sb_lock);
7475 }
7476
7477 /**
7478  * vlv_force_pll_on - forcibly enable just the PLL
7479  * @dev_priv: i915 private structure
7480  * @pipe: pipe PLL to enable
7481  * @dpll: PLL configuration
7482  *
7483  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7484  * in cases where we need the PLL enabled even when @pipe is not going to
7485  * be enabled.
7486  */
7487 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7488                       const struct dpll *dpll)
7489 {
7490         struct intel_crtc *crtc =
7491                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7492         struct intel_crtc_state pipe_config = {
7493                 .base.crtc = &crtc->base,
7494                 .pixel_multiplier = 1,
7495                 .dpll = *dpll,
7496         };
7497
7498         if (IS_CHERRYVIEW(dev)) {
7499                 chv_compute_dpll(crtc, &pipe_config);
7500                 chv_prepare_pll(crtc, &pipe_config);
7501                 chv_enable_pll(crtc, &pipe_config);
7502         } else {
7503                 vlv_compute_dpll(crtc, &pipe_config);
7504                 vlv_prepare_pll(crtc, &pipe_config);
7505                 vlv_enable_pll(crtc, &pipe_config);
7506         }
7507 }
7508
7509 /**
7510  * vlv_force_pll_off - forcibly disable just the PLL
7511  * @dev_priv: i915 private structure
7512  * @pipe: pipe PLL to disable
7513  *
7514  * Disable the PLL for @pipe. To be used in cases where we need
7515  * the PLL enabled even when @pipe is not going to be enabled.
7516  */
7517 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7518 {
7519         if (IS_CHERRYVIEW(dev))
7520                 chv_disable_pll(to_i915(dev), pipe);
7521         else
7522                 vlv_disable_pll(to_i915(dev), pipe);
7523 }
7524
7525 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7526                               struct intel_crtc_state *crtc_state,
7527                               intel_clock_t *reduced_clock,
7528                               int num_connectors)
7529 {
7530         struct drm_device *dev = crtc->base.dev;
7531         struct drm_i915_private *dev_priv = dev->dev_private;
7532         u32 dpll;
7533         bool is_sdvo;
7534         struct dpll *clock = &crtc_state->dpll;
7535
7536         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7537
7538         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7539                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7540
7541         dpll = DPLL_VGA_MODE_DIS;
7542
7543         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7544                 dpll |= DPLLB_MODE_LVDS;
7545         else
7546                 dpll |= DPLLB_MODE_DAC_SERIAL;
7547
7548         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7549                 dpll |= (crtc_state->pixel_multiplier - 1)
7550                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7551         }
7552
7553         if (is_sdvo)
7554                 dpll |= DPLL_SDVO_HIGH_SPEED;
7555
7556         if (crtc_state->has_dp_encoder)
7557                 dpll |= DPLL_SDVO_HIGH_SPEED;
7558
7559         /* compute bitmask from p1 value */
7560         if (IS_PINEVIEW(dev))
7561                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7562         else {
7563                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564                 if (IS_G4X(dev) && reduced_clock)
7565                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7566         }
7567         switch (clock->p2) {
7568         case 5:
7569                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7570                 break;
7571         case 7:
7572                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7573                 break;
7574         case 10:
7575                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7576                 break;
7577         case 14:
7578                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7579                 break;
7580         }
7581         if (INTEL_INFO(dev)->gen >= 4)
7582                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7583
7584         if (crtc_state->sdvo_tv_clock)
7585                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7586         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7587                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7589         else
7590                 dpll |= PLL_REF_INPUT_DREFCLK;
7591
7592         dpll |= DPLL_VCO_ENABLE;
7593         crtc_state->dpll_hw_state.dpll = dpll;
7594
7595         if (INTEL_INFO(dev)->gen >= 4) {
7596                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7597                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7598                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7599         }
7600 }
7601
7602 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7603                               struct intel_crtc_state *crtc_state,
7604                               intel_clock_t *reduced_clock,
7605                               int num_connectors)
7606 {
7607         struct drm_device *dev = crtc->base.dev;
7608         struct drm_i915_private *dev_priv = dev->dev_private;
7609         u32 dpll;
7610         struct dpll *clock = &crtc_state->dpll;
7611
7612         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7613
7614         dpll = DPLL_VGA_MODE_DIS;
7615
7616         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7617                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7618         } else {
7619                 if (clock->p1 == 2)
7620                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7621                 else
7622                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7623                 if (clock->p2 == 4)
7624                         dpll |= PLL_P2_DIVIDE_BY_4;
7625         }
7626
7627         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7628                 dpll |= DPLL_DVO_2X_MODE;
7629
7630         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7631                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7632                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7633         else
7634                 dpll |= PLL_REF_INPUT_DREFCLK;
7635
7636         dpll |= DPLL_VCO_ENABLE;
7637         crtc_state->dpll_hw_state.dpll = dpll;
7638 }
7639
7640 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7641 {
7642         struct drm_device *dev = intel_crtc->base.dev;
7643         struct drm_i915_private *dev_priv = dev->dev_private;
7644         enum pipe pipe = intel_crtc->pipe;
7645         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7646         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7647         uint32_t crtc_vtotal, crtc_vblank_end;
7648         int vsyncshift = 0;
7649
7650         /* We need to be careful not to changed the adjusted mode, for otherwise
7651          * the hw state checker will get angry at the mismatch. */
7652         crtc_vtotal = adjusted_mode->crtc_vtotal;
7653         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7654
7655         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7656                 /* the chip adds 2 halflines automatically */
7657                 crtc_vtotal -= 1;
7658                 crtc_vblank_end -= 1;
7659
7660                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7661                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7662                 else
7663                         vsyncshift = adjusted_mode->crtc_hsync_start -
7664                                 adjusted_mode->crtc_htotal / 2;
7665                 if (vsyncshift < 0)
7666                         vsyncshift += adjusted_mode->crtc_htotal;
7667         }
7668
7669         if (INTEL_INFO(dev)->gen > 3)
7670                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7671
7672         I915_WRITE(HTOTAL(cpu_transcoder),
7673                    (adjusted_mode->crtc_hdisplay - 1) |
7674                    ((adjusted_mode->crtc_htotal - 1) << 16));
7675         I915_WRITE(HBLANK(cpu_transcoder),
7676                    (adjusted_mode->crtc_hblank_start - 1) |
7677                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7678         I915_WRITE(HSYNC(cpu_transcoder),
7679                    (adjusted_mode->crtc_hsync_start - 1) |
7680                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7681
7682         I915_WRITE(VTOTAL(cpu_transcoder),
7683                    (adjusted_mode->crtc_vdisplay - 1) |
7684                    ((crtc_vtotal - 1) << 16));
7685         I915_WRITE(VBLANK(cpu_transcoder),
7686                    (adjusted_mode->crtc_vblank_start - 1) |
7687                    ((crtc_vblank_end - 1) << 16));
7688         I915_WRITE(VSYNC(cpu_transcoder),
7689                    (adjusted_mode->crtc_vsync_start - 1) |
7690                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7691
7692         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7693          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7694          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7695          * bits. */
7696         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7697             (pipe == PIPE_B || pipe == PIPE_C))
7698                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7699
7700         /* pipesrc controls the size that is scaled from, which should
7701          * always be the user's requested size.
7702          */
7703         I915_WRITE(PIPESRC(pipe),
7704                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7705                    (intel_crtc->config->pipe_src_h - 1));
7706 }
7707
7708 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7709                                    struct intel_crtc_state *pipe_config)
7710 {
7711         struct drm_device *dev = crtc->base.dev;
7712         struct drm_i915_private *dev_priv = dev->dev_private;
7713         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7714         uint32_t tmp;
7715
7716         tmp = I915_READ(HTOTAL(cpu_transcoder));
7717         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7718         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7719         tmp = I915_READ(HBLANK(cpu_transcoder));
7720         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7721         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7722         tmp = I915_READ(HSYNC(cpu_transcoder));
7723         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7724         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7725
7726         tmp = I915_READ(VTOTAL(cpu_transcoder));
7727         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7728         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7729         tmp = I915_READ(VBLANK(cpu_transcoder));
7730         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7731         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7732         tmp = I915_READ(VSYNC(cpu_transcoder));
7733         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7734         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7735
7736         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7737                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7738                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7739                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7740         }
7741
7742         tmp = I915_READ(PIPESRC(crtc->pipe));
7743         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7744         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7745
7746         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7747         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7748 }
7749
7750 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7751                                  struct intel_crtc_state *pipe_config)
7752 {
7753         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7754         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7755         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7756         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7757
7758         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7759         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7760         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7761         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7762
7763         mode->flags = pipe_config->base.adjusted_mode.flags;
7764         mode->type = DRM_MODE_TYPE_DRIVER;
7765
7766         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7767         mode->flags |= pipe_config->base.adjusted_mode.flags;
7768
7769         mode->hsync = drm_mode_hsync(mode);
7770         mode->vrefresh = drm_mode_vrefresh(mode);
7771         drm_mode_set_name(mode);
7772 }
7773
7774 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7775 {
7776         struct drm_device *dev = intel_crtc->base.dev;
7777         struct drm_i915_private *dev_priv = dev->dev_private;
7778         uint32_t pipeconf;
7779
7780         pipeconf = 0;
7781
7782         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7783             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7784                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7785
7786         if (intel_crtc->config->double_wide)
7787                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7788
7789         /* only g4x and later have fancy bpc/dither controls */
7790         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7791                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7792                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7793                         pipeconf |= PIPECONF_DITHER_EN |
7794                                     PIPECONF_DITHER_TYPE_SP;
7795
7796                 switch (intel_crtc->config->pipe_bpp) {
7797                 case 18:
7798                         pipeconf |= PIPECONF_6BPC;
7799                         break;
7800                 case 24:
7801                         pipeconf |= PIPECONF_8BPC;
7802                         break;
7803                 case 30:
7804                         pipeconf |= PIPECONF_10BPC;
7805                         break;
7806                 default:
7807                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7808                         BUG();
7809                 }
7810         }
7811
7812         if (HAS_PIPE_CXSR(dev)) {
7813                 if (intel_crtc->lowfreq_avail) {
7814                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7815                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7816                 } else {
7817                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7818                 }
7819         }
7820
7821         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7822                 if (INTEL_INFO(dev)->gen < 4 ||
7823                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7824                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7825                 else
7826                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7827         } else
7828                 pipeconf |= PIPECONF_PROGRESSIVE;
7829
7830         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7831                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7832
7833         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7834         POSTING_READ(PIPECONF(intel_crtc->pipe));
7835 }
7836
7837 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7838                                    struct intel_crtc_state *crtc_state)
7839 {
7840         struct drm_device *dev = crtc->base.dev;
7841         struct drm_i915_private *dev_priv = dev->dev_private;
7842         int refclk, num_connectors = 0;
7843         intel_clock_t clock;
7844         bool ok;
7845         bool is_dsi = false;
7846         struct intel_encoder *encoder;
7847         const intel_limit_t *limit;
7848         struct drm_atomic_state *state = crtc_state->base.state;
7849         struct drm_connector *connector;
7850         struct drm_connector_state *connector_state;
7851         int i;
7852
7853         memset(&crtc_state->dpll_hw_state, 0,
7854                sizeof(crtc_state->dpll_hw_state));
7855
7856         for_each_connector_in_state(state, connector, connector_state, i) {
7857                 if (connector_state->crtc != &crtc->base)
7858                         continue;
7859
7860                 encoder = to_intel_encoder(connector_state->best_encoder);
7861
7862                 switch (encoder->type) {
7863                 case INTEL_OUTPUT_DSI:
7864                         is_dsi = true;
7865                         break;
7866                 default:
7867                         break;
7868                 }
7869
7870                 num_connectors++;
7871         }
7872
7873         if (is_dsi)
7874                 return 0;
7875
7876         if (!crtc_state->clock_set) {
7877                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7878
7879                 /*
7880                  * Returns a set of divisors for the desired target clock with
7881                  * the given refclk, or FALSE.  The returned values represent
7882                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7883                  * 2) / p1 / p2.
7884                  */
7885                 limit = intel_limit(crtc_state, refclk);
7886                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7887                                                  crtc_state->port_clock,
7888                                                  refclk, NULL, &clock);
7889                 if (!ok) {
7890                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7891                         return -EINVAL;
7892                 }
7893
7894                 /* Compat-code for transition, will disappear. */
7895                 crtc_state->dpll.n = clock.n;
7896                 crtc_state->dpll.m1 = clock.m1;
7897                 crtc_state->dpll.m2 = clock.m2;
7898                 crtc_state->dpll.p1 = clock.p1;
7899                 crtc_state->dpll.p2 = clock.p2;
7900         }
7901
7902         if (IS_GEN2(dev)) {
7903                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7904                                   num_connectors);
7905         } else if (IS_CHERRYVIEW(dev)) {
7906                 chv_compute_dpll(crtc, crtc_state);
7907         } else if (IS_VALLEYVIEW(dev)) {
7908                 vlv_compute_dpll(crtc, crtc_state);
7909         } else {
7910                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7911                                   num_connectors);
7912         }
7913
7914         return 0;
7915 }
7916
7917 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7918                                  struct intel_crtc_state *pipe_config)
7919 {
7920         struct drm_device *dev = crtc->base.dev;
7921         struct drm_i915_private *dev_priv = dev->dev_private;
7922         uint32_t tmp;
7923
7924         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7925                 return;
7926
7927         tmp = I915_READ(PFIT_CONTROL);
7928         if (!(tmp & PFIT_ENABLE))
7929                 return;
7930
7931         /* Check whether the pfit is attached to our pipe. */
7932         if (INTEL_INFO(dev)->gen < 4) {
7933                 if (crtc->pipe != PIPE_B)
7934                         return;
7935         } else {
7936                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7937                         return;
7938         }
7939
7940         pipe_config->gmch_pfit.control = tmp;
7941         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7942         if (INTEL_INFO(dev)->gen < 5)
7943                 pipe_config->gmch_pfit.lvds_border_bits =
7944                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7945 }
7946
7947 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7948                                struct intel_crtc_state *pipe_config)
7949 {
7950         struct drm_device *dev = crtc->base.dev;
7951         struct drm_i915_private *dev_priv = dev->dev_private;
7952         int pipe = pipe_config->cpu_transcoder;
7953         intel_clock_t clock;
7954         u32 mdiv;
7955         int refclk = 100000;
7956
7957         /* In case of MIPI DPLL will not even be used */
7958         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7959                 return;
7960
7961         mutex_lock(&dev_priv->sb_lock);
7962         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7963         mutex_unlock(&dev_priv->sb_lock);
7964
7965         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7966         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7967         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7968         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7969         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7970
7971         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7972 }
7973
7974 static void
7975 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7976                               struct intel_initial_plane_config *plane_config)
7977 {
7978         struct drm_device *dev = crtc->base.dev;
7979         struct drm_i915_private *dev_priv = dev->dev_private;
7980         u32 val, base, offset;
7981         int pipe = crtc->pipe, plane = crtc->plane;
7982         int fourcc, pixel_format;
7983         unsigned int aligned_height;
7984         struct drm_framebuffer *fb;
7985         struct intel_framebuffer *intel_fb;
7986
7987         val = I915_READ(DSPCNTR(plane));
7988         if (!(val & DISPLAY_PLANE_ENABLE))
7989                 return;
7990
7991         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7992         if (!intel_fb) {
7993                 DRM_DEBUG_KMS("failed to alloc fb\n");
7994                 return;
7995         }
7996
7997         fb = &intel_fb->base;
7998
7999         if (INTEL_INFO(dev)->gen >= 4) {
8000                 if (val & DISPPLANE_TILED) {
8001                         plane_config->tiling = I915_TILING_X;
8002                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8003                 }
8004         }
8005
8006         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8007         fourcc = i9xx_format_to_fourcc(pixel_format);
8008         fb->pixel_format = fourcc;
8009         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8010
8011         if (INTEL_INFO(dev)->gen >= 4) {
8012                 if (plane_config->tiling)
8013                         offset = I915_READ(DSPTILEOFF(plane));
8014                 else
8015                         offset = I915_READ(DSPLINOFF(plane));
8016                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8017         } else {
8018                 base = I915_READ(DSPADDR(plane));
8019         }
8020         plane_config->base = base;
8021
8022         val = I915_READ(PIPESRC(pipe));
8023         fb->width = ((val >> 16) & 0xfff) + 1;
8024         fb->height = ((val >> 0) & 0xfff) + 1;
8025
8026         val = I915_READ(DSPSTRIDE(pipe));
8027         fb->pitches[0] = val & 0xffffffc0;
8028
8029         aligned_height = intel_fb_align_height(dev, fb->height,
8030                                                fb->pixel_format,
8031                                                fb->modifier[0]);
8032
8033         plane_config->size = fb->pitches[0] * aligned_height;
8034
8035         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8036                       pipe_name(pipe), plane, fb->width, fb->height,
8037                       fb->bits_per_pixel, base, fb->pitches[0],
8038                       plane_config->size);
8039
8040         plane_config->fb = intel_fb;
8041 }
8042
8043 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8044                                struct intel_crtc_state *pipe_config)
8045 {
8046         struct drm_device *dev = crtc->base.dev;
8047         struct drm_i915_private *dev_priv = dev->dev_private;
8048         int pipe = pipe_config->cpu_transcoder;
8049         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8050         intel_clock_t clock;
8051         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8052         int refclk = 100000;
8053
8054         mutex_lock(&dev_priv->sb_lock);
8055         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8056         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8057         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8058         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8059         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8060         mutex_unlock(&dev_priv->sb_lock);
8061
8062         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8063         clock.m2 = (pll_dw0 & 0xff) << 22;
8064         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8065                 clock.m2 |= pll_dw2 & 0x3fffff;
8066         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8067         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8068         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8069
8070         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8071 }
8072
8073 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8074                                  struct intel_crtc_state *pipe_config)
8075 {
8076         struct drm_device *dev = crtc->base.dev;
8077         struct drm_i915_private *dev_priv = dev->dev_private;
8078         uint32_t tmp;
8079
8080         if (!intel_display_power_is_enabled(dev_priv,
8081                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8082                 return false;
8083
8084         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8085         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8086
8087         tmp = I915_READ(PIPECONF(crtc->pipe));
8088         if (!(tmp & PIPECONF_ENABLE))
8089                 return false;
8090
8091         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8092                 switch (tmp & PIPECONF_BPC_MASK) {
8093                 case PIPECONF_6BPC:
8094                         pipe_config->pipe_bpp = 18;
8095                         break;
8096                 case PIPECONF_8BPC:
8097                         pipe_config->pipe_bpp = 24;
8098                         break;
8099                 case PIPECONF_10BPC:
8100                         pipe_config->pipe_bpp = 30;
8101                         break;
8102                 default:
8103                         break;
8104                 }
8105         }
8106
8107         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8108                 pipe_config->limited_color_range = true;
8109
8110         if (INTEL_INFO(dev)->gen < 4)
8111                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8112
8113         intel_get_pipe_timings(crtc, pipe_config);
8114
8115         i9xx_get_pfit_config(crtc, pipe_config);
8116
8117         if (INTEL_INFO(dev)->gen >= 4) {
8118                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8119                 pipe_config->pixel_multiplier =
8120                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8121                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8122                 pipe_config->dpll_hw_state.dpll_md = tmp;
8123         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8124                 tmp = I915_READ(DPLL(crtc->pipe));
8125                 pipe_config->pixel_multiplier =
8126                         ((tmp & SDVO_MULTIPLIER_MASK)
8127                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8128         } else {
8129                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8130                  * port and will be fixed up in the encoder->get_config
8131                  * function. */
8132                 pipe_config->pixel_multiplier = 1;
8133         }
8134         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8135         if (!IS_VALLEYVIEW(dev)) {
8136                 /*
8137                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8138                  * on 830. Filter it out here so that we don't
8139                  * report errors due to that.
8140                  */
8141                 if (IS_I830(dev))
8142                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8143
8144                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8145                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8146         } else {
8147                 /* Mask out read-only status bits. */
8148                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8149                                                      DPLL_PORTC_READY_MASK |
8150                                                      DPLL_PORTB_READY_MASK);
8151         }
8152
8153         if (IS_CHERRYVIEW(dev))
8154                 chv_crtc_clock_get(crtc, pipe_config);
8155         else if (IS_VALLEYVIEW(dev))
8156                 vlv_crtc_clock_get(crtc, pipe_config);
8157         else
8158                 i9xx_crtc_clock_get(crtc, pipe_config);
8159
8160         /*
8161          * Normally the dotclock is filled in by the encoder .get_config()
8162          * but in case the pipe is enabled w/o any ports we need a sane
8163          * default.
8164          */
8165         pipe_config->base.adjusted_mode.crtc_clock =
8166                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8167
8168         return true;
8169 }
8170
8171 static void ironlake_init_pch_refclk(struct drm_device *dev)
8172 {
8173         struct drm_i915_private *dev_priv = dev->dev_private;
8174         struct intel_encoder *encoder;
8175         u32 val, final;
8176         bool has_lvds = false;
8177         bool has_cpu_edp = false;
8178         bool has_panel = false;
8179         bool has_ck505 = false;
8180         bool can_ssc = false;
8181
8182         /* We need to take the global config into account */
8183         for_each_intel_encoder(dev, encoder) {
8184                 switch (encoder->type) {
8185                 case INTEL_OUTPUT_LVDS:
8186                         has_panel = true;
8187                         has_lvds = true;
8188                         break;
8189                 case INTEL_OUTPUT_EDP:
8190                         has_panel = true;
8191                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8192                                 has_cpu_edp = true;
8193                         break;
8194                 default:
8195                         break;
8196                 }
8197         }
8198
8199         if (HAS_PCH_IBX(dev)) {
8200                 has_ck505 = dev_priv->vbt.display_clock_mode;
8201                 can_ssc = has_ck505;
8202         } else {
8203                 has_ck505 = false;
8204                 can_ssc = true;
8205         }
8206
8207         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208                       has_panel, has_lvds, has_ck505);
8209
8210         /* Ironlake: try to setup display ref clock before DPLL
8211          * enabling. This is only under driver's control after
8212          * PCH B stepping, previous chipset stepping should be
8213          * ignoring this setting.
8214          */
8215         val = I915_READ(PCH_DREF_CONTROL);
8216
8217         /* As we must carefully and slowly disable/enable each source in turn,
8218          * compute the final state we want first and check if we need to
8219          * make any changes at all.
8220          */
8221         final = val;
8222         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8223         if (has_ck505)
8224                 final |= DREF_NONSPREAD_CK505_ENABLE;
8225         else
8226                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8227
8228         final &= ~DREF_SSC_SOURCE_MASK;
8229         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230         final &= ~DREF_SSC1_ENABLE;
8231
8232         if (has_panel) {
8233                 final |= DREF_SSC_SOURCE_ENABLE;
8234
8235                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236                         final |= DREF_SSC1_ENABLE;
8237
8238                 if (has_cpu_edp) {
8239                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8241                         else
8242                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8243                 } else
8244                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8245         } else {
8246                 final |= DREF_SSC_SOURCE_DISABLE;
8247                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248         }
8249
8250         if (final == val)
8251                 return;
8252
8253         /* Always enable nonspread source */
8254         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8255
8256         if (has_ck505)
8257                 val |= DREF_NONSPREAD_CK505_ENABLE;
8258         else
8259                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8260
8261         if (has_panel) {
8262                 val &= ~DREF_SSC_SOURCE_MASK;
8263                 val |= DREF_SSC_SOURCE_ENABLE;
8264
8265                 /* SSC must be turned on before enabling the CPU output  */
8266                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8267                         DRM_DEBUG_KMS("Using SSC on panel\n");
8268                         val |= DREF_SSC1_ENABLE;
8269                 } else
8270                         val &= ~DREF_SSC1_ENABLE;
8271
8272                 /* Get SSC going before enabling the outputs */
8273                 I915_WRITE(PCH_DREF_CONTROL, val);
8274                 POSTING_READ(PCH_DREF_CONTROL);
8275                 udelay(200);
8276
8277                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8278
8279                 /* Enable CPU source on CPU attached eDP */
8280                 if (has_cpu_edp) {
8281                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8282                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8283                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8284                         } else
8285                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8286                 } else
8287                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288
8289                 I915_WRITE(PCH_DREF_CONTROL, val);
8290                 POSTING_READ(PCH_DREF_CONTROL);
8291                 udelay(200);
8292         } else {
8293                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8294
8295                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8296
8297                 /* Turn off CPU output */
8298                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8299
8300                 I915_WRITE(PCH_DREF_CONTROL, val);
8301                 POSTING_READ(PCH_DREF_CONTROL);
8302                 udelay(200);
8303
8304                 /* Turn off the SSC source */
8305                 val &= ~DREF_SSC_SOURCE_MASK;
8306                 val |= DREF_SSC_SOURCE_DISABLE;
8307
8308                 /* Turn off SSC1 */
8309                 val &= ~DREF_SSC1_ENABLE;
8310
8311                 I915_WRITE(PCH_DREF_CONTROL, val);
8312                 POSTING_READ(PCH_DREF_CONTROL);
8313                 udelay(200);
8314         }
8315
8316         BUG_ON(val != final);
8317 }
8318
8319 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8320 {
8321         uint32_t tmp;
8322
8323         tmp = I915_READ(SOUTH_CHICKEN2);
8324         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325         I915_WRITE(SOUTH_CHICKEN2, tmp);
8326
8327         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8330
8331         tmp = I915_READ(SOUTH_CHICKEN2);
8332         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333         I915_WRITE(SOUTH_CHICKEN2, tmp);
8334
8335         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8338 }
8339
8340 /* WaMPhyProgramming:hsw */
8341 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8342 {
8343         uint32_t tmp;
8344
8345         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346         tmp &= ~(0xFF << 24);
8347         tmp |= (0x12 << 24);
8348         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8349
8350         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8351         tmp |= (1 << 11);
8352         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8355         tmp |= (1 << 11);
8356         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8357
8358         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8367         tmp &= ~(7 << 13);
8368         tmp |= (5 << 13);
8369         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8370
8371         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8372         tmp &= ~(7 << 13);
8373         tmp |= (5 << 13);
8374         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8375
8376         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8377         tmp &= ~0xFF;
8378         tmp |= 0x1C;
8379         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8380
8381         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8382         tmp &= ~0xFF;
8383         tmp |= 0x1C;
8384         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8385
8386         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387         tmp &= ~(0xFF << 16);
8388         tmp |= (0x1C << 16);
8389         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8390
8391         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392         tmp &= ~(0xFF << 16);
8393         tmp |= (0x1C << 16);
8394         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8395
8396         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8397         tmp |= (1 << 27);
8398         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8399
8400         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8401         tmp |= (1 << 27);
8402         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8403
8404         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405         tmp &= ~(0xF << 28);
8406         tmp |= (4 << 28);
8407         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8408
8409         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410         tmp &= ~(0xF << 28);
8411         tmp |= (4 << 28);
8412         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8413 }
8414
8415 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8416  * Programming" based on the parameters passed:
8417  * - Sequence to enable CLKOUT_DP
8418  * - Sequence to enable CLKOUT_DP without spread
8419  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8420  */
8421 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8422                                  bool with_fdi)
8423 {
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425         uint32_t reg, tmp;
8426
8427         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8428                 with_spread = true;
8429         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8430                 with_fdi = false;
8431
8432         mutex_lock(&dev_priv->sb_lock);
8433
8434         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8435         tmp &= ~SBI_SSCCTL_DISABLE;
8436         tmp |= SBI_SSCCTL_PATHALT;
8437         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438
8439         udelay(24);
8440
8441         if (with_spread) {
8442                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8443                 tmp &= ~SBI_SSCCTL_PATHALT;
8444                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8445
8446                 if (with_fdi) {
8447                         lpt_reset_fdi_mphy(dev_priv);
8448                         lpt_program_fdi_mphy(dev_priv);
8449                 }
8450         }
8451
8452         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8453         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8454         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8455         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8456
8457         mutex_unlock(&dev_priv->sb_lock);
8458 }
8459
8460 /* Sequence to disable CLKOUT_DP */
8461 static void lpt_disable_clkout_dp(struct drm_device *dev)
8462 {
8463         struct drm_i915_private *dev_priv = dev->dev_private;
8464         uint32_t reg, tmp;
8465
8466         mutex_lock(&dev_priv->sb_lock);
8467
8468         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8469         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8470         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8471         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8472
8473         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8475                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8476                         tmp |= SBI_SSCCTL_PATHALT;
8477                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8478                         udelay(32);
8479                 }
8480                 tmp |= SBI_SSCCTL_DISABLE;
8481                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8482         }
8483
8484         mutex_unlock(&dev_priv->sb_lock);
8485 }
8486
8487 static void lpt_init_pch_refclk(struct drm_device *dev)
8488 {
8489         struct intel_encoder *encoder;
8490         bool has_vga = false;
8491
8492         for_each_intel_encoder(dev, encoder) {
8493                 switch (encoder->type) {
8494                 case INTEL_OUTPUT_ANALOG:
8495                         has_vga = true;
8496                         break;
8497                 default:
8498                         break;
8499                 }
8500         }
8501
8502         if (has_vga)
8503                 lpt_enable_clkout_dp(dev, true, true);
8504         else
8505                 lpt_disable_clkout_dp(dev);
8506 }
8507
8508 /*
8509  * Initialize reference clocks when the driver loads
8510  */
8511 void intel_init_pch_refclk(struct drm_device *dev)
8512 {
8513         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8514                 ironlake_init_pch_refclk(dev);
8515         else if (HAS_PCH_LPT(dev))
8516                 lpt_init_pch_refclk(dev);
8517 }
8518
8519 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8520 {
8521         struct drm_device *dev = crtc_state->base.crtc->dev;
8522         struct drm_i915_private *dev_priv = dev->dev_private;
8523         struct drm_atomic_state *state = crtc_state->base.state;
8524         struct drm_connector *connector;
8525         struct drm_connector_state *connector_state;
8526         struct intel_encoder *encoder;
8527         int num_connectors = 0, i;
8528         bool is_lvds = false;
8529
8530         for_each_connector_in_state(state, connector, connector_state, i) {
8531                 if (connector_state->crtc != crtc_state->base.crtc)
8532                         continue;
8533
8534                 encoder = to_intel_encoder(connector_state->best_encoder);
8535
8536                 switch (encoder->type) {
8537                 case INTEL_OUTPUT_LVDS:
8538                         is_lvds = true;
8539                         break;
8540                 default:
8541                         break;
8542                 }
8543                 num_connectors++;
8544         }
8545
8546         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8547                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8548                               dev_priv->vbt.lvds_ssc_freq);
8549                 return dev_priv->vbt.lvds_ssc_freq;
8550         }
8551
8552         return 120000;
8553 }
8554
8555 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8556 {
8557         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8559         int pipe = intel_crtc->pipe;
8560         uint32_t val;
8561
8562         val = 0;
8563
8564         switch (intel_crtc->config->pipe_bpp) {
8565         case 18:
8566                 val |= PIPECONF_6BPC;
8567                 break;
8568         case 24:
8569                 val |= PIPECONF_8BPC;
8570                 break;
8571         case 30:
8572                 val |= PIPECONF_10BPC;
8573                 break;
8574         case 36:
8575                 val |= PIPECONF_12BPC;
8576                 break;
8577         default:
8578                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8579                 BUG();
8580         }
8581
8582         if (intel_crtc->config->dither)
8583                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8584
8585         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8586                 val |= PIPECONF_INTERLACED_ILK;
8587         else
8588                 val |= PIPECONF_PROGRESSIVE;
8589
8590         if (intel_crtc->config->limited_color_range)
8591                 val |= PIPECONF_COLOR_RANGE_SELECT;
8592
8593         I915_WRITE(PIPECONF(pipe), val);
8594         POSTING_READ(PIPECONF(pipe));
8595 }
8596
8597 /*
8598  * Set up the pipe CSC unit.
8599  *
8600  * Currently only full range RGB to limited range RGB conversion
8601  * is supported, but eventually this should handle various
8602  * RGB<->YCbCr scenarios as well.
8603  */
8604 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8605 {
8606         struct drm_device *dev = crtc->dev;
8607         struct drm_i915_private *dev_priv = dev->dev_private;
8608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609         int pipe = intel_crtc->pipe;
8610         uint16_t coeff = 0x7800; /* 1.0 */
8611
8612         /*
8613          * TODO: Check what kind of values actually come out of the pipe
8614          * with these coeff/postoff values and adjust to get the best
8615          * accuracy. Perhaps we even need to take the bpc value into
8616          * consideration.
8617          */
8618
8619         if (intel_crtc->config->limited_color_range)
8620                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8621
8622         /*
8623          * GY/GU and RY/RU should be the other way around according
8624          * to BSpec, but reality doesn't agree. Just set them up in
8625          * a way that results in the correct picture.
8626          */
8627         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8628         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8629
8630         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8631         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8632
8633         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8634         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8635
8636         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8637         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8638         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8639
8640         if (INTEL_INFO(dev)->gen > 6) {
8641                 uint16_t postoff = 0;
8642
8643                 if (intel_crtc->config->limited_color_range)
8644                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8645
8646                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8647                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8648                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8649
8650                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8651         } else {
8652                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8653
8654                 if (intel_crtc->config->limited_color_range)
8655                         mode |= CSC_BLACK_SCREEN_OFFSET;
8656
8657                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8658         }
8659 }
8660
8661 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8662 {
8663         struct drm_device *dev = crtc->dev;
8664         struct drm_i915_private *dev_priv = dev->dev_private;
8665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666         enum pipe pipe = intel_crtc->pipe;
8667         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8668         uint32_t val;
8669
8670         val = 0;
8671
8672         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8673                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8674
8675         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8676                 val |= PIPECONF_INTERLACED_ILK;
8677         else
8678                 val |= PIPECONF_PROGRESSIVE;
8679
8680         I915_WRITE(PIPECONF(cpu_transcoder), val);
8681         POSTING_READ(PIPECONF(cpu_transcoder));
8682
8683         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8684         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8685
8686         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8687                 val = 0;
8688
8689                 switch (intel_crtc->config->pipe_bpp) {
8690                 case 18:
8691                         val |= PIPEMISC_DITHER_6_BPC;
8692                         break;
8693                 case 24:
8694                         val |= PIPEMISC_DITHER_8_BPC;
8695                         break;
8696                 case 30:
8697                         val |= PIPEMISC_DITHER_10_BPC;
8698                         break;
8699                 case 36:
8700                         val |= PIPEMISC_DITHER_12_BPC;
8701                         break;
8702                 default:
8703                         /* Case prevented by pipe_config_set_bpp. */
8704                         BUG();
8705                 }
8706
8707                 if (intel_crtc->config->dither)
8708                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8709
8710                 I915_WRITE(PIPEMISC(pipe), val);
8711         }
8712 }
8713
8714 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8715                                     struct intel_crtc_state *crtc_state,
8716                                     intel_clock_t *clock,
8717                                     bool *has_reduced_clock,
8718                                     intel_clock_t *reduced_clock)
8719 {
8720         struct drm_device *dev = crtc->dev;
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         int refclk;
8723         const intel_limit_t *limit;
8724         bool ret;
8725
8726         refclk = ironlake_get_refclk(crtc_state);
8727
8728         /*
8729          * Returns a set of divisors for the desired target clock with the given
8730          * refclk, or FALSE.  The returned values represent the clock equation:
8731          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8732          */
8733         limit = intel_limit(crtc_state, refclk);
8734         ret = dev_priv->display.find_dpll(limit, crtc_state,
8735                                           crtc_state->port_clock,
8736                                           refclk, NULL, clock);
8737         if (!ret)
8738                 return false;
8739
8740         return true;
8741 }
8742
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8744 {
8745         /*
8746          * Account for spread spectrum to avoid
8747          * oversubscribing the link. Max center spread
8748          * is 2.5%; use 5% for safety's sake.
8749          */
8750         u32 bps = target_clock * bpp * 21 / 20;
8751         return DIV_ROUND_UP(bps, link_bw * 8);
8752 }
8753
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8755 {
8756         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8757 }
8758
8759 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760                                       struct intel_crtc_state *crtc_state,
8761                                       u32 *fp,
8762                                       intel_clock_t *reduced_clock, u32 *fp2)
8763 {
8764         struct drm_crtc *crtc = &intel_crtc->base;
8765         struct drm_device *dev = crtc->dev;
8766         struct drm_i915_private *dev_priv = dev->dev_private;
8767         struct drm_atomic_state *state = crtc_state->base.state;
8768         struct drm_connector *connector;
8769         struct drm_connector_state *connector_state;
8770         struct intel_encoder *encoder;
8771         uint32_t dpll;
8772         int factor, num_connectors = 0, i;
8773         bool is_lvds = false, is_sdvo = false;
8774
8775         for_each_connector_in_state(state, connector, connector_state, i) {
8776                 if (connector_state->crtc != crtc_state->base.crtc)
8777                         continue;
8778
8779                 encoder = to_intel_encoder(connector_state->best_encoder);
8780
8781                 switch (encoder->type) {
8782                 case INTEL_OUTPUT_LVDS:
8783                         is_lvds = true;
8784                         break;
8785                 case INTEL_OUTPUT_SDVO:
8786                 case INTEL_OUTPUT_HDMI:
8787                         is_sdvo = true;
8788                         break;
8789                 default:
8790                         break;
8791                 }
8792
8793                 num_connectors++;
8794         }
8795
8796         /* Enable autotuning of the PLL clock (if permissible) */
8797         factor = 21;
8798         if (is_lvds) {
8799                 if ((intel_panel_use_ssc(dev_priv) &&
8800                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8801                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8802                         factor = 25;
8803         } else if (crtc_state->sdvo_tv_clock)
8804                 factor = 20;
8805
8806         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8807                 *fp |= FP_CB_TUNE;
8808
8809         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8810                 *fp2 |= FP_CB_TUNE;
8811
8812         dpll = 0;
8813
8814         if (is_lvds)
8815                 dpll |= DPLLB_MODE_LVDS;
8816         else
8817                 dpll |= DPLLB_MODE_DAC_SERIAL;
8818
8819         dpll |= (crtc_state->pixel_multiplier - 1)
8820                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8821
8822         if (is_sdvo)
8823                 dpll |= DPLL_SDVO_HIGH_SPEED;
8824         if (crtc_state->has_dp_encoder)
8825                 dpll |= DPLL_SDVO_HIGH_SPEED;
8826
8827         /* compute bitmask from p1 value */
8828         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8829         /* also FPA1 */
8830         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8831
8832         switch (crtc_state->dpll.p2) {
8833         case 5:
8834                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8835                 break;
8836         case 7:
8837                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8838                 break;
8839         case 10:
8840                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8841                 break;
8842         case 14:
8843                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8844                 break;
8845         }
8846
8847         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8848                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8849         else
8850                 dpll |= PLL_REF_INPUT_DREFCLK;
8851
8852         return dpll | DPLL_VCO_ENABLE;
8853 }
8854
8855 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8856                                        struct intel_crtc_state *crtc_state)
8857 {
8858         struct drm_device *dev = crtc->base.dev;
8859         intel_clock_t clock, reduced_clock;
8860         u32 dpll = 0, fp = 0, fp2 = 0;
8861         bool ok, has_reduced_clock = false;
8862         bool is_lvds = false;
8863         struct intel_shared_dpll *pll;
8864
8865         memset(&crtc_state->dpll_hw_state, 0,
8866                sizeof(crtc_state->dpll_hw_state));
8867
8868         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8869
8870         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8871              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8872
8873         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8874                                      &has_reduced_clock, &reduced_clock);
8875         if (!ok && !crtc_state->clock_set) {
8876                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8877                 return -EINVAL;
8878         }
8879         /* Compat-code for transition, will disappear. */
8880         if (!crtc_state->clock_set) {
8881                 crtc_state->dpll.n = clock.n;
8882                 crtc_state->dpll.m1 = clock.m1;
8883                 crtc_state->dpll.m2 = clock.m2;
8884                 crtc_state->dpll.p1 = clock.p1;
8885                 crtc_state->dpll.p2 = clock.p2;
8886         }
8887
8888         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8889         if (crtc_state->has_pch_encoder) {
8890                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8891                 if (has_reduced_clock)
8892                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8893
8894                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8895                                              &fp, &reduced_clock,
8896                                              has_reduced_clock ? &fp2 : NULL);
8897
8898                 crtc_state->dpll_hw_state.dpll = dpll;
8899                 crtc_state->dpll_hw_state.fp0 = fp;
8900                 if (has_reduced_clock)
8901                         crtc_state->dpll_hw_state.fp1 = fp2;
8902                 else
8903                         crtc_state->dpll_hw_state.fp1 = fp;
8904
8905                 pll = intel_get_shared_dpll(crtc, crtc_state);
8906                 if (pll == NULL) {
8907                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8908                                          pipe_name(crtc->pipe));
8909                         return -EINVAL;
8910                 }
8911         }
8912
8913         if (is_lvds && has_reduced_clock)
8914                 crtc->lowfreq_avail = true;
8915         else
8916                 crtc->lowfreq_avail = false;
8917
8918         return 0;
8919 }
8920
8921 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8922                                          struct intel_link_m_n *m_n)
8923 {
8924         struct drm_device *dev = crtc->base.dev;
8925         struct drm_i915_private *dev_priv = dev->dev_private;
8926         enum pipe pipe = crtc->pipe;
8927
8928         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8929         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8930         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8931                 & ~TU_SIZE_MASK;
8932         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8933         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8934                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935 }
8936
8937 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8938                                          enum transcoder transcoder,
8939                                          struct intel_link_m_n *m_n,
8940                                          struct intel_link_m_n *m2_n2)
8941 {
8942         struct drm_device *dev = crtc->base.dev;
8943         struct drm_i915_private *dev_priv = dev->dev_private;
8944         enum pipe pipe = crtc->pipe;
8945
8946         if (INTEL_INFO(dev)->gen >= 5) {
8947                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8948                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8949                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8950                         & ~TU_SIZE_MASK;
8951                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8952                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8953                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8955                  * gen < 8) and if DRRS is supported (to make sure the
8956                  * registers are not unnecessarily read).
8957                  */
8958                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8959                         crtc->config->has_drrs) {
8960                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8961                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8962                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8963                                         & ~TU_SIZE_MASK;
8964                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8965                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8966                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8967                 }
8968         } else {
8969                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8970                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8971                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8972                         & ~TU_SIZE_MASK;
8973                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8974                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8975                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976         }
8977 }
8978
8979 void intel_dp_get_m_n(struct intel_crtc *crtc,
8980                       struct intel_crtc_state *pipe_config)
8981 {
8982         if (pipe_config->has_pch_encoder)
8983                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8984         else
8985                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8986                                              &pipe_config->dp_m_n,
8987                                              &pipe_config->dp_m2_n2);
8988 }
8989
8990 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8991                                         struct intel_crtc_state *pipe_config)
8992 {
8993         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8994                                      &pipe_config->fdi_m_n, NULL);
8995 }
8996
8997 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8998                                     struct intel_crtc_state *pipe_config)
8999 {
9000         struct drm_device *dev = crtc->base.dev;
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9003         uint32_t ps_ctrl = 0;
9004         int id = -1;
9005         int i;
9006
9007         /* find scaler attached to this pipe */
9008         for (i = 0; i < crtc->num_scalers; i++) {
9009                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9010                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9011                         id = i;
9012                         pipe_config->pch_pfit.enabled = true;
9013                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9014                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9015                         break;
9016                 }
9017         }
9018
9019         scaler_state->scaler_id = id;
9020         if (id >= 0) {
9021                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9022         } else {
9023                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9024         }
9025 }
9026
9027 static void
9028 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9029                                  struct intel_initial_plane_config *plane_config)
9030 {
9031         struct drm_device *dev = crtc->base.dev;
9032         struct drm_i915_private *dev_priv = dev->dev_private;
9033         u32 val, base, offset, stride_mult, tiling;
9034         int pipe = crtc->pipe;
9035         int fourcc, pixel_format;
9036         unsigned int aligned_height;
9037         struct drm_framebuffer *fb;
9038         struct intel_framebuffer *intel_fb;
9039
9040         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9041         if (!intel_fb) {
9042                 DRM_DEBUG_KMS("failed to alloc fb\n");
9043                 return;
9044         }
9045
9046         fb = &intel_fb->base;
9047
9048         val = I915_READ(PLANE_CTL(pipe, 0));
9049         if (!(val & PLANE_CTL_ENABLE))
9050                 goto error;
9051
9052         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9053         fourcc = skl_format_to_fourcc(pixel_format,
9054                                       val & PLANE_CTL_ORDER_RGBX,
9055                                       val & PLANE_CTL_ALPHA_MASK);
9056         fb->pixel_format = fourcc;
9057         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9058
9059         tiling = val & PLANE_CTL_TILED_MASK;
9060         switch (tiling) {
9061         case PLANE_CTL_TILED_LINEAR:
9062                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9063                 break;
9064         case PLANE_CTL_TILED_X:
9065                 plane_config->tiling = I915_TILING_X;
9066                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9067                 break;
9068         case PLANE_CTL_TILED_Y:
9069                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9070                 break;
9071         case PLANE_CTL_TILED_YF:
9072                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9073                 break;
9074         default:
9075                 MISSING_CASE(tiling);
9076                 goto error;
9077         }
9078
9079         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9080         plane_config->base = base;
9081
9082         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9083
9084         val = I915_READ(PLANE_SIZE(pipe, 0));
9085         fb->height = ((val >> 16) & 0xfff) + 1;
9086         fb->width = ((val >> 0) & 0x1fff) + 1;
9087
9088         val = I915_READ(PLANE_STRIDE(pipe, 0));
9089         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9090                                                 fb->pixel_format);
9091         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9092
9093         aligned_height = intel_fb_align_height(dev, fb->height,
9094                                                fb->pixel_format,
9095                                                fb->modifier[0]);
9096
9097         plane_config->size = fb->pitches[0] * aligned_height;
9098
9099         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9100                       pipe_name(pipe), fb->width, fb->height,
9101                       fb->bits_per_pixel, base, fb->pitches[0],
9102                       plane_config->size);
9103
9104         plane_config->fb = intel_fb;
9105         return;
9106
9107 error:
9108         kfree(fb);
9109 }
9110
9111 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9112                                      struct intel_crtc_state *pipe_config)
9113 {
9114         struct drm_device *dev = crtc->base.dev;
9115         struct drm_i915_private *dev_priv = dev->dev_private;
9116         uint32_t tmp;
9117
9118         tmp = I915_READ(PF_CTL(crtc->pipe));
9119
9120         if (tmp & PF_ENABLE) {
9121                 pipe_config->pch_pfit.enabled = true;
9122                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9123                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9124
9125                 /* We currently do not free assignements of panel fitters on
9126                  * ivb/hsw (since we don't use the higher upscaling modes which
9127                  * differentiates them) so just WARN about this case for now. */
9128                 if (IS_GEN7(dev)) {
9129                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9130                                 PF_PIPE_SEL_IVB(crtc->pipe));
9131                 }
9132         }
9133 }
9134
9135 static void
9136 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9137                                   struct intel_initial_plane_config *plane_config)
9138 {
9139         struct drm_device *dev = crtc->base.dev;
9140         struct drm_i915_private *dev_priv = dev->dev_private;
9141         u32 val, base, offset;
9142         int pipe = crtc->pipe;
9143         int fourcc, pixel_format;
9144         unsigned int aligned_height;
9145         struct drm_framebuffer *fb;
9146         struct intel_framebuffer *intel_fb;
9147
9148         val = I915_READ(DSPCNTR(pipe));
9149         if (!(val & DISPLAY_PLANE_ENABLE))
9150                 return;
9151
9152         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9153         if (!intel_fb) {
9154                 DRM_DEBUG_KMS("failed to alloc fb\n");
9155                 return;
9156         }
9157
9158         fb = &intel_fb->base;
9159
9160         if (INTEL_INFO(dev)->gen >= 4) {
9161                 if (val & DISPPLANE_TILED) {
9162                         plane_config->tiling = I915_TILING_X;
9163                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9164                 }
9165         }
9166
9167         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9168         fourcc = i9xx_format_to_fourcc(pixel_format);
9169         fb->pixel_format = fourcc;
9170         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9171
9172         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9173         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9174                 offset = I915_READ(DSPOFFSET(pipe));
9175         } else {
9176                 if (plane_config->tiling)
9177                         offset = I915_READ(DSPTILEOFF(pipe));
9178                 else
9179                         offset = I915_READ(DSPLINOFF(pipe));
9180         }
9181         plane_config->base = base;
9182
9183         val = I915_READ(PIPESRC(pipe));
9184         fb->width = ((val >> 16) & 0xfff) + 1;
9185         fb->height = ((val >> 0) & 0xfff) + 1;
9186
9187         val = I915_READ(DSPSTRIDE(pipe));
9188         fb->pitches[0] = val & 0xffffffc0;
9189
9190         aligned_height = intel_fb_align_height(dev, fb->height,
9191                                                fb->pixel_format,
9192                                                fb->modifier[0]);
9193
9194         plane_config->size = fb->pitches[0] * aligned_height;
9195
9196         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9197                       pipe_name(pipe), fb->width, fb->height,
9198                       fb->bits_per_pixel, base, fb->pitches[0],
9199                       plane_config->size);
9200
9201         plane_config->fb = intel_fb;
9202 }
9203
9204 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9205                                      struct intel_crtc_state *pipe_config)
9206 {
9207         struct drm_device *dev = crtc->base.dev;
9208         struct drm_i915_private *dev_priv = dev->dev_private;
9209         uint32_t tmp;
9210
9211         if (!intel_display_power_is_enabled(dev_priv,
9212                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9213                 return false;
9214
9215         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9216         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9217
9218         tmp = I915_READ(PIPECONF(crtc->pipe));
9219         if (!(tmp & PIPECONF_ENABLE))
9220                 return false;
9221
9222         switch (tmp & PIPECONF_BPC_MASK) {
9223         case PIPECONF_6BPC:
9224                 pipe_config->pipe_bpp = 18;
9225                 break;
9226         case PIPECONF_8BPC:
9227                 pipe_config->pipe_bpp = 24;
9228                 break;
9229         case PIPECONF_10BPC:
9230                 pipe_config->pipe_bpp = 30;
9231                 break;
9232         case PIPECONF_12BPC:
9233                 pipe_config->pipe_bpp = 36;
9234                 break;
9235         default:
9236                 break;
9237         }
9238
9239         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9240                 pipe_config->limited_color_range = true;
9241
9242         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9243                 struct intel_shared_dpll *pll;
9244
9245                 pipe_config->has_pch_encoder = true;
9246
9247                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9248                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9249                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9250
9251                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9252
9253                 if (HAS_PCH_IBX(dev_priv->dev)) {
9254                         pipe_config->shared_dpll =
9255                                 (enum intel_dpll_id) crtc->pipe;
9256                 } else {
9257                         tmp = I915_READ(PCH_DPLL_SEL);
9258                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9259                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9260                         else
9261                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9262                 }
9263
9264                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9265
9266                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9267                                            &pipe_config->dpll_hw_state));
9268
9269                 tmp = pipe_config->dpll_hw_state.dpll;
9270                 pipe_config->pixel_multiplier =
9271                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9272                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9273
9274                 ironlake_pch_clock_get(crtc, pipe_config);
9275         } else {
9276                 pipe_config->pixel_multiplier = 1;
9277         }
9278
9279         intel_get_pipe_timings(crtc, pipe_config);
9280
9281         ironlake_get_pfit_config(crtc, pipe_config);
9282
9283         return true;
9284 }
9285
9286 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9287 {
9288         struct drm_device *dev = dev_priv->dev;
9289         struct intel_crtc *crtc;
9290
9291         for_each_intel_crtc(dev, crtc)
9292                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9293                      pipe_name(crtc->pipe));
9294
9295         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9296         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9297         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9298         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9299         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9300         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9301              "CPU PWM1 enabled\n");
9302         if (IS_HASWELL(dev))
9303                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9304                      "CPU PWM2 enabled\n");
9305         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9306              "PCH PWM1 enabled\n");
9307         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9308              "Utility pin enabled\n");
9309         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9310
9311         /*
9312          * In theory we can still leave IRQs enabled, as long as only the HPD
9313          * interrupts remain enabled. We used to check for that, but since it's
9314          * gen-specific and since we only disable LCPLL after we fully disable
9315          * the interrupts, the check below should be enough.
9316          */
9317         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9318 }
9319
9320 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9321 {
9322         struct drm_device *dev = dev_priv->dev;
9323
9324         if (IS_HASWELL(dev))
9325                 return I915_READ(D_COMP_HSW);
9326         else
9327                 return I915_READ(D_COMP_BDW);
9328 }
9329
9330 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9331 {
9332         struct drm_device *dev = dev_priv->dev;
9333
9334         if (IS_HASWELL(dev)) {
9335                 mutex_lock(&dev_priv->rps.hw_lock);
9336                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9337                                             val))
9338                         DRM_ERROR("Failed to write to D_COMP\n");
9339                 mutex_unlock(&dev_priv->rps.hw_lock);
9340         } else {
9341                 I915_WRITE(D_COMP_BDW, val);
9342                 POSTING_READ(D_COMP_BDW);
9343         }
9344 }
9345
9346 /*
9347  * This function implements pieces of two sequences from BSpec:
9348  * - Sequence for display software to disable LCPLL
9349  * - Sequence for display software to allow package C8+
9350  * The steps implemented here are just the steps that actually touch the LCPLL
9351  * register. Callers should take care of disabling all the display engine
9352  * functions, doing the mode unset, fixing interrupts, etc.
9353  */
9354 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9355                               bool switch_to_fclk, bool allow_power_down)
9356 {
9357         uint32_t val;
9358
9359         assert_can_disable_lcpll(dev_priv);
9360
9361         val = I915_READ(LCPLL_CTL);
9362
9363         if (switch_to_fclk) {
9364                 val |= LCPLL_CD_SOURCE_FCLK;
9365                 I915_WRITE(LCPLL_CTL, val);
9366
9367                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9368                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9369                         DRM_ERROR("Switching to FCLK failed\n");
9370
9371                 val = I915_READ(LCPLL_CTL);
9372         }
9373
9374         val |= LCPLL_PLL_DISABLE;
9375         I915_WRITE(LCPLL_CTL, val);
9376         POSTING_READ(LCPLL_CTL);
9377
9378         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9379                 DRM_ERROR("LCPLL still locked\n");
9380
9381         val = hsw_read_dcomp(dev_priv);
9382         val |= D_COMP_COMP_DISABLE;
9383         hsw_write_dcomp(dev_priv, val);
9384         ndelay(100);
9385
9386         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9387                      1))
9388                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9389
9390         if (allow_power_down) {
9391                 val = I915_READ(LCPLL_CTL);
9392                 val |= LCPLL_POWER_DOWN_ALLOW;
9393                 I915_WRITE(LCPLL_CTL, val);
9394                 POSTING_READ(LCPLL_CTL);
9395         }
9396 }
9397
9398 /*
9399  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9400  * source.
9401  */
9402 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9403 {
9404         uint32_t val;
9405
9406         val = I915_READ(LCPLL_CTL);
9407
9408         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9409                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9410                 return;
9411
9412         /*
9413          * Make sure we're not on PC8 state before disabling PC8, otherwise
9414          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9415          */
9416         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9417
9418         if (val & LCPLL_POWER_DOWN_ALLOW) {
9419                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9420                 I915_WRITE(LCPLL_CTL, val);
9421                 POSTING_READ(LCPLL_CTL);
9422         }
9423
9424         val = hsw_read_dcomp(dev_priv);
9425         val |= D_COMP_COMP_FORCE;
9426         val &= ~D_COMP_COMP_DISABLE;
9427         hsw_write_dcomp(dev_priv, val);
9428
9429         val = I915_READ(LCPLL_CTL);
9430         val &= ~LCPLL_PLL_DISABLE;
9431         I915_WRITE(LCPLL_CTL, val);
9432
9433         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9434                 DRM_ERROR("LCPLL not locked yet\n");
9435
9436         if (val & LCPLL_CD_SOURCE_FCLK) {
9437                 val = I915_READ(LCPLL_CTL);
9438                 val &= ~LCPLL_CD_SOURCE_FCLK;
9439                 I915_WRITE(LCPLL_CTL, val);
9440
9441                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9442                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9443                         DRM_ERROR("Switching back to LCPLL failed\n");
9444         }
9445
9446         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9447         intel_update_cdclk(dev_priv->dev);
9448 }
9449
9450 /*
9451  * Package states C8 and deeper are really deep PC states that can only be
9452  * reached when all the devices on the system allow it, so even if the graphics
9453  * device allows PC8+, it doesn't mean the system will actually get to these
9454  * states. Our driver only allows PC8+ when going into runtime PM.
9455  *
9456  * The requirements for PC8+ are that all the outputs are disabled, the power
9457  * well is disabled and most interrupts are disabled, and these are also
9458  * requirements for runtime PM. When these conditions are met, we manually do
9459  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9460  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9461  * hang the machine.
9462  *
9463  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9464  * the state of some registers, so when we come back from PC8+ we need to
9465  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9466  * need to take care of the registers kept by RC6. Notice that this happens even
9467  * if we don't put the device in PCI D3 state (which is what currently happens
9468  * because of the runtime PM support).
9469  *
9470  * For more, read "Display Sequences for Package C8" on the hardware
9471  * documentation.
9472  */
9473 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9474 {
9475         struct drm_device *dev = dev_priv->dev;
9476         uint32_t val;
9477
9478         DRM_DEBUG_KMS("Enabling package C8+\n");
9479
9480         if (HAS_PCH_LPT_LP(dev)) {
9481                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9482                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9483                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9484         }
9485
9486         lpt_disable_clkout_dp(dev);
9487         hsw_disable_lcpll(dev_priv, true, true);
9488 }
9489
9490 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9491 {
9492         struct drm_device *dev = dev_priv->dev;
9493         uint32_t val;
9494
9495         DRM_DEBUG_KMS("Disabling package C8+\n");
9496
9497         hsw_restore_lcpll(dev_priv);
9498         lpt_init_pch_refclk(dev);
9499
9500         if (HAS_PCH_LPT_LP(dev)) {
9501                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9502                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9503                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9504         }
9505
9506         intel_prepare_ddi(dev);
9507 }
9508
9509 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9510 {
9511         struct drm_device *dev = old_state->dev;
9512         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9513
9514         broxton_set_cdclk(dev, req_cdclk);
9515 }
9516
9517 /* compute the max rate for new configuration */
9518 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9519 {
9520         struct intel_crtc *intel_crtc;
9521         struct intel_crtc_state *crtc_state;
9522         int max_pixel_rate = 0;
9523
9524         for_each_intel_crtc(state->dev, intel_crtc) {
9525                 int pixel_rate;
9526
9527                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9528                 if (IS_ERR(crtc_state))
9529                         return PTR_ERR(crtc_state);
9530
9531                 if (!crtc_state->base.enable)
9532                         continue;
9533
9534                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9535
9536                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9537                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9538                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9539
9540                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9541         }
9542
9543         return max_pixel_rate;
9544 }
9545
9546 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9547 {
9548         struct drm_i915_private *dev_priv = dev->dev_private;
9549         uint32_t val, data;
9550         int ret;
9551
9552         if (WARN((I915_READ(LCPLL_CTL) &
9553                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9554                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9555                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9556                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9557                  "trying to change cdclk frequency with cdclk not enabled\n"))
9558                 return;
9559
9560         mutex_lock(&dev_priv->rps.hw_lock);
9561         ret = sandybridge_pcode_write(dev_priv,
9562                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9563         mutex_unlock(&dev_priv->rps.hw_lock);
9564         if (ret) {
9565                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9566                 return;
9567         }
9568
9569         val = I915_READ(LCPLL_CTL);
9570         val |= LCPLL_CD_SOURCE_FCLK;
9571         I915_WRITE(LCPLL_CTL, val);
9572
9573         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9574                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9575                 DRM_ERROR("Switching to FCLK failed\n");
9576
9577         val = I915_READ(LCPLL_CTL);
9578         val &= ~LCPLL_CLK_FREQ_MASK;
9579
9580         switch (cdclk) {
9581         case 450000:
9582                 val |= LCPLL_CLK_FREQ_450;
9583                 data = 0;
9584                 break;
9585         case 540000:
9586                 val |= LCPLL_CLK_FREQ_54O_BDW;
9587                 data = 1;
9588                 break;
9589         case 337500:
9590                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9591                 data = 2;
9592                 break;
9593         case 675000:
9594                 val |= LCPLL_CLK_FREQ_675_BDW;
9595                 data = 3;
9596                 break;
9597         default:
9598                 WARN(1, "invalid cdclk frequency\n");
9599                 return;
9600         }
9601
9602         I915_WRITE(LCPLL_CTL, val);
9603
9604         val = I915_READ(LCPLL_CTL);
9605         val &= ~LCPLL_CD_SOURCE_FCLK;
9606         I915_WRITE(LCPLL_CTL, val);
9607
9608         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9609                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9610                 DRM_ERROR("Switching back to LCPLL failed\n");
9611
9612         mutex_lock(&dev_priv->rps.hw_lock);
9613         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9614         mutex_unlock(&dev_priv->rps.hw_lock);
9615
9616         intel_update_cdclk(dev);
9617
9618         WARN(cdclk != dev_priv->cdclk_freq,
9619              "cdclk requested %d kHz but got %d kHz\n",
9620              cdclk, dev_priv->cdclk_freq);
9621 }
9622
9623 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9624 {
9625         struct drm_i915_private *dev_priv = to_i915(state->dev);
9626         int max_pixclk = ilk_max_pixel_rate(state);
9627         int cdclk;
9628
9629         /*
9630          * FIXME should also account for plane ratio
9631          * once 64bpp pixel formats are supported.
9632          */
9633         if (max_pixclk > 540000)
9634                 cdclk = 675000;
9635         else if (max_pixclk > 450000)
9636                 cdclk = 540000;
9637         else if (max_pixclk > 337500)
9638                 cdclk = 450000;
9639         else
9640                 cdclk = 337500;
9641
9642         /*
9643          * FIXME move the cdclk caclulation to
9644          * compute_config() so we can fail gracegully.
9645          */
9646         if (cdclk > dev_priv->max_cdclk_freq) {
9647                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9648                           cdclk, dev_priv->max_cdclk_freq);
9649                 cdclk = dev_priv->max_cdclk_freq;
9650         }
9651
9652         to_intel_atomic_state(state)->cdclk = cdclk;
9653
9654         return 0;
9655 }
9656
9657 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9658 {
9659         struct drm_device *dev = old_state->dev;
9660         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9661
9662         broadwell_set_cdclk(dev, req_cdclk);
9663 }
9664
9665 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9666                                       struct intel_crtc_state *crtc_state)
9667 {
9668         if (!intel_ddi_pll_select(crtc, crtc_state))
9669                 return -EINVAL;
9670
9671         crtc->lowfreq_avail = false;
9672
9673         return 0;
9674 }
9675
9676 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9677                                 enum port port,
9678                                 struct intel_crtc_state *pipe_config)
9679 {
9680         switch (port) {
9681         case PORT_A:
9682                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9683                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9684                 break;
9685         case PORT_B:
9686                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9687                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9688                 break;
9689         case PORT_C:
9690                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9691                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9692                 break;
9693         default:
9694                 DRM_ERROR("Incorrect port type\n");
9695         }
9696 }
9697
9698 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9699                                 enum port port,
9700                                 struct intel_crtc_state *pipe_config)
9701 {
9702         u32 temp, dpll_ctl1;
9703
9704         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9705         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9706
9707         switch (pipe_config->ddi_pll_sel) {
9708         case SKL_DPLL0:
9709                 /*
9710                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9711                  * of the shared DPLL framework and thus needs to be read out
9712                  * separately
9713                  */
9714                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9715                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9716                 break;
9717         case SKL_DPLL1:
9718                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9719                 break;
9720         case SKL_DPLL2:
9721                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9722                 break;
9723         case SKL_DPLL3:
9724                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9725                 break;
9726         }
9727 }
9728
9729 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9730                                 enum port port,
9731                                 struct intel_crtc_state *pipe_config)
9732 {
9733         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9734
9735         switch (pipe_config->ddi_pll_sel) {
9736         case PORT_CLK_SEL_WRPLL1:
9737                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9738                 break;
9739         case PORT_CLK_SEL_WRPLL2:
9740                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9741                 break;
9742         }
9743 }
9744
9745 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9746                                        struct intel_crtc_state *pipe_config)
9747 {
9748         struct drm_device *dev = crtc->base.dev;
9749         struct drm_i915_private *dev_priv = dev->dev_private;
9750         struct intel_shared_dpll *pll;
9751         enum port port;
9752         uint32_t tmp;
9753
9754         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9755
9756         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9757
9758         if (IS_SKYLAKE(dev))
9759                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9760         else if (IS_BROXTON(dev))
9761                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9762         else
9763                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9764
9765         if (pipe_config->shared_dpll >= 0) {
9766                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9767
9768                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9769                                            &pipe_config->dpll_hw_state));
9770         }
9771
9772         /*
9773          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9774          * DDI E. So just check whether this pipe is wired to DDI E and whether
9775          * the PCH transcoder is on.
9776          */
9777         if (INTEL_INFO(dev)->gen < 9 &&
9778             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9779                 pipe_config->has_pch_encoder = true;
9780
9781                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9782                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9783                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9784
9785                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9786         }
9787 }
9788
9789 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9790                                     struct intel_crtc_state *pipe_config)
9791 {
9792         struct drm_device *dev = crtc->base.dev;
9793         struct drm_i915_private *dev_priv = dev->dev_private;
9794         enum intel_display_power_domain pfit_domain;
9795         uint32_t tmp;
9796
9797         if (!intel_display_power_is_enabled(dev_priv,
9798                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9799                 return false;
9800
9801         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9802         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9803
9804         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9805         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9806                 enum pipe trans_edp_pipe;
9807                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9808                 default:
9809                         WARN(1, "unknown pipe linked to edp transcoder\n");
9810                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9811                 case TRANS_DDI_EDP_INPUT_A_ON:
9812                         trans_edp_pipe = PIPE_A;
9813                         break;
9814                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9815                         trans_edp_pipe = PIPE_B;
9816                         break;
9817                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9818                         trans_edp_pipe = PIPE_C;
9819                         break;
9820                 }
9821
9822                 if (trans_edp_pipe == crtc->pipe)
9823                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9824         }
9825
9826         if (!intel_display_power_is_enabled(dev_priv,
9827                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9828                 return false;
9829
9830         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9831         if (!(tmp & PIPECONF_ENABLE))
9832                 return false;
9833
9834         haswell_get_ddi_port_state(crtc, pipe_config);
9835
9836         intel_get_pipe_timings(crtc, pipe_config);
9837
9838         if (INTEL_INFO(dev)->gen >= 9) {
9839                 skl_init_scalers(dev, crtc, pipe_config);
9840         }
9841
9842         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9843
9844         if (INTEL_INFO(dev)->gen >= 9) {
9845                 pipe_config->scaler_state.scaler_id = -1;
9846                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9847         }
9848
9849         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9850                 if (INTEL_INFO(dev)->gen >= 9)
9851                         skylake_get_pfit_config(crtc, pipe_config);
9852                 else
9853                         ironlake_get_pfit_config(crtc, pipe_config);
9854         }
9855
9856         if (IS_HASWELL(dev))
9857                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9858                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9859
9860         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9861                 pipe_config->pixel_multiplier =
9862                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9863         } else {
9864                 pipe_config->pixel_multiplier = 1;
9865         }
9866
9867         return true;
9868 }
9869
9870 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9871 {
9872         struct drm_device *dev = crtc->dev;
9873         struct drm_i915_private *dev_priv = dev->dev_private;
9874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9875         uint32_t cntl = 0, size = 0;
9876
9877         if (base) {
9878                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9879                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9880                 unsigned int stride = roundup_pow_of_two(width) * 4;
9881
9882                 switch (stride) {
9883                 default:
9884                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9885                                   width, stride);
9886                         stride = 256;
9887                         /* fallthrough */
9888                 case 256:
9889                 case 512:
9890                 case 1024:
9891                 case 2048:
9892                         break;
9893                 }
9894
9895                 cntl |= CURSOR_ENABLE |
9896                         CURSOR_GAMMA_ENABLE |
9897                         CURSOR_FORMAT_ARGB |
9898                         CURSOR_STRIDE(stride);
9899
9900                 size = (height << 12) | width;
9901         }
9902
9903         if (intel_crtc->cursor_cntl != 0 &&
9904             (intel_crtc->cursor_base != base ||
9905              intel_crtc->cursor_size != size ||
9906              intel_crtc->cursor_cntl != cntl)) {
9907                 /* On these chipsets we can only modify the base/size/stride
9908                  * whilst the cursor is disabled.
9909                  */
9910                 I915_WRITE(CURCNTR(PIPE_A), 0);
9911                 POSTING_READ(CURCNTR(PIPE_A));
9912                 intel_crtc->cursor_cntl = 0;
9913         }
9914
9915         if (intel_crtc->cursor_base != base) {
9916                 I915_WRITE(CURBASE(PIPE_A), base);
9917                 intel_crtc->cursor_base = base;
9918         }
9919
9920         if (intel_crtc->cursor_size != size) {
9921                 I915_WRITE(CURSIZE, size);
9922                 intel_crtc->cursor_size = size;
9923         }
9924
9925         if (intel_crtc->cursor_cntl != cntl) {
9926                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9927                 POSTING_READ(CURCNTR(PIPE_A));
9928                 intel_crtc->cursor_cntl = cntl;
9929         }
9930 }
9931
9932 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9933 {
9934         struct drm_device *dev = crtc->dev;
9935         struct drm_i915_private *dev_priv = dev->dev_private;
9936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9937         int pipe = intel_crtc->pipe;
9938         uint32_t cntl;
9939
9940         cntl = 0;
9941         if (base) {
9942                 cntl = MCURSOR_GAMMA_ENABLE;
9943                 switch (intel_crtc->base.cursor->state->crtc_w) {
9944                         case 64:
9945                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9946                                 break;
9947                         case 128:
9948                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9949                                 break;
9950                         case 256:
9951                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9952                                 break;
9953                         default:
9954                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9955                                 return;
9956                 }
9957                 cntl |= pipe << 28; /* Connect to correct pipe */
9958
9959                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9960                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9961         }
9962
9963         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9964                 cntl |= CURSOR_ROTATE_180;
9965
9966         if (intel_crtc->cursor_cntl != cntl) {
9967                 I915_WRITE(CURCNTR(pipe), cntl);
9968                 POSTING_READ(CURCNTR(pipe));
9969                 intel_crtc->cursor_cntl = cntl;
9970         }
9971
9972         /* and commit changes on next vblank */
9973         I915_WRITE(CURBASE(pipe), base);
9974         POSTING_READ(CURBASE(pipe));
9975
9976         intel_crtc->cursor_base = base;
9977 }
9978
9979 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9980 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9981                                      bool on)
9982 {
9983         struct drm_device *dev = crtc->dev;
9984         struct drm_i915_private *dev_priv = dev->dev_private;
9985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986         int pipe = intel_crtc->pipe;
9987         struct drm_plane_state *cursor_state = crtc->cursor->state;
9988         int x = cursor_state->crtc_x;
9989         int y = cursor_state->crtc_y;
9990         u32 base = 0, pos = 0;
9991
9992         if (on)
9993                 base = intel_crtc->cursor_addr;
9994
9995         if (x >= intel_crtc->config->pipe_src_w)
9996                 base = 0;
9997
9998         if (y >= intel_crtc->config->pipe_src_h)
9999                 base = 0;
10000
10001         if (x < 0) {
10002                 if (x + cursor_state->crtc_w <= 0)
10003                         base = 0;
10004
10005                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10006                 x = -x;
10007         }
10008         pos |= x << CURSOR_X_SHIFT;
10009
10010         if (y < 0) {
10011                 if (y + cursor_state->crtc_h <= 0)
10012                         base = 0;
10013
10014                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10015                 y = -y;
10016         }
10017         pos |= y << CURSOR_Y_SHIFT;
10018
10019         if (base == 0 && intel_crtc->cursor_base == 0)
10020                 return;
10021
10022         I915_WRITE(CURPOS(pipe), pos);
10023
10024         /* ILK+ do this automagically */
10025         if (HAS_GMCH_DISPLAY(dev) &&
10026             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10027                 base += (cursor_state->crtc_h *
10028                          cursor_state->crtc_w - 1) * 4;
10029         }
10030
10031         if (IS_845G(dev) || IS_I865G(dev))
10032                 i845_update_cursor(crtc, base);
10033         else
10034                 i9xx_update_cursor(crtc, base);
10035 }
10036
10037 static bool cursor_size_ok(struct drm_device *dev,
10038                            uint32_t width, uint32_t height)
10039 {
10040         if (width == 0 || height == 0)
10041                 return false;
10042
10043         /*
10044          * 845g/865g are special in that they are only limited by
10045          * the width of their cursors, the height is arbitrary up to
10046          * the precision of the register. Everything else requires
10047          * square cursors, limited to a few power-of-two sizes.
10048          */
10049         if (IS_845G(dev) || IS_I865G(dev)) {
10050                 if ((width & 63) != 0)
10051                         return false;
10052
10053                 if (width > (IS_845G(dev) ? 64 : 512))
10054                         return false;
10055
10056                 if (height > 1023)
10057                         return false;
10058         } else {
10059                 switch (width | height) {
10060                 case 256:
10061                 case 128:
10062                         if (IS_GEN2(dev))
10063                                 return false;
10064                 case 64:
10065                         break;
10066                 default:
10067                         return false;
10068                 }
10069         }
10070
10071         return true;
10072 }
10073
10074 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10075                                  u16 *blue, uint32_t start, uint32_t size)
10076 {
10077         int end = (start + size > 256) ? 256 : start + size, i;
10078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10079
10080         for (i = start; i < end; i++) {
10081                 intel_crtc->lut_r[i] = red[i] >> 8;
10082                 intel_crtc->lut_g[i] = green[i] >> 8;
10083                 intel_crtc->lut_b[i] = blue[i] >> 8;
10084         }
10085
10086         intel_crtc_load_lut(crtc);
10087 }
10088
10089 /* VESA 640x480x72Hz mode to set on the pipe */
10090 static struct drm_display_mode load_detect_mode = {
10091         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10092                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10093 };
10094
10095 struct drm_framebuffer *
10096 __intel_framebuffer_create(struct drm_device *dev,
10097                            struct drm_mode_fb_cmd2 *mode_cmd,
10098                            struct drm_i915_gem_object *obj)
10099 {
10100         struct intel_framebuffer *intel_fb;
10101         int ret;
10102
10103         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10104         if (!intel_fb) {
10105                 drm_gem_object_unreference(&obj->base);
10106                 return ERR_PTR(-ENOMEM);
10107         }
10108
10109         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10110         if (ret)
10111                 goto err;
10112
10113         return &intel_fb->base;
10114 err:
10115         drm_gem_object_unreference(&obj->base);
10116         kfree(intel_fb);
10117
10118         return ERR_PTR(ret);
10119 }
10120
10121 static struct drm_framebuffer *
10122 intel_framebuffer_create(struct drm_device *dev,
10123                          struct drm_mode_fb_cmd2 *mode_cmd,
10124                          struct drm_i915_gem_object *obj)
10125 {
10126         struct drm_framebuffer *fb;
10127         int ret;
10128
10129         ret = i915_mutex_lock_interruptible(dev);
10130         if (ret)
10131                 return ERR_PTR(ret);
10132         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10133         mutex_unlock(&dev->struct_mutex);
10134
10135         return fb;
10136 }
10137
10138 static u32
10139 intel_framebuffer_pitch_for_width(int width, int bpp)
10140 {
10141         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10142         return ALIGN(pitch, 64);
10143 }
10144
10145 static u32
10146 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10147 {
10148         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10149         return PAGE_ALIGN(pitch * mode->vdisplay);
10150 }
10151
10152 static struct drm_framebuffer *
10153 intel_framebuffer_create_for_mode(struct drm_device *dev,
10154                                   struct drm_display_mode *mode,
10155                                   int depth, int bpp)
10156 {
10157         struct drm_i915_gem_object *obj;
10158         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10159
10160         obj = i915_gem_alloc_object(dev,
10161                                     intel_framebuffer_size_for_mode(mode, bpp));
10162         if (obj == NULL)
10163                 return ERR_PTR(-ENOMEM);
10164
10165         mode_cmd.width = mode->hdisplay;
10166         mode_cmd.height = mode->vdisplay;
10167         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10168                                                                 bpp);
10169         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10170
10171         return intel_framebuffer_create(dev, &mode_cmd, obj);
10172 }
10173
10174 static struct drm_framebuffer *
10175 mode_fits_in_fbdev(struct drm_device *dev,
10176                    struct drm_display_mode *mode)
10177 {
10178 #ifdef CONFIG_DRM_FBDEV_EMULATION
10179         struct drm_i915_private *dev_priv = dev->dev_private;
10180         struct drm_i915_gem_object *obj;
10181         struct drm_framebuffer *fb;
10182
10183         if (!dev_priv->fbdev)
10184                 return NULL;
10185
10186         if (!dev_priv->fbdev->fb)
10187                 return NULL;
10188
10189         obj = dev_priv->fbdev->fb->obj;
10190         BUG_ON(!obj);
10191
10192         fb = &dev_priv->fbdev->fb->base;
10193         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10194                                                                fb->bits_per_pixel))
10195                 return NULL;
10196
10197         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10198                 return NULL;
10199
10200         return fb;
10201 #else
10202         return NULL;
10203 #endif
10204 }
10205
10206 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10207                                            struct drm_crtc *crtc,
10208                                            struct drm_display_mode *mode,
10209                                            struct drm_framebuffer *fb,
10210                                            int x, int y)
10211 {
10212         struct drm_plane_state *plane_state;
10213         int hdisplay, vdisplay;
10214         int ret;
10215
10216         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10217         if (IS_ERR(plane_state))
10218                 return PTR_ERR(plane_state);
10219
10220         if (mode)
10221                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10222         else
10223                 hdisplay = vdisplay = 0;
10224
10225         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10226         if (ret)
10227                 return ret;
10228         drm_atomic_set_fb_for_plane(plane_state, fb);
10229         plane_state->crtc_x = 0;
10230         plane_state->crtc_y = 0;
10231         plane_state->crtc_w = hdisplay;
10232         plane_state->crtc_h = vdisplay;
10233         plane_state->src_x = x << 16;
10234         plane_state->src_y = y << 16;
10235         plane_state->src_w = hdisplay << 16;
10236         plane_state->src_h = vdisplay << 16;
10237
10238         return 0;
10239 }
10240
10241 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10242                                 struct drm_display_mode *mode,
10243                                 struct intel_load_detect_pipe *old,
10244                                 struct drm_modeset_acquire_ctx *ctx)
10245 {
10246         struct intel_crtc *intel_crtc;
10247         struct intel_encoder *intel_encoder =
10248                 intel_attached_encoder(connector);
10249         struct drm_crtc *possible_crtc;
10250         struct drm_encoder *encoder = &intel_encoder->base;
10251         struct drm_crtc *crtc = NULL;
10252         struct drm_device *dev = encoder->dev;
10253         struct drm_framebuffer *fb;
10254         struct drm_mode_config *config = &dev->mode_config;
10255         struct drm_atomic_state *state = NULL;
10256         struct drm_connector_state *connector_state;
10257         struct intel_crtc_state *crtc_state;
10258         int ret, i = -1;
10259
10260         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10261                       connector->base.id, connector->name,
10262                       encoder->base.id, encoder->name);
10263
10264 retry:
10265         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10266         if (ret)
10267                 goto fail;
10268
10269         /*
10270          * Algorithm gets a little messy:
10271          *
10272          *   - if the connector already has an assigned crtc, use it (but make
10273          *     sure it's on first)
10274          *
10275          *   - try to find the first unused crtc that can drive this connector,
10276          *     and use that if we find one
10277          */
10278
10279         /* See if we already have a CRTC for this connector */
10280         if (encoder->crtc) {
10281                 crtc = encoder->crtc;
10282
10283                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10284                 if (ret)
10285                         goto fail;
10286                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10287                 if (ret)
10288                         goto fail;
10289
10290                 old->dpms_mode = connector->dpms;
10291                 old->load_detect_temp = false;
10292
10293                 /* Make sure the crtc and connector are running */
10294                 if (connector->dpms != DRM_MODE_DPMS_ON)
10295                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10296
10297                 return true;
10298         }
10299
10300         /* Find an unused one (if possible) */
10301         for_each_crtc(dev, possible_crtc) {
10302                 i++;
10303                 if (!(encoder->possible_crtcs & (1 << i)))
10304                         continue;
10305                 if (possible_crtc->state->enable)
10306                         continue;
10307
10308                 crtc = possible_crtc;
10309                 break;
10310         }
10311
10312         /*
10313          * If we didn't find an unused CRTC, don't use any.
10314          */
10315         if (!crtc) {
10316                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10317                 goto fail;
10318         }
10319
10320         ret = drm_modeset_lock(&crtc->mutex, ctx);
10321         if (ret)
10322                 goto fail;
10323         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10324         if (ret)
10325                 goto fail;
10326
10327         intel_crtc = to_intel_crtc(crtc);
10328         old->dpms_mode = connector->dpms;
10329         old->load_detect_temp = true;
10330         old->release_fb = NULL;
10331
10332         state = drm_atomic_state_alloc(dev);
10333         if (!state)
10334                 return false;
10335
10336         state->acquire_ctx = ctx;
10337
10338         connector_state = drm_atomic_get_connector_state(state, connector);
10339         if (IS_ERR(connector_state)) {
10340                 ret = PTR_ERR(connector_state);
10341                 goto fail;
10342         }
10343
10344         connector_state->crtc = crtc;
10345         connector_state->best_encoder = &intel_encoder->base;
10346
10347         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10348         if (IS_ERR(crtc_state)) {
10349                 ret = PTR_ERR(crtc_state);
10350                 goto fail;
10351         }
10352
10353         crtc_state->base.active = crtc_state->base.enable = true;
10354
10355         if (!mode)
10356                 mode = &load_detect_mode;
10357
10358         /* We need a framebuffer large enough to accommodate all accesses
10359          * that the plane may generate whilst we perform load detection.
10360          * We can not rely on the fbcon either being present (we get called
10361          * during its initialisation to detect all boot displays, or it may
10362          * not even exist) or that it is large enough to satisfy the
10363          * requested mode.
10364          */
10365         fb = mode_fits_in_fbdev(dev, mode);
10366         if (fb == NULL) {
10367                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10368                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10369                 old->release_fb = fb;
10370         } else
10371                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10372         if (IS_ERR(fb)) {
10373                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10374                 goto fail;
10375         }
10376
10377         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10378         if (ret)
10379                 goto fail;
10380
10381         drm_mode_copy(&crtc_state->base.mode, mode);
10382
10383         if (drm_atomic_commit(state)) {
10384                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10385                 if (old->release_fb)
10386                         old->release_fb->funcs->destroy(old->release_fb);
10387                 goto fail;
10388         }
10389         crtc->primary->crtc = crtc;
10390
10391         /* let the connector get through one full cycle before testing */
10392         intel_wait_for_vblank(dev, intel_crtc->pipe);
10393         return true;
10394
10395 fail:
10396         drm_atomic_state_free(state);
10397         state = NULL;
10398
10399         if (ret == -EDEADLK) {
10400                 drm_modeset_backoff(ctx);
10401                 goto retry;
10402         }
10403
10404         return false;
10405 }
10406
10407 void intel_release_load_detect_pipe(struct drm_connector *connector,
10408                                     struct intel_load_detect_pipe *old,
10409                                     struct drm_modeset_acquire_ctx *ctx)
10410 {
10411         struct drm_device *dev = connector->dev;
10412         struct intel_encoder *intel_encoder =
10413                 intel_attached_encoder(connector);
10414         struct drm_encoder *encoder = &intel_encoder->base;
10415         struct drm_crtc *crtc = encoder->crtc;
10416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10417         struct drm_atomic_state *state;
10418         struct drm_connector_state *connector_state;
10419         struct intel_crtc_state *crtc_state;
10420         int ret;
10421
10422         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10423                       connector->base.id, connector->name,
10424                       encoder->base.id, encoder->name);
10425
10426         if (old->load_detect_temp) {
10427                 state = drm_atomic_state_alloc(dev);
10428                 if (!state)
10429                         goto fail;
10430
10431                 state->acquire_ctx = ctx;
10432
10433                 connector_state = drm_atomic_get_connector_state(state, connector);
10434                 if (IS_ERR(connector_state))
10435                         goto fail;
10436
10437                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10438                 if (IS_ERR(crtc_state))
10439                         goto fail;
10440
10441                 connector_state->best_encoder = NULL;
10442                 connector_state->crtc = NULL;
10443
10444                 crtc_state->base.enable = crtc_state->base.active = false;
10445
10446                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10447                                                       0, 0);
10448                 if (ret)
10449                         goto fail;
10450
10451                 ret = drm_atomic_commit(state);
10452                 if (ret)
10453                         goto fail;
10454
10455                 if (old->release_fb) {
10456                         drm_framebuffer_unregister_private(old->release_fb);
10457                         drm_framebuffer_unreference(old->release_fb);
10458                 }
10459
10460                 return;
10461         }
10462
10463         /* Switch crtc and encoder back off if necessary */
10464         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10465                 connector->funcs->dpms(connector, old->dpms_mode);
10466
10467         return;
10468 fail:
10469         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10470         drm_atomic_state_free(state);
10471 }
10472
10473 static int i9xx_pll_refclk(struct drm_device *dev,
10474                            const struct intel_crtc_state *pipe_config)
10475 {
10476         struct drm_i915_private *dev_priv = dev->dev_private;
10477         u32 dpll = pipe_config->dpll_hw_state.dpll;
10478
10479         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10480                 return dev_priv->vbt.lvds_ssc_freq;
10481         else if (HAS_PCH_SPLIT(dev))
10482                 return 120000;
10483         else if (!IS_GEN2(dev))
10484                 return 96000;
10485         else
10486                 return 48000;
10487 }
10488
10489 /* Returns the clock of the currently programmed mode of the given pipe. */
10490 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10491                                 struct intel_crtc_state *pipe_config)
10492 {
10493         struct drm_device *dev = crtc->base.dev;
10494         struct drm_i915_private *dev_priv = dev->dev_private;
10495         int pipe = pipe_config->cpu_transcoder;
10496         u32 dpll = pipe_config->dpll_hw_state.dpll;
10497         u32 fp;
10498         intel_clock_t clock;
10499         int port_clock;
10500         int refclk = i9xx_pll_refclk(dev, pipe_config);
10501
10502         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10503                 fp = pipe_config->dpll_hw_state.fp0;
10504         else
10505                 fp = pipe_config->dpll_hw_state.fp1;
10506
10507         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10508         if (IS_PINEVIEW(dev)) {
10509                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10510                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10511         } else {
10512                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10513                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10514         }
10515
10516         if (!IS_GEN2(dev)) {
10517                 if (IS_PINEVIEW(dev))
10518                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10519                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10520                 else
10521                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10522                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10523
10524                 switch (dpll & DPLL_MODE_MASK) {
10525                 case DPLLB_MODE_DAC_SERIAL:
10526                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10527                                 5 : 10;
10528                         break;
10529                 case DPLLB_MODE_LVDS:
10530                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10531                                 7 : 14;
10532                         break;
10533                 default:
10534                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10535                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10536                         return;
10537                 }
10538
10539                 if (IS_PINEVIEW(dev))
10540                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10541                 else
10542                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10543         } else {
10544                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10545                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10546
10547                 if (is_lvds) {
10548                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10549                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10550
10551                         if (lvds & LVDS_CLKB_POWER_UP)
10552                                 clock.p2 = 7;
10553                         else
10554                                 clock.p2 = 14;
10555                 } else {
10556                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10557                                 clock.p1 = 2;
10558                         else {
10559                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10560                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10561                         }
10562                         if (dpll & PLL_P2_DIVIDE_BY_4)
10563                                 clock.p2 = 4;
10564                         else
10565                                 clock.p2 = 2;
10566                 }
10567
10568                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10569         }
10570
10571         /*
10572          * This value includes pixel_multiplier. We will use
10573          * port_clock to compute adjusted_mode.crtc_clock in the
10574          * encoder's get_config() function.
10575          */
10576         pipe_config->port_clock = port_clock;
10577 }
10578
10579 int intel_dotclock_calculate(int link_freq,
10580                              const struct intel_link_m_n *m_n)
10581 {
10582         /*
10583          * The calculation for the data clock is:
10584          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10585          * But we want to avoid losing precison if possible, so:
10586          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10587          *
10588          * and the link clock is simpler:
10589          * link_clock = (m * link_clock) / n
10590          */
10591
10592         if (!m_n->link_n)
10593                 return 0;
10594
10595         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10596 }
10597
10598 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10599                                    struct intel_crtc_state *pipe_config)
10600 {
10601         struct drm_device *dev = crtc->base.dev;
10602
10603         /* read out port_clock from the DPLL */
10604         i9xx_crtc_clock_get(crtc, pipe_config);
10605
10606         /*
10607          * This value does not include pixel_multiplier.
10608          * We will check that port_clock and adjusted_mode.crtc_clock
10609          * agree once we know their relationship in the encoder's
10610          * get_config() function.
10611          */
10612         pipe_config->base.adjusted_mode.crtc_clock =
10613                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10614                                          &pipe_config->fdi_m_n);
10615 }
10616
10617 /** Returns the currently programmed mode of the given pipe. */
10618 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10619                                              struct drm_crtc *crtc)
10620 {
10621         struct drm_i915_private *dev_priv = dev->dev_private;
10622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10623         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10624         struct drm_display_mode *mode;
10625         struct intel_crtc_state pipe_config;
10626         int htot = I915_READ(HTOTAL(cpu_transcoder));
10627         int hsync = I915_READ(HSYNC(cpu_transcoder));
10628         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10629         int vsync = I915_READ(VSYNC(cpu_transcoder));
10630         enum pipe pipe = intel_crtc->pipe;
10631
10632         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10633         if (!mode)
10634                 return NULL;
10635
10636         /*
10637          * Construct a pipe_config sufficient for getting the clock info
10638          * back out of crtc_clock_get.
10639          *
10640          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10641          * to use a real value here instead.
10642          */
10643         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10644         pipe_config.pixel_multiplier = 1;
10645         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10646         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10647         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10648         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10649
10650         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10651         mode->hdisplay = (htot & 0xffff) + 1;
10652         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10653         mode->hsync_start = (hsync & 0xffff) + 1;
10654         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10655         mode->vdisplay = (vtot & 0xffff) + 1;
10656         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10657         mode->vsync_start = (vsync & 0xffff) + 1;
10658         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10659
10660         drm_mode_set_name(mode);
10661
10662         return mode;
10663 }
10664
10665 void intel_mark_busy(struct drm_device *dev)
10666 {
10667         struct drm_i915_private *dev_priv = dev->dev_private;
10668
10669         if (dev_priv->mm.busy)
10670                 return;
10671
10672         intel_runtime_pm_get(dev_priv);
10673         i915_update_gfx_val(dev_priv);
10674         if (INTEL_INFO(dev)->gen >= 6)
10675                 gen6_rps_busy(dev_priv);
10676         dev_priv->mm.busy = true;
10677 }
10678
10679 void intel_mark_idle(struct drm_device *dev)
10680 {
10681         struct drm_i915_private *dev_priv = dev->dev_private;
10682
10683         if (!dev_priv->mm.busy)
10684                 return;
10685
10686         dev_priv->mm.busy = false;
10687
10688         if (INTEL_INFO(dev)->gen >= 6)
10689                 gen6_rps_idle(dev->dev_private);
10690
10691         intel_runtime_pm_put(dev_priv);
10692 }
10693
10694 static void intel_crtc_destroy(struct drm_crtc *crtc)
10695 {
10696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10697         struct drm_device *dev = crtc->dev;
10698         struct intel_unpin_work *work;
10699
10700         spin_lock_irq(&dev->event_lock);
10701         work = intel_crtc->unpin_work;
10702         intel_crtc->unpin_work = NULL;
10703         spin_unlock_irq(&dev->event_lock);
10704
10705         if (work) {
10706                 cancel_work_sync(&work->work);
10707                 kfree(work);
10708         }
10709
10710         drm_crtc_cleanup(crtc);
10711
10712         kfree(intel_crtc);
10713 }
10714
10715 static void intel_unpin_work_fn(struct work_struct *__work)
10716 {
10717         struct intel_unpin_work *work =
10718                 container_of(__work, struct intel_unpin_work, work);
10719         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10720         struct drm_device *dev = crtc->base.dev;
10721         struct drm_plane *primary = crtc->base.primary;
10722
10723         mutex_lock(&dev->struct_mutex);
10724         intel_unpin_fb_obj(work->old_fb, primary->state);
10725         drm_gem_object_unreference(&work->pending_flip_obj->base);
10726
10727         if (work->flip_queued_req)
10728                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10729         mutex_unlock(&dev->struct_mutex);
10730
10731         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10732         drm_framebuffer_unreference(work->old_fb);
10733
10734         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10735         atomic_dec(&crtc->unpin_work_count);
10736
10737         kfree(work);
10738 }
10739
10740 static void do_intel_finish_page_flip(struct drm_device *dev,
10741                                       struct drm_crtc *crtc)
10742 {
10743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10744         struct intel_unpin_work *work;
10745         unsigned long flags;
10746
10747         /* Ignore early vblank irqs */
10748         if (intel_crtc == NULL)
10749                 return;
10750
10751         /*
10752          * This is called both by irq handlers and the reset code (to complete
10753          * lost pageflips) so needs the full irqsave spinlocks.
10754          */
10755         spin_lock_irqsave(&dev->event_lock, flags);
10756         work = intel_crtc->unpin_work;
10757
10758         /* Ensure we don't miss a work->pending update ... */
10759         smp_rmb();
10760
10761         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10762                 spin_unlock_irqrestore(&dev->event_lock, flags);
10763                 return;
10764         }
10765
10766         page_flip_completed(intel_crtc);
10767
10768         spin_unlock_irqrestore(&dev->event_lock, flags);
10769 }
10770
10771 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10772 {
10773         struct drm_i915_private *dev_priv = dev->dev_private;
10774         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10775
10776         do_intel_finish_page_flip(dev, crtc);
10777 }
10778
10779 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10780 {
10781         struct drm_i915_private *dev_priv = dev->dev_private;
10782         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10783
10784         do_intel_finish_page_flip(dev, crtc);
10785 }
10786
10787 /* Is 'a' after or equal to 'b'? */
10788 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10789 {
10790         return !((a - b) & 0x80000000);
10791 }
10792
10793 static bool page_flip_finished(struct intel_crtc *crtc)
10794 {
10795         struct drm_device *dev = crtc->base.dev;
10796         struct drm_i915_private *dev_priv = dev->dev_private;
10797
10798         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10799             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10800                 return true;
10801
10802         /*
10803          * The relevant registers doen't exist on pre-ctg.
10804          * As the flip done interrupt doesn't trigger for mmio
10805          * flips on gmch platforms, a flip count check isn't
10806          * really needed there. But since ctg has the registers,
10807          * include it in the check anyway.
10808          */
10809         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10810                 return true;
10811
10812         /*
10813          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10814          * used the same base address. In that case the mmio flip might
10815          * have completed, but the CS hasn't even executed the flip yet.
10816          *
10817          * A flip count check isn't enough as the CS might have updated
10818          * the base address just after start of vblank, but before we
10819          * managed to process the interrupt. This means we'd complete the
10820          * CS flip too soon.
10821          *
10822          * Combining both checks should get us a good enough result. It may
10823          * still happen that the CS flip has been executed, but has not
10824          * yet actually completed. But in case the base address is the same
10825          * anyway, we don't really care.
10826          */
10827         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10828                 crtc->unpin_work->gtt_offset &&
10829                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10830                                     crtc->unpin_work->flip_count);
10831 }
10832
10833 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10834 {
10835         struct drm_i915_private *dev_priv = dev->dev_private;
10836         struct intel_crtc *intel_crtc =
10837                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10838         unsigned long flags;
10839
10840
10841         /*
10842          * This is called both by irq handlers and the reset code (to complete
10843          * lost pageflips) so needs the full irqsave spinlocks.
10844          *
10845          * NB: An MMIO update of the plane base pointer will also
10846          * generate a page-flip completion irq, i.e. every modeset
10847          * is also accompanied by a spurious intel_prepare_page_flip().
10848          */
10849         spin_lock_irqsave(&dev->event_lock, flags);
10850         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10851                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10852         spin_unlock_irqrestore(&dev->event_lock, flags);
10853 }
10854
10855 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10856 {
10857         /* Ensure that the work item is consistent when activating it ... */
10858         smp_wmb();
10859         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10860         /* and that it is marked active as soon as the irq could fire. */
10861         smp_wmb();
10862 }
10863
10864 static int intel_gen2_queue_flip(struct drm_device *dev,
10865                                  struct drm_crtc *crtc,
10866                                  struct drm_framebuffer *fb,
10867                                  struct drm_i915_gem_object *obj,
10868                                  struct drm_i915_gem_request *req,
10869                                  uint32_t flags)
10870 {
10871         struct intel_engine_cs *ring = req->ring;
10872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10873         u32 flip_mask;
10874         int ret;
10875
10876         ret = intel_ring_begin(req, 6);
10877         if (ret)
10878                 return ret;
10879
10880         /* Can't queue multiple flips, so wait for the previous
10881          * one to finish before executing the next.
10882          */
10883         if (intel_crtc->plane)
10884                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10885         else
10886                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10887         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10888         intel_ring_emit(ring, MI_NOOP);
10889         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10890                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10891         intel_ring_emit(ring, fb->pitches[0]);
10892         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10893         intel_ring_emit(ring, 0); /* aux display base address, unused */
10894
10895         intel_mark_page_flip_active(intel_crtc);
10896         return 0;
10897 }
10898
10899 static int intel_gen3_queue_flip(struct drm_device *dev,
10900                                  struct drm_crtc *crtc,
10901                                  struct drm_framebuffer *fb,
10902                                  struct drm_i915_gem_object *obj,
10903                                  struct drm_i915_gem_request *req,
10904                                  uint32_t flags)
10905 {
10906         struct intel_engine_cs *ring = req->ring;
10907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10908         u32 flip_mask;
10909         int ret;
10910
10911         ret = intel_ring_begin(req, 6);
10912         if (ret)
10913                 return ret;
10914
10915         if (intel_crtc->plane)
10916                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10917         else
10918                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10919         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10920         intel_ring_emit(ring, MI_NOOP);
10921         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10922                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10923         intel_ring_emit(ring, fb->pitches[0]);
10924         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10925         intel_ring_emit(ring, MI_NOOP);
10926
10927         intel_mark_page_flip_active(intel_crtc);
10928         return 0;
10929 }
10930
10931 static int intel_gen4_queue_flip(struct drm_device *dev,
10932                                  struct drm_crtc *crtc,
10933                                  struct drm_framebuffer *fb,
10934                                  struct drm_i915_gem_object *obj,
10935                                  struct drm_i915_gem_request *req,
10936                                  uint32_t flags)
10937 {
10938         struct intel_engine_cs *ring = req->ring;
10939         struct drm_i915_private *dev_priv = dev->dev_private;
10940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10941         uint32_t pf, pipesrc;
10942         int ret;
10943
10944         ret = intel_ring_begin(req, 4);
10945         if (ret)
10946                 return ret;
10947
10948         /* i965+ uses the linear or tiled offsets from the
10949          * Display Registers (which do not change across a page-flip)
10950          * so we need only reprogram the base address.
10951          */
10952         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10953                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10954         intel_ring_emit(ring, fb->pitches[0]);
10955         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10956                         obj->tiling_mode);
10957
10958         /* XXX Enabling the panel-fitter across page-flip is so far
10959          * untested on non-native modes, so ignore it for now.
10960          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10961          */
10962         pf = 0;
10963         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10964         intel_ring_emit(ring, pf | pipesrc);
10965
10966         intel_mark_page_flip_active(intel_crtc);
10967         return 0;
10968 }
10969
10970 static int intel_gen6_queue_flip(struct drm_device *dev,
10971                                  struct drm_crtc *crtc,
10972                                  struct drm_framebuffer *fb,
10973                                  struct drm_i915_gem_object *obj,
10974                                  struct drm_i915_gem_request *req,
10975                                  uint32_t flags)
10976 {
10977         struct intel_engine_cs *ring = req->ring;
10978         struct drm_i915_private *dev_priv = dev->dev_private;
10979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10980         uint32_t pf, pipesrc;
10981         int ret;
10982
10983         ret = intel_ring_begin(req, 4);
10984         if (ret)
10985                 return ret;
10986
10987         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10988                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10989         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10990         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10991
10992         /* Contrary to the suggestions in the documentation,
10993          * "Enable Panel Fitter" does not seem to be required when page
10994          * flipping with a non-native mode, and worse causes a normal
10995          * modeset to fail.
10996          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10997          */
10998         pf = 0;
10999         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11000         intel_ring_emit(ring, pf | pipesrc);
11001
11002         intel_mark_page_flip_active(intel_crtc);
11003         return 0;
11004 }
11005
11006 static int intel_gen7_queue_flip(struct drm_device *dev,
11007                                  struct drm_crtc *crtc,
11008                                  struct drm_framebuffer *fb,
11009                                  struct drm_i915_gem_object *obj,
11010                                  struct drm_i915_gem_request *req,
11011                                  uint32_t flags)
11012 {
11013         struct intel_engine_cs *ring = req->ring;
11014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11015         uint32_t plane_bit = 0;
11016         int len, ret;
11017
11018         switch (intel_crtc->plane) {
11019         case PLANE_A:
11020                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11021                 break;
11022         case PLANE_B:
11023                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11024                 break;
11025         case PLANE_C:
11026                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11027                 break;
11028         default:
11029                 WARN_ONCE(1, "unknown plane in flip command\n");
11030                 return -ENODEV;
11031         }
11032
11033         len = 4;
11034         if (ring->id == RCS) {
11035                 len += 6;
11036                 /*
11037                  * On Gen 8, SRM is now taking an extra dword to accommodate
11038                  * 48bits addresses, and we need a NOOP for the batch size to
11039                  * stay even.
11040                  */
11041                 if (IS_GEN8(dev))
11042                         len += 2;
11043         }
11044
11045         /*
11046          * BSpec MI_DISPLAY_FLIP for IVB:
11047          * "The full packet must be contained within the same cache line."
11048          *
11049          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11050          * cacheline, if we ever start emitting more commands before
11051          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11052          * then do the cacheline alignment, and finally emit the
11053          * MI_DISPLAY_FLIP.
11054          */
11055         ret = intel_ring_cacheline_align(req);
11056         if (ret)
11057                 return ret;
11058
11059         ret = intel_ring_begin(req, len);
11060         if (ret)
11061                 return ret;
11062
11063         /* Unmask the flip-done completion message. Note that the bspec says that
11064          * we should do this for both the BCS and RCS, and that we must not unmask
11065          * more than one flip event at any time (or ensure that one flip message
11066          * can be sent by waiting for flip-done prior to queueing new flips).
11067          * Experimentation says that BCS works despite DERRMR masking all
11068          * flip-done completion events and that unmasking all planes at once
11069          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11070          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11071          */
11072         if (ring->id == RCS) {
11073                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11074                 intel_ring_emit(ring, DERRMR);
11075                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11076                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11077                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11078                 if (IS_GEN8(dev))
11079                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11080                                               MI_SRM_LRM_GLOBAL_GTT);
11081                 else
11082                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11083                                               MI_SRM_LRM_GLOBAL_GTT);
11084                 intel_ring_emit(ring, DERRMR);
11085                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11086                 if (IS_GEN8(dev)) {
11087                         intel_ring_emit(ring, 0);
11088                         intel_ring_emit(ring, MI_NOOP);
11089                 }
11090         }
11091
11092         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11093         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11094         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11095         intel_ring_emit(ring, (MI_NOOP));
11096
11097         intel_mark_page_flip_active(intel_crtc);
11098         return 0;
11099 }
11100
11101 static bool use_mmio_flip(struct intel_engine_cs *ring,
11102                           struct drm_i915_gem_object *obj)
11103 {
11104         /*
11105          * This is not being used for older platforms, because
11106          * non-availability of flip done interrupt forces us to use
11107          * CS flips. Older platforms derive flip done using some clever
11108          * tricks involving the flip_pending status bits and vblank irqs.
11109          * So using MMIO flips there would disrupt this mechanism.
11110          */
11111
11112         if (ring == NULL)
11113                 return true;
11114
11115         if (INTEL_INFO(ring->dev)->gen < 5)
11116                 return false;
11117
11118         if (i915.use_mmio_flip < 0)
11119                 return false;
11120         else if (i915.use_mmio_flip > 0)
11121                 return true;
11122         else if (i915.enable_execlists)
11123                 return true;
11124         else
11125                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11126 }
11127
11128 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11129 {
11130         struct drm_device *dev = intel_crtc->base.dev;
11131         struct drm_i915_private *dev_priv = dev->dev_private;
11132         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11133         const enum pipe pipe = intel_crtc->pipe;
11134         u32 ctl, stride;
11135
11136         ctl = I915_READ(PLANE_CTL(pipe, 0));
11137         ctl &= ~PLANE_CTL_TILED_MASK;
11138         switch (fb->modifier[0]) {
11139         case DRM_FORMAT_MOD_NONE:
11140                 break;
11141         case I915_FORMAT_MOD_X_TILED:
11142                 ctl |= PLANE_CTL_TILED_X;
11143                 break;
11144         case I915_FORMAT_MOD_Y_TILED:
11145                 ctl |= PLANE_CTL_TILED_Y;
11146                 break;
11147         case I915_FORMAT_MOD_Yf_TILED:
11148                 ctl |= PLANE_CTL_TILED_YF;
11149                 break;
11150         default:
11151                 MISSING_CASE(fb->modifier[0]);
11152         }
11153
11154         /*
11155          * The stride is either expressed as a multiple of 64 bytes chunks for
11156          * linear buffers or in number of tiles for tiled buffers.
11157          */
11158         stride = fb->pitches[0] /
11159                  intel_fb_stride_alignment(dev, fb->modifier[0],
11160                                            fb->pixel_format);
11161
11162         /*
11163          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11164          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11165          */
11166         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11167         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11168
11169         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11170         POSTING_READ(PLANE_SURF(pipe, 0));
11171 }
11172
11173 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11174 {
11175         struct drm_device *dev = intel_crtc->base.dev;
11176         struct drm_i915_private *dev_priv = dev->dev_private;
11177         struct intel_framebuffer *intel_fb =
11178                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11179         struct drm_i915_gem_object *obj = intel_fb->obj;
11180         u32 dspcntr;
11181         u32 reg;
11182
11183         reg = DSPCNTR(intel_crtc->plane);
11184         dspcntr = I915_READ(reg);
11185
11186         if (obj->tiling_mode != I915_TILING_NONE)
11187                 dspcntr |= DISPPLANE_TILED;
11188         else
11189                 dspcntr &= ~DISPPLANE_TILED;
11190
11191         I915_WRITE(reg, dspcntr);
11192
11193         I915_WRITE(DSPSURF(intel_crtc->plane),
11194                    intel_crtc->unpin_work->gtt_offset);
11195         POSTING_READ(DSPSURF(intel_crtc->plane));
11196
11197 }
11198
11199 /*
11200  * XXX: This is the temporary way to update the plane registers until we get
11201  * around to using the usual plane update functions for MMIO flips
11202  */
11203 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11204 {
11205         struct drm_device *dev = intel_crtc->base.dev;
11206
11207         intel_mark_page_flip_active(intel_crtc);
11208
11209         intel_pipe_update_start(intel_crtc);
11210
11211         if (INTEL_INFO(dev)->gen >= 9)
11212                 skl_do_mmio_flip(intel_crtc);
11213         else
11214                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11215                 ilk_do_mmio_flip(intel_crtc);
11216
11217         intel_pipe_update_end(intel_crtc);
11218 }
11219
11220 static void intel_mmio_flip_work_func(struct work_struct *work)
11221 {
11222         struct intel_mmio_flip *mmio_flip =
11223                 container_of(work, struct intel_mmio_flip, work);
11224
11225         if (mmio_flip->req)
11226                 WARN_ON(__i915_wait_request(mmio_flip->req,
11227                                             mmio_flip->crtc->reset_counter,
11228                                             false, NULL,
11229                                             &mmio_flip->i915->rps.mmioflips));
11230
11231         intel_do_mmio_flip(mmio_flip->crtc);
11232
11233         i915_gem_request_unreference__unlocked(mmio_flip->req);
11234         kfree(mmio_flip);
11235 }
11236
11237 static int intel_queue_mmio_flip(struct drm_device *dev,
11238                                  struct drm_crtc *crtc,
11239                                  struct drm_framebuffer *fb,
11240                                  struct drm_i915_gem_object *obj,
11241                                  struct intel_engine_cs *ring,
11242                                  uint32_t flags)
11243 {
11244         struct intel_mmio_flip *mmio_flip;
11245
11246         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11247         if (mmio_flip == NULL)
11248                 return -ENOMEM;
11249
11250         mmio_flip->i915 = to_i915(dev);
11251         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11252         mmio_flip->crtc = to_intel_crtc(crtc);
11253
11254         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11255         schedule_work(&mmio_flip->work);
11256
11257         return 0;
11258 }
11259
11260 static int intel_default_queue_flip(struct drm_device *dev,
11261                                     struct drm_crtc *crtc,
11262                                     struct drm_framebuffer *fb,
11263                                     struct drm_i915_gem_object *obj,
11264                                     struct drm_i915_gem_request *req,
11265                                     uint32_t flags)
11266 {
11267         return -ENODEV;
11268 }
11269
11270 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11271                                          struct drm_crtc *crtc)
11272 {
11273         struct drm_i915_private *dev_priv = dev->dev_private;
11274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11275         struct intel_unpin_work *work = intel_crtc->unpin_work;
11276         u32 addr;
11277
11278         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11279                 return true;
11280
11281         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11282                 return false;
11283
11284         if (!work->enable_stall_check)
11285                 return false;
11286
11287         if (work->flip_ready_vblank == 0) {
11288                 if (work->flip_queued_req &&
11289                     !i915_gem_request_completed(work->flip_queued_req, true))
11290                         return false;
11291
11292                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11293         }
11294
11295         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11296                 return false;
11297
11298         /* Potential stall - if we see that the flip has happened,
11299          * assume a missed interrupt. */
11300         if (INTEL_INFO(dev)->gen >= 4)
11301                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11302         else
11303                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11304
11305         /* There is a potential issue here with a false positive after a flip
11306          * to the same address. We could address this by checking for a
11307          * non-incrementing frame counter.
11308          */
11309         return addr == work->gtt_offset;
11310 }
11311
11312 void intel_check_page_flip(struct drm_device *dev, int pipe)
11313 {
11314         struct drm_i915_private *dev_priv = dev->dev_private;
11315         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11317         struct intel_unpin_work *work;
11318
11319         WARN_ON(!in_interrupt());
11320
11321         if (crtc == NULL)
11322                 return;
11323
11324         spin_lock(&dev->event_lock);
11325         work = intel_crtc->unpin_work;
11326         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11327                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11328                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11329                 page_flip_completed(intel_crtc);
11330                 work = NULL;
11331         }
11332         if (work != NULL &&
11333             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11334                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11335         spin_unlock(&dev->event_lock);
11336 }
11337
11338 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11339                                 struct drm_framebuffer *fb,
11340                                 struct drm_pending_vblank_event *event,
11341                                 uint32_t page_flip_flags)
11342 {
11343         struct drm_device *dev = crtc->dev;
11344         struct drm_i915_private *dev_priv = dev->dev_private;
11345         struct drm_framebuffer *old_fb = crtc->primary->fb;
11346         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11348         struct drm_plane *primary = crtc->primary;
11349         enum pipe pipe = intel_crtc->pipe;
11350         struct intel_unpin_work *work;
11351         struct intel_engine_cs *ring;
11352         bool mmio_flip;
11353         struct drm_i915_gem_request *request = NULL;
11354         int ret;
11355
11356         /*
11357          * drm_mode_page_flip_ioctl() should already catch this, but double
11358          * check to be safe.  In the future we may enable pageflipping from
11359          * a disabled primary plane.
11360          */
11361         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11362                 return -EBUSY;
11363
11364         /* Can't change pixel format via MI display flips. */
11365         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11366                 return -EINVAL;
11367
11368         /*
11369          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11370          * Note that pitch changes could also affect these register.
11371          */
11372         if (INTEL_INFO(dev)->gen > 3 &&
11373             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11374              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11375                 return -EINVAL;
11376
11377         if (i915_terminally_wedged(&dev_priv->gpu_error))
11378                 goto out_hang;
11379
11380         work = kzalloc(sizeof(*work), GFP_KERNEL);
11381         if (work == NULL)
11382                 return -ENOMEM;
11383
11384         work->event = event;
11385         work->crtc = crtc;
11386         work->old_fb = old_fb;
11387         INIT_WORK(&work->work, intel_unpin_work_fn);
11388
11389         ret = drm_crtc_vblank_get(crtc);
11390         if (ret)
11391                 goto free_work;
11392
11393         /* We borrow the event spin lock for protecting unpin_work */
11394         spin_lock_irq(&dev->event_lock);
11395         if (intel_crtc->unpin_work) {
11396                 /* Before declaring the flip queue wedged, check if
11397                  * the hardware completed the operation behind our backs.
11398                  */
11399                 if (__intel_pageflip_stall_check(dev, crtc)) {
11400                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11401                         page_flip_completed(intel_crtc);
11402                 } else {
11403                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11404                         spin_unlock_irq(&dev->event_lock);
11405
11406                         drm_crtc_vblank_put(crtc);
11407                         kfree(work);
11408                         return -EBUSY;
11409                 }
11410         }
11411         intel_crtc->unpin_work = work;
11412         spin_unlock_irq(&dev->event_lock);
11413
11414         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11415                 flush_workqueue(dev_priv->wq);
11416
11417         /* Reference the objects for the scheduled work. */
11418         drm_framebuffer_reference(work->old_fb);
11419         drm_gem_object_reference(&obj->base);
11420
11421         crtc->primary->fb = fb;
11422         update_state_fb(crtc->primary);
11423
11424         work->pending_flip_obj = obj;
11425
11426         ret = i915_mutex_lock_interruptible(dev);
11427         if (ret)
11428                 goto cleanup;
11429
11430         atomic_inc(&intel_crtc->unpin_work_count);
11431         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11432
11433         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11434                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11435
11436         if (IS_VALLEYVIEW(dev)) {
11437                 ring = &dev_priv->ring[BCS];
11438                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11439                         /* vlv: DISPLAY_FLIP fails to change tiling */
11440                         ring = NULL;
11441         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11442                 ring = &dev_priv->ring[BCS];
11443         } else if (INTEL_INFO(dev)->gen >= 7) {
11444                 ring = i915_gem_request_get_ring(obj->last_write_req);
11445                 if (ring == NULL || ring->id != RCS)
11446                         ring = &dev_priv->ring[BCS];
11447         } else {
11448                 ring = &dev_priv->ring[RCS];
11449         }
11450
11451         mmio_flip = use_mmio_flip(ring, obj);
11452
11453         /* When using CS flips, we want to emit semaphores between rings.
11454          * However, when using mmio flips we will create a task to do the
11455          * synchronisation, so all we want here is to pin the framebuffer
11456          * into the display plane and skip any waits.
11457          */
11458         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11459                                          crtc->primary->state,
11460                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11461         if (ret)
11462                 goto cleanup_pending;
11463
11464         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11465                                                   obj, 0);
11466         work->gtt_offset += intel_crtc->dspaddr_offset;
11467
11468         if (mmio_flip) {
11469                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11470                                             page_flip_flags);
11471                 if (ret)
11472                         goto cleanup_unpin;
11473
11474                 i915_gem_request_assign(&work->flip_queued_req,
11475                                         obj->last_write_req);
11476         } else {
11477                 if (!request) {
11478                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11479                         if (ret)
11480                                 goto cleanup_unpin;
11481                 }
11482
11483                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11484                                                    page_flip_flags);
11485                 if (ret)
11486                         goto cleanup_unpin;
11487
11488                 i915_gem_request_assign(&work->flip_queued_req, request);
11489         }
11490
11491         if (request)
11492                 i915_add_request_no_flush(request);
11493
11494         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11495         work->enable_stall_check = true;
11496
11497         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11498                           to_intel_plane(primary)->frontbuffer_bit);
11499         mutex_unlock(&dev->struct_mutex);
11500
11501         intel_fbc_disable_crtc(intel_crtc);
11502         intel_frontbuffer_flip_prepare(dev,
11503                                        to_intel_plane(primary)->frontbuffer_bit);
11504
11505         trace_i915_flip_request(intel_crtc->plane, obj);
11506
11507         return 0;
11508
11509 cleanup_unpin:
11510         intel_unpin_fb_obj(fb, crtc->primary->state);
11511 cleanup_pending:
11512         if (request)
11513                 i915_gem_request_cancel(request);
11514         atomic_dec(&intel_crtc->unpin_work_count);
11515         mutex_unlock(&dev->struct_mutex);
11516 cleanup:
11517         crtc->primary->fb = old_fb;
11518         update_state_fb(crtc->primary);
11519
11520         drm_gem_object_unreference_unlocked(&obj->base);
11521         drm_framebuffer_unreference(work->old_fb);
11522
11523         spin_lock_irq(&dev->event_lock);
11524         intel_crtc->unpin_work = NULL;
11525         spin_unlock_irq(&dev->event_lock);
11526
11527         drm_crtc_vblank_put(crtc);
11528 free_work:
11529         kfree(work);
11530
11531         if (ret == -EIO) {
11532                 struct drm_atomic_state *state;
11533                 struct drm_plane_state *plane_state;
11534
11535 out_hang:
11536                 state = drm_atomic_state_alloc(dev);
11537                 if (!state)
11538                         return -ENOMEM;
11539                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11540
11541 retry:
11542                 plane_state = drm_atomic_get_plane_state(state, primary);
11543                 ret = PTR_ERR_OR_ZERO(plane_state);
11544                 if (!ret) {
11545                         drm_atomic_set_fb_for_plane(plane_state, fb);
11546
11547                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11548                         if (!ret)
11549                                 ret = drm_atomic_commit(state);
11550                 }
11551
11552                 if (ret == -EDEADLK) {
11553                         drm_modeset_backoff(state->acquire_ctx);
11554                         drm_atomic_state_clear(state);
11555                         goto retry;
11556                 }
11557
11558                 if (ret)
11559                         drm_atomic_state_free(state);
11560
11561                 if (ret == 0 && event) {
11562                         spin_lock_irq(&dev->event_lock);
11563                         drm_send_vblank_event(dev, pipe, event);
11564                         spin_unlock_irq(&dev->event_lock);
11565                 }
11566         }
11567         return ret;
11568 }
11569
11570
11571 /**
11572  * intel_wm_need_update - Check whether watermarks need updating
11573  * @plane: drm plane
11574  * @state: new plane state
11575  *
11576  * Check current plane state versus the new one to determine whether
11577  * watermarks need to be recalculated.
11578  *
11579  * Returns true or false.
11580  */
11581 static bool intel_wm_need_update(struct drm_plane *plane,
11582                                  struct drm_plane_state *state)
11583 {
11584         /* Update watermarks on tiling changes. */
11585         if (!plane->state->fb || !state->fb ||
11586             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11587             plane->state->rotation != state->rotation)
11588                 return true;
11589
11590         if (plane->state->crtc_w != state->crtc_w)
11591                 return true;
11592
11593         return false;
11594 }
11595
11596 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11597                                     struct drm_plane_state *plane_state)
11598 {
11599         struct drm_crtc *crtc = crtc_state->crtc;
11600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11601         struct drm_plane *plane = plane_state->plane;
11602         struct drm_device *dev = crtc->dev;
11603         struct drm_i915_private *dev_priv = dev->dev_private;
11604         struct intel_plane_state *old_plane_state =
11605                 to_intel_plane_state(plane->state);
11606         int idx = intel_crtc->base.base.id, ret;
11607         int i = drm_plane_index(plane);
11608         bool mode_changed = needs_modeset(crtc_state);
11609         bool was_crtc_enabled = crtc->state->active;
11610         bool is_crtc_enabled = crtc_state->active;
11611
11612         bool turn_off, turn_on, visible, was_visible;
11613         struct drm_framebuffer *fb = plane_state->fb;
11614
11615         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11616             plane->type != DRM_PLANE_TYPE_CURSOR) {
11617                 ret = skl_update_scaler_plane(
11618                         to_intel_crtc_state(crtc_state),
11619                         to_intel_plane_state(plane_state));
11620                 if (ret)
11621                         return ret;
11622         }
11623
11624         /*
11625          * Disabling a plane is always okay; we just need to update
11626          * fb tracking in a special way since cleanup_fb() won't
11627          * get called by the plane helpers.
11628          */
11629         if (old_plane_state->base.fb && !fb)
11630                 intel_crtc->atomic.disabled_planes |= 1 << i;
11631
11632         was_visible = old_plane_state->visible;
11633         visible = to_intel_plane_state(plane_state)->visible;
11634
11635         if (!was_crtc_enabled && WARN_ON(was_visible))
11636                 was_visible = false;
11637
11638         if (!is_crtc_enabled && WARN_ON(visible))
11639                 visible = false;
11640
11641         if (!was_visible && !visible)
11642                 return 0;
11643
11644         turn_off = was_visible && (!visible || mode_changed);
11645         turn_on = visible && (!was_visible || mode_changed);
11646
11647         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11648                          plane->base.id, fb ? fb->base.id : -1);
11649
11650         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11651                          plane->base.id, was_visible, visible,
11652                          turn_off, turn_on, mode_changed);
11653
11654         if (turn_on) {
11655                 intel_crtc->atomic.update_wm_pre = true;
11656                 /* must disable cxsr around plane enable/disable */
11657                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11658                         intel_crtc->atomic.disable_cxsr = true;
11659                         /* to potentially re-enable cxsr */
11660                         intel_crtc->atomic.wait_vblank = true;
11661                         intel_crtc->atomic.update_wm_post = true;
11662                 }
11663         } else if (turn_off) {
11664                 intel_crtc->atomic.update_wm_post = true;
11665                 /* must disable cxsr around plane enable/disable */
11666                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11667                         if (is_crtc_enabled)
11668                                 intel_crtc->atomic.wait_vblank = true;
11669                         intel_crtc->atomic.disable_cxsr = true;
11670                 }
11671         } else if (intel_wm_need_update(plane, plane_state)) {
11672                 intel_crtc->atomic.update_wm_pre = true;
11673         }
11674
11675         if (visible || was_visible)
11676                 intel_crtc->atomic.fb_bits |=
11677                         to_intel_plane(plane)->frontbuffer_bit;
11678
11679         switch (plane->type) {
11680         case DRM_PLANE_TYPE_PRIMARY:
11681                 intel_crtc->atomic.wait_for_flips = true;
11682                 intel_crtc->atomic.pre_disable_primary = turn_off;
11683                 intel_crtc->atomic.post_enable_primary = turn_on;
11684
11685                 if (turn_off) {
11686                         /*
11687                          * FIXME: Actually if we will still have any other
11688                          * plane enabled on the pipe we could let IPS enabled
11689                          * still, but for now lets consider that when we make
11690                          * primary invisible by setting DSPCNTR to 0 on
11691                          * update_primary_plane function IPS needs to be
11692                          * disable.
11693                          */
11694                         intel_crtc->atomic.disable_ips = true;
11695
11696                         intel_crtc->atomic.disable_fbc = true;
11697                 }
11698
11699                 /*
11700                  * FBC does not work on some platforms for rotated
11701                  * planes, so disable it when rotation is not 0 and
11702                  * update it when rotation is set back to 0.
11703                  *
11704                  * FIXME: This is redundant with the fbc update done in
11705                  * the primary plane enable function except that that
11706                  * one is done too late. We eventually need to unify
11707                  * this.
11708                  */
11709
11710                 if (visible &&
11711                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11712                     dev_priv->fbc.crtc == intel_crtc &&
11713                     plane_state->rotation != BIT(DRM_ROTATE_0))
11714                         intel_crtc->atomic.disable_fbc = true;
11715
11716                 /*
11717                  * BDW signals flip done immediately if the plane
11718                  * is disabled, even if the plane enable is already
11719                  * armed to occur at the next vblank :(
11720                  */
11721                 if (turn_on && IS_BROADWELL(dev))
11722                         intel_crtc->atomic.wait_vblank = true;
11723
11724                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11725                 break;
11726         case DRM_PLANE_TYPE_CURSOR:
11727                 break;
11728         case DRM_PLANE_TYPE_OVERLAY:
11729                 if (turn_off && !mode_changed) {
11730                         intel_crtc->atomic.wait_vblank = true;
11731                         intel_crtc->atomic.update_sprite_watermarks |=
11732                                 1 << i;
11733                 }
11734         }
11735         return 0;
11736 }
11737
11738 static bool encoders_cloneable(const struct intel_encoder *a,
11739                                const struct intel_encoder *b)
11740 {
11741         /* masks could be asymmetric, so check both ways */
11742         return a == b || (a->cloneable & (1 << b->type) &&
11743                           b->cloneable & (1 << a->type));
11744 }
11745
11746 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11747                                          struct intel_crtc *crtc,
11748                                          struct intel_encoder *encoder)
11749 {
11750         struct intel_encoder *source_encoder;
11751         struct drm_connector *connector;
11752         struct drm_connector_state *connector_state;
11753         int i;
11754
11755         for_each_connector_in_state(state, connector, connector_state, i) {
11756                 if (connector_state->crtc != &crtc->base)
11757                         continue;
11758
11759                 source_encoder =
11760                         to_intel_encoder(connector_state->best_encoder);
11761                 if (!encoders_cloneable(encoder, source_encoder))
11762                         return false;
11763         }
11764
11765         return true;
11766 }
11767
11768 static bool check_encoder_cloning(struct drm_atomic_state *state,
11769                                   struct intel_crtc *crtc)
11770 {
11771         struct intel_encoder *encoder;
11772         struct drm_connector *connector;
11773         struct drm_connector_state *connector_state;
11774         int i;
11775
11776         for_each_connector_in_state(state, connector, connector_state, i) {
11777                 if (connector_state->crtc != &crtc->base)
11778                         continue;
11779
11780                 encoder = to_intel_encoder(connector_state->best_encoder);
11781                 if (!check_single_encoder_cloning(state, crtc, encoder))
11782                         return false;
11783         }
11784
11785         return true;
11786 }
11787
11788 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11789                                    struct drm_crtc_state *crtc_state)
11790 {
11791         struct drm_device *dev = crtc->dev;
11792         struct drm_i915_private *dev_priv = dev->dev_private;
11793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11794         struct intel_crtc_state *pipe_config =
11795                 to_intel_crtc_state(crtc_state);
11796         struct drm_atomic_state *state = crtc_state->state;
11797         int ret;
11798         bool mode_changed = needs_modeset(crtc_state);
11799
11800         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11801                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11802                 return -EINVAL;
11803         }
11804
11805         if (mode_changed && !crtc_state->active)
11806                 intel_crtc->atomic.update_wm_post = true;
11807
11808         if (mode_changed && crtc_state->enable &&
11809             dev_priv->display.crtc_compute_clock &&
11810             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11811                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11812                                                            pipe_config);
11813                 if (ret)
11814                         return ret;
11815         }
11816
11817         ret = 0;
11818         if (INTEL_INFO(dev)->gen >= 9) {
11819                 if (mode_changed)
11820                         ret = skl_update_scaler_crtc(pipe_config);
11821
11822                 if (!ret)
11823                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11824                                                          pipe_config);
11825         }
11826
11827         return ret;
11828 }
11829
11830 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11831         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11832         .load_lut = intel_crtc_load_lut,
11833         .atomic_begin = intel_begin_crtc_commit,
11834         .atomic_flush = intel_finish_crtc_commit,
11835         .atomic_check = intel_crtc_atomic_check,
11836 };
11837
11838 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11839 {
11840         struct intel_connector *connector;
11841
11842         for_each_intel_connector(dev, connector) {
11843                 if (connector->base.encoder) {
11844                         connector->base.state->best_encoder =
11845                                 connector->base.encoder;
11846                         connector->base.state->crtc =
11847                                 connector->base.encoder->crtc;
11848                 } else {
11849                         connector->base.state->best_encoder = NULL;
11850                         connector->base.state->crtc = NULL;
11851                 }
11852         }
11853 }
11854
11855 static void
11856 connected_sink_compute_bpp(struct intel_connector *connector,
11857                            struct intel_crtc_state *pipe_config)
11858 {
11859         int bpp = pipe_config->pipe_bpp;
11860
11861         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11862                 connector->base.base.id,
11863                 connector->base.name);
11864
11865         /* Don't use an invalid EDID bpc value */
11866         if (connector->base.display_info.bpc &&
11867             connector->base.display_info.bpc * 3 < bpp) {
11868                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11869                               bpp, connector->base.display_info.bpc*3);
11870                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11871         }
11872
11873         /* Clamp bpp to 8 on screens without EDID 1.4 */
11874         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11875                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11876                               bpp);
11877                 pipe_config->pipe_bpp = 24;
11878         }
11879 }
11880
11881 static int
11882 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11883                           struct intel_crtc_state *pipe_config)
11884 {
11885         struct drm_device *dev = crtc->base.dev;
11886         struct drm_atomic_state *state;
11887         struct drm_connector *connector;
11888         struct drm_connector_state *connector_state;
11889         int bpp, i;
11890
11891         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11892                 bpp = 10*3;
11893         else if (INTEL_INFO(dev)->gen >= 5)
11894                 bpp = 12*3;
11895         else
11896                 bpp = 8*3;
11897
11898
11899         pipe_config->pipe_bpp = bpp;
11900
11901         state = pipe_config->base.state;
11902
11903         /* Clamp display bpp to EDID value */
11904         for_each_connector_in_state(state, connector, connector_state, i) {
11905                 if (connector_state->crtc != &crtc->base)
11906                         continue;
11907
11908                 connected_sink_compute_bpp(to_intel_connector(connector),
11909                                            pipe_config);
11910         }
11911
11912         return bpp;
11913 }
11914
11915 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11916 {
11917         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11918                         "type: 0x%x flags: 0x%x\n",
11919                 mode->crtc_clock,
11920                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11921                 mode->crtc_hsync_end, mode->crtc_htotal,
11922                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11923                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11924 }
11925
11926 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11927                                    struct intel_crtc_state *pipe_config,
11928                                    const char *context)
11929 {
11930         struct drm_device *dev = crtc->base.dev;
11931         struct drm_plane *plane;
11932         struct intel_plane *intel_plane;
11933         struct intel_plane_state *state;
11934         struct drm_framebuffer *fb;
11935
11936         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11937                       context, pipe_config, pipe_name(crtc->pipe));
11938
11939         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11940         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11941                       pipe_config->pipe_bpp, pipe_config->dither);
11942         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11943                       pipe_config->has_pch_encoder,
11944                       pipe_config->fdi_lanes,
11945                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11946                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11947                       pipe_config->fdi_m_n.tu);
11948         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11949                       pipe_config->has_dp_encoder,
11950                       pipe_config->lane_count,
11951                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11952                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11953                       pipe_config->dp_m_n.tu);
11954
11955         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11956                       pipe_config->has_dp_encoder,
11957                       pipe_config->lane_count,
11958                       pipe_config->dp_m2_n2.gmch_m,
11959                       pipe_config->dp_m2_n2.gmch_n,
11960                       pipe_config->dp_m2_n2.link_m,
11961                       pipe_config->dp_m2_n2.link_n,
11962                       pipe_config->dp_m2_n2.tu);
11963
11964         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11965                       pipe_config->has_audio,
11966                       pipe_config->has_infoframe);
11967
11968         DRM_DEBUG_KMS("requested mode:\n");
11969         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11970         DRM_DEBUG_KMS("adjusted mode:\n");
11971         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11972         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11973         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11974         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11975                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11976         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11977                       crtc->num_scalers,
11978                       pipe_config->scaler_state.scaler_users,
11979                       pipe_config->scaler_state.scaler_id);
11980         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11981                       pipe_config->gmch_pfit.control,
11982                       pipe_config->gmch_pfit.pgm_ratios,
11983                       pipe_config->gmch_pfit.lvds_border_bits);
11984         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11985                       pipe_config->pch_pfit.pos,
11986                       pipe_config->pch_pfit.size,
11987                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11988         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11989         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11990
11991         if (IS_BROXTON(dev)) {
11992                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11993                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11994                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11995                               pipe_config->ddi_pll_sel,
11996                               pipe_config->dpll_hw_state.ebb0,
11997                               pipe_config->dpll_hw_state.ebb4,
11998                               pipe_config->dpll_hw_state.pll0,
11999                               pipe_config->dpll_hw_state.pll1,
12000                               pipe_config->dpll_hw_state.pll2,
12001                               pipe_config->dpll_hw_state.pll3,
12002                               pipe_config->dpll_hw_state.pll6,
12003                               pipe_config->dpll_hw_state.pll8,
12004                               pipe_config->dpll_hw_state.pll9,
12005                               pipe_config->dpll_hw_state.pll10,
12006                               pipe_config->dpll_hw_state.pcsdw12);
12007         } else if (IS_SKYLAKE(dev)) {
12008                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12009                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12010                               pipe_config->ddi_pll_sel,
12011                               pipe_config->dpll_hw_state.ctrl1,
12012                               pipe_config->dpll_hw_state.cfgcr1,
12013                               pipe_config->dpll_hw_state.cfgcr2);
12014         } else if (HAS_DDI(dev)) {
12015                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12016                               pipe_config->ddi_pll_sel,
12017                               pipe_config->dpll_hw_state.wrpll);
12018         } else {
12019                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12020                               "fp0: 0x%x, fp1: 0x%x\n",
12021                               pipe_config->dpll_hw_state.dpll,
12022                               pipe_config->dpll_hw_state.dpll_md,
12023                               pipe_config->dpll_hw_state.fp0,
12024                               pipe_config->dpll_hw_state.fp1);
12025         }
12026
12027         DRM_DEBUG_KMS("planes on this crtc\n");
12028         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12029                 intel_plane = to_intel_plane(plane);
12030                 if (intel_plane->pipe != crtc->pipe)
12031                         continue;
12032
12033                 state = to_intel_plane_state(plane->state);
12034                 fb = state->base.fb;
12035                 if (!fb) {
12036                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12037                                 "disabled, scaler_id = %d\n",
12038                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12039                                 plane->base.id, intel_plane->pipe,
12040                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12041                                 drm_plane_index(plane), state->scaler_id);
12042                         continue;
12043                 }
12044
12045                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12046                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12047                         plane->base.id, intel_plane->pipe,
12048                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12049                         drm_plane_index(plane));
12050                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12051                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12052                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12053                         state->scaler_id,
12054                         state->src.x1 >> 16, state->src.y1 >> 16,
12055                         drm_rect_width(&state->src) >> 16,
12056                         drm_rect_height(&state->src) >> 16,
12057                         state->dst.x1, state->dst.y1,
12058                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12059         }
12060 }
12061
12062 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12063 {
12064         struct drm_device *dev = state->dev;
12065         struct intel_encoder *encoder;
12066         struct drm_connector *connector;
12067         struct drm_connector_state *connector_state;
12068         unsigned int used_ports = 0;
12069         int i;
12070
12071         /*
12072          * Walk the connector list instead of the encoder
12073          * list to detect the problem on ddi platforms
12074          * where there's just one encoder per digital port.
12075          */
12076         for_each_connector_in_state(state, connector, connector_state, i) {
12077                 if (!connector_state->best_encoder)
12078                         continue;
12079
12080                 encoder = to_intel_encoder(connector_state->best_encoder);
12081
12082                 WARN_ON(!connector_state->crtc);
12083
12084                 switch (encoder->type) {
12085                         unsigned int port_mask;
12086                 case INTEL_OUTPUT_UNKNOWN:
12087                         if (WARN_ON(!HAS_DDI(dev)))
12088                                 break;
12089                 case INTEL_OUTPUT_DISPLAYPORT:
12090                 case INTEL_OUTPUT_HDMI:
12091                 case INTEL_OUTPUT_EDP:
12092                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12093
12094                         /* the same port mustn't appear more than once */
12095                         if (used_ports & port_mask)
12096                                 return false;
12097
12098                         used_ports |= port_mask;
12099                 default:
12100                         break;
12101                 }
12102         }
12103
12104         return true;
12105 }
12106
12107 static void
12108 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12109 {
12110         struct drm_crtc_state tmp_state;
12111         struct intel_crtc_scaler_state scaler_state;
12112         struct intel_dpll_hw_state dpll_hw_state;
12113         enum intel_dpll_id shared_dpll;
12114         uint32_t ddi_pll_sel;
12115         bool force_thru;
12116
12117         /* FIXME: before the switch to atomic started, a new pipe_config was
12118          * kzalloc'd. Code that depends on any field being zero should be
12119          * fixed, so that the crtc_state can be safely duplicated. For now,
12120          * only fields that are know to not cause problems are preserved. */
12121
12122         tmp_state = crtc_state->base;
12123         scaler_state = crtc_state->scaler_state;
12124         shared_dpll = crtc_state->shared_dpll;
12125         dpll_hw_state = crtc_state->dpll_hw_state;
12126         ddi_pll_sel = crtc_state->ddi_pll_sel;
12127         force_thru = crtc_state->pch_pfit.force_thru;
12128
12129         memset(crtc_state, 0, sizeof *crtc_state);
12130
12131         crtc_state->base = tmp_state;
12132         crtc_state->scaler_state = scaler_state;
12133         crtc_state->shared_dpll = shared_dpll;
12134         crtc_state->dpll_hw_state = dpll_hw_state;
12135         crtc_state->ddi_pll_sel = ddi_pll_sel;
12136         crtc_state->pch_pfit.force_thru = force_thru;
12137 }
12138
12139 static int
12140 intel_modeset_pipe_config(struct drm_crtc *crtc,
12141                           struct intel_crtc_state *pipe_config)
12142 {
12143         struct drm_atomic_state *state = pipe_config->base.state;
12144         struct intel_encoder *encoder;
12145         struct drm_connector *connector;
12146         struct drm_connector_state *connector_state;
12147         int base_bpp, ret = -EINVAL;
12148         int i;
12149         bool retry = true;
12150
12151         clear_intel_crtc_state(pipe_config);
12152
12153         pipe_config->cpu_transcoder =
12154                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12155
12156         /*
12157          * Sanitize sync polarity flags based on requested ones. If neither
12158          * positive or negative polarity is requested, treat this as meaning
12159          * negative polarity.
12160          */
12161         if (!(pipe_config->base.adjusted_mode.flags &
12162               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12163                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12164
12165         if (!(pipe_config->base.adjusted_mode.flags &
12166               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12167                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12168
12169         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12170                                              pipe_config);
12171         if (base_bpp < 0)
12172                 goto fail;
12173
12174         /*
12175          * Determine the real pipe dimensions. Note that stereo modes can
12176          * increase the actual pipe size due to the frame doubling and
12177          * insertion of additional space for blanks between the frame. This
12178          * is stored in the crtc timings. We use the requested mode to do this
12179          * computation to clearly distinguish it from the adjusted mode, which
12180          * can be changed by the connectors in the below retry loop.
12181          */
12182         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12183                                &pipe_config->pipe_src_w,
12184                                &pipe_config->pipe_src_h);
12185
12186 encoder_retry:
12187         /* Ensure the port clock defaults are reset when retrying. */
12188         pipe_config->port_clock = 0;
12189         pipe_config->pixel_multiplier = 1;
12190
12191         /* Fill in default crtc timings, allow encoders to overwrite them. */
12192         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12193                               CRTC_STEREO_DOUBLE);
12194
12195         /* Pass our mode to the connectors and the CRTC to give them a chance to
12196          * adjust it according to limitations or connector properties, and also
12197          * a chance to reject the mode entirely.
12198          */
12199         for_each_connector_in_state(state, connector, connector_state, i) {
12200                 if (connector_state->crtc != crtc)
12201                         continue;
12202
12203                 encoder = to_intel_encoder(connector_state->best_encoder);
12204
12205                 if (!(encoder->compute_config(encoder, pipe_config))) {
12206                         DRM_DEBUG_KMS("Encoder config failure\n");
12207                         goto fail;
12208                 }
12209         }
12210
12211         /* Set default port clock if not overwritten by the encoder. Needs to be
12212          * done afterwards in case the encoder adjusts the mode. */
12213         if (!pipe_config->port_clock)
12214                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12215                         * pipe_config->pixel_multiplier;
12216
12217         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12218         if (ret < 0) {
12219                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12220                 goto fail;
12221         }
12222
12223         if (ret == RETRY) {
12224                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12225                         ret = -EINVAL;
12226                         goto fail;
12227                 }
12228
12229                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12230                 retry = false;
12231                 goto encoder_retry;
12232         }
12233
12234         /* Dithering seems to not pass-through bits correctly when it should, so
12235          * only enable it on 6bpc panels. */
12236         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12237         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12238                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12239
12240 fail:
12241         return ret;
12242 }
12243
12244 static void
12245 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12246 {
12247         struct drm_crtc *crtc;
12248         struct drm_crtc_state *crtc_state;
12249         int i;
12250
12251         /* Double check state. */
12252         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12253                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12254
12255                 /* Update hwmode for vblank functions */
12256                 if (crtc->state->active)
12257                         crtc->hwmode = crtc->state->adjusted_mode;
12258                 else
12259                         crtc->hwmode.crtc_clock = 0;
12260         }
12261 }
12262
12263 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12264 {
12265         int diff;
12266
12267         if (clock1 == clock2)
12268                 return true;
12269
12270         if (!clock1 || !clock2)
12271                 return false;
12272
12273         diff = abs(clock1 - clock2);
12274
12275         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12276                 return true;
12277
12278         return false;
12279 }
12280
12281 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12282         list_for_each_entry((intel_crtc), \
12283                             &(dev)->mode_config.crtc_list, \
12284                             base.head) \
12285                 if (mask & (1 <<(intel_crtc)->pipe))
12286
12287 static bool
12288 intel_compare_m_n(unsigned int m, unsigned int n,
12289                   unsigned int m2, unsigned int n2,
12290                   bool exact)
12291 {
12292         if (m == m2 && n == n2)
12293                 return true;
12294
12295         if (exact || !m || !n || !m2 || !n2)
12296                 return false;
12297
12298         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12299
12300         if (m > m2) {
12301                 while (m > m2) {
12302                         m2 <<= 1;
12303                         n2 <<= 1;
12304                 }
12305         } else if (m < m2) {
12306                 while (m < m2) {
12307                         m <<= 1;
12308                         n <<= 1;
12309                 }
12310         }
12311
12312         return m == m2 && n == n2;
12313 }
12314
12315 static bool
12316 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12317                        struct intel_link_m_n *m2_n2,
12318                        bool adjust)
12319 {
12320         if (m_n->tu == m2_n2->tu &&
12321             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12322                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12323             intel_compare_m_n(m_n->link_m, m_n->link_n,
12324                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12325                 if (adjust)
12326                         *m2_n2 = *m_n;
12327
12328                 return true;
12329         }
12330
12331         return false;
12332 }
12333
12334 static bool
12335 intel_pipe_config_compare(struct drm_device *dev,
12336                           struct intel_crtc_state *current_config,
12337                           struct intel_crtc_state *pipe_config,
12338                           bool adjust)
12339 {
12340         bool ret = true;
12341
12342 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12343         do { \
12344                 if (!adjust) \
12345                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12346                 else \
12347                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12348         } while (0)
12349
12350 #define PIPE_CONF_CHECK_X(name) \
12351         if (current_config->name != pipe_config->name) { \
12352                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353                           "(expected 0x%08x, found 0x%08x)\n", \
12354                           current_config->name, \
12355                           pipe_config->name); \
12356                 ret = false; \
12357         }
12358
12359 #define PIPE_CONF_CHECK_I(name) \
12360         if (current_config->name != pipe_config->name) { \
12361                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12362                           "(expected %i, found %i)\n", \
12363                           current_config->name, \
12364                           pipe_config->name); \
12365                 ret = false; \
12366         }
12367
12368 #define PIPE_CONF_CHECK_M_N(name) \
12369         if (!intel_compare_link_m_n(&current_config->name, \
12370                                     &pipe_config->name,\
12371                                     adjust)) { \
12372                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12373                           "(expected tu %i gmch %i/%i link %i/%i, " \
12374                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12375                           current_config->name.tu, \
12376                           current_config->name.gmch_m, \
12377                           current_config->name.gmch_n, \
12378                           current_config->name.link_m, \
12379                           current_config->name.link_n, \
12380                           pipe_config->name.tu, \
12381                           pipe_config->name.gmch_m, \
12382                           pipe_config->name.gmch_n, \
12383                           pipe_config->name.link_m, \
12384                           pipe_config->name.link_n); \
12385                 ret = false; \
12386         }
12387
12388 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12389         if (!intel_compare_link_m_n(&current_config->name, \
12390                                     &pipe_config->name, adjust) && \
12391             !intel_compare_link_m_n(&current_config->alt_name, \
12392                                     &pipe_config->name, adjust)) { \
12393                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12394                           "(expected tu %i gmch %i/%i link %i/%i, " \
12395                           "or tu %i gmch %i/%i link %i/%i, " \
12396                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12397                           current_config->name.tu, \
12398                           current_config->name.gmch_m, \
12399                           current_config->name.gmch_n, \
12400                           current_config->name.link_m, \
12401                           current_config->name.link_n, \
12402                           current_config->alt_name.tu, \
12403                           current_config->alt_name.gmch_m, \
12404                           current_config->alt_name.gmch_n, \
12405                           current_config->alt_name.link_m, \
12406                           current_config->alt_name.link_n, \
12407                           pipe_config->name.tu, \
12408                           pipe_config->name.gmch_m, \
12409                           pipe_config->name.gmch_n, \
12410                           pipe_config->name.link_m, \
12411                           pipe_config->name.link_n); \
12412                 ret = false; \
12413         }
12414
12415 /* This is required for BDW+ where there is only one set of registers for
12416  * switching between high and low RR.
12417  * This macro can be used whenever a comparison has to be made between one
12418  * hw state and multiple sw state variables.
12419  */
12420 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12421         if ((current_config->name != pipe_config->name) && \
12422                 (current_config->alt_name != pipe_config->name)) { \
12423                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12424                                   "(expected %i or %i, found %i)\n", \
12425                                   current_config->name, \
12426                                   current_config->alt_name, \
12427                                   pipe_config->name); \
12428                         ret = false; \
12429         }
12430
12431 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12432         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12433                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12434                           "(expected %i, found %i)\n", \
12435                           current_config->name & (mask), \
12436                           pipe_config->name & (mask)); \
12437                 ret = false; \
12438         }
12439
12440 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12441         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12442                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12443                           "(expected %i, found %i)\n", \
12444                           current_config->name, \
12445                           pipe_config->name); \
12446                 ret = false; \
12447         }
12448
12449 #define PIPE_CONF_QUIRK(quirk)  \
12450         ((current_config->quirks | pipe_config->quirks) & (quirk))
12451
12452         PIPE_CONF_CHECK_I(cpu_transcoder);
12453
12454         PIPE_CONF_CHECK_I(has_pch_encoder);
12455         PIPE_CONF_CHECK_I(fdi_lanes);
12456         PIPE_CONF_CHECK_M_N(fdi_m_n);
12457
12458         PIPE_CONF_CHECK_I(has_dp_encoder);
12459         PIPE_CONF_CHECK_I(lane_count);
12460
12461         if (INTEL_INFO(dev)->gen < 8) {
12462                 PIPE_CONF_CHECK_M_N(dp_m_n);
12463
12464                 PIPE_CONF_CHECK_I(has_drrs);
12465                 if (current_config->has_drrs)
12466                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12467         } else
12468                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12469
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12474         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12475         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12476
12477         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12478         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12479         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12480         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12481         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12482         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12483
12484         PIPE_CONF_CHECK_I(pixel_multiplier);
12485         PIPE_CONF_CHECK_I(has_hdmi_sink);
12486         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12487             IS_VALLEYVIEW(dev))
12488                 PIPE_CONF_CHECK_I(limited_color_range);
12489         PIPE_CONF_CHECK_I(has_infoframe);
12490
12491         PIPE_CONF_CHECK_I(has_audio);
12492
12493         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12494                               DRM_MODE_FLAG_INTERLACE);
12495
12496         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12497                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12498                                       DRM_MODE_FLAG_PHSYNC);
12499                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12500                                       DRM_MODE_FLAG_NHSYNC);
12501                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502                                       DRM_MODE_FLAG_PVSYNC);
12503                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12504                                       DRM_MODE_FLAG_NVSYNC);
12505         }
12506
12507         PIPE_CONF_CHECK_X(gmch_pfit.control);
12508         /* pfit ratios are autocomputed by the hw on gen4+ */
12509         if (INTEL_INFO(dev)->gen < 4)
12510                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12511         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12512
12513         if (!adjust) {
12514                 PIPE_CONF_CHECK_I(pipe_src_w);
12515                 PIPE_CONF_CHECK_I(pipe_src_h);
12516
12517                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12518                 if (current_config->pch_pfit.enabled) {
12519                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12520                         PIPE_CONF_CHECK_X(pch_pfit.size);
12521                 }
12522
12523                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12524         }
12525
12526         /* BDW+ don't expose a synchronous way to read the state */
12527         if (IS_HASWELL(dev))
12528                 PIPE_CONF_CHECK_I(ips_enabled);
12529
12530         PIPE_CONF_CHECK_I(double_wide);
12531
12532         PIPE_CONF_CHECK_X(ddi_pll_sel);
12533
12534         PIPE_CONF_CHECK_I(shared_dpll);
12535         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12536         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12537         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12538         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12539         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12540         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12541         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12542         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12543
12544         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12545                 PIPE_CONF_CHECK_I(pipe_bpp);
12546
12547         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12548         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12549
12550 #undef PIPE_CONF_CHECK_X
12551 #undef PIPE_CONF_CHECK_I
12552 #undef PIPE_CONF_CHECK_I_ALT
12553 #undef PIPE_CONF_CHECK_FLAGS
12554 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12555 #undef PIPE_CONF_QUIRK
12556 #undef INTEL_ERR_OR_DBG_KMS
12557
12558         return ret;
12559 }
12560
12561 static void check_wm_state(struct drm_device *dev)
12562 {
12563         struct drm_i915_private *dev_priv = dev->dev_private;
12564         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12565         struct intel_crtc *intel_crtc;
12566         int plane;
12567
12568         if (INTEL_INFO(dev)->gen < 9)
12569                 return;
12570
12571         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12572         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12573
12574         for_each_intel_crtc(dev, intel_crtc) {
12575                 struct skl_ddb_entry *hw_entry, *sw_entry;
12576                 const enum pipe pipe = intel_crtc->pipe;
12577
12578                 if (!intel_crtc->active)
12579                         continue;
12580
12581                 /* planes */
12582                 for_each_plane(dev_priv, pipe, plane) {
12583                         hw_entry = &hw_ddb.plane[pipe][plane];
12584                         sw_entry = &sw_ddb->plane[pipe][plane];
12585
12586                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12587                                 continue;
12588
12589                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12590                                   "(expected (%u,%u), found (%u,%u))\n",
12591                                   pipe_name(pipe), plane + 1,
12592                                   sw_entry->start, sw_entry->end,
12593                                   hw_entry->start, hw_entry->end);
12594                 }
12595
12596                 /* cursor */
12597                 hw_entry = &hw_ddb.cursor[pipe];
12598                 sw_entry = &sw_ddb->cursor[pipe];
12599
12600                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12601                         continue;
12602
12603                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12604                           "(expected (%u,%u), found (%u,%u))\n",
12605                           pipe_name(pipe),
12606                           sw_entry->start, sw_entry->end,
12607                           hw_entry->start, hw_entry->end);
12608         }
12609 }
12610
12611 static void
12612 check_connector_state(struct drm_device *dev,
12613                       struct drm_atomic_state *old_state)
12614 {
12615         struct drm_connector_state *old_conn_state;
12616         struct drm_connector *connector;
12617         int i;
12618
12619         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12620                 struct drm_encoder *encoder = connector->encoder;
12621                 struct drm_connector_state *state = connector->state;
12622
12623                 /* This also checks the encoder/connector hw state with the
12624                  * ->get_hw_state callbacks. */
12625                 intel_connector_check_state(to_intel_connector(connector));
12626
12627                 I915_STATE_WARN(state->best_encoder != encoder,
12628                      "connector's atomic encoder doesn't match legacy encoder\n");
12629         }
12630 }
12631
12632 static void
12633 check_encoder_state(struct drm_device *dev)
12634 {
12635         struct intel_encoder *encoder;
12636         struct intel_connector *connector;
12637
12638         for_each_intel_encoder(dev, encoder) {
12639                 bool enabled = false;
12640                 enum pipe pipe;
12641
12642                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12643                               encoder->base.base.id,
12644                               encoder->base.name);
12645
12646                 for_each_intel_connector(dev, connector) {
12647                         if (connector->base.state->best_encoder != &encoder->base)
12648                                 continue;
12649                         enabled = true;
12650
12651                         I915_STATE_WARN(connector->base.state->crtc !=
12652                                         encoder->base.crtc,
12653                              "connector's crtc doesn't match encoder crtc\n");
12654                 }
12655
12656                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12657                      "encoder's enabled state mismatch "
12658                      "(expected %i, found %i)\n",
12659                      !!encoder->base.crtc, enabled);
12660
12661                 if (!encoder->base.crtc) {
12662                         bool active;
12663
12664                         active = encoder->get_hw_state(encoder, &pipe);
12665                         I915_STATE_WARN(active,
12666                              "encoder detached but still enabled on pipe %c.\n",
12667                              pipe_name(pipe));
12668                 }
12669         }
12670 }
12671
12672 static void
12673 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12674 {
12675         struct drm_i915_private *dev_priv = dev->dev_private;
12676         struct intel_encoder *encoder;
12677         struct drm_crtc_state *old_crtc_state;
12678         struct drm_crtc *crtc;
12679         int i;
12680
12681         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12682                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12683                 struct intel_crtc_state *pipe_config, *sw_config;
12684                 bool active;
12685
12686                 if (!needs_modeset(crtc->state) &&
12687                     !to_intel_crtc_state(crtc->state)->update_pipe)
12688                         continue;
12689
12690                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12691                 pipe_config = to_intel_crtc_state(old_crtc_state);
12692                 memset(pipe_config, 0, sizeof(*pipe_config));
12693                 pipe_config->base.crtc = crtc;
12694                 pipe_config->base.state = old_state;
12695
12696                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12697                               crtc->base.id);
12698
12699                 active = dev_priv->display.get_pipe_config(intel_crtc,
12700                                                            pipe_config);
12701
12702                 /* hw state is inconsistent with the pipe quirk */
12703                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12704                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12705                         active = crtc->state->active;
12706
12707                 I915_STATE_WARN(crtc->state->active != active,
12708                      "crtc active state doesn't match with hw state "
12709                      "(expected %i, found %i)\n", crtc->state->active, active);
12710
12711                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12712                      "transitional active state does not match atomic hw state "
12713                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12714
12715                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12716                         enum pipe pipe;
12717
12718                         active = encoder->get_hw_state(encoder, &pipe);
12719                         I915_STATE_WARN(active != crtc->state->active,
12720                                 "[ENCODER:%i] active %i with crtc active %i\n",
12721                                 encoder->base.base.id, active, crtc->state->active);
12722
12723                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12724                                         "Encoder connected to wrong pipe %c\n",
12725                                         pipe_name(pipe));
12726
12727                         if (active)
12728                                 encoder->get_config(encoder, pipe_config);
12729                 }
12730
12731                 if (!crtc->state->active)
12732                         continue;
12733
12734                 sw_config = to_intel_crtc_state(crtc->state);
12735                 if (!intel_pipe_config_compare(dev, sw_config,
12736                                                pipe_config, false)) {
12737                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12738                         intel_dump_pipe_config(intel_crtc, pipe_config,
12739                                                "[hw state]");
12740                         intel_dump_pipe_config(intel_crtc, sw_config,
12741                                                "[sw state]");
12742                 }
12743         }
12744 }
12745
12746 static void
12747 check_shared_dpll_state(struct drm_device *dev)
12748 {
12749         struct drm_i915_private *dev_priv = dev->dev_private;
12750         struct intel_crtc *crtc;
12751         struct intel_dpll_hw_state dpll_hw_state;
12752         int i;
12753
12754         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12755                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12756                 int enabled_crtcs = 0, active_crtcs = 0;
12757                 bool active;
12758
12759                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12760
12761                 DRM_DEBUG_KMS("%s\n", pll->name);
12762
12763                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12764
12765                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12766                      "more active pll users than references: %i vs %i\n",
12767                      pll->active, hweight32(pll->config.crtc_mask));
12768                 I915_STATE_WARN(pll->active && !pll->on,
12769                      "pll in active use but not on in sw tracking\n");
12770                 I915_STATE_WARN(pll->on && !pll->active,
12771                      "pll in on but not on in use in sw tracking\n");
12772                 I915_STATE_WARN(pll->on != active,
12773                      "pll on state mismatch (expected %i, found %i)\n",
12774                      pll->on, active);
12775
12776                 for_each_intel_crtc(dev, crtc) {
12777                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12778                                 enabled_crtcs++;
12779                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12780                                 active_crtcs++;
12781                 }
12782                 I915_STATE_WARN(pll->active != active_crtcs,
12783                      "pll active crtcs mismatch (expected %i, found %i)\n",
12784                      pll->active, active_crtcs);
12785                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12786                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12787                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12788
12789                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12790                                        sizeof(dpll_hw_state)),
12791                      "pll hw state mismatch\n");
12792         }
12793 }
12794
12795 static void
12796 intel_modeset_check_state(struct drm_device *dev,
12797                           struct drm_atomic_state *old_state)
12798 {
12799         check_wm_state(dev);
12800         check_connector_state(dev, old_state);
12801         check_encoder_state(dev);
12802         check_crtc_state(dev, old_state);
12803         check_shared_dpll_state(dev);
12804 }
12805
12806 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12807                                      int dotclock)
12808 {
12809         /*
12810          * FDI already provided one idea for the dotclock.
12811          * Yell if the encoder disagrees.
12812          */
12813         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12814              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12815              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12816 }
12817
12818 static void update_scanline_offset(struct intel_crtc *crtc)
12819 {
12820         struct drm_device *dev = crtc->base.dev;
12821
12822         /*
12823          * The scanline counter increments at the leading edge of hsync.
12824          *
12825          * On most platforms it starts counting from vtotal-1 on the
12826          * first active line. That means the scanline counter value is
12827          * always one less than what we would expect. Ie. just after
12828          * start of vblank, which also occurs at start of hsync (on the
12829          * last active line), the scanline counter will read vblank_start-1.
12830          *
12831          * On gen2 the scanline counter starts counting from 1 instead
12832          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12833          * to keep the value positive), instead of adding one.
12834          *
12835          * On HSW+ the behaviour of the scanline counter depends on the output
12836          * type. For DP ports it behaves like most other platforms, but on HDMI
12837          * there's an extra 1 line difference. So we need to add two instead of
12838          * one to the value.
12839          */
12840         if (IS_GEN2(dev)) {
12841                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12842                 int vtotal;
12843
12844                 vtotal = adjusted_mode->crtc_vtotal;
12845                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12846                         vtotal /= 2;
12847
12848                 crtc->scanline_offset = vtotal - 1;
12849         } else if (HAS_DDI(dev) &&
12850                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12851                 crtc->scanline_offset = 2;
12852         } else
12853                 crtc->scanline_offset = 1;
12854 }
12855
12856 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12857 {
12858         struct drm_device *dev = state->dev;
12859         struct drm_i915_private *dev_priv = to_i915(dev);
12860         struct intel_shared_dpll_config *shared_dpll = NULL;
12861         struct intel_crtc *intel_crtc;
12862         struct intel_crtc_state *intel_crtc_state;
12863         struct drm_crtc *crtc;
12864         struct drm_crtc_state *crtc_state;
12865         int i;
12866
12867         if (!dev_priv->display.crtc_compute_clock)
12868                 return;
12869
12870         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12871                 int dpll;
12872
12873                 intel_crtc = to_intel_crtc(crtc);
12874                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12875                 dpll = intel_crtc_state->shared_dpll;
12876
12877                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12878                         continue;
12879
12880                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12881
12882                 if (!shared_dpll)
12883                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12884
12885                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12886         }
12887 }
12888
12889 /*
12890  * This implements the workaround described in the "notes" section of the mode
12891  * set sequence documentation. When going from no pipes or single pipe to
12892  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12893  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12894  */
12895 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12896 {
12897         struct drm_crtc_state *crtc_state;
12898         struct intel_crtc *intel_crtc;
12899         struct drm_crtc *crtc;
12900         struct intel_crtc_state *first_crtc_state = NULL;
12901         struct intel_crtc_state *other_crtc_state = NULL;
12902         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12903         int i;
12904
12905         /* look at all crtc's that are going to be enabled in during modeset */
12906         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12907                 intel_crtc = to_intel_crtc(crtc);
12908
12909                 if (!crtc_state->active || !needs_modeset(crtc_state))
12910                         continue;
12911
12912                 if (first_crtc_state) {
12913                         other_crtc_state = to_intel_crtc_state(crtc_state);
12914                         break;
12915                 } else {
12916                         first_crtc_state = to_intel_crtc_state(crtc_state);
12917                         first_pipe = intel_crtc->pipe;
12918                 }
12919         }
12920
12921         /* No workaround needed? */
12922         if (!first_crtc_state)
12923                 return 0;
12924
12925         /* w/a possibly needed, check how many crtc's are already enabled. */
12926         for_each_intel_crtc(state->dev, intel_crtc) {
12927                 struct intel_crtc_state *pipe_config;
12928
12929                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12930                 if (IS_ERR(pipe_config))
12931                         return PTR_ERR(pipe_config);
12932
12933                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12934
12935                 if (!pipe_config->base.active ||
12936                     needs_modeset(&pipe_config->base))
12937                         continue;
12938
12939                 /* 2 or more enabled crtcs means no need for w/a */
12940                 if (enabled_pipe != INVALID_PIPE)
12941                         return 0;
12942
12943                 enabled_pipe = intel_crtc->pipe;
12944         }
12945
12946         if (enabled_pipe != INVALID_PIPE)
12947                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12948         else if (other_crtc_state)
12949                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12950
12951         return 0;
12952 }
12953
12954 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12955 {
12956         struct drm_crtc *crtc;
12957         struct drm_crtc_state *crtc_state;
12958         int ret = 0;
12959
12960         /* add all active pipes to the state */
12961         for_each_crtc(state->dev, crtc) {
12962                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12963                 if (IS_ERR(crtc_state))
12964                         return PTR_ERR(crtc_state);
12965
12966                 if (!crtc_state->active || needs_modeset(crtc_state))
12967                         continue;
12968
12969                 crtc_state->mode_changed = true;
12970
12971                 ret = drm_atomic_add_affected_connectors(state, crtc);
12972                 if (ret)
12973                         break;
12974
12975                 ret = drm_atomic_add_affected_planes(state, crtc);
12976                 if (ret)
12977                         break;
12978         }
12979
12980         return ret;
12981 }
12982
12983 static int intel_modeset_checks(struct drm_atomic_state *state)
12984 {
12985         struct drm_device *dev = state->dev;
12986         struct drm_i915_private *dev_priv = dev->dev_private;
12987         int ret;
12988
12989         if (!check_digital_port_conflicts(state)) {
12990                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12991                 return -EINVAL;
12992         }
12993
12994         /*
12995          * See if the config requires any additional preparation, e.g.
12996          * to adjust global state with pipes off.  We need to do this
12997          * here so we can get the modeset_pipe updated config for the new
12998          * mode set on this crtc.  For other crtcs we need to use the
12999          * adjusted_mode bits in the crtc directly.
13000          */
13001         if (dev_priv->display.modeset_calc_cdclk) {
13002                 unsigned int cdclk;
13003
13004                 ret = dev_priv->display.modeset_calc_cdclk(state);
13005
13006                 cdclk = to_intel_atomic_state(state)->cdclk;
13007                 if (!ret && cdclk != dev_priv->cdclk_freq)
13008                         ret = intel_modeset_all_pipes(state);
13009
13010                 if (ret < 0)
13011                         return ret;
13012         } else
13013                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13014
13015         intel_modeset_clear_plls(state);
13016
13017         if (IS_HASWELL(dev))
13018                 return haswell_mode_set_planes_workaround(state);
13019
13020         return 0;
13021 }
13022
13023 /**
13024  * intel_atomic_check - validate state object
13025  * @dev: drm device
13026  * @state: state to validate
13027  */
13028 static int intel_atomic_check(struct drm_device *dev,
13029                               struct drm_atomic_state *state)
13030 {
13031         struct drm_crtc *crtc;
13032         struct drm_crtc_state *crtc_state;
13033         int ret, i;
13034         bool any_ms = false;
13035
13036         ret = drm_atomic_helper_check_modeset(dev, state);
13037         if (ret)
13038                 return ret;
13039
13040         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13041                 struct intel_crtc_state *pipe_config =
13042                         to_intel_crtc_state(crtc_state);
13043
13044                 /* Catch I915_MODE_FLAG_INHERITED */
13045                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13046                         crtc_state->mode_changed = true;
13047
13048                 if (!crtc_state->enable) {
13049                         if (needs_modeset(crtc_state))
13050                                 any_ms = true;
13051                         continue;
13052                 }
13053
13054                 if (!needs_modeset(crtc_state))
13055                         continue;
13056
13057                 /* FIXME: For only active_changed we shouldn't need to do any
13058                  * state recomputation at all. */
13059
13060                 ret = drm_atomic_add_affected_connectors(state, crtc);
13061                 if (ret)
13062                         return ret;
13063
13064                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13065                 if (ret)
13066                         return ret;
13067
13068                 if (intel_pipe_config_compare(state->dev,
13069                                         to_intel_crtc_state(crtc->state),
13070                                         pipe_config, true)) {
13071                         crtc_state->mode_changed = false;
13072                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13073                 }
13074
13075                 if (needs_modeset(crtc_state)) {
13076                         any_ms = true;
13077
13078                         ret = drm_atomic_add_affected_planes(state, crtc);
13079                         if (ret)
13080                                 return ret;
13081                 }
13082
13083                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13084                                        needs_modeset(crtc_state) ?
13085                                        "[modeset]" : "[fastset]");
13086         }
13087
13088         if (any_ms) {
13089                 ret = intel_modeset_checks(state);
13090
13091                 if (ret)
13092                         return ret;
13093         } else
13094                 to_intel_atomic_state(state)->cdclk =
13095                         to_i915(state->dev)->cdclk_freq;
13096
13097         return drm_atomic_helper_check_planes(state->dev, state);
13098 }
13099
13100 /**
13101  * intel_atomic_commit - commit validated state object
13102  * @dev: DRM device
13103  * @state: the top-level driver state object
13104  * @async: asynchronous commit
13105  *
13106  * This function commits a top-level state object that has been validated
13107  * with drm_atomic_helper_check().
13108  *
13109  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13110  * we can only handle plane-related operations and do not yet support
13111  * asynchronous commit.
13112  *
13113  * RETURNS
13114  * Zero for success or -errno.
13115  */
13116 static int intel_atomic_commit(struct drm_device *dev,
13117                                struct drm_atomic_state *state,
13118                                bool async)
13119 {
13120         struct drm_i915_private *dev_priv = dev->dev_private;
13121         struct drm_crtc *crtc;
13122         struct drm_crtc_state *crtc_state;
13123         int ret = 0;
13124         int i;
13125         bool any_ms = false;
13126
13127         if (async) {
13128                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13129                 return -EINVAL;
13130         }
13131
13132         ret = drm_atomic_helper_prepare_planes(dev, state);
13133         if (ret)
13134                 return ret;
13135
13136         drm_atomic_helper_swap_state(dev, state);
13137
13138         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13140
13141                 if (!needs_modeset(crtc->state))
13142                         continue;
13143
13144                 any_ms = true;
13145                 intel_pre_plane_update(intel_crtc);
13146
13147                 if (crtc_state->active) {
13148                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13149                         dev_priv->display.crtc_disable(crtc);
13150                         intel_crtc->active = false;
13151                         intel_disable_shared_dpll(intel_crtc);
13152                 }
13153         }
13154
13155         /* Only after disabling all output pipelines that will be changed can we
13156          * update the the output configuration. */
13157         intel_modeset_update_crtc_state(state);
13158
13159         if (any_ms) {
13160                 intel_shared_dpll_commit(state);
13161
13162                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13163                 modeset_update_crtc_power_domains(state);
13164         }
13165
13166         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13167         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13168                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13169                 bool modeset = needs_modeset(crtc->state);
13170                 bool update_pipe = !modeset &&
13171                         to_intel_crtc_state(crtc->state)->update_pipe;
13172                 unsigned long put_domains = 0;
13173
13174                 if (modeset && crtc->state->active) {
13175                         update_scanline_offset(to_intel_crtc(crtc));
13176                         dev_priv->display.crtc_enable(crtc);
13177                 }
13178
13179                 if (update_pipe) {
13180                         put_domains = modeset_get_crtc_power_domains(crtc);
13181
13182                         /* make sure intel_modeset_check_state runs */
13183                         any_ms = true;
13184                 }
13185
13186                 if (!modeset)
13187                         intel_pre_plane_update(intel_crtc);
13188
13189                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13190
13191                 if (put_domains)
13192                         modeset_put_power_domains(dev_priv, put_domains);
13193
13194                 intel_post_plane_update(intel_crtc);
13195         }
13196
13197         /* FIXME: add subpixel order */
13198
13199         drm_atomic_helper_wait_for_vblanks(dev, state);
13200         drm_atomic_helper_cleanup_planes(dev, state);
13201
13202         if (any_ms)
13203                 intel_modeset_check_state(dev, state);
13204
13205         drm_atomic_state_free(state);
13206
13207         return 0;
13208 }
13209
13210 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13211 {
13212         struct drm_device *dev = crtc->dev;
13213         struct drm_atomic_state *state;
13214         struct drm_crtc_state *crtc_state;
13215         int ret;
13216
13217         state = drm_atomic_state_alloc(dev);
13218         if (!state) {
13219                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13220                               crtc->base.id);
13221                 return;
13222         }
13223
13224         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13225
13226 retry:
13227         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13228         ret = PTR_ERR_OR_ZERO(crtc_state);
13229         if (!ret) {
13230                 if (!crtc_state->active)
13231                         goto out;
13232
13233                 crtc_state->mode_changed = true;
13234                 ret = drm_atomic_commit(state);
13235         }
13236
13237         if (ret == -EDEADLK) {
13238                 drm_atomic_state_clear(state);
13239                 drm_modeset_backoff(state->acquire_ctx);
13240                 goto retry;
13241         }
13242
13243         if (ret)
13244 out:
13245                 drm_atomic_state_free(state);
13246 }
13247
13248 #undef for_each_intel_crtc_masked
13249
13250 static const struct drm_crtc_funcs intel_crtc_funcs = {
13251         .gamma_set = intel_crtc_gamma_set,
13252         .set_config = drm_atomic_helper_set_config,
13253         .destroy = intel_crtc_destroy,
13254         .page_flip = intel_crtc_page_flip,
13255         .atomic_duplicate_state = intel_crtc_duplicate_state,
13256         .atomic_destroy_state = intel_crtc_destroy_state,
13257 };
13258
13259 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13260                                       struct intel_shared_dpll *pll,
13261                                       struct intel_dpll_hw_state *hw_state)
13262 {
13263         uint32_t val;
13264
13265         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13266                 return false;
13267
13268         val = I915_READ(PCH_DPLL(pll->id));
13269         hw_state->dpll = val;
13270         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13271         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13272
13273         return val & DPLL_VCO_ENABLE;
13274 }
13275
13276 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13277                                   struct intel_shared_dpll *pll)
13278 {
13279         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13280         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13281 }
13282
13283 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13284                                 struct intel_shared_dpll *pll)
13285 {
13286         /* PCH refclock must be enabled first */
13287         ibx_assert_pch_refclk_enabled(dev_priv);
13288
13289         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13290
13291         /* Wait for the clocks to stabilize. */
13292         POSTING_READ(PCH_DPLL(pll->id));
13293         udelay(150);
13294
13295         /* The pixel multiplier can only be updated once the
13296          * DPLL is enabled and the clocks are stable.
13297          *
13298          * So write it again.
13299          */
13300         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13301         POSTING_READ(PCH_DPLL(pll->id));
13302         udelay(200);
13303 }
13304
13305 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13306                                  struct intel_shared_dpll *pll)
13307 {
13308         struct drm_device *dev = dev_priv->dev;
13309         struct intel_crtc *crtc;
13310
13311         /* Make sure no transcoder isn't still depending on us. */
13312         for_each_intel_crtc(dev, crtc) {
13313                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13314                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13315         }
13316
13317         I915_WRITE(PCH_DPLL(pll->id), 0);
13318         POSTING_READ(PCH_DPLL(pll->id));
13319         udelay(200);
13320 }
13321
13322 static char *ibx_pch_dpll_names[] = {
13323         "PCH DPLL A",
13324         "PCH DPLL B",
13325 };
13326
13327 static void ibx_pch_dpll_init(struct drm_device *dev)
13328 {
13329         struct drm_i915_private *dev_priv = dev->dev_private;
13330         int i;
13331
13332         dev_priv->num_shared_dpll = 2;
13333
13334         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13335                 dev_priv->shared_dplls[i].id = i;
13336                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13337                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13338                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13339                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13340                 dev_priv->shared_dplls[i].get_hw_state =
13341                         ibx_pch_dpll_get_hw_state;
13342         }
13343 }
13344
13345 static void intel_shared_dpll_init(struct drm_device *dev)
13346 {
13347         struct drm_i915_private *dev_priv = dev->dev_private;
13348
13349         if (HAS_DDI(dev))
13350                 intel_ddi_pll_init(dev);
13351         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13352                 ibx_pch_dpll_init(dev);
13353         else
13354                 dev_priv->num_shared_dpll = 0;
13355
13356         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13357 }
13358
13359 /**
13360  * intel_prepare_plane_fb - Prepare fb for usage on plane
13361  * @plane: drm plane to prepare for
13362  * @fb: framebuffer to prepare for presentation
13363  *
13364  * Prepares a framebuffer for usage on a display plane.  Generally this
13365  * involves pinning the underlying object and updating the frontbuffer tracking
13366  * bits.  Some older platforms need special physical address handling for
13367  * cursor planes.
13368  *
13369  * Returns 0 on success, negative error code on failure.
13370  */
13371 int
13372 intel_prepare_plane_fb(struct drm_plane *plane,
13373                        const struct drm_plane_state *new_state)
13374 {
13375         struct drm_device *dev = plane->dev;
13376         struct drm_framebuffer *fb = new_state->fb;
13377         struct intel_plane *intel_plane = to_intel_plane(plane);
13378         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13379         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13380         int ret = 0;
13381
13382         if (!obj)
13383                 return 0;
13384
13385         mutex_lock(&dev->struct_mutex);
13386
13387         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13388             INTEL_INFO(dev)->cursor_needs_physical) {
13389                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13390                 ret = i915_gem_object_attach_phys(obj, align);
13391                 if (ret)
13392                         DRM_DEBUG_KMS("failed to attach phys object\n");
13393         } else {
13394                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13395         }
13396
13397         if (ret == 0)
13398                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13399
13400         mutex_unlock(&dev->struct_mutex);
13401
13402         return ret;
13403 }
13404
13405 /**
13406  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13407  * @plane: drm plane to clean up for
13408  * @fb: old framebuffer that was on plane
13409  *
13410  * Cleans up a framebuffer that has just been removed from a plane.
13411  */
13412 void
13413 intel_cleanup_plane_fb(struct drm_plane *plane,
13414                        const struct drm_plane_state *old_state)
13415 {
13416         struct drm_device *dev = plane->dev;
13417         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13418
13419         if (!obj)
13420                 return;
13421
13422         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13423             !INTEL_INFO(dev)->cursor_needs_physical) {
13424                 mutex_lock(&dev->struct_mutex);
13425                 intel_unpin_fb_obj(old_state->fb, old_state);
13426                 mutex_unlock(&dev->struct_mutex);
13427         }
13428 }
13429
13430 int
13431 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13432 {
13433         int max_scale;
13434         struct drm_device *dev;
13435         struct drm_i915_private *dev_priv;
13436         int crtc_clock, cdclk;
13437
13438         if (!intel_crtc || !crtc_state)
13439                 return DRM_PLANE_HELPER_NO_SCALING;
13440
13441         dev = intel_crtc->base.dev;
13442         dev_priv = dev->dev_private;
13443         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13444         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13445
13446         if (!crtc_clock || !cdclk)
13447                 return DRM_PLANE_HELPER_NO_SCALING;
13448
13449         /*
13450          * skl max scale is lower of:
13451          *    close to 3 but not 3, -1 is for that purpose
13452          *            or
13453          *    cdclk/crtc_clock
13454          */
13455         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13456
13457         return max_scale;
13458 }
13459
13460 static int
13461 intel_check_primary_plane(struct drm_plane *plane,
13462                           struct intel_crtc_state *crtc_state,
13463                           struct intel_plane_state *state)
13464 {
13465         struct drm_crtc *crtc = state->base.crtc;
13466         struct drm_framebuffer *fb = state->base.fb;
13467         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13468         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13469         bool can_position = false;
13470
13471         /* use scaler when colorkey is not required */
13472         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13473             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13474                 min_scale = 1;
13475                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13476                 can_position = true;
13477         }
13478
13479         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13480                                              &state->dst, &state->clip,
13481                                              min_scale, max_scale,
13482                                              can_position, true,
13483                                              &state->visible);
13484 }
13485
13486 static void
13487 intel_commit_primary_plane(struct drm_plane *plane,
13488                            struct intel_plane_state *state)
13489 {
13490         struct drm_crtc *crtc = state->base.crtc;
13491         struct drm_framebuffer *fb = state->base.fb;
13492         struct drm_device *dev = plane->dev;
13493         struct drm_i915_private *dev_priv = dev->dev_private;
13494         struct intel_crtc *intel_crtc;
13495         struct drm_rect *src = &state->src;
13496
13497         crtc = crtc ? crtc : plane->crtc;
13498         intel_crtc = to_intel_crtc(crtc);
13499
13500         plane->fb = fb;
13501         crtc->x = src->x1 >> 16;
13502         crtc->y = src->y1 >> 16;
13503
13504         if (!crtc->state->active)
13505                 return;
13506
13507         dev_priv->display.update_primary_plane(crtc, fb,
13508                                                state->src.x1 >> 16,
13509                                                state->src.y1 >> 16);
13510 }
13511
13512 static void
13513 intel_disable_primary_plane(struct drm_plane *plane,
13514                             struct drm_crtc *crtc)
13515 {
13516         struct drm_device *dev = plane->dev;
13517         struct drm_i915_private *dev_priv = dev->dev_private;
13518
13519         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13520 }
13521
13522 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13523                                     struct drm_crtc_state *old_crtc_state)
13524 {
13525         struct drm_device *dev = crtc->dev;
13526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13527         struct intel_crtc_state *old_intel_state =
13528                 to_intel_crtc_state(old_crtc_state);
13529         bool modeset = needs_modeset(crtc->state);
13530
13531         if (intel_crtc->atomic.update_wm_pre)
13532                 intel_update_watermarks(crtc);
13533
13534         /* Perform vblank evasion around commit operation */
13535         if (crtc->state->active)
13536                 intel_pipe_update_start(intel_crtc);
13537
13538         if (modeset)
13539                 return;
13540
13541         if (to_intel_crtc_state(crtc->state)->update_pipe)
13542                 intel_update_pipe_config(intel_crtc, old_intel_state);
13543         else if (INTEL_INFO(dev)->gen >= 9)
13544                 skl_detach_scalers(intel_crtc);
13545 }
13546
13547 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13548                                      struct drm_crtc_state *old_crtc_state)
13549 {
13550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13551
13552         if (crtc->state->active)
13553                 intel_pipe_update_end(intel_crtc);
13554 }
13555
13556 /**
13557  * intel_plane_destroy - destroy a plane
13558  * @plane: plane to destroy
13559  *
13560  * Common destruction function for all types of planes (primary, cursor,
13561  * sprite).
13562  */
13563 void intel_plane_destroy(struct drm_plane *plane)
13564 {
13565         struct intel_plane *intel_plane = to_intel_plane(plane);
13566         drm_plane_cleanup(plane);
13567         kfree(intel_plane);
13568 }
13569
13570 const struct drm_plane_funcs intel_plane_funcs = {
13571         .update_plane = drm_atomic_helper_update_plane,
13572         .disable_plane = drm_atomic_helper_disable_plane,
13573         .destroy = intel_plane_destroy,
13574         .set_property = drm_atomic_helper_plane_set_property,
13575         .atomic_get_property = intel_plane_atomic_get_property,
13576         .atomic_set_property = intel_plane_atomic_set_property,
13577         .atomic_duplicate_state = intel_plane_duplicate_state,
13578         .atomic_destroy_state = intel_plane_destroy_state,
13579
13580 };
13581
13582 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13583                                                     int pipe)
13584 {
13585         struct intel_plane *primary;
13586         struct intel_plane_state *state;
13587         const uint32_t *intel_primary_formats;
13588         unsigned int num_formats;
13589
13590         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13591         if (primary == NULL)
13592                 return NULL;
13593
13594         state = intel_create_plane_state(&primary->base);
13595         if (!state) {
13596                 kfree(primary);
13597                 return NULL;
13598         }
13599         primary->base.state = &state->base;
13600
13601         primary->can_scale = false;
13602         primary->max_downscale = 1;
13603         if (INTEL_INFO(dev)->gen >= 9) {
13604                 primary->can_scale = true;
13605                 state->scaler_id = -1;
13606         }
13607         primary->pipe = pipe;
13608         primary->plane = pipe;
13609         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13610         primary->check_plane = intel_check_primary_plane;
13611         primary->commit_plane = intel_commit_primary_plane;
13612         primary->disable_plane = intel_disable_primary_plane;
13613         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13614                 primary->plane = !pipe;
13615
13616         if (INTEL_INFO(dev)->gen >= 9) {
13617                 intel_primary_formats = skl_primary_formats;
13618                 num_formats = ARRAY_SIZE(skl_primary_formats);
13619         } else if (INTEL_INFO(dev)->gen >= 4) {
13620                 intel_primary_formats = i965_primary_formats;
13621                 num_formats = ARRAY_SIZE(i965_primary_formats);
13622         } else {
13623                 intel_primary_formats = i8xx_primary_formats;
13624                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13625         }
13626
13627         drm_universal_plane_init(dev, &primary->base, 0,
13628                                  &intel_plane_funcs,
13629                                  intel_primary_formats, num_formats,
13630                                  DRM_PLANE_TYPE_PRIMARY);
13631
13632         if (INTEL_INFO(dev)->gen >= 4)
13633                 intel_create_rotation_property(dev, primary);
13634
13635         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13636
13637         return &primary->base;
13638 }
13639
13640 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13641 {
13642         if (!dev->mode_config.rotation_property) {
13643                 unsigned long flags = BIT(DRM_ROTATE_0) |
13644                         BIT(DRM_ROTATE_180);
13645
13646                 if (INTEL_INFO(dev)->gen >= 9)
13647                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13648
13649                 dev->mode_config.rotation_property =
13650                         drm_mode_create_rotation_property(dev, flags);
13651         }
13652         if (dev->mode_config.rotation_property)
13653                 drm_object_attach_property(&plane->base.base,
13654                                 dev->mode_config.rotation_property,
13655                                 plane->base.state->rotation);
13656 }
13657
13658 static int
13659 intel_check_cursor_plane(struct drm_plane *plane,
13660                          struct intel_crtc_state *crtc_state,
13661                          struct intel_plane_state *state)
13662 {
13663         struct drm_crtc *crtc = crtc_state->base.crtc;
13664         struct drm_framebuffer *fb = state->base.fb;
13665         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13666         unsigned stride;
13667         int ret;
13668
13669         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13670                                             &state->dst, &state->clip,
13671                                             DRM_PLANE_HELPER_NO_SCALING,
13672                                             DRM_PLANE_HELPER_NO_SCALING,
13673                                             true, true, &state->visible);
13674         if (ret)
13675                 return ret;
13676
13677         /* if we want to turn off the cursor ignore width and height */
13678         if (!obj)
13679                 return 0;
13680
13681         /* Check for which cursor types we support */
13682         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13683                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13684                           state->base.crtc_w, state->base.crtc_h);
13685                 return -EINVAL;
13686         }
13687
13688         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13689         if (obj->base.size < stride * state->base.crtc_h) {
13690                 DRM_DEBUG_KMS("buffer is too small\n");
13691                 return -ENOMEM;
13692         }
13693
13694         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13695                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13696                 return -EINVAL;
13697         }
13698
13699         return 0;
13700 }
13701
13702 static void
13703 intel_disable_cursor_plane(struct drm_plane *plane,
13704                            struct drm_crtc *crtc)
13705 {
13706         intel_crtc_update_cursor(crtc, false);
13707 }
13708
13709 static void
13710 intel_commit_cursor_plane(struct drm_plane *plane,
13711                           struct intel_plane_state *state)
13712 {
13713         struct drm_crtc *crtc = state->base.crtc;
13714         struct drm_device *dev = plane->dev;
13715         struct intel_crtc *intel_crtc;
13716         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13717         uint32_t addr;
13718
13719         crtc = crtc ? crtc : plane->crtc;
13720         intel_crtc = to_intel_crtc(crtc);
13721
13722         if (intel_crtc->cursor_bo == obj)
13723                 goto update;
13724
13725         if (!obj)
13726                 addr = 0;
13727         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13728                 addr = i915_gem_obj_ggtt_offset(obj);
13729         else
13730                 addr = obj->phys_handle->busaddr;
13731
13732         intel_crtc->cursor_addr = addr;
13733         intel_crtc->cursor_bo = obj;
13734
13735 update:
13736         if (crtc->state->active)
13737                 intel_crtc_update_cursor(crtc, state->visible);
13738 }
13739
13740 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13741                                                    int pipe)
13742 {
13743         struct intel_plane *cursor;
13744         struct intel_plane_state *state;
13745
13746         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13747         if (cursor == NULL)
13748                 return NULL;
13749
13750         state = intel_create_plane_state(&cursor->base);
13751         if (!state) {
13752                 kfree(cursor);
13753                 return NULL;
13754         }
13755         cursor->base.state = &state->base;
13756
13757         cursor->can_scale = false;
13758         cursor->max_downscale = 1;
13759         cursor->pipe = pipe;
13760         cursor->plane = pipe;
13761         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13762         cursor->check_plane = intel_check_cursor_plane;
13763         cursor->commit_plane = intel_commit_cursor_plane;
13764         cursor->disable_plane = intel_disable_cursor_plane;
13765
13766         drm_universal_plane_init(dev, &cursor->base, 0,
13767                                  &intel_plane_funcs,
13768                                  intel_cursor_formats,
13769                                  ARRAY_SIZE(intel_cursor_formats),
13770                                  DRM_PLANE_TYPE_CURSOR);
13771
13772         if (INTEL_INFO(dev)->gen >= 4) {
13773                 if (!dev->mode_config.rotation_property)
13774                         dev->mode_config.rotation_property =
13775                                 drm_mode_create_rotation_property(dev,
13776                                                         BIT(DRM_ROTATE_0) |
13777                                                         BIT(DRM_ROTATE_180));
13778                 if (dev->mode_config.rotation_property)
13779                         drm_object_attach_property(&cursor->base.base,
13780                                 dev->mode_config.rotation_property,
13781                                 state->base.rotation);
13782         }
13783
13784         if (INTEL_INFO(dev)->gen >=9)
13785                 state->scaler_id = -1;
13786
13787         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13788
13789         return &cursor->base;
13790 }
13791
13792 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13793         struct intel_crtc_state *crtc_state)
13794 {
13795         int i;
13796         struct intel_scaler *intel_scaler;
13797         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13798
13799         for (i = 0; i < intel_crtc->num_scalers; i++) {
13800                 intel_scaler = &scaler_state->scalers[i];
13801                 intel_scaler->in_use = 0;
13802                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13803         }
13804
13805         scaler_state->scaler_id = -1;
13806 }
13807
13808 static void intel_crtc_init(struct drm_device *dev, int pipe)
13809 {
13810         struct drm_i915_private *dev_priv = dev->dev_private;
13811         struct intel_crtc *intel_crtc;
13812         struct intel_crtc_state *crtc_state = NULL;
13813         struct drm_plane *primary = NULL;
13814         struct drm_plane *cursor = NULL;
13815         int i, ret;
13816
13817         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13818         if (intel_crtc == NULL)
13819                 return;
13820
13821         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13822         if (!crtc_state)
13823                 goto fail;
13824         intel_crtc->config = crtc_state;
13825         intel_crtc->base.state = &crtc_state->base;
13826         crtc_state->base.crtc = &intel_crtc->base;
13827
13828         /* initialize shared scalers */
13829         if (INTEL_INFO(dev)->gen >= 9) {
13830                 if (pipe == PIPE_C)
13831                         intel_crtc->num_scalers = 1;
13832                 else
13833                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13834
13835                 skl_init_scalers(dev, intel_crtc, crtc_state);
13836         }
13837
13838         primary = intel_primary_plane_create(dev, pipe);
13839         if (!primary)
13840                 goto fail;
13841
13842         cursor = intel_cursor_plane_create(dev, pipe);
13843         if (!cursor)
13844                 goto fail;
13845
13846         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13847                                         cursor, &intel_crtc_funcs);
13848         if (ret)
13849                 goto fail;
13850
13851         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13852         for (i = 0; i < 256; i++) {
13853                 intel_crtc->lut_r[i] = i;
13854                 intel_crtc->lut_g[i] = i;
13855                 intel_crtc->lut_b[i] = i;
13856         }
13857
13858         /*
13859          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13860          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13861          */
13862         intel_crtc->pipe = pipe;
13863         intel_crtc->plane = pipe;
13864         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13865                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13866                 intel_crtc->plane = !pipe;
13867         }
13868
13869         intel_crtc->cursor_base = ~0;
13870         intel_crtc->cursor_cntl = ~0;
13871         intel_crtc->cursor_size = ~0;
13872
13873         intel_crtc->wm.cxsr_allowed = true;
13874
13875         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13876                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13877         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13878         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13879
13880         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13881
13882         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13883         return;
13884
13885 fail:
13886         if (primary)
13887                 drm_plane_cleanup(primary);
13888         if (cursor)
13889                 drm_plane_cleanup(cursor);
13890         kfree(crtc_state);
13891         kfree(intel_crtc);
13892 }
13893
13894 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13895 {
13896         struct drm_encoder *encoder = connector->base.encoder;
13897         struct drm_device *dev = connector->base.dev;
13898
13899         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13900
13901         if (!encoder || WARN_ON(!encoder->crtc))
13902                 return INVALID_PIPE;
13903
13904         return to_intel_crtc(encoder->crtc)->pipe;
13905 }
13906
13907 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13908                                 struct drm_file *file)
13909 {
13910         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13911         struct drm_crtc *drmmode_crtc;
13912         struct intel_crtc *crtc;
13913
13914         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13915
13916         if (!drmmode_crtc) {
13917                 DRM_ERROR("no such CRTC id\n");
13918                 return -ENOENT;
13919         }
13920
13921         crtc = to_intel_crtc(drmmode_crtc);
13922         pipe_from_crtc_id->pipe = crtc->pipe;
13923
13924         return 0;
13925 }
13926
13927 static int intel_encoder_clones(struct intel_encoder *encoder)
13928 {
13929         struct drm_device *dev = encoder->base.dev;
13930         struct intel_encoder *source_encoder;
13931         int index_mask = 0;
13932         int entry = 0;
13933
13934         for_each_intel_encoder(dev, source_encoder) {
13935                 if (encoders_cloneable(encoder, source_encoder))
13936                         index_mask |= (1 << entry);
13937
13938                 entry++;
13939         }
13940
13941         return index_mask;
13942 }
13943
13944 static bool has_edp_a(struct drm_device *dev)
13945 {
13946         struct drm_i915_private *dev_priv = dev->dev_private;
13947
13948         if (!IS_MOBILE(dev))
13949                 return false;
13950
13951         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13952                 return false;
13953
13954         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13955                 return false;
13956
13957         return true;
13958 }
13959
13960 static bool intel_crt_present(struct drm_device *dev)
13961 {
13962         struct drm_i915_private *dev_priv = dev->dev_private;
13963
13964         if (INTEL_INFO(dev)->gen >= 9)
13965                 return false;
13966
13967         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13968                 return false;
13969
13970         if (IS_CHERRYVIEW(dev))
13971                 return false;
13972
13973         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13974                 return false;
13975
13976         return true;
13977 }
13978
13979 static void intel_setup_outputs(struct drm_device *dev)
13980 {
13981         struct drm_i915_private *dev_priv = dev->dev_private;
13982         struct intel_encoder *encoder;
13983         bool dpd_is_edp = false;
13984
13985         intel_lvds_init(dev);
13986
13987         if (intel_crt_present(dev))
13988                 intel_crt_init(dev);
13989
13990         if (IS_BROXTON(dev)) {
13991                 /*
13992                  * FIXME: Broxton doesn't support port detection via the
13993                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13994                  * detect the ports.
13995                  */
13996                 intel_ddi_init(dev, PORT_A);
13997                 intel_ddi_init(dev, PORT_B);
13998                 intel_ddi_init(dev, PORT_C);
13999         } else if (HAS_DDI(dev)) {
14000                 int found;
14001
14002                 /*
14003                  * Haswell uses DDI functions to detect digital outputs.
14004                  * On SKL pre-D0 the strap isn't connected, so we assume
14005                  * it's there.
14006                  */
14007                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14008                 /* WaIgnoreDDIAStrap: skl */
14009                 if (found || IS_SKYLAKE(dev))
14010                         intel_ddi_init(dev, PORT_A);
14011
14012                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14013                  * register */
14014                 found = I915_READ(SFUSE_STRAP);
14015
14016                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14017                         intel_ddi_init(dev, PORT_B);
14018                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14019                         intel_ddi_init(dev, PORT_C);
14020                 if (found & SFUSE_STRAP_DDID_DETECTED)
14021                         intel_ddi_init(dev, PORT_D);
14022                 /*
14023                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14024                  */
14025                 if (IS_SKYLAKE(dev) &&
14026                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14027                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14028                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14029                         intel_ddi_init(dev, PORT_E);
14030
14031         } else if (HAS_PCH_SPLIT(dev)) {
14032                 int found;
14033                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14034
14035                 if (has_edp_a(dev))
14036                         intel_dp_init(dev, DP_A, PORT_A);
14037
14038                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14039                         /* PCH SDVOB multiplex with HDMIB */
14040                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14041                         if (!found)
14042                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14043                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14044                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14045                 }
14046
14047                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14048                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14049
14050                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14051                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14052
14053                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14054                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14055
14056                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14057                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14058         } else if (IS_VALLEYVIEW(dev)) {
14059                 /*
14060                  * The DP_DETECTED bit is the latched state of the DDC
14061                  * SDA pin at boot. However since eDP doesn't require DDC
14062                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14063                  * eDP ports may have been muxed to an alternate function.
14064                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14065                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14066                  * detect eDP ports.
14067                  */
14068                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14069                     !intel_dp_is_edp(dev, PORT_B))
14070                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14071                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14072                     intel_dp_is_edp(dev, PORT_B))
14073                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14074
14075                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14076                     !intel_dp_is_edp(dev, PORT_C))
14077                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14078                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14079                     intel_dp_is_edp(dev, PORT_C))
14080                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14081
14082                 if (IS_CHERRYVIEW(dev)) {
14083                         /* eDP not supported on port D, so don't check VBT */
14084                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14085                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14086                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14087                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14088                 }
14089
14090                 intel_dsi_init(dev);
14091         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14092                 bool found = false;
14093
14094                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14095                         DRM_DEBUG_KMS("probing SDVOB\n");
14096                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14097                         if (!found && IS_G4X(dev)) {
14098                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14099                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14100                         }
14101
14102                         if (!found && IS_G4X(dev))
14103                                 intel_dp_init(dev, DP_B, PORT_B);
14104                 }
14105
14106                 /* Before G4X SDVOC doesn't have its own detect register */
14107
14108                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14109                         DRM_DEBUG_KMS("probing SDVOC\n");
14110                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14111                 }
14112
14113                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14114
14115                         if (IS_G4X(dev)) {
14116                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14117                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14118                         }
14119                         if (IS_G4X(dev))
14120                                 intel_dp_init(dev, DP_C, PORT_C);
14121                 }
14122
14123                 if (IS_G4X(dev) &&
14124                     (I915_READ(DP_D) & DP_DETECTED))
14125                         intel_dp_init(dev, DP_D, PORT_D);
14126         } else if (IS_GEN2(dev))
14127                 intel_dvo_init(dev);
14128
14129         if (SUPPORTS_TV(dev))
14130                 intel_tv_init(dev);
14131
14132         intel_psr_init(dev);
14133
14134         for_each_intel_encoder(dev, encoder) {
14135                 encoder->base.possible_crtcs = encoder->crtc_mask;
14136                 encoder->base.possible_clones =
14137                         intel_encoder_clones(encoder);
14138         }
14139
14140         intel_init_pch_refclk(dev);
14141
14142         drm_helper_move_panel_connectors_to_head(dev);
14143 }
14144
14145 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14146 {
14147         struct drm_device *dev = fb->dev;
14148         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14149
14150         drm_framebuffer_cleanup(fb);
14151         mutex_lock(&dev->struct_mutex);
14152         WARN_ON(!intel_fb->obj->framebuffer_references--);
14153         drm_gem_object_unreference(&intel_fb->obj->base);
14154         mutex_unlock(&dev->struct_mutex);
14155         kfree(intel_fb);
14156 }
14157
14158 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14159                                                 struct drm_file *file,
14160                                                 unsigned int *handle)
14161 {
14162         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14163         struct drm_i915_gem_object *obj = intel_fb->obj;
14164
14165         return drm_gem_handle_create(file, &obj->base, handle);
14166 }
14167
14168 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14169                                         struct drm_file *file,
14170                                         unsigned flags, unsigned color,
14171                                         struct drm_clip_rect *clips,
14172                                         unsigned num_clips)
14173 {
14174         struct drm_device *dev = fb->dev;
14175         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14176         struct drm_i915_gem_object *obj = intel_fb->obj;
14177
14178         mutex_lock(&dev->struct_mutex);
14179         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14180         mutex_unlock(&dev->struct_mutex);
14181
14182         return 0;
14183 }
14184
14185 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14186         .destroy = intel_user_framebuffer_destroy,
14187         .create_handle = intel_user_framebuffer_create_handle,
14188         .dirty = intel_user_framebuffer_dirty,
14189 };
14190
14191 static
14192 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14193                          uint32_t pixel_format)
14194 {
14195         u32 gen = INTEL_INFO(dev)->gen;
14196
14197         if (gen >= 9) {
14198                 /* "The stride in bytes must not exceed the of the size of 8K
14199                  *  pixels and 32K bytes."
14200                  */
14201                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14202         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14203                 return 32*1024;
14204         } else if (gen >= 4) {
14205                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14206                         return 16*1024;
14207                 else
14208                         return 32*1024;
14209         } else if (gen >= 3) {
14210                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14211                         return 8*1024;
14212                 else
14213                         return 16*1024;
14214         } else {
14215                 /* XXX DSPC is limited to 4k tiled */
14216                 return 8*1024;
14217         }
14218 }
14219
14220 static int intel_framebuffer_init(struct drm_device *dev,
14221                                   struct intel_framebuffer *intel_fb,
14222                                   struct drm_mode_fb_cmd2 *mode_cmd,
14223                                   struct drm_i915_gem_object *obj)
14224 {
14225         unsigned int aligned_height;
14226         int ret;
14227         u32 pitch_limit, stride_alignment;
14228
14229         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14230
14231         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14232                 /* Enforce that fb modifier and tiling mode match, but only for
14233                  * X-tiled. This is needed for FBC. */
14234                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14235                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14236                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14237                         return -EINVAL;
14238                 }
14239         } else {
14240                 if (obj->tiling_mode == I915_TILING_X)
14241                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14242                 else if (obj->tiling_mode == I915_TILING_Y) {
14243                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14244                         return -EINVAL;
14245                 }
14246         }
14247
14248         /* Passed in modifier sanity checking. */
14249         switch (mode_cmd->modifier[0]) {
14250         case I915_FORMAT_MOD_Y_TILED:
14251         case I915_FORMAT_MOD_Yf_TILED:
14252                 if (INTEL_INFO(dev)->gen < 9) {
14253                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14254                                   mode_cmd->modifier[0]);
14255                         return -EINVAL;
14256                 }
14257         case DRM_FORMAT_MOD_NONE:
14258         case I915_FORMAT_MOD_X_TILED:
14259                 break;
14260         default:
14261                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14262                           mode_cmd->modifier[0]);
14263                 return -EINVAL;
14264         }
14265
14266         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14267                                                      mode_cmd->pixel_format);
14268         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14269                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14270                           mode_cmd->pitches[0], stride_alignment);
14271                 return -EINVAL;
14272         }
14273
14274         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14275                                            mode_cmd->pixel_format);
14276         if (mode_cmd->pitches[0] > pitch_limit) {
14277                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14278                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14279                           "tiled" : "linear",
14280                           mode_cmd->pitches[0], pitch_limit);
14281                 return -EINVAL;
14282         }
14283
14284         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14285             mode_cmd->pitches[0] != obj->stride) {
14286                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14287                           mode_cmd->pitches[0], obj->stride);
14288                 return -EINVAL;
14289         }
14290
14291         /* Reject formats not supported by any plane early. */
14292         switch (mode_cmd->pixel_format) {
14293         case DRM_FORMAT_C8:
14294         case DRM_FORMAT_RGB565:
14295         case DRM_FORMAT_XRGB8888:
14296         case DRM_FORMAT_ARGB8888:
14297                 break;
14298         case DRM_FORMAT_XRGB1555:
14299                 if (INTEL_INFO(dev)->gen > 3) {
14300                         DRM_DEBUG("unsupported pixel format: %s\n",
14301                                   drm_get_format_name(mode_cmd->pixel_format));
14302                         return -EINVAL;
14303                 }
14304                 break;
14305         case DRM_FORMAT_ABGR8888:
14306                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14307                         DRM_DEBUG("unsupported pixel format: %s\n",
14308                                   drm_get_format_name(mode_cmd->pixel_format));
14309                         return -EINVAL;
14310                 }
14311                 break;
14312         case DRM_FORMAT_XBGR8888:
14313         case DRM_FORMAT_XRGB2101010:
14314         case DRM_FORMAT_XBGR2101010:
14315                 if (INTEL_INFO(dev)->gen < 4) {
14316                         DRM_DEBUG("unsupported pixel format: %s\n",
14317                                   drm_get_format_name(mode_cmd->pixel_format));
14318                         return -EINVAL;
14319                 }
14320                 break;
14321         case DRM_FORMAT_ABGR2101010:
14322                 if (!IS_VALLEYVIEW(dev)) {
14323                         DRM_DEBUG("unsupported pixel format: %s\n",
14324                                   drm_get_format_name(mode_cmd->pixel_format));
14325                         return -EINVAL;
14326                 }
14327                 break;
14328         case DRM_FORMAT_YUYV:
14329         case DRM_FORMAT_UYVY:
14330         case DRM_FORMAT_YVYU:
14331         case DRM_FORMAT_VYUY:
14332                 if (INTEL_INFO(dev)->gen < 5) {
14333                         DRM_DEBUG("unsupported pixel format: %s\n",
14334                                   drm_get_format_name(mode_cmd->pixel_format));
14335                         return -EINVAL;
14336                 }
14337                 break;
14338         default:
14339                 DRM_DEBUG("unsupported pixel format: %s\n",
14340                           drm_get_format_name(mode_cmd->pixel_format));
14341                 return -EINVAL;
14342         }
14343
14344         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14345         if (mode_cmd->offsets[0] != 0)
14346                 return -EINVAL;
14347
14348         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14349                                                mode_cmd->pixel_format,
14350                                                mode_cmd->modifier[0]);
14351         /* FIXME drm helper for size checks (especially planar formats)? */
14352         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14353                 return -EINVAL;
14354
14355         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14356         intel_fb->obj = obj;
14357         intel_fb->obj->framebuffer_references++;
14358
14359         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14360         if (ret) {
14361                 DRM_ERROR("framebuffer init failed %d\n", ret);
14362                 return ret;
14363         }
14364
14365         return 0;
14366 }
14367
14368 static struct drm_framebuffer *
14369 intel_user_framebuffer_create(struct drm_device *dev,
14370                               struct drm_file *filp,
14371                               struct drm_mode_fb_cmd2 *mode_cmd)
14372 {
14373         struct drm_i915_gem_object *obj;
14374
14375         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14376                                                 mode_cmd->handles[0]));
14377         if (&obj->base == NULL)
14378                 return ERR_PTR(-ENOENT);
14379
14380         return intel_framebuffer_create(dev, mode_cmd, obj);
14381 }
14382
14383 #ifndef CONFIG_DRM_FBDEV_EMULATION
14384 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14385 {
14386 }
14387 #endif
14388
14389 static const struct drm_mode_config_funcs intel_mode_funcs = {
14390         .fb_create = intel_user_framebuffer_create,
14391         .output_poll_changed = intel_fbdev_output_poll_changed,
14392         .atomic_check = intel_atomic_check,
14393         .atomic_commit = intel_atomic_commit,
14394         .atomic_state_alloc = intel_atomic_state_alloc,
14395         .atomic_state_clear = intel_atomic_state_clear,
14396 };
14397
14398 /* Set up chip specific display functions */
14399 static void intel_init_display(struct drm_device *dev)
14400 {
14401         struct drm_i915_private *dev_priv = dev->dev_private;
14402
14403         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14404                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14405         else if (IS_CHERRYVIEW(dev))
14406                 dev_priv->display.find_dpll = chv_find_best_dpll;
14407         else if (IS_VALLEYVIEW(dev))
14408                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14409         else if (IS_PINEVIEW(dev))
14410                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14411         else
14412                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14413
14414         if (INTEL_INFO(dev)->gen >= 9) {
14415                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14416                 dev_priv->display.get_initial_plane_config =
14417                         skylake_get_initial_plane_config;
14418                 dev_priv->display.crtc_compute_clock =
14419                         haswell_crtc_compute_clock;
14420                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14421                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14422                 dev_priv->display.update_primary_plane =
14423                         skylake_update_primary_plane;
14424         } else if (HAS_DDI(dev)) {
14425                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14426                 dev_priv->display.get_initial_plane_config =
14427                         ironlake_get_initial_plane_config;
14428                 dev_priv->display.crtc_compute_clock =
14429                         haswell_crtc_compute_clock;
14430                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14431                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14432                 dev_priv->display.update_primary_plane =
14433                         ironlake_update_primary_plane;
14434         } else if (HAS_PCH_SPLIT(dev)) {
14435                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14436                 dev_priv->display.get_initial_plane_config =
14437                         ironlake_get_initial_plane_config;
14438                 dev_priv->display.crtc_compute_clock =
14439                         ironlake_crtc_compute_clock;
14440                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14441                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14442                 dev_priv->display.update_primary_plane =
14443                         ironlake_update_primary_plane;
14444         } else if (IS_VALLEYVIEW(dev)) {
14445                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14446                 dev_priv->display.get_initial_plane_config =
14447                         i9xx_get_initial_plane_config;
14448                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14449                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14450                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14451                 dev_priv->display.update_primary_plane =
14452                         i9xx_update_primary_plane;
14453         } else {
14454                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14455                 dev_priv->display.get_initial_plane_config =
14456                         i9xx_get_initial_plane_config;
14457                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14458                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14459                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14460                 dev_priv->display.update_primary_plane =
14461                         i9xx_update_primary_plane;
14462         }
14463
14464         /* Returns the core display clock speed */
14465         if (IS_SKYLAKE(dev))
14466                 dev_priv->display.get_display_clock_speed =
14467                         skylake_get_display_clock_speed;
14468         else if (IS_BROXTON(dev))
14469                 dev_priv->display.get_display_clock_speed =
14470                         broxton_get_display_clock_speed;
14471         else if (IS_BROADWELL(dev))
14472                 dev_priv->display.get_display_clock_speed =
14473                         broadwell_get_display_clock_speed;
14474         else if (IS_HASWELL(dev))
14475                 dev_priv->display.get_display_clock_speed =
14476                         haswell_get_display_clock_speed;
14477         else if (IS_VALLEYVIEW(dev))
14478                 dev_priv->display.get_display_clock_speed =
14479                         valleyview_get_display_clock_speed;
14480         else if (IS_GEN5(dev))
14481                 dev_priv->display.get_display_clock_speed =
14482                         ilk_get_display_clock_speed;
14483         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14484                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14485                 dev_priv->display.get_display_clock_speed =
14486                         i945_get_display_clock_speed;
14487         else if (IS_GM45(dev))
14488                 dev_priv->display.get_display_clock_speed =
14489                         gm45_get_display_clock_speed;
14490         else if (IS_CRESTLINE(dev))
14491                 dev_priv->display.get_display_clock_speed =
14492                         i965gm_get_display_clock_speed;
14493         else if (IS_PINEVIEW(dev))
14494                 dev_priv->display.get_display_clock_speed =
14495                         pnv_get_display_clock_speed;
14496         else if (IS_G33(dev) || IS_G4X(dev))
14497                 dev_priv->display.get_display_clock_speed =
14498                         g33_get_display_clock_speed;
14499         else if (IS_I915G(dev))
14500                 dev_priv->display.get_display_clock_speed =
14501                         i915_get_display_clock_speed;
14502         else if (IS_I945GM(dev) || IS_845G(dev))
14503                 dev_priv->display.get_display_clock_speed =
14504                         i9xx_misc_get_display_clock_speed;
14505         else if (IS_PINEVIEW(dev))
14506                 dev_priv->display.get_display_clock_speed =
14507                         pnv_get_display_clock_speed;
14508         else if (IS_I915GM(dev))
14509                 dev_priv->display.get_display_clock_speed =
14510                         i915gm_get_display_clock_speed;
14511         else if (IS_I865G(dev))
14512                 dev_priv->display.get_display_clock_speed =
14513                         i865_get_display_clock_speed;
14514         else if (IS_I85X(dev))
14515                 dev_priv->display.get_display_clock_speed =
14516                         i85x_get_display_clock_speed;
14517         else { /* 830 */
14518                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14519                 dev_priv->display.get_display_clock_speed =
14520                         i830_get_display_clock_speed;
14521         }
14522
14523         if (IS_GEN5(dev)) {
14524                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14525         } else if (IS_GEN6(dev)) {
14526                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14527         } else if (IS_IVYBRIDGE(dev)) {
14528                 /* FIXME: detect B0+ stepping and use auto training */
14529                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14530         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14531                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14532                 if (IS_BROADWELL(dev)) {
14533                         dev_priv->display.modeset_commit_cdclk =
14534                                 broadwell_modeset_commit_cdclk;
14535                         dev_priv->display.modeset_calc_cdclk =
14536                                 broadwell_modeset_calc_cdclk;
14537                 }
14538         } else if (IS_VALLEYVIEW(dev)) {
14539                 dev_priv->display.modeset_commit_cdclk =
14540                         valleyview_modeset_commit_cdclk;
14541                 dev_priv->display.modeset_calc_cdclk =
14542                         valleyview_modeset_calc_cdclk;
14543         } else if (IS_BROXTON(dev)) {
14544                 dev_priv->display.modeset_commit_cdclk =
14545                         broxton_modeset_commit_cdclk;
14546                 dev_priv->display.modeset_calc_cdclk =
14547                         broxton_modeset_calc_cdclk;
14548         }
14549
14550         switch (INTEL_INFO(dev)->gen) {
14551         case 2:
14552                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14553                 break;
14554
14555         case 3:
14556                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14557                 break;
14558
14559         case 4:
14560         case 5:
14561                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14562                 break;
14563
14564         case 6:
14565                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14566                 break;
14567         case 7:
14568         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14569                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14570                 break;
14571         case 9:
14572                 /* Drop through - unsupported since execlist only. */
14573         default:
14574                 /* Default just returns -ENODEV to indicate unsupported */
14575                 dev_priv->display.queue_flip = intel_default_queue_flip;
14576         }
14577
14578         mutex_init(&dev_priv->pps_mutex);
14579 }
14580
14581 /*
14582  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14583  * resume, or other times.  This quirk makes sure that's the case for
14584  * affected systems.
14585  */
14586 static void quirk_pipea_force(struct drm_device *dev)
14587 {
14588         struct drm_i915_private *dev_priv = dev->dev_private;
14589
14590         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14591         DRM_INFO("applying pipe a force quirk\n");
14592 }
14593
14594 static void quirk_pipeb_force(struct drm_device *dev)
14595 {
14596         struct drm_i915_private *dev_priv = dev->dev_private;
14597
14598         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14599         DRM_INFO("applying pipe b force quirk\n");
14600 }
14601
14602 /*
14603  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14604  */
14605 static void quirk_ssc_force_disable(struct drm_device *dev)
14606 {
14607         struct drm_i915_private *dev_priv = dev->dev_private;
14608         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14609         DRM_INFO("applying lvds SSC disable quirk\n");
14610 }
14611
14612 /*
14613  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14614  * brightness value
14615  */
14616 static void quirk_invert_brightness(struct drm_device *dev)
14617 {
14618         struct drm_i915_private *dev_priv = dev->dev_private;
14619         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14620         DRM_INFO("applying inverted panel brightness quirk\n");
14621 }
14622
14623 /* Some VBT's incorrectly indicate no backlight is present */
14624 static void quirk_backlight_present(struct drm_device *dev)
14625 {
14626         struct drm_i915_private *dev_priv = dev->dev_private;
14627         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14628         DRM_INFO("applying backlight present quirk\n");
14629 }
14630
14631 struct intel_quirk {
14632         int device;
14633         int subsystem_vendor;
14634         int subsystem_device;
14635         void (*hook)(struct drm_device *dev);
14636 };
14637
14638 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14639 struct intel_dmi_quirk {
14640         void (*hook)(struct drm_device *dev);
14641         const struct dmi_system_id (*dmi_id_list)[];
14642 };
14643
14644 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14645 {
14646         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14647         return 1;
14648 }
14649
14650 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14651         {
14652                 .dmi_id_list = &(const struct dmi_system_id[]) {
14653                         {
14654                                 .callback = intel_dmi_reverse_brightness,
14655                                 .ident = "NCR Corporation",
14656                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14657                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14658                                 },
14659                         },
14660                         { }  /* terminating entry */
14661                 },
14662                 .hook = quirk_invert_brightness,
14663         },
14664 };
14665
14666 static struct intel_quirk intel_quirks[] = {
14667         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14668         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14669
14670         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14671         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14672
14673         /* 830 needs to leave pipe A & dpll A up */
14674         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14675
14676         /* 830 needs to leave pipe B & dpll B up */
14677         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14678
14679         /* Lenovo U160 cannot use SSC on LVDS */
14680         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14681
14682         /* Sony Vaio Y cannot use SSC on LVDS */
14683         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14684
14685         /* Acer Aspire 5734Z must invert backlight brightness */
14686         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14687
14688         /* Acer/eMachines G725 */
14689         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14690
14691         /* Acer/eMachines e725 */
14692         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14693
14694         /* Acer/Packard Bell NCL20 */
14695         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14696
14697         /* Acer Aspire 4736Z */
14698         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14699
14700         /* Acer Aspire 5336 */
14701         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14702
14703         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14704         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14705
14706         /* Acer C720 Chromebook (Core i3 4005U) */
14707         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14708
14709         /* Apple Macbook 2,1 (Core 2 T7400) */
14710         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14711
14712         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14713         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14714
14715         /* HP Chromebook 14 (Celeron 2955U) */
14716         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14717
14718         /* Dell Chromebook 11 */
14719         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14720 };
14721
14722 static void intel_init_quirks(struct drm_device *dev)
14723 {
14724         struct pci_dev *d = dev->pdev;
14725         int i;
14726
14727         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14728                 struct intel_quirk *q = &intel_quirks[i];
14729
14730                 if (d->device == q->device &&
14731                     (d->subsystem_vendor == q->subsystem_vendor ||
14732                      q->subsystem_vendor == PCI_ANY_ID) &&
14733                     (d->subsystem_device == q->subsystem_device ||
14734                      q->subsystem_device == PCI_ANY_ID))
14735                         q->hook(dev);
14736         }
14737         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14738                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14739                         intel_dmi_quirks[i].hook(dev);
14740         }
14741 }
14742
14743 /* Disable the VGA plane that we never use */
14744 static void i915_disable_vga(struct drm_device *dev)
14745 {
14746         struct drm_i915_private *dev_priv = dev->dev_private;
14747         u8 sr1;
14748         u32 vga_reg = i915_vgacntrl_reg(dev);
14749
14750         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14751         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14752         outb(SR01, VGA_SR_INDEX);
14753         sr1 = inb(VGA_SR_DATA);
14754         outb(sr1 | 1<<5, VGA_SR_DATA);
14755         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14756         udelay(300);
14757
14758         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14759         POSTING_READ(vga_reg);
14760 }
14761
14762 void intel_modeset_init_hw(struct drm_device *dev)
14763 {
14764         intel_update_cdclk(dev);
14765         intel_prepare_ddi(dev);
14766         intel_init_clock_gating(dev);
14767         intel_enable_gt_powersave(dev);
14768 }
14769
14770 void intel_modeset_init(struct drm_device *dev)
14771 {
14772         struct drm_i915_private *dev_priv = dev->dev_private;
14773         int sprite, ret;
14774         enum pipe pipe;
14775         struct intel_crtc *crtc;
14776
14777         drm_mode_config_init(dev);
14778
14779         dev->mode_config.min_width = 0;
14780         dev->mode_config.min_height = 0;
14781
14782         dev->mode_config.preferred_depth = 24;
14783         dev->mode_config.prefer_shadow = 1;
14784
14785         dev->mode_config.allow_fb_modifiers = true;
14786
14787         dev->mode_config.funcs = &intel_mode_funcs;
14788
14789         intel_init_quirks(dev);
14790
14791         intel_init_pm(dev);
14792
14793         if (INTEL_INFO(dev)->num_pipes == 0)
14794                 return;
14795
14796         /*
14797          * There may be no VBT; and if the BIOS enabled SSC we can
14798          * just keep using it to avoid unnecessary flicker.  Whereas if the
14799          * BIOS isn't using it, don't assume it will work even if the VBT
14800          * indicates as much.
14801          */
14802         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14803                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14804                                             DREF_SSC1_ENABLE);
14805
14806                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14807                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14808                                      bios_lvds_use_ssc ? "en" : "dis",
14809                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14810                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14811                 }
14812         }
14813
14814         intel_init_display(dev);
14815         intel_init_audio(dev);
14816
14817         if (IS_GEN2(dev)) {
14818                 dev->mode_config.max_width = 2048;
14819                 dev->mode_config.max_height = 2048;
14820         } else if (IS_GEN3(dev)) {
14821                 dev->mode_config.max_width = 4096;
14822                 dev->mode_config.max_height = 4096;
14823         } else {
14824                 dev->mode_config.max_width = 8192;
14825                 dev->mode_config.max_height = 8192;
14826         }
14827
14828         if (IS_845G(dev) || IS_I865G(dev)) {
14829                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14830                 dev->mode_config.cursor_height = 1023;
14831         } else if (IS_GEN2(dev)) {
14832                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14833                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14834         } else {
14835                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14836                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14837         }
14838
14839         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14840
14841         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14842                       INTEL_INFO(dev)->num_pipes,
14843                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14844
14845         for_each_pipe(dev_priv, pipe) {
14846                 intel_crtc_init(dev, pipe);
14847                 for_each_sprite(dev_priv, pipe, sprite) {
14848                         ret = intel_plane_init(dev, pipe, sprite);
14849                         if (ret)
14850                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14851                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14852                 }
14853         }
14854
14855         intel_update_czclk(dev_priv);
14856         intel_update_cdclk(dev);
14857
14858         intel_shared_dpll_init(dev);
14859
14860         /* Just disable it once at startup */
14861         i915_disable_vga(dev);
14862         intel_setup_outputs(dev);
14863
14864         /* Just in case the BIOS is doing something questionable. */
14865         intel_fbc_disable(dev_priv);
14866
14867         drm_modeset_lock_all(dev);
14868         intel_modeset_setup_hw_state(dev);
14869         drm_modeset_unlock_all(dev);
14870
14871         for_each_intel_crtc(dev, crtc) {
14872                 struct intel_initial_plane_config plane_config = {};
14873
14874                 if (!crtc->active)
14875                         continue;
14876
14877                 /*
14878                  * Note that reserving the BIOS fb up front prevents us
14879                  * from stuffing other stolen allocations like the ring
14880                  * on top.  This prevents some ugliness at boot time, and
14881                  * can even allow for smooth boot transitions if the BIOS
14882                  * fb is large enough for the active pipe configuration.
14883                  */
14884                 dev_priv->display.get_initial_plane_config(crtc,
14885                                                            &plane_config);
14886
14887                 /*
14888                  * If the fb is shared between multiple heads, we'll
14889                  * just get the first one.
14890                  */
14891                 intel_find_initial_plane_obj(crtc, &plane_config);
14892         }
14893 }
14894
14895 static void intel_enable_pipe_a(struct drm_device *dev)
14896 {
14897         struct intel_connector *connector;
14898         struct drm_connector *crt = NULL;
14899         struct intel_load_detect_pipe load_detect_temp;
14900         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14901
14902         /* We can't just switch on the pipe A, we need to set things up with a
14903          * proper mode and output configuration. As a gross hack, enable pipe A
14904          * by enabling the load detect pipe once. */
14905         for_each_intel_connector(dev, connector) {
14906                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14907                         crt = &connector->base;
14908                         break;
14909                 }
14910         }
14911
14912         if (!crt)
14913                 return;
14914
14915         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14916                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14917 }
14918
14919 static bool
14920 intel_check_plane_mapping(struct intel_crtc *crtc)
14921 {
14922         struct drm_device *dev = crtc->base.dev;
14923         struct drm_i915_private *dev_priv = dev->dev_private;
14924         u32 reg, val;
14925
14926         if (INTEL_INFO(dev)->num_pipes == 1)
14927                 return true;
14928
14929         reg = DSPCNTR(!crtc->plane);
14930         val = I915_READ(reg);
14931
14932         if ((val & DISPLAY_PLANE_ENABLE) &&
14933             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14934                 return false;
14935
14936         return true;
14937 }
14938
14939 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14940 {
14941         struct drm_device *dev = crtc->base.dev;
14942         struct intel_encoder *encoder;
14943
14944         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14945                 return true;
14946
14947         return false;
14948 }
14949
14950 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14951 {
14952         struct drm_device *dev = crtc->base.dev;
14953         struct drm_i915_private *dev_priv = dev->dev_private;
14954         u32 reg;
14955
14956         /* Clear any frame start delays used for debugging left by the BIOS */
14957         reg = PIPECONF(crtc->config->cpu_transcoder);
14958         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14959
14960         /* restore vblank interrupts to correct state */
14961         drm_crtc_vblank_reset(&crtc->base);
14962         if (crtc->active) {
14963                 struct intel_plane *plane;
14964
14965                 drm_crtc_vblank_on(&crtc->base);
14966
14967                 /* Disable everything but the primary plane */
14968                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14969                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14970                                 continue;
14971
14972                         plane->disable_plane(&plane->base, &crtc->base);
14973                 }
14974         }
14975
14976         /* We need to sanitize the plane -> pipe mapping first because this will
14977          * disable the crtc (and hence change the state) if it is wrong. Note
14978          * that gen4+ has a fixed plane -> pipe mapping.  */
14979         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14980                 bool plane;
14981
14982                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14983                               crtc->base.base.id);
14984
14985                 /* Pipe has the wrong plane attached and the plane is active.
14986                  * Temporarily change the plane mapping and disable everything
14987                  * ...  */
14988                 plane = crtc->plane;
14989                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14990                 crtc->plane = !plane;
14991                 intel_crtc_disable_noatomic(&crtc->base);
14992                 crtc->plane = plane;
14993         }
14994
14995         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14996             crtc->pipe == PIPE_A && !crtc->active) {
14997                 /* BIOS forgot to enable pipe A, this mostly happens after
14998                  * resume. Force-enable the pipe to fix this, the update_dpms
14999                  * call below we restore the pipe to the right state, but leave
15000                  * the required bits on. */
15001                 intel_enable_pipe_a(dev);
15002         }
15003
15004         /* Adjust the state of the output pipe according to whether we
15005          * have active connectors/encoders. */
15006         if (!intel_crtc_has_encoders(crtc))
15007                 intel_crtc_disable_noatomic(&crtc->base);
15008
15009         if (crtc->active != crtc->base.state->active) {
15010                 struct intel_encoder *encoder;
15011
15012                 /* This can happen either due to bugs in the get_hw_state
15013                  * functions or because of calls to intel_crtc_disable_noatomic,
15014                  * or because the pipe is force-enabled due to the
15015                  * pipe A quirk. */
15016                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15017                               crtc->base.base.id,
15018                               crtc->base.state->enable ? "enabled" : "disabled",
15019                               crtc->active ? "enabled" : "disabled");
15020
15021                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15022                 crtc->base.state->active = crtc->active;
15023                 crtc->base.enabled = crtc->active;
15024
15025                 /* Because we only establish the connector -> encoder ->
15026                  * crtc links if something is active, this means the
15027                  * crtc is now deactivated. Break the links. connector
15028                  * -> encoder links are only establish when things are
15029                  *  actually up, hence no need to break them. */
15030                 WARN_ON(crtc->active);
15031
15032                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15033                         encoder->base.crtc = NULL;
15034         }
15035
15036         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15037                 /*
15038                  * We start out with underrun reporting disabled to avoid races.
15039                  * For correct bookkeeping mark this on active crtcs.
15040                  *
15041                  * Also on gmch platforms we dont have any hardware bits to
15042                  * disable the underrun reporting. Which means we need to start
15043                  * out with underrun reporting disabled also on inactive pipes,
15044                  * since otherwise we'll complain about the garbage we read when
15045                  * e.g. coming up after runtime pm.
15046                  *
15047                  * No protection against concurrent access is required - at
15048                  * worst a fifo underrun happens which also sets this to false.
15049                  */
15050                 crtc->cpu_fifo_underrun_disabled = true;
15051                 crtc->pch_fifo_underrun_disabled = true;
15052         }
15053 }
15054
15055 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15056 {
15057         struct intel_connector *connector;
15058         struct drm_device *dev = encoder->base.dev;
15059         bool active = false;
15060
15061         /* We need to check both for a crtc link (meaning that the
15062          * encoder is active and trying to read from a pipe) and the
15063          * pipe itself being active. */
15064         bool has_active_crtc = encoder->base.crtc &&
15065                 to_intel_crtc(encoder->base.crtc)->active;
15066
15067         for_each_intel_connector(dev, connector) {
15068                 if (connector->base.encoder != &encoder->base)
15069                         continue;
15070
15071                 active = true;
15072                 break;
15073         }
15074
15075         if (active && !has_active_crtc) {
15076                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15077                               encoder->base.base.id,
15078                               encoder->base.name);
15079
15080                 /* Connector is active, but has no active pipe. This is
15081                  * fallout from our resume register restoring. Disable
15082                  * the encoder manually again. */
15083                 if (encoder->base.crtc) {
15084                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15085                                       encoder->base.base.id,
15086                                       encoder->base.name);
15087                         encoder->disable(encoder);
15088                         if (encoder->post_disable)
15089                                 encoder->post_disable(encoder);
15090                 }
15091                 encoder->base.crtc = NULL;
15092
15093                 /* Inconsistent output/port/pipe state happens presumably due to
15094                  * a bug in one of the get_hw_state functions. Or someplace else
15095                  * in our code, like the register restore mess on resume. Clamp
15096                  * things to off as a safer default. */
15097                 for_each_intel_connector(dev, connector) {
15098                         if (connector->encoder != encoder)
15099                                 continue;
15100                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15101                         connector->base.encoder = NULL;
15102                 }
15103         }
15104         /* Enabled encoders without active connectors will be fixed in
15105          * the crtc fixup. */
15106 }
15107
15108 void i915_redisable_vga_power_on(struct drm_device *dev)
15109 {
15110         struct drm_i915_private *dev_priv = dev->dev_private;
15111         u32 vga_reg = i915_vgacntrl_reg(dev);
15112
15113         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15114                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15115                 i915_disable_vga(dev);
15116         }
15117 }
15118
15119 void i915_redisable_vga(struct drm_device *dev)
15120 {
15121         struct drm_i915_private *dev_priv = dev->dev_private;
15122
15123         /* This function can be called both from intel_modeset_setup_hw_state or
15124          * at a very early point in our resume sequence, where the power well
15125          * structures are not yet restored. Since this function is at a very
15126          * paranoid "someone might have enabled VGA while we were not looking"
15127          * level, just check if the power well is enabled instead of trying to
15128          * follow the "don't touch the power well if we don't need it" policy
15129          * the rest of the driver uses. */
15130         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15131                 return;
15132
15133         i915_redisable_vga_power_on(dev);
15134 }
15135
15136 static bool primary_get_hw_state(struct intel_plane *plane)
15137 {
15138         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15139
15140         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15141 }
15142
15143 /* FIXME read out full plane state for all planes */
15144 static void readout_plane_state(struct intel_crtc *crtc)
15145 {
15146         struct drm_plane *primary = crtc->base.primary;
15147         struct intel_plane_state *plane_state =
15148                 to_intel_plane_state(primary->state);
15149
15150         plane_state->visible =
15151                 primary_get_hw_state(to_intel_plane(primary));
15152
15153         if (plane_state->visible)
15154                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15155 }
15156
15157 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15158 {
15159         struct drm_i915_private *dev_priv = dev->dev_private;
15160         enum pipe pipe;
15161         struct intel_crtc *crtc;
15162         struct intel_encoder *encoder;
15163         struct intel_connector *connector;
15164         int i;
15165
15166         for_each_intel_crtc(dev, crtc) {
15167                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15168                 memset(crtc->config, 0, sizeof(*crtc->config));
15169                 crtc->config->base.crtc = &crtc->base;
15170
15171                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15172                                                                  crtc->config);
15173
15174                 crtc->base.state->active = crtc->active;
15175                 crtc->base.enabled = crtc->active;
15176
15177                 readout_plane_state(crtc);
15178
15179                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15180                               crtc->base.base.id,
15181                               crtc->active ? "enabled" : "disabled");
15182         }
15183
15184         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15185                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15186
15187                 pll->on = pll->get_hw_state(dev_priv, pll,
15188                                             &pll->config.hw_state);
15189                 pll->active = 0;
15190                 pll->config.crtc_mask = 0;
15191                 for_each_intel_crtc(dev, crtc) {
15192                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15193                                 pll->active++;
15194                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15195                         }
15196                 }
15197
15198                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15199                               pll->name, pll->config.crtc_mask, pll->on);
15200
15201                 if (pll->config.crtc_mask)
15202                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15203         }
15204
15205         for_each_intel_encoder(dev, encoder) {
15206                 pipe = 0;
15207
15208                 if (encoder->get_hw_state(encoder, &pipe)) {
15209                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15210                         encoder->base.crtc = &crtc->base;
15211                         encoder->get_config(encoder, crtc->config);
15212                 } else {
15213                         encoder->base.crtc = NULL;
15214                 }
15215
15216                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15217                               encoder->base.base.id,
15218                               encoder->base.name,
15219                               encoder->base.crtc ? "enabled" : "disabled",
15220                               pipe_name(pipe));
15221         }
15222
15223         for_each_intel_connector(dev, connector) {
15224                 if (connector->get_hw_state(connector)) {
15225                         connector->base.dpms = DRM_MODE_DPMS_ON;
15226                         connector->base.encoder = &connector->encoder->base;
15227                 } else {
15228                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15229                         connector->base.encoder = NULL;
15230                 }
15231                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15232                               connector->base.base.id,
15233                               connector->base.name,
15234                               connector->base.encoder ? "enabled" : "disabled");
15235         }
15236
15237         for_each_intel_crtc(dev, crtc) {
15238                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15239
15240                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15241                 if (crtc->base.state->active) {
15242                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15243                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15244                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15245
15246                         /*
15247                          * The initial mode needs to be set in order to keep
15248                          * the atomic core happy. It wants a valid mode if the
15249                          * crtc's enabled, so we do the above call.
15250                          *
15251                          * At this point some state updated by the connectors
15252                          * in their ->detect() callback has not run yet, so
15253                          * no recalculation can be done yet.
15254                          *
15255                          * Even if we could do a recalculation and modeset
15256                          * right now it would cause a double modeset if
15257                          * fbdev or userspace chooses a different initial mode.
15258                          *
15259                          * If that happens, someone indicated they wanted a
15260                          * mode change, which means it's safe to do a full
15261                          * recalculation.
15262                          */
15263                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15264
15265                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15266                         update_scanline_offset(crtc);
15267                 }
15268         }
15269 }
15270
15271 /* Scan out the current hw modeset state,
15272  * and sanitizes it to the current state
15273  */
15274 static void
15275 intel_modeset_setup_hw_state(struct drm_device *dev)
15276 {
15277         struct drm_i915_private *dev_priv = dev->dev_private;
15278         enum pipe pipe;
15279         struct intel_crtc *crtc;
15280         struct intel_encoder *encoder;
15281         int i;
15282
15283         intel_modeset_readout_hw_state(dev);
15284
15285         /* HW state is read out, now we need to sanitize this mess. */
15286         for_each_intel_encoder(dev, encoder) {
15287                 intel_sanitize_encoder(encoder);
15288         }
15289
15290         for_each_pipe(dev_priv, pipe) {
15291                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15292                 intel_sanitize_crtc(crtc);
15293                 intel_dump_pipe_config(crtc, crtc->config,
15294                                        "[setup_hw_state]");
15295         }
15296
15297         intel_modeset_update_connector_atomic_state(dev);
15298
15299         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15300                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15301
15302                 if (!pll->on || pll->active)
15303                         continue;
15304
15305                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15306
15307                 pll->disable(dev_priv, pll);
15308                 pll->on = false;
15309         }
15310
15311         if (IS_VALLEYVIEW(dev))
15312                 vlv_wm_get_hw_state(dev);
15313         else if (IS_GEN9(dev))
15314                 skl_wm_get_hw_state(dev);
15315         else if (HAS_PCH_SPLIT(dev))
15316                 ilk_wm_get_hw_state(dev);
15317
15318         for_each_intel_crtc(dev, crtc) {
15319                 unsigned long put_domains;
15320
15321                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15322                 if (WARN_ON(put_domains))
15323                         modeset_put_power_domains(dev_priv, put_domains);
15324         }
15325         intel_display_set_init_power(dev_priv, false);
15326 }
15327
15328 void intel_display_resume(struct drm_device *dev)
15329 {
15330         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15331         struct intel_connector *conn;
15332         struct intel_plane *plane;
15333         struct drm_crtc *crtc;
15334         int ret;
15335
15336         if (!state)
15337                 return;
15338
15339         state->acquire_ctx = dev->mode_config.acquire_ctx;
15340
15341         /* preserve complete old state, including dpll */
15342         intel_atomic_get_shared_dpll_state(state);
15343
15344         for_each_crtc(dev, crtc) {
15345                 struct drm_crtc_state *crtc_state =
15346                         drm_atomic_get_crtc_state(state, crtc);
15347
15348                 ret = PTR_ERR_OR_ZERO(crtc_state);
15349                 if (ret)
15350                         goto err;
15351
15352                 /* force a restore */
15353                 crtc_state->mode_changed = true;
15354         }
15355
15356         for_each_intel_plane(dev, plane) {
15357                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15358                 if (ret)
15359                         goto err;
15360         }
15361
15362         for_each_intel_connector(dev, conn) {
15363                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15364                 if (ret)
15365                         goto err;
15366         }
15367
15368         intel_modeset_setup_hw_state(dev);
15369
15370         i915_redisable_vga(dev);
15371         ret = drm_atomic_commit(state);
15372         if (!ret)
15373                 return;
15374
15375 err:
15376         DRM_ERROR("Restoring old state failed with %i\n", ret);
15377         drm_atomic_state_free(state);
15378 }
15379
15380 void intel_modeset_gem_init(struct drm_device *dev)
15381 {
15382         struct drm_crtc *c;
15383         struct drm_i915_gem_object *obj;
15384         int ret;
15385
15386         mutex_lock(&dev->struct_mutex);
15387         intel_init_gt_powersave(dev);
15388         mutex_unlock(&dev->struct_mutex);
15389
15390         intel_modeset_init_hw(dev);
15391
15392         intel_setup_overlay(dev);
15393
15394         /*
15395          * Make sure any fbs we allocated at startup are properly
15396          * pinned & fenced.  When we do the allocation it's too early
15397          * for this.
15398          */
15399         for_each_crtc(dev, c) {
15400                 obj = intel_fb_obj(c->primary->fb);
15401                 if (obj == NULL)
15402                         continue;
15403
15404                 mutex_lock(&dev->struct_mutex);
15405                 ret = intel_pin_and_fence_fb_obj(c->primary,
15406                                                  c->primary->fb,
15407                                                  c->primary->state,
15408                                                  NULL, NULL);
15409                 mutex_unlock(&dev->struct_mutex);
15410                 if (ret) {
15411                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15412                                   to_intel_crtc(c)->pipe);
15413                         drm_framebuffer_unreference(c->primary->fb);
15414                         c->primary->fb = NULL;
15415                         c->primary->crtc = c->primary->state->crtc = NULL;
15416                         update_state_fb(c->primary);
15417                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15418                 }
15419         }
15420
15421         intel_backlight_register(dev);
15422 }
15423
15424 void intel_connector_unregister(struct intel_connector *intel_connector)
15425 {
15426         struct drm_connector *connector = &intel_connector->base;
15427
15428         intel_panel_destroy_backlight(connector);
15429         drm_connector_unregister(connector);
15430 }
15431
15432 void intel_modeset_cleanup(struct drm_device *dev)
15433 {
15434         struct drm_i915_private *dev_priv = dev->dev_private;
15435         struct drm_connector *connector;
15436
15437         intel_disable_gt_powersave(dev);
15438
15439         intel_backlight_unregister(dev);
15440
15441         /*
15442          * Interrupts and polling as the first thing to avoid creating havoc.
15443          * Too much stuff here (turning of connectors, ...) would
15444          * experience fancy races otherwise.
15445          */
15446         intel_irq_uninstall(dev_priv);
15447
15448         /*
15449          * Due to the hpd irq storm handling the hotplug work can re-arm the
15450          * poll handlers. Hence disable polling after hpd handling is shut down.
15451          */
15452         drm_kms_helper_poll_fini(dev);
15453
15454         intel_unregister_dsm_handler();
15455
15456         intel_fbc_disable(dev_priv);
15457
15458         /* flush any delayed tasks or pending work */
15459         flush_scheduled_work();
15460
15461         /* destroy the backlight and sysfs files before encoders/connectors */
15462         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15463                 struct intel_connector *intel_connector;
15464
15465                 intel_connector = to_intel_connector(connector);
15466                 intel_connector->unregister(intel_connector);
15467         }
15468
15469         drm_mode_config_cleanup(dev);
15470
15471         intel_cleanup_overlay(dev);
15472
15473         mutex_lock(&dev->struct_mutex);
15474         intel_cleanup_gt_powersave(dev);
15475         mutex_unlock(&dev->struct_mutex);
15476 }
15477
15478 /*
15479  * Return which encoder is currently attached for connector.
15480  */
15481 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15482 {
15483         return &intel_attached_encoder(connector)->base;
15484 }
15485
15486 void intel_connector_attach_encoder(struct intel_connector *connector,
15487                                     struct intel_encoder *encoder)
15488 {
15489         connector->encoder = encoder;
15490         drm_mode_connector_attach_encoder(&connector->base,
15491                                           &encoder->base);
15492 }
15493
15494 /*
15495  * set vga decode state - true == enable VGA decode
15496  */
15497 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15498 {
15499         struct drm_i915_private *dev_priv = dev->dev_private;
15500         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15501         u16 gmch_ctrl;
15502
15503         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15504                 DRM_ERROR("failed to read control word\n");
15505                 return -EIO;
15506         }
15507
15508         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15509                 return 0;
15510
15511         if (state)
15512                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15513         else
15514                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15515
15516         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15517                 DRM_ERROR("failed to write control word\n");
15518                 return -EIO;
15519         }
15520
15521         return 0;
15522 }
15523
15524 struct intel_display_error_state {
15525
15526         u32 power_well_driver;
15527
15528         int num_transcoders;
15529
15530         struct intel_cursor_error_state {
15531                 u32 control;
15532                 u32 position;
15533                 u32 base;
15534                 u32 size;
15535         } cursor[I915_MAX_PIPES];
15536
15537         struct intel_pipe_error_state {
15538                 bool power_domain_on;
15539                 u32 source;
15540                 u32 stat;
15541         } pipe[I915_MAX_PIPES];
15542
15543         struct intel_plane_error_state {
15544                 u32 control;
15545                 u32 stride;
15546                 u32 size;
15547                 u32 pos;
15548                 u32 addr;
15549                 u32 surface;
15550                 u32 tile_offset;
15551         } plane[I915_MAX_PIPES];
15552
15553         struct intel_transcoder_error_state {
15554                 bool power_domain_on;
15555                 enum transcoder cpu_transcoder;
15556
15557                 u32 conf;
15558
15559                 u32 htotal;
15560                 u32 hblank;
15561                 u32 hsync;
15562                 u32 vtotal;
15563                 u32 vblank;
15564                 u32 vsync;
15565         } transcoder[4];
15566 };
15567
15568 struct intel_display_error_state *
15569 intel_display_capture_error_state(struct drm_device *dev)
15570 {
15571         struct drm_i915_private *dev_priv = dev->dev_private;
15572         struct intel_display_error_state *error;
15573         int transcoders[] = {
15574                 TRANSCODER_A,
15575                 TRANSCODER_B,
15576                 TRANSCODER_C,
15577                 TRANSCODER_EDP,
15578         };
15579         int i;
15580
15581         if (INTEL_INFO(dev)->num_pipes == 0)
15582                 return NULL;
15583
15584         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15585         if (error == NULL)
15586                 return NULL;
15587
15588         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15589                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15590
15591         for_each_pipe(dev_priv, i) {
15592                 error->pipe[i].power_domain_on =
15593                         __intel_display_power_is_enabled(dev_priv,
15594                                                          POWER_DOMAIN_PIPE(i));
15595                 if (!error->pipe[i].power_domain_on)
15596                         continue;
15597
15598                 error->cursor[i].control = I915_READ(CURCNTR(i));
15599                 error->cursor[i].position = I915_READ(CURPOS(i));
15600                 error->cursor[i].base = I915_READ(CURBASE(i));
15601
15602                 error->plane[i].control = I915_READ(DSPCNTR(i));
15603                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15604                 if (INTEL_INFO(dev)->gen <= 3) {
15605                         error->plane[i].size = I915_READ(DSPSIZE(i));
15606                         error->plane[i].pos = I915_READ(DSPPOS(i));
15607                 }
15608                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15609                         error->plane[i].addr = I915_READ(DSPADDR(i));
15610                 if (INTEL_INFO(dev)->gen >= 4) {
15611                         error->plane[i].surface = I915_READ(DSPSURF(i));
15612                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15613                 }
15614
15615                 error->pipe[i].source = I915_READ(PIPESRC(i));
15616
15617                 if (HAS_GMCH_DISPLAY(dev))
15618                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15619         }
15620
15621         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15622         if (HAS_DDI(dev_priv->dev))
15623                 error->num_transcoders++; /* Account for eDP. */
15624
15625         for (i = 0; i < error->num_transcoders; i++) {
15626                 enum transcoder cpu_transcoder = transcoders[i];
15627
15628                 error->transcoder[i].power_domain_on =
15629                         __intel_display_power_is_enabled(dev_priv,
15630                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15631                 if (!error->transcoder[i].power_domain_on)
15632                         continue;
15633
15634                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15635
15636                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15637                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15638                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15639                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15640                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15641                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15642                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15643         }
15644
15645         return error;
15646 }
15647
15648 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15649
15650 void
15651 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15652                                 struct drm_device *dev,
15653                                 struct intel_display_error_state *error)
15654 {
15655         struct drm_i915_private *dev_priv = dev->dev_private;
15656         int i;
15657
15658         if (!error)
15659                 return;
15660
15661         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15662         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15663                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15664                            error->power_well_driver);
15665         for_each_pipe(dev_priv, i) {
15666                 err_printf(m, "Pipe [%d]:\n", i);
15667                 err_printf(m, "  Power: %s\n",
15668                            error->pipe[i].power_domain_on ? "on" : "off");
15669                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15670                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15671
15672                 err_printf(m, "Plane [%d]:\n", i);
15673                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15674                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15675                 if (INTEL_INFO(dev)->gen <= 3) {
15676                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15677                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15678                 }
15679                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15680                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15681                 if (INTEL_INFO(dev)->gen >= 4) {
15682                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15683                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15684                 }
15685
15686                 err_printf(m, "Cursor [%d]:\n", i);
15687                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15688                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15689                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15690         }
15691
15692         for (i = 0; i < error->num_transcoders; i++) {
15693                 err_printf(m, "CPU transcoder: %c\n",
15694                            transcoder_name(error->transcoder[i].cpu_transcoder));
15695                 err_printf(m, "  Power: %s\n",
15696                            error->transcoder[i].power_domain_on ? "on" : "off");
15697                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15698                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15699                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15700                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15701                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15702                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15703                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15704         }
15705 }
15706
15707 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15708 {
15709         struct intel_crtc *crtc;
15710
15711         for_each_intel_crtc(dev, crtc) {
15712                 struct intel_unpin_work *work;
15713
15714                 spin_lock_irq(&dev->event_lock);
15715
15716                 work = crtc->unpin_work;
15717
15718                 if (work && work->event &&
15719                     work->event->base.file_priv == file) {
15720                         kfree(work->event);
15721                         work->event = NULL;
15722                 }
15723
15724                 spin_unlock_irq(&dev->event_lock);
15725         }
15726 }